1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/delay.h> 16 #include <linux/notifier.h> 17 #include <linux/ip.h> 18 #include <linux/tcp.h> 19 #include <linux/in.h> 20 #include <linux/ethtool.h> 21 #include <linux/topology.h> 22 #include <linux/gfp.h> 23 #include <linux/aer.h> 24 #include <linux/interrupt.h> 25 #include "net_driver.h" 26 #include "efx.h" 27 #include "nic.h" 28 #include "selftest.h" 29 30 #include "workarounds.h" 31 32 /************************************************************************** 33 * 34 * Type name strings 35 * 36 ************************************************************************** 37 */ 38 39 /* Loopback mode names (see LOOPBACK_MODE()) */ 40 const unsigned int ef4_loopback_mode_max = LOOPBACK_MAX; 41 const char *const ef4_loopback_mode_names[] = { 42 [LOOPBACK_NONE] = "NONE", 43 [LOOPBACK_DATA] = "DATAPATH", 44 [LOOPBACK_GMAC] = "GMAC", 45 [LOOPBACK_XGMII] = "XGMII", 46 [LOOPBACK_XGXS] = "XGXS", 47 [LOOPBACK_XAUI] = "XAUI", 48 [LOOPBACK_GMII] = "GMII", 49 [LOOPBACK_SGMII] = "SGMII", 50 [LOOPBACK_XGBR] = "XGBR", 51 [LOOPBACK_XFI] = "XFI", 52 [LOOPBACK_XAUI_FAR] = "XAUI_FAR", 53 [LOOPBACK_GMII_FAR] = "GMII_FAR", 54 [LOOPBACK_SGMII_FAR] = "SGMII_FAR", 55 [LOOPBACK_XFI_FAR] = "XFI_FAR", 56 [LOOPBACK_GPHY] = "GPHY", 57 [LOOPBACK_PHYXS] = "PHYXS", 58 [LOOPBACK_PCS] = "PCS", 59 [LOOPBACK_PMAPMD] = "PMA/PMD", 60 [LOOPBACK_XPORT] = "XPORT", 61 [LOOPBACK_XGMII_WS] = "XGMII_WS", 62 [LOOPBACK_XAUI_WS] = "XAUI_WS", 63 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", 64 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", 65 [LOOPBACK_GMII_WS] = "GMII_WS", 66 [LOOPBACK_XFI_WS] = "XFI_WS", 67 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", 68 [LOOPBACK_PHYXS_WS] = "PHYXS_WS", 69 }; 70 71 const unsigned int ef4_reset_type_max = RESET_TYPE_MAX; 72 const char *const ef4_reset_type_names[] = { 73 [RESET_TYPE_INVISIBLE] = "INVISIBLE", 74 [RESET_TYPE_ALL] = "ALL", 75 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL", 76 [RESET_TYPE_WORLD] = "WORLD", 77 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE", 78 [RESET_TYPE_DATAPATH] = "DATAPATH", 79 [RESET_TYPE_DISABLE] = "DISABLE", 80 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", 81 [RESET_TYPE_INT_ERROR] = "INT_ERROR", 82 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", 83 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR", 84 [RESET_TYPE_TX_SKIP] = "TX_SKIP", 85 }; 86 87 /* Reset workqueue. If any NIC has a hardware failure then a reset will be 88 * queued onto this work queue. This is not a per-nic work queue, because 89 * ef4_reset_work() acquires the rtnl lock, so resets are naturally serialised. 90 */ 91 static struct workqueue_struct *reset_workqueue; 92 93 /* How often and how many times to poll for a reset while waiting for a 94 * BIST that another function started to complete. 95 */ 96 #define BIST_WAIT_DELAY_MS 100 97 #define BIST_WAIT_DELAY_COUNT 100 98 99 /************************************************************************** 100 * 101 * Configurable values 102 * 103 *************************************************************************/ 104 105 /* 106 * Use separate channels for TX and RX events 107 * 108 * Set this to 1 to use separate channels for TX and RX. It allows us 109 * to control interrupt affinity separately for TX and RX. 110 * 111 * This is only used in MSI-X interrupt mode 112 */ 113 bool ef4_separate_tx_channels; 114 module_param(ef4_separate_tx_channels, bool, 0444); 115 MODULE_PARM_DESC(ef4_separate_tx_channels, 116 "Use separate channels for TX and RX"); 117 118 /* This is the weight assigned to each of the (per-channel) virtual 119 * NAPI devices. 120 */ 121 static int napi_weight = 64; 122 123 /* This is the time (in jiffies) between invocations of the hardware 124 * monitor. 125 * On Falcon-based NICs, this will: 126 * - Check the on-board hardware monitor; 127 * - Poll the link state and reconfigure the hardware as necessary. 128 * On Siena-based NICs for power systems with EEH support, this will give EEH a 129 * chance to start. 130 */ 131 static unsigned int ef4_monitor_interval = 1 * HZ; 132 133 /* Initial interrupt moderation settings. They can be modified after 134 * module load with ethtool. 135 * 136 * The default for RX should strike a balance between increasing the 137 * round-trip latency and reducing overhead. 138 */ 139 static unsigned int rx_irq_mod_usec = 60; 140 141 /* Initial interrupt moderation settings. They can be modified after 142 * module load with ethtool. 143 * 144 * This default is chosen to ensure that a 10G link does not go idle 145 * while a TX queue is stopped after it has become full. A queue is 146 * restarted when it drops below half full. The time this takes (assuming 147 * worst case 3 descriptors per packet and 1024 descriptors) is 148 * 512 / 3 * 1.2 = 205 usec. 149 */ 150 static unsigned int tx_irq_mod_usec = 150; 151 152 /* This is the first interrupt mode to try out of: 153 * 0 => MSI-X 154 * 1 => MSI 155 * 2 => legacy 156 */ 157 static unsigned int interrupt_mode; 158 159 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 160 * i.e. the number of CPUs among which we may distribute simultaneous 161 * interrupt handling. 162 * 163 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 164 * The default (0) means to assign an interrupt to each core. 165 */ 166 static unsigned int rss_cpus; 167 module_param(rss_cpus, uint, 0444); 168 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); 169 170 static bool phy_flash_cfg; 171 module_param(phy_flash_cfg, bool, 0644); 172 MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); 173 174 static unsigned irq_adapt_low_thresh = 8000; 175 module_param(irq_adapt_low_thresh, uint, 0644); 176 MODULE_PARM_DESC(irq_adapt_low_thresh, 177 "Threshold score for reducing IRQ moderation"); 178 179 static unsigned irq_adapt_high_thresh = 16000; 180 module_param(irq_adapt_high_thresh, uint, 0644); 181 MODULE_PARM_DESC(irq_adapt_high_thresh, 182 "Threshold score for increasing IRQ moderation"); 183 184 static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 185 NETIF_MSG_LINK | NETIF_MSG_IFDOWN | 186 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | 187 NETIF_MSG_TX_ERR | NETIF_MSG_HW); 188 module_param(debug, uint, 0); 189 MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); 190 191 /************************************************************************** 192 * 193 * Utility functions and prototypes 194 * 195 *************************************************************************/ 196 197 static int ef4_soft_enable_interrupts(struct ef4_nic *efx); 198 static void ef4_soft_disable_interrupts(struct ef4_nic *efx); 199 static void ef4_remove_channel(struct ef4_channel *channel); 200 static void ef4_remove_channels(struct ef4_nic *efx); 201 static const struct ef4_channel_type ef4_default_channel_type; 202 static void ef4_remove_port(struct ef4_nic *efx); 203 static void ef4_init_napi_channel(struct ef4_channel *channel); 204 static void ef4_fini_napi(struct ef4_nic *efx); 205 static void ef4_fini_napi_channel(struct ef4_channel *channel); 206 static void ef4_fini_struct(struct ef4_nic *efx); 207 static void ef4_start_all(struct ef4_nic *efx); 208 static void ef4_stop_all(struct ef4_nic *efx); 209 210 #define EF4_ASSERT_RESET_SERIALISED(efx) \ 211 do { \ 212 if ((efx->state == STATE_READY) || \ 213 (efx->state == STATE_RECOVERY) || \ 214 (efx->state == STATE_DISABLED)) \ 215 ASSERT_RTNL(); \ 216 } while (0) 217 218 static int ef4_check_disabled(struct ef4_nic *efx) 219 { 220 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) { 221 netif_err(efx, drv, efx->net_dev, 222 "device is disabled due to earlier errors\n"); 223 return -EIO; 224 } 225 return 0; 226 } 227 228 /************************************************************************** 229 * 230 * Event queue processing 231 * 232 *************************************************************************/ 233 234 /* Process channel's event queue 235 * 236 * This function is responsible for processing the event queue of a 237 * single channel. The caller must guarantee that this function will 238 * never be concurrently called more than once on the same channel, 239 * though different channels may be being processed concurrently. 240 */ 241 static int ef4_process_channel(struct ef4_channel *channel, int budget) 242 { 243 struct ef4_tx_queue *tx_queue; 244 int spent; 245 246 if (unlikely(!channel->enabled)) 247 return 0; 248 249 ef4_for_each_channel_tx_queue(tx_queue, channel) { 250 tx_queue->pkts_compl = 0; 251 tx_queue->bytes_compl = 0; 252 } 253 254 spent = ef4_nic_process_eventq(channel, budget); 255 if (spent && ef4_channel_has_rx_queue(channel)) { 256 struct ef4_rx_queue *rx_queue = 257 ef4_channel_get_rx_queue(channel); 258 259 ef4_rx_flush_packet(channel); 260 ef4_fast_push_rx_descriptors(rx_queue, true); 261 } 262 263 /* Update BQL */ 264 ef4_for_each_channel_tx_queue(tx_queue, channel) { 265 if (tx_queue->bytes_compl) { 266 netdev_tx_completed_queue(tx_queue->core_txq, 267 tx_queue->pkts_compl, tx_queue->bytes_compl); 268 } 269 } 270 271 return spent; 272 } 273 274 /* NAPI poll handler 275 * 276 * NAPI guarantees serialisation of polls of the same device, which 277 * provides the guarantee required by ef4_process_channel(). 278 */ 279 static void ef4_update_irq_mod(struct ef4_nic *efx, struct ef4_channel *channel) 280 { 281 int step = efx->irq_mod_step_us; 282 283 if (channel->irq_mod_score < irq_adapt_low_thresh) { 284 if (channel->irq_moderation_us > step) { 285 channel->irq_moderation_us -= step; 286 efx->type->push_irq_moderation(channel); 287 } 288 } else if (channel->irq_mod_score > irq_adapt_high_thresh) { 289 if (channel->irq_moderation_us < 290 efx->irq_rx_moderation_us) { 291 channel->irq_moderation_us += step; 292 efx->type->push_irq_moderation(channel); 293 } 294 } 295 296 channel->irq_count = 0; 297 channel->irq_mod_score = 0; 298 } 299 300 static int ef4_poll(struct napi_struct *napi, int budget) 301 { 302 struct ef4_channel *channel = 303 container_of(napi, struct ef4_channel, napi_str); 304 struct ef4_nic *efx = channel->efx; 305 int spent; 306 307 netif_vdbg(efx, intr, efx->net_dev, 308 "channel %d NAPI poll executing on CPU %d\n", 309 channel->channel, raw_smp_processor_id()); 310 311 spent = ef4_process_channel(channel, budget); 312 313 if (spent < budget) { 314 if (ef4_channel_has_rx_queue(channel) && 315 efx->irq_rx_adaptive && 316 unlikely(++channel->irq_count == 1000)) { 317 ef4_update_irq_mod(efx, channel); 318 } 319 320 ef4_filter_rfs_expire(channel); 321 322 /* There is no race here; although napi_disable() will 323 * only wait for napi_complete(), this isn't a problem 324 * since ef4_nic_eventq_read_ack() will have no effect if 325 * interrupts have already been disabled. 326 */ 327 napi_complete_done(napi, spent); 328 ef4_nic_eventq_read_ack(channel); 329 } 330 331 return spent; 332 } 333 334 /* Create event queue 335 * Event queue memory allocations are done only once. If the channel 336 * is reset, the memory buffer will be reused; this guards against 337 * errors during channel reset and also simplifies interrupt handling. 338 */ 339 static int ef4_probe_eventq(struct ef4_channel *channel) 340 { 341 struct ef4_nic *efx = channel->efx; 342 unsigned long entries; 343 344 netif_dbg(efx, probe, efx->net_dev, 345 "chan %d create event queue\n", channel->channel); 346 347 /* Build an event queue with room for one event per tx and rx buffer, 348 * plus some extra for link state events and MCDI completions. */ 349 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 350 EF4_BUG_ON_PARANOID(entries > EF4_MAX_EVQ_SIZE); 351 channel->eventq_mask = max(entries, EF4_MIN_EVQ_SIZE) - 1; 352 353 return ef4_nic_probe_eventq(channel); 354 } 355 356 /* Prepare channel's event queue */ 357 static int ef4_init_eventq(struct ef4_channel *channel) 358 { 359 struct ef4_nic *efx = channel->efx; 360 int rc; 361 362 EF4_WARN_ON_PARANOID(channel->eventq_init); 363 364 netif_dbg(efx, drv, efx->net_dev, 365 "chan %d init event queue\n", channel->channel); 366 367 rc = ef4_nic_init_eventq(channel); 368 if (rc == 0) { 369 efx->type->push_irq_moderation(channel); 370 channel->eventq_read_ptr = 0; 371 channel->eventq_init = true; 372 } 373 return rc; 374 } 375 376 /* Enable event queue processing and NAPI */ 377 void ef4_start_eventq(struct ef4_channel *channel) 378 { 379 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 380 "chan %d start event queue\n", channel->channel); 381 382 /* Make sure the NAPI handler sees the enabled flag set */ 383 channel->enabled = true; 384 smp_wmb(); 385 386 napi_enable(&channel->napi_str); 387 ef4_nic_eventq_read_ack(channel); 388 } 389 390 /* Disable event queue processing and NAPI */ 391 void ef4_stop_eventq(struct ef4_channel *channel) 392 { 393 if (!channel->enabled) 394 return; 395 396 napi_disable(&channel->napi_str); 397 channel->enabled = false; 398 } 399 400 static void ef4_fini_eventq(struct ef4_channel *channel) 401 { 402 if (!channel->eventq_init) 403 return; 404 405 netif_dbg(channel->efx, drv, channel->efx->net_dev, 406 "chan %d fini event queue\n", channel->channel); 407 408 ef4_nic_fini_eventq(channel); 409 channel->eventq_init = false; 410 } 411 412 static void ef4_remove_eventq(struct ef4_channel *channel) 413 { 414 netif_dbg(channel->efx, drv, channel->efx->net_dev, 415 "chan %d remove event queue\n", channel->channel); 416 417 ef4_nic_remove_eventq(channel); 418 } 419 420 /************************************************************************** 421 * 422 * Channel handling 423 * 424 *************************************************************************/ 425 426 /* Allocate and initialise a channel structure. */ 427 static struct ef4_channel * 428 ef4_alloc_channel(struct ef4_nic *efx, int i, struct ef4_channel *old_channel) 429 { 430 struct ef4_channel *channel; 431 struct ef4_rx_queue *rx_queue; 432 struct ef4_tx_queue *tx_queue; 433 int j; 434 435 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 436 if (!channel) 437 return NULL; 438 439 channel->efx = efx; 440 channel->channel = i; 441 channel->type = &ef4_default_channel_type; 442 443 for (j = 0; j < EF4_TXQ_TYPES; j++) { 444 tx_queue = &channel->tx_queue[j]; 445 tx_queue->efx = efx; 446 tx_queue->queue = i * EF4_TXQ_TYPES + j; 447 tx_queue->channel = channel; 448 } 449 450 rx_queue = &channel->rx_queue; 451 rx_queue->efx = efx; 452 timer_setup(&rx_queue->slow_fill, ef4_rx_slow_fill, 0); 453 454 return channel; 455 } 456 457 /* Allocate and initialise a channel structure, copying parameters 458 * (but not resources) from an old channel structure. 459 */ 460 static struct ef4_channel * 461 ef4_copy_channel(const struct ef4_channel *old_channel) 462 { 463 struct ef4_channel *channel; 464 struct ef4_rx_queue *rx_queue; 465 struct ef4_tx_queue *tx_queue; 466 int j; 467 468 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 469 if (!channel) 470 return NULL; 471 472 *channel = *old_channel; 473 474 channel->napi_dev = NULL; 475 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); 476 channel->napi_str.napi_id = 0; 477 channel->napi_str.state = 0; 478 memset(&channel->eventq, 0, sizeof(channel->eventq)); 479 480 for (j = 0; j < EF4_TXQ_TYPES; j++) { 481 tx_queue = &channel->tx_queue[j]; 482 if (tx_queue->channel) 483 tx_queue->channel = channel; 484 tx_queue->buffer = NULL; 485 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 486 } 487 488 rx_queue = &channel->rx_queue; 489 rx_queue->buffer = NULL; 490 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 491 timer_setup(&rx_queue->slow_fill, ef4_rx_slow_fill, 0); 492 493 return channel; 494 } 495 496 static int ef4_probe_channel(struct ef4_channel *channel) 497 { 498 struct ef4_tx_queue *tx_queue; 499 struct ef4_rx_queue *rx_queue; 500 int rc; 501 502 netif_dbg(channel->efx, probe, channel->efx->net_dev, 503 "creating channel %d\n", channel->channel); 504 505 rc = channel->type->pre_probe(channel); 506 if (rc) 507 goto fail; 508 509 rc = ef4_probe_eventq(channel); 510 if (rc) 511 goto fail; 512 513 ef4_for_each_channel_tx_queue(tx_queue, channel) { 514 rc = ef4_probe_tx_queue(tx_queue); 515 if (rc) 516 goto fail; 517 } 518 519 ef4_for_each_channel_rx_queue(rx_queue, channel) { 520 rc = ef4_probe_rx_queue(rx_queue); 521 if (rc) 522 goto fail; 523 } 524 525 return 0; 526 527 fail: 528 ef4_remove_channel(channel); 529 return rc; 530 } 531 532 static void 533 ef4_get_channel_name(struct ef4_channel *channel, char *buf, size_t len) 534 { 535 struct ef4_nic *efx = channel->efx; 536 const char *type; 537 int number; 538 539 number = channel->channel; 540 if (efx->tx_channel_offset == 0) { 541 type = ""; 542 } else if (channel->channel < efx->tx_channel_offset) { 543 type = "-rx"; 544 } else { 545 type = "-tx"; 546 number -= efx->tx_channel_offset; 547 } 548 snprintf(buf, len, "%s%s-%d", efx->name, type, number); 549 } 550 551 static void ef4_set_channel_names(struct ef4_nic *efx) 552 { 553 struct ef4_channel *channel; 554 555 ef4_for_each_channel(channel, efx) 556 channel->type->get_name(channel, 557 efx->msi_context[channel->channel].name, 558 sizeof(efx->msi_context[0].name)); 559 } 560 561 static int ef4_probe_channels(struct ef4_nic *efx) 562 { 563 struct ef4_channel *channel; 564 int rc; 565 566 /* Restart special buffer allocation */ 567 efx->next_buffer_table = 0; 568 569 /* Probe channels in reverse, so that any 'extra' channels 570 * use the start of the buffer table. This allows the traffic 571 * channels to be resized without moving them or wasting the 572 * entries before them. 573 */ 574 ef4_for_each_channel_rev(channel, efx) { 575 rc = ef4_probe_channel(channel); 576 if (rc) { 577 netif_err(efx, probe, efx->net_dev, 578 "failed to create channel %d\n", 579 channel->channel); 580 goto fail; 581 } 582 } 583 ef4_set_channel_names(efx); 584 585 return 0; 586 587 fail: 588 ef4_remove_channels(efx); 589 return rc; 590 } 591 592 /* Channels are shutdown and reinitialised whilst the NIC is running 593 * to propagate configuration changes (mtu, checksum offload), or 594 * to clear hardware error conditions 595 */ 596 static void ef4_start_datapath(struct ef4_nic *efx) 597 { 598 netdev_features_t old_features = efx->net_dev->features; 599 bool old_rx_scatter = efx->rx_scatter; 600 struct ef4_tx_queue *tx_queue; 601 struct ef4_rx_queue *rx_queue; 602 struct ef4_channel *channel; 603 size_t rx_buf_len; 604 605 /* Calculate the rx buffer allocation parameters required to 606 * support the current MTU, including padding for header 607 * alignment and overruns. 608 */ 609 efx->rx_dma_len = (efx->rx_prefix_size + 610 EF4_MAX_FRAME_LEN(efx->net_dev->mtu) + 611 efx->type->rx_buffer_padding); 612 rx_buf_len = (sizeof(struct ef4_rx_page_state) + 613 efx->rx_ip_align + efx->rx_dma_len); 614 if (rx_buf_len <= PAGE_SIZE) { 615 efx->rx_scatter = efx->type->always_rx_scatter; 616 efx->rx_buffer_order = 0; 617 } else if (efx->type->can_rx_scatter) { 618 BUILD_BUG_ON(EF4_RX_USR_BUF_SIZE % L1_CACHE_BYTES); 619 BUILD_BUG_ON(sizeof(struct ef4_rx_page_state) + 620 2 * ALIGN(NET_IP_ALIGN + EF4_RX_USR_BUF_SIZE, 621 EF4_RX_BUF_ALIGNMENT) > 622 PAGE_SIZE); 623 efx->rx_scatter = true; 624 efx->rx_dma_len = EF4_RX_USR_BUF_SIZE; 625 efx->rx_buffer_order = 0; 626 } else { 627 efx->rx_scatter = false; 628 efx->rx_buffer_order = get_order(rx_buf_len); 629 } 630 631 ef4_rx_config_page_split(efx); 632 if (efx->rx_buffer_order) 633 netif_dbg(efx, drv, efx->net_dev, 634 "RX buf len=%u; page order=%u batch=%u\n", 635 efx->rx_dma_len, efx->rx_buffer_order, 636 efx->rx_pages_per_batch); 637 else 638 netif_dbg(efx, drv, efx->net_dev, 639 "RX buf len=%u step=%u bpp=%u; page batch=%u\n", 640 efx->rx_dma_len, efx->rx_page_buf_step, 641 efx->rx_bufs_per_page, efx->rx_pages_per_batch); 642 643 /* Restore previously fixed features in hw_features and remove 644 * features which are fixed now 645 */ 646 efx->net_dev->hw_features |= efx->net_dev->features; 647 efx->net_dev->hw_features &= ~efx->fixed_features; 648 efx->net_dev->features |= efx->fixed_features; 649 if (efx->net_dev->features != old_features) 650 netdev_features_change(efx->net_dev); 651 652 /* RX filters may also have scatter-enabled flags */ 653 if (efx->rx_scatter != old_rx_scatter) 654 efx->type->filter_update_rx_scatter(efx); 655 656 /* We must keep at least one descriptor in a TX ring empty. 657 * We could avoid this when the queue size does not exactly 658 * match the hardware ring size, but it's not that important. 659 * Therefore we stop the queue when one more skb might fill 660 * the ring completely. We wake it when half way back to 661 * empty. 662 */ 663 efx->txq_stop_thresh = efx->txq_entries - ef4_tx_max_skb_descs(efx); 664 efx->txq_wake_thresh = efx->txq_stop_thresh / 2; 665 666 /* Initialise the channels */ 667 ef4_for_each_channel(channel, efx) { 668 ef4_for_each_channel_tx_queue(tx_queue, channel) { 669 ef4_init_tx_queue(tx_queue); 670 atomic_inc(&efx->active_queues); 671 } 672 673 ef4_for_each_channel_rx_queue(rx_queue, channel) { 674 ef4_init_rx_queue(rx_queue); 675 atomic_inc(&efx->active_queues); 676 ef4_stop_eventq(channel); 677 ef4_fast_push_rx_descriptors(rx_queue, false); 678 ef4_start_eventq(channel); 679 } 680 681 WARN_ON(channel->rx_pkt_n_frags); 682 } 683 684 if (netif_device_present(efx->net_dev)) 685 netif_tx_wake_all_queues(efx->net_dev); 686 } 687 688 static void ef4_stop_datapath(struct ef4_nic *efx) 689 { 690 struct ef4_channel *channel; 691 struct ef4_tx_queue *tx_queue; 692 struct ef4_rx_queue *rx_queue; 693 int rc; 694 695 EF4_ASSERT_RESET_SERIALISED(efx); 696 BUG_ON(efx->port_enabled); 697 698 /* Stop RX refill */ 699 ef4_for_each_channel(channel, efx) { 700 ef4_for_each_channel_rx_queue(rx_queue, channel) 701 rx_queue->refill_enabled = false; 702 } 703 704 ef4_for_each_channel(channel, efx) { 705 /* RX packet processing is pipelined, so wait for the 706 * NAPI handler to complete. At least event queue 0 707 * might be kept active by non-data events, so don't 708 * use napi_synchronize() but actually disable NAPI 709 * temporarily. 710 */ 711 if (ef4_channel_has_rx_queue(channel)) { 712 ef4_stop_eventq(channel); 713 ef4_start_eventq(channel); 714 } 715 } 716 717 rc = efx->type->fini_dmaq(efx); 718 if (rc && EF4_WORKAROUND_7803(efx)) { 719 /* Schedule a reset to recover from the flush failure. The 720 * descriptor caches reference memory we're about to free, 721 * but falcon_reconfigure_mac_wrapper() won't reconnect 722 * the MACs because of the pending reset. 723 */ 724 netif_err(efx, drv, efx->net_dev, 725 "Resetting to recover from flush failure\n"); 726 ef4_schedule_reset(efx, RESET_TYPE_ALL); 727 } else if (rc) { 728 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 729 } else { 730 netif_dbg(efx, drv, efx->net_dev, 731 "successfully flushed all queues\n"); 732 } 733 734 ef4_for_each_channel(channel, efx) { 735 ef4_for_each_channel_rx_queue(rx_queue, channel) 736 ef4_fini_rx_queue(rx_queue); 737 ef4_for_each_possible_channel_tx_queue(tx_queue, channel) 738 ef4_fini_tx_queue(tx_queue); 739 } 740 } 741 742 static void ef4_remove_channel(struct ef4_channel *channel) 743 { 744 struct ef4_tx_queue *tx_queue; 745 struct ef4_rx_queue *rx_queue; 746 747 netif_dbg(channel->efx, drv, channel->efx->net_dev, 748 "destroy chan %d\n", channel->channel); 749 750 ef4_for_each_channel_rx_queue(rx_queue, channel) 751 ef4_remove_rx_queue(rx_queue); 752 ef4_for_each_possible_channel_tx_queue(tx_queue, channel) 753 ef4_remove_tx_queue(tx_queue); 754 ef4_remove_eventq(channel); 755 channel->type->post_remove(channel); 756 } 757 758 static void ef4_remove_channels(struct ef4_nic *efx) 759 { 760 struct ef4_channel *channel; 761 762 ef4_for_each_channel(channel, efx) 763 ef4_remove_channel(channel); 764 } 765 766 int 767 ef4_realloc_channels(struct ef4_nic *efx, u32 rxq_entries, u32 txq_entries) 768 { 769 struct ef4_channel *other_channel[EF4_MAX_CHANNELS], *channel; 770 u32 old_rxq_entries, old_txq_entries; 771 unsigned i, next_buffer_table = 0; 772 int rc, rc2; 773 774 rc = ef4_check_disabled(efx); 775 if (rc) 776 return rc; 777 778 /* Not all channels should be reallocated. We must avoid 779 * reallocating their buffer table entries. 780 */ 781 ef4_for_each_channel(channel, efx) { 782 struct ef4_rx_queue *rx_queue; 783 struct ef4_tx_queue *tx_queue; 784 785 if (channel->type->copy) 786 continue; 787 next_buffer_table = max(next_buffer_table, 788 channel->eventq.index + 789 channel->eventq.entries); 790 ef4_for_each_channel_rx_queue(rx_queue, channel) 791 next_buffer_table = max(next_buffer_table, 792 rx_queue->rxd.index + 793 rx_queue->rxd.entries); 794 ef4_for_each_channel_tx_queue(tx_queue, channel) 795 next_buffer_table = max(next_buffer_table, 796 tx_queue->txd.index + 797 tx_queue->txd.entries); 798 } 799 800 ef4_device_detach_sync(efx); 801 ef4_stop_all(efx); 802 ef4_soft_disable_interrupts(efx); 803 804 /* Clone channels (where possible) */ 805 memset(other_channel, 0, sizeof(other_channel)); 806 for (i = 0; i < efx->n_channels; i++) { 807 channel = efx->channel[i]; 808 if (channel->type->copy) 809 channel = channel->type->copy(channel); 810 if (!channel) { 811 rc = -ENOMEM; 812 goto out; 813 } 814 other_channel[i] = channel; 815 } 816 817 /* Swap entry counts and channel pointers */ 818 old_rxq_entries = efx->rxq_entries; 819 old_txq_entries = efx->txq_entries; 820 efx->rxq_entries = rxq_entries; 821 efx->txq_entries = txq_entries; 822 for (i = 0; i < efx->n_channels; i++) { 823 channel = efx->channel[i]; 824 efx->channel[i] = other_channel[i]; 825 other_channel[i] = channel; 826 } 827 828 /* Restart buffer table allocation */ 829 efx->next_buffer_table = next_buffer_table; 830 831 for (i = 0; i < efx->n_channels; i++) { 832 channel = efx->channel[i]; 833 if (!channel->type->copy) 834 continue; 835 rc = ef4_probe_channel(channel); 836 if (rc) 837 goto rollback; 838 ef4_init_napi_channel(efx->channel[i]); 839 } 840 841 out: 842 /* Destroy unused channel structures */ 843 for (i = 0; i < efx->n_channels; i++) { 844 channel = other_channel[i]; 845 if (channel && channel->type->copy) { 846 ef4_fini_napi_channel(channel); 847 ef4_remove_channel(channel); 848 kfree(channel); 849 } 850 } 851 852 rc2 = ef4_soft_enable_interrupts(efx); 853 if (rc2) { 854 rc = rc ? rc : rc2; 855 netif_err(efx, drv, efx->net_dev, 856 "unable to restart interrupts on channel reallocation\n"); 857 ef4_schedule_reset(efx, RESET_TYPE_DISABLE); 858 } else { 859 ef4_start_all(efx); 860 netif_device_attach(efx->net_dev); 861 } 862 return rc; 863 864 rollback: 865 /* Swap back */ 866 efx->rxq_entries = old_rxq_entries; 867 efx->txq_entries = old_txq_entries; 868 for (i = 0; i < efx->n_channels; i++) { 869 channel = efx->channel[i]; 870 efx->channel[i] = other_channel[i]; 871 other_channel[i] = channel; 872 } 873 goto out; 874 } 875 876 void ef4_schedule_slow_fill(struct ef4_rx_queue *rx_queue) 877 { 878 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); 879 } 880 881 static const struct ef4_channel_type ef4_default_channel_type = { 882 .pre_probe = ef4_channel_dummy_op_int, 883 .post_remove = ef4_channel_dummy_op_void, 884 .get_name = ef4_get_channel_name, 885 .copy = ef4_copy_channel, 886 .keep_eventq = false, 887 }; 888 889 int ef4_channel_dummy_op_int(struct ef4_channel *channel) 890 { 891 return 0; 892 } 893 894 void ef4_channel_dummy_op_void(struct ef4_channel *channel) 895 { 896 } 897 898 /************************************************************************** 899 * 900 * Port handling 901 * 902 **************************************************************************/ 903 904 /* This ensures that the kernel is kept informed (via 905 * netif_carrier_on/off) of the link status, and also maintains the 906 * link status's stop on the port's TX queue. 907 */ 908 void ef4_link_status_changed(struct ef4_nic *efx) 909 { 910 struct ef4_link_state *link_state = &efx->link_state; 911 912 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure 913 * that no events are triggered between unregister_netdev() and the 914 * driver unloading. A more general condition is that NETDEV_CHANGE 915 * can only be generated between NETDEV_UP and NETDEV_DOWN */ 916 if (!netif_running(efx->net_dev)) 917 return; 918 919 if (link_state->up != netif_carrier_ok(efx->net_dev)) { 920 efx->n_link_state_changes++; 921 922 if (link_state->up) 923 netif_carrier_on(efx->net_dev); 924 else 925 netif_carrier_off(efx->net_dev); 926 } 927 928 /* Status message for kernel log */ 929 if (link_state->up) 930 netif_info(efx, link, efx->net_dev, 931 "link up at %uMbps %s-duplex (MTU %d)\n", 932 link_state->speed, link_state->fd ? "full" : "half", 933 efx->net_dev->mtu); 934 else 935 netif_info(efx, link, efx->net_dev, "link down\n"); 936 } 937 938 void ef4_link_set_advertising(struct ef4_nic *efx, u32 advertising) 939 { 940 efx->link_advertising = advertising; 941 if (advertising) { 942 if (advertising & ADVERTISED_Pause) 943 efx->wanted_fc |= (EF4_FC_TX | EF4_FC_RX); 944 else 945 efx->wanted_fc &= ~(EF4_FC_TX | EF4_FC_RX); 946 if (advertising & ADVERTISED_Asym_Pause) 947 efx->wanted_fc ^= EF4_FC_TX; 948 } 949 } 950 951 void ef4_link_set_wanted_fc(struct ef4_nic *efx, u8 wanted_fc) 952 { 953 efx->wanted_fc = wanted_fc; 954 if (efx->link_advertising) { 955 if (wanted_fc & EF4_FC_RX) 956 efx->link_advertising |= (ADVERTISED_Pause | 957 ADVERTISED_Asym_Pause); 958 else 959 efx->link_advertising &= ~(ADVERTISED_Pause | 960 ADVERTISED_Asym_Pause); 961 if (wanted_fc & EF4_FC_TX) 962 efx->link_advertising ^= ADVERTISED_Asym_Pause; 963 } 964 } 965 966 static void ef4_fini_port(struct ef4_nic *efx); 967 968 /* We assume that efx->type->reconfigure_mac will always try to sync RX 969 * filters and therefore needs to read-lock the filter table against freeing 970 */ 971 void ef4_mac_reconfigure(struct ef4_nic *efx) 972 { 973 down_read(&efx->filter_sem); 974 efx->type->reconfigure_mac(efx); 975 up_read(&efx->filter_sem); 976 } 977 978 /* Push loopback/power/transmit disable settings to the PHY, and reconfigure 979 * the MAC appropriately. All other PHY configuration changes are pushed 980 * through phy_op->set_link_ksettings(), and pushed asynchronously to the MAC 981 * through ef4_monitor(). 982 * 983 * Callers must hold the mac_lock 984 */ 985 int __ef4_reconfigure_port(struct ef4_nic *efx) 986 { 987 enum ef4_phy_mode phy_mode; 988 int rc; 989 990 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 991 992 /* Disable PHY transmit in mac level loopbacks */ 993 phy_mode = efx->phy_mode; 994 if (LOOPBACK_INTERNAL(efx)) 995 efx->phy_mode |= PHY_MODE_TX_DISABLED; 996 else 997 efx->phy_mode &= ~PHY_MODE_TX_DISABLED; 998 999 rc = efx->type->reconfigure_port(efx); 1000 1001 if (rc) 1002 efx->phy_mode = phy_mode; 1003 1004 return rc; 1005 } 1006 1007 /* Reinitialise the MAC to pick up new PHY settings, even if the port is 1008 * disabled. */ 1009 int ef4_reconfigure_port(struct ef4_nic *efx) 1010 { 1011 int rc; 1012 1013 EF4_ASSERT_RESET_SERIALISED(efx); 1014 1015 mutex_lock(&efx->mac_lock); 1016 rc = __ef4_reconfigure_port(efx); 1017 mutex_unlock(&efx->mac_lock); 1018 1019 return rc; 1020 } 1021 1022 /* Asynchronous work item for changing MAC promiscuity and multicast 1023 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current 1024 * MAC directly. */ 1025 static void ef4_mac_work(struct work_struct *data) 1026 { 1027 struct ef4_nic *efx = container_of(data, struct ef4_nic, mac_work); 1028 1029 mutex_lock(&efx->mac_lock); 1030 if (efx->port_enabled) 1031 ef4_mac_reconfigure(efx); 1032 mutex_unlock(&efx->mac_lock); 1033 } 1034 1035 static int ef4_probe_port(struct ef4_nic *efx) 1036 { 1037 int rc; 1038 1039 netif_dbg(efx, probe, efx->net_dev, "create port\n"); 1040 1041 if (phy_flash_cfg) 1042 efx->phy_mode = PHY_MODE_SPECIAL; 1043 1044 /* Connect up MAC/PHY operations table */ 1045 rc = efx->type->probe_port(efx); 1046 if (rc) 1047 return rc; 1048 1049 /* Initialise MAC address to permanent address */ 1050 ether_addr_copy(efx->net_dev->dev_addr, efx->net_dev->perm_addr); 1051 1052 return 0; 1053 } 1054 1055 static int ef4_init_port(struct ef4_nic *efx) 1056 { 1057 int rc; 1058 1059 netif_dbg(efx, drv, efx->net_dev, "init port\n"); 1060 1061 mutex_lock(&efx->mac_lock); 1062 1063 rc = efx->phy_op->init(efx); 1064 if (rc) 1065 goto fail1; 1066 1067 efx->port_initialized = true; 1068 1069 /* Reconfigure the MAC before creating dma queues (required for 1070 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ 1071 ef4_mac_reconfigure(efx); 1072 1073 /* Ensure the PHY advertises the correct flow control settings */ 1074 rc = efx->phy_op->reconfigure(efx); 1075 if (rc && rc != -EPERM) 1076 goto fail2; 1077 1078 mutex_unlock(&efx->mac_lock); 1079 return 0; 1080 1081 fail2: 1082 efx->phy_op->fini(efx); 1083 fail1: 1084 mutex_unlock(&efx->mac_lock); 1085 return rc; 1086 } 1087 1088 static void ef4_start_port(struct ef4_nic *efx) 1089 { 1090 netif_dbg(efx, ifup, efx->net_dev, "start port\n"); 1091 BUG_ON(efx->port_enabled); 1092 1093 mutex_lock(&efx->mac_lock); 1094 efx->port_enabled = true; 1095 1096 /* Ensure MAC ingress/egress is enabled */ 1097 ef4_mac_reconfigure(efx); 1098 1099 mutex_unlock(&efx->mac_lock); 1100 } 1101 1102 /* Cancel work for MAC reconfiguration, periodic hardware monitoring 1103 * and the async self-test, wait for them to finish and prevent them 1104 * being scheduled again. This doesn't cover online resets, which 1105 * should only be cancelled when removing the device. 1106 */ 1107 static void ef4_stop_port(struct ef4_nic *efx) 1108 { 1109 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); 1110 1111 EF4_ASSERT_RESET_SERIALISED(efx); 1112 1113 mutex_lock(&efx->mac_lock); 1114 efx->port_enabled = false; 1115 mutex_unlock(&efx->mac_lock); 1116 1117 /* Serialise against ef4_set_multicast_list() */ 1118 netif_addr_lock_bh(efx->net_dev); 1119 netif_addr_unlock_bh(efx->net_dev); 1120 1121 cancel_delayed_work_sync(&efx->monitor_work); 1122 ef4_selftest_async_cancel(efx); 1123 cancel_work_sync(&efx->mac_work); 1124 } 1125 1126 static void ef4_fini_port(struct ef4_nic *efx) 1127 { 1128 netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); 1129 1130 if (!efx->port_initialized) 1131 return; 1132 1133 efx->phy_op->fini(efx); 1134 efx->port_initialized = false; 1135 1136 efx->link_state.up = false; 1137 ef4_link_status_changed(efx); 1138 } 1139 1140 static void ef4_remove_port(struct ef4_nic *efx) 1141 { 1142 netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); 1143 1144 efx->type->remove_port(efx); 1145 } 1146 1147 /************************************************************************** 1148 * 1149 * NIC handling 1150 * 1151 **************************************************************************/ 1152 1153 static LIST_HEAD(ef4_primary_list); 1154 static LIST_HEAD(ef4_unassociated_list); 1155 1156 static bool ef4_same_controller(struct ef4_nic *left, struct ef4_nic *right) 1157 { 1158 return left->type == right->type && 1159 left->vpd_sn && right->vpd_sn && 1160 !strcmp(left->vpd_sn, right->vpd_sn); 1161 } 1162 1163 static void ef4_associate(struct ef4_nic *efx) 1164 { 1165 struct ef4_nic *other, *next; 1166 1167 if (efx->primary == efx) { 1168 /* Adding primary function; look for secondaries */ 1169 1170 netif_dbg(efx, probe, efx->net_dev, "adding to primary list\n"); 1171 list_add_tail(&efx->node, &ef4_primary_list); 1172 1173 list_for_each_entry_safe(other, next, &ef4_unassociated_list, 1174 node) { 1175 if (ef4_same_controller(efx, other)) { 1176 list_del(&other->node); 1177 netif_dbg(other, probe, other->net_dev, 1178 "moving to secondary list of %s %s\n", 1179 pci_name(efx->pci_dev), 1180 efx->net_dev->name); 1181 list_add_tail(&other->node, 1182 &efx->secondary_list); 1183 other->primary = efx; 1184 } 1185 } 1186 } else { 1187 /* Adding secondary function; look for primary */ 1188 1189 list_for_each_entry(other, &ef4_primary_list, node) { 1190 if (ef4_same_controller(efx, other)) { 1191 netif_dbg(efx, probe, efx->net_dev, 1192 "adding to secondary list of %s %s\n", 1193 pci_name(other->pci_dev), 1194 other->net_dev->name); 1195 list_add_tail(&efx->node, 1196 &other->secondary_list); 1197 efx->primary = other; 1198 return; 1199 } 1200 } 1201 1202 netif_dbg(efx, probe, efx->net_dev, 1203 "adding to unassociated list\n"); 1204 list_add_tail(&efx->node, &ef4_unassociated_list); 1205 } 1206 } 1207 1208 static void ef4_dissociate(struct ef4_nic *efx) 1209 { 1210 struct ef4_nic *other, *next; 1211 1212 list_del(&efx->node); 1213 efx->primary = NULL; 1214 1215 list_for_each_entry_safe(other, next, &efx->secondary_list, node) { 1216 list_del(&other->node); 1217 netif_dbg(other, probe, other->net_dev, 1218 "moving to unassociated list\n"); 1219 list_add_tail(&other->node, &ef4_unassociated_list); 1220 other->primary = NULL; 1221 } 1222 } 1223 1224 /* This configures the PCI device to enable I/O and DMA. */ 1225 static int ef4_init_io(struct ef4_nic *efx) 1226 { 1227 struct pci_dev *pci_dev = efx->pci_dev; 1228 dma_addr_t dma_mask = efx->type->max_dma_mask; 1229 unsigned int mem_map_size = efx->type->mem_map_size(efx); 1230 int rc, bar; 1231 1232 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); 1233 1234 bar = efx->type->mem_bar; 1235 1236 rc = pci_enable_device(pci_dev); 1237 if (rc) { 1238 netif_err(efx, probe, efx->net_dev, 1239 "failed to enable PCI device\n"); 1240 goto fail1; 1241 } 1242 1243 pci_set_master(pci_dev); 1244 1245 /* Set the PCI DMA mask. Try all possibilities from our genuine mask 1246 * down to 32 bits, because some architectures will allow 40 bit 1247 * masks event though they reject 46 bit masks. 1248 */ 1249 while (dma_mask > 0x7fffffffUL) { 1250 rc = dma_set_mask_and_coherent(&pci_dev->dev, dma_mask); 1251 if (rc == 0) 1252 break; 1253 dma_mask >>= 1; 1254 } 1255 if (rc) { 1256 netif_err(efx, probe, efx->net_dev, 1257 "could not find a suitable DMA mask\n"); 1258 goto fail2; 1259 } 1260 netif_dbg(efx, probe, efx->net_dev, 1261 "using DMA mask %llx\n", (unsigned long long) dma_mask); 1262 1263 efx->membase_phys = pci_resource_start(efx->pci_dev, bar); 1264 rc = pci_request_region(pci_dev, bar, "sfc"); 1265 if (rc) { 1266 netif_err(efx, probe, efx->net_dev, 1267 "request for memory BAR failed\n"); 1268 rc = -EIO; 1269 goto fail3; 1270 } 1271 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); 1272 if (!efx->membase) { 1273 netif_err(efx, probe, efx->net_dev, 1274 "could not map memory BAR at %llx+%x\n", 1275 (unsigned long long)efx->membase_phys, mem_map_size); 1276 rc = -ENOMEM; 1277 goto fail4; 1278 } 1279 netif_dbg(efx, probe, efx->net_dev, 1280 "memory BAR at %llx+%x (virtual %p)\n", 1281 (unsigned long long)efx->membase_phys, mem_map_size, 1282 efx->membase); 1283 1284 return 0; 1285 1286 fail4: 1287 pci_release_region(efx->pci_dev, bar); 1288 fail3: 1289 efx->membase_phys = 0; 1290 fail2: 1291 pci_disable_device(efx->pci_dev); 1292 fail1: 1293 return rc; 1294 } 1295 1296 static void ef4_fini_io(struct ef4_nic *efx) 1297 { 1298 int bar; 1299 1300 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); 1301 1302 if (efx->membase) { 1303 iounmap(efx->membase); 1304 efx->membase = NULL; 1305 } 1306 1307 if (efx->membase_phys) { 1308 bar = efx->type->mem_bar; 1309 pci_release_region(efx->pci_dev, bar); 1310 efx->membase_phys = 0; 1311 } 1312 1313 /* Don't disable bus-mastering if VFs are assigned */ 1314 if (!pci_vfs_assigned(efx->pci_dev)) 1315 pci_disable_device(efx->pci_dev); 1316 } 1317 1318 void ef4_set_default_rx_indir_table(struct ef4_nic *efx) 1319 { 1320 size_t i; 1321 1322 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) 1323 efx->rx_indir_table[i] = 1324 ethtool_rxfh_indir_default(i, efx->rss_spread); 1325 } 1326 1327 static unsigned int ef4_wanted_parallelism(struct ef4_nic *efx) 1328 { 1329 cpumask_var_t thread_mask; 1330 unsigned int count; 1331 int cpu; 1332 1333 if (rss_cpus) { 1334 count = rss_cpus; 1335 } else { 1336 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { 1337 netif_warn(efx, probe, efx->net_dev, 1338 "RSS disabled due to allocation failure\n"); 1339 return 1; 1340 } 1341 1342 count = 0; 1343 for_each_online_cpu(cpu) { 1344 if (!cpumask_test_cpu(cpu, thread_mask)) { 1345 ++count; 1346 cpumask_or(thread_mask, thread_mask, 1347 topology_sibling_cpumask(cpu)); 1348 } 1349 } 1350 1351 free_cpumask_var(thread_mask); 1352 } 1353 1354 if (count > EF4_MAX_RX_QUEUES) { 1355 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, 1356 "Reducing number of rx queues from %u to %u.\n", 1357 count, EF4_MAX_RX_QUEUES); 1358 count = EF4_MAX_RX_QUEUES; 1359 } 1360 1361 return count; 1362 } 1363 1364 /* Probe the number and type of interrupts we are able to obtain, and 1365 * the resulting numbers of channels and RX queues. 1366 */ 1367 static int ef4_probe_interrupts(struct ef4_nic *efx) 1368 { 1369 unsigned int extra_channels = 0; 1370 unsigned int i, j; 1371 int rc; 1372 1373 for (i = 0; i < EF4_MAX_EXTRA_CHANNELS; i++) 1374 if (efx->extra_channel_type[i]) 1375 ++extra_channels; 1376 1377 if (efx->interrupt_mode == EF4_INT_MODE_MSIX) { 1378 struct msix_entry xentries[EF4_MAX_CHANNELS]; 1379 unsigned int n_channels; 1380 1381 n_channels = ef4_wanted_parallelism(efx); 1382 if (ef4_separate_tx_channels) 1383 n_channels *= 2; 1384 n_channels += extra_channels; 1385 n_channels = min(n_channels, efx->max_channels); 1386 1387 for (i = 0; i < n_channels; i++) 1388 xentries[i].entry = i; 1389 rc = pci_enable_msix_range(efx->pci_dev, 1390 xentries, 1, n_channels); 1391 if (rc < 0) { 1392 /* Fall back to single channel MSI */ 1393 efx->interrupt_mode = EF4_INT_MODE_MSI; 1394 netif_err(efx, drv, efx->net_dev, 1395 "could not enable MSI-X\n"); 1396 } else if (rc < n_channels) { 1397 netif_err(efx, drv, efx->net_dev, 1398 "WARNING: Insufficient MSI-X vectors" 1399 " available (%d < %u).\n", rc, n_channels); 1400 netif_err(efx, drv, efx->net_dev, 1401 "WARNING: Performance may be reduced.\n"); 1402 n_channels = rc; 1403 } 1404 1405 if (rc > 0) { 1406 efx->n_channels = n_channels; 1407 if (n_channels > extra_channels) 1408 n_channels -= extra_channels; 1409 if (ef4_separate_tx_channels) { 1410 efx->n_tx_channels = min(max(n_channels / 2, 1411 1U), 1412 efx->max_tx_channels); 1413 efx->n_rx_channels = max(n_channels - 1414 efx->n_tx_channels, 1415 1U); 1416 } else { 1417 efx->n_tx_channels = min(n_channels, 1418 efx->max_tx_channels); 1419 efx->n_rx_channels = n_channels; 1420 } 1421 for (i = 0; i < efx->n_channels; i++) 1422 ef4_get_channel(efx, i)->irq = 1423 xentries[i].vector; 1424 } 1425 } 1426 1427 /* Try single interrupt MSI */ 1428 if (efx->interrupt_mode == EF4_INT_MODE_MSI) { 1429 efx->n_channels = 1; 1430 efx->n_rx_channels = 1; 1431 efx->n_tx_channels = 1; 1432 rc = pci_enable_msi(efx->pci_dev); 1433 if (rc == 0) { 1434 ef4_get_channel(efx, 0)->irq = efx->pci_dev->irq; 1435 } else { 1436 netif_err(efx, drv, efx->net_dev, 1437 "could not enable MSI\n"); 1438 efx->interrupt_mode = EF4_INT_MODE_LEGACY; 1439 } 1440 } 1441 1442 /* Assume legacy interrupts */ 1443 if (efx->interrupt_mode == EF4_INT_MODE_LEGACY) { 1444 efx->n_channels = 1 + (ef4_separate_tx_channels ? 1 : 0); 1445 efx->n_rx_channels = 1; 1446 efx->n_tx_channels = 1; 1447 efx->legacy_irq = efx->pci_dev->irq; 1448 } 1449 1450 /* Assign extra channels if possible */ 1451 j = efx->n_channels; 1452 for (i = 0; i < EF4_MAX_EXTRA_CHANNELS; i++) { 1453 if (!efx->extra_channel_type[i]) 1454 continue; 1455 if (efx->interrupt_mode != EF4_INT_MODE_MSIX || 1456 efx->n_channels <= extra_channels) { 1457 efx->extra_channel_type[i]->handle_no_channel(efx); 1458 } else { 1459 --j; 1460 ef4_get_channel(efx, j)->type = 1461 efx->extra_channel_type[i]; 1462 } 1463 } 1464 1465 efx->rss_spread = efx->n_rx_channels; 1466 1467 return 0; 1468 } 1469 1470 static int ef4_soft_enable_interrupts(struct ef4_nic *efx) 1471 { 1472 struct ef4_channel *channel, *end_channel; 1473 int rc; 1474 1475 BUG_ON(efx->state == STATE_DISABLED); 1476 1477 efx->irq_soft_enabled = true; 1478 smp_wmb(); 1479 1480 ef4_for_each_channel(channel, efx) { 1481 if (!channel->type->keep_eventq) { 1482 rc = ef4_init_eventq(channel); 1483 if (rc) 1484 goto fail; 1485 } 1486 ef4_start_eventq(channel); 1487 } 1488 1489 return 0; 1490 fail: 1491 end_channel = channel; 1492 ef4_for_each_channel(channel, efx) { 1493 if (channel == end_channel) 1494 break; 1495 ef4_stop_eventq(channel); 1496 if (!channel->type->keep_eventq) 1497 ef4_fini_eventq(channel); 1498 } 1499 1500 return rc; 1501 } 1502 1503 static void ef4_soft_disable_interrupts(struct ef4_nic *efx) 1504 { 1505 struct ef4_channel *channel; 1506 1507 if (efx->state == STATE_DISABLED) 1508 return; 1509 1510 efx->irq_soft_enabled = false; 1511 smp_wmb(); 1512 1513 if (efx->legacy_irq) 1514 synchronize_irq(efx->legacy_irq); 1515 1516 ef4_for_each_channel(channel, efx) { 1517 if (channel->irq) 1518 synchronize_irq(channel->irq); 1519 1520 ef4_stop_eventq(channel); 1521 if (!channel->type->keep_eventq) 1522 ef4_fini_eventq(channel); 1523 } 1524 } 1525 1526 static int ef4_enable_interrupts(struct ef4_nic *efx) 1527 { 1528 struct ef4_channel *channel, *end_channel; 1529 int rc; 1530 1531 BUG_ON(efx->state == STATE_DISABLED); 1532 1533 if (efx->eeh_disabled_legacy_irq) { 1534 enable_irq(efx->legacy_irq); 1535 efx->eeh_disabled_legacy_irq = false; 1536 } 1537 1538 efx->type->irq_enable_master(efx); 1539 1540 ef4_for_each_channel(channel, efx) { 1541 if (channel->type->keep_eventq) { 1542 rc = ef4_init_eventq(channel); 1543 if (rc) 1544 goto fail; 1545 } 1546 } 1547 1548 rc = ef4_soft_enable_interrupts(efx); 1549 if (rc) 1550 goto fail; 1551 1552 return 0; 1553 1554 fail: 1555 end_channel = channel; 1556 ef4_for_each_channel(channel, efx) { 1557 if (channel == end_channel) 1558 break; 1559 if (channel->type->keep_eventq) 1560 ef4_fini_eventq(channel); 1561 } 1562 1563 efx->type->irq_disable_non_ev(efx); 1564 1565 return rc; 1566 } 1567 1568 static void ef4_disable_interrupts(struct ef4_nic *efx) 1569 { 1570 struct ef4_channel *channel; 1571 1572 ef4_soft_disable_interrupts(efx); 1573 1574 ef4_for_each_channel(channel, efx) { 1575 if (channel->type->keep_eventq) 1576 ef4_fini_eventq(channel); 1577 } 1578 1579 efx->type->irq_disable_non_ev(efx); 1580 } 1581 1582 static void ef4_remove_interrupts(struct ef4_nic *efx) 1583 { 1584 struct ef4_channel *channel; 1585 1586 /* Remove MSI/MSI-X interrupts */ 1587 ef4_for_each_channel(channel, efx) 1588 channel->irq = 0; 1589 pci_disable_msi(efx->pci_dev); 1590 pci_disable_msix(efx->pci_dev); 1591 1592 /* Remove legacy interrupt */ 1593 efx->legacy_irq = 0; 1594 } 1595 1596 static void ef4_set_channels(struct ef4_nic *efx) 1597 { 1598 struct ef4_channel *channel; 1599 struct ef4_tx_queue *tx_queue; 1600 1601 efx->tx_channel_offset = 1602 ef4_separate_tx_channels ? 1603 efx->n_channels - efx->n_tx_channels : 0; 1604 1605 /* We need to mark which channels really have RX and TX 1606 * queues, and adjust the TX queue numbers if we have separate 1607 * RX-only and TX-only channels. 1608 */ 1609 ef4_for_each_channel(channel, efx) { 1610 if (channel->channel < efx->n_rx_channels) 1611 channel->rx_queue.core_index = channel->channel; 1612 else 1613 channel->rx_queue.core_index = -1; 1614 1615 ef4_for_each_channel_tx_queue(tx_queue, channel) 1616 tx_queue->queue -= (efx->tx_channel_offset * 1617 EF4_TXQ_TYPES); 1618 } 1619 } 1620 1621 static int ef4_probe_nic(struct ef4_nic *efx) 1622 { 1623 int rc; 1624 1625 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); 1626 1627 /* Carry out hardware-type specific initialisation */ 1628 rc = efx->type->probe(efx); 1629 if (rc) 1630 return rc; 1631 1632 do { 1633 if (!efx->max_channels || !efx->max_tx_channels) { 1634 netif_err(efx, drv, efx->net_dev, 1635 "Insufficient resources to allocate" 1636 " any channels\n"); 1637 rc = -ENOSPC; 1638 goto fail1; 1639 } 1640 1641 /* Determine the number of channels and queues by trying 1642 * to hook in MSI-X interrupts. 1643 */ 1644 rc = ef4_probe_interrupts(efx); 1645 if (rc) 1646 goto fail1; 1647 1648 ef4_set_channels(efx); 1649 1650 /* dimension_resources can fail with EAGAIN */ 1651 rc = efx->type->dimension_resources(efx); 1652 if (rc != 0 && rc != -EAGAIN) 1653 goto fail2; 1654 1655 if (rc == -EAGAIN) 1656 /* try again with new max_channels */ 1657 ef4_remove_interrupts(efx); 1658 1659 } while (rc == -EAGAIN); 1660 1661 if (efx->n_channels > 1) 1662 netdev_rss_key_fill(&efx->rx_hash_key, 1663 sizeof(efx->rx_hash_key)); 1664 ef4_set_default_rx_indir_table(efx); 1665 1666 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); 1667 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); 1668 1669 /* Initialise the interrupt moderation settings */ 1670 efx->irq_mod_step_us = DIV_ROUND_UP(efx->timer_quantum_ns, 1000); 1671 ef4_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, 1672 true); 1673 1674 return 0; 1675 1676 fail2: 1677 ef4_remove_interrupts(efx); 1678 fail1: 1679 efx->type->remove(efx); 1680 return rc; 1681 } 1682 1683 static void ef4_remove_nic(struct ef4_nic *efx) 1684 { 1685 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); 1686 1687 ef4_remove_interrupts(efx); 1688 efx->type->remove(efx); 1689 } 1690 1691 static int ef4_probe_filters(struct ef4_nic *efx) 1692 { 1693 int rc; 1694 1695 spin_lock_init(&efx->filter_lock); 1696 init_rwsem(&efx->filter_sem); 1697 mutex_lock(&efx->mac_lock); 1698 down_write(&efx->filter_sem); 1699 rc = efx->type->filter_table_probe(efx); 1700 if (rc) 1701 goto out_unlock; 1702 1703 #ifdef CONFIG_RFS_ACCEL 1704 if (efx->type->offload_features & NETIF_F_NTUPLE) { 1705 struct ef4_channel *channel; 1706 int i, success = 1; 1707 1708 ef4_for_each_channel(channel, efx) { 1709 channel->rps_flow_id = 1710 kcalloc(efx->type->max_rx_ip_filters, 1711 sizeof(*channel->rps_flow_id), 1712 GFP_KERNEL); 1713 if (!channel->rps_flow_id) 1714 success = 0; 1715 else 1716 for (i = 0; 1717 i < efx->type->max_rx_ip_filters; 1718 ++i) 1719 channel->rps_flow_id[i] = 1720 RPS_FLOW_ID_INVALID; 1721 } 1722 1723 if (!success) { 1724 ef4_for_each_channel(channel, efx) 1725 kfree(channel->rps_flow_id); 1726 efx->type->filter_table_remove(efx); 1727 rc = -ENOMEM; 1728 goto out_unlock; 1729 } 1730 1731 efx->rps_expire_index = efx->rps_expire_channel = 0; 1732 } 1733 #endif 1734 out_unlock: 1735 up_write(&efx->filter_sem); 1736 mutex_unlock(&efx->mac_lock); 1737 return rc; 1738 } 1739 1740 static void ef4_remove_filters(struct ef4_nic *efx) 1741 { 1742 #ifdef CONFIG_RFS_ACCEL 1743 struct ef4_channel *channel; 1744 1745 ef4_for_each_channel(channel, efx) 1746 kfree(channel->rps_flow_id); 1747 #endif 1748 down_write(&efx->filter_sem); 1749 efx->type->filter_table_remove(efx); 1750 up_write(&efx->filter_sem); 1751 } 1752 1753 static void ef4_restore_filters(struct ef4_nic *efx) 1754 { 1755 down_read(&efx->filter_sem); 1756 efx->type->filter_table_restore(efx); 1757 up_read(&efx->filter_sem); 1758 } 1759 1760 /************************************************************************** 1761 * 1762 * NIC startup/shutdown 1763 * 1764 *************************************************************************/ 1765 1766 static int ef4_probe_all(struct ef4_nic *efx) 1767 { 1768 int rc; 1769 1770 rc = ef4_probe_nic(efx); 1771 if (rc) { 1772 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); 1773 goto fail1; 1774 } 1775 1776 rc = ef4_probe_port(efx); 1777 if (rc) { 1778 netif_err(efx, probe, efx->net_dev, "failed to create port\n"); 1779 goto fail2; 1780 } 1781 1782 BUILD_BUG_ON(EF4_DEFAULT_DMAQ_SIZE < EF4_RXQ_MIN_ENT); 1783 if (WARN_ON(EF4_DEFAULT_DMAQ_SIZE < EF4_TXQ_MIN_ENT(efx))) { 1784 rc = -EINVAL; 1785 goto fail3; 1786 } 1787 efx->rxq_entries = efx->txq_entries = EF4_DEFAULT_DMAQ_SIZE; 1788 1789 rc = ef4_probe_filters(efx); 1790 if (rc) { 1791 netif_err(efx, probe, efx->net_dev, 1792 "failed to create filter tables\n"); 1793 goto fail4; 1794 } 1795 1796 rc = ef4_probe_channels(efx); 1797 if (rc) 1798 goto fail5; 1799 1800 return 0; 1801 1802 fail5: 1803 ef4_remove_filters(efx); 1804 fail4: 1805 fail3: 1806 ef4_remove_port(efx); 1807 fail2: 1808 ef4_remove_nic(efx); 1809 fail1: 1810 return rc; 1811 } 1812 1813 /* If the interface is supposed to be running but is not, start 1814 * the hardware and software data path, regular activity for the port 1815 * (MAC statistics, link polling, etc.) and schedule the port to be 1816 * reconfigured. Interrupts must already be enabled. This function 1817 * is safe to call multiple times, so long as the NIC is not disabled. 1818 * Requires the RTNL lock. 1819 */ 1820 static void ef4_start_all(struct ef4_nic *efx) 1821 { 1822 EF4_ASSERT_RESET_SERIALISED(efx); 1823 BUG_ON(efx->state == STATE_DISABLED); 1824 1825 /* Check that it is appropriate to restart the interface. All 1826 * of these flags are safe to read under just the rtnl lock */ 1827 if (efx->port_enabled || !netif_running(efx->net_dev) || 1828 efx->reset_pending) 1829 return; 1830 1831 ef4_start_port(efx); 1832 ef4_start_datapath(efx); 1833 1834 /* Start the hardware monitor if there is one */ 1835 if (efx->type->monitor != NULL) 1836 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1837 ef4_monitor_interval); 1838 1839 efx->type->start_stats(efx); 1840 efx->type->pull_stats(efx); 1841 spin_lock_bh(&efx->stats_lock); 1842 efx->type->update_stats(efx, NULL, NULL); 1843 spin_unlock_bh(&efx->stats_lock); 1844 } 1845 1846 /* Quiesce the hardware and software data path, and regular activity 1847 * for the port without bringing the link down. Safe to call multiple 1848 * times with the NIC in almost any state, but interrupts should be 1849 * enabled. Requires the RTNL lock. 1850 */ 1851 static void ef4_stop_all(struct ef4_nic *efx) 1852 { 1853 EF4_ASSERT_RESET_SERIALISED(efx); 1854 1855 /* port_enabled can be read safely under the rtnl lock */ 1856 if (!efx->port_enabled) 1857 return; 1858 1859 /* update stats before we go down so we can accurately count 1860 * rx_nodesc_drops 1861 */ 1862 efx->type->pull_stats(efx); 1863 spin_lock_bh(&efx->stats_lock); 1864 efx->type->update_stats(efx, NULL, NULL); 1865 spin_unlock_bh(&efx->stats_lock); 1866 efx->type->stop_stats(efx); 1867 ef4_stop_port(efx); 1868 1869 /* Stop the kernel transmit interface. This is only valid if 1870 * the device is stopped or detached; otherwise the watchdog 1871 * may fire immediately. 1872 */ 1873 WARN_ON(netif_running(efx->net_dev) && 1874 netif_device_present(efx->net_dev)); 1875 netif_tx_disable(efx->net_dev); 1876 1877 ef4_stop_datapath(efx); 1878 } 1879 1880 static void ef4_remove_all(struct ef4_nic *efx) 1881 { 1882 ef4_remove_channels(efx); 1883 ef4_remove_filters(efx); 1884 ef4_remove_port(efx); 1885 ef4_remove_nic(efx); 1886 } 1887 1888 /************************************************************************** 1889 * 1890 * Interrupt moderation 1891 * 1892 **************************************************************************/ 1893 unsigned int ef4_usecs_to_ticks(struct ef4_nic *efx, unsigned int usecs) 1894 { 1895 if (usecs == 0) 1896 return 0; 1897 if (usecs * 1000 < efx->timer_quantum_ns) 1898 return 1; /* never round down to 0 */ 1899 return usecs * 1000 / efx->timer_quantum_ns; 1900 } 1901 1902 unsigned int ef4_ticks_to_usecs(struct ef4_nic *efx, unsigned int ticks) 1903 { 1904 /* We must round up when converting ticks to microseconds 1905 * because we round down when converting the other way. 1906 */ 1907 return DIV_ROUND_UP(ticks * efx->timer_quantum_ns, 1000); 1908 } 1909 1910 /* Set interrupt moderation parameters */ 1911 int ef4_init_irq_moderation(struct ef4_nic *efx, unsigned int tx_usecs, 1912 unsigned int rx_usecs, bool rx_adaptive, 1913 bool rx_may_override_tx) 1914 { 1915 struct ef4_channel *channel; 1916 unsigned int timer_max_us; 1917 1918 EF4_ASSERT_RESET_SERIALISED(efx); 1919 1920 timer_max_us = efx->timer_max_ns / 1000; 1921 1922 if (tx_usecs > timer_max_us || rx_usecs > timer_max_us) 1923 return -EINVAL; 1924 1925 if (tx_usecs != rx_usecs && efx->tx_channel_offset == 0 && 1926 !rx_may_override_tx) { 1927 netif_err(efx, drv, efx->net_dev, "Channels are shared. " 1928 "RX and TX IRQ moderation must be equal\n"); 1929 return -EINVAL; 1930 } 1931 1932 efx->irq_rx_adaptive = rx_adaptive; 1933 efx->irq_rx_moderation_us = rx_usecs; 1934 ef4_for_each_channel(channel, efx) { 1935 if (ef4_channel_has_rx_queue(channel)) 1936 channel->irq_moderation_us = rx_usecs; 1937 else if (ef4_channel_has_tx_queues(channel)) 1938 channel->irq_moderation_us = tx_usecs; 1939 } 1940 1941 return 0; 1942 } 1943 1944 void ef4_get_irq_moderation(struct ef4_nic *efx, unsigned int *tx_usecs, 1945 unsigned int *rx_usecs, bool *rx_adaptive) 1946 { 1947 *rx_adaptive = efx->irq_rx_adaptive; 1948 *rx_usecs = efx->irq_rx_moderation_us; 1949 1950 /* If channels are shared between RX and TX, so is IRQ 1951 * moderation. Otherwise, IRQ moderation is the same for all 1952 * TX channels and is not adaptive. 1953 */ 1954 if (efx->tx_channel_offset == 0) { 1955 *tx_usecs = *rx_usecs; 1956 } else { 1957 struct ef4_channel *tx_channel; 1958 1959 tx_channel = efx->channel[efx->tx_channel_offset]; 1960 *tx_usecs = tx_channel->irq_moderation_us; 1961 } 1962 } 1963 1964 /************************************************************************** 1965 * 1966 * Hardware monitor 1967 * 1968 **************************************************************************/ 1969 1970 /* Run periodically off the general workqueue */ 1971 static void ef4_monitor(struct work_struct *data) 1972 { 1973 struct ef4_nic *efx = container_of(data, struct ef4_nic, 1974 monitor_work.work); 1975 1976 netif_vdbg(efx, timer, efx->net_dev, 1977 "hardware monitor executing on CPU %d\n", 1978 raw_smp_processor_id()); 1979 BUG_ON(efx->type->monitor == NULL); 1980 1981 /* If the mac_lock is already held then it is likely a port 1982 * reconfiguration is already in place, which will likely do 1983 * most of the work of monitor() anyway. */ 1984 if (mutex_trylock(&efx->mac_lock)) { 1985 if (efx->port_enabled) 1986 efx->type->monitor(efx); 1987 mutex_unlock(&efx->mac_lock); 1988 } 1989 1990 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1991 ef4_monitor_interval); 1992 } 1993 1994 /************************************************************************** 1995 * 1996 * ioctls 1997 * 1998 *************************************************************************/ 1999 2000 /* Net device ioctl 2001 * Context: process, rtnl_lock() held. 2002 */ 2003 static int ef4_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 2004 { 2005 struct ef4_nic *efx = netdev_priv(net_dev); 2006 struct mii_ioctl_data *data = if_mii(ifr); 2007 2008 /* Convert phy_id from older PRTAD/DEVAD format */ 2009 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && 2010 (data->phy_id & 0xfc00) == 0x0400) 2011 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; 2012 2013 return mdio_mii_ioctl(&efx->mdio, data, cmd); 2014 } 2015 2016 /************************************************************************** 2017 * 2018 * NAPI interface 2019 * 2020 **************************************************************************/ 2021 2022 static void ef4_init_napi_channel(struct ef4_channel *channel) 2023 { 2024 struct ef4_nic *efx = channel->efx; 2025 2026 channel->napi_dev = efx->net_dev; 2027 netif_napi_add(channel->napi_dev, &channel->napi_str, 2028 ef4_poll, napi_weight); 2029 } 2030 2031 static void ef4_init_napi(struct ef4_nic *efx) 2032 { 2033 struct ef4_channel *channel; 2034 2035 ef4_for_each_channel(channel, efx) 2036 ef4_init_napi_channel(channel); 2037 } 2038 2039 static void ef4_fini_napi_channel(struct ef4_channel *channel) 2040 { 2041 if (channel->napi_dev) 2042 netif_napi_del(&channel->napi_str); 2043 2044 channel->napi_dev = NULL; 2045 } 2046 2047 static void ef4_fini_napi(struct ef4_nic *efx) 2048 { 2049 struct ef4_channel *channel; 2050 2051 ef4_for_each_channel(channel, efx) 2052 ef4_fini_napi_channel(channel); 2053 } 2054 2055 /************************************************************************** 2056 * 2057 * Kernel net device interface 2058 * 2059 *************************************************************************/ 2060 2061 /* Context: process, rtnl_lock() held. */ 2062 int ef4_net_open(struct net_device *net_dev) 2063 { 2064 struct ef4_nic *efx = netdev_priv(net_dev); 2065 int rc; 2066 2067 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", 2068 raw_smp_processor_id()); 2069 2070 rc = ef4_check_disabled(efx); 2071 if (rc) 2072 return rc; 2073 if (efx->phy_mode & PHY_MODE_SPECIAL) 2074 return -EBUSY; 2075 2076 /* Notify the kernel of the link state polled during driver load, 2077 * before the monitor starts running */ 2078 ef4_link_status_changed(efx); 2079 2080 ef4_start_all(efx); 2081 ef4_selftest_async_start(efx); 2082 return 0; 2083 } 2084 2085 /* Context: process, rtnl_lock() held. 2086 * Note that the kernel will ignore our return code; this method 2087 * should really be a void. 2088 */ 2089 int ef4_net_stop(struct net_device *net_dev) 2090 { 2091 struct ef4_nic *efx = netdev_priv(net_dev); 2092 2093 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", 2094 raw_smp_processor_id()); 2095 2096 /* Stop the device and flush all the channels */ 2097 ef4_stop_all(efx); 2098 2099 return 0; 2100 } 2101 2102 /* Context: process, dev_base_lock or RTNL held, non-blocking. */ 2103 static void ef4_net_stats(struct net_device *net_dev, 2104 struct rtnl_link_stats64 *stats) 2105 { 2106 struct ef4_nic *efx = netdev_priv(net_dev); 2107 2108 spin_lock_bh(&efx->stats_lock); 2109 efx->type->update_stats(efx, NULL, stats); 2110 spin_unlock_bh(&efx->stats_lock); 2111 } 2112 2113 /* Context: netif_tx_lock held, BHs disabled. */ 2114 static void ef4_watchdog(struct net_device *net_dev) 2115 { 2116 struct ef4_nic *efx = netdev_priv(net_dev); 2117 2118 netif_err(efx, tx_err, efx->net_dev, 2119 "TX stuck with port_enabled=%d: resetting channels\n", 2120 efx->port_enabled); 2121 2122 ef4_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); 2123 } 2124 2125 2126 /* Context: process, rtnl_lock() held. */ 2127 static int ef4_change_mtu(struct net_device *net_dev, int new_mtu) 2128 { 2129 struct ef4_nic *efx = netdev_priv(net_dev); 2130 int rc; 2131 2132 rc = ef4_check_disabled(efx); 2133 if (rc) 2134 return rc; 2135 2136 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); 2137 2138 ef4_device_detach_sync(efx); 2139 ef4_stop_all(efx); 2140 2141 mutex_lock(&efx->mac_lock); 2142 net_dev->mtu = new_mtu; 2143 ef4_mac_reconfigure(efx); 2144 mutex_unlock(&efx->mac_lock); 2145 2146 ef4_start_all(efx); 2147 netif_device_attach(efx->net_dev); 2148 return 0; 2149 } 2150 2151 static int ef4_set_mac_address(struct net_device *net_dev, void *data) 2152 { 2153 struct ef4_nic *efx = netdev_priv(net_dev); 2154 struct sockaddr *addr = data; 2155 u8 *new_addr = addr->sa_data; 2156 u8 old_addr[6]; 2157 int rc; 2158 2159 if (!is_valid_ether_addr(new_addr)) { 2160 netif_err(efx, drv, efx->net_dev, 2161 "invalid ethernet MAC address requested: %pM\n", 2162 new_addr); 2163 return -EADDRNOTAVAIL; 2164 } 2165 2166 /* save old address */ 2167 ether_addr_copy(old_addr, net_dev->dev_addr); 2168 ether_addr_copy(net_dev->dev_addr, new_addr); 2169 if (efx->type->set_mac_address) { 2170 rc = efx->type->set_mac_address(efx); 2171 if (rc) { 2172 ether_addr_copy(net_dev->dev_addr, old_addr); 2173 return rc; 2174 } 2175 } 2176 2177 /* Reconfigure the MAC */ 2178 mutex_lock(&efx->mac_lock); 2179 ef4_mac_reconfigure(efx); 2180 mutex_unlock(&efx->mac_lock); 2181 2182 return 0; 2183 } 2184 2185 /* Context: netif_addr_lock held, BHs disabled. */ 2186 static void ef4_set_rx_mode(struct net_device *net_dev) 2187 { 2188 struct ef4_nic *efx = netdev_priv(net_dev); 2189 2190 if (efx->port_enabled) 2191 queue_work(efx->workqueue, &efx->mac_work); 2192 /* Otherwise ef4_start_port() will do this */ 2193 } 2194 2195 static int ef4_set_features(struct net_device *net_dev, netdev_features_t data) 2196 { 2197 struct ef4_nic *efx = netdev_priv(net_dev); 2198 int rc; 2199 2200 /* If disabling RX n-tuple filtering, clear existing filters */ 2201 if (net_dev->features & ~data & NETIF_F_NTUPLE) { 2202 rc = efx->type->filter_clear_rx(efx, EF4_FILTER_PRI_MANUAL); 2203 if (rc) 2204 return rc; 2205 } 2206 2207 /* If Rx VLAN filter is changed, update filters via mac_reconfigure */ 2208 if ((net_dev->features ^ data) & NETIF_F_HW_VLAN_CTAG_FILTER) { 2209 /* ef4_set_rx_mode() will schedule MAC work to update filters 2210 * when a new features are finally set in net_dev. 2211 */ 2212 ef4_set_rx_mode(net_dev); 2213 } 2214 2215 return 0; 2216 } 2217 2218 static const struct net_device_ops ef4_netdev_ops = { 2219 .ndo_open = ef4_net_open, 2220 .ndo_stop = ef4_net_stop, 2221 .ndo_get_stats64 = ef4_net_stats, 2222 .ndo_tx_timeout = ef4_watchdog, 2223 .ndo_start_xmit = ef4_hard_start_xmit, 2224 .ndo_validate_addr = eth_validate_addr, 2225 .ndo_do_ioctl = ef4_ioctl, 2226 .ndo_change_mtu = ef4_change_mtu, 2227 .ndo_set_mac_address = ef4_set_mac_address, 2228 .ndo_set_rx_mode = ef4_set_rx_mode, 2229 .ndo_set_features = ef4_set_features, 2230 .ndo_setup_tc = ef4_setup_tc, 2231 #ifdef CONFIG_RFS_ACCEL 2232 .ndo_rx_flow_steer = ef4_filter_rfs, 2233 #endif 2234 }; 2235 2236 static void ef4_update_name(struct ef4_nic *efx) 2237 { 2238 strcpy(efx->name, efx->net_dev->name); 2239 ef4_mtd_rename(efx); 2240 ef4_set_channel_names(efx); 2241 } 2242 2243 static int ef4_netdev_event(struct notifier_block *this, 2244 unsigned long event, void *ptr) 2245 { 2246 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr); 2247 2248 if ((net_dev->netdev_ops == &ef4_netdev_ops) && 2249 event == NETDEV_CHANGENAME) 2250 ef4_update_name(netdev_priv(net_dev)); 2251 2252 return NOTIFY_DONE; 2253 } 2254 2255 static struct notifier_block ef4_netdev_notifier = { 2256 .notifier_call = ef4_netdev_event, 2257 }; 2258 2259 static ssize_t 2260 show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) 2261 { 2262 struct ef4_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2263 return sprintf(buf, "%d\n", efx->phy_type); 2264 } 2265 static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL); 2266 2267 static int ef4_register_netdev(struct ef4_nic *efx) 2268 { 2269 struct net_device *net_dev = efx->net_dev; 2270 struct ef4_channel *channel; 2271 int rc; 2272 2273 net_dev->watchdog_timeo = 5 * HZ; 2274 net_dev->irq = efx->pci_dev->irq; 2275 net_dev->netdev_ops = &ef4_netdev_ops; 2276 net_dev->ethtool_ops = &ef4_ethtool_ops; 2277 net_dev->gso_max_segs = EF4_TSO_MAX_SEGS; 2278 net_dev->min_mtu = EF4_MIN_MTU; 2279 net_dev->max_mtu = EF4_MAX_MTU; 2280 2281 rtnl_lock(); 2282 2283 /* Enable resets to be scheduled and check whether any were 2284 * already requested. If so, the NIC is probably hosed so we 2285 * abort. 2286 */ 2287 efx->state = STATE_READY; 2288 smp_mb(); /* ensure we change state before checking reset_pending */ 2289 if (efx->reset_pending) { 2290 netif_err(efx, probe, efx->net_dev, 2291 "aborting probe due to scheduled reset\n"); 2292 rc = -EIO; 2293 goto fail_locked; 2294 } 2295 2296 rc = dev_alloc_name(net_dev, net_dev->name); 2297 if (rc < 0) 2298 goto fail_locked; 2299 ef4_update_name(efx); 2300 2301 /* Always start with carrier off; PHY events will detect the link */ 2302 netif_carrier_off(net_dev); 2303 2304 rc = register_netdevice(net_dev); 2305 if (rc) 2306 goto fail_locked; 2307 2308 ef4_for_each_channel(channel, efx) { 2309 struct ef4_tx_queue *tx_queue; 2310 ef4_for_each_channel_tx_queue(tx_queue, channel) 2311 ef4_init_tx_queue_core_txq(tx_queue); 2312 } 2313 2314 ef4_associate(efx); 2315 2316 rtnl_unlock(); 2317 2318 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2319 if (rc) { 2320 netif_err(efx, drv, efx->net_dev, 2321 "failed to init net dev attributes\n"); 2322 goto fail_registered; 2323 } 2324 return 0; 2325 2326 fail_registered: 2327 rtnl_lock(); 2328 ef4_dissociate(efx); 2329 unregister_netdevice(net_dev); 2330 fail_locked: 2331 efx->state = STATE_UNINIT; 2332 rtnl_unlock(); 2333 netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); 2334 return rc; 2335 } 2336 2337 static void ef4_unregister_netdev(struct ef4_nic *efx) 2338 { 2339 if (!efx->net_dev) 2340 return; 2341 2342 BUG_ON(netdev_priv(efx->net_dev) != efx); 2343 2344 if (ef4_dev_registered(efx)) { 2345 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); 2346 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2347 unregister_netdev(efx->net_dev); 2348 } 2349 } 2350 2351 /************************************************************************** 2352 * 2353 * Device reset and suspend 2354 * 2355 **************************************************************************/ 2356 2357 /* Tears down the entire software state and most of the hardware state 2358 * before reset. */ 2359 void ef4_reset_down(struct ef4_nic *efx, enum reset_type method) 2360 { 2361 EF4_ASSERT_RESET_SERIALISED(efx); 2362 2363 ef4_stop_all(efx); 2364 ef4_disable_interrupts(efx); 2365 2366 mutex_lock(&efx->mac_lock); 2367 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE && 2368 method != RESET_TYPE_DATAPATH) 2369 efx->phy_op->fini(efx); 2370 efx->type->fini(efx); 2371 } 2372 2373 /* This function will always ensure that the locks acquired in 2374 * ef4_reset_down() are released. A failure return code indicates 2375 * that we were unable to reinitialise the hardware, and the 2376 * driver should be disabled. If ok is false, then the rx and tx 2377 * engines are not restarted, pending a RESET_DISABLE. */ 2378 int ef4_reset_up(struct ef4_nic *efx, enum reset_type method, bool ok) 2379 { 2380 int rc; 2381 2382 EF4_ASSERT_RESET_SERIALISED(efx); 2383 2384 /* Ensure that SRAM is initialised even if we're disabling the device */ 2385 rc = efx->type->init(efx); 2386 if (rc) { 2387 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); 2388 goto fail; 2389 } 2390 2391 if (!ok) 2392 goto fail; 2393 2394 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE && 2395 method != RESET_TYPE_DATAPATH) { 2396 rc = efx->phy_op->init(efx); 2397 if (rc) 2398 goto fail; 2399 rc = efx->phy_op->reconfigure(efx); 2400 if (rc && rc != -EPERM) 2401 netif_err(efx, drv, efx->net_dev, 2402 "could not restore PHY settings\n"); 2403 } 2404 2405 rc = ef4_enable_interrupts(efx); 2406 if (rc) 2407 goto fail; 2408 2409 down_read(&efx->filter_sem); 2410 ef4_restore_filters(efx); 2411 up_read(&efx->filter_sem); 2412 2413 mutex_unlock(&efx->mac_lock); 2414 2415 ef4_start_all(efx); 2416 2417 return 0; 2418 2419 fail: 2420 efx->port_initialized = false; 2421 2422 mutex_unlock(&efx->mac_lock); 2423 2424 return rc; 2425 } 2426 2427 /* Reset the NIC using the specified method. Note that the reset may 2428 * fail, in which case the card will be left in an unusable state. 2429 * 2430 * Caller must hold the rtnl_lock. 2431 */ 2432 int ef4_reset(struct ef4_nic *efx, enum reset_type method) 2433 { 2434 int rc, rc2; 2435 bool disabled; 2436 2437 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", 2438 RESET_TYPE(method)); 2439 2440 ef4_device_detach_sync(efx); 2441 ef4_reset_down(efx, method); 2442 2443 rc = efx->type->reset(efx, method); 2444 if (rc) { 2445 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); 2446 goto out; 2447 } 2448 2449 /* Clear flags for the scopes we covered. We assume the NIC and 2450 * driver are now quiescent so that there is no race here. 2451 */ 2452 if (method < RESET_TYPE_MAX_METHOD) 2453 efx->reset_pending &= -(1 << (method + 1)); 2454 else /* it doesn't fit into the well-ordered scope hierarchy */ 2455 __clear_bit(method, &efx->reset_pending); 2456 2457 /* Reinitialise bus-mastering, which may have been turned off before 2458 * the reset was scheduled. This is still appropriate, even in the 2459 * RESET_TYPE_DISABLE since this driver generally assumes the hardware 2460 * can respond to requests. */ 2461 pci_set_master(efx->pci_dev); 2462 2463 out: 2464 /* Leave device stopped if necessary */ 2465 disabled = rc || 2466 method == RESET_TYPE_DISABLE || 2467 method == RESET_TYPE_RECOVER_OR_DISABLE; 2468 rc2 = ef4_reset_up(efx, method, !disabled); 2469 if (rc2) { 2470 disabled = true; 2471 if (!rc) 2472 rc = rc2; 2473 } 2474 2475 if (disabled) { 2476 dev_close(efx->net_dev); 2477 netif_err(efx, drv, efx->net_dev, "has been disabled\n"); 2478 efx->state = STATE_DISABLED; 2479 } else { 2480 netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); 2481 netif_device_attach(efx->net_dev); 2482 } 2483 return rc; 2484 } 2485 2486 /* Try recovery mechanisms. 2487 * For now only EEH is supported. 2488 * Returns 0 if the recovery mechanisms are unsuccessful. 2489 * Returns a non-zero value otherwise. 2490 */ 2491 int ef4_try_recovery(struct ef4_nic *efx) 2492 { 2493 #ifdef CONFIG_EEH 2494 /* A PCI error can occur and not be seen by EEH because nothing 2495 * happens on the PCI bus. In this case the driver may fail and 2496 * schedule a 'recover or reset', leading to this recovery handler. 2497 * Manually call the eeh failure check function. 2498 */ 2499 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev); 2500 if (eeh_dev_check_failure(eehdev)) { 2501 /* The EEH mechanisms will handle the error and reset the 2502 * device if necessary. 2503 */ 2504 return 1; 2505 } 2506 #endif 2507 return 0; 2508 } 2509 2510 /* The worker thread exists so that code that cannot sleep can 2511 * schedule a reset for later. 2512 */ 2513 static void ef4_reset_work(struct work_struct *data) 2514 { 2515 struct ef4_nic *efx = container_of(data, struct ef4_nic, reset_work); 2516 unsigned long pending; 2517 enum reset_type method; 2518 2519 pending = READ_ONCE(efx->reset_pending); 2520 method = fls(pending) - 1; 2521 2522 if ((method == RESET_TYPE_RECOVER_OR_DISABLE || 2523 method == RESET_TYPE_RECOVER_OR_ALL) && 2524 ef4_try_recovery(efx)) 2525 return; 2526 2527 if (!pending) 2528 return; 2529 2530 rtnl_lock(); 2531 2532 /* We checked the state in ef4_schedule_reset() but it may 2533 * have changed by now. Now that we have the RTNL lock, 2534 * it cannot change again. 2535 */ 2536 if (efx->state == STATE_READY) 2537 (void)ef4_reset(efx, method); 2538 2539 rtnl_unlock(); 2540 } 2541 2542 void ef4_schedule_reset(struct ef4_nic *efx, enum reset_type type) 2543 { 2544 enum reset_type method; 2545 2546 if (efx->state == STATE_RECOVERY) { 2547 netif_dbg(efx, drv, efx->net_dev, 2548 "recovering: skip scheduling %s reset\n", 2549 RESET_TYPE(type)); 2550 return; 2551 } 2552 2553 switch (type) { 2554 case RESET_TYPE_INVISIBLE: 2555 case RESET_TYPE_ALL: 2556 case RESET_TYPE_RECOVER_OR_ALL: 2557 case RESET_TYPE_WORLD: 2558 case RESET_TYPE_DISABLE: 2559 case RESET_TYPE_RECOVER_OR_DISABLE: 2560 case RESET_TYPE_DATAPATH: 2561 method = type; 2562 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", 2563 RESET_TYPE(method)); 2564 break; 2565 default: 2566 method = efx->type->map_reset_reason(type); 2567 netif_dbg(efx, drv, efx->net_dev, 2568 "scheduling %s reset for %s\n", 2569 RESET_TYPE(method), RESET_TYPE(type)); 2570 break; 2571 } 2572 2573 set_bit(method, &efx->reset_pending); 2574 smp_mb(); /* ensure we change reset_pending before checking state */ 2575 2576 /* If we're not READY then just leave the flags set as the cue 2577 * to abort probing or reschedule the reset later. 2578 */ 2579 if (READ_ONCE(efx->state) != STATE_READY) 2580 return; 2581 2582 queue_work(reset_workqueue, &efx->reset_work); 2583 } 2584 2585 /************************************************************************** 2586 * 2587 * List of NICs we support 2588 * 2589 **************************************************************************/ 2590 2591 /* PCI device ID table */ 2592 static const struct pci_device_id ef4_pci_table[] = { 2593 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 2594 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), 2595 .driver_data = (unsigned long) &falcon_a1_nic_type}, 2596 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 2597 PCI_DEVICE_ID_SOLARFLARE_SFC4000B), 2598 .driver_data = (unsigned long) &falcon_b0_nic_type}, 2599 {0} /* end of list */ 2600 }; 2601 2602 /************************************************************************** 2603 * 2604 * Dummy PHY/MAC operations 2605 * 2606 * Can be used for some unimplemented operations 2607 * Needed so all function pointers are valid and do not have to be tested 2608 * before use 2609 * 2610 **************************************************************************/ 2611 int ef4_port_dummy_op_int(struct ef4_nic *efx) 2612 { 2613 return 0; 2614 } 2615 void ef4_port_dummy_op_void(struct ef4_nic *efx) {} 2616 2617 static bool ef4_port_dummy_op_poll(struct ef4_nic *efx) 2618 { 2619 return false; 2620 } 2621 2622 static const struct ef4_phy_operations ef4_dummy_phy_operations = { 2623 .init = ef4_port_dummy_op_int, 2624 .reconfigure = ef4_port_dummy_op_int, 2625 .poll = ef4_port_dummy_op_poll, 2626 .fini = ef4_port_dummy_op_void, 2627 }; 2628 2629 /************************************************************************** 2630 * 2631 * Data housekeeping 2632 * 2633 **************************************************************************/ 2634 2635 /* This zeroes out and then fills in the invariants in a struct 2636 * ef4_nic (including all sub-structures). 2637 */ 2638 static int ef4_init_struct(struct ef4_nic *efx, 2639 struct pci_dev *pci_dev, struct net_device *net_dev) 2640 { 2641 int i; 2642 2643 /* Initialise common structures */ 2644 INIT_LIST_HEAD(&efx->node); 2645 INIT_LIST_HEAD(&efx->secondary_list); 2646 spin_lock_init(&efx->biu_lock); 2647 #ifdef CONFIG_SFC_FALCON_MTD 2648 INIT_LIST_HEAD(&efx->mtd_list); 2649 #endif 2650 INIT_WORK(&efx->reset_work, ef4_reset_work); 2651 INIT_DELAYED_WORK(&efx->monitor_work, ef4_monitor); 2652 INIT_DELAYED_WORK(&efx->selftest_work, ef4_selftest_async_work); 2653 efx->pci_dev = pci_dev; 2654 efx->msg_enable = debug; 2655 efx->state = STATE_UNINIT; 2656 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); 2657 2658 efx->net_dev = net_dev; 2659 efx->rx_prefix_size = efx->type->rx_prefix_size; 2660 efx->rx_ip_align = 2661 NET_IP_ALIGN ? (efx->rx_prefix_size + NET_IP_ALIGN) % 4 : 0; 2662 efx->rx_packet_hash_offset = 2663 efx->type->rx_hash_offset - efx->type->rx_prefix_size; 2664 efx->rx_packet_ts_offset = 2665 efx->type->rx_ts_offset - efx->type->rx_prefix_size; 2666 spin_lock_init(&efx->stats_lock); 2667 mutex_init(&efx->mac_lock); 2668 efx->phy_op = &ef4_dummy_phy_operations; 2669 efx->mdio.dev = net_dev; 2670 INIT_WORK(&efx->mac_work, ef4_mac_work); 2671 init_waitqueue_head(&efx->flush_wq); 2672 2673 for (i = 0; i < EF4_MAX_CHANNELS; i++) { 2674 efx->channel[i] = ef4_alloc_channel(efx, i, NULL); 2675 if (!efx->channel[i]) 2676 goto fail; 2677 efx->msi_context[i].efx = efx; 2678 efx->msi_context[i].index = i; 2679 } 2680 2681 /* Higher numbered interrupt modes are less capable! */ 2682 efx->interrupt_mode = max(efx->type->max_interrupt_mode, 2683 interrupt_mode); 2684 2685 /* Would be good to use the net_dev name, but we're too early */ 2686 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", 2687 pci_name(pci_dev)); 2688 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); 2689 if (!efx->workqueue) 2690 goto fail; 2691 2692 return 0; 2693 2694 fail: 2695 ef4_fini_struct(efx); 2696 return -ENOMEM; 2697 } 2698 2699 static void ef4_fini_struct(struct ef4_nic *efx) 2700 { 2701 int i; 2702 2703 for (i = 0; i < EF4_MAX_CHANNELS; i++) 2704 kfree(efx->channel[i]); 2705 2706 kfree(efx->vpd_sn); 2707 2708 if (efx->workqueue) { 2709 destroy_workqueue(efx->workqueue); 2710 efx->workqueue = NULL; 2711 } 2712 } 2713 2714 void ef4_update_sw_stats(struct ef4_nic *efx, u64 *stats) 2715 { 2716 u64 n_rx_nodesc_trunc = 0; 2717 struct ef4_channel *channel; 2718 2719 ef4_for_each_channel(channel, efx) 2720 n_rx_nodesc_trunc += channel->n_rx_nodesc_trunc; 2721 stats[GENERIC_STAT_rx_nodesc_trunc] = n_rx_nodesc_trunc; 2722 stats[GENERIC_STAT_rx_noskb_drops] = atomic_read(&efx->n_rx_noskb_drops); 2723 } 2724 2725 /************************************************************************** 2726 * 2727 * PCI interface 2728 * 2729 **************************************************************************/ 2730 2731 /* Main body of final NIC shutdown code 2732 * This is called only at module unload (or hotplug removal). 2733 */ 2734 static void ef4_pci_remove_main(struct ef4_nic *efx) 2735 { 2736 /* Flush reset_work. It can no longer be scheduled since we 2737 * are not READY. 2738 */ 2739 BUG_ON(efx->state == STATE_READY); 2740 cancel_work_sync(&efx->reset_work); 2741 2742 ef4_disable_interrupts(efx); 2743 ef4_nic_fini_interrupt(efx); 2744 ef4_fini_port(efx); 2745 efx->type->fini(efx); 2746 ef4_fini_napi(efx); 2747 ef4_remove_all(efx); 2748 } 2749 2750 /* Final NIC shutdown 2751 * This is called only at module unload (or hotplug removal). A PF can call 2752 * this on its VFs to ensure they are unbound first. 2753 */ 2754 static void ef4_pci_remove(struct pci_dev *pci_dev) 2755 { 2756 struct ef4_nic *efx; 2757 2758 efx = pci_get_drvdata(pci_dev); 2759 if (!efx) 2760 return; 2761 2762 /* Mark the NIC as fini, then stop the interface */ 2763 rtnl_lock(); 2764 ef4_dissociate(efx); 2765 dev_close(efx->net_dev); 2766 ef4_disable_interrupts(efx); 2767 efx->state = STATE_UNINIT; 2768 rtnl_unlock(); 2769 2770 ef4_unregister_netdev(efx); 2771 2772 ef4_mtd_remove(efx); 2773 2774 ef4_pci_remove_main(efx); 2775 2776 ef4_fini_io(efx); 2777 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); 2778 2779 ef4_fini_struct(efx); 2780 free_netdev(efx->net_dev); 2781 2782 pci_disable_pcie_error_reporting(pci_dev); 2783 }; 2784 2785 /* NIC VPD information 2786 * Called during probe to display the part number of the 2787 * installed NIC. VPD is potentially very large but this should 2788 * always appear within the first 512 bytes. 2789 */ 2790 #define SFC_VPD_LEN 512 2791 static void ef4_probe_vpd_strings(struct ef4_nic *efx) 2792 { 2793 struct pci_dev *dev = efx->pci_dev; 2794 char vpd_data[SFC_VPD_LEN]; 2795 ssize_t vpd_size; 2796 int ro_start, ro_size, i, j; 2797 2798 /* Get the vpd data from the device */ 2799 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); 2800 if (vpd_size <= 0) { 2801 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); 2802 return; 2803 } 2804 2805 /* Get the Read only section */ 2806 ro_start = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); 2807 if (ro_start < 0) { 2808 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); 2809 return; 2810 } 2811 2812 ro_size = pci_vpd_lrdt_size(&vpd_data[ro_start]); 2813 j = ro_size; 2814 i = ro_start + PCI_VPD_LRDT_TAG_SIZE; 2815 if (i + j > vpd_size) 2816 j = vpd_size - i; 2817 2818 /* Get the Part number */ 2819 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); 2820 if (i < 0) { 2821 netif_err(efx, drv, efx->net_dev, "Part number not found\n"); 2822 return; 2823 } 2824 2825 j = pci_vpd_info_field_size(&vpd_data[i]); 2826 i += PCI_VPD_INFO_FLD_HDR_SIZE; 2827 if (i + j > vpd_size) { 2828 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); 2829 return; 2830 } 2831 2832 netif_info(efx, drv, efx->net_dev, 2833 "Part Number : %.*s\n", j, &vpd_data[i]); 2834 2835 i = ro_start + PCI_VPD_LRDT_TAG_SIZE; 2836 j = ro_size; 2837 i = pci_vpd_find_info_keyword(vpd_data, i, j, "SN"); 2838 if (i < 0) { 2839 netif_err(efx, drv, efx->net_dev, "Serial number not found\n"); 2840 return; 2841 } 2842 2843 j = pci_vpd_info_field_size(&vpd_data[i]); 2844 i += PCI_VPD_INFO_FLD_HDR_SIZE; 2845 if (i + j > vpd_size) { 2846 netif_err(efx, drv, efx->net_dev, "Incomplete serial number\n"); 2847 return; 2848 } 2849 2850 efx->vpd_sn = kmalloc(j + 1, GFP_KERNEL); 2851 if (!efx->vpd_sn) 2852 return; 2853 2854 snprintf(efx->vpd_sn, j + 1, "%s", &vpd_data[i]); 2855 } 2856 2857 2858 /* Main body of NIC initialisation 2859 * This is called at module load (or hotplug insertion, theoretically). 2860 */ 2861 static int ef4_pci_probe_main(struct ef4_nic *efx) 2862 { 2863 int rc; 2864 2865 /* Do start-of-day initialisation */ 2866 rc = ef4_probe_all(efx); 2867 if (rc) 2868 goto fail1; 2869 2870 ef4_init_napi(efx); 2871 2872 rc = efx->type->init(efx); 2873 if (rc) { 2874 netif_err(efx, probe, efx->net_dev, 2875 "failed to initialise NIC\n"); 2876 goto fail3; 2877 } 2878 2879 rc = ef4_init_port(efx); 2880 if (rc) { 2881 netif_err(efx, probe, efx->net_dev, 2882 "failed to initialise port\n"); 2883 goto fail4; 2884 } 2885 2886 rc = ef4_nic_init_interrupt(efx); 2887 if (rc) 2888 goto fail5; 2889 rc = ef4_enable_interrupts(efx); 2890 if (rc) 2891 goto fail6; 2892 2893 return 0; 2894 2895 fail6: 2896 ef4_nic_fini_interrupt(efx); 2897 fail5: 2898 ef4_fini_port(efx); 2899 fail4: 2900 efx->type->fini(efx); 2901 fail3: 2902 ef4_fini_napi(efx); 2903 ef4_remove_all(efx); 2904 fail1: 2905 return rc; 2906 } 2907 2908 /* NIC initialisation 2909 * 2910 * This is called at module load (or hotplug insertion, 2911 * theoretically). It sets up PCI mappings, resets the NIC, 2912 * sets up and registers the network devices with the kernel and hooks 2913 * the interrupt service routine. It does not prepare the device for 2914 * transmission; this is left to the first time one of the network 2915 * interfaces is brought up (i.e. ef4_net_open). 2916 */ 2917 static int ef4_pci_probe(struct pci_dev *pci_dev, 2918 const struct pci_device_id *entry) 2919 { 2920 struct net_device *net_dev; 2921 struct ef4_nic *efx; 2922 int rc; 2923 2924 /* Allocate and initialise a struct net_device and struct ef4_nic */ 2925 net_dev = alloc_etherdev_mqs(sizeof(*efx), EF4_MAX_CORE_TX_QUEUES, 2926 EF4_MAX_RX_QUEUES); 2927 if (!net_dev) 2928 return -ENOMEM; 2929 efx = netdev_priv(net_dev); 2930 efx->type = (const struct ef4_nic_type *) entry->driver_data; 2931 efx->fixed_features |= NETIF_F_HIGHDMA; 2932 2933 pci_set_drvdata(pci_dev, efx); 2934 SET_NETDEV_DEV(net_dev, &pci_dev->dev); 2935 rc = ef4_init_struct(efx, pci_dev, net_dev); 2936 if (rc) 2937 goto fail1; 2938 2939 netif_info(efx, probe, efx->net_dev, 2940 "Solarflare NIC detected\n"); 2941 2942 ef4_probe_vpd_strings(efx); 2943 2944 /* Set up basic I/O (BAR mappings etc) */ 2945 rc = ef4_init_io(efx); 2946 if (rc) 2947 goto fail2; 2948 2949 rc = ef4_pci_probe_main(efx); 2950 if (rc) 2951 goto fail3; 2952 2953 net_dev->features |= (efx->type->offload_features | NETIF_F_SG | 2954 NETIF_F_RXCSUM); 2955 /* Mask for features that also apply to VLAN devices */ 2956 net_dev->vlan_features |= (NETIF_F_HW_CSUM | NETIF_F_SG | 2957 NETIF_F_HIGHDMA | NETIF_F_RXCSUM); 2958 2959 net_dev->hw_features = net_dev->features & ~efx->fixed_features; 2960 2961 /* Disable VLAN filtering by default. It may be enforced if 2962 * the feature is fixed (i.e. VLAN filters are required to 2963 * receive VLAN tagged packets due to vPort restrictions). 2964 */ 2965 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 2966 net_dev->features |= efx->fixed_features; 2967 2968 rc = ef4_register_netdev(efx); 2969 if (rc) 2970 goto fail4; 2971 2972 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); 2973 2974 /* Try to create MTDs, but allow this to fail */ 2975 rtnl_lock(); 2976 rc = ef4_mtd_probe(efx); 2977 rtnl_unlock(); 2978 if (rc && rc != -EPERM) 2979 netif_warn(efx, probe, efx->net_dev, 2980 "failed to create MTDs (%d)\n", rc); 2981 2982 rc = pci_enable_pcie_error_reporting(pci_dev); 2983 if (rc && rc != -EINVAL) 2984 netif_notice(efx, probe, efx->net_dev, 2985 "PCIE error reporting unavailable (%d).\n", 2986 rc); 2987 2988 return 0; 2989 2990 fail4: 2991 ef4_pci_remove_main(efx); 2992 fail3: 2993 ef4_fini_io(efx); 2994 fail2: 2995 ef4_fini_struct(efx); 2996 fail1: 2997 WARN_ON(rc > 0); 2998 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); 2999 free_netdev(net_dev); 3000 return rc; 3001 } 3002 3003 static int ef4_pm_freeze(struct device *dev) 3004 { 3005 struct ef4_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 3006 3007 rtnl_lock(); 3008 3009 if (efx->state != STATE_DISABLED) { 3010 efx->state = STATE_UNINIT; 3011 3012 ef4_device_detach_sync(efx); 3013 3014 ef4_stop_all(efx); 3015 ef4_disable_interrupts(efx); 3016 } 3017 3018 rtnl_unlock(); 3019 3020 return 0; 3021 } 3022 3023 static int ef4_pm_thaw(struct device *dev) 3024 { 3025 int rc; 3026 struct ef4_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 3027 3028 rtnl_lock(); 3029 3030 if (efx->state != STATE_DISABLED) { 3031 rc = ef4_enable_interrupts(efx); 3032 if (rc) 3033 goto fail; 3034 3035 mutex_lock(&efx->mac_lock); 3036 efx->phy_op->reconfigure(efx); 3037 mutex_unlock(&efx->mac_lock); 3038 3039 ef4_start_all(efx); 3040 3041 netif_device_attach(efx->net_dev); 3042 3043 efx->state = STATE_READY; 3044 3045 efx->type->resume_wol(efx); 3046 } 3047 3048 rtnl_unlock(); 3049 3050 /* Reschedule any quenched resets scheduled during ef4_pm_freeze() */ 3051 queue_work(reset_workqueue, &efx->reset_work); 3052 3053 return 0; 3054 3055 fail: 3056 rtnl_unlock(); 3057 3058 return rc; 3059 } 3060 3061 static int ef4_pm_poweroff(struct device *dev) 3062 { 3063 struct pci_dev *pci_dev = to_pci_dev(dev); 3064 struct ef4_nic *efx = pci_get_drvdata(pci_dev); 3065 3066 efx->type->fini(efx); 3067 3068 efx->reset_pending = 0; 3069 3070 pci_save_state(pci_dev); 3071 return pci_set_power_state(pci_dev, PCI_D3hot); 3072 } 3073 3074 /* Used for both resume and restore */ 3075 static int ef4_pm_resume(struct device *dev) 3076 { 3077 struct pci_dev *pci_dev = to_pci_dev(dev); 3078 struct ef4_nic *efx = pci_get_drvdata(pci_dev); 3079 int rc; 3080 3081 rc = pci_set_power_state(pci_dev, PCI_D0); 3082 if (rc) 3083 return rc; 3084 pci_restore_state(pci_dev); 3085 rc = pci_enable_device(pci_dev); 3086 if (rc) 3087 return rc; 3088 pci_set_master(efx->pci_dev); 3089 rc = efx->type->reset(efx, RESET_TYPE_ALL); 3090 if (rc) 3091 return rc; 3092 rc = efx->type->init(efx); 3093 if (rc) 3094 return rc; 3095 rc = ef4_pm_thaw(dev); 3096 return rc; 3097 } 3098 3099 static int ef4_pm_suspend(struct device *dev) 3100 { 3101 int rc; 3102 3103 ef4_pm_freeze(dev); 3104 rc = ef4_pm_poweroff(dev); 3105 if (rc) 3106 ef4_pm_resume(dev); 3107 return rc; 3108 } 3109 3110 static const struct dev_pm_ops ef4_pm_ops = { 3111 .suspend = ef4_pm_suspend, 3112 .resume = ef4_pm_resume, 3113 .freeze = ef4_pm_freeze, 3114 .thaw = ef4_pm_thaw, 3115 .poweroff = ef4_pm_poweroff, 3116 .restore = ef4_pm_resume, 3117 }; 3118 3119 /* A PCI error affecting this device was detected. 3120 * At this point MMIO and DMA may be disabled. 3121 * Stop the software path and request a slot reset. 3122 */ 3123 static pci_ers_result_t ef4_io_error_detected(struct pci_dev *pdev, 3124 enum pci_channel_state state) 3125 { 3126 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; 3127 struct ef4_nic *efx = pci_get_drvdata(pdev); 3128 3129 if (state == pci_channel_io_perm_failure) 3130 return PCI_ERS_RESULT_DISCONNECT; 3131 3132 rtnl_lock(); 3133 3134 if (efx->state != STATE_DISABLED) { 3135 efx->state = STATE_RECOVERY; 3136 efx->reset_pending = 0; 3137 3138 ef4_device_detach_sync(efx); 3139 3140 ef4_stop_all(efx); 3141 ef4_disable_interrupts(efx); 3142 3143 status = PCI_ERS_RESULT_NEED_RESET; 3144 } else { 3145 /* If the interface is disabled we don't want to do anything 3146 * with it. 3147 */ 3148 status = PCI_ERS_RESULT_RECOVERED; 3149 } 3150 3151 rtnl_unlock(); 3152 3153 pci_disable_device(pdev); 3154 3155 return status; 3156 } 3157 3158 /* Fake a successful reset, which will be performed later in ef4_io_resume. */ 3159 static pci_ers_result_t ef4_io_slot_reset(struct pci_dev *pdev) 3160 { 3161 struct ef4_nic *efx = pci_get_drvdata(pdev); 3162 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; 3163 3164 if (pci_enable_device(pdev)) { 3165 netif_err(efx, hw, efx->net_dev, 3166 "Cannot re-enable PCI device after reset.\n"); 3167 status = PCI_ERS_RESULT_DISCONNECT; 3168 } 3169 3170 return status; 3171 } 3172 3173 /* Perform the actual reset and resume I/O operations. */ 3174 static void ef4_io_resume(struct pci_dev *pdev) 3175 { 3176 struct ef4_nic *efx = pci_get_drvdata(pdev); 3177 int rc; 3178 3179 rtnl_lock(); 3180 3181 if (efx->state == STATE_DISABLED) 3182 goto out; 3183 3184 rc = ef4_reset(efx, RESET_TYPE_ALL); 3185 if (rc) { 3186 netif_err(efx, hw, efx->net_dev, 3187 "ef4_reset failed after PCI error (%d)\n", rc); 3188 } else { 3189 efx->state = STATE_READY; 3190 netif_dbg(efx, hw, efx->net_dev, 3191 "Done resetting and resuming IO after PCI error.\n"); 3192 } 3193 3194 out: 3195 rtnl_unlock(); 3196 } 3197 3198 /* For simplicity and reliability, we always require a slot reset and try to 3199 * reset the hardware when a pci error affecting the device is detected. 3200 * We leave both the link_reset and mmio_enabled callback unimplemented: 3201 * with our request for slot reset the mmio_enabled callback will never be 3202 * called, and the link_reset callback is not used by AER or EEH mechanisms. 3203 */ 3204 static const struct pci_error_handlers ef4_err_handlers = { 3205 .error_detected = ef4_io_error_detected, 3206 .slot_reset = ef4_io_slot_reset, 3207 .resume = ef4_io_resume, 3208 }; 3209 3210 static struct pci_driver ef4_pci_driver = { 3211 .name = KBUILD_MODNAME, 3212 .id_table = ef4_pci_table, 3213 .probe = ef4_pci_probe, 3214 .remove = ef4_pci_remove, 3215 .driver.pm = &ef4_pm_ops, 3216 .err_handler = &ef4_err_handlers, 3217 }; 3218 3219 /************************************************************************** 3220 * 3221 * Kernel module interface 3222 * 3223 *************************************************************************/ 3224 3225 module_param(interrupt_mode, uint, 0444); 3226 MODULE_PARM_DESC(interrupt_mode, 3227 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); 3228 3229 static int __init ef4_init_module(void) 3230 { 3231 int rc; 3232 3233 printk(KERN_INFO "Solarflare Falcon driver v" EF4_DRIVER_VERSION "\n"); 3234 3235 rc = register_netdevice_notifier(&ef4_netdev_notifier); 3236 if (rc) 3237 goto err_notifier; 3238 3239 reset_workqueue = create_singlethread_workqueue("sfc_reset"); 3240 if (!reset_workqueue) { 3241 rc = -ENOMEM; 3242 goto err_reset; 3243 } 3244 3245 rc = pci_register_driver(&ef4_pci_driver); 3246 if (rc < 0) 3247 goto err_pci; 3248 3249 return 0; 3250 3251 err_pci: 3252 destroy_workqueue(reset_workqueue); 3253 err_reset: 3254 unregister_netdevice_notifier(&ef4_netdev_notifier); 3255 err_notifier: 3256 return rc; 3257 } 3258 3259 static void __exit ef4_exit_module(void) 3260 { 3261 printk(KERN_INFO "Solarflare Falcon driver unloading\n"); 3262 3263 pci_unregister_driver(&ef4_pci_driver); 3264 destroy_workqueue(reset_workqueue); 3265 unregister_netdevice_notifier(&ef4_netdev_notifier); 3266 3267 } 3268 3269 module_init(ef4_init_module); 3270 module_exit(ef4_exit_module); 3271 3272 MODULE_AUTHOR("Solarflare Communications and " 3273 "Michael Brown <mbrown@fensystems.co.uk>"); 3274 MODULE_DESCRIPTION("Solarflare Falcon network driver"); 3275 MODULE_LICENSE("GPL"); 3276 MODULE_DEVICE_TABLE(pci, ef4_pci_table); 3277 MODULE_VERSION(EF4_DRIVER_VERSION); 3278