1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include "net_driver.h" 12 #include <linux/module.h> 13 #include <linux/filter.h> 14 #include "efx_channels.h" 15 #include "efx.h" 16 #include "efx_common.h" 17 #include "tx_common.h" 18 #include "rx_common.h" 19 #include "nic.h" 20 #include "sriov.h" 21 #include "workarounds.h" 22 23 /* This is the first interrupt mode to try out of: 24 * 0 => MSI-X 25 * 1 => MSI 26 * 2 => legacy 27 */ 28 unsigned int efx_interrupt_mode = EFX_INT_MODE_MSIX; 29 30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 31 * i.e. the number of CPUs among which we may distribute simultaneous 32 * interrupt handling. 33 * 34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 35 * The default (0) means to assign an interrupt to each core. 36 */ 37 unsigned int rss_cpus; 38 39 static unsigned int irq_adapt_low_thresh = 8000; 40 module_param(irq_adapt_low_thresh, uint, 0644); 41 MODULE_PARM_DESC(irq_adapt_low_thresh, 42 "Threshold score for reducing IRQ moderation"); 43 44 static unsigned int irq_adapt_high_thresh = 16000; 45 module_param(irq_adapt_high_thresh, uint, 0644); 46 MODULE_PARM_DESC(irq_adapt_high_thresh, 47 "Threshold score for increasing IRQ moderation"); 48 49 /* This is the weight assigned to each of the (per-channel) virtual 50 * NAPI devices. 51 */ 52 static int napi_weight = 64; 53 54 /*************** 55 * Housekeeping 56 ***************/ 57 58 int efx_channel_dummy_op_int(struct efx_channel *channel) 59 { 60 return 0; 61 } 62 63 void efx_channel_dummy_op_void(struct efx_channel *channel) 64 { 65 } 66 67 static const struct efx_channel_type efx_default_channel_type = { 68 .pre_probe = efx_channel_dummy_op_int, 69 .post_remove = efx_channel_dummy_op_void, 70 .get_name = efx_get_channel_name, 71 .copy = efx_copy_channel, 72 .want_txqs = efx_default_channel_want_txqs, 73 .keep_eventq = false, 74 .want_pio = true, 75 }; 76 77 /************* 78 * INTERRUPTS 79 *************/ 80 81 static unsigned int efx_wanted_parallelism(struct efx_nic *efx) 82 { 83 cpumask_var_t thread_mask; 84 unsigned int count; 85 int cpu; 86 87 if (rss_cpus) { 88 count = rss_cpus; 89 } else { 90 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { 91 netif_warn(efx, probe, efx->net_dev, 92 "RSS disabled due to allocation failure\n"); 93 return 1; 94 } 95 96 count = 0; 97 for_each_online_cpu(cpu) { 98 if (!cpumask_test_cpu(cpu, thread_mask)) { 99 ++count; 100 cpumask_or(thread_mask, thread_mask, 101 topology_sibling_cpumask(cpu)); 102 } 103 } 104 105 free_cpumask_var(thread_mask); 106 } 107 108 if (count > EFX_MAX_RX_QUEUES) { 109 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, 110 "Reducing number of rx queues from %u to %u.\n", 111 count, EFX_MAX_RX_QUEUES); 112 count = EFX_MAX_RX_QUEUES; 113 } 114 115 /* If RSS is requested for the PF *and* VFs then we can't write RSS 116 * table entries that are inaccessible to VFs 117 */ 118 #ifdef CONFIG_SFC_SRIOV 119 if (efx->type->sriov_wanted) { 120 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && 121 count > efx_vf_size(efx)) { 122 netif_warn(efx, probe, efx->net_dev, 123 "Reducing number of RSS channels from %u to %u for " 124 "VF support. Increase vf-msix-limit to use more " 125 "channels on the PF.\n", 126 count, efx_vf_size(efx)); 127 count = efx_vf_size(efx); 128 } 129 } 130 #endif 131 132 return count; 133 } 134 135 static int efx_allocate_msix_channels(struct efx_nic *efx, 136 unsigned int max_channels, 137 unsigned int extra_channels, 138 unsigned int parallelism) 139 { 140 unsigned int n_channels = parallelism; 141 int vec_count; 142 int tx_per_ev; 143 int n_xdp_tx; 144 int n_xdp_ev; 145 146 if (efx_separate_tx_channels) 147 n_channels *= 2; 148 n_channels += extra_channels; 149 150 /* To allow XDP transmit to happen from arbitrary NAPI contexts 151 * we allocate a TX queue per CPU. We share event queues across 152 * multiple tx queues, assuming tx and ev queues are both 153 * maximum size. 154 */ 155 tx_per_ev = EFX_MAX_EVQ_SIZE / EFX_TXQ_MAX_ENT(efx); 156 tx_per_ev = min(tx_per_ev, EFX_MAX_TXQ_PER_CHANNEL); 157 n_xdp_tx = num_possible_cpus(); 158 n_xdp_ev = DIV_ROUND_UP(n_xdp_tx, tx_per_ev); 159 160 vec_count = pci_msix_vec_count(efx->pci_dev); 161 if (vec_count < 0) 162 return vec_count; 163 164 max_channels = min_t(unsigned int, vec_count, max_channels); 165 166 /* Check resources. 167 * We need a channel per event queue, plus a VI per tx queue. 168 * This may be more pessimistic than it needs to be. 169 */ 170 if (n_channels >= max_channels) { 171 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; 172 netif_warn(efx, drv, efx->net_dev, 173 "Insufficient resources for %d XDP event queues (%d other channels, max %d)\n", 174 n_xdp_ev, n_channels, max_channels); 175 netif_warn(efx, drv, efx->net_dev, 176 "XDP_TX and XDP_REDIRECT might decrease device's performance\n"); 177 } else if (n_channels + n_xdp_tx > efx->max_vis) { 178 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; 179 netif_warn(efx, drv, efx->net_dev, 180 "Insufficient resources for %d XDP TX queues (%d other channels, max VIs %d)\n", 181 n_xdp_tx, n_channels, efx->max_vis); 182 netif_warn(efx, drv, efx->net_dev, 183 "XDP_TX and XDP_REDIRECT might decrease device's performance\n"); 184 } else if (n_channels + n_xdp_ev > max_channels) { 185 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_SHARED; 186 netif_warn(efx, drv, efx->net_dev, 187 "Insufficient resources for %d XDP event queues (%d other channels, max %d)\n", 188 n_xdp_ev, n_channels, max_channels); 189 190 n_xdp_ev = max_channels - n_channels; 191 netif_warn(efx, drv, efx->net_dev, 192 "XDP_TX and XDP_REDIRECT will work with reduced performance (%d cpus/tx_queue)\n", 193 DIV_ROUND_UP(n_xdp_tx, tx_per_ev * n_xdp_ev)); 194 } else { 195 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_DEDICATED; 196 } 197 198 if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_BORROWED) { 199 efx->n_xdp_channels = n_xdp_ev; 200 efx->xdp_tx_per_channel = tx_per_ev; 201 efx->xdp_tx_queue_count = n_xdp_tx; 202 n_channels += n_xdp_ev; 203 netif_dbg(efx, drv, efx->net_dev, 204 "Allocating %d TX and %d event queues for XDP\n", 205 n_xdp_ev * tx_per_ev, n_xdp_ev); 206 } else { 207 efx->n_xdp_channels = 0; 208 efx->xdp_tx_per_channel = 0; 209 efx->xdp_tx_queue_count = n_xdp_tx; 210 } 211 212 if (vec_count < n_channels) { 213 netif_err(efx, drv, efx->net_dev, 214 "WARNING: Insufficient MSI-X vectors available (%d < %u).\n", 215 vec_count, n_channels); 216 netif_err(efx, drv, efx->net_dev, 217 "WARNING: Performance may be reduced.\n"); 218 n_channels = vec_count; 219 } 220 221 n_channels = min(n_channels, max_channels); 222 223 efx->n_channels = n_channels; 224 225 /* Ignore XDP tx channels when creating rx channels. */ 226 n_channels -= efx->n_xdp_channels; 227 228 if (efx_separate_tx_channels) { 229 efx->n_tx_channels = 230 min(max(n_channels / 2, 1U), 231 efx->max_tx_channels); 232 efx->tx_channel_offset = 233 n_channels - efx->n_tx_channels; 234 efx->n_rx_channels = 235 max(n_channels - 236 efx->n_tx_channels, 1U); 237 } else { 238 efx->n_tx_channels = min(n_channels, efx->max_tx_channels); 239 efx->tx_channel_offset = 0; 240 efx->n_rx_channels = n_channels; 241 } 242 243 efx->n_rx_channels = min(efx->n_rx_channels, parallelism); 244 efx->n_tx_channels = min(efx->n_tx_channels, parallelism); 245 246 efx->xdp_channel_offset = n_channels; 247 248 netif_dbg(efx, drv, efx->net_dev, 249 "Allocating %u RX channels\n", 250 efx->n_rx_channels); 251 252 return efx->n_channels; 253 } 254 255 /* Probe the number and type of interrupts we are able to obtain, and 256 * the resulting numbers of channels and RX queues. 257 */ 258 int efx_probe_interrupts(struct efx_nic *efx) 259 { 260 unsigned int extra_channels = 0; 261 unsigned int rss_spread; 262 unsigned int i, j; 263 int rc; 264 265 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) 266 if (efx->extra_channel_type[i]) 267 ++extra_channels; 268 269 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 270 unsigned int parallelism = efx_wanted_parallelism(efx); 271 struct msix_entry xentries[EFX_MAX_CHANNELS]; 272 unsigned int n_channels; 273 274 rc = efx_allocate_msix_channels(efx, efx->max_channels, 275 extra_channels, parallelism); 276 if (rc >= 0) { 277 n_channels = rc; 278 for (i = 0; i < n_channels; i++) 279 xentries[i].entry = i; 280 rc = pci_enable_msix_range(efx->pci_dev, xentries, 1, 281 n_channels); 282 } 283 if (rc < 0) { 284 /* Fall back to single channel MSI */ 285 netif_err(efx, drv, efx->net_dev, 286 "could not enable MSI-X\n"); 287 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI) 288 efx->interrupt_mode = EFX_INT_MODE_MSI; 289 else 290 return rc; 291 } else if (rc < n_channels) { 292 netif_err(efx, drv, efx->net_dev, 293 "WARNING: Insufficient MSI-X vectors" 294 " available (%d < %u).\n", rc, n_channels); 295 netif_err(efx, drv, efx->net_dev, 296 "WARNING: Performance may be reduced.\n"); 297 n_channels = rc; 298 } 299 300 if (rc > 0) { 301 for (i = 0; i < efx->n_channels; i++) 302 efx_get_channel(efx, i)->irq = 303 xentries[i].vector; 304 } 305 } 306 307 /* Try single interrupt MSI */ 308 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { 309 efx->n_channels = 1; 310 efx->n_rx_channels = 1; 311 efx->n_tx_channels = 1; 312 efx->n_xdp_channels = 0; 313 efx->xdp_channel_offset = efx->n_channels; 314 rc = pci_enable_msi(efx->pci_dev); 315 if (rc == 0) { 316 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; 317 } else { 318 netif_err(efx, drv, efx->net_dev, 319 "could not enable MSI\n"); 320 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY) 321 efx->interrupt_mode = EFX_INT_MODE_LEGACY; 322 else 323 return rc; 324 } 325 } 326 327 /* Assume legacy interrupts */ 328 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { 329 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0); 330 efx->n_rx_channels = 1; 331 efx->n_tx_channels = 1; 332 efx->n_xdp_channels = 0; 333 efx->xdp_channel_offset = efx->n_channels; 334 efx->legacy_irq = efx->pci_dev->irq; 335 } 336 337 /* Assign extra channels if possible, before XDP channels */ 338 efx->n_extra_tx_channels = 0; 339 j = efx->xdp_channel_offset; 340 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { 341 if (!efx->extra_channel_type[i]) 342 continue; 343 if (j <= efx->tx_channel_offset + efx->n_tx_channels) { 344 efx->extra_channel_type[i]->handle_no_channel(efx); 345 } else { 346 --j; 347 efx_get_channel(efx, j)->type = 348 efx->extra_channel_type[i]; 349 if (efx_channel_has_tx_queues(efx_get_channel(efx, j))) 350 efx->n_extra_tx_channels++; 351 } 352 } 353 354 rss_spread = efx->n_rx_channels; 355 /* RSS might be usable on VFs even if it is disabled on the PF */ 356 #ifdef CONFIG_SFC_SRIOV 357 if (efx->type->sriov_wanted) { 358 efx->rss_spread = ((rss_spread > 1 || 359 !efx->type->sriov_wanted(efx)) ? 360 rss_spread : efx_vf_size(efx)); 361 return 0; 362 } 363 #endif 364 efx->rss_spread = rss_spread; 365 366 return 0; 367 } 368 369 #if defined(CONFIG_SMP) 370 void efx_set_interrupt_affinity(struct efx_nic *efx) 371 { 372 struct efx_channel *channel; 373 unsigned int cpu; 374 375 efx_for_each_channel(channel, efx) { 376 cpu = cpumask_local_spread(channel->channel, 377 pcibus_to_node(efx->pci_dev->bus)); 378 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); 379 } 380 } 381 382 void efx_clear_interrupt_affinity(struct efx_nic *efx) 383 { 384 struct efx_channel *channel; 385 386 efx_for_each_channel(channel, efx) 387 irq_set_affinity_hint(channel->irq, NULL); 388 } 389 #else 390 void 391 efx_set_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused))) 392 { 393 } 394 395 void 396 efx_clear_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused))) 397 { 398 } 399 #endif /* CONFIG_SMP */ 400 401 void efx_remove_interrupts(struct efx_nic *efx) 402 { 403 struct efx_channel *channel; 404 405 /* Remove MSI/MSI-X interrupts */ 406 efx_for_each_channel(channel, efx) 407 channel->irq = 0; 408 pci_disable_msi(efx->pci_dev); 409 pci_disable_msix(efx->pci_dev); 410 411 /* Remove legacy interrupt */ 412 efx->legacy_irq = 0; 413 } 414 415 /*************** 416 * EVENT QUEUES 417 ***************/ 418 419 /* Create event queue 420 * Event queue memory allocations are done only once. If the channel 421 * is reset, the memory buffer will be reused; this guards against 422 * errors during channel reset and also simplifies interrupt handling. 423 */ 424 int efx_probe_eventq(struct efx_channel *channel) 425 { 426 struct efx_nic *efx = channel->efx; 427 unsigned long entries; 428 429 netif_dbg(efx, probe, efx->net_dev, 430 "chan %d create event queue\n", channel->channel); 431 432 /* Build an event queue with room for one event per tx and rx buffer, 433 * plus some extra for link state events and MCDI completions. 434 */ 435 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 436 EFX_WARN_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); 437 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; 438 439 return efx_nic_probe_eventq(channel); 440 } 441 442 /* Prepare channel's event queue */ 443 int efx_init_eventq(struct efx_channel *channel) 444 { 445 struct efx_nic *efx = channel->efx; 446 int rc; 447 448 EFX_WARN_ON_PARANOID(channel->eventq_init); 449 450 netif_dbg(efx, drv, efx->net_dev, 451 "chan %d init event queue\n", channel->channel); 452 453 rc = efx_nic_init_eventq(channel); 454 if (rc == 0) { 455 efx->type->push_irq_moderation(channel); 456 channel->eventq_read_ptr = 0; 457 channel->eventq_init = true; 458 } 459 return rc; 460 } 461 462 /* Enable event queue processing and NAPI */ 463 void efx_start_eventq(struct efx_channel *channel) 464 { 465 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 466 "chan %d start event queue\n", channel->channel); 467 468 /* Make sure the NAPI handler sees the enabled flag set */ 469 channel->enabled = true; 470 smp_wmb(); 471 472 napi_enable(&channel->napi_str); 473 efx_nic_eventq_read_ack(channel); 474 } 475 476 /* Disable event queue processing and NAPI */ 477 void efx_stop_eventq(struct efx_channel *channel) 478 { 479 if (!channel->enabled) 480 return; 481 482 napi_disable(&channel->napi_str); 483 channel->enabled = false; 484 } 485 486 void efx_fini_eventq(struct efx_channel *channel) 487 { 488 if (!channel->eventq_init) 489 return; 490 491 netif_dbg(channel->efx, drv, channel->efx->net_dev, 492 "chan %d fini event queue\n", channel->channel); 493 494 efx_nic_fini_eventq(channel); 495 channel->eventq_init = false; 496 } 497 498 void efx_remove_eventq(struct efx_channel *channel) 499 { 500 netif_dbg(channel->efx, drv, channel->efx->net_dev, 501 "chan %d remove event queue\n", channel->channel); 502 503 efx_nic_remove_eventq(channel); 504 } 505 506 /************************************************************************** 507 * 508 * Channel handling 509 * 510 *************************************************************************/ 511 512 #ifdef CONFIG_RFS_ACCEL 513 static void efx_filter_rfs_expire(struct work_struct *data) 514 { 515 struct delayed_work *dwork = to_delayed_work(data); 516 struct efx_channel *channel; 517 unsigned int time, quota; 518 519 channel = container_of(dwork, struct efx_channel, filter_work); 520 time = jiffies - channel->rfs_last_expiry; 521 quota = channel->rfs_filter_count * time / (30 * HZ); 522 if (quota >= 20 && __efx_filter_rfs_expire(channel, min(channel->rfs_filter_count, quota))) 523 channel->rfs_last_expiry += time; 524 /* Ensure we do more work eventually even if NAPI poll is not happening */ 525 schedule_delayed_work(dwork, 30 * HZ); 526 } 527 #endif 528 529 /* Allocate and initialise a channel structure. */ 530 static struct efx_channel *efx_alloc_channel(struct efx_nic *efx, int i) 531 { 532 struct efx_rx_queue *rx_queue; 533 struct efx_tx_queue *tx_queue; 534 struct efx_channel *channel; 535 int j; 536 537 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 538 if (!channel) 539 return NULL; 540 541 channel->efx = efx; 542 channel->channel = i; 543 channel->type = &efx_default_channel_type; 544 545 for (j = 0; j < EFX_MAX_TXQ_PER_CHANNEL; j++) { 546 tx_queue = &channel->tx_queue[j]; 547 tx_queue->efx = efx; 548 tx_queue->queue = -1; 549 tx_queue->label = j; 550 tx_queue->channel = channel; 551 } 552 553 #ifdef CONFIG_RFS_ACCEL 554 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); 555 #endif 556 557 rx_queue = &channel->rx_queue; 558 rx_queue->efx = efx; 559 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); 560 561 return channel; 562 } 563 564 int efx_init_channels(struct efx_nic *efx) 565 { 566 unsigned int i; 567 568 for (i = 0; i < EFX_MAX_CHANNELS; i++) { 569 efx->channel[i] = efx_alloc_channel(efx, i); 570 if (!efx->channel[i]) 571 return -ENOMEM; 572 efx->msi_context[i].efx = efx; 573 efx->msi_context[i].index = i; 574 } 575 576 /* Higher numbered interrupt modes are less capable! */ 577 efx->interrupt_mode = min(efx->type->min_interrupt_mode, 578 efx_interrupt_mode); 579 580 efx->max_channels = EFX_MAX_CHANNELS; 581 efx->max_tx_channels = EFX_MAX_CHANNELS; 582 583 return 0; 584 } 585 586 void efx_fini_channels(struct efx_nic *efx) 587 { 588 unsigned int i; 589 590 for (i = 0; i < EFX_MAX_CHANNELS; i++) 591 if (efx->channel[i]) { 592 kfree(efx->channel[i]); 593 efx->channel[i] = NULL; 594 } 595 } 596 597 /* Allocate and initialise a channel structure, copying parameters 598 * (but not resources) from an old channel structure. 599 */ 600 struct efx_channel *efx_copy_channel(const struct efx_channel *old_channel) 601 { 602 struct efx_rx_queue *rx_queue; 603 struct efx_tx_queue *tx_queue; 604 struct efx_channel *channel; 605 int j; 606 607 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 608 if (!channel) 609 return NULL; 610 611 *channel = *old_channel; 612 613 channel->napi_dev = NULL; 614 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); 615 channel->napi_str.napi_id = 0; 616 channel->napi_str.state = 0; 617 memset(&channel->eventq, 0, sizeof(channel->eventq)); 618 619 for (j = 0; j < EFX_MAX_TXQ_PER_CHANNEL; j++) { 620 tx_queue = &channel->tx_queue[j]; 621 if (tx_queue->channel) 622 tx_queue->channel = channel; 623 tx_queue->buffer = NULL; 624 tx_queue->cb_page = NULL; 625 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 626 } 627 628 rx_queue = &channel->rx_queue; 629 rx_queue->buffer = NULL; 630 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 631 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); 632 #ifdef CONFIG_RFS_ACCEL 633 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); 634 #endif 635 636 return channel; 637 } 638 639 static int efx_probe_channel(struct efx_channel *channel) 640 { 641 struct efx_tx_queue *tx_queue; 642 struct efx_rx_queue *rx_queue; 643 int rc; 644 645 netif_dbg(channel->efx, probe, channel->efx->net_dev, 646 "creating channel %d\n", channel->channel); 647 648 rc = channel->type->pre_probe(channel); 649 if (rc) 650 goto fail; 651 652 rc = efx_probe_eventq(channel); 653 if (rc) 654 goto fail; 655 656 efx_for_each_channel_tx_queue(tx_queue, channel) { 657 rc = efx_probe_tx_queue(tx_queue); 658 if (rc) 659 goto fail; 660 } 661 662 efx_for_each_channel_rx_queue(rx_queue, channel) { 663 rc = efx_probe_rx_queue(rx_queue); 664 if (rc) 665 goto fail; 666 } 667 668 channel->rx_list = NULL; 669 670 return 0; 671 672 fail: 673 efx_remove_channel(channel); 674 return rc; 675 } 676 677 void efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) 678 { 679 struct efx_nic *efx = channel->efx; 680 const char *type; 681 int number; 682 683 number = channel->channel; 684 685 if (number >= efx->xdp_channel_offset && 686 !WARN_ON_ONCE(!efx->n_xdp_channels)) { 687 type = "-xdp"; 688 number -= efx->xdp_channel_offset; 689 } else if (efx->tx_channel_offset == 0) { 690 type = ""; 691 } else if (number < efx->tx_channel_offset) { 692 type = "-rx"; 693 } else { 694 type = "-tx"; 695 number -= efx->tx_channel_offset; 696 } 697 snprintf(buf, len, "%s%s-%d", efx->name, type, number); 698 } 699 700 void efx_set_channel_names(struct efx_nic *efx) 701 { 702 struct efx_channel *channel; 703 704 efx_for_each_channel(channel, efx) 705 channel->type->get_name(channel, 706 efx->msi_context[channel->channel].name, 707 sizeof(efx->msi_context[0].name)); 708 } 709 710 int efx_probe_channels(struct efx_nic *efx) 711 { 712 struct efx_channel *channel; 713 int rc; 714 715 /* Restart special buffer allocation */ 716 efx->next_buffer_table = 0; 717 718 /* Probe channels in reverse, so that any 'extra' channels 719 * use the start of the buffer table. This allows the traffic 720 * channels to be resized without moving them or wasting the 721 * entries before them. 722 */ 723 efx_for_each_channel_rev(channel, efx) { 724 rc = efx_probe_channel(channel); 725 if (rc) { 726 netif_err(efx, probe, efx->net_dev, 727 "failed to create channel %d\n", 728 channel->channel); 729 goto fail; 730 } 731 } 732 efx_set_channel_names(efx); 733 734 return 0; 735 736 fail: 737 efx_remove_channels(efx); 738 return rc; 739 } 740 741 void efx_remove_channel(struct efx_channel *channel) 742 { 743 struct efx_tx_queue *tx_queue; 744 struct efx_rx_queue *rx_queue; 745 746 netif_dbg(channel->efx, drv, channel->efx->net_dev, 747 "destroy chan %d\n", channel->channel); 748 749 efx_for_each_channel_rx_queue(rx_queue, channel) 750 efx_remove_rx_queue(rx_queue); 751 efx_for_each_channel_tx_queue(tx_queue, channel) 752 efx_remove_tx_queue(tx_queue); 753 efx_remove_eventq(channel); 754 channel->type->post_remove(channel); 755 } 756 757 void efx_remove_channels(struct efx_nic *efx) 758 { 759 struct efx_channel *channel; 760 761 efx_for_each_channel(channel, efx) 762 efx_remove_channel(channel); 763 764 kfree(efx->xdp_tx_queues); 765 } 766 767 int efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) 768 { 769 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; 770 unsigned int i, next_buffer_table = 0; 771 u32 old_rxq_entries, old_txq_entries; 772 int rc, rc2; 773 774 rc = efx_check_disabled(efx); 775 if (rc) 776 return rc; 777 778 /* Not all channels should be reallocated. We must avoid 779 * reallocating their buffer table entries. 780 */ 781 efx_for_each_channel(channel, efx) { 782 struct efx_rx_queue *rx_queue; 783 struct efx_tx_queue *tx_queue; 784 785 if (channel->type->copy) 786 continue; 787 next_buffer_table = max(next_buffer_table, 788 channel->eventq.index + 789 channel->eventq.entries); 790 efx_for_each_channel_rx_queue(rx_queue, channel) 791 next_buffer_table = max(next_buffer_table, 792 rx_queue->rxd.index + 793 rx_queue->rxd.entries); 794 efx_for_each_channel_tx_queue(tx_queue, channel) 795 next_buffer_table = max(next_buffer_table, 796 tx_queue->txd.index + 797 tx_queue->txd.entries); 798 } 799 800 efx_device_detach_sync(efx); 801 efx_stop_all(efx); 802 efx_soft_disable_interrupts(efx); 803 804 /* Clone channels (where possible) */ 805 memset(other_channel, 0, sizeof(other_channel)); 806 for (i = 0; i < efx->n_channels; i++) { 807 channel = efx->channel[i]; 808 if (channel->type->copy) 809 channel = channel->type->copy(channel); 810 if (!channel) { 811 rc = -ENOMEM; 812 goto out; 813 } 814 other_channel[i] = channel; 815 } 816 817 /* Swap entry counts and channel pointers */ 818 old_rxq_entries = efx->rxq_entries; 819 old_txq_entries = efx->txq_entries; 820 efx->rxq_entries = rxq_entries; 821 efx->txq_entries = txq_entries; 822 for (i = 0; i < efx->n_channels; i++) 823 swap(efx->channel[i], other_channel[i]); 824 825 /* Restart buffer table allocation */ 826 efx->next_buffer_table = next_buffer_table; 827 828 for (i = 0; i < efx->n_channels; i++) { 829 channel = efx->channel[i]; 830 if (!channel->type->copy) 831 continue; 832 rc = efx_probe_channel(channel); 833 if (rc) 834 goto rollback; 835 efx_init_napi_channel(efx->channel[i]); 836 } 837 838 out: 839 /* Destroy unused channel structures */ 840 for (i = 0; i < efx->n_channels; i++) { 841 channel = other_channel[i]; 842 if (channel && channel->type->copy) { 843 efx_fini_napi_channel(channel); 844 efx_remove_channel(channel); 845 kfree(channel); 846 } 847 } 848 849 rc2 = efx_soft_enable_interrupts(efx); 850 if (rc2) { 851 rc = rc ? rc : rc2; 852 netif_err(efx, drv, efx->net_dev, 853 "unable to restart interrupts on channel reallocation\n"); 854 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 855 } else { 856 efx_start_all(efx); 857 efx_device_attach_if_not_resetting(efx); 858 } 859 return rc; 860 861 rollback: 862 /* Swap back */ 863 efx->rxq_entries = old_rxq_entries; 864 efx->txq_entries = old_txq_entries; 865 for (i = 0; i < efx->n_channels; i++) 866 swap(efx->channel[i], other_channel[i]); 867 goto out; 868 } 869 870 static inline int 871 efx_set_xdp_tx_queue(struct efx_nic *efx, int xdp_queue_number, 872 struct efx_tx_queue *tx_queue) 873 { 874 if (xdp_queue_number >= efx->xdp_tx_queue_count) 875 return -EINVAL; 876 877 netif_dbg(efx, drv, efx->net_dev, "Channel %u TXQ %u is XDP %u, HW %u\n", 878 tx_queue->channel->channel, tx_queue->label, 879 xdp_queue_number, tx_queue->queue); 880 efx->xdp_tx_queues[xdp_queue_number] = tx_queue; 881 return 0; 882 } 883 884 int efx_set_channels(struct efx_nic *efx) 885 { 886 struct efx_tx_queue *tx_queue; 887 struct efx_channel *channel; 888 unsigned int next_queue = 0; 889 int xdp_queue_number; 890 int rc; 891 892 efx->tx_channel_offset = 893 efx_separate_tx_channels ? 894 efx->n_channels - efx->n_tx_channels : 0; 895 896 if (efx->xdp_tx_queue_count) { 897 EFX_WARN_ON_PARANOID(efx->xdp_tx_queues); 898 899 /* Allocate array for XDP TX queue lookup. */ 900 efx->xdp_tx_queues = kcalloc(efx->xdp_tx_queue_count, 901 sizeof(*efx->xdp_tx_queues), 902 GFP_KERNEL); 903 if (!efx->xdp_tx_queues) 904 return -ENOMEM; 905 } 906 907 /* We need to mark which channels really have RX and TX 908 * queues, and adjust the TX queue numbers if we have separate 909 * RX-only and TX-only channels. 910 */ 911 xdp_queue_number = 0; 912 efx_for_each_channel(channel, efx) { 913 if (channel->channel < efx->n_rx_channels) 914 channel->rx_queue.core_index = channel->channel; 915 else 916 channel->rx_queue.core_index = -1; 917 918 if (channel->channel >= efx->tx_channel_offset) { 919 if (efx_channel_is_xdp_tx(channel)) { 920 efx_for_each_channel_tx_queue(tx_queue, channel) { 921 tx_queue->queue = next_queue++; 922 rc = efx_set_xdp_tx_queue(efx, xdp_queue_number, tx_queue); 923 if (rc == 0) 924 xdp_queue_number++; 925 } 926 } else { 927 efx_for_each_channel_tx_queue(tx_queue, channel) { 928 tx_queue->queue = next_queue++; 929 netif_dbg(efx, drv, efx->net_dev, "Channel %u TXQ %u is HW %u\n", 930 channel->channel, tx_queue->label, 931 tx_queue->queue); 932 } 933 934 /* If XDP is borrowing queues from net stack, it must use the queue 935 * with no csum offload, which is the first one of the channel 936 * (note: channel->tx_queue_by_type is not initialized yet) 937 */ 938 if (efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_BORROWED) { 939 tx_queue = &channel->tx_queue[0]; 940 rc = efx_set_xdp_tx_queue(efx, xdp_queue_number, tx_queue); 941 if (rc == 0) 942 xdp_queue_number++; 943 } 944 } 945 } 946 } 947 WARN_ON(efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_DEDICATED && 948 xdp_queue_number != efx->xdp_tx_queue_count); 949 WARN_ON(efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED && 950 xdp_queue_number > efx->xdp_tx_queue_count); 951 952 /* If we have more CPUs than assigned XDP TX queues, assign the already 953 * existing queues to the exceeding CPUs 954 */ 955 next_queue = 0; 956 while (xdp_queue_number < efx->xdp_tx_queue_count) { 957 tx_queue = efx->xdp_tx_queues[next_queue++]; 958 rc = efx_set_xdp_tx_queue(efx, xdp_queue_number, tx_queue); 959 if (rc == 0) 960 xdp_queue_number++; 961 } 962 963 rc = netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); 964 if (rc) 965 return rc; 966 return netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); 967 } 968 969 bool efx_default_channel_want_txqs(struct efx_channel *channel) 970 { 971 return channel->channel - channel->efx->tx_channel_offset < 972 channel->efx->n_tx_channels; 973 } 974 975 /************* 976 * START/STOP 977 *************/ 978 979 int efx_soft_enable_interrupts(struct efx_nic *efx) 980 { 981 struct efx_channel *channel, *end_channel; 982 int rc; 983 984 BUG_ON(efx->state == STATE_DISABLED); 985 986 efx->irq_soft_enabled = true; 987 smp_wmb(); 988 989 efx_for_each_channel(channel, efx) { 990 if (!channel->type->keep_eventq) { 991 rc = efx_init_eventq(channel); 992 if (rc) 993 goto fail; 994 } 995 efx_start_eventq(channel); 996 } 997 998 efx_mcdi_mode_event(efx); 999 1000 return 0; 1001 fail: 1002 end_channel = channel; 1003 efx_for_each_channel(channel, efx) { 1004 if (channel == end_channel) 1005 break; 1006 efx_stop_eventq(channel); 1007 if (!channel->type->keep_eventq) 1008 efx_fini_eventq(channel); 1009 } 1010 1011 return rc; 1012 } 1013 1014 void efx_soft_disable_interrupts(struct efx_nic *efx) 1015 { 1016 struct efx_channel *channel; 1017 1018 if (efx->state == STATE_DISABLED) 1019 return; 1020 1021 efx_mcdi_mode_poll(efx); 1022 1023 efx->irq_soft_enabled = false; 1024 smp_wmb(); 1025 1026 if (efx->legacy_irq) 1027 synchronize_irq(efx->legacy_irq); 1028 1029 efx_for_each_channel(channel, efx) { 1030 if (channel->irq) 1031 synchronize_irq(channel->irq); 1032 1033 efx_stop_eventq(channel); 1034 if (!channel->type->keep_eventq) 1035 efx_fini_eventq(channel); 1036 } 1037 1038 /* Flush the asynchronous MCDI request queue */ 1039 efx_mcdi_flush_async(efx); 1040 } 1041 1042 int efx_enable_interrupts(struct efx_nic *efx) 1043 { 1044 struct efx_channel *channel, *end_channel; 1045 int rc; 1046 1047 /* TODO: Is this really a bug? */ 1048 BUG_ON(efx->state == STATE_DISABLED); 1049 1050 if (efx->eeh_disabled_legacy_irq) { 1051 enable_irq(efx->legacy_irq); 1052 efx->eeh_disabled_legacy_irq = false; 1053 } 1054 1055 efx->type->irq_enable_master(efx); 1056 1057 efx_for_each_channel(channel, efx) { 1058 if (channel->type->keep_eventq) { 1059 rc = efx_init_eventq(channel); 1060 if (rc) 1061 goto fail; 1062 } 1063 } 1064 1065 rc = efx_soft_enable_interrupts(efx); 1066 if (rc) 1067 goto fail; 1068 1069 return 0; 1070 1071 fail: 1072 end_channel = channel; 1073 efx_for_each_channel(channel, efx) { 1074 if (channel == end_channel) 1075 break; 1076 if (channel->type->keep_eventq) 1077 efx_fini_eventq(channel); 1078 } 1079 1080 efx->type->irq_disable_non_ev(efx); 1081 1082 return rc; 1083 } 1084 1085 void efx_disable_interrupts(struct efx_nic *efx) 1086 { 1087 struct efx_channel *channel; 1088 1089 efx_soft_disable_interrupts(efx); 1090 1091 efx_for_each_channel(channel, efx) { 1092 if (channel->type->keep_eventq) 1093 efx_fini_eventq(channel); 1094 } 1095 1096 efx->type->irq_disable_non_ev(efx); 1097 } 1098 1099 void efx_start_channels(struct efx_nic *efx) 1100 { 1101 struct efx_tx_queue *tx_queue; 1102 struct efx_rx_queue *rx_queue; 1103 struct efx_channel *channel; 1104 1105 efx_for_each_channel(channel, efx) { 1106 efx_for_each_channel_tx_queue(tx_queue, channel) { 1107 efx_init_tx_queue(tx_queue); 1108 atomic_inc(&efx->active_queues); 1109 } 1110 1111 efx_for_each_channel_rx_queue(rx_queue, channel) { 1112 efx_init_rx_queue(rx_queue); 1113 atomic_inc(&efx->active_queues); 1114 efx_stop_eventq(channel); 1115 efx_fast_push_rx_descriptors(rx_queue, false); 1116 efx_start_eventq(channel); 1117 } 1118 1119 WARN_ON(channel->rx_pkt_n_frags); 1120 } 1121 } 1122 1123 void efx_stop_channels(struct efx_nic *efx) 1124 { 1125 struct efx_tx_queue *tx_queue; 1126 struct efx_rx_queue *rx_queue; 1127 struct efx_channel *channel; 1128 int rc = 0; 1129 1130 /* Stop RX refill */ 1131 efx_for_each_channel(channel, efx) { 1132 efx_for_each_channel_rx_queue(rx_queue, channel) 1133 rx_queue->refill_enabled = false; 1134 } 1135 1136 efx_for_each_channel(channel, efx) { 1137 /* RX packet processing is pipelined, so wait for the 1138 * NAPI handler to complete. At least event queue 0 1139 * might be kept active by non-data events, so don't 1140 * use napi_synchronize() but actually disable NAPI 1141 * temporarily. 1142 */ 1143 if (efx_channel_has_rx_queue(channel)) { 1144 efx_stop_eventq(channel); 1145 efx_start_eventq(channel); 1146 } 1147 } 1148 1149 if (efx->type->fini_dmaq) 1150 rc = efx->type->fini_dmaq(efx); 1151 1152 if (rc) { 1153 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 1154 } else { 1155 netif_dbg(efx, drv, efx->net_dev, 1156 "successfully flushed all queues\n"); 1157 } 1158 1159 efx_for_each_channel(channel, efx) { 1160 efx_for_each_channel_rx_queue(rx_queue, channel) 1161 efx_fini_rx_queue(rx_queue); 1162 efx_for_each_channel_tx_queue(tx_queue, channel) 1163 efx_fini_tx_queue(tx_queue); 1164 } 1165 } 1166 1167 /************************************************************************** 1168 * 1169 * NAPI interface 1170 * 1171 *************************************************************************/ 1172 1173 /* Process channel's event queue 1174 * 1175 * This function is responsible for processing the event queue of a 1176 * single channel. The caller must guarantee that this function will 1177 * never be concurrently called more than once on the same channel, 1178 * though different channels may be being processed concurrently. 1179 */ 1180 static int efx_process_channel(struct efx_channel *channel, int budget) 1181 { 1182 struct efx_tx_queue *tx_queue; 1183 struct list_head rx_list; 1184 int spent; 1185 1186 if (unlikely(!channel->enabled)) 1187 return 0; 1188 1189 /* Prepare the batch receive list */ 1190 EFX_WARN_ON_PARANOID(channel->rx_list != NULL); 1191 INIT_LIST_HEAD(&rx_list); 1192 channel->rx_list = &rx_list; 1193 1194 efx_for_each_channel_tx_queue(tx_queue, channel) { 1195 tx_queue->pkts_compl = 0; 1196 tx_queue->bytes_compl = 0; 1197 } 1198 1199 spent = efx_nic_process_eventq(channel, budget); 1200 if (spent && efx_channel_has_rx_queue(channel)) { 1201 struct efx_rx_queue *rx_queue = 1202 efx_channel_get_rx_queue(channel); 1203 1204 efx_rx_flush_packet(channel); 1205 efx_fast_push_rx_descriptors(rx_queue, true); 1206 } 1207 1208 /* Update BQL */ 1209 efx_for_each_channel_tx_queue(tx_queue, channel) { 1210 if (tx_queue->bytes_compl) { 1211 netdev_tx_completed_queue(tx_queue->core_txq, 1212 tx_queue->pkts_compl, 1213 tx_queue->bytes_compl); 1214 } 1215 } 1216 1217 /* Receive any packets we queued up */ 1218 netif_receive_skb_list(channel->rx_list); 1219 channel->rx_list = NULL; 1220 1221 return spent; 1222 } 1223 1224 static void efx_update_irq_mod(struct efx_nic *efx, struct efx_channel *channel) 1225 { 1226 int step = efx->irq_mod_step_us; 1227 1228 if (channel->irq_mod_score < irq_adapt_low_thresh) { 1229 if (channel->irq_moderation_us > step) { 1230 channel->irq_moderation_us -= step; 1231 efx->type->push_irq_moderation(channel); 1232 } 1233 } else if (channel->irq_mod_score > irq_adapt_high_thresh) { 1234 if (channel->irq_moderation_us < 1235 efx->irq_rx_moderation_us) { 1236 channel->irq_moderation_us += step; 1237 efx->type->push_irq_moderation(channel); 1238 } 1239 } 1240 1241 channel->irq_count = 0; 1242 channel->irq_mod_score = 0; 1243 } 1244 1245 /* NAPI poll handler 1246 * 1247 * NAPI guarantees serialisation of polls of the same device, which 1248 * provides the guarantee required by efx_process_channel(). 1249 */ 1250 static int efx_poll(struct napi_struct *napi, int budget) 1251 { 1252 struct efx_channel *channel = 1253 container_of(napi, struct efx_channel, napi_str); 1254 struct efx_nic *efx = channel->efx; 1255 #ifdef CONFIG_RFS_ACCEL 1256 unsigned int time; 1257 #endif 1258 int spent; 1259 1260 netif_vdbg(efx, intr, efx->net_dev, 1261 "channel %d NAPI poll executing on CPU %d\n", 1262 channel->channel, raw_smp_processor_id()); 1263 1264 spent = efx_process_channel(channel, budget); 1265 1266 xdp_do_flush_map(); 1267 1268 if (spent < budget) { 1269 if (efx_channel_has_rx_queue(channel) && 1270 efx->irq_rx_adaptive && 1271 unlikely(++channel->irq_count == 1000)) { 1272 efx_update_irq_mod(efx, channel); 1273 } 1274 1275 #ifdef CONFIG_RFS_ACCEL 1276 /* Perhaps expire some ARFS filters */ 1277 time = jiffies - channel->rfs_last_expiry; 1278 /* Would our quota be >= 20? */ 1279 if (channel->rfs_filter_count * time >= 600 * HZ) 1280 mod_delayed_work(system_wq, &channel->filter_work, 0); 1281 #endif 1282 1283 /* There is no race here; although napi_disable() will 1284 * only wait for napi_complete(), this isn't a problem 1285 * since efx_nic_eventq_read_ack() will have no effect if 1286 * interrupts have already been disabled. 1287 */ 1288 if (napi_complete_done(napi, spent)) 1289 efx_nic_eventq_read_ack(channel); 1290 } 1291 1292 return spent; 1293 } 1294 1295 void efx_init_napi_channel(struct efx_channel *channel) 1296 { 1297 struct efx_nic *efx = channel->efx; 1298 1299 channel->napi_dev = efx->net_dev; 1300 netif_napi_add(channel->napi_dev, &channel->napi_str, 1301 efx_poll, napi_weight); 1302 } 1303 1304 void efx_init_napi(struct efx_nic *efx) 1305 { 1306 struct efx_channel *channel; 1307 1308 efx_for_each_channel(channel, efx) 1309 efx_init_napi_channel(channel); 1310 } 1311 1312 void efx_fini_napi_channel(struct efx_channel *channel) 1313 { 1314 if (channel->napi_dev) 1315 netif_napi_del(&channel->napi_str); 1316 1317 channel->napi_dev = NULL; 1318 } 1319 1320 void efx_fini_napi(struct efx_nic *efx) 1321 { 1322 struct efx_channel *channel; 1323 1324 efx_for_each_channel(channel, efx) 1325 efx_fini_napi_channel(channel); 1326 } 1327