1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include "net_driver.h" 12 #include <linux/module.h> 13 #include <linux/filter.h> 14 #include "efx_channels.h" 15 #include "efx.h" 16 #include "efx_common.h" 17 #include "tx_common.h" 18 #include "rx_common.h" 19 #include "nic.h" 20 #include "sriov.h" 21 #include "workarounds.h" 22 23 /* This is the first interrupt mode to try out of: 24 * 0 => MSI-X 25 * 1 => MSI 26 * 2 => legacy 27 */ 28 unsigned int efx_interrupt_mode = EFX_INT_MODE_MSIX; 29 30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 31 * i.e. the number of CPUs among which we may distribute simultaneous 32 * interrupt handling. 33 * 34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 35 * The default (0) means to assign an interrupt to each core. 36 */ 37 unsigned int rss_cpus; 38 39 static unsigned int irq_adapt_low_thresh = 8000; 40 module_param(irq_adapt_low_thresh, uint, 0644); 41 MODULE_PARM_DESC(irq_adapt_low_thresh, 42 "Threshold score for reducing IRQ moderation"); 43 44 static unsigned int irq_adapt_high_thresh = 16000; 45 module_param(irq_adapt_high_thresh, uint, 0644); 46 MODULE_PARM_DESC(irq_adapt_high_thresh, 47 "Threshold score for increasing IRQ moderation"); 48 49 /* This is the weight assigned to each of the (per-channel) virtual 50 * NAPI devices. 51 */ 52 static int napi_weight = 64; 53 54 /*************** 55 * Housekeeping 56 ***************/ 57 58 int efx_channel_dummy_op_int(struct efx_channel *channel) 59 { 60 return 0; 61 } 62 63 void efx_channel_dummy_op_void(struct efx_channel *channel) 64 { 65 } 66 67 static const struct efx_channel_type efx_default_channel_type = { 68 .pre_probe = efx_channel_dummy_op_int, 69 .post_remove = efx_channel_dummy_op_void, 70 .get_name = efx_get_channel_name, 71 .copy = efx_copy_channel, 72 .want_txqs = efx_default_channel_want_txqs, 73 .keep_eventq = false, 74 .want_pio = true, 75 }; 76 77 /************* 78 * INTERRUPTS 79 *************/ 80 81 static unsigned int count_online_cores(struct efx_nic *efx, bool local_node) 82 { 83 cpumask_var_t filter_mask; 84 unsigned int count; 85 int cpu; 86 87 if (unlikely(!zalloc_cpumask_var(&filter_mask, GFP_KERNEL))) { 88 netif_warn(efx, probe, efx->net_dev, 89 "RSS disabled due to allocation failure\n"); 90 return 1; 91 } 92 93 cpumask_copy(filter_mask, cpu_online_mask); 94 if (local_node) 95 cpumask_and(filter_mask, filter_mask, 96 cpumask_of_pcibus(efx->pci_dev->bus)); 97 98 count = 0; 99 for_each_cpu(cpu, filter_mask) { 100 ++count; 101 cpumask_andnot(filter_mask, filter_mask, topology_sibling_cpumask(cpu)); 102 } 103 104 free_cpumask_var(filter_mask); 105 106 return count; 107 } 108 109 static unsigned int efx_wanted_parallelism(struct efx_nic *efx) 110 { 111 unsigned int count; 112 113 if (rss_cpus) { 114 count = rss_cpus; 115 } else { 116 count = count_online_cores(efx, true); 117 118 /* If no online CPUs in local node, fallback to any online CPUs */ 119 if (count == 0) 120 count = count_online_cores(efx, false); 121 } 122 123 if (count > EFX_MAX_RX_QUEUES) { 124 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, 125 "Reducing number of rx queues from %u to %u.\n", 126 count, EFX_MAX_RX_QUEUES); 127 count = EFX_MAX_RX_QUEUES; 128 } 129 130 /* If RSS is requested for the PF *and* VFs then we can't write RSS 131 * table entries that are inaccessible to VFs 132 */ 133 #ifdef CONFIG_SFC_SRIOV 134 if (efx->type->sriov_wanted) { 135 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && 136 count > efx_vf_size(efx)) { 137 netif_warn(efx, probe, efx->net_dev, 138 "Reducing number of RSS channels from %u to %u for " 139 "VF support. Increase vf-msix-limit to use more " 140 "channels on the PF.\n", 141 count, efx_vf_size(efx)); 142 count = efx_vf_size(efx); 143 } 144 } 145 #endif 146 147 return count; 148 } 149 150 static int efx_allocate_msix_channels(struct efx_nic *efx, 151 unsigned int max_channels, 152 unsigned int extra_channels, 153 unsigned int parallelism) 154 { 155 unsigned int n_channels = parallelism; 156 int vec_count; 157 int tx_per_ev; 158 int n_xdp_tx; 159 int n_xdp_ev; 160 161 if (efx_separate_tx_channels) 162 n_channels *= 2; 163 n_channels += extra_channels; 164 165 /* To allow XDP transmit to happen from arbitrary NAPI contexts 166 * we allocate a TX queue per CPU. We share event queues across 167 * multiple tx queues, assuming tx and ev queues are both 168 * maximum size. 169 */ 170 tx_per_ev = EFX_MAX_EVQ_SIZE / EFX_TXQ_MAX_ENT(efx); 171 tx_per_ev = min(tx_per_ev, EFX_MAX_TXQ_PER_CHANNEL); 172 n_xdp_tx = num_possible_cpus(); 173 n_xdp_ev = DIV_ROUND_UP(n_xdp_tx, tx_per_ev); 174 175 vec_count = pci_msix_vec_count(efx->pci_dev); 176 if (vec_count < 0) 177 return vec_count; 178 179 max_channels = min_t(unsigned int, vec_count, max_channels); 180 181 /* Check resources. 182 * We need a channel per event queue, plus a VI per tx queue. 183 * This may be more pessimistic than it needs to be. 184 */ 185 if (n_channels >= max_channels) { 186 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; 187 netif_warn(efx, drv, efx->net_dev, 188 "Insufficient resources for %d XDP event queues (%d other channels, max %d)\n", 189 n_xdp_ev, n_channels, max_channels); 190 netif_warn(efx, drv, efx->net_dev, 191 "XDP_TX and XDP_REDIRECT might decrease device's performance\n"); 192 } else if (n_channels + n_xdp_tx > efx->max_vis) { 193 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; 194 netif_warn(efx, drv, efx->net_dev, 195 "Insufficient resources for %d XDP TX queues (%d other channels, max VIs %d)\n", 196 n_xdp_tx, n_channels, efx->max_vis); 197 netif_warn(efx, drv, efx->net_dev, 198 "XDP_TX and XDP_REDIRECT might decrease device's performance\n"); 199 } else if (n_channels + n_xdp_ev > max_channels) { 200 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_SHARED; 201 netif_warn(efx, drv, efx->net_dev, 202 "Insufficient resources for %d XDP event queues (%d other channels, max %d)\n", 203 n_xdp_ev, n_channels, max_channels); 204 205 n_xdp_ev = max_channels - n_channels; 206 netif_warn(efx, drv, efx->net_dev, 207 "XDP_TX and XDP_REDIRECT will work with reduced performance (%d cpus/tx_queue)\n", 208 DIV_ROUND_UP(n_xdp_tx, tx_per_ev * n_xdp_ev)); 209 } else { 210 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_DEDICATED; 211 } 212 213 if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_BORROWED) { 214 efx->n_xdp_channels = n_xdp_ev; 215 efx->xdp_tx_per_channel = tx_per_ev; 216 efx->xdp_tx_queue_count = n_xdp_tx; 217 n_channels += n_xdp_ev; 218 netif_dbg(efx, drv, efx->net_dev, 219 "Allocating %d TX and %d event queues for XDP\n", 220 n_xdp_ev * tx_per_ev, n_xdp_ev); 221 } else { 222 efx->n_xdp_channels = 0; 223 efx->xdp_tx_per_channel = 0; 224 efx->xdp_tx_queue_count = n_xdp_tx; 225 } 226 227 if (vec_count < n_channels) { 228 netif_err(efx, drv, efx->net_dev, 229 "WARNING: Insufficient MSI-X vectors available (%d < %u).\n", 230 vec_count, n_channels); 231 netif_err(efx, drv, efx->net_dev, 232 "WARNING: Performance may be reduced.\n"); 233 n_channels = vec_count; 234 } 235 236 n_channels = min(n_channels, max_channels); 237 238 efx->n_channels = n_channels; 239 240 /* Ignore XDP tx channels when creating rx channels. */ 241 n_channels -= efx->n_xdp_channels; 242 243 if (efx_separate_tx_channels) { 244 efx->n_tx_channels = 245 min(max(n_channels / 2, 1U), 246 efx->max_tx_channels); 247 efx->tx_channel_offset = 248 n_channels - efx->n_tx_channels; 249 efx->n_rx_channels = 250 max(n_channels - 251 efx->n_tx_channels, 1U); 252 } else { 253 efx->n_tx_channels = min(n_channels, efx->max_tx_channels); 254 efx->tx_channel_offset = 0; 255 efx->n_rx_channels = n_channels; 256 } 257 258 efx->n_rx_channels = min(efx->n_rx_channels, parallelism); 259 efx->n_tx_channels = min(efx->n_tx_channels, parallelism); 260 261 efx->xdp_channel_offset = n_channels; 262 263 netif_dbg(efx, drv, efx->net_dev, 264 "Allocating %u RX channels\n", 265 efx->n_rx_channels); 266 267 return efx->n_channels; 268 } 269 270 /* Probe the number and type of interrupts we are able to obtain, and 271 * the resulting numbers of channels and RX queues. 272 */ 273 int efx_probe_interrupts(struct efx_nic *efx) 274 { 275 unsigned int extra_channels = 0; 276 unsigned int rss_spread; 277 unsigned int i, j; 278 int rc; 279 280 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) 281 if (efx->extra_channel_type[i]) 282 ++extra_channels; 283 284 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 285 unsigned int parallelism = efx_wanted_parallelism(efx); 286 struct msix_entry xentries[EFX_MAX_CHANNELS]; 287 unsigned int n_channels; 288 289 rc = efx_allocate_msix_channels(efx, efx->max_channels, 290 extra_channels, parallelism); 291 if (rc >= 0) { 292 n_channels = rc; 293 for (i = 0; i < n_channels; i++) 294 xentries[i].entry = i; 295 rc = pci_enable_msix_range(efx->pci_dev, xentries, 1, 296 n_channels); 297 } 298 if (rc < 0) { 299 /* Fall back to single channel MSI */ 300 netif_err(efx, drv, efx->net_dev, 301 "could not enable MSI-X\n"); 302 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI) 303 efx->interrupt_mode = EFX_INT_MODE_MSI; 304 else 305 return rc; 306 } else if (rc < n_channels) { 307 netif_err(efx, drv, efx->net_dev, 308 "WARNING: Insufficient MSI-X vectors" 309 " available (%d < %u).\n", rc, n_channels); 310 netif_err(efx, drv, efx->net_dev, 311 "WARNING: Performance may be reduced.\n"); 312 n_channels = rc; 313 } 314 315 if (rc > 0) { 316 for (i = 0; i < efx->n_channels; i++) 317 efx_get_channel(efx, i)->irq = 318 xentries[i].vector; 319 } 320 } 321 322 /* Try single interrupt MSI */ 323 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { 324 efx->n_channels = 1; 325 efx->n_rx_channels = 1; 326 efx->n_tx_channels = 1; 327 efx->n_xdp_channels = 0; 328 efx->xdp_channel_offset = efx->n_channels; 329 rc = pci_enable_msi(efx->pci_dev); 330 if (rc == 0) { 331 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; 332 } else { 333 netif_err(efx, drv, efx->net_dev, 334 "could not enable MSI\n"); 335 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY) 336 efx->interrupt_mode = EFX_INT_MODE_LEGACY; 337 else 338 return rc; 339 } 340 } 341 342 /* Assume legacy interrupts */ 343 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { 344 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0); 345 efx->n_rx_channels = 1; 346 efx->n_tx_channels = 1; 347 efx->n_xdp_channels = 0; 348 efx->xdp_channel_offset = efx->n_channels; 349 efx->legacy_irq = efx->pci_dev->irq; 350 } 351 352 /* Assign extra channels if possible, before XDP channels */ 353 efx->n_extra_tx_channels = 0; 354 j = efx->xdp_channel_offset; 355 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { 356 if (!efx->extra_channel_type[i]) 357 continue; 358 if (j <= efx->tx_channel_offset + efx->n_tx_channels) { 359 efx->extra_channel_type[i]->handle_no_channel(efx); 360 } else { 361 --j; 362 efx_get_channel(efx, j)->type = 363 efx->extra_channel_type[i]; 364 if (efx_channel_has_tx_queues(efx_get_channel(efx, j))) 365 efx->n_extra_tx_channels++; 366 } 367 } 368 369 rss_spread = efx->n_rx_channels; 370 /* RSS might be usable on VFs even if it is disabled on the PF */ 371 #ifdef CONFIG_SFC_SRIOV 372 if (efx->type->sriov_wanted) { 373 efx->rss_spread = ((rss_spread > 1 || 374 !efx->type->sriov_wanted(efx)) ? 375 rss_spread : efx_vf_size(efx)); 376 return 0; 377 } 378 #endif 379 efx->rss_spread = rss_spread; 380 381 return 0; 382 } 383 384 #if defined(CONFIG_SMP) 385 void efx_set_interrupt_affinity(struct efx_nic *efx) 386 { 387 const struct cpumask *numa_mask = cpumask_of_pcibus(efx->pci_dev->bus); 388 struct efx_channel *channel; 389 unsigned int cpu; 390 391 /* If no online CPUs in local node, fallback to any online CPU */ 392 if (cpumask_first_and(cpu_online_mask, numa_mask) >= nr_cpu_ids) 393 numa_mask = cpu_online_mask; 394 395 cpu = -1; 396 efx_for_each_channel(channel, efx) { 397 cpu = cpumask_next_and(cpu, cpu_online_mask, numa_mask); 398 if (cpu >= nr_cpu_ids) 399 cpu = cpumask_first_and(cpu_online_mask, numa_mask); 400 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); 401 } 402 } 403 404 void efx_clear_interrupt_affinity(struct efx_nic *efx) 405 { 406 struct efx_channel *channel; 407 408 efx_for_each_channel(channel, efx) 409 irq_set_affinity_hint(channel->irq, NULL); 410 } 411 #else 412 void 413 efx_set_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused))) 414 { 415 } 416 417 void 418 efx_clear_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused))) 419 { 420 } 421 #endif /* CONFIG_SMP */ 422 423 void efx_remove_interrupts(struct efx_nic *efx) 424 { 425 struct efx_channel *channel; 426 427 /* Remove MSI/MSI-X interrupts */ 428 efx_for_each_channel(channel, efx) 429 channel->irq = 0; 430 pci_disable_msi(efx->pci_dev); 431 pci_disable_msix(efx->pci_dev); 432 433 /* Remove legacy interrupt */ 434 efx->legacy_irq = 0; 435 } 436 437 /*************** 438 * EVENT QUEUES 439 ***************/ 440 441 /* Create event queue 442 * Event queue memory allocations are done only once. If the channel 443 * is reset, the memory buffer will be reused; this guards against 444 * errors during channel reset and also simplifies interrupt handling. 445 */ 446 int efx_probe_eventq(struct efx_channel *channel) 447 { 448 struct efx_nic *efx = channel->efx; 449 unsigned long entries; 450 451 netif_dbg(efx, probe, efx->net_dev, 452 "chan %d create event queue\n", channel->channel); 453 454 /* Build an event queue with room for one event per tx and rx buffer, 455 * plus some extra for link state events and MCDI completions. 456 */ 457 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 458 EFX_WARN_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); 459 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; 460 461 return efx_nic_probe_eventq(channel); 462 } 463 464 /* Prepare channel's event queue */ 465 int efx_init_eventq(struct efx_channel *channel) 466 { 467 struct efx_nic *efx = channel->efx; 468 int rc; 469 470 EFX_WARN_ON_PARANOID(channel->eventq_init); 471 472 netif_dbg(efx, drv, efx->net_dev, 473 "chan %d init event queue\n", channel->channel); 474 475 rc = efx_nic_init_eventq(channel); 476 if (rc == 0) { 477 efx->type->push_irq_moderation(channel); 478 channel->eventq_read_ptr = 0; 479 channel->eventq_init = true; 480 } 481 return rc; 482 } 483 484 /* Enable event queue processing and NAPI */ 485 void efx_start_eventq(struct efx_channel *channel) 486 { 487 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 488 "chan %d start event queue\n", channel->channel); 489 490 /* Make sure the NAPI handler sees the enabled flag set */ 491 channel->enabled = true; 492 smp_wmb(); 493 494 napi_enable(&channel->napi_str); 495 efx_nic_eventq_read_ack(channel); 496 } 497 498 /* Disable event queue processing and NAPI */ 499 void efx_stop_eventq(struct efx_channel *channel) 500 { 501 if (!channel->enabled) 502 return; 503 504 napi_disable(&channel->napi_str); 505 channel->enabled = false; 506 } 507 508 void efx_fini_eventq(struct efx_channel *channel) 509 { 510 if (!channel->eventq_init) 511 return; 512 513 netif_dbg(channel->efx, drv, channel->efx->net_dev, 514 "chan %d fini event queue\n", channel->channel); 515 516 efx_nic_fini_eventq(channel); 517 channel->eventq_init = false; 518 } 519 520 void efx_remove_eventq(struct efx_channel *channel) 521 { 522 netif_dbg(channel->efx, drv, channel->efx->net_dev, 523 "chan %d remove event queue\n", channel->channel); 524 525 efx_nic_remove_eventq(channel); 526 } 527 528 /************************************************************************** 529 * 530 * Channel handling 531 * 532 *************************************************************************/ 533 534 #ifdef CONFIG_RFS_ACCEL 535 static void efx_filter_rfs_expire(struct work_struct *data) 536 { 537 struct delayed_work *dwork = to_delayed_work(data); 538 struct efx_channel *channel; 539 unsigned int time, quota; 540 541 channel = container_of(dwork, struct efx_channel, filter_work); 542 time = jiffies - channel->rfs_last_expiry; 543 quota = channel->rfs_filter_count * time / (30 * HZ); 544 if (quota >= 20 && __efx_filter_rfs_expire(channel, min(channel->rfs_filter_count, quota))) 545 channel->rfs_last_expiry += time; 546 /* Ensure we do more work eventually even if NAPI poll is not happening */ 547 schedule_delayed_work(dwork, 30 * HZ); 548 } 549 #endif 550 551 /* Allocate and initialise a channel structure. */ 552 static struct efx_channel *efx_alloc_channel(struct efx_nic *efx, int i) 553 { 554 struct efx_rx_queue *rx_queue; 555 struct efx_tx_queue *tx_queue; 556 struct efx_channel *channel; 557 int j; 558 559 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 560 if (!channel) 561 return NULL; 562 563 channel->efx = efx; 564 channel->channel = i; 565 channel->type = &efx_default_channel_type; 566 567 for (j = 0; j < EFX_MAX_TXQ_PER_CHANNEL; j++) { 568 tx_queue = &channel->tx_queue[j]; 569 tx_queue->efx = efx; 570 tx_queue->queue = -1; 571 tx_queue->label = j; 572 tx_queue->channel = channel; 573 } 574 575 #ifdef CONFIG_RFS_ACCEL 576 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); 577 #endif 578 579 rx_queue = &channel->rx_queue; 580 rx_queue->efx = efx; 581 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); 582 583 return channel; 584 } 585 586 int efx_init_channels(struct efx_nic *efx) 587 { 588 unsigned int i; 589 590 for (i = 0; i < EFX_MAX_CHANNELS; i++) { 591 efx->channel[i] = efx_alloc_channel(efx, i); 592 if (!efx->channel[i]) 593 return -ENOMEM; 594 efx->msi_context[i].efx = efx; 595 efx->msi_context[i].index = i; 596 } 597 598 /* Higher numbered interrupt modes are less capable! */ 599 efx->interrupt_mode = min(efx->type->min_interrupt_mode, 600 efx_interrupt_mode); 601 602 efx->max_channels = EFX_MAX_CHANNELS; 603 efx->max_tx_channels = EFX_MAX_CHANNELS; 604 605 return 0; 606 } 607 608 void efx_fini_channels(struct efx_nic *efx) 609 { 610 unsigned int i; 611 612 for (i = 0; i < EFX_MAX_CHANNELS; i++) 613 if (efx->channel[i]) { 614 kfree(efx->channel[i]); 615 efx->channel[i] = NULL; 616 } 617 } 618 619 /* Allocate and initialise a channel structure, copying parameters 620 * (but not resources) from an old channel structure. 621 */ 622 struct efx_channel *efx_copy_channel(const struct efx_channel *old_channel) 623 { 624 struct efx_rx_queue *rx_queue; 625 struct efx_tx_queue *tx_queue; 626 struct efx_channel *channel; 627 int j; 628 629 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 630 if (!channel) 631 return NULL; 632 633 *channel = *old_channel; 634 635 channel->napi_dev = NULL; 636 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); 637 channel->napi_str.napi_id = 0; 638 channel->napi_str.state = 0; 639 memset(&channel->eventq, 0, sizeof(channel->eventq)); 640 641 for (j = 0; j < EFX_MAX_TXQ_PER_CHANNEL; j++) { 642 tx_queue = &channel->tx_queue[j]; 643 if (tx_queue->channel) 644 tx_queue->channel = channel; 645 tx_queue->buffer = NULL; 646 tx_queue->cb_page = NULL; 647 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 648 } 649 650 rx_queue = &channel->rx_queue; 651 rx_queue->buffer = NULL; 652 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 653 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); 654 #ifdef CONFIG_RFS_ACCEL 655 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); 656 #endif 657 658 return channel; 659 } 660 661 static int efx_probe_channel(struct efx_channel *channel) 662 { 663 struct efx_tx_queue *tx_queue; 664 struct efx_rx_queue *rx_queue; 665 int rc; 666 667 netif_dbg(channel->efx, probe, channel->efx->net_dev, 668 "creating channel %d\n", channel->channel); 669 670 rc = channel->type->pre_probe(channel); 671 if (rc) 672 goto fail; 673 674 rc = efx_probe_eventq(channel); 675 if (rc) 676 goto fail; 677 678 efx_for_each_channel_tx_queue(tx_queue, channel) { 679 rc = efx_probe_tx_queue(tx_queue); 680 if (rc) 681 goto fail; 682 } 683 684 efx_for_each_channel_rx_queue(rx_queue, channel) { 685 rc = efx_probe_rx_queue(rx_queue); 686 if (rc) 687 goto fail; 688 } 689 690 channel->rx_list = NULL; 691 692 return 0; 693 694 fail: 695 efx_remove_channel(channel); 696 return rc; 697 } 698 699 void efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) 700 { 701 struct efx_nic *efx = channel->efx; 702 const char *type; 703 int number; 704 705 number = channel->channel; 706 707 if (number >= efx->xdp_channel_offset && 708 !WARN_ON_ONCE(!efx->n_xdp_channels)) { 709 type = "-xdp"; 710 number -= efx->xdp_channel_offset; 711 } else if (efx->tx_channel_offset == 0) { 712 type = ""; 713 } else if (number < efx->tx_channel_offset) { 714 type = "-rx"; 715 } else { 716 type = "-tx"; 717 number -= efx->tx_channel_offset; 718 } 719 snprintf(buf, len, "%s%s-%d", efx->name, type, number); 720 } 721 722 void efx_set_channel_names(struct efx_nic *efx) 723 { 724 struct efx_channel *channel; 725 726 efx_for_each_channel(channel, efx) 727 channel->type->get_name(channel, 728 efx->msi_context[channel->channel].name, 729 sizeof(efx->msi_context[0].name)); 730 } 731 732 int efx_probe_channels(struct efx_nic *efx) 733 { 734 struct efx_channel *channel; 735 int rc; 736 737 /* Restart special buffer allocation */ 738 efx->next_buffer_table = 0; 739 740 /* Probe channels in reverse, so that any 'extra' channels 741 * use the start of the buffer table. This allows the traffic 742 * channels to be resized without moving them or wasting the 743 * entries before them. 744 */ 745 efx_for_each_channel_rev(channel, efx) { 746 rc = efx_probe_channel(channel); 747 if (rc) { 748 netif_err(efx, probe, efx->net_dev, 749 "failed to create channel %d\n", 750 channel->channel); 751 goto fail; 752 } 753 } 754 efx_set_channel_names(efx); 755 756 return 0; 757 758 fail: 759 efx_remove_channels(efx); 760 return rc; 761 } 762 763 void efx_remove_channel(struct efx_channel *channel) 764 { 765 struct efx_tx_queue *tx_queue; 766 struct efx_rx_queue *rx_queue; 767 768 netif_dbg(channel->efx, drv, channel->efx->net_dev, 769 "destroy chan %d\n", channel->channel); 770 771 efx_for_each_channel_rx_queue(rx_queue, channel) 772 efx_remove_rx_queue(rx_queue); 773 efx_for_each_channel_tx_queue(tx_queue, channel) 774 efx_remove_tx_queue(tx_queue); 775 efx_remove_eventq(channel); 776 channel->type->post_remove(channel); 777 } 778 779 void efx_remove_channels(struct efx_nic *efx) 780 { 781 struct efx_channel *channel; 782 783 efx_for_each_channel(channel, efx) 784 efx_remove_channel(channel); 785 786 kfree(efx->xdp_tx_queues); 787 } 788 789 int efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) 790 { 791 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; 792 unsigned int i, next_buffer_table = 0; 793 u32 old_rxq_entries, old_txq_entries; 794 int rc, rc2; 795 796 rc = efx_check_disabled(efx); 797 if (rc) 798 return rc; 799 800 /* Not all channels should be reallocated. We must avoid 801 * reallocating their buffer table entries. 802 */ 803 efx_for_each_channel(channel, efx) { 804 struct efx_rx_queue *rx_queue; 805 struct efx_tx_queue *tx_queue; 806 807 if (channel->type->copy) 808 continue; 809 next_buffer_table = max(next_buffer_table, 810 channel->eventq.index + 811 channel->eventq.entries); 812 efx_for_each_channel_rx_queue(rx_queue, channel) 813 next_buffer_table = max(next_buffer_table, 814 rx_queue->rxd.index + 815 rx_queue->rxd.entries); 816 efx_for_each_channel_tx_queue(tx_queue, channel) 817 next_buffer_table = max(next_buffer_table, 818 tx_queue->txd.index + 819 tx_queue->txd.entries); 820 } 821 822 efx_device_detach_sync(efx); 823 efx_stop_all(efx); 824 efx_soft_disable_interrupts(efx); 825 826 /* Clone channels (where possible) */ 827 memset(other_channel, 0, sizeof(other_channel)); 828 for (i = 0; i < efx->n_channels; i++) { 829 channel = efx->channel[i]; 830 if (channel->type->copy) 831 channel = channel->type->copy(channel); 832 if (!channel) { 833 rc = -ENOMEM; 834 goto out; 835 } 836 other_channel[i] = channel; 837 } 838 839 /* Swap entry counts and channel pointers */ 840 old_rxq_entries = efx->rxq_entries; 841 old_txq_entries = efx->txq_entries; 842 efx->rxq_entries = rxq_entries; 843 efx->txq_entries = txq_entries; 844 for (i = 0; i < efx->n_channels; i++) 845 swap(efx->channel[i], other_channel[i]); 846 847 /* Restart buffer table allocation */ 848 efx->next_buffer_table = next_buffer_table; 849 850 for (i = 0; i < efx->n_channels; i++) { 851 channel = efx->channel[i]; 852 if (!channel->type->copy) 853 continue; 854 rc = efx_probe_channel(channel); 855 if (rc) 856 goto rollback; 857 efx_init_napi_channel(efx->channel[i]); 858 } 859 860 out: 861 /* Destroy unused channel structures */ 862 for (i = 0; i < efx->n_channels; i++) { 863 channel = other_channel[i]; 864 if (channel && channel->type->copy) { 865 efx_fini_napi_channel(channel); 866 efx_remove_channel(channel); 867 kfree(channel); 868 } 869 } 870 871 rc2 = efx_soft_enable_interrupts(efx); 872 if (rc2) { 873 rc = rc ? rc : rc2; 874 netif_err(efx, drv, efx->net_dev, 875 "unable to restart interrupts on channel reallocation\n"); 876 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 877 } else { 878 efx_start_all(efx); 879 efx_device_attach_if_not_resetting(efx); 880 } 881 return rc; 882 883 rollback: 884 /* Swap back */ 885 efx->rxq_entries = old_rxq_entries; 886 efx->txq_entries = old_txq_entries; 887 for (i = 0; i < efx->n_channels; i++) 888 swap(efx->channel[i], other_channel[i]); 889 goto out; 890 } 891 892 static inline int 893 efx_set_xdp_tx_queue(struct efx_nic *efx, int xdp_queue_number, 894 struct efx_tx_queue *tx_queue) 895 { 896 if (xdp_queue_number >= efx->xdp_tx_queue_count) 897 return -EINVAL; 898 899 netif_dbg(efx, drv, efx->net_dev, "Channel %u TXQ %u is XDP %u, HW %u\n", 900 tx_queue->channel->channel, tx_queue->label, 901 xdp_queue_number, tx_queue->queue); 902 efx->xdp_tx_queues[xdp_queue_number] = tx_queue; 903 return 0; 904 } 905 906 int efx_set_channels(struct efx_nic *efx) 907 { 908 struct efx_tx_queue *tx_queue; 909 struct efx_channel *channel; 910 unsigned int next_queue = 0; 911 int xdp_queue_number; 912 int rc; 913 914 efx->tx_channel_offset = 915 efx_separate_tx_channels ? 916 efx->n_channels - efx->n_tx_channels : 0; 917 918 if (efx->xdp_tx_queue_count) { 919 EFX_WARN_ON_PARANOID(efx->xdp_tx_queues); 920 921 /* Allocate array for XDP TX queue lookup. */ 922 efx->xdp_tx_queues = kcalloc(efx->xdp_tx_queue_count, 923 sizeof(*efx->xdp_tx_queues), 924 GFP_KERNEL); 925 if (!efx->xdp_tx_queues) 926 return -ENOMEM; 927 } 928 929 /* We need to mark which channels really have RX and TX 930 * queues, and adjust the TX queue numbers if we have separate 931 * RX-only and TX-only channels. 932 */ 933 xdp_queue_number = 0; 934 efx_for_each_channel(channel, efx) { 935 if (channel->channel < efx->n_rx_channels) 936 channel->rx_queue.core_index = channel->channel; 937 else 938 channel->rx_queue.core_index = -1; 939 940 if (channel->channel >= efx->tx_channel_offset) { 941 if (efx_channel_is_xdp_tx(channel)) { 942 efx_for_each_channel_tx_queue(tx_queue, channel) { 943 tx_queue->queue = next_queue++; 944 rc = efx_set_xdp_tx_queue(efx, xdp_queue_number, tx_queue); 945 if (rc == 0) 946 xdp_queue_number++; 947 } 948 } else { 949 efx_for_each_channel_tx_queue(tx_queue, channel) { 950 tx_queue->queue = next_queue++; 951 netif_dbg(efx, drv, efx->net_dev, "Channel %u TXQ %u is HW %u\n", 952 channel->channel, tx_queue->label, 953 tx_queue->queue); 954 } 955 956 /* If XDP is borrowing queues from net stack, it must use the queue 957 * with no csum offload, which is the first one of the channel 958 * (note: channel->tx_queue_by_type is not initialized yet) 959 */ 960 if (efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_BORROWED) { 961 tx_queue = &channel->tx_queue[0]; 962 rc = efx_set_xdp_tx_queue(efx, xdp_queue_number, tx_queue); 963 if (rc == 0) 964 xdp_queue_number++; 965 } 966 } 967 } 968 } 969 WARN_ON(efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_DEDICATED && 970 xdp_queue_number != efx->xdp_tx_queue_count); 971 WARN_ON(efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED && 972 xdp_queue_number > efx->xdp_tx_queue_count); 973 974 /* If we have more CPUs than assigned XDP TX queues, assign the already 975 * existing queues to the exceeding CPUs 976 */ 977 next_queue = 0; 978 while (xdp_queue_number < efx->xdp_tx_queue_count) { 979 tx_queue = efx->xdp_tx_queues[next_queue++]; 980 rc = efx_set_xdp_tx_queue(efx, xdp_queue_number, tx_queue); 981 if (rc == 0) 982 xdp_queue_number++; 983 } 984 985 rc = netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); 986 if (rc) 987 return rc; 988 return netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); 989 } 990 991 bool efx_default_channel_want_txqs(struct efx_channel *channel) 992 { 993 return channel->channel - channel->efx->tx_channel_offset < 994 channel->efx->n_tx_channels; 995 } 996 997 /************* 998 * START/STOP 999 *************/ 1000 1001 int efx_soft_enable_interrupts(struct efx_nic *efx) 1002 { 1003 struct efx_channel *channel, *end_channel; 1004 int rc; 1005 1006 BUG_ON(efx->state == STATE_DISABLED); 1007 1008 efx->irq_soft_enabled = true; 1009 smp_wmb(); 1010 1011 efx_for_each_channel(channel, efx) { 1012 if (!channel->type->keep_eventq) { 1013 rc = efx_init_eventq(channel); 1014 if (rc) 1015 goto fail; 1016 } 1017 efx_start_eventq(channel); 1018 } 1019 1020 efx_mcdi_mode_event(efx); 1021 1022 return 0; 1023 fail: 1024 end_channel = channel; 1025 efx_for_each_channel(channel, efx) { 1026 if (channel == end_channel) 1027 break; 1028 efx_stop_eventq(channel); 1029 if (!channel->type->keep_eventq) 1030 efx_fini_eventq(channel); 1031 } 1032 1033 return rc; 1034 } 1035 1036 void efx_soft_disable_interrupts(struct efx_nic *efx) 1037 { 1038 struct efx_channel *channel; 1039 1040 if (efx->state == STATE_DISABLED) 1041 return; 1042 1043 efx_mcdi_mode_poll(efx); 1044 1045 efx->irq_soft_enabled = false; 1046 smp_wmb(); 1047 1048 if (efx->legacy_irq) 1049 synchronize_irq(efx->legacy_irq); 1050 1051 efx_for_each_channel(channel, efx) { 1052 if (channel->irq) 1053 synchronize_irq(channel->irq); 1054 1055 efx_stop_eventq(channel); 1056 if (!channel->type->keep_eventq) 1057 efx_fini_eventq(channel); 1058 } 1059 1060 /* Flush the asynchronous MCDI request queue */ 1061 efx_mcdi_flush_async(efx); 1062 } 1063 1064 int efx_enable_interrupts(struct efx_nic *efx) 1065 { 1066 struct efx_channel *channel, *end_channel; 1067 int rc; 1068 1069 /* TODO: Is this really a bug? */ 1070 BUG_ON(efx->state == STATE_DISABLED); 1071 1072 if (efx->eeh_disabled_legacy_irq) { 1073 enable_irq(efx->legacy_irq); 1074 efx->eeh_disabled_legacy_irq = false; 1075 } 1076 1077 efx->type->irq_enable_master(efx); 1078 1079 efx_for_each_channel(channel, efx) { 1080 if (channel->type->keep_eventq) { 1081 rc = efx_init_eventq(channel); 1082 if (rc) 1083 goto fail; 1084 } 1085 } 1086 1087 rc = efx_soft_enable_interrupts(efx); 1088 if (rc) 1089 goto fail; 1090 1091 return 0; 1092 1093 fail: 1094 end_channel = channel; 1095 efx_for_each_channel(channel, efx) { 1096 if (channel == end_channel) 1097 break; 1098 if (channel->type->keep_eventq) 1099 efx_fini_eventq(channel); 1100 } 1101 1102 efx->type->irq_disable_non_ev(efx); 1103 1104 return rc; 1105 } 1106 1107 void efx_disable_interrupts(struct efx_nic *efx) 1108 { 1109 struct efx_channel *channel; 1110 1111 efx_soft_disable_interrupts(efx); 1112 1113 efx_for_each_channel(channel, efx) { 1114 if (channel->type->keep_eventq) 1115 efx_fini_eventq(channel); 1116 } 1117 1118 efx->type->irq_disable_non_ev(efx); 1119 } 1120 1121 void efx_start_channels(struct efx_nic *efx) 1122 { 1123 struct efx_tx_queue *tx_queue; 1124 struct efx_rx_queue *rx_queue; 1125 struct efx_channel *channel; 1126 1127 efx_for_each_channel(channel, efx) { 1128 efx_for_each_channel_tx_queue(tx_queue, channel) { 1129 efx_init_tx_queue(tx_queue); 1130 atomic_inc(&efx->active_queues); 1131 } 1132 1133 efx_for_each_channel_rx_queue(rx_queue, channel) { 1134 efx_init_rx_queue(rx_queue); 1135 atomic_inc(&efx->active_queues); 1136 efx_stop_eventq(channel); 1137 efx_fast_push_rx_descriptors(rx_queue, false); 1138 efx_start_eventq(channel); 1139 } 1140 1141 WARN_ON(channel->rx_pkt_n_frags); 1142 } 1143 } 1144 1145 void efx_stop_channels(struct efx_nic *efx) 1146 { 1147 struct efx_tx_queue *tx_queue; 1148 struct efx_rx_queue *rx_queue; 1149 struct efx_channel *channel; 1150 int rc = 0; 1151 1152 /* Stop RX refill */ 1153 efx_for_each_channel(channel, efx) { 1154 efx_for_each_channel_rx_queue(rx_queue, channel) 1155 rx_queue->refill_enabled = false; 1156 } 1157 1158 efx_for_each_channel(channel, efx) { 1159 /* RX packet processing is pipelined, so wait for the 1160 * NAPI handler to complete. At least event queue 0 1161 * might be kept active by non-data events, so don't 1162 * use napi_synchronize() but actually disable NAPI 1163 * temporarily. 1164 */ 1165 if (efx_channel_has_rx_queue(channel)) { 1166 efx_stop_eventq(channel); 1167 efx_start_eventq(channel); 1168 } 1169 } 1170 1171 if (efx->type->fini_dmaq) 1172 rc = efx->type->fini_dmaq(efx); 1173 1174 if (rc) { 1175 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 1176 } else { 1177 netif_dbg(efx, drv, efx->net_dev, 1178 "successfully flushed all queues\n"); 1179 } 1180 1181 efx_for_each_channel(channel, efx) { 1182 efx_for_each_channel_rx_queue(rx_queue, channel) 1183 efx_fini_rx_queue(rx_queue); 1184 efx_for_each_channel_tx_queue(tx_queue, channel) 1185 efx_fini_tx_queue(tx_queue); 1186 } 1187 } 1188 1189 /************************************************************************** 1190 * 1191 * NAPI interface 1192 * 1193 *************************************************************************/ 1194 1195 /* Process channel's event queue 1196 * 1197 * This function is responsible for processing the event queue of a 1198 * single channel. The caller must guarantee that this function will 1199 * never be concurrently called more than once on the same channel, 1200 * though different channels may be being processed concurrently. 1201 */ 1202 static int efx_process_channel(struct efx_channel *channel, int budget) 1203 { 1204 struct efx_tx_queue *tx_queue; 1205 struct list_head rx_list; 1206 int spent; 1207 1208 if (unlikely(!channel->enabled)) 1209 return 0; 1210 1211 /* Prepare the batch receive list */ 1212 EFX_WARN_ON_PARANOID(channel->rx_list != NULL); 1213 INIT_LIST_HEAD(&rx_list); 1214 channel->rx_list = &rx_list; 1215 1216 efx_for_each_channel_tx_queue(tx_queue, channel) { 1217 tx_queue->pkts_compl = 0; 1218 tx_queue->bytes_compl = 0; 1219 } 1220 1221 spent = efx_nic_process_eventq(channel, budget); 1222 if (spent && efx_channel_has_rx_queue(channel)) { 1223 struct efx_rx_queue *rx_queue = 1224 efx_channel_get_rx_queue(channel); 1225 1226 efx_rx_flush_packet(channel); 1227 efx_fast_push_rx_descriptors(rx_queue, true); 1228 } 1229 1230 /* Update BQL */ 1231 efx_for_each_channel_tx_queue(tx_queue, channel) { 1232 if (tx_queue->bytes_compl) { 1233 netdev_tx_completed_queue(tx_queue->core_txq, 1234 tx_queue->pkts_compl, 1235 tx_queue->bytes_compl); 1236 } 1237 } 1238 1239 /* Receive any packets we queued up */ 1240 netif_receive_skb_list(channel->rx_list); 1241 channel->rx_list = NULL; 1242 1243 return spent; 1244 } 1245 1246 static void efx_update_irq_mod(struct efx_nic *efx, struct efx_channel *channel) 1247 { 1248 int step = efx->irq_mod_step_us; 1249 1250 if (channel->irq_mod_score < irq_adapt_low_thresh) { 1251 if (channel->irq_moderation_us > step) { 1252 channel->irq_moderation_us -= step; 1253 efx->type->push_irq_moderation(channel); 1254 } 1255 } else if (channel->irq_mod_score > irq_adapt_high_thresh) { 1256 if (channel->irq_moderation_us < 1257 efx->irq_rx_moderation_us) { 1258 channel->irq_moderation_us += step; 1259 efx->type->push_irq_moderation(channel); 1260 } 1261 } 1262 1263 channel->irq_count = 0; 1264 channel->irq_mod_score = 0; 1265 } 1266 1267 /* NAPI poll handler 1268 * 1269 * NAPI guarantees serialisation of polls of the same device, which 1270 * provides the guarantee required by efx_process_channel(). 1271 */ 1272 static int efx_poll(struct napi_struct *napi, int budget) 1273 { 1274 struct efx_channel *channel = 1275 container_of(napi, struct efx_channel, napi_str); 1276 struct efx_nic *efx = channel->efx; 1277 #ifdef CONFIG_RFS_ACCEL 1278 unsigned int time; 1279 #endif 1280 int spent; 1281 1282 netif_vdbg(efx, intr, efx->net_dev, 1283 "channel %d NAPI poll executing on CPU %d\n", 1284 channel->channel, raw_smp_processor_id()); 1285 1286 spent = efx_process_channel(channel, budget); 1287 1288 xdp_do_flush_map(); 1289 1290 if (spent < budget) { 1291 if (efx_channel_has_rx_queue(channel) && 1292 efx->irq_rx_adaptive && 1293 unlikely(++channel->irq_count == 1000)) { 1294 efx_update_irq_mod(efx, channel); 1295 } 1296 1297 #ifdef CONFIG_RFS_ACCEL 1298 /* Perhaps expire some ARFS filters */ 1299 time = jiffies - channel->rfs_last_expiry; 1300 /* Would our quota be >= 20? */ 1301 if (channel->rfs_filter_count * time >= 600 * HZ) 1302 mod_delayed_work(system_wq, &channel->filter_work, 0); 1303 #endif 1304 1305 /* There is no race here; although napi_disable() will 1306 * only wait for napi_complete(), this isn't a problem 1307 * since efx_nic_eventq_read_ack() will have no effect if 1308 * interrupts have already been disabled. 1309 */ 1310 if (napi_complete_done(napi, spent)) 1311 efx_nic_eventq_read_ack(channel); 1312 } 1313 1314 return spent; 1315 } 1316 1317 void efx_init_napi_channel(struct efx_channel *channel) 1318 { 1319 struct efx_nic *efx = channel->efx; 1320 1321 channel->napi_dev = efx->net_dev; 1322 netif_napi_add(channel->napi_dev, &channel->napi_str, 1323 efx_poll, napi_weight); 1324 } 1325 1326 void efx_init_napi(struct efx_nic *efx) 1327 { 1328 struct efx_channel *channel; 1329 1330 efx_for_each_channel(channel, efx) 1331 efx_init_napi_channel(channel); 1332 } 1333 1334 void efx_fini_napi_channel(struct efx_channel *channel) 1335 { 1336 if (channel->napi_dev) 1337 netif_napi_del(&channel->napi_str); 1338 1339 channel->napi_dev = NULL; 1340 } 1341 1342 void efx_fini_napi(struct efx_nic *efx) 1343 { 1344 struct efx_channel *channel; 1345 1346 efx_for_each_channel(channel, efx) 1347 efx_fini_napi_channel(channel); 1348 } 1349