1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2012-2017 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 #ifndef EFX_EF10_REGS_H 11 #define EFX_EF10_REGS_H 12 13 /* EF10 hardware architecture definitions have a name prefix following 14 * the format: 15 * 16 * E<type>_<min-rev><max-rev>_ 17 * 18 * The following <type> strings are used: 19 * 20 * MMIO register Host memory structure 21 * ------------------------------------------------------------- 22 * Address R 23 * Bitfield RF SF 24 * Enumerator FE SE 25 * 26 * <min-rev> is the first revision to which the definition applies: 27 * 28 * D: Huntington A0 29 * 30 * If the definition has been changed or removed in later revisions 31 * then <max-rev> is the last revision to which the definition applies; 32 * otherwise it is "Z". 33 */ 34 35 /************************************************************************** 36 * 37 * EF10 registers and descriptors 38 * 39 ************************************************************************** 40 */ 41 42 /* BIU_HW_REV_ID_REG: */ 43 #define ER_DZ_BIU_HW_REV_ID 0x00000000 44 #define ERF_DZ_HW_REV_ID_LBN 0 45 #define ERF_DZ_HW_REV_ID_WIDTH 32 46 47 /* BIU_MC_SFT_STATUS_REG: */ 48 #define ER_DZ_BIU_MC_SFT_STATUS 0x00000010 49 #define ER_DZ_BIU_MC_SFT_STATUS_STEP 4 50 #define ER_DZ_BIU_MC_SFT_STATUS_ROWS 8 51 #define ERF_DZ_MC_SFT_STATUS_LBN 0 52 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 53 54 /* BIU_INT_ISR_REG: */ 55 #define ER_DZ_BIU_INT_ISR 0x00000090 56 #define ERF_DZ_ISR_REG_LBN 0 57 #define ERF_DZ_ISR_REG_WIDTH 32 58 59 /* MC_DB_LWRD_REG: */ 60 #define ER_DZ_MC_DB_LWRD 0x00000200 61 #define ERF_DZ_MC_DOORBELL_L_LBN 0 62 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 63 64 /* MC_DB_HWRD_REG: */ 65 #define ER_DZ_MC_DB_HWRD 0x00000204 66 #define ERF_DZ_MC_DOORBELL_H_LBN 0 67 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 68 69 /* EVQ_RPTR_REG: */ 70 #define ER_DZ_EVQ_RPTR 0x00000400 71 #define ER_DZ_EVQ_RPTR_STEP 8192 72 #define ER_DZ_EVQ_RPTR_ROWS 2048 73 #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 74 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 75 #define ERF_DZ_EVQ_RPTR_LBN 0 76 #define ERF_DZ_EVQ_RPTR_WIDTH 15 77 78 /* EVQ_TMR_REG: */ 79 #define ER_DZ_EVQ_TMR 0x00000420 80 #define ER_DZ_EVQ_TMR_STEP 8192 81 #define ER_DZ_EVQ_TMR_ROWS 2048 82 #define ERF_FZ_TC_TMR_REL_VAL_LBN 16 83 #define ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 84 #define ERF_DZ_TC_TIMER_MODE_LBN 14 85 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 86 #define ERF_DZ_TC_TIMER_VAL_LBN 0 87 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 88 89 /* RX_DESC_UPD_REG: */ 90 #define ER_DZ_RX_DESC_UPD 0x00000830 91 #define ER_DZ_RX_DESC_UPD_STEP 8192 92 #define ER_DZ_RX_DESC_UPD_ROWS 2048 93 #define ERF_DZ_RX_DESC_WPTR_LBN 0 94 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 95 96 /* TX_DESC_UPD_REG: */ 97 #define ER_DZ_TX_DESC_UPD 0x00000a10 98 #define ER_DZ_TX_DESC_UPD_STEP 8192 99 #define ER_DZ_TX_DESC_UPD_ROWS 2048 100 #define ERF_DZ_RSVD_LBN 76 101 #define ERF_DZ_RSVD_WIDTH 20 102 #define ERF_DZ_TX_DESC_WPTR_LBN 64 103 #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 104 #define ERF_DZ_TX_DESC_HWORD_LBN 32 105 #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 106 #define ERF_DZ_TX_DESC_LWORD_LBN 0 107 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 108 109 /* DRIVER_EV */ 110 #define ESF_DZ_DRV_CODE_LBN 60 111 #define ESF_DZ_DRV_CODE_WIDTH 4 112 #define ESF_DZ_DRV_SUB_CODE_LBN 56 113 #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 114 #define ESE_DZ_DRV_TIMER_EV 3 115 #define ESE_DZ_DRV_START_UP_EV 2 116 #define ESE_DZ_DRV_WAKE_UP_EV 1 117 #define ESF_DZ_DRV_SUB_DATA_LBN 0 118 #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 119 #define ESF_DZ_DRV_EVQ_ID_LBN 0 120 #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 121 #define ESF_DZ_DRV_TMR_ID_LBN 0 122 #define ESF_DZ_DRV_TMR_ID_WIDTH 14 123 124 /* EVENT_ENTRY */ 125 #define ESF_DZ_EV_CODE_LBN 60 126 #define ESF_DZ_EV_CODE_WIDTH 4 127 #define ESE_DZ_EV_CODE_MCDI_EV 12 128 #define ESE_DZ_EV_CODE_DRIVER_EV 5 129 #define ESE_DZ_EV_CODE_TX_EV 2 130 #define ESE_DZ_EV_CODE_RX_EV 0 131 #define ESE_DZ_OTHER other 132 #define ESF_DZ_EV_DATA_LBN 0 133 #define ESF_DZ_EV_DATA_WIDTH 60 134 135 /* MC_EVENT */ 136 #define ESF_DZ_MC_CODE_LBN 60 137 #define ESF_DZ_MC_CODE_WIDTH 4 138 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 139 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 140 #define ESF_DZ_MC_DROP_EVENT_LBN 58 141 #define ESF_DZ_MC_DROP_EVENT_WIDTH 1 142 #define ESF_DZ_MC_SOFT_LBN 0 143 #define ESF_DZ_MC_SOFT_WIDTH 58 144 145 /* RX_EVENT */ 146 #define ESF_DZ_RX_CODE_LBN 60 147 #define ESF_DZ_RX_CODE_WIDTH 4 148 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 149 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 150 #define ESF_DZ_RX_DROP_EVENT_LBN 58 151 #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 152 #define ESF_DD_RX_EV_RSVD2_LBN 54 153 #define ESF_DD_RX_EV_RSVD2_WIDTH 4 154 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 155 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 156 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56 157 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1 158 #define ESF_EZ_RX_EV_RSVD2_LBN 54 159 #define ESF_EZ_RX_EV_RSVD2_WIDTH 2 160 #define ESF_DZ_RX_EV_SOFT2_LBN 52 161 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 162 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 163 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 164 #define ESF_DE_RX_L4_CLASS_LBN 45 165 #define ESF_DE_RX_L4_CLASS_WIDTH 3 166 #define ESE_DE_L4_CLASS_RSVD7 7 167 #define ESE_DE_L4_CLASS_RSVD6 6 168 #define ESE_DE_L4_CLASS_RSVD5 5 169 #define ESE_DE_L4_CLASS_RSVD4 4 170 #define ESE_DE_L4_CLASS_RSVD3 3 171 #define ESE_DE_L4_CLASS_UDP 2 172 #define ESE_DE_L4_CLASS_TCP 1 173 #define ESE_DE_L4_CLASS_UNKNOWN 0 174 #define ESF_FZ_RX_FASTPD_INDCTR_LBN 47 175 #define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1 176 #define ESF_FZ_RX_L4_CLASS_LBN 45 177 #define ESF_FZ_RX_L4_CLASS_WIDTH 2 178 #define ESE_FZ_L4_CLASS_RSVD3 3 179 #define ESE_FZ_L4_CLASS_UDP 2 180 #define ESE_FZ_L4_CLASS_TCP 1 181 #define ESE_FZ_L4_CLASS_UNKNOWN 0 182 #define ESF_DZ_RX_L3_CLASS_LBN 42 183 #define ESF_DZ_RX_L3_CLASS_WIDTH 3 184 #define ESE_DZ_L3_CLASS_RSVD7 7 185 #define ESE_DZ_L3_CLASS_IP6_FRAG 6 186 #define ESE_DZ_L3_CLASS_ARP 5 187 #define ESE_DZ_L3_CLASS_IP4_FRAG 4 188 #define ESE_DZ_L3_CLASS_FCOE 3 189 #define ESE_DZ_L3_CLASS_IP6 2 190 #define ESE_DZ_L3_CLASS_IP4 1 191 #define ESE_DZ_L3_CLASS_UNKNOWN 0 192 #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 193 #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 194 #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 195 #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 196 #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 197 #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 198 #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 199 #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 200 #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 201 #define ESE_DZ_ETH_TAG_CLASS_NONE 0 202 #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 203 #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 204 #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 205 #define ESE_DZ_ETH_BASE_CLASS_LLC 1 206 #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 207 #define ESF_DZ_RX_MAC_CLASS_LBN 35 208 #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 209 #define ESE_DZ_MAC_CLASS_MCAST 1 210 #define ESE_DZ_MAC_CLASS_UCAST 0 211 #define ESF_DD_RX_EV_SOFT1_LBN 32 212 #define ESF_DD_RX_EV_SOFT1_WIDTH 3 213 #define ESF_EZ_RX_EV_SOFT1_LBN 34 214 #define ESF_EZ_RX_EV_SOFT1_WIDTH 1 215 #define ESF_EZ_RX_ENCAP_HDR_LBN 32 216 #define ESF_EZ_RX_ENCAP_HDR_WIDTH 2 217 #define ESE_EZ_ENCAP_HDR_GRE 2 218 #define ESE_EZ_ENCAP_HDR_VXLAN 1 219 #define ESE_EZ_ENCAP_HDR_NONE 0 220 #define ESF_DD_RX_EV_RSVD1_LBN 30 221 #define ESF_DD_RX_EV_RSVD1_WIDTH 2 222 #define ESF_EZ_RX_EV_RSVD1_LBN 31 223 #define ESF_EZ_RX_EV_RSVD1_WIDTH 1 224 #define ESF_EZ_RX_ABORT_LBN 30 225 #define ESF_EZ_RX_ABORT_WIDTH 1 226 #define ESF_DZ_RX_ECC_ERR_LBN 29 227 #define ESF_DZ_RX_ECC_ERR_WIDTH 1 228 #define ESF_DZ_RX_TRUNC_ERR_LBN 29 229 #define ESF_DZ_RX_TRUNC_ERR_WIDTH 1 230 #define ESF_DZ_RX_CRC1_ERR_LBN 28 231 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 232 #define ESF_DZ_RX_CRC0_ERR_LBN 27 233 #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 234 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 235 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 236 #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 237 #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 238 #define ESF_DZ_RX_ECRC_ERR_LBN 24 239 #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 240 #define ESF_DZ_RX_QLABEL_LBN 16 241 #define ESF_DZ_RX_QLABEL_WIDTH 5 242 #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 243 #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 244 #define ESF_DZ_RX_CONT_LBN 14 245 #define ESF_DZ_RX_CONT_WIDTH 1 246 #define ESF_DZ_RX_BYTES_LBN 0 247 #define ESF_DZ_RX_BYTES_WIDTH 14 248 249 /* RX_KER_DESC */ 250 #define ESF_DZ_RX_KER_RESERVED_LBN 62 251 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 252 #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 253 #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 254 #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 255 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 256 257 /* TX_CSUM_TSTAMP_DESC */ 258 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 259 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 260 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 261 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 262 #define ESE_DZ_TX_OPTION_DESC_TSO 7 263 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 264 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 265 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8 266 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1 267 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7 268 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1 269 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6 270 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1 271 #define ESF_DZ_TX_TIMESTAMP_LBN 5 272 #define ESF_DZ_TX_TIMESTAMP_WIDTH 1 273 #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 274 #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 275 #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 276 #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 277 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 278 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 279 #define ESE_DZ_TX_OPTION_CRC_FCOE 1 280 #define ESE_DZ_TX_OPTION_CRC_OFF 0 281 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 282 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 283 #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 284 #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 285 286 /* TX_EVENT */ 287 #define ESF_DZ_TX_CODE_LBN 60 288 #define ESF_DZ_TX_CODE_WIDTH 4 289 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 290 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 291 #define ESF_DZ_TX_DROP_EVENT_LBN 58 292 #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 293 #define ESF_DD_TX_EV_RSVD_LBN 48 294 #define ESF_DD_TX_EV_RSVD_WIDTH 10 295 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 296 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 297 #define ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56 298 #define ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1 299 #define ESF_EZ_TX_EV_RSVD_LBN 48 300 #define ESF_EZ_TX_EV_RSVD_WIDTH 8 301 #define ESF_DZ_TX_SOFT2_LBN 32 302 #define ESF_DZ_TX_SOFT2_WIDTH 16 303 #define ESF_DD_TX_SOFT1_LBN 24 304 #define ESF_DD_TX_SOFT1_WIDTH 8 305 #define ESF_EZ_TX_CAN_MERGE_LBN 31 306 #define ESF_EZ_TX_CAN_MERGE_WIDTH 1 307 #define ESF_EZ_TX_SOFT1_LBN 24 308 #define ESF_EZ_TX_SOFT1_WIDTH 7 309 #define ESF_DZ_TX_QLABEL_LBN 16 310 #define ESF_DZ_TX_QLABEL_WIDTH 5 311 #define ESF_DZ_TX_DESCR_INDX_LBN 0 312 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 313 314 /* TX_KER_DESC */ 315 #define ESF_DZ_TX_KER_TYPE_LBN 63 316 #define ESF_DZ_TX_KER_TYPE_WIDTH 1 317 #define ESF_DZ_TX_KER_CONT_LBN 62 318 #define ESF_DZ_TX_KER_CONT_WIDTH 1 319 #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 320 #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 321 #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 322 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 323 324 /* TX_PIO_DESC */ 325 #define ESF_DZ_TX_PIO_TYPE_LBN 63 326 #define ESF_DZ_TX_PIO_TYPE_WIDTH 1 327 #define ESF_DZ_TX_PIO_OPT_LBN 60 328 #define ESF_DZ_TX_PIO_OPT_WIDTH 3 329 #define ESE_DZ_TX_OPTION_DESC_PIO 1 330 #define ESF_DZ_TX_PIO_CONT_LBN 59 331 #define ESF_DZ_TX_PIO_CONT_WIDTH 1 332 #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 333 #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 334 #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 335 #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 336 337 /* TX_TSO_DESC */ 338 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 339 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 340 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 341 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 342 #define ESE_DZ_TX_OPTION_DESC_TSO 7 343 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 344 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 345 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 346 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 347 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 348 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 349 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 350 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 351 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 352 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 353 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 354 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 355 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 356 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 357 358 /* TX_TSO_V2_DESC_A */ 359 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 360 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 361 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 362 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 363 #define ESE_DZ_TX_OPTION_DESC_TSO 7 364 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 365 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 366 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 367 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 368 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 369 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 370 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 371 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 372 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 373 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 374 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 375 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 376 377 /* TX_TSO_V2_DESC_B */ 378 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 379 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 380 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 381 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 382 #define ESE_DZ_TX_OPTION_DESC_TSO 7 383 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 384 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 385 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 386 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 387 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 388 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 389 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 390 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 391 #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 392 #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 393 #define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0 394 #define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16 395 396 /*************************************************************************/ 397 398 /* TX_DESC_UPD_REG: Transmit descriptor update register. 399 * We may write just one dword of these registers. 400 */ 401 #define ER_DZ_TX_DESC_UPD_DWORD (ER_DZ_TX_DESC_UPD + 2 * 4) 402 #define ERF_DZ_TX_DESC_WPTR_DWORD_LBN (ERF_DZ_TX_DESC_WPTR_LBN - 2 * 32) 403 #define ERF_DZ_TX_DESC_WPTR_DWORD_WIDTH ERF_DZ_TX_DESC_WPTR_WIDTH 404 405 /* The workaround for bug 35388 requires multiplexing writes through 406 * the TX_DESC_UPD_DWORD address. 407 * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) 408 * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) 409 * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) 410 */ 411 #define ER_DD_EVQ_INDIRECT ER_DZ_TX_DESC_UPD_DWORD 412 #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 413 #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 414 #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 415 #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 416 #define ERF_DD_EVQ_IND_RPTR_LBN 0 417 #define ERF_DD_EVQ_IND_RPTR_WIDTH 8 418 #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 419 #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 420 #define EFE_DD_EVQ_IND_TIMER_FLAGS 3 421 #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 422 #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 423 #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 424 #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 425 426 /* TX_PIOBUF 427 * PIO buffer aperture (paged) 428 */ 429 #define ER_DZ_TX_PIOBUF 4096 430 #define ER_DZ_TX_PIOBUF_SIZE 2048 431 432 /* RX packet prefix */ 433 #define ES_DZ_RX_PREFIX_HASH_OFST 0 434 #define ES_DZ_RX_PREFIX_VLAN1_OFST 4 435 #define ES_DZ_RX_PREFIX_VLAN2_OFST 6 436 #define ES_DZ_RX_PREFIX_PKTLEN_OFST 8 437 #define ES_DZ_RX_PREFIX_TSTAMP_OFST 10 438 #define ES_DZ_RX_PREFIX_SIZE 14 439 440 #endif /* EFX_EF10_REGS_H */ 441