19c517165SBen Hutchings /**************************************************************************** 29c517165SBen Hutchings * Driver for Solarflare network controllers and boards 39c517165SBen Hutchings * Copyright 2012-2013 Solarflare Communications Inc. 49c517165SBen Hutchings * 59c517165SBen Hutchings * This program is free software; you can redistribute it and/or modify it 69c517165SBen Hutchings * under the terms of the GNU General Public License version 2 as published 79c517165SBen Hutchings * by the Free Software Foundation, incorporated herein by reference. 89c517165SBen Hutchings */ 99c517165SBen Hutchings 109c517165SBen Hutchings #ifndef EFX_EF10_REGS_H 119c517165SBen Hutchings #define EFX_EF10_REGS_H 129c517165SBen Hutchings 139c517165SBen Hutchings /* EF10 hardware architecture definitions have a name prefix following 149c517165SBen Hutchings * the format: 159c517165SBen Hutchings * 169c517165SBen Hutchings * E<type>_<min-rev><max-rev>_ 179c517165SBen Hutchings * 189c517165SBen Hutchings * The following <type> strings are used: 199c517165SBen Hutchings * 209c517165SBen Hutchings * MMIO register Host memory structure 219c517165SBen Hutchings * ------------------------------------------------------------- 229c517165SBen Hutchings * Address R 239c517165SBen Hutchings * Bitfield RF SF 249c517165SBen Hutchings * Enumerator FE SE 259c517165SBen Hutchings * 269c517165SBen Hutchings * <min-rev> is the first revision to which the definition applies: 279c517165SBen Hutchings * 289c517165SBen Hutchings * D: Huntington A0 299c517165SBen Hutchings * 309c517165SBen Hutchings * If the definition has been changed or removed in later revisions 319c517165SBen Hutchings * then <max-rev> is the last revision to which the definition applies; 329c517165SBen Hutchings * otherwise it is "Z". 339c517165SBen Hutchings */ 349c517165SBen Hutchings 359c517165SBen Hutchings /************************************************************************** 369c517165SBen Hutchings * 379c517165SBen Hutchings * EF10 registers and descriptors 389c517165SBen Hutchings * 399c517165SBen Hutchings ************************************************************************** 409c517165SBen Hutchings */ 419c517165SBen Hutchings 429c517165SBen Hutchings /* BIU_HW_REV_ID_REG: */ 439c517165SBen Hutchings #define ER_DZ_BIU_HW_REV_ID 0x00000000 449c517165SBen Hutchings #define ERF_DZ_HW_REV_ID_LBN 0 459c517165SBen Hutchings #define ERF_DZ_HW_REV_ID_WIDTH 32 469c517165SBen Hutchings 479c517165SBen Hutchings /* BIU_MC_SFT_STATUS_REG: */ 489c517165SBen Hutchings #define ER_DZ_BIU_MC_SFT_STATUS 0x00000010 499c517165SBen Hutchings #define ER_DZ_BIU_MC_SFT_STATUS_STEP 4 509c517165SBen Hutchings #define ER_DZ_BIU_MC_SFT_STATUS_ROWS 8 519c517165SBen Hutchings #define ERF_DZ_MC_SFT_STATUS_LBN 0 529c517165SBen Hutchings #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 539c517165SBen Hutchings 549c517165SBen Hutchings /* BIU_INT_ISR_REG: */ 559c517165SBen Hutchings #define ER_DZ_BIU_INT_ISR 0x00000090 569c517165SBen Hutchings #define ERF_DZ_ISR_REG_LBN 0 579c517165SBen Hutchings #define ERF_DZ_ISR_REG_WIDTH 32 589c517165SBen Hutchings 599c517165SBen Hutchings /* MC_DB_LWRD_REG: */ 609c517165SBen Hutchings #define ER_DZ_MC_DB_LWRD 0x00000200 619c517165SBen Hutchings #define ERF_DZ_MC_DOORBELL_L_LBN 0 629c517165SBen Hutchings #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 639c517165SBen Hutchings 649c517165SBen Hutchings /* MC_DB_HWRD_REG: */ 659c517165SBen Hutchings #define ER_DZ_MC_DB_HWRD 0x00000204 669c517165SBen Hutchings #define ERF_DZ_MC_DOORBELL_H_LBN 0 679c517165SBen Hutchings #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 689c517165SBen Hutchings 699c517165SBen Hutchings /* EVQ_RPTR_REG: */ 709c517165SBen Hutchings #define ER_DZ_EVQ_RPTR 0x00000400 719c517165SBen Hutchings #define ER_DZ_EVQ_RPTR_STEP 8192 729c517165SBen Hutchings #define ER_DZ_EVQ_RPTR_ROWS 2048 739c517165SBen Hutchings #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 749c517165SBen Hutchings #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 759c517165SBen Hutchings #define ERF_DZ_EVQ_RPTR_LBN 0 769c517165SBen Hutchings #define ERF_DZ_EVQ_RPTR_WIDTH 15 779c517165SBen Hutchings 789c517165SBen Hutchings /* EVQ_TMR_REG: */ 799c517165SBen Hutchings #define ER_DZ_EVQ_TMR 0x00000420 809c517165SBen Hutchings #define ER_DZ_EVQ_TMR_STEP 8192 819c517165SBen Hutchings #define ER_DZ_EVQ_TMR_ROWS 2048 829c517165SBen Hutchings #define ERF_DZ_TC_TIMER_MODE_LBN 14 839c517165SBen Hutchings #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 849c517165SBen Hutchings #define ERF_DZ_TC_TIMER_VAL_LBN 0 859c517165SBen Hutchings #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 869c517165SBen Hutchings 879c517165SBen Hutchings /* RX_DESC_UPD_REG: */ 889c517165SBen Hutchings #define ER_DZ_RX_DESC_UPD 0x00000830 899c517165SBen Hutchings #define ER_DZ_RX_DESC_UPD_STEP 8192 909c517165SBen Hutchings #define ER_DZ_RX_DESC_UPD_ROWS 2048 919c517165SBen Hutchings #define ERF_DZ_RX_DESC_WPTR_LBN 0 929c517165SBen Hutchings #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 939c517165SBen Hutchings 949c517165SBen Hutchings /* TX_DESC_UPD_REG: */ 959c517165SBen Hutchings #define ER_DZ_TX_DESC_UPD 0x00000a10 969c517165SBen Hutchings #define ER_DZ_TX_DESC_UPD_STEP 8192 979c517165SBen Hutchings #define ER_DZ_TX_DESC_UPD_ROWS 2048 989c517165SBen Hutchings #define ERF_DZ_RSVD_LBN 76 999c517165SBen Hutchings #define ERF_DZ_RSVD_WIDTH 20 1009c517165SBen Hutchings #define ERF_DZ_TX_DESC_WPTR_LBN 64 1019c517165SBen Hutchings #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 1029c517165SBen Hutchings #define ERF_DZ_TX_DESC_HWORD_LBN 32 1039c517165SBen Hutchings #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 1049c517165SBen Hutchings #define ERF_DZ_TX_DESC_LWORD_LBN 0 1059c517165SBen Hutchings #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 1069c517165SBen Hutchings 1079c517165SBen Hutchings /* DRIVER_EV */ 1089c517165SBen Hutchings #define ESF_DZ_DRV_CODE_LBN 60 1099c517165SBen Hutchings #define ESF_DZ_DRV_CODE_WIDTH 4 1109c517165SBen Hutchings #define ESF_DZ_DRV_SUB_CODE_LBN 56 1119c517165SBen Hutchings #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 1129c517165SBen Hutchings #define ESE_DZ_DRV_TIMER_EV 3 1139c517165SBen Hutchings #define ESE_DZ_DRV_START_UP_EV 2 1149c517165SBen Hutchings #define ESE_DZ_DRV_WAKE_UP_EV 1 1159c517165SBen Hutchings #define ESF_DZ_DRV_SUB_DATA_LBN 0 1169c517165SBen Hutchings #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 1179c517165SBen Hutchings #define ESF_DZ_DRV_EVQ_ID_LBN 0 1189c517165SBen Hutchings #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 1199c517165SBen Hutchings #define ESF_DZ_DRV_TMR_ID_LBN 0 1209c517165SBen Hutchings #define ESF_DZ_DRV_TMR_ID_WIDTH 14 1219c517165SBen Hutchings 1229c517165SBen Hutchings /* EVENT_ENTRY */ 1239c517165SBen Hutchings #define ESF_DZ_EV_CODE_LBN 60 1249c517165SBen Hutchings #define ESF_DZ_EV_CODE_WIDTH 4 1259c517165SBen Hutchings #define ESE_DZ_EV_CODE_MCDI_EV 12 1269c517165SBen Hutchings #define ESE_DZ_EV_CODE_DRIVER_EV 5 1279c517165SBen Hutchings #define ESE_DZ_EV_CODE_TX_EV 2 1289c517165SBen Hutchings #define ESE_DZ_EV_CODE_RX_EV 0 1299c517165SBen Hutchings #define ESE_DZ_OTHER other 1309c517165SBen Hutchings #define ESF_DZ_EV_DATA_LBN 0 1319c517165SBen Hutchings #define ESF_DZ_EV_DATA_WIDTH 60 1329c517165SBen Hutchings 1339c517165SBen Hutchings /* MC_EVENT */ 1349c517165SBen Hutchings #define ESF_DZ_MC_CODE_LBN 60 1359c517165SBen Hutchings #define ESF_DZ_MC_CODE_WIDTH 4 1369c517165SBen Hutchings #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 1379c517165SBen Hutchings #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 1389c517165SBen Hutchings #define ESF_DZ_MC_DROP_EVENT_LBN 58 1399c517165SBen Hutchings #define ESF_DZ_MC_DROP_EVENT_WIDTH 1 1409c517165SBen Hutchings #define ESF_DZ_MC_SOFT_LBN 0 1419c517165SBen Hutchings #define ESF_DZ_MC_SOFT_WIDTH 58 1429c517165SBen Hutchings 1439c517165SBen Hutchings /* RX_EVENT */ 1449c517165SBen Hutchings #define ESF_DZ_RX_CODE_LBN 60 1459c517165SBen Hutchings #define ESF_DZ_RX_CODE_WIDTH 4 1469c517165SBen Hutchings #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 1479c517165SBen Hutchings #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 1489c517165SBen Hutchings #define ESF_DZ_RX_DROP_EVENT_LBN 58 1499c517165SBen Hutchings #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 1509c517165SBen Hutchings #define ESF_DZ_RX_EV_RSVD2_LBN 54 1519c517165SBen Hutchings #define ESF_DZ_RX_EV_RSVD2_WIDTH 4 1529c517165SBen Hutchings #define ESF_DZ_RX_EV_SOFT2_LBN 52 1539c517165SBen Hutchings #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 1549c517165SBen Hutchings #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 1559c517165SBen Hutchings #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 1569c517165SBen Hutchings #define ESF_DZ_RX_L4_CLASS_LBN 45 1579c517165SBen Hutchings #define ESF_DZ_RX_L4_CLASS_WIDTH 3 1589c517165SBen Hutchings #define ESE_DZ_L4_CLASS_RSVD7 7 1599c517165SBen Hutchings #define ESE_DZ_L4_CLASS_RSVD6 6 1609c517165SBen Hutchings #define ESE_DZ_L4_CLASS_RSVD5 5 1619c517165SBen Hutchings #define ESE_DZ_L4_CLASS_RSVD4 4 1629c517165SBen Hutchings #define ESE_DZ_L4_CLASS_RSVD3 3 1639c517165SBen Hutchings #define ESE_DZ_L4_CLASS_UDP 2 1649c517165SBen Hutchings #define ESE_DZ_L4_CLASS_TCP 1 1659c517165SBen Hutchings #define ESE_DZ_L4_CLASS_UNKNOWN 0 1669c517165SBen Hutchings #define ESF_DZ_RX_L3_CLASS_LBN 42 1679c517165SBen Hutchings #define ESF_DZ_RX_L3_CLASS_WIDTH 3 1689c517165SBen Hutchings #define ESE_DZ_L3_CLASS_RSVD7 7 1699c517165SBen Hutchings #define ESE_DZ_L3_CLASS_IP6_FRAG 6 1709c517165SBen Hutchings #define ESE_DZ_L3_CLASS_ARP 5 1719c517165SBen Hutchings #define ESE_DZ_L3_CLASS_IP4_FRAG 4 1729c517165SBen Hutchings #define ESE_DZ_L3_CLASS_FCOE 3 1739c517165SBen Hutchings #define ESE_DZ_L3_CLASS_IP6 2 1749c517165SBen Hutchings #define ESE_DZ_L3_CLASS_IP4 1 1759c517165SBen Hutchings #define ESE_DZ_L3_CLASS_UNKNOWN 0 1769c517165SBen Hutchings #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 1779c517165SBen Hutchings #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 1789c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 1799c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 1809c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 1819c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 1829c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 1839c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 1849c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 1859c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_NONE 0 1869c517165SBen Hutchings #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 1879c517165SBen Hutchings #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 1889c517165SBen Hutchings #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 1899c517165SBen Hutchings #define ESE_DZ_ETH_BASE_CLASS_LLC 1 1909c517165SBen Hutchings #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 1919c517165SBen Hutchings #define ESF_DZ_RX_MAC_CLASS_LBN 35 1929c517165SBen Hutchings #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 1939c517165SBen Hutchings #define ESE_DZ_MAC_CLASS_MCAST 1 1949c517165SBen Hutchings #define ESE_DZ_MAC_CLASS_UCAST 0 1959c517165SBen Hutchings #define ESF_DZ_RX_EV_SOFT1_LBN 32 1969c517165SBen Hutchings #define ESF_DZ_RX_EV_SOFT1_WIDTH 3 1979c517165SBen Hutchings #define ESF_DZ_RX_EV_RSVD1_LBN 31 1989c517165SBen Hutchings #define ESF_DZ_RX_EV_RSVD1_WIDTH 1 1999c517165SBen Hutchings #define ESF_DZ_RX_ABORT_LBN 30 2009c517165SBen Hutchings #define ESF_DZ_RX_ABORT_WIDTH 1 2019c517165SBen Hutchings #define ESF_DZ_RX_ECC_ERR_LBN 29 2029c517165SBen Hutchings #define ESF_DZ_RX_ECC_ERR_WIDTH 1 2039c517165SBen Hutchings #define ESF_DZ_RX_CRC1_ERR_LBN 28 2049c517165SBen Hutchings #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 2059c517165SBen Hutchings #define ESF_DZ_RX_CRC0_ERR_LBN 27 2069c517165SBen Hutchings #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 2079c517165SBen Hutchings #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 2089c517165SBen Hutchings #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 2099c517165SBen Hutchings #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 2109c517165SBen Hutchings #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 2119c517165SBen Hutchings #define ESF_DZ_RX_ECRC_ERR_LBN 24 2129c517165SBen Hutchings #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 2139c517165SBen Hutchings #define ESF_DZ_RX_QLABEL_LBN 16 2149c517165SBen Hutchings #define ESF_DZ_RX_QLABEL_WIDTH 5 2159c517165SBen Hutchings #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 2169c517165SBen Hutchings #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 2179c517165SBen Hutchings #define ESF_DZ_RX_CONT_LBN 14 2189c517165SBen Hutchings #define ESF_DZ_RX_CONT_WIDTH 1 2199c517165SBen Hutchings #define ESF_DZ_RX_BYTES_LBN 0 2209c517165SBen Hutchings #define ESF_DZ_RX_BYTES_WIDTH 14 2219c517165SBen Hutchings 2229c517165SBen Hutchings /* RX_KER_DESC */ 2239c517165SBen Hutchings #define ESF_DZ_RX_KER_RESERVED_LBN 62 2249c517165SBen Hutchings #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 2259c517165SBen Hutchings #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 2269c517165SBen Hutchings #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 2279c517165SBen Hutchings #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 2289c517165SBen Hutchings #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 2299c517165SBen Hutchings 2309c517165SBen Hutchings /* RX_USER_DESC */ 2319c517165SBen Hutchings #define ESF_DZ_RX_USR_RESERVED_LBN 62 2329c517165SBen Hutchings #define ESF_DZ_RX_USR_RESERVED_WIDTH 2 2339c517165SBen Hutchings #define ESF_DZ_RX_USR_BYTE_CNT_LBN 48 2349c517165SBen Hutchings #define ESF_DZ_RX_USR_BYTE_CNT_WIDTH 14 2359c517165SBen Hutchings #define ESF_DZ_RX_USR_BUF_PAGE_SIZE_LBN 44 2369c517165SBen Hutchings #define ESF_DZ_RX_USR_BUF_PAGE_SIZE_WIDTH 4 2379c517165SBen Hutchings #define ESE_DZ_USR_BUF_PAGE_SZ_4MB 10 2389c517165SBen Hutchings #define ESE_DZ_USR_BUF_PAGE_SZ_1MB 8 2399c517165SBen Hutchings #define ESE_DZ_USR_BUF_PAGE_SZ_64KB 4 2409c517165SBen Hutchings #define ESE_DZ_USR_BUF_PAGE_SZ_4KB 0 2419c517165SBen Hutchings #define ESF_DZ_RX_USR_BUF_ID_OFFSET_LBN 0 2429c517165SBen Hutchings #define ESF_DZ_RX_USR_BUF_ID_OFFSET_WIDTH 44 2439c517165SBen Hutchings #define ESF_DZ_RX_USR_4KBPS_BUF_ID_LBN 12 2449c517165SBen Hutchings #define ESF_DZ_RX_USR_4KBPS_BUF_ID_WIDTH 32 2459c517165SBen Hutchings #define ESF_DZ_RX_USR_64KBPS_BUF_ID_LBN 16 2469c517165SBen Hutchings #define ESF_DZ_RX_USR_64KBPS_BUF_ID_WIDTH 28 2479c517165SBen Hutchings #define ESF_DZ_RX_USR_1MBPS_BUF_ID_LBN 20 2489c517165SBen Hutchings #define ESF_DZ_RX_USR_1MBPS_BUF_ID_WIDTH 24 2499c517165SBen Hutchings #define ESF_DZ_RX_USR_4MBPS_BUF_ID_LBN 22 2509c517165SBen Hutchings #define ESF_DZ_RX_USR_4MBPS_BUF_ID_WIDTH 22 2519c517165SBen Hutchings #define ESF_DZ_RX_USR_4MBPS_BYTE_OFFSET_LBN 0 2529c517165SBen Hutchings #define ESF_DZ_RX_USR_4MBPS_BYTE_OFFSET_WIDTH 22 2539c517165SBen Hutchings #define ESF_DZ_RX_USR_1MBPS_BYTE_OFFSET_LBN 0 2549c517165SBen Hutchings #define ESF_DZ_RX_USR_1MBPS_BYTE_OFFSET_WIDTH 20 2559c517165SBen Hutchings #define ESF_DZ_RX_USR_64KBPS_BYTE_OFFSET_LBN 0 2569c517165SBen Hutchings #define ESF_DZ_RX_USR_64KBPS_BYTE_OFFSET_WIDTH 16 2579c517165SBen Hutchings #define ESF_DZ_RX_USR_4KBPS_BYTE_OFFSET_LBN 0 2589c517165SBen Hutchings #define ESF_DZ_RX_USR_4KBPS_BYTE_OFFSET_WIDTH 12 2599c517165SBen Hutchings 2609c517165SBen Hutchings /* TX_CSUM_TSTAMP_DESC */ 2619c517165SBen Hutchings #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 2629c517165SBen Hutchings #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 2639c517165SBen Hutchings #define ESF_DZ_TX_OPTION_TYPE_LBN 60 2649c517165SBen Hutchings #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 2659c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_TSO 7 2669c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_VLAN 6 2679c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 2689c517165SBen Hutchings #define ESF_DZ_TX_TIMESTAMP_LBN 5 2699c517165SBen Hutchings #define ESF_DZ_TX_TIMESTAMP_WIDTH 1 2709c517165SBen Hutchings #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 2719c517165SBen Hutchings #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 2729c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 2739c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 2749c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 2759c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 2769c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_FCOE 1 2779c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_OFF 0 2789c517165SBen Hutchings #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 2799c517165SBen Hutchings #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 2809c517165SBen Hutchings #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 2819c517165SBen Hutchings #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 2829c517165SBen Hutchings 2839c517165SBen Hutchings /* TX_EVENT */ 2849c517165SBen Hutchings #define ESF_DZ_TX_CODE_LBN 60 2859c517165SBen Hutchings #define ESF_DZ_TX_CODE_WIDTH 4 2869c517165SBen Hutchings #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 2879c517165SBen Hutchings #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 2889c517165SBen Hutchings #define ESF_DZ_TX_DROP_EVENT_LBN 58 2899c517165SBen Hutchings #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 2909c517165SBen Hutchings #define ESF_DZ_TX_EV_RSVD_LBN 48 2919c517165SBen Hutchings #define ESF_DZ_TX_EV_RSVD_WIDTH 10 2929c517165SBen Hutchings #define ESF_DZ_TX_SOFT2_LBN 32 2939c517165SBen Hutchings #define ESF_DZ_TX_SOFT2_WIDTH 16 2949c517165SBen Hutchings #define ESF_DZ_TX_CAN_MERGE_LBN 31 2959c517165SBen Hutchings #define ESF_DZ_TX_CAN_MERGE_WIDTH 1 2969c517165SBen Hutchings #define ESF_DZ_TX_SOFT1_LBN 24 2979c517165SBen Hutchings #define ESF_DZ_TX_SOFT1_WIDTH 7 2989c517165SBen Hutchings #define ESF_DZ_TX_QLABEL_LBN 16 2999c517165SBen Hutchings #define ESF_DZ_TX_QLABEL_WIDTH 5 3009c517165SBen Hutchings #define ESF_DZ_TX_DESCR_INDX_LBN 0 3019c517165SBen Hutchings #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 3029c517165SBen Hutchings 3039c517165SBen Hutchings /* TX_KER_DESC */ 3049c517165SBen Hutchings #define ESF_DZ_TX_KER_TYPE_LBN 63 3059c517165SBen Hutchings #define ESF_DZ_TX_KER_TYPE_WIDTH 1 3069c517165SBen Hutchings #define ESF_DZ_TX_KER_CONT_LBN 62 3079c517165SBen Hutchings #define ESF_DZ_TX_KER_CONT_WIDTH 1 3089c517165SBen Hutchings #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 3099c517165SBen Hutchings #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 3109c517165SBen Hutchings #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 3119c517165SBen Hutchings #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 3129c517165SBen Hutchings 3139c517165SBen Hutchings /* TX_PIO_DESC */ 3149c517165SBen Hutchings #define ESF_DZ_TX_PIO_TYPE_LBN 63 3159c517165SBen Hutchings #define ESF_DZ_TX_PIO_TYPE_WIDTH 1 3169c517165SBen Hutchings #define ESF_DZ_TX_PIO_OPT_LBN 60 3179c517165SBen Hutchings #define ESF_DZ_TX_PIO_OPT_WIDTH 3 3189c517165SBen Hutchings #define ESF_DZ_TX_PIO_CONT_LBN 59 3199c517165SBen Hutchings #define ESF_DZ_TX_PIO_CONT_WIDTH 1 3209c517165SBen Hutchings #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 3219c517165SBen Hutchings #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 3229c517165SBen Hutchings #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 3239c517165SBen Hutchings #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 3249c517165SBen Hutchings 3259c517165SBen Hutchings /* TX_TSO_DESC */ 3269c517165SBen Hutchings #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 3279c517165SBen Hutchings #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 3289c517165SBen Hutchings #define ESF_DZ_TX_OPTION_TYPE_LBN 60 3299c517165SBen Hutchings #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 3309c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_TSO 7 3319c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_VLAN 6 3329c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 3339c517165SBen Hutchings #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 3349c517165SBen Hutchings #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 3359c517165SBen Hutchings #define ESF_DZ_TX_TSO_IP_ID_LBN 32 3369c517165SBen Hutchings #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 3379c517165SBen Hutchings #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 3389c517165SBen Hutchings #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 3399c517165SBen Hutchings 3409c517165SBen Hutchings /* TX_USER_DESC */ 3419c517165SBen Hutchings #define ESF_DZ_TX_USR_TYPE_LBN 63 3429c517165SBen Hutchings #define ESF_DZ_TX_USR_TYPE_WIDTH 1 3439c517165SBen Hutchings #define ESF_DZ_TX_USR_CONT_LBN 62 3449c517165SBen Hutchings #define ESF_DZ_TX_USR_CONT_WIDTH 1 3459c517165SBen Hutchings #define ESF_DZ_TX_USR_BYTE_CNT_LBN 48 3469c517165SBen Hutchings #define ESF_DZ_TX_USR_BYTE_CNT_WIDTH 14 3479c517165SBen Hutchings #define ESF_DZ_TX_USR_BUF_PAGE_SIZE_LBN 44 3489c517165SBen Hutchings #define ESF_DZ_TX_USR_BUF_PAGE_SIZE_WIDTH 4 3499c517165SBen Hutchings #define ESE_DZ_USR_BUF_PAGE_SZ_4MB 10 3509c517165SBen Hutchings #define ESE_DZ_USR_BUF_PAGE_SZ_1MB 8 3519c517165SBen Hutchings #define ESE_DZ_USR_BUF_PAGE_SZ_64KB 4 3529c517165SBen Hutchings #define ESE_DZ_USR_BUF_PAGE_SZ_4KB 0 3539c517165SBen Hutchings #define ESF_DZ_TX_USR_BUF_ID_OFFSET_LBN 0 3549c517165SBen Hutchings #define ESF_DZ_TX_USR_BUF_ID_OFFSET_WIDTH 44 3559c517165SBen Hutchings #define ESF_DZ_TX_USR_4KBPS_BUF_ID_LBN 12 3569c517165SBen Hutchings #define ESF_DZ_TX_USR_4KBPS_BUF_ID_WIDTH 32 3579c517165SBen Hutchings #define ESF_DZ_TX_USR_64KBPS_BUF_ID_LBN 16 3589c517165SBen Hutchings #define ESF_DZ_TX_USR_64KBPS_BUF_ID_WIDTH 28 3599c517165SBen Hutchings #define ESF_DZ_TX_USR_1MBPS_BUF_ID_LBN 20 3609c517165SBen Hutchings #define ESF_DZ_TX_USR_1MBPS_BUF_ID_WIDTH 24 3619c517165SBen Hutchings #define ESF_DZ_TX_USR_4MBPS_BUF_ID_LBN 22 3629c517165SBen Hutchings #define ESF_DZ_TX_USR_4MBPS_BUF_ID_WIDTH 22 3639c517165SBen Hutchings #define ESF_DZ_TX_USR_4MBPS_BYTE_OFFSET_LBN 0 3649c517165SBen Hutchings #define ESF_DZ_TX_USR_4MBPS_BYTE_OFFSET_WIDTH 22 3659c517165SBen Hutchings #define ESF_DZ_TX_USR_1MBPS_BYTE_OFFSET_LBN 0 3669c517165SBen Hutchings #define ESF_DZ_TX_USR_1MBPS_BYTE_OFFSET_WIDTH 20 3679c517165SBen Hutchings #define ESF_DZ_TX_USR_64KBPS_BYTE_OFFSET_LBN 0 3689c517165SBen Hutchings #define ESF_DZ_TX_USR_64KBPS_BYTE_OFFSET_WIDTH 16 3699c517165SBen Hutchings #define ESF_DZ_TX_USR_4KBPS_BYTE_OFFSET_LBN 0 3709c517165SBen Hutchings #define ESF_DZ_TX_USR_4KBPS_BYTE_OFFSET_WIDTH 12 3719c517165SBen Hutchings /*************************************************************************/ 3729c517165SBen Hutchings 3739c517165SBen Hutchings /* TX_DESC_UPD_REG: Transmit descriptor update register. 3749c517165SBen Hutchings * We may write just one dword of these registers. 3759c517165SBen Hutchings */ 3769c517165SBen Hutchings #define ER_DZ_TX_DESC_UPD_DWORD (ER_DZ_TX_DESC_UPD + 2 * 4) 3779c517165SBen Hutchings #define ERF_DZ_TX_DESC_WPTR_DWORD_LBN (ERF_DZ_TX_DESC_WPTR_LBN - 2 * 32) 3789c517165SBen Hutchings #define ERF_DZ_TX_DESC_WPTR_DWORD_WIDTH ERF_DZ_TX_DESC_WPTR_WIDTH 3799c517165SBen Hutchings 3809c517165SBen Hutchings /* The workaround for bug 35388 requires multiplexing writes through 3819c517165SBen Hutchings * the TX_DESC_UPD_DWORD address. 3829c517165SBen Hutchings * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) 3839c517165SBen Hutchings * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) 3849c517165SBen Hutchings * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) 3859c517165SBen Hutchings */ 3869c517165SBen Hutchings #define ER_DD_EVQ_INDIRECT ER_DZ_TX_DESC_UPD_DWORD 3879c517165SBen Hutchings #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 3889c517165SBen Hutchings #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 3899c517165SBen Hutchings #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 3909c517165SBen Hutchings #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 3919c517165SBen Hutchings #define ERF_DD_EVQ_IND_RPTR_LBN 0 3929c517165SBen Hutchings #define ERF_DD_EVQ_IND_RPTR_WIDTH 8 3939c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 3949c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 3959c517165SBen Hutchings #define EFE_DD_EVQ_IND_TIMER_FLAGS 3 3969c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 3979c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 3989c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 3999c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 4009c517165SBen Hutchings 4019c517165SBen Hutchings /* TX_PIOBUF 4029c517165SBen Hutchings * PIO buffer aperture (paged) 4039c517165SBen Hutchings */ 4049c517165SBen Hutchings #define ER_DZ_TX_PIOBUF 4096 4059c517165SBen Hutchings #define ER_DZ_TX_PIOBUF_SIZE 2048 4069c517165SBen Hutchings 4079c517165SBen Hutchings /* RX packet prefix */ 4089c517165SBen Hutchings #define ES_DZ_RX_PREFIX_HASH_OFST 0 4099c517165SBen Hutchings #define ES_DZ_RX_PREFIX_VLAN1_OFST 4 4109c517165SBen Hutchings #define ES_DZ_RX_PREFIX_VLAN2_OFST 6 4119c517165SBen Hutchings #define ES_DZ_RX_PREFIX_PKTLEN_OFST 8 4129c517165SBen Hutchings #define ES_DZ_RX_PREFIX_TSTAMP_OFST 10 4139c517165SBen Hutchings #define ES_DZ_RX_PREFIX_SIZE 14 4149c517165SBen Hutchings 4159c517165SBen Hutchings #endif /* EFX_EF10_REGS_H */ 416