1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 29c517165SBen Hutchings /**************************************************************************** 39c517165SBen Hutchings * Driver for Solarflare network controllers and boards 4d8d8ccf2SBert Kenward * Copyright 2012-2017 Solarflare Communications Inc. 59c517165SBen Hutchings */ 69c517165SBen Hutchings 79c517165SBen Hutchings #ifndef EFX_EF10_REGS_H 89c517165SBen Hutchings #define EFX_EF10_REGS_H 99c517165SBen Hutchings 109c517165SBen Hutchings /* EF10 hardware architecture definitions have a name prefix following 119c517165SBen Hutchings * the format: 129c517165SBen Hutchings * 139c517165SBen Hutchings * E<type>_<min-rev><max-rev>_ 149c517165SBen Hutchings * 159c517165SBen Hutchings * The following <type> strings are used: 169c517165SBen Hutchings * 179c517165SBen Hutchings * MMIO register Host memory structure 189c517165SBen Hutchings * ------------------------------------------------------------- 199c517165SBen Hutchings * Address R 209c517165SBen Hutchings * Bitfield RF SF 219c517165SBen Hutchings * Enumerator FE SE 229c517165SBen Hutchings * 239c517165SBen Hutchings * <min-rev> is the first revision to which the definition applies: 249c517165SBen Hutchings * 259c517165SBen Hutchings * D: Huntington A0 269c517165SBen Hutchings * 279c517165SBen Hutchings * If the definition has been changed or removed in later revisions 289c517165SBen Hutchings * then <max-rev> is the last revision to which the definition applies; 299c517165SBen Hutchings * otherwise it is "Z". 309c517165SBen Hutchings */ 319c517165SBen Hutchings 329c517165SBen Hutchings /************************************************************************** 339c517165SBen Hutchings * 349c517165SBen Hutchings * EF10 registers and descriptors 359c517165SBen Hutchings * 369c517165SBen Hutchings ************************************************************************** 379c517165SBen Hutchings */ 389c517165SBen Hutchings 399c517165SBen Hutchings /* BIU_HW_REV_ID_REG: */ 409c517165SBen Hutchings #define ER_DZ_BIU_HW_REV_ID 0x00000000 419c517165SBen Hutchings #define ERF_DZ_HW_REV_ID_LBN 0 429c517165SBen Hutchings #define ERF_DZ_HW_REV_ID_WIDTH 32 439c517165SBen Hutchings 449c517165SBen Hutchings /* BIU_MC_SFT_STATUS_REG: */ 459c517165SBen Hutchings #define ER_DZ_BIU_MC_SFT_STATUS 0x00000010 469c517165SBen Hutchings #define ER_DZ_BIU_MC_SFT_STATUS_STEP 4 479c517165SBen Hutchings #define ER_DZ_BIU_MC_SFT_STATUS_ROWS 8 489c517165SBen Hutchings #define ERF_DZ_MC_SFT_STATUS_LBN 0 499c517165SBen Hutchings #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 509c517165SBen Hutchings 519c517165SBen Hutchings /* BIU_INT_ISR_REG: */ 529c517165SBen Hutchings #define ER_DZ_BIU_INT_ISR 0x00000090 539c517165SBen Hutchings #define ERF_DZ_ISR_REG_LBN 0 549c517165SBen Hutchings #define ERF_DZ_ISR_REG_WIDTH 32 559c517165SBen Hutchings 569c517165SBen Hutchings /* MC_DB_LWRD_REG: */ 579c517165SBen Hutchings #define ER_DZ_MC_DB_LWRD 0x00000200 589c517165SBen Hutchings #define ERF_DZ_MC_DOORBELL_L_LBN 0 599c517165SBen Hutchings #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 609c517165SBen Hutchings 619c517165SBen Hutchings /* MC_DB_HWRD_REG: */ 629c517165SBen Hutchings #define ER_DZ_MC_DB_HWRD 0x00000204 639c517165SBen Hutchings #define ERF_DZ_MC_DOORBELL_H_LBN 0 649c517165SBen Hutchings #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 659c517165SBen Hutchings 669c517165SBen Hutchings /* EVQ_RPTR_REG: */ 679c517165SBen Hutchings #define ER_DZ_EVQ_RPTR 0x00000400 689c517165SBen Hutchings #define ER_DZ_EVQ_RPTR_STEP 8192 699c517165SBen Hutchings #define ER_DZ_EVQ_RPTR_ROWS 2048 709c517165SBen Hutchings #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 719c517165SBen Hutchings #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 729c517165SBen Hutchings #define ERF_DZ_EVQ_RPTR_LBN 0 739c517165SBen Hutchings #define ERF_DZ_EVQ_RPTR_WIDTH 15 749c517165SBen Hutchings 759c517165SBen Hutchings /* EVQ_TMR_REG: */ 769c517165SBen Hutchings #define ER_DZ_EVQ_TMR 0x00000420 779c517165SBen Hutchings #define ER_DZ_EVQ_TMR_STEP 8192 789c517165SBen Hutchings #define ER_DZ_EVQ_TMR_ROWS 2048 79d8d8ccf2SBert Kenward #define ERF_FZ_TC_TMR_REL_VAL_LBN 16 80d8d8ccf2SBert Kenward #define ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 819c517165SBen Hutchings #define ERF_DZ_TC_TIMER_MODE_LBN 14 829c517165SBen Hutchings #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 839c517165SBen Hutchings #define ERF_DZ_TC_TIMER_VAL_LBN 0 849c517165SBen Hutchings #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 859c517165SBen Hutchings 869c517165SBen Hutchings /* RX_DESC_UPD_REG: */ 879c517165SBen Hutchings #define ER_DZ_RX_DESC_UPD 0x00000830 889c517165SBen Hutchings #define ER_DZ_RX_DESC_UPD_STEP 8192 899c517165SBen Hutchings #define ER_DZ_RX_DESC_UPD_ROWS 2048 909c517165SBen Hutchings #define ERF_DZ_RX_DESC_WPTR_LBN 0 919c517165SBen Hutchings #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 929c517165SBen Hutchings 939c517165SBen Hutchings /* TX_DESC_UPD_REG: */ 949c517165SBen Hutchings #define ER_DZ_TX_DESC_UPD 0x00000a10 959c517165SBen Hutchings #define ER_DZ_TX_DESC_UPD_STEP 8192 969c517165SBen Hutchings #define ER_DZ_TX_DESC_UPD_ROWS 2048 979c517165SBen Hutchings #define ERF_DZ_RSVD_LBN 76 989c517165SBen Hutchings #define ERF_DZ_RSVD_WIDTH 20 999c517165SBen Hutchings #define ERF_DZ_TX_DESC_WPTR_LBN 64 1009c517165SBen Hutchings #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 1019c517165SBen Hutchings #define ERF_DZ_TX_DESC_HWORD_LBN 32 1029c517165SBen Hutchings #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 1039c517165SBen Hutchings #define ERF_DZ_TX_DESC_LWORD_LBN 0 1049c517165SBen Hutchings #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 1059c517165SBen Hutchings 1069c517165SBen Hutchings /* DRIVER_EV */ 1079c517165SBen Hutchings #define ESF_DZ_DRV_CODE_LBN 60 1089c517165SBen Hutchings #define ESF_DZ_DRV_CODE_WIDTH 4 1099c517165SBen Hutchings #define ESF_DZ_DRV_SUB_CODE_LBN 56 1109c517165SBen Hutchings #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 1119c517165SBen Hutchings #define ESE_DZ_DRV_TIMER_EV 3 1129c517165SBen Hutchings #define ESE_DZ_DRV_START_UP_EV 2 1139c517165SBen Hutchings #define ESE_DZ_DRV_WAKE_UP_EV 1 1149c517165SBen Hutchings #define ESF_DZ_DRV_SUB_DATA_LBN 0 1159c517165SBen Hutchings #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 1169c517165SBen Hutchings #define ESF_DZ_DRV_EVQ_ID_LBN 0 1179c517165SBen Hutchings #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 1189c517165SBen Hutchings #define ESF_DZ_DRV_TMR_ID_LBN 0 1199c517165SBen Hutchings #define ESF_DZ_DRV_TMR_ID_WIDTH 14 1209c517165SBen Hutchings 1219c517165SBen Hutchings /* EVENT_ENTRY */ 1229c517165SBen Hutchings #define ESF_DZ_EV_CODE_LBN 60 1239c517165SBen Hutchings #define ESF_DZ_EV_CODE_WIDTH 4 1249c517165SBen Hutchings #define ESE_DZ_EV_CODE_MCDI_EV 12 1259c517165SBen Hutchings #define ESE_DZ_EV_CODE_DRIVER_EV 5 1269c517165SBen Hutchings #define ESE_DZ_EV_CODE_TX_EV 2 1279c517165SBen Hutchings #define ESE_DZ_EV_CODE_RX_EV 0 1289c517165SBen Hutchings #define ESE_DZ_OTHER other 1299c517165SBen Hutchings #define ESF_DZ_EV_DATA_LBN 0 1309c517165SBen Hutchings #define ESF_DZ_EV_DATA_WIDTH 60 1319c517165SBen Hutchings 1329c517165SBen Hutchings /* MC_EVENT */ 1339c517165SBen Hutchings #define ESF_DZ_MC_CODE_LBN 60 1349c517165SBen Hutchings #define ESF_DZ_MC_CODE_WIDTH 4 1359c517165SBen Hutchings #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 1369c517165SBen Hutchings #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 1379c517165SBen Hutchings #define ESF_DZ_MC_DROP_EVENT_LBN 58 1389c517165SBen Hutchings #define ESF_DZ_MC_DROP_EVENT_WIDTH 1 1399c517165SBen Hutchings #define ESF_DZ_MC_SOFT_LBN 0 1409c517165SBen Hutchings #define ESF_DZ_MC_SOFT_WIDTH 58 1419c517165SBen Hutchings 1429c517165SBen Hutchings /* RX_EVENT */ 1439c517165SBen Hutchings #define ESF_DZ_RX_CODE_LBN 60 1449c517165SBen Hutchings #define ESF_DZ_RX_CODE_WIDTH 4 1459c517165SBen Hutchings #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 1469c517165SBen Hutchings #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 1479c517165SBen Hutchings #define ESF_DZ_RX_DROP_EVENT_LBN 58 1489c517165SBen Hutchings #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 149e17705c4SEdward Cree #define ESF_DD_RX_EV_RSVD2_LBN 54 150e17705c4SEdward Cree #define ESF_DD_RX_EV_RSVD2_WIDTH 4 151e17705c4SEdward Cree #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 152e17705c4SEdward Cree #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 153e17705c4SEdward Cree #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56 154e17705c4SEdward Cree #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1 155e17705c4SEdward Cree #define ESF_EZ_RX_EV_RSVD2_LBN 54 156e17705c4SEdward Cree #define ESF_EZ_RX_EV_RSVD2_WIDTH 2 1579c517165SBen Hutchings #define ESF_DZ_RX_EV_SOFT2_LBN 52 1589c517165SBen Hutchings #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 1599c517165SBen Hutchings #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 1609c517165SBen Hutchings #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 161d8d8ccf2SBert Kenward #define ESF_DE_RX_L4_CLASS_LBN 45 162d8d8ccf2SBert Kenward #define ESF_DE_RX_L4_CLASS_WIDTH 3 163d8d8ccf2SBert Kenward #define ESE_DE_L4_CLASS_RSVD7 7 164d8d8ccf2SBert Kenward #define ESE_DE_L4_CLASS_RSVD6 6 165d8d8ccf2SBert Kenward #define ESE_DE_L4_CLASS_RSVD5 5 166d8d8ccf2SBert Kenward #define ESE_DE_L4_CLASS_RSVD4 4 167d8d8ccf2SBert Kenward #define ESE_DE_L4_CLASS_RSVD3 3 168d8d8ccf2SBert Kenward #define ESE_DE_L4_CLASS_UDP 2 169d8d8ccf2SBert Kenward #define ESE_DE_L4_CLASS_TCP 1 170d8d8ccf2SBert Kenward #define ESE_DE_L4_CLASS_UNKNOWN 0 171d8d8ccf2SBert Kenward #define ESF_FZ_RX_FASTPD_INDCTR_LBN 47 172d8d8ccf2SBert Kenward #define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1 173d8d8ccf2SBert Kenward #define ESF_FZ_RX_L4_CLASS_LBN 45 174d8d8ccf2SBert Kenward #define ESF_FZ_RX_L4_CLASS_WIDTH 2 175d8d8ccf2SBert Kenward #define ESE_FZ_L4_CLASS_RSVD3 3 176d8d8ccf2SBert Kenward #define ESE_FZ_L4_CLASS_UDP 2 177d8d8ccf2SBert Kenward #define ESE_FZ_L4_CLASS_TCP 1 178d8d8ccf2SBert Kenward #define ESE_FZ_L4_CLASS_UNKNOWN 0 1799c517165SBen Hutchings #define ESF_DZ_RX_L3_CLASS_LBN 42 1809c517165SBen Hutchings #define ESF_DZ_RX_L3_CLASS_WIDTH 3 1819c517165SBen Hutchings #define ESE_DZ_L3_CLASS_RSVD7 7 1829c517165SBen Hutchings #define ESE_DZ_L3_CLASS_IP6_FRAG 6 1839c517165SBen Hutchings #define ESE_DZ_L3_CLASS_ARP 5 1849c517165SBen Hutchings #define ESE_DZ_L3_CLASS_IP4_FRAG 4 1859c517165SBen Hutchings #define ESE_DZ_L3_CLASS_FCOE 3 1869c517165SBen Hutchings #define ESE_DZ_L3_CLASS_IP6 2 1879c517165SBen Hutchings #define ESE_DZ_L3_CLASS_IP4 1 1889c517165SBen Hutchings #define ESE_DZ_L3_CLASS_UNKNOWN 0 1899c517165SBen Hutchings #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 1909c517165SBen Hutchings #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 1919c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 1929c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 1939c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 1949c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 1959c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 1969c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 1979c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 1989c517165SBen Hutchings #define ESE_DZ_ETH_TAG_CLASS_NONE 0 1999c517165SBen Hutchings #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 2009c517165SBen Hutchings #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 2019c517165SBen Hutchings #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 2029c517165SBen Hutchings #define ESE_DZ_ETH_BASE_CLASS_LLC 1 2039c517165SBen Hutchings #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 2049c517165SBen Hutchings #define ESF_DZ_RX_MAC_CLASS_LBN 35 2059c517165SBen Hutchings #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 2069c517165SBen Hutchings #define ESE_DZ_MAC_CLASS_MCAST 1 2079c517165SBen Hutchings #define ESE_DZ_MAC_CLASS_UCAST 0 208e17705c4SEdward Cree #define ESF_DD_RX_EV_SOFT1_LBN 32 209e17705c4SEdward Cree #define ESF_DD_RX_EV_SOFT1_WIDTH 3 210e17705c4SEdward Cree #define ESF_EZ_RX_EV_SOFT1_LBN 34 211e17705c4SEdward Cree #define ESF_EZ_RX_EV_SOFT1_WIDTH 1 212e17705c4SEdward Cree #define ESF_EZ_RX_ENCAP_HDR_LBN 32 213e17705c4SEdward Cree #define ESF_EZ_RX_ENCAP_HDR_WIDTH 2 214e17705c4SEdward Cree #define ESE_EZ_ENCAP_HDR_GRE 2 215e17705c4SEdward Cree #define ESE_EZ_ENCAP_HDR_VXLAN 1 216e17705c4SEdward Cree #define ESE_EZ_ENCAP_HDR_NONE 0 217e17705c4SEdward Cree #define ESF_DD_RX_EV_RSVD1_LBN 30 218e17705c4SEdward Cree #define ESF_DD_RX_EV_RSVD1_WIDTH 2 219e17705c4SEdward Cree #define ESF_EZ_RX_EV_RSVD1_LBN 31 220e17705c4SEdward Cree #define ESF_EZ_RX_EV_RSVD1_WIDTH 1 221e17705c4SEdward Cree #define ESF_EZ_RX_ABORT_LBN 30 222e17705c4SEdward Cree #define ESF_EZ_RX_ABORT_WIDTH 1 2239c517165SBen Hutchings #define ESF_DZ_RX_ECC_ERR_LBN 29 2249c517165SBen Hutchings #define ESF_DZ_RX_ECC_ERR_WIDTH 1 225d8d8ccf2SBert Kenward #define ESF_DZ_RX_TRUNC_ERR_LBN 29 226d8d8ccf2SBert Kenward #define ESF_DZ_RX_TRUNC_ERR_WIDTH 1 2279c517165SBen Hutchings #define ESF_DZ_RX_CRC1_ERR_LBN 28 2289c517165SBen Hutchings #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 2299c517165SBen Hutchings #define ESF_DZ_RX_CRC0_ERR_LBN 27 2309c517165SBen Hutchings #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 2319c517165SBen Hutchings #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 2329c517165SBen Hutchings #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 2339c517165SBen Hutchings #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 2349c517165SBen Hutchings #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 2359c517165SBen Hutchings #define ESF_DZ_RX_ECRC_ERR_LBN 24 2369c517165SBen Hutchings #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 2379c517165SBen Hutchings #define ESF_DZ_RX_QLABEL_LBN 16 2389c517165SBen Hutchings #define ESF_DZ_RX_QLABEL_WIDTH 5 2399c517165SBen Hutchings #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 2409c517165SBen Hutchings #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 2419c517165SBen Hutchings #define ESF_DZ_RX_CONT_LBN 14 2429c517165SBen Hutchings #define ESF_DZ_RX_CONT_WIDTH 1 2439c517165SBen Hutchings #define ESF_DZ_RX_BYTES_LBN 0 2449c517165SBen Hutchings #define ESF_DZ_RX_BYTES_WIDTH 14 2459c517165SBen Hutchings 2469c517165SBen Hutchings /* RX_KER_DESC */ 2479c517165SBen Hutchings #define ESF_DZ_RX_KER_RESERVED_LBN 62 2489c517165SBen Hutchings #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 2499c517165SBen Hutchings #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 2509c517165SBen Hutchings #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 2519c517165SBen Hutchings #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 2529c517165SBen Hutchings #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 2539c517165SBen Hutchings 2549c517165SBen Hutchings /* TX_CSUM_TSTAMP_DESC */ 2559c517165SBen Hutchings #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 2569c517165SBen Hutchings #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 2579c517165SBen Hutchings #define ESF_DZ_TX_OPTION_TYPE_LBN 60 2589c517165SBen Hutchings #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 2599c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_TSO 7 2609c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_VLAN 6 2619c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 262e17705c4SEdward Cree #define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8 263e17705c4SEdward Cree #define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1 264e17705c4SEdward Cree #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7 265e17705c4SEdward Cree #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1 266e17705c4SEdward Cree #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6 267e17705c4SEdward Cree #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1 2689c517165SBen Hutchings #define ESF_DZ_TX_TIMESTAMP_LBN 5 2699c517165SBen Hutchings #define ESF_DZ_TX_TIMESTAMP_WIDTH 1 2709c517165SBen Hutchings #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 2719c517165SBen Hutchings #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 2729c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 2739c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 2749c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 2759c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 2769c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_FCOE 1 2779c517165SBen Hutchings #define ESE_DZ_TX_OPTION_CRC_OFF 0 2789c517165SBen Hutchings #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 2799c517165SBen Hutchings #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 2809c517165SBen Hutchings #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 2819c517165SBen Hutchings #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 2829c517165SBen Hutchings 2839c517165SBen Hutchings /* TX_EVENT */ 2849c517165SBen Hutchings #define ESF_DZ_TX_CODE_LBN 60 2859c517165SBen Hutchings #define ESF_DZ_TX_CODE_WIDTH 4 2869c517165SBen Hutchings #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 2879c517165SBen Hutchings #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 2889c517165SBen Hutchings #define ESF_DZ_TX_DROP_EVENT_LBN 58 2899c517165SBen Hutchings #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 290e17705c4SEdward Cree #define ESF_DD_TX_EV_RSVD_LBN 48 291e17705c4SEdward Cree #define ESF_DD_TX_EV_RSVD_WIDTH 10 292e17705c4SEdward Cree #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 293e17705c4SEdward Cree #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 294e17705c4SEdward Cree #define ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56 295e17705c4SEdward Cree #define ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1 296e17705c4SEdward Cree #define ESF_EZ_TX_EV_RSVD_LBN 48 297e17705c4SEdward Cree #define ESF_EZ_TX_EV_RSVD_WIDTH 8 2989c517165SBen Hutchings #define ESF_DZ_TX_SOFT2_LBN 32 2999c517165SBen Hutchings #define ESF_DZ_TX_SOFT2_WIDTH 16 300e17705c4SEdward Cree #define ESF_DD_TX_SOFT1_LBN 24 301e17705c4SEdward Cree #define ESF_DD_TX_SOFT1_WIDTH 8 302e17705c4SEdward Cree #define ESF_EZ_TX_CAN_MERGE_LBN 31 303e17705c4SEdward Cree #define ESF_EZ_TX_CAN_MERGE_WIDTH 1 304e17705c4SEdward Cree #define ESF_EZ_TX_SOFT1_LBN 24 305e17705c4SEdward Cree #define ESF_EZ_TX_SOFT1_WIDTH 7 3069c517165SBen Hutchings #define ESF_DZ_TX_QLABEL_LBN 16 3079c517165SBen Hutchings #define ESF_DZ_TX_QLABEL_WIDTH 5 3089c517165SBen Hutchings #define ESF_DZ_TX_DESCR_INDX_LBN 0 3099c517165SBen Hutchings #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 3109c517165SBen Hutchings 3119c517165SBen Hutchings /* TX_KER_DESC */ 3129c517165SBen Hutchings #define ESF_DZ_TX_KER_TYPE_LBN 63 3139c517165SBen Hutchings #define ESF_DZ_TX_KER_TYPE_WIDTH 1 3149c517165SBen Hutchings #define ESF_DZ_TX_KER_CONT_LBN 62 3159c517165SBen Hutchings #define ESF_DZ_TX_KER_CONT_WIDTH 1 3169c517165SBen Hutchings #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 3179c517165SBen Hutchings #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 3189c517165SBen Hutchings #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 3199c517165SBen Hutchings #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 3209c517165SBen Hutchings 3219c517165SBen Hutchings /* TX_PIO_DESC */ 3229c517165SBen Hutchings #define ESF_DZ_TX_PIO_TYPE_LBN 63 3239c517165SBen Hutchings #define ESF_DZ_TX_PIO_TYPE_WIDTH 1 3249c517165SBen Hutchings #define ESF_DZ_TX_PIO_OPT_LBN 60 3259c517165SBen Hutchings #define ESF_DZ_TX_PIO_OPT_WIDTH 3 326ee45fd92SJon Cooper #define ESE_DZ_TX_OPTION_DESC_PIO 1 3279c517165SBen Hutchings #define ESF_DZ_TX_PIO_CONT_LBN 59 3289c517165SBen Hutchings #define ESF_DZ_TX_PIO_CONT_WIDTH 1 3299c517165SBen Hutchings #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 3309c517165SBen Hutchings #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 3319c517165SBen Hutchings #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 3329c517165SBen Hutchings #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 3339c517165SBen Hutchings 3349c517165SBen Hutchings /* TX_TSO_DESC */ 3359c517165SBen Hutchings #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 3369c517165SBen Hutchings #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 3379c517165SBen Hutchings #define ESF_DZ_TX_OPTION_TYPE_LBN 60 3389c517165SBen Hutchings #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 3399c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_TSO 7 3409c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_VLAN 6 3419c517165SBen Hutchings #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 342e17705c4SEdward Cree #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 343e17705c4SEdward Cree #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 344d8d8ccf2SBert Kenward #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 345d8d8ccf2SBert Kenward #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 346e17705c4SEdward Cree #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 347e17705c4SEdward Cree #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 3489c517165SBen Hutchings #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 3499c517165SBen Hutchings #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 3509c517165SBen Hutchings #define ESF_DZ_TX_TSO_IP_ID_LBN 32 3519c517165SBen Hutchings #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 3529c517165SBen Hutchings #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 3539c517165SBen Hutchings #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 3549c517165SBen Hutchings 355d8d8ccf2SBert Kenward /* TX_TSO_V2_DESC_A */ 356e17705c4SEdward Cree #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 357e17705c4SEdward Cree #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 358e17705c4SEdward Cree #define ESF_DZ_TX_OPTION_TYPE_LBN 60 359e17705c4SEdward Cree #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 360e17705c4SEdward Cree #define ESE_DZ_TX_OPTION_DESC_TSO 7 361e17705c4SEdward Cree #define ESE_DZ_TX_OPTION_DESC_VLAN 6 362e17705c4SEdward Cree #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 363e17705c4SEdward Cree #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 364e17705c4SEdward Cree #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 365e17705c4SEdward Cree #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 366e17705c4SEdward Cree #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 367e17705c4SEdward Cree #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 368e17705c4SEdward Cree #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 369e17705c4SEdward Cree #define ESF_DZ_TX_TSO_IP_ID_LBN 32 370e17705c4SEdward Cree #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 371e17705c4SEdward Cree #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 372e17705c4SEdward Cree #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 373e17705c4SEdward Cree 374d8d8ccf2SBert Kenward /* TX_TSO_V2_DESC_B */ 375e17705c4SEdward Cree #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 376e17705c4SEdward Cree #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 377e17705c4SEdward Cree #define ESF_DZ_TX_OPTION_TYPE_LBN 60 378e17705c4SEdward Cree #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 379e17705c4SEdward Cree #define ESE_DZ_TX_OPTION_DESC_TSO 7 380e17705c4SEdward Cree #define ESE_DZ_TX_OPTION_DESC_VLAN 6 381e17705c4SEdward Cree #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 382e17705c4SEdward Cree #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 383e17705c4SEdward Cree #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 384e17705c4SEdward Cree #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 385e17705c4SEdward Cree #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 386e17705c4SEdward Cree #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 387e17705c4SEdward Cree #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 388e17705c4SEdward Cree #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 389e17705c4SEdward Cree #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 390d8d8ccf2SBert Kenward #define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0 391d8d8ccf2SBert Kenward #define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16 392e17705c4SEdward Cree 3939c517165SBen Hutchings /*************************************************************************/ 3949c517165SBen Hutchings 3959c517165SBen Hutchings /* TX_DESC_UPD_REG: Transmit descriptor update register. 3969c517165SBen Hutchings * We may write just one dword of these registers. 3979c517165SBen Hutchings */ 3989c517165SBen Hutchings #define ER_DZ_TX_DESC_UPD_DWORD (ER_DZ_TX_DESC_UPD + 2 * 4) 3999c517165SBen Hutchings #define ERF_DZ_TX_DESC_WPTR_DWORD_LBN (ERF_DZ_TX_DESC_WPTR_LBN - 2 * 32) 4009c517165SBen Hutchings #define ERF_DZ_TX_DESC_WPTR_DWORD_WIDTH ERF_DZ_TX_DESC_WPTR_WIDTH 4019c517165SBen Hutchings 4029c517165SBen Hutchings /* The workaround for bug 35388 requires multiplexing writes through 4039c517165SBen Hutchings * the TX_DESC_UPD_DWORD address. 4049c517165SBen Hutchings * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) 4059c517165SBen Hutchings * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) 4069c517165SBen Hutchings * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) 4079c517165SBen Hutchings */ 4089c517165SBen Hutchings #define ER_DD_EVQ_INDIRECT ER_DZ_TX_DESC_UPD_DWORD 4099c517165SBen Hutchings #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 4109c517165SBen Hutchings #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 4119c517165SBen Hutchings #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 4129c517165SBen Hutchings #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 4139c517165SBen Hutchings #define ERF_DD_EVQ_IND_RPTR_LBN 0 4149c517165SBen Hutchings #define ERF_DD_EVQ_IND_RPTR_WIDTH 8 4159c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 4169c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 4179c517165SBen Hutchings #define EFE_DD_EVQ_IND_TIMER_FLAGS 3 4189c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 4199c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 4209c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 4219c517165SBen Hutchings #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 4229c517165SBen Hutchings 4239c517165SBen Hutchings /* TX_PIOBUF 4249c517165SBen Hutchings * PIO buffer aperture (paged) 4259c517165SBen Hutchings */ 4269c517165SBen Hutchings #define ER_DZ_TX_PIOBUF 4096 4279c517165SBen Hutchings #define ER_DZ_TX_PIOBUF_SIZE 2048 4289c517165SBen Hutchings 4299c517165SBen Hutchings /* RX packet prefix */ 4309c517165SBen Hutchings #define ES_DZ_RX_PREFIX_HASH_OFST 0 4319c517165SBen Hutchings #define ES_DZ_RX_PREFIX_VLAN1_OFST 4 4329c517165SBen Hutchings #define ES_DZ_RX_PREFIX_VLAN2_OFST 6 4339c517165SBen Hutchings #define ES_DZ_RX_PREFIX_PKTLEN_OFST 8 4349c517165SBen Hutchings #define ES_DZ_RX_PREFIX_TSTAMP_OFST 10 4359c517165SBen Hutchings #define ES_DZ_RX_PREFIX_SIZE 14 4369c517165SBen Hutchings 4379c517165SBen Hutchings #endif /* EFX_EF10_REGS_H */ 438