xref: /openbmc/linux/drivers/net/ethernet/sfc/ef100_tx.c (revision 0760aad038b5a032c31ea124feed63d88627d2f1)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3  * Driver for Solarflare network controllers and boards
4  * Copyright 2018 Solarflare Communications Inc.
5  * Copyright 2019-2020 Xilinx Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published
9  * by the Free Software Foundation, incorporated herein by reference.
10  */
11 
12 #include <net/ip6_checksum.h>
13 
14 #include "net_driver.h"
15 #include "tx_common.h"
16 #include "nic_common.h"
17 #include "mcdi_functions.h"
18 #include "ef100_regs.h"
19 #include "io.h"
20 #include "ef100_tx.h"
21 #include "ef100_nic.h"
22 
23 int ef100_tx_probe(struct efx_tx_queue *tx_queue)
24 {
25 	/* Allocate an extra descriptor for the QMDA status completion entry */
26 	return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
27 				    (tx_queue->ptr_mask + 2) *
28 				    sizeof(efx_oword_t),
29 				    GFP_KERNEL);
30 	return 0;
31 }
32 
33 void ef100_tx_init(struct efx_tx_queue *tx_queue)
34 {
35 	/* must be the inverse of lookup in efx_get_tx_channel */
36 	tx_queue->core_txq =
37 		netdev_get_tx_queue(tx_queue->efx->net_dev,
38 				    tx_queue->channel->channel -
39 				    tx_queue->efx->tx_channel_offset);
40 
41 	if (efx_mcdi_tx_init(tx_queue, false))
42 		netdev_WARN(tx_queue->efx->net_dev,
43 			    "failed to initialise TXQ %d\n", tx_queue->queue);
44 }
45 
46 static bool ef100_tx_can_tso(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
47 {
48 	struct efx_nic *efx = tx_queue->efx;
49 	struct ef100_nic_data *nic_data;
50 	struct efx_tx_buffer *buffer;
51 	struct tcphdr *tcphdr;
52 	struct iphdr *iphdr;
53 	size_t header_len;
54 	u32 mss;
55 
56 	nic_data = efx->nic_data;
57 
58 	if (!skb_is_gso_tcp(skb))
59 		return false;
60 	if (!(efx->net_dev->features & NETIF_F_TSO))
61 		return false;
62 
63 	mss = skb_shinfo(skb)->gso_size;
64 	if (unlikely(mss < 4)) {
65 		WARN_ONCE(1, "MSS of %u is too small for TSO\n", mss);
66 		return false;
67 	}
68 
69 	header_len = efx_tx_tso_header_length(skb);
70 	if (header_len > nic_data->tso_max_hdr_len)
71 		return false;
72 
73 	if (skb_shinfo(skb)->gso_segs > nic_data->tso_max_payload_num_segs) {
74 		/* net_dev->gso_max_segs should've caught this */
75 		WARN_ON_ONCE(1);
76 		return false;
77 	}
78 
79 	if (skb->data_len / mss > nic_data->tso_max_frames)
80 		return false;
81 
82 	/* net_dev->gso_max_size should've caught this */
83 	if (WARN_ON_ONCE(skb->data_len > nic_data->tso_max_payload_len))
84 		return false;
85 
86 	/* Reserve an empty buffer for the TSO V3 descriptor.
87 	 * Convey the length of the header since we already know it.
88 	 */
89 	buffer = efx_tx_queue_get_insert_buffer(tx_queue);
90 	buffer->flags = EFX_TX_BUF_TSO_V3 | EFX_TX_BUF_CONT;
91 	buffer->len = header_len;
92 	buffer->unmap_len = 0;
93 	buffer->skb = skb;
94 	++tx_queue->insert_count;
95 
96 	/* Adjust the TCP checksum to exclude the total length, since we set
97 	 * ED_INNER_IP_LEN in the descriptor.
98 	 */
99 	tcphdr = tcp_hdr(skb);
100 	if (skb_is_gso_v6(skb)) {
101 		tcphdr->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
102 						 &ipv6_hdr(skb)->daddr,
103 						 0, IPPROTO_TCP, 0);
104 	} else {
105 		iphdr = ip_hdr(skb);
106 		tcphdr->check = ~csum_tcpudp_magic(iphdr->saddr, iphdr->daddr,
107 						   0, IPPROTO_TCP, 0);
108 	}
109 	return true;
110 }
111 
112 static efx_oword_t *ef100_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
113 {
114 	if (likely(tx_queue->txd.buf.addr))
115 		return ((efx_oword_t *)tx_queue->txd.buf.addr) + index;
116 	else
117 		return NULL;
118 }
119 
120 static void ef100_notify_tx_desc(struct efx_tx_queue *tx_queue)
121 {
122 	unsigned int write_ptr;
123 	efx_dword_t reg;
124 
125 	tx_queue->xmit_pending = false;
126 
127 	if (unlikely(tx_queue->notify_count == tx_queue->write_count))
128 		return;
129 
130 	write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
131 	/* The write pointer goes into the high word */
132 	EFX_POPULATE_DWORD_1(reg, ERF_GZ_TX_RING_PIDX, write_ptr);
133 	efx_writed_page(tx_queue->efx, &reg,
134 			ER_GZ_TX_RING_DOORBELL, tx_queue->queue);
135 	tx_queue->notify_count = tx_queue->write_count;
136 }
137 
138 static void ef100_tx_push_buffers(struct efx_tx_queue *tx_queue)
139 {
140 	ef100_notify_tx_desc(tx_queue);
141 	++tx_queue->pushes;
142 }
143 
144 static void ef100_set_tx_csum_partial(const struct sk_buff *skb,
145 				      struct efx_tx_buffer *buffer, efx_oword_t *txd)
146 {
147 	efx_oword_t csum;
148 	int csum_start;
149 
150 	if (!skb || skb->ip_summed != CHECKSUM_PARTIAL)
151 		return;
152 
153 	/* skb->csum_start has the offset from head, but we need the offset
154 	 * from data.
155 	 */
156 	csum_start = skb_checksum_start_offset(skb);
157 	EFX_POPULATE_OWORD_3(csum,
158 			     ESF_GZ_TX_SEND_CSO_PARTIAL_EN, 1,
159 			     ESF_GZ_TX_SEND_CSO_PARTIAL_START_W,
160 			     csum_start >> 1,
161 			     ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W,
162 			     skb->csum_offset >> 1);
163 	EFX_OR_OWORD(*txd, *txd, csum);
164 }
165 
166 static void ef100_set_tx_hw_vlan(const struct sk_buff *skb, efx_oword_t *txd)
167 {
168 	u16 vlan_tci = skb_vlan_tag_get(skb);
169 	efx_oword_t vlan;
170 
171 	EFX_POPULATE_OWORD_2(vlan,
172 			     ESF_GZ_TX_SEND_VLAN_INSERT_EN, 1,
173 			     ESF_GZ_TX_SEND_VLAN_INSERT_TCI, vlan_tci);
174 	EFX_OR_OWORD(*txd, *txd, vlan);
175 }
176 
177 static void ef100_make_send_desc(struct efx_nic *efx,
178 				 const struct sk_buff *skb,
179 				 struct efx_tx_buffer *buffer, efx_oword_t *txd,
180 				 unsigned int segment_count)
181 {
182 	/* TX send descriptor */
183 	EFX_POPULATE_OWORD_3(*txd,
184 			     ESF_GZ_TX_SEND_NUM_SEGS, segment_count,
185 			     ESF_GZ_TX_SEND_LEN, buffer->len,
186 			     ESF_GZ_TX_SEND_ADDR, buffer->dma_addr);
187 
188 	if (likely(efx->net_dev->features & NETIF_F_HW_CSUM))
189 		ef100_set_tx_csum_partial(skb, buffer, txd);
190 	if (efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_TX &&
191 	    skb && skb_vlan_tag_present(skb))
192 		ef100_set_tx_hw_vlan(skb, txd);
193 }
194 
195 static void ef100_make_tso_desc(struct efx_nic *efx,
196 				const struct sk_buff *skb,
197 				struct efx_tx_buffer *buffer, efx_oword_t *txd,
198 				unsigned int segment_count)
199 {
200 	u32 mangleid = (efx->net_dev->features & NETIF_F_TSO_MANGLEID) ||
201 		skb_shinfo(skb)->gso_type & SKB_GSO_TCP_FIXEDID ?
202 		ESE_GZ_TX_DESC_IP4_ID_NO_OP :
203 		ESE_GZ_TX_DESC_IP4_ID_INC_MOD16;
204 	u16 vlan_enable =  efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_TX ?
205 		skb_vlan_tag_present(skb) : 0;
206 	unsigned int len, ip_offset, tcp_offset, payload_segs;
207 	u16 vlan_tci = skb_vlan_tag_get(skb);
208 	u32 mss = skb_shinfo(skb)->gso_size;
209 
210 	len = skb->len - buffer->len;
211 	/* We use 1 for the TSO descriptor and 1 for the header */
212 	payload_segs = segment_count - 2;
213 	ip_offset =  skb_network_offset(skb);
214 	tcp_offset = skb_transport_offset(skb);
215 
216 	EFX_POPULATE_OWORD_13(*txd,
217 			      ESF_GZ_TX_DESC_TYPE, ESE_GZ_TX_DESC_TYPE_TSO,
218 			      ESF_GZ_TX_TSO_MSS, mss,
219 			      ESF_GZ_TX_TSO_HDR_NUM_SEGS, 1,
220 			      ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS, payload_segs,
221 			      ESF_GZ_TX_TSO_HDR_LEN_W, buffer->len >> 1,
222 			      ESF_GZ_TX_TSO_PAYLOAD_LEN, len,
223 			      ESF_GZ_TX_TSO_CSO_INNER_L4, 1,
224 			      ESF_GZ_TX_TSO_INNER_L3_OFF_W, ip_offset >> 1,
225 			      ESF_GZ_TX_TSO_INNER_L4_OFF_W, tcp_offset >> 1,
226 			      ESF_GZ_TX_TSO_ED_INNER_IP4_ID, mangleid,
227 			      ESF_GZ_TX_TSO_ED_INNER_IP_LEN, 1,
228 			      ESF_GZ_TX_TSO_VLAN_INSERT_EN, vlan_enable,
229 			      ESF_GZ_TX_TSO_VLAN_INSERT_TCI, vlan_tci
230 		);
231 }
232 
233 static void ef100_tx_make_descriptors(struct efx_tx_queue *tx_queue,
234 				      const struct sk_buff *skb,
235 				      unsigned int segment_count)
236 {
237 	unsigned int old_write_count = tx_queue->write_count;
238 	unsigned int new_write_count = old_write_count;
239 	struct efx_tx_buffer *buffer;
240 	unsigned int next_desc_type;
241 	unsigned int write_ptr;
242 	efx_oword_t *txd;
243 	unsigned int nr_descs = tx_queue->insert_count - old_write_count;
244 
245 	if (unlikely(nr_descs == 0))
246 		return;
247 
248 	if (segment_count)
249 		next_desc_type = ESE_GZ_TX_DESC_TYPE_TSO;
250 	else
251 		next_desc_type = ESE_GZ_TX_DESC_TYPE_SEND;
252 
253 	/* if it's a raw write (such as XDP) then always SEND single frames */
254 	if (!skb)
255 		nr_descs = 1;
256 
257 	do {
258 		write_ptr = new_write_count & tx_queue->ptr_mask;
259 		buffer = &tx_queue->buffer[write_ptr];
260 		txd = ef100_tx_desc(tx_queue, write_ptr);
261 		++new_write_count;
262 
263 		/* Create TX descriptor ring entry */
264 		tx_queue->packet_write_count = new_write_count;
265 
266 		switch (next_desc_type) {
267 		case ESE_GZ_TX_DESC_TYPE_SEND:
268 			ef100_make_send_desc(tx_queue->efx, skb,
269 					     buffer, txd, nr_descs);
270 			break;
271 		case ESE_GZ_TX_DESC_TYPE_TSO:
272 			/* TX TSO descriptor */
273 			WARN_ON_ONCE(!(buffer->flags & EFX_TX_BUF_TSO_V3));
274 			ef100_make_tso_desc(tx_queue->efx, skb,
275 					    buffer, txd, nr_descs);
276 			break;
277 		default:
278 			/* TX segment descriptor */
279 			EFX_POPULATE_OWORD_3(*txd,
280 					     ESF_GZ_TX_DESC_TYPE, ESE_GZ_TX_DESC_TYPE_SEG,
281 					     ESF_GZ_TX_SEG_LEN, buffer->len,
282 					     ESF_GZ_TX_SEG_ADDR, buffer->dma_addr);
283 		}
284 		/* if it's a raw write (such as XDP) then always SEND */
285 		next_desc_type = skb ? ESE_GZ_TX_DESC_TYPE_SEG :
286 				       ESE_GZ_TX_DESC_TYPE_SEND;
287 
288 	} while (new_write_count != tx_queue->insert_count);
289 
290 	wmb(); /* Ensure descriptors are written before they are fetched */
291 
292 	tx_queue->write_count = new_write_count;
293 
294 	/* The write_count above must be updated before reading
295 	 * channel->holdoff_doorbell to avoid a race with the
296 	 * completion path, so ensure these operations are not
297 	 * re-ordered.  This also flushes the update of write_count
298 	 * back into the cache.
299 	 */
300 	smp_mb();
301 }
302 
303 void ef100_tx_write(struct efx_tx_queue *tx_queue)
304 {
305 	ef100_tx_make_descriptors(tx_queue, NULL, 0);
306 	ef100_tx_push_buffers(tx_queue);
307 }
308 
309 void ef100_ev_tx(struct efx_channel *channel, const efx_qword_t *p_event)
310 {
311 	unsigned int tx_done =
312 		EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_TXCMPL_NUM_DESC);
313 	unsigned int qlabel =
314 		EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_TXCMPL_Q_LABEL);
315 	struct efx_tx_queue *tx_queue =
316 		efx_channel_get_tx_queue(channel, qlabel);
317 	unsigned int tx_index = (tx_queue->read_count + tx_done - 1) &
318 				tx_queue->ptr_mask;
319 
320 	efx_xmit_done(tx_queue, tx_index);
321 }
322 
323 /* Add a socket buffer to a TX queue
324  *
325  * You must hold netif_tx_lock() to call this function.
326  *
327  * Returns 0 on success, error code otherwise. In case of an error this
328  * function will free the SKB.
329  */
330 int ef100_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
331 {
332 	unsigned int old_insert_count = tx_queue->insert_count;
333 	struct efx_nic *efx = tx_queue->efx;
334 	bool xmit_more = netdev_xmit_more();
335 	unsigned int fill_level;
336 	unsigned int segments;
337 	int rc;
338 
339 	if (!tx_queue->buffer || !tx_queue->ptr_mask) {
340 		netif_stop_queue(efx->net_dev);
341 		dev_kfree_skb_any(skb);
342 		return -ENODEV;
343 	}
344 
345 	segments = skb_is_gso(skb) ? skb_shinfo(skb)->gso_segs : 0;
346 	if (segments == 1)
347 		segments = 0;	/* Don't use TSO/GSO for a single segment. */
348 	if (segments && !ef100_tx_can_tso(tx_queue, skb)) {
349 		rc = efx_tx_tso_fallback(tx_queue, skb);
350 		tx_queue->tso_fallbacks++;
351 		if (rc)
352 			goto err;
353 		else
354 			return 0;
355 	}
356 
357 	/* Map for DMA and create descriptors */
358 	rc = efx_tx_map_data(tx_queue, skb, segments);
359 	if (rc)
360 		goto err;
361 	ef100_tx_make_descriptors(tx_queue, skb, segments);
362 
363 	fill_level = efx_channel_tx_old_fill_level(tx_queue->channel);
364 	if (fill_level > efx->txq_stop_thresh) {
365 		struct efx_tx_queue *txq2;
366 
367 		netif_tx_stop_queue(tx_queue->core_txq);
368 		/* Re-read after a memory barrier in case we've raced with
369 		 * the completion path. Otherwise there's a danger we'll never
370 		 * restart the queue if all completions have just happened.
371 		 */
372 		smp_mb();
373 		efx_for_each_channel_tx_queue(txq2, tx_queue->channel)
374 			txq2->old_read_count = READ_ONCE(txq2->read_count);
375 		fill_level = efx_channel_tx_old_fill_level(tx_queue->channel);
376 		if (fill_level < efx->txq_stop_thresh)
377 			netif_tx_start_queue(tx_queue->core_txq);
378 	}
379 
380 	tx_queue->xmit_pending = true;
381 
382 	/* If xmit_more then we don't need to push the doorbell, unless there
383 	 * are 256 descriptors already queued in which case we have to push to
384 	 * ensure we never push more than 256 at once.
385 	 */
386 	if (__netdev_tx_sent_queue(tx_queue->core_txq, skb->len, xmit_more) ||
387 	    tx_queue->write_count - tx_queue->notify_count > 255)
388 		ef100_tx_push_buffers(tx_queue);
389 
390 	if (segments) {
391 		tx_queue->tso_bursts++;
392 		tx_queue->tso_packets += segments;
393 		tx_queue->tx_packets  += segments;
394 	} else {
395 		tx_queue->tx_packets++;
396 	}
397 	return 0;
398 
399 err:
400 	efx_enqueue_unwind(tx_queue, old_insert_count);
401 	if (!IS_ERR_OR_NULL(skb))
402 		dev_kfree_skb_any(skb);
403 
404 	/* If we're not expecting another transmit and we had something to push
405 	 * on this queue then we need to push here to get the previous packets
406 	 * out.  We only enter this branch from before the xmit_more handling
407 	 * above, so xmit_pending still refers to the old state.
408 	 */
409 	if (tx_queue->xmit_pending && !xmit_more)
410 		ef100_tx_push_buffers(tx_queue);
411 	return rc;
412 }
413