1adf72ee3SEdward Cree /* SPDX-License-Identifier: GPL-2.0-only */ 2adf72ee3SEdward Cree /**************************************************************************** 3adf72ee3SEdward Cree * Driver for Solarflare network controllers and boards 4adf72ee3SEdward Cree * Copyright 2018 Solarflare Communications Inc. 5*8ca353daSEdward Cree * Copyright 2019-2022 Xilinx Inc. 6adf72ee3SEdward Cree * 7adf72ee3SEdward Cree * This program is free software; you can redistribute it and/or modify it 8adf72ee3SEdward Cree * under the terms of the GNU General Public License version 2 as published 9adf72ee3SEdward Cree * by the Free Software Foundation, incorporated herein by reference. 10adf72ee3SEdward Cree */ 11adf72ee3SEdward Cree 12adf72ee3SEdward Cree #ifndef EFX_EF100_REGS_H 13adf72ee3SEdward Cree #define EFX_EF100_REGS_H 14adf72ee3SEdward Cree 15adf72ee3SEdward Cree /* EF100 hardware architecture definitions have a name prefix following 16adf72ee3SEdward Cree * the format: 17adf72ee3SEdward Cree * 18adf72ee3SEdward Cree * E<type>_<min-rev><max-rev>_ 19adf72ee3SEdward Cree * 20adf72ee3SEdward Cree * The following <type> strings are used: 21adf72ee3SEdward Cree * 22adf72ee3SEdward Cree * MMIO register Host memory structure 23adf72ee3SEdward Cree * ------------------------------------------------------------- 24adf72ee3SEdward Cree * Address R 25adf72ee3SEdward Cree * Bitfield RF SF 26adf72ee3SEdward Cree * Enumerator FE SE 27adf72ee3SEdward Cree * 28adf72ee3SEdward Cree * <min-rev> is the first revision to which the definition applies: 29adf72ee3SEdward Cree * 30adf72ee3SEdward Cree * G: Riverhead 31adf72ee3SEdward Cree * 32adf72ee3SEdward Cree * If the definition has been changed or removed in later revisions 33adf72ee3SEdward Cree * then <max-rev> is the last revision to which the definition applies; 34adf72ee3SEdward Cree * otherwise it is "Z". 35adf72ee3SEdward Cree */ 36adf72ee3SEdward Cree 37adf72ee3SEdward Cree /************************************************************************** 38adf72ee3SEdward Cree * 39adf72ee3SEdward Cree * EF100 registers and descriptors 40adf72ee3SEdward Cree * 41adf72ee3SEdward Cree ************************************************************************** 42adf72ee3SEdward Cree */ 43adf72ee3SEdward Cree 44adf72ee3SEdward Cree /* HW_REV_ID_REG: Hardware revision info register */ 45adf72ee3SEdward Cree #define ER_GZ_HW_REV_ID 0x00000000 46adf72ee3SEdward Cree 47adf72ee3SEdward Cree /* NIC_REV_ID: SoftNIC revision info register */ 48adf72ee3SEdward Cree #define ER_GZ_NIC_REV_ID 0x00000004 49adf72ee3SEdward Cree 50adf72ee3SEdward Cree /* NIC_MAGIC: Signature register that should contain a well-known value */ 51adf72ee3SEdward Cree #define ER_GZ_NIC_MAGIC 0x00000008 52adf72ee3SEdward Cree #define ERF_GZ_NIC_MAGIC_LBN 0 53adf72ee3SEdward Cree #define ERF_GZ_NIC_MAGIC_WIDTH 32 54adf72ee3SEdward Cree #define EFE_GZ_NIC_MAGIC_EXPECTED 0xEF100FCB 55adf72ee3SEdward Cree 56adf72ee3SEdward Cree /* MC_SFT_STATUS: MC soft status */ 57adf72ee3SEdward Cree #define ER_GZ_MC_SFT_STATUS 0x00000010 58adf72ee3SEdward Cree #define ER_GZ_MC_SFT_STATUS_STEP 4 59adf72ee3SEdward Cree #define ER_GZ_MC_SFT_STATUS_ROWS 2 60adf72ee3SEdward Cree 61adf72ee3SEdward Cree /* MC_DB_LWRD_REG: MC doorbell register, low word */ 62adf72ee3SEdward Cree #define ER_GZ_MC_DB_LWRD 0x00000020 63adf72ee3SEdward Cree 64adf72ee3SEdward Cree /* MC_DB_HWRD_REG: MC doorbell register, high word */ 65adf72ee3SEdward Cree #define ER_GZ_MC_DB_HWRD 0x00000024 66adf72ee3SEdward Cree 67adf72ee3SEdward Cree /* EVQ_INT_PRIME: Prime EVQ */ 68adf72ee3SEdward Cree #define ER_GZ_EVQ_INT_PRIME 0x00000040 69adf72ee3SEdward Cree #define ERF_GZ_IDX_LBN 16 70adf72ee3SEdward Cree #define ERF_GZ_IDX_WIDTH 16 71adf72ee3SEdward Cree #define ERF_GZ_EVQ_ID_LBN 0 72adf72ee3SEdward Cree #define ERF_GZ_EVQ_ID_WIDTH 16 73adf72ee3SEdward Cree 74adf72ee3SEdward Cree /* INT_AGG_RING_PRIME: Prime interrupt aggregation ring. */ 75adf72ee3SEdward Cree #define ER_GZ_INT_AGG_RING_PRIME 0x00000048 76adf72ee3SEdward Cree /* defined as ERF_GZ_IDX_LBN 16; access=WO reset=0x0 */ 77adf72ee3SEdward Cree /* defined as ERF_GZ_IDX_WIDTH 16 */ 78adf72ee3SEdward Cree #define ERF_GZ_RING_ID_LBN 0 79adf72ee3SEdward Cree #define ERF_GZ_RING_ID_WIDTH 16 80adf72ee3SEdward Cree 81adf72ee3SEdward Cree /* EVQ_TMR: EVQ timer control */ 82adf72ee3SEdward Cree #define ER_GZ_EVQ_TMR 0x00000104 83adf72ee3SEdward Cree #define ER_GZ_EVQ_TMR_STEP 65536 84adf72ee3SEdward Cree #define ER_GZ_EVQ_TMR_ROWS 1024 85adf72ee3SEdward Cree 86adf72ee3SEdward Cree /* EVQ_UNSOL_CREDIT_GRANT_SEQ: Grant credits for unsolicited events. */ 87adf72ee3SEdward Cree #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ 0x00000108 88adf72ee3SEdward Cree #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_STEP 65536 89adf72ee3SEdward Cree #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_ROWS 1024 90adf72ee3SEdward Cree 91adf72ee3SEdward Cree /* EVQ_DESC_CREDIT_GRANT_SEQ: Grant credits for descriptor proxy events. */ 92adf72ee3SEdward Cree #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ 0x00000110 93adf72ee3SEdward Cree #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_STEP 65536 94adf72ee3SEdward Cree #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_ROWS 1024 95adf72ee3SEdward Cree 96adf72ee3SEdward Cree /* RX_RING_DOORBELL: Ring Rx doorbell. */ 97adf72ee3SEdward Cree #define ER_GZ_RX_RING_DOORBELL 0x00000180 98adf72ee3SEdward Cree #define ER_GZ_RX_RING_DOORBELL_STEP 65536 99adf72ee3SEdward Cree #define ER_GZ_RX_RING_DOORBELL_ROWS 1024 100adf72ee3SEdward Cree #define ERF_GZ_RX_RING_PIDX_LBN 16 101adf72ee3SEdward Cree #define ERF_GZ_RX_RING_PIDX_WIDTH 16 102adf72ee3SEdward Cree 103adf72ee3SEdward Cree /* TX_RING_DOORBELL: Ring Tx doorbell. */ 104adf72ee3SEdward Cree #define ER_GZ_TX_RING_DOORBELL 0x00000200 105adf72ee3SEdward Cree #define ER_GZ_TX_RING_DOORBELL_STEP 65536 106adf72ee3SEdward Cree #define ER_GZ_TX_RING_DOORBELL_ROWS 1024 107adf72ee3SEdward Cree #define ERF_GZ_TX_RING_PIDX_LBN 16 108adf72ee3SEdward Cree #define ERF_GZ_TX_RING_PIDX_WIDTH 16 109adf72ee3SEdward Cree 110adf72ee3SEdward Cree /* TX_DESC_PUSH: Tx ring descriptor push. Reserved for future use. */ 111adf72ee3SEdward Cree #define ER_GZ_TX_DESC_PUSH 0x00000210 112adf72ee3SEdward Cree #define ER_GZ_TX_DESC_PUSH_STEP 65536 113adf72ee3SEdward Cree #define ER_GZ_TX_DESC_PUSH_ROWS 1024 114adf72ee3SEdward Cree 115adf72ee3SEdward Cree /* THE_TIME: NIC hardware time */ 116adf72ee3SEdward Cree #define ER_GZ_THE_TIME 0x00000280 117adf72ee3SEdward Cree #define ER_GZ_THE_TIME_STEP 65536 118adf72ee3SEdward Cree #define ER_GZ_THE_TIME_ROWS 1024 119adf72ee3SEdward Cree #define ERF_GZ_THE_TIME_SECS_LBN 32 120adf72ee3SEdward Cree #define ERF_GZ_THE_TIME_SECS_WIDTH 32 121adf72ee3SEdward Cree #define ERF_GZ_THE_TIME_NANOS_LBN 2 122adf72ee3SEdward Cree #define ERF_GZ_THE_TIME_NANOS_WIDTH 30 123adf72ee3SEdward Cree #define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_LBN 1 124adf72ee3SEdward Cree #define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_WIDTH 1 125adf72ee3SEdward Cree #define ERF_GZ_THE_TIME_CLOCK_IS_SET_LBN 0 126adf72ee3SEdward Cree #define ERF_GZ_THE_TIME_CLOCK_IS_SET_WIDTH 1 127adf72ee3SEdward Cree 128adf72ee3SEdward Cree /* PARAMS_TLV_LEN: Size of design parameters area in bytes */ 129adf72ee3SEdward Cree #define ER_GZ_PARAMS_TLV_LEN 0x00000c00 130adf72ee3SEdward Cree #define ER_GZ_PARAMS_TLV_LEN_STEP 65536 131adf72ee3SEdward Cree #define ER_GZ_PARAMS_TLV_LEN_ROWS 1024 132adf72ee3SEdward Cree 133adf72ee3SEdward Cree /* PARAMS_TLV: Design parameters */ 134adf72ee3SEdward Cree #define ER_GZ_PARAMS_TLV 0x00000c04 135adf72ee3SEdward Cree #define ER_GZ_PARAMS_TLV_STEP 65536 136adf72ee3SEdward Cree #define ER_GZ_PARAMS_TLV_ROWS 1024 137adf72ee3SEdward Cree 138adf72ee3SEdward Cree /* EW_EMBEDDED_EVENT */ 139adf72ee3SEdward Cree #define ESF_GZ_EV_256_EVENT_LBN 0 140adf72ee3SEdward Cree #define ESF_GZ_EV_256_EVENT_WIDTH 64 141adf72ee3SEdward Cree #define ESE_GZ_EW_EMBEDDED_EVENT_STRUCT_SIZE 64 142adf72ee3SEdward Cree 143adf72ee3SEdward Cree /* NMMU_PAGESZ_2M_ADDR */ 144adf72ee3SEdward Cree #define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_LBN 59 145adf72ee3SEdward Cree #define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_WIDTH 5 146adf72ee3SEdward Cree #define ESE_GZ_NMMU_PAGE_SIZE_2M 9 147adf72ee3SEdward Cree #define ESF_GZ_NMMU_2M_PAGE_ID_LBN 21 148adf72ee3SEdward Cree #define ESF_GZ_NMMU_2M_PAGE_ID_WIDTH 38 149adf72ee3SEdward Cree #define ESF_GZ_NMMU_2M_PAGE_OFFSET_LBN 0 150adf72ee3SEdward Cree #define ESF_GZ_NMMU_2M_PAGE_OFFSET_WIDTH 21 151adf72ee3SEdward Cree #define ESE_GZ_NMMU_PAGESZ_2M_ADDR_STRUCT_SIZE 64 152adf72ee3SEdward Cree 153adf72ee3SEdward Cree /* PARAM_TLV */ 154adf72ee3SEdward Cree #define ESF_GZ_TLV_VALUE_LBN 16 155adf72ee3SEdward Cree #define ESF_GZ_TLV_VALUE_WIDTH 8 156adf72ee3SEdward Cree #define ESE_GZ_TLV_VALUE_LENMIN 8 157adf72ee3SEdward Cree #define ESE_GZ_TLV_VALUE_LENMAX 2040 158adf72ee3SEdward Cree #define ESF_GZ_TLV_LEN_LBN 8 159adf72ee3SEdward Cree #define ESF_GZ_TLV_LEN_WIDTH 8 160adf72ee3SEdward Cree #define ESF_GZ_TLV_TYPE_LBN 0 161adf72ee3SEdward Cree #define ESF_GZ_TLV_TYPE_WIDTH 8 162adf72ee3SEdward Cree #define ESE_GZ_DP_NMMU_GROUP_SIZE 5 163adf72ee3SEdward Cree #define ESE_GZ_DP_EVQ_UNSOL_CREDIT_SEQ_BITS 4 164adf72ee3SEdward Cree #define ESE_GZ_DP_TX_EV_NUM_DESCS_BITS 3 165adf72ee3SEdward Cree #define ESE_GZ_DP_RX_EV_NUM_PACKETS_BITS 2 166adf72ee3SEdward Cree #define ESE_GZ_DP_PARTIAL_TSTAMP_SUB_NANO_BITS 1 167adf72ee3SEdward Cree #define ESE_GZ_DP_PAD 0 168adf72ee3SEdward Cree #define ESE_GZ_PARAM_TLV_STRUCT_SIZE 24 169adf72ee3SEdward Cree 170adf72ee3SEdward Cree /* PCI_EXPRESS_XCAP_HDR */ 171adf72ee3SEdward Cree #define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_LBN 20 172adf72ee3SEdward Cree #define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_WIDTH 12 173adf72ee3SEdward Cree #define ESF_GZ_PCI_EXPRESS_XCAP_VER_LBN 16 174adf72ee3SEdward Cree #define ESF_GZ_PCI_EXPRESS_XCAP_VER_WIDTH 4 175adf72ee3SEdward Cree #define ESE_GZ_PCI_EXPRESS_XCAP_VER_VSEC 1 176adf72ee3SEdward Cree #define ESF_GZ_PCI_EXPRESS_XCAP_ID_LBN 0 177adf72ee3SEdward Cree #define ESF_GZ_PCI_EXPRESS_XCAP_ID_WIDTH 16 178adf72ee3SEdward Cree #define ESE_GZ_PCI_EXPRESS_XCAP_ID_VNDR 0xb 179adf72ee3SEdward Cree #define ESE_GZ_PCI_EXPRESS_XCAP_HDR_STRUCT_SIZE 32 180adf72ee3SEdward Cree 181adf72ee3SEdward Cree /* RHEAD_BASE_EVENT */ 182adf72ee3SEdward Cree #define ESF_GZ_E_TYPE_LBN 60 183adf72ee3SEdward Cree #define ESF_GZ_E_TYPE_WIDTH 4 184adf72ee3SEdward Cree #define ESF_GZ_EV_EVQ_PHASE_LBN 59 185adf72ee3SEdward Cree #define ESF_GZ_EV_EVQ_PHASE_WIDTH 1 186adf72ee3SEdward Cree #define ESE_GZ_RHEAD_BASE_EVENT_STRUCT_SIZE 64 187adf72ee3SEdward Cree 188adf72ee3SEdward Cree /* RHEAD_EW_EVENT */ 189adf72ee3SEdward Cree #define ESF_GZ_EV_256_EV32_PHASE_LBN 255 190adf72ee3SEdward Cree #define ESF_GZ_EV_256_EV32_PHASE_WIDTH 1 191adf72ee3SEdward Cree #define ESF_GZ_EV_256_EV32_TYPE_LBN 251 192adf72ee3SEdward Cree #define ESF_GZ_EV_256_EV32_TYPE_WIDTH 4 193adf72ee3SEdward Cree #define ESE_GZ_EF100_EVEW_VIRTQ_DESC 2 194adf72ee3SEdward Cree #define ESE_GZ_EF100_EVEW_TXQ_DESC 1 195adf72ee3SEdward Cree #define ESE_GZ_EF100_EVEW_64BIT 0 196adf72ee3SEdward Cree #define ESE_GZ_RHEAD_EW_EVENT_STRUCT_SIZE 256 197adf72ee3SEdward Cree 198adf72ee3SEdward Cree /* RX_DESC */ 199adf72ee3SEdward Cree #define ESF_GZ_RX_BUF_ADDR_LBN 0 200adf72ee3SEdward Cree #define ESF_GZ_RX_BUF_ADDR_WIDTH 64 201adf72ee3SEdward Cree #define ESE_GZ_RX_DESC_STRUCT_SIZE 64 202adf72ee3SEdward Cree 203adf72ee3SEdward Cree /* TXQ_DESC_PROXY_EVENT */ 204adf72ee3SEdward Cree #define ESF_GZ_EV_TXQ_DP_VI_ID_LBN 128 205adf72ee3SEdward Cree #define ESF_GZ_EV_TXQ_DP_VI_ID_WIDTH 16 206adf72ee3SEdward Cree #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_LBN 0 207adf72ee3SEdward Cree #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_WIDTH 128 208adf72ee3SEdward Cree #define ESE_GZ_TXQ_DESC_PROXY_EVENT_STRUCT_SIZE 144 209adf72ee3SEdward Cree 210adf72ee3SEdward Cree /* TX_DESC_TYPE */ 211adf72ee3SEdward Cree #define ESF_GZ_TX_DESC_TYPE_LBN 124 212adf72ee3SEdward Cree #define ESF_GZ_TX_DESC_TYPE_WIDTH 4 213adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_TYPE_DESC2CMPT 7 214adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_TYPE_MEM2MEM 4 215adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_TYPE_SEG 3 216adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_TYPE_TSO 2 217adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_TYPE_PREFIX 1 218adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_TYPE_SEND 0 219adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_TYPE_STRUCT_SIZE 128 220adf72ee3SEdward Cree 221adf72ee3SEdward Cree /* VIRTQ_DESC_PROXY_EVENT */ 222adf72ee3SEdward Cree #define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_LBN 144 223adf72ee3SEdward Cree #define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_WIDTH 16 224adf72ee3SEdward Cree #define ESF_GZ_EV_VQ_DP_VI_ID_LBN 128 225adf72ee3SEdward Cree #define ESF_GZ_EV_VQ_DP_VI_ID_WIDTH 16 226adf72ee3SEdward Cree #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_LBN 0 227adf72ee3SEdward Cree #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_WIDTH 128 228adf72ee3SEdward Cree #define ESE_GZ_VIRTQ_DESC_PROXY_EVENT_STRUCT_SIZE 160 229adf72ee3SEdward Cree 230adf72ee3SEdward Cree /* XIL_CFGBAR_TBL_ENTRY */ 231adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_LBN 96 232adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_WIDTH 32 233adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_LBN 68 234adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_WIDTH 60 235adf72ee3SEdward Cree #define ESE_GZ_CONT_CAP_OFFSET_BYTES_SHIFT 4 236adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_LBN 67 237adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_WIDTH 29 238adf72ee3SEdward Cree #define ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT 4 239adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_LBN 68 240adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_WIDTH 28 241adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_CONT_CAP_RSV_LBN 67 242adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_CONT_CAP_RSV_WIDTH 1 243adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_EF100_BAR_LBN 64 244adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_EF100_BAR_WIDTH 3 245adf72ee3SEdward Cree #define ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID 7 246adf72ee3SEdward Cree #define ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM 6 247adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_CONT_CAP_BAR_LBN 64 248adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_CONT_CAP_BAR_WIDTH 3 249adf72ee3SEdward Cree #define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_INVALID 7 250adf72ee3SEdward Cree #define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_EXPANSION_ROM 6 251adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_ENTRY_SIZE_LBN 32 252adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_ENTRY_SIZE_WIDTH 32 253adf72ee3SEdward Cree #define ESE_GZ_CFGBAR_ENTRY_SIZE_EF100 12 254adf72ee3SEdward Cree #define ESE_GZ_CFGBAR_ENTRY_HEADER_SIZE 8 255adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_ENTRY_LAST_LBN 28 256adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_ENTRY_LAST_WIDTH 1 257adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_ENTRY_REV_LBN 20 258adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_ENTRY_REV_WIDTH 8 259adf72ee3SEdward Cree #define ESE_GZ_CFGBAR_ENTRY_REV_EF100 0 260adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_ENTRY_FORMAT_LBN 0 261adf72ee3SEdward Cree #define ESF_GZ_CFGBAR_ENTRY_FORMAT_WIDTH 20 262adf72ee3SEdward Cree #define ESE_GZ_CFGBAR_ENTRY_LAST 0xfffff 263adf72ee3SEdward Cree #define ESE_GZ_CFGBAR_ENTRY_CONT_CAP_ADDR 0xffffe 264adf72ee3SEdward Cree #define ESE_GZ_CFGBAR_ENTRY_EF100 0xef100 265adf72ee3SEdward Cree #define ESE_GZ_XIL_CFGBAR_TBL_ENTRY_STRUCT_SIZE 128 266adf72ee3SEdward Cree 267adf72ee3SEdward Cree /* XIL_CFGBAR_VSEC */ 268adf72ee3SEdward Cree #define ESF_GZ_VSEC_TBL_OFF_HI_LBN 64 269adf72ee3SEdward Cree #define ESF_GZ_VSEC_TBL_OFF_HI_WIDTH 32 270adf72ee3SEdward Cree #define ESE_GZ_VSEC_TBL_OFF_HI_BYTES_SHIFT 32 271adf72ee3SEdward Cree #define ESF_GZ_VSEC_TBL_OFF_LO_LBN 36 272adf72ee3SEdward Cree #define ESF_GZ_VSEC_TBL_OFF_LO_WIDTH 28 273adf72ee3SEdward Cree #define ESE_GZ_VSEC_TBL_OFF_LO_BYTES_SHIFT 4 274adf72ee3SEdward Cree #define ESF_GZ_VSEC_TBL_BAR_LBN 32 275adf72ee3SEdward Cree #define ESF_GZ_VSEC_TBL_BAR_WIDTH 4 276adf72ee3SEdward Cree #define ESE_GZ_VSEC_BAR_NUM_INVALID 7 277adf72ee3SEdward Cree #define ESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM 6 278adf72ee3SEdward Cree #define ESF_GZ_VSEC_LEN_LBN 20 279adf72ee3SEdward Cree #define ESF_GZ_VSEC_LEN_WIDTH 12 280adf72ee3SEdward Cree #define ESE_GZ_VSEC_LEN_HIGH_OFFT 16 281adf72ee3SEdward Cree #define ESE_GZ_VSEC_LEN_MIN 12 282adf72ee3SEdward Cree #define ESF_GZ_VSEC_VER_LBN 16 283adf72ee3SEdward Cree #define ESF_GZ_VSEC_VER_WIDTH 4 284adf72ee3SEdward Cree #define ESE_GZ_VSEC_VER_XIL_CFGBAR 0 285adf72ee3SEdward Cree #define ESF_GZ_VSEC_ID_LBN 0 286adf72ee3SEdward Cree #define ESF_GZ_VSEC_ID_WIDTH 16 287adf72ee3SEdward Cree #define ESE_GZ_XILINX_VSEC_ID 0x20 288adf72ee3SEdward Cree #define ESE_GZ_XIL_CFGBAR_VSEC_STRUCT_SIZE 96 289adf72ee3SEdward Cree 290adf72ee3SEdward Cree /* rh_egres_hclass */ 291adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_LBN 15 292adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_WIDTH 1 293adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_LBN 13 294adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_WIDTH 2 295adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_LBN 12 296adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_WIDTH 1 297adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_LBN 10 298adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_WIDTH 2 299adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_LBN 8 300adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_WIDTH 2 301adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_LBN 5 302adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_WIDTH 3 303adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_LBN 3 304adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_WIDTH 2 305adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_LBN 2 306adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_WIDTH 1 307adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_LBN 0 308adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_WIDTH 2 309adf72ee3SEdward Cree #define ESE_GZ_RH_EGRES_HCLASS_STRUCT_SIZE 16 310adf72ee3SEdward Cree 311adf72ee3SEdward Cree /* sf_driver */ 312adf72ee3SEdward Cree #define ESF_GZ_DRIVER_E_TYPE_LBN 60 313adf72ee3SEdward Cree #define ESF_GZ_DRIVER_E_TYPE_WIDTH 4 314adf72ee3SEdward Cree #define ESF_GZ_DRIVER_PHASE_LBN 59 315adf72ee3SEdward Cree #define ESF_GZ_DRIVER_PHASE_WIDTH 1 316adf72ee3SEdward Cree #define ESF_GZ_DRIVER_DATA_LBN 0 317adf72ee3SEdward Cree #define ESF_GZ_DRIVER_DATA_WIDTH 59 318adf72ee3SEdward Cree #define ESE_GZ_SF_DRIVER_STRUCT_SIZE 64 319adf72ee3SEdward Cree 320adf72ee3SEdward Cree /* sf_ev_rsvd */ 321adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_TBD_NEXT_LBN 34 322adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_TBD_NEXT_WIDTH 3 323adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_LBN 30 324adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_WIDTH 4 325adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_SRC_QID_LBN 18 326adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_SRC_QID_WIDTH 12 327adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_SEQ_NUM_LBN 2 328adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_SEQ_NUM_WIDTH 16 329adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_TBD_LBN 0 330adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_TBD_WIDTH 2 331adf72ee3SEdward Cree #define ESE_GZ_SF_EV_RSVD_STRUCT_SIZE 37 332adf72ee3SEdward Cree 333adf72ee3SEdward Cree /* sf_flush_evnt */ 334adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_E_TYPE_LBN 60 335adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_E_TYPE_WIDTH 4 336adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_PHASE_LBN 59 337adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_PHASE_WIDTH 1 338adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_SUB_TYPE_LBN 53 339adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_SUB_TYPE_WIDTH 6 340adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_RSVD_LBN 10 341adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_RSVD_WIDTH 43 342adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_LABEL_LBN 4 343adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_LABEL_WIDTH 6 344adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_FLUSH_TYPE_LBN 0 345adf72ee3SEdward Cree #define ESF_GZ_EV_FLSH_FLUSH_TYPE_WIDTH 4 346adf72ee3SEdward Cree #define ESE_GZ_SF_FLUSH_EVNT_STRUCT_SIZE 64 347adf72ee3SEdward Cree 348adf72ee3SEdward Cree /* sf_rx_pkts */ 349adf72ee3SEdward Cree #define ESF_GZ_EV_RXPKTS_E_TYPE_LBN 60 350adf72ee3SEdward Cree #define ESF_GZ_EV_RXPKTS_E_TYPE_WIDTH 4 351adf72ee3SEdward Cree #define ESF_GZ_EV_RXPKTS_PHASE_LBN 59 352adf72ee3SEdward Cree #define ESF_GZ_EV_RXPKTS_PHASE_WIDTH 1 353adf72ee3SEdward Cree #define ESF_GZ_EV_RXPKTS_RSVD_LBN 22 354adf72ee3SEdward Cree #define ESF_GZ_EV_RXPKTS_RSVD_WIDTH 37 355adf72ee3SEdward Cree #define ESF_GZ_EV_RXPKTS_Q_LABEL_LBN 16 356adf72ee3SEdward Cree #define ESF_GZ_EV_RXPKTS_Q_LABEL_WIDTH 6 357adf72ee3SEdward Cree #define ESF_GZ_EV_RXPKTS_NUM_PKT_LBN 0 358adf72ee3SEdward Cree #define ESF_GZ_EV_RXPKTS_NUM_PKT_WIDTH 16 359adf72ee3SEdward Cree #define ESE_GZ_SF_RX_PKTS_STRUCT_SIZE 64 360adf72ee3SEdward Cree 361adf72ee3SEdward Cree /* sf_rx_prefix */ 362adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_LBN 160 363adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_WIDTH 16 364adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_CSUM_FRAME_LBN 144 365adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_CSUM_FRAME_WIDTH 16 366*8ca353daSEdward Cree #define ESF_GZ_RX_PREFIX_INGRESS_MPORT_LBN 128 367*8ca353daSEdward Cree #define ESF_GZ_RX_PREFIX_INGRESS_MPORT_WIDTH 16 368adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_USER_MARK_LBN 96 369adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_USER_MARK_WIDTH 32 370adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_RSS_HASH_LBN 64 371adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_RSS_HASH_WIDTH 32 372*8ca353daSEdward Cree #define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN 34 373*8ca353daSEdward Cree #define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_WIDTH 30 374*8ca353daSEdward Cree #define ESF_GZ_RX_PREFIX_VSWITCH_STATUS_LBN 33 375*8ca353daSEdward Cree #define ESF_GZ_RX_PREFIX_VSWITCH_STATUS_WIDTH 1 376*8ca353daSEdward Cree #define ESF_GZ_RX_PREFIX_VLAN_STRIPPED_LBN 32 377*8ca353daSEdward Cree #define ESF_GZ_RX_PREFIX_VLAN_STRIPPED_WIDTH 1 378adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_CLASS_LBN 16 379adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_CLASS_WIDTH 16 380adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_USER_FLAG_LBN 15 381adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_USER_FLAG_WIDTH 1 382adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_RSS_HASH_VALID_LBN 14 383adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_RSS_HASH_VALID_WIDTH 1 384adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_LENGTH_LBN 0 385adf72ee3SEdward Cree #define ESF_GZ_RX_PREFIX_LENGTH_WIDTH 14 386adf72ee3SEdward Cree #define ESE_GZ_SF_RX_PREFIX_STRUCT_SIZE 176 387adf72ee3SEdward Cree 388adf72ee3SEdward Cree /* sf_rxtx_generic */ 389adf72ee3SEdward Cree #define ESF_GZ_EV_BARRIER_LBN 167 390adf72ee3SEdward Cree #define ESF_GZ_EV_BARRIER_WIDTH 1 391adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_LBN 130 392adf72ee3SEdward Cree #define ESF_GZ_EV_RSVD_WIDTH 37 393adf72ee3SEdward Cree #define ESF_GZ_EV_DPRXY_LBN 129 394adf72ee3SEdward Cree #define ESF_GZ_EV_DPRXY_WIDTH 1 395adf72ee3SEdward Cree #define ESF_GZ_EV_VIRTIO_LBN 128 396adf72ee3SEdward Cree #define ESF_GZ_EV_VIRTIO_WIDTH 1 397adf72ee3SEdward Cree #define ESF_GZ_EV_COUNT_LBN 0 398adf72ee3SEdward Cree #define ESF_GZ_EV_COUNT_WIDTH 128 399adf72ee3SEdward Cree #define ESE_GZ_SF_RXTX_GENERIC_STRUCT_SIZE 168 400adf72ee3SEdward Cree 401adf72ee3SEdward Cree /* sf_ts_stamp */ 402adf72ee3SEdward Cree #define ESF_GZ_EV_TS_E_TYPE_LBN 60 403adf72ee3SEdward Cree #define ESF_GZ_EV_TS_E_TYPE_WIDTH 4 404adf72ee3SEdward Cree #define ESF_GZ_EV_TS_PHASE_LBN 59 405adf72ee3SEdward Cree #define ESF_GZ_EV_TS_PHASE_WIDTH 1 406adf72ee3SEdward Cree #define ESF_GZ_EV_TS_RSVD_LBN 56 407adf72ee3SEdward Cree #define ESF_GZ_EV_TS_RSVD_WIDTH 3 408adf72ee3SEdward Cree #define ESF_GZ_EV_TS_STATUS_LBN 54 409adf72ee3SEdward Cree #define ESF_GZ_EV_TS_STATUS_WIDTH 2 410adf72ee3SEdward Cree #define ESF_GZ_EV_TS_Q_LABEL_LBN 48 411adf72ee3SEdward Cree #define ESF_GZ_EV_TS_Q_LABEL_WIDTH 6 412adf72ee3SEdward Cree #define ESF_GZ_EV_TS_DESC_ID_LBN 32 413adf72ee3SEdward Cree #define ESF_GZ_EV_TS_DESC_ID_WIDTH 16 414adf72ee3SEdward Cree #define ESF_GZ_EV_TS_PARTIAL_STAMP_LBN 0 415adf72ee3SEdward Cree #define ESF_GZ_EV_TS_PARTIAL_STAMP_WIDTH 32 416adf72ee3SEdward Cree #define ESE_GZ_SF_TS_STAMP_STRUCT_SIZE 64 417adf72ee3SEdward Cree 418adf72ee3SEdward Cree /* sf_tx_cmplt */ 419adf72ee3SEdward Cree #define ESF_GZ_EV_TXCMPL_E_TYPE_LBN 60 420adf72ee3SEdward Cree #define ESF_GZ_EV_TXCMPL_E_TYPE_WIDTH 4 421adf72ee3SEdward Cree #define ESF_GZ_EV_TXCMPL_PHASE_LBN 59 422adf72ee3SEdward Cree #define ESF_GZ_EV_TXCMPL_PHASE_WIDTH 1 423adf72ee3SEdward Cree #define ESF_GZ_EV_TXCMPL_RSVD_LBN 22 424adf72ee3SEdward Cree #define ESF_GZ_EV_TXCMPL_RSVD_WIDTH 37 425adf72ee3SEdward Cree #define ESF_GZ_EV_TXCMPL_Q_LABEL_LBN 16 426adf72ee3SEdward Cree #define ESF_GZ_EV_TXCMPL_Q_LABEL_WIDTH 6 427adf72ee3SEdward Cree #define ESF_GZ_EV_TXCMPL_NUM_DESC_LBN 0 428adf72ee3SEdward Cree #define ESF_GZ_EV_TXCMPL_NUM_DESC_WIDTH 16 429adf72ee3SEdward Cree #define ESE_GZ_SF_TX_CMPLT_STRUCT_SIZE 64 430adf72ee3SEdward Cree 431adf72ee3SEdward Cree /* sf_tx_desc2cmpt_dsc_fmt */ 432adf72ee3SEdward Cree #define ESF_GZ_D2C_TGT_VI_ID_LBN 108 433adf72ee3SEdward Cree #define ESF_GZ_D2C_TGT_VI_ID_WIDTH 16 434adf72ee3SEdward Cree #define ESF_GZ_D2C_CMPT2_LBN 107 435adf72ee3SEdward Cree #define ESF_GZ_D2C_CMPT2_WIDTH 1 436adf72ee3SEdward Cree #define ESF_GZ_D2C_ABS_VI_ID_LBN 106 437adf72ee3SEdward Cree #define ESF_GZ_D2C_ABS_VI_ID_WIDTH 1 438adf72ee3SEdward Cree #define ESF_GZ_D2C_ORDERED_LBN 105 439adf72ee3SEdward Cree #define ESF_GZ_D2C_ORDERED_WIDTH 1 440adf72ee3SEdward Cree #define ESF_GZ_D2C_SKIP_N_LBN 97 441adf72ee3SEdward Cree #define ESF_GZ_D2C_SKIP_N_WIDTH 8 442adf72ee3SEdward Cree #define ESF_GZ_D2C_RSVD_LBN 64 443adf72ee3SEdward Cree #define ESF_GZ_D2C_RSVD_WIDTH 33 444adf72ee3SEdward Cree #define ESF_GZ_D2C_COMPLETION_LBN 0 445adf72ee3SEdward Cree #define ESF_GZ_D2C_COMPLETION_WIDTH 64 446adf72ee3SEdward Cree #define ESE_GZ_SF_TX_DESC2CMPT_DSC_FMT_STRUCT_SIZE 124 447adf72ee3SEdward Cree 448adf72ee3SEdward Cree /* sf_tx_mem2mem_dsc_fmt */ 449adf72ee3SEdward Cree #define ESF_GZ_M2M_ADDR_SPC_EN_LBN 123 450adf72ee3SEdward Cree #define ESF_GZ_M2M_ADDR_SPC_EN_WIDTH 1 451adf72ee3SEdward Cree #define ESF_GZ_M2M_TRANSLATE_ADDR_LBN 122 452adf72ee3SEdward Cree #define ESF_GZ_M2M_TRANSLATE_ADDR_WIDTH 1 453adf72ee3SEdward Cree #define ESF_GZ_M2M_RSVD_LBN 120 454adf72ee3SEdward Cree #define ESF_GZ_M2M_RSVD_WIDTH 2 455*8ca353daSEdward Cree #define ESF_GZ_M2M_ADDR_SPC_ID_LBN 84 456*8ca353daSEdward Cree #define ESF_GZ_M2M_ADDR_SPC_ID_WIDTH 36 457adf72ee3SEdward Cree #define ESF_GZ_M2M_LEN_MINUS_1_LBN 64 458adf72ee3SEdward Cree #define ESF_GZ_M2M_LEN_MINUS_1_WIDTH 20 459adf72ee3SEdward Cree #define ESF_GZ_M2M_ADDR_LBN 0 460adf72ee3SEdward Cree #define ESF_GZ_M2M_ADDR_WIDTH 64 461adf72ee3SEdward Cree #define ESE_GZ_SF_TX_MEM2MEM_DSC_FMT_STRUCT_SIZE 124 462adf72ee3SEdward Cree 463adf72ee3SEdward Cree /* sf_tx_ovr_dsc_fmt */ 464adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_MARK_EN_LBN 123 465adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_MARK_EN_WIDTH 1 466adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_LBN 122 467adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_WIDTH 1 468adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_LBN 121 469adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_WIDTH 1 470adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_LBN 120 471adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_WIDTH 1 472adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_RSRVD_LBN 64 473adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_RSRVD_WIDTH 56 474adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_LBN 48 475adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_WIDTH 16 476adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_LBN 32 477adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_WIDTH 16 478adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_MARK_LBN 0 479adf72ee3SEdward Cree #define ESF_GZ_TX_PREFIX_MARK_WIDTH 32 480adf72ee3SEdward Cree #define ESE_GZ_SF_TX_OVR_DSC_FMT_STRUCT_SIZE 124 481adf72ee3SEdward Cree 482adf72ee3SEdward Cree /* sf_tx_seg_dsc_fmt */ 483adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_ADDR_SPC_EN_LBN 123 484adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_ADDR_SPC_EN_WIDTH 1 485adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_TRANSLATE_ADDR_LBN 122 486adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_TRANSLATE_ADDR_WIDTH 1 487adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_RSVD2_LBN 120 488adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_RSVD2_WIDTH 2 489*8ca353daSEdward Cree #define ESF_GZ_TX_SEG_ADDR_SPC_ID_LBN 84 490*8ca353daSEdward Cree #define ESF_GZ_TX_SEG_ADDR_SPC_ID_WIDTH 36 491adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_RSVD_LBN 80 492adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_RSVD_WIDTH 4 493adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_LEN_LBN 64 494adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_LEN_WIDTH 16 495adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_ADDR_LBN 0 496adf72ee3SEdward Cree #define ESF_GZ_TX_SEG_ADDR_WIDTH 64 497adf72ee3SEdward Cree #define ESE_GZ_SF_TX_SEG_DSC_FMT_STRUCT_SIZE 124 498adf72ee3SEdward Cree 499adf72ee3SEdward Cree /* sf_tx_std_dsc_fmt */ 500adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_LBN 108 501adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_WIDTH 16 502adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_VLAN_INSERT_EN_LBN 107 503adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_VLAN_INSERT_EN_WIDTH 1 504adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_TSTAMP_REQ_LBN 106 505adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_TSTAMP_REQ_WIDTH 1 506adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_OUTER_L4_LBN 105 507adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_OUTER_L4_WIDTH 1 508adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_OUTER_L3_LBN 104 509adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_OUTER_L3_WIDTH 1 510adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_INNER_L3_LBN 101 511adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_INNER_L3_WIDTH 3 512adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_RSVD_LBN 99 513adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_RSVD_WIDTH 2 514adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_LBN 97 515adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_WIDTH 2 516adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_LBN 92 517adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_WIDTH 5 518adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_LBN 83 519adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_WIDTH 9 520adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_NUM_SEGS_LBN 78 521adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_NUM_SEGS_WIDTH 5 522adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_LEN_LBN 64 523adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_LEN_WIDTH 14 524adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_ADDR_LBN 0 525adf72ee3SEdward Cree #define ESF_GZ_TX_SEND_ADDR_WIDTH 64 526adf72ee3SEdward Cree #define ESE_GZ_SF_TX_STD_DSC_FMT_STRUCT_SIZE 124 527adf72ee3SEdward Cree 528adf72ee3SEdward Cree /* sf_tx_tso_dsc_fmt */ 529adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_LBN 108 530adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_WIDTH 16 531adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_VLAN_INSERT_EN_LBN 107 532adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_VLAN_INSERT_EN_WIDTH 1 533adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_TSTAMP_REQ_LBN 106 534adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_TSTAMP_REQ_WIDTH 1 535adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_CSO_OUTER_L4_LBN 105 536adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_CSO_OUTER_L4_WIDTH 1 537adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_CSO_OUTER_L3_LBN 104 538adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_CSO_OUTER_L3_WIDTH 1 539adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_CSO_INNER_L3_LBN 101 540adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_CSO_INNER_L3_WIDTH 3 541adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_RSVD_LBN 94 542adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_RSVD_WIDTH 7 543adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_CSO_INNER_L4_LBN 93 544adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_CSO_INNER_L4_WIDTH 1 545adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_INNER_L4_OFF_W_LBN 85 546adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_INNER_L4_OFF_W_WIDTH 8 547adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_INNER_L3_OFF_W_LBN 77 548adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_INNER_L3_OFF_W_WIDTH 8 549adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_LBN 69 550adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_WIDTH 8 551adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_LBN 64 552adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_WIDTH 5 553adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_PAYLOAD_LEN_LBN 42 554adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_PAYLOAD_LEN_WIDTH 22 555adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_HDR_LEN_W_LBN 34 556adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_HDR_LEN_W_WIDTH 8 557adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_LBN 33 558adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_WIDTH 1 559adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_LBN 32 560adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_WIDTH 1 561adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_LBN 31 562adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_WIDTH 1 563adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_LBN 29 564adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_WIDTH 2 565adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_LBN 27 566adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_WIDTH 2 567adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_LBN 17 568adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_WIDTH 10 569adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_HDR_NUM_SEGS_LBN 14 570adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_HDR_NUM_SEGS_WIDTH 3 571adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_MSS_LBN 0 572adf72ee3SEdward Cree #define ESF_GZ_TX_TSO_MSS_WIDTH 14 573adf72ee3SEdward Cree #define ESE_GZ_SF_TX_TSO_DSC_FMT_STRUCT_SIZE 124 574adf72ee3SEdward Cree 575adf72ee3SEdward Cree 576*8ca353daSEdward Cree /* Enum D2VIO_MSG_OP */ 577*8ca353daSEdward Cree #define ESE_GZ_QUE_JBDNE 3 578*8ca353daSEdward Cree #define ESE_GZ_QUE_EVICT 2 579*8ca353daSEdward Cree #define ESE_GZ_QUE_EMPTY 1 580*8ca353daSEdward Cree #define ESE_GZ_NOP 0 581*8ca353daSEdward Cree 582adf72ee3SEdward Cree /* Enum DESIGN_PARAMS */ 583adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_RX_MAX_RUNT 17 584adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_VI_STRIDES 16 585adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES 15 586adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS 14 587adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN 13 588adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_COMPAT 12 589adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES 11 590adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS 10 591adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN 9 592adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY 8 593adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY 7 594adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS 6 595adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN 5 596adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS 4 597adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE 3 598adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS 2 599adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS 1 600adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_PAD 0 601adf72ee3SEdward Cree 602adf72ee3SEdward Cree /* Enum DESIGN_PARAM_DEFAULTS */ 603adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT 0x3fffff 604adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT 8192 605adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN_DEFAULT 8192 606adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS_DEFAULT 0x1106 607adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT 0x3ff 608adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_RX_MAX_RUNT_DEFAULT 640 609adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS_DEFAULT 512 610adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES_DEFAULT 512 611adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT 192 612adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY_DEFAULT 64 613adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY_DEFAULT 64 614adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE_DEFAULT 32 615adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT 16 616adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS_DEFAULT 7 617adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT 4 618adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS_DEFAULT 2 619adf72ee3SEdward Cree #define ESE_EF100_DP_GZ_COMPAT_DEFAULT 0 620adf72ee3SEdward Cree 621adf72ee3SEdward Cree /* Enum HOST_IF_CONSTANTS */ 622adf72ee3SEdward Cree #define ESE_GZ_FCW_LEN 0x4C 623adf72ee3SEdward Cree #define ESE_GZ_RX_PKT_PREFIX_LEN 22 624adf72ee3SEdward Cree 625adf72ee3SEdward Cree /* Enum PCI_CONSTANTS */ 626adf72ee3SEdward Cree #define ESE_GZ_PCI_BASE_CONFIG_SPACE_SIZE 256 627adf72ee3SEdward Cree #define ESE_GZ_PCI_EXPRESS_XCAP_HDR_SIZE 4 628adf72ee3SEdward Cree 629*8ca353daSEdward Cree /* Enum RH_DSC_TYPE */ 630*8ca353daSEdward Cree #define ESE_GZ_TX_TOMB 0xF 631*8ca353daSEdward Cree #define ESE_GZ_TX_VIO 0xE 632*8ca353daSEdward Cree #define ESE_GZ_TX_TSO_OVRRD 0x8 633*8ca353daSEdward Cree #define ESE_GZ_TX_D2CMP 0x7 634*8ca353daSEdward Cree #define ESE_GZ_TX_DATA 0x6 635*8ca353daSEdward Cree #define ESE_GZ_TX_D2M 0x5 636*8ca353daSEdward Cree #define ESE_GZ_TX_M2M 0x4 637*8ca353daSEdward Cree #define ESE_GZ_TX_SEG 0x3 638*8ca353daSEdward Cree #define ESE_GZ_TX_TSO 0x2 639*8ca353daSEdward Cree #define ESE_GZ_TX_OVRRD 0x1 640*8ca353daSEdward Cree #define ESE_GZ_TX_SEND 0x0 641*8ca353daSEdward Cree 642adf72ee3SEdward Cree /* Enum RH_HCLASS_L2_CLASS */ 643adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L2_CLASS_E2_0123VLAN 1 644adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L2_CLASS_OTHER 0 645adf72ee3SEdward Cree 646adf72ee3SEdward Cree /* Enum RH_HCLASS_L2_STATUS */ 647adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L2_STATUS_RESERVED 3 648adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L2_STATUS_FCS_ERR 2 649adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L2_STATUS_LEN_ERR 1 650adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L2_STATUS_OK 0 651adf72ee3SEdward Cree 652adf72ee3SEdward Cree /* Enum RH_HCLASS_L3_CLASS */ 653adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L3_CLASS_OTHER 3 654adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L3_CLASS_IP6 2 655adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L3_CLASS_IP4BAD 1 656adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L3_CLASS_IP4GOOD 0 657adf72ee3SEdward Cree 658adf72ee3SEdward Cree /* Enum RH_HCLASS_L4_CLASS */ 659adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L4_CLASS_OTHER 3 660adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L4_CLASS_FRAG 2 661adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L4_CLASS_UDP 1 662adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L4_CLASS_TCP 0 663adf72ee3SEdward Cree 664adf72ee3SEdward Cree /* Enum RH_HCLASS_L4_CSUM */ 665adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L4_CSUM_GOOD 1 666adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_L4_CSUM_BAD_OR_UNKNOWN 0 667adf72ee3SEdward Cree 668adf72ee3SEdward Cree /* Enum RH_HCLASS_TUNNEL_CLASS */ 669adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_7 7 670adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_6 6 671adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_5 5 672adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_4 4 673adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_GENEVE 3 674adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NVGRE 2 675adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_VXLAN 1 676adf72ee3SEdward Cree #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NONE 0 677adf72ee3SEdward Cree 678*8ca353daSEdward Cree /* Enum SF_CTL_EVENT_SUBTYPE */ 679*8ca353daSEdward Cree #define ESE_GZ_EF100_CTL_EV_EVQ_TIMEOUT 0x3 680*8ca353daSEdward Cree #define ESE_GZ_EF100_CTL_EV_FLUSH 0x2 681*8ca353daSEdward Cree #define ESE_GZ_EF100_CTL_EV_TIME_SYNC 0x1 682*8ca353daSEdward Cree #define ESE_GZ_EF100_CTL_EV_UNSOL_OVERFLOW 0x0 683*8ca353daSEdward Cree 684*8ca353daSEdward Cree /* Enum SF_EVENT_TYPE */ 685*8ca353daSEdward Cree #define ESE_GZ_EF100_EV_DRIVER 0x5 686*8ca353daSEdward Cree #define ESE_GZ_EF100_EV_MCDI 0x4 687*8ca353daSEdward Cree #define ESE_GZ_EF100_EV_CONTROL 0x3 688*8ca353daSEdward Cree #define ESE_GZ_EF100_EV_TX_TIMESTAMP 0x2 689*8ca353daSEdward Cree #define ESE_GZ_EF100_EV_TX_COMPLETION 0x1 690*8ca353daSEdward Cree #define ESE_GZ_EF100_EV_RX_PKTS 0x0 691*8ca353daSEdward Cree 692*8ca353daSEdward Cree /* Enum SF_EW_EVENT_TYPE */ 693*8ca353daSEdward Cree #define ESE_GZ_EF100_EWEV_VIRTQ_DESC 0x2 694*8ca353daSEdward Cree #define ESE_GZ_EF100_EWEV_TXQ_DESC 0x1 695*8ca353daSEdward Cree #define ESE_GZ_EF100_EWEV_64BIT 0x0 696*8ca353daSEdward Cree 697adf72ee3SEdward Cree /* Enum TX_DESC_CSO_PARTIAL_EN */ 698adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_TCP 2 699adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_UDP 1 700adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_OFF 0 701adf72ee3SEdward Cree 702adf72ee3SEdward Cree /* Enum TX_DESC_CS_INNER_L3 */ 703adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_CS_INNER_L3_GENEVE 3 704adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_CS_INNER_L3_NVGRE 2 705adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_CS_INNER_L3_VXLAN 1 706adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_CS_INNER_L3_OFF 0 707adf72ee3SEdward Cree 708adf72ee3SEdward Cree /* Enum TX_DESC_IP4_ID */ 709adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_IP4_ID_INC_MOD16 2 710adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_IP4_ID_INC_MOD15 1 711adf72ee3SEdward Cree #define ESE_GZ_TX_DESC_IP4_ID_NO_OP 0 712*8ca353daSEdward Cree 713*8ca353daSEdward Cree /* Enum VIRTIO_NET_HDR_F */ 714*8ca353daSEdward Cree #define ESE_GZ_NEEDS_CSUM 0x1 715*8ca353daSEdward Cree 716*8ca353daSEdward Cree /* Enum VIRTIO_NET_HDR_GSO */ 717*8ca353daSEdward Cree #define ESE_GZ_TCPV6 0x4 718*8ca353daSEdward Cree #define ESE_GZ_UDP 0x3 719*8ca353daSEdward Cree #define ESE_GZ_TCPV4 0x1 720*8ca353daSEdward Cree #define ESE_GZ_NONE 0x0 721adf72ee3SEdward Cree /**************************************************************************/ 722adf72ee3SEdward Cree 723adf72ee3SEdward Cree #define ESF_GZ_EV_DEBUG_EVENT_GEN_FLAGS_LBN 44 724adf72ee3SEdward Cree #define ESF_GZ_EV_DEBUG_EVENT_GEN_FLAGS_WIDTH 4 725adf72ee3SEdward Cree #define ESF_GZ_EV_DEBUG_SRC_QID_LBN 32 726adf72ee3SEdward Cree #define ESF_GZ_EV_DEBUG_SRC_QID_WIDTH 12 727adf72ee3SEdward Cree #define ESF_GZ_EV_DEBUG_SEQ_NUM_LBN 16 728adf72ee3SEdward Cree #define ESF_GZ_EV_DEBUG_SEQ_NUM_WIDTH 16 729adf72ee3SEdward Cree 730adf72ee3SEdward Cree #endif /* EFX_EF100_REGS_H */ 731