1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3  * Driver for Solarflare network controllers and boards
4  * Copyright 2018 Solarflare Communications Inc.
5  * Copyright 2019-2022 Xilinx Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published
9  * by the Free Software Foundation, incorporated herein by reference.
10  */
11 
12 #include "ef100_nic.h"
13 #include "efx_common.h"
14 #include "efx_channels.h"
15 #include "io.h"
16 #include "selftest.h"
17 #include "ef100_regs.h"
18 #include "mcdi.h"
19 #include "mcdi_pcol.h"
20 #include "mcdi_port_common.h"
21 #include "mcdi_functions.h"
22 #include "mcdi_filters.h"
23 #include "ef100_rx.h"
24 #include "ef100_tx.h"
25 #include "ef100_sriov.h"
26 #include "ef100_netdev.h"
27 #include "rx_common.h"
28 
29 #define EF100_MAX_VIS 4096
30 #define EF100_NUM_MCDI_BUFFERS	1
31 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
32 
33 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT)
34 
35 /*	MCDI
36  */
37 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr)
38 {
39 	struct ef100_nic_data *nic_data = efx->nic_data;
40 
41 	if (dma_addr)
42 		*dma_addr = nic_data->mcdi_buf.dma_addr +
43 			    bufid * ALIGN(MCDI_BUF_LEN, 256);
44 	return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256);
45 }
46 
47 static int ef100_get_warm_boot_count(struct efx_nic *efx)
48 {
49 	efx_dword_t reg;
50 
51 	efx_readd(efx, &reg, efx_reg(efx, ER_GZ_MC_SFT_STATUS));
52 
53 	if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) {
54 		netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n");
55 		efx->state = STATE_DISABLED;
56 		return -ENETDOWN;
57 	} else {
58 		return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
59 			EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
60 	}
61 }
62 
63 static void ef100_mcdi_request(struct efx_nic *efx,
64 			       const efx_dword_t *hdr, size_t hdr_len,
65 			       const efx_dword_t *sdu, size_t sdu_len)
66 {
67 	dma_addr_t dma_addr;
68 	u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr);
69 
70 	memcpy(pdu, hdr, hdr_len);
71 	memcpy(pdu + hdr_len, sdu, sdu_len);
72 	wmb();
73 
74 	/* The hardware provides 'low' and 'high' (doorbell) registers
75 	 * for passing the 64-bit address of an MCDI request to
76 	 * firmware.  However the dwords are swapped by firmware.  The
77 	 * least significant bits of the doorbell are then 0 for all
78 	 * MCDI requests due to alignment.
79 	 */
80 	_efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32),  efx_reg(efx, ER_GZ_MC_DB_LWRD));
81 	_efx_writed(efx, cpu_to_le32((u32)dma_addr),  efx_reg(efx, ER_GZ_MC_DB_HWRD));
82 }
83 
84 static bool ef100_mcdi_poll_response(struct efx_nic *efx)
85 {
86 	const efx_dword_t hdr =
87 		*(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL));
88 
89 	rmb();
90 	return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
91 }
92 
93 static void ef100_mcdi_read_response(struct efx_nic *efx,
94 				     efx_dword_t *outbuf, size_t offset,
95 				     size_t outlen)
96 {
97 	const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL);
98 
99 	memcpy(outbuf, pdu + offset, outlen);
100 }
101 
102 static int ef100_mcdi_poll_reboot(struct efx_nic *efx)
103 {
104 	struct ef100_nic_data *nic_data = efx->nic_data;
105 	int rc;
106 
107 	rc = ef100_get_warm_boot_count(efx);
108 	if (rc < 0) {
109 		/* The firmware is presumably in the process of
110 		 * rebooting.  However, we are supposed to report each
111 		 * reboot just once, so we must only do that once we
112 		 * can read and store the updated warm boot count.
113 		 */
114 		return 0;
115 	}
116 
117 	if (rc == nic_data->warm_boot_count)
118 		return 0;
119 
120 	nic_data->warm_boot_count = rc;
121 
122 	return -EIO;
123 }
124 
125 static void ef100_mcdi_reboot_detected(struct efx_nic *efx)
126 {
127 }
128 
129 /*	MCDI calls
130  */
131 static int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address)
132 {
133 	MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
134 	size_t outlen;
135 	int rc;
136 
137 	BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
138 
139 	rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
140 			  outbuf, sizeof(outbuf), &outlen);
141 	if (rc)
142 		return rc;
143 	if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
144 		return -EIO;
145 
146 	ether_addr_copy(mac_address,
147 			MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
148 	return 0;
149 }
150 
151 static int efx_ef100_init_datapath_caps(struct efx_nic *efx)
152 {
153 	MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN);
154 	struct ef100_nic_data *nic_data = efx->nic_data;
155 	u8 vi_window_mode;
156 	size_t outlen;
157 	int rc;
158 
159 	BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
160 
161 	rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
162 			  outbuf, sizeof(outbuf), &outlen);
163 	if (rc)
164 		return rc;
165 	if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
166 		netif_err(efx, drv, efx->net_dev,
167 			  "unable to read datapath firmware capabilities\n");
168 		return -EIO;
169 	}
170 
171 	nic_data->datapath_caps = MCDI_DWORD(outbuf,
172 					     GET_CAPABILITIES_OUT_FLAGS1);
173 	nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
174 					      GET_CAPABILITIES_V2_OUT_FLAGS2);
175 	if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN)
176 		nic_data->datapath_caps3 = 0;
177 	else
178 		nic_data->datapath_caps3 = MCDI_DWORD(outbuf,
179 						      GET_CAPABILITIES_V7_OUT_FLAGS3);
180 
181 	vi_window_mode = MCDI_BYTE(outbuf,
182 				   GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
183 	rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
184 	if (rc)
185 		return rc;
186 
187 	if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3)) {
188 		struct net_device *net_dev = efx->net_dev;
189 		netdev_features_t tso = NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_PARTIAL |
190 					NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
191 					NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM;
192 
193 		net_dev->features |= tso;
194 		net_dev->hw_features |= tso;
195 		net_dev->hw_enc_features |= tso;
196 		/* EF100 HW can only offload outer checksums if they are UDP,
197 		 * so for GRE_CSUM we have to use GSO_PARTIAL.
198 		 */
199 		net_dev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
200 	}
201 	efx->num_mac_stats = MCDI_WORD(outbuf,
202 				       GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
203 	netif_dbg(efx, probe, efx->net_dev,
204 		  "firmware reports num_mac_stats = %u\n",
205 		  efx->num_mac_stats);
206 	return 0;
207 }
208 
209 /*	Event handling
210  */
211 static int ef100_ev_probe(struct efx_channel *channel)
212 {
213 	/* Allocate an extra descriptor for the QMDA status completion entry */
214 	return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
215 				    (channel->eventq_mask + 2) *
216 				    sizeof(efx_qword_t),
217 				    GFP_KERNEL);
218 }
219 
220 static int ef100_ev_init(struct efx_channel *channel)
221 {
222 	struct ef100_nic_data *nic_data = channel->efx->nic_data;
223 
224 	/* initial phase is 0 */
225 	clear_bit(channel->channel, nic_data->evq_phases);
226 
227 	return efx_mcdi_ev_init(channel, false, false);
228 }
229 
230 static void ef100_ev_read_ack(struct efx_channel *channel)
231 {
232 	efx_dword_t evq_prime;
233 
234 	EFX_POPULATE_DWORD_2(evq_prime,
235 			     ERF_GZ_EVQ_ID, channel->channel,
236 			     ERF_GZ_IDX, channel->eventq_read_ptr &
237 					 channel->eventq_mask);
238 
239 	efx_writed(channel->efx, &evq_prime,
240 		   efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME));
241 }
242 
243 static int ef100_ev_process(struct efx_channel *channel, int quota)
244 {
245 	struct efx_nic *efx = channel->efx;
246 	struct ef100_nic_data *nic_data;
247 	bool evq_phase, old_evq_phase;
248 	unsigned int read_ptr;
249 	efx_qword_t *p_event;
250 	int spent = 0;
251 	bool ev_phase;
252 	int ev_type;
253 
254 	if (unlikely(!channel->enabled))
255 		return 0;
256 
257 	nic_data = efx->nic_data;
258 	evq_phase = test_bit(channel->channel, nic_data->evq_phases);
259 	old_evq_phase = evq_phase;
260 	read_ptr = channel->eventq_read_ptr;
261 	BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN);
262 
263 	while (spent < quota) {
264 		p_event = efx_event(channel, read_ptr);
265 
266 		ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE);
267 		if (ev_phase != evq_phase)
268 			break;
269 
270 		netif_vdbg(efx, drv, efx->net_dev,
271 			   "processing event on %d " EFX_QWORD_FMT "\n",
272 			   channel->channel, EFX_QWORD_VAL(*p_event));
273 
274 		ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE);
275 
276 		switch (ev_type) {
277 		case ESE_GZ_EF100_EV_RX_PKTS:
278 			efx_ef100_ev_rx(channel, p_event);
279 			++spent;
280 			break;
281 		case ESE_GZ_EF100_EV_MCDI:
282 			efx_mcdi_process_event(channel, p_event);
283 			break;
284 		case ESE_GZ_EF100_EV_TX_COMPLETION:
285 			ef100_ev_tx(channel, p_event);
286 			break;
287 		case ESE_GZ_EF100_EV_DRIVER:
288 			netif_info(efx, drv, efx->net_dev,
289 				   "Driver initiated event " EFX_QWORD_FMT "\n",
290 				   EFX_QWORD_VAL(*p_event));
291 			break;
292 		default:
293 			netif_info(efx, drv, efx->net_dev,
294 				   "Unhandled event " EFX_QWORD_FMT "\n",
295 				   EFX_QWORD_VAL(*p_event));
296 		}
297 
298 		++read_ptr;
299 		if ((read_ptr & channel->eventq_mask) == 0)
300 			evq_phase = !evq_phase;
301 	}
302 
303 	channel->eventq_read_ptr = read_ptr;
304 	if (evq_phase != old_evq_phase)
305 		change_bit(channel->channel, nic_data->evq_phases);
306 
307 	return spent;
308 }
309 
310 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id)
311 {
312 	struct efx_msi_context *context = dev_id;
313 	struct efx_nic *efx = context->efx;
314 
315 	netif_vdbg(efx, intr, efx->net_dev,
316 		   "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
317 
318 	if (likely(READ_ONCE(efx->irq_soft_enabled))) {
319 		/* Note test interrupts */
320 		if (context->index == efx->irq_level)
321 			efx->last_irq_cpu = raw_smp_processor_id();
322 
323 		/* Schedule processing of the channel */
324 		efx_schedule_channel_irq(efx->channel[context->index]);
325 	}
326 
327 	return IRQ_HANDLED;
328 }
329 
330 static int ef100_phy_probe(struct efx_nic *efx)
331 {
332 	struct efx_mcdi_phy_data *phy_data;
333 	int rc;
334 
335 	/* Probe for the PHY */
336 	efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL);
337 	if (!efx->phy_data)
338 		return -ENOMEM;
339 
340 	rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data);
341 	if (rc)
342 		return rc;
343 
344 	/* Populate driver and ethtool settings */
345 	phy_data = efx->phy_data;
346 	mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap,
347 				efx->link_advertising);
348 	efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap,
349 						   false);
350 
351 	/* Default to Autonegotiated flow control if the PHY supports it */
352 	efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
353 	if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
354 		efx->wanted_fc |= EFX_FC_AUTO;
355 	efx_link_set_wanted_fc(efx, efx->wanted_fc);
356 
357 	/* Push settings to the PHY. Failure is not fatal, the user can try to
358 	 * fix it using ethtool.
359 	 */
360 	rc = efx_mcdi_port_reconfigure(efx);
361 	if (rc && rc != -EPERM)
362 		netif_warn(efx, drv, efx->net_dev,
363 			   "could not initialise PHY settings\n");
364 
365 	return 0;
366 }
367 
368 static int ef100_filter_table_probe(struct efx_nic *efx)
369 {
370 	return efx_mcdi_filter_table_probe(efx, true);
371 }
372 
373 static int ef100_filter_table_up(struct efx_nic *efx)
374 {
375 	int rc;
376 
377 	rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
378 	if (rc) {
379 		efx_mcdi_filter_table_down(efx);
380 		return rc;
381 	}
382 
383 	rc = efx_mcdi_filter_add_vlan(efx, 0);
384 	if (rc) {
385 		efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
386 		efx_mcdi_filter_table_down(efx);
387 	}
388 
389 	return rc;
390 }
391 
392 static void ef100_filter_table_down(struct efx_nic *efx)
393 {
394 	efx_mcdi_filter_del_vlan(efx, 0);
395 	efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
396 	efx_mcdi_filter_table_down(efx);
397 }
398 
399 /*	Other
400  */
401 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only)
402 {
403 	WARN_ON(!mutex_is_locked(&efx->mac_lock));
404 
405 	efx_mcdi_filter_sync_rx_mode(efx);
406 
407 	if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
408 		return efx_mcdi_set_mtu(efx);
409 	return efx_mcdi_set_mac(efx);
410 }
411 
412 static enum reset_type ef100_map_reset_reason(enum reset_type reason)
413 {
414 	if (reason == RESET_TYPE_TX_WATCHDOG)
415 		return reason;
416 	return RESET_TYPE_DISABLE;
417 }
418 
419 static int ef100_map_reset_flags(u32 *flags)
420 {
421 	/* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */
422 	if ((*flags & EF100_RESET_PORT)) {
423 		*flags &= ~EF100_RESET_PORT;
424 		return RESET_TYPE_ALL;
425 	}
426 	if (*flags & ETH_RESET_MGMT) {
427 		*flags &= ~ETH_RESET_MGMT;
428 		return RESET_TYPE_DISABLE;
429 	}
430 
431 	return -EINVAL;
432 }
433 
434 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type)
435 {
436 	int rc;
437 
438 	dev_close(efx->net_dev);
439 
440 	if (reset_type == RESET_TYPE_TX_WATCHDOG) {
441 		netif_device_attach(efx->net_dev);
442 		__clear_bit(reset_type, &efx->reset_pending);
443 		rc = dev_open(efx->net_dev, NULL);
444 	} else if (reset_type == RESET_TYPE_ALL) {
445 		rc = efx_mcdi_reset(efx, reset_type);
446 		if (rc)
447 			return rc;
448 
449 		netif_device_attach(efx->net_dev);
450 
451 		rc = dev_open(efx->net_dev, NULL);
452 	} else {
453 		rc = 1;	/* Leave the device closed */
454 	}
455 	return rc;
456 }
457 
458 static void ef100_common_stat_mask(unsigned long *mask)
459 {
460 	__set_bit(EF100_STAT_port_rx_packets, mask);
461 	__set_bit(EF100_STAT_port_tx_packets, mask);
462 	__set_bit(EF100_STAT_port_rx_bytes, mask);
463 	__set_bit(EF100_STAT_port_tx_bytes, mask);
464 	__set_bit(EF100_STAT_port_rx_multicast, mask);
465 	__set_bit(EF100_STAT_port_rx_bad, mask);
466 	__set_bit(EF100_STAT_port_rx_align_error, mask);
467 	__set_bit(EF100_STAT_port_rx_overflow, mask);
468 }
469 
470 static void ef100_ethtool_stat_mask(unsigned long *mask)
471 {
472 	__set_bit(EF100_STAT_port_tx_pause, mask);
473 	__set_bit(EF100_STAT_port_tx_unicast, mask);
474 	__set_bit(EF100_STAT_port_tx_multicast, mask);
475 	__set_bit(EF100_STAT_port_tx_broadcast, mask);
476 	__set_bit(EF100_STAT_port_tx_lt64, mask);
477 	__set_bit(EF100_STAT_port_tx_64, mask);
478 	__set_bit(EF100_STAT_port_tx_65_to_127, mask);
479 	__set_bit(EF100_STAT_port_tx_128_to_255, mask);
480 	__set_bit(EF100_STAT_port_tx_256_to_511, mask);
481 	__set_bit(EF100_STAT_port_tx_512_to_1023, mask);
482 	__set_bit(EF100_STAT_port_tx_1024_to_15xx, mask);
483 	__set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask);
484 	__set_bit(EF100_STAT_port_rx_good, mask);
485 	__set_bit(EF100_STAT_port_rx_pause, mask);
486 	__set_bit(EF100_STAT_port_rx_unicast, mask);
487 	__set_bit(EF100_STAT_port_rx_broadcast, mask);
488 	__set_bit(EF100_STAT_port_rx_lt64, mask);
489 	__set_bit(EF100_STAT_port_rx_64, mask);
490 	__set_bit(EF100_STAT_port_rx_65_to_127, mask);
491 	__set_bit(EF100_STAT_port_rx_128_to_255, mask);
492 	__set_bit(EF100_STAT_port_rx_256_to_511, mask);
493 	__set_bit(EF100_STAT_port_rx_512_to_1023, mask);
494 	__set_bit(EF100_STAT_port_rx_1024_to_15xx, mask);
495 	__set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask);
496 	__set_bit(EF100_STAT_port_rx_gtjumbo, mask);
497 	__set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask);
498 	__set_bit(EF100_STAT_port_rx_length_error, mask);
499 	__set_bit(EF100_STAT_port_rx_nodesc_drops, mask);
500 	__set_bit(GENERIC_STAT_rx_nodesc_trunc, mask);
501 	__set_bit(GENERIC_STAT_rx_noskb_drops, mask);
502 }
503 
504 #define EF100_DMA_STAT(ext_name, mcdi_name)			\
505 	[EF100_STAT_ ## ext_name] =				\
506 	{ #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
507 
508 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = {
509 	EF100_DMA_STAT(port_tx_bytes, TX_BYTES),
510 	EF100_DMA_STAT(port_tx_packets, TX_PKTS),
511 	EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
512 	EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
513 	EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
514 	EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
515 	EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
516 	EF100_DMA_STAT(port_tx_64, TX_64_PKTS),
517 	EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
518 	EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
519 	EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
520 	EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
521 	EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
522 	EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
523 	EF100_DMA_STAT(port_rx_bytes, RX_BYTES),
524 	EF100_DMA_STAT(port_rx_packets, RX_PKTS),
525 	EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
526 	EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
527 	EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
528 	EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
529 	EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
530 	EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
531 	EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
532 	EF100_DMA_STAT(port_rx_64, RX_64_PKTS),
533 	EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
534 	EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
535 	EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
536 	EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
537 	EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
538 	EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
539 	EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
540 	EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
541 	EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
542 	EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
543 	EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
544 	EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
545 	EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
546 	EFX_GENERIC_SW_STAT(rx_noskb_drops),
547 };
548 
549 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names)
550 {
551 	DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
552 
553 	ef100_ethtool_stat_mask(mask);
554 	return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT,
555 				      mask, names);
556 }
557 
558 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats,
559 					struct rtnl_link_stats64 *core_stats)
560 {
561 	struct ef100_nic_data *nic_data = efx->nic_data;
562 	DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
563 	size_t stats_count = 0, index;
564 	u64 *stats = nic_data->stats;
565 
566 	ef100_ethtool_stat_mask(mask);
567 
568 	if (full_stats) {
569 		for_each_set_bit(index, mask, EF100_STAT_COUNT) {
570 			if (ef100_stat_desc[index].name) {
571 				*full_stats++ = stats[index];
572 				++stats_count;
573 			}
574 		}
575 	}
576 
577 	if (!core_stats)
578 		return stats_count;
579 
580 	core_stats->rx_packets = stats[EF100_STAT_port_rx_packets];
581 	core_stats->tx_packets = stats[EF100_STAT_port_tx_packets];
582 	core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes];
583 	core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes];
584 	core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] +
585 				 stats[GENERIC_STAT_rx_nodesc_trunc] +
586 				 stats[GENERIC_STAT_rx_noskb_drops];
587 	core_stats->multicast = stats[EF100_STAT_port_rx_multicast];
588 	core_stats->rx_length_errors =
589 			stats[EF100_STAT_port_rx_gtjumbo] +
590 			stats[EF100_STAT_port_rx_length_error];
591 	core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad];
592 	core_stats->rx_frame_errors =
593 			stats[EF100_STAT_port_rx_align_error];
594 	core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow];
595 	core_stats->rx_errors = (core_stats->rx_length_errors +
596 				 core_stats->rx_crc_errors +
597 				 core_stats->rx_frame_errors);
598 
599 	return stats_count;
600 }
601 
602 static size_t ef100_update_stats(struct efx_nic *efx,
603 				 u64 *full_stats,
604 				 struct rtnl_link_stats64 *core_stats)
605 {
606 	__le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC);
607 	struct ef100_nic_data *nic_data = efx->nic_data;
608 	DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
609 	u64 *stats = nic_data->stats;
610 
611 	ef100_common_stat_mask(mask);
612 	ef100_ethtool_stat_mask(mask);
613 
614 	if (!mc_stats)
615 		return 0;
616 
617 	efx_nic_copy_stats(efx, mc_stats);
618 	efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask,
619 			     stats, mc_stats, false);
620 
621 	kfree(mc_stats);
622 
623 	return ef100_update_stats_common(efx, full_stats, core_stats);
624 }
625 
626 static int efx_ef100_get_phys_port_id(struct efx_nic *efx,
627 				      struct netdev_phys_item_id *ppid)
628 {
629 	struct ef100_nic_data *nic_data = efx->nic_data;
630 
631 	if (!is_valid_ether_addr(nic_data->port_id))
632 		return -EOPNOTSUPP;
633 
634 	ppid->id_len = ETH_ALEN;
635 	memcpy(ppid->id, nic_data->port_id, ppid->id_len);
636 
637 	return 0;
638 }
639 
640 static int efx_ef100_irq_test_generate(struct efx_nic *efx)
641 {
642 	MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
643 
644 	BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
645 
646 	MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
647 	return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT,
648 				  inbuf, sizeof(inbuf), NULL, 0, NULL);
649 }
650 
651 #define EFX_EF100_TEST 1
652 
653 static void efx_ef100_ev_test_generate(struct efx_channel *channel)
654 {
655 	MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
656 	struct efx_nic *efx = channel->efx;
657 	efx_qword_t event;
658 	int rc;
659 
660 	EFX_POPULATE_QWORD_2(event,
661 			     ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER,
662 			     ESF_GZ_DRIVER_DATA, EFX_EF100_TEST);
663 
664 	MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
665 
666 	/* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
667 	 * already swapped the data to little-endian order.
668 	 */
669 	memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
670 	       sizeof(efx_qword_t));
671 
672 	rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
673 			  NULL, 0, NULL);
674 	if (rc && (rc != -ENETDOWN))
675 		goto fail;
676 
677 	return;
678 
679 fail:
680 	WARN_ON(true);
681 	netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
682 }
683 
684 static unsigned int ef100_check_caps(const struct efx_nic *efx,
685 				     u8 flag, u32 offset)
686 {
687 	const struct ef100_nic_data *nic_data = efx->nic_data;
688 
689 	switch (offset) {
690 	case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST:
691 		return nic_data->datapath_caps & BIT_ULL(flag);
692 	case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST:
693 		return nic_data->datapath_caps2 & BIT_ULL(flag);
694 	case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST:
695 		return nic_data->datapath_caps3 & BIT_ULL(flag);
696 	default:
697 		return 0;
698 	}
699 }
700 
701 static unsigned int efx_ef100_recycle_ring_size(const struct efx_nic *efx)
702 {
703 	/* Maximum link speed for Riverhead is 100G */
704 	return 10 * EFX_RECYCLE_RING_SIZE_10G;
705 }
706 
707 /*	NIC level access functions
708  */
709 #define EF100_OFFLOAD_FEATURES	(NETIF_F_HW_CSUM | NETIF_F_RXCSUM |	\
710 	NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \
711 	NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \
712 	NETIF_F_HW_VLAN_CTAG_TX)
713 
714 const struct efx_nic_type ef100_pf_nic_type = {
715 	.revision = EFX_REV_EF100,
716 	.is_vf = false,
717 	.probe = ef100_probe_pf,
718 	.offload_features = EF100_OFFLOAD_FEATURES,
719 	.mcdi_max_ver = 2,
720 	.mcdi_request = ef100_mcdi_request,
721 	.mcdi_poll_response = ef100_mcdi_poll_response,
722 	.mcdi_read_response = ef100_mcdi_read_response,
723 	.mcdi_poll_reboot = ef100_mcdi_poll_reboot,
724 	.mcdi_reboot_detected = ef100_mcdi_reboot_detected,
725 	.irq_enable_master = efx_port_dummy_op_void,
726 	.irq_test_generate = efx_ef100_irq_test_generate,
727 	.irq_disable_non_ev = efx_port_dummy_op_void,
728 	.push_irq_moderation = efx_channel_dummy_op_void,
729 	.min_interrupt_mode = EFX_INT_MODE_MSIX,
730 	.map_reset_reason = ef100_map_reset_reason,
731 	.map_reset_flags = ef100_map_reset_flags,
732 	.reset = ef100_reset,
733 
734 	.check_caps = ef100_check_caps,
735 
736 	.ev_probe = ef100_ev_probe,
737 	.ev_init = ef100_ev_init,
738 	.ev_fini = efx_mcdi_ev_fini,
739 	.ev_remove = efx_mcdi_ev_remove,
740 	.irq_handle_msi = ef100_msi_interrupt,
741 	.ev_process = ef100_ev_process,
742 	.ev_read_ack = ef100_ev_read_ack,
743 	.ev_test_generate = efx_ef100_ev_test_generate,
744 	.tx_probe = ef100_tx_probe,
745 	.tx_init = ef100_tx_init,
746 	.tx_write = ef100_tx_write,
747 	.tx_enqueue = ef100_enqueue_skb,
748 	.rx_probe = efx_mcdi_rx_probe,
749 	.rx_init = efx_mcdi_rx_init,
750 	.rx_remove = efx_mcdi_rx_remove,
751 	.rx_write = ef100_rx_write,
752 	.rx_packet = __ef100_rx_packet,
753 	.rx_buf_hash_valid = ef100_rx_buf_hash_valid,
754 	.fini_dmaq = efx_fini_dmaq,
755 	.max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
756 	.filter_table_probe = ef100_filter_table_up,
757 	.filter_table_restore = efx_mcdi_filter_table_restore,
758 	.filter_table_remove = ef100_filter_table_down,
759 	.filter_insert = efx_mcdi_filter_insert,
760 	.filter_remove_safe = efx_mcdi_filter_remove_safe,
761 	.filter_get_safe = efx_mcdi_filter_get_safe,
762 	.filter_clear_rx = efx_mcdi_filter_clear_rx,
763 	.filter_count_rx_used = efx_mcdi_filter_count_rx_used,
764 	.filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
765 	.filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
766 #ifdef CONFIG_RFS_ACCEL
767 	.filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
768 #endif
769 
770 	.get_phys_port_id = efx_ef100_get_phys_port_id,
771 
772 	.rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
773 	.rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
774 	.rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
775 	.rx_hash_key_size = 40,
776 	.rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
777 	.rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
778 	.rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
779 	.rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
780 	.rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
781 	.rx_recycle_ring_size = efx_ef100_recycle_ring_size,
782 
783 	.reconfigure_mac = ef100_reconfigure_mac,
784 	.reconfigure_port = efx_mcdi_port_reconfigure,
785 	.test_nvram = efx_new_mcdi_nvram_test_all,
786 	.describe_stats = ef100_describe_stats,
787 	.start_stats = efx_mcdi_mac_start_stats,
788 	.update_stats = ef100_update_stats,
789 	.pull_stats = efx_mcdi_mac_pull_stats,
790 	.stop_stats = efx_mcdi_mac_stop_stats,
791 #ifdef CONFIG_SFC_SRIOV
792 	.sriov_configure = efx_ef100_sriov_configure,
793 #endif
794 
795 	/* Per-type bar/size configuration not used on ef100. Location of
796 	 * registers is defined by extended capabilities.
797 	 */
798 	.mem_bar = NULL,
799 	.mem_map_size = NULL,
800 
801 };
802 
803 const struct efx_nic_type ef100_vf_nic_type = {
804 	.revision = EFX_REV_EF100,
805 	.is_vf = true,
806 	.probe = ef100_probe_vf,
807 	.offload_features = EF100_OFFLOAD_FEATURES,
808 	.mcdi_max_ver = 2,
809 	.mcdi_request = ef100_mcdi_request,
810 	.mcdi_poll_response = ef100_mcdi_poll_response,
811 	.mcdi_read_response = ef100_mcdi_read_response,
812 	.mcdi_poll_reboot = ef100_mcdi_poll_reboot,
813 	.mcdi_reboot_detected = ef100_mcdi_reboot_detected,
814 	.irq_enable_master = efx_port_dummy_op_void,
815 	.irq_test_generate = efx_ef100_irq_test_generate,
816 	.irq_disable_non_ev = efx_port_dummy_op_void,
817 	.push_irq_moderation = efx_channel_dummy_op_void,
818 	.min_interrupt_mode = EFX_INT_MODE_MSIX,
819 	.map_reset_reason = ef100_map_reset_reason,
820 	.map_reset_flags = ef100_map_reset_flags,
821 	.reset = ef100_reset,
822 	.check_caps = ef100_check_caps,
823 	.ev_probe = ef100_ev_probe,
824 	.ev_init = ef100_ev_init,
825 	.ev_fini = efx_mcdi_ev_fini,
826 	.ev_remove = efx_mcdi_ev_remove,
827 	.irq_handle_msi = ef100_msi_interrupt,
828 	.ev_process = ef100_ev_process,
829 	.ev_read_ack = ef100_ev_read_ack,
830 	.ev_test_generate = efx_ef100_ev_test_generate,
831 	.tx_probe = ef100_tx_probe,
832 	.tx_init = ef100_tx_init,
833 	.tx_write = ef100_tx_write,
834 	.tx_enqueue = ef100_enqueue_skb,
835 	.rx_probe = efx_mcdi_rx_probe,
836 	.rx_init = efx_mcdi_rx_init,
837 	.rx_remove = efx_mcdi_rx_remove,
838 	.rx_write = ef100_rx_write,
839 	.rx_packet = __ef100_rx_packet,
840 	.rx_buf_hash_valid = ef100_rx_buf_hash_valid,
841 	.fini_dmaq = efx_fini_dmaq,
842 	.max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
843 	.filter_table_probe = ef100_filter_table_up,
844 	.filter_table_restore = efx_mcdi_filter_table_restore,
845 	.filter_table_remove = ef100_filter_table_down,
846 	.filter_insert = efx_mcdi_filter_insert,
847 	.filter_remove_safe = efx_mcdi_filter_remove_safe,
848 	.filter_get_safe = efx_mcdi_filter_get_safe,
849 	.filter_clear_rx = efx_mcdi_filter_clear_rx,
850 	.filter_count_rx_used = efx_mcdi_filter_count_rx_used,
851 	.filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
852 	.filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
853 #ifdef CONFIG_RFS_ACCEL
854 	.filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
855 #endif
856 
857 	.rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
858 	.rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
859 	.rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
860 	.rx_hash_key_size = 40,
861 	.rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
862 	.rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
863 	.rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
864 	.rx_recycle_ring_size = efx_ef100_recycle_ring_size,
865 
866 	.reconfigure_mac = ef100_reconfigure_mac,
867 	.test_nvram = efx_new_mcdi_nvram_test_all,
868 	.describe_stats = ef100_describe_stats,
869 	.start_stats = efx_mcdi_mac_start_stats,
870 	.update_stats = ef100_update_stats,
871 	.pull_stats = efx_mcdi_mac_pull_stats,
872 	.stop_stats = efx_mcdi_mac_stop_stats,
873 
874 	.mem_bar = NULL,
875 	.mem_map_size = NULL,
876 
877 };
878 
879 static int compare_versions(const char *a, const char *b)
880 {
881 	int a_major, a_minor, a_point, a_patch;
882 	int b_major, b_minor, b_point, b_patch;
883 	int a_matched, b_matched;
884 
885 	a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch);
886 	b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch);
887 
888 	if (a_matched == 4 && b_matched != 4)
889 		return +1;
890 
891 	if (a_matched != 4 && b_matched == 4)
892 		return -1;
893 
894 	if (a_matched != 4 && b_matched != 4)
895 		return 0;
896 
897 	if (a_major != b_major)
898 		return a_major - b_major;
899 
900 	if (a_minor != b_minor)
901 		return a_minor - b_minor;
902 
903 	if (a_point != b_point)
904 		return a_point - b_point;
905 
906 	return a_patch - b_patch;
907 }
908 
909 enum ef100_tlv_state_machine {
910 	EF100_TLV_TYPE,
911 	EF100_TLV_TYPE_CONT,
912 	EF100_TLV_LENGTH,
913 	EF100_TLV_VALUE
914 };
915 
916 struct ef100_tlv_state {
917 	enum ef100_tlv_state_machine state;
918 	u64 value;
919 	u32 value_offset;
920 	u16 type;
921 	u8 len;
922 };
923 
924 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte)
925 {
926 	switch (state->state) {
927 	case EF100_TLV_TYPE:
928 		state->type = byte & 0x7f;
929 		state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT
930 					     : EF100_TLV_LENGTH;
931 		/* Clear ready to read in a new entry */
932 		state->value = 0;
933 		state->value_offset = 0;
934 		return 0;
935 	case EF100_TLV_TYPE_CONT:
936 		state->type |= byte << 7;
937 		state->state = EF100_TLV_LENGTH;
938 		return 0;
939 	case EF100_TLV_LENGTH:
940 		state->len = byte;
941 		/* We only handle TLVs that fit in a u64 */
942 		if (state->len > sizeof(state->value))
943 			return -EOPNOTSUPP;
944 		/* len may be zero, implying a value of zero */
945 		state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE;
946 		return 0;
947 	case EF100_TLV_VALUE:
948 		state->value |= ((u64)byte) << (state->value_offset * 8);
949 		state->value_offset++;
950 		if (state->value_offset >= state->len)
951 			state->state = EF100_TLV_TYPE;
952 		return 0;
953 	default: /* state machine error, can't happen */
954 		WARN_ON_ONCE(1);
955 		return -EIO;
956 	}
957 }
958 
959 static int ef100_process_design_param(struct efx_nic *efx,
960 				      const struct ef100_tlv_state *reader)
961 {
962 	struct ef100_nic_data *nic_data = efx->nic_data;
963 
964 	switch (reader->type) {
965 	case ESE_EF100_DP_GZ_PAD: /* padding, skip it */
966 		return 0;
967 	case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS:
968 		/* Driver doesn't support timestamping yet, so we don't care */
969 		return 0;
970 	case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS:
971 		/* Driver doesn't support unsolicited-event credits yet, so
972 		 * we don't care
973 		 */
974 		return 0;
975 	case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE:
976 		/* Driver doesn't manage the NMMU (so we don't care) */
977 		return 0;
978 	case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS:
979 		/* Driver uses CHECKSUM_COMPLETE, so we don't care about
980 		 * protocol checksum validation
981 		 */
982 		return 0;
983 	case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN:
984 		nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff);
985 		return 0;
986 	case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS:
987 		/* We always put HDR_NUM_SEGS=1 in our TSO descriptors */
988 		if (!reader->value) {
989 			netif_err(efx, probe, efx->net_dev,
990 				  "TSO_MAX_HDR_NUM_SEGS < 1\n");
991 			return -EOPNOTSUPP;
992 		}
993 		return 0;
994 	case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY:
995 	case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY:
996 		/* Our TXQ and RXQ sizes are always power-of-two and thus divisible by
997 		 * EFX_MIN_DMAQ_SIZE, so we just need to check that
998 		 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY.
999 		 * This is very unlikely to fail.
1000 		 */
1001 		if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE ||
1002 		    EFX_MIN_DMAQ_SIZE % (u32)reader->value) {
1003 			netif_err(efx, probe, efx->net_dev,
1004 				  "%s size granularity is %llu, can't guarantee safety\n",
1005 				  reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ",
1006 				  reader->value);
1007 			return -EOPNOTSUPP;
1008 		}
1009 		return 0;
1010 	case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN:
1011 		nic_data->tso_max_payload_len = min_t(u64, reader->value,
1012 						      GSO_LEGACY_MAX_SIZE);
1013 		netif_set_tso_max_size(efx->net_dev,
1014 				       nic_data->tso_max_payload_len);
1015 		return 0;
1016 	case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS:
1017 		nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff);
1018 		netif_set_tso_max_segs(efx->net_dev,
1019 				       nic_data->tso_max_payload_num_segs);
1020 		return 0;
1021 	case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES:
1022 		nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff);
1023 		return 0;
1024 	case ESE_EF100_DP_GZ_COMPAT:
1025 		if (reader->value) {
1026 			netif_err(efx, probe, efx->net_dev,
1027 				  "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n",
1028 				  reader->value);
1029 			return -EOPNOTSUPP;
1030 		}
1031 		return 0;
1032 	case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN:
1033 		/* Driver doesn't use mem2mem transfers */
1034 		return 0;
1035 	case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS:
1036 		/* Driver doesn't currently use EVQ_TIMER */
1037 		return 0;
1038 	case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES:
1039 		/* Driver doesn't manage the NMMU (so we don't care) */
1040 		return 0;
1041 	case ESE_EF100_DP_GZ_VI_STRIDES:
1042 		/* We never try to set the VI stride, and we don't rely on
1043 		 * being able to find VIs past VI 0 until after we've learned
1044 		 * the current stride from MC_CMD_GET_CAPABILITIES.
1045 		 * So the value of this shouldn't matter.
1046 		 */
1047 		if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT)
1048 			netif_dbg(efx, probe, efx->net_dev,
1049 				  "NIC has other than default VI_STRIDES (mask "
1050 				  "%#llx), early probing might use wrong one\n",
1051 				  reader->value);
1052 		return 0;
1053 	case ESE_EF100_DP_GZ_RX_MAX_RUNT:
1054 		/* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't
1055 		 * care whether it indicates runt or overlength for any given
1056 		 * packet, so we don't care about this parameter.
1057 		 */
1058 		return 0;
1059 	default:
1060 		/* Host interface says "Drivers should ignore design parameters
1061 		 * that they do not recognise."
1062 		 */
1063 		netif_dbg(efx, probe, efx->net_dev,
1064 			  "Ignoring unrecognised design parameter %u\n",
1065 			  reader->type);
1066 		return 0;
1067 	}
1068 }
1069 
1070 static int ef100_check_design_params(struct efx_nic *efx)
1071 {
1072 	struct ef100_tlv_state reader = {};
1073 	u32 total_len, offset = 0;
1074 	efx_dword_t reg;
1075 	int rc = 0, i;
1076 	u32 data;
1077 
1078 	efx_readd(efx, &reg, ER_GZ_PARAMS_TLV_LEN);
1079 	total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
1080 	netif_dbg(efx, probe, efx->net_dev, "%u bytes of design parameters\n",
1081 		  total_len);
1082 	while (offset < total_len) {
1083 		efx_readd(efx, &reg, ER_GZ_PARAMS_TLV + offset);
1084 		data = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
1085 		for (i = 0; i < sizeof(data); i++) {
1086 			rc = ef100_tlv_feed(&reader, data);
1087 			/* Got a complete value? */
1088 			if (!rc && reader.state == EF100_TLV_TYPE)
1089 				rc = ef100_process_design_param(efx, &reader);
1090 			if (rc)
1091 				goto out;
1092 			data >>= 8;
1093 			offset++;
1094 		}
1095 	}
1096 	/* Check we didn't end halfway through a TLV entry, which could either
1097 	 * mean that the TLV stream is truncated or just that it's corrupted
1098 	 * and our state machine is out of sync.
1099 	 */
1100 	if (reader.state != EF100_TLV_TYPE) {
1101 		if (reader.state == EF100_TLV_TYPE_CONT)
1102 			netif_err(efx, probe, efx->net_dev,
1103 				  "truncated design parameter (incomplete type %u)\n",
1104 				  reader.type);
1105 		else
1106 			netif_err(efx, probe, efx->net_dev,
1107 				  "truncated design parameter %u\n",
1108 				  reader.type);
1109 		rc = -EIO;
1110 	}
1111 out:
1112 	return rc;
1113 }
1114 
1115 /*	NIC probe and remove
1116  */
1117 static int ef100_probe_main(struct efx_nic *efx)
1118 {
1119 	unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]);
1120 	struct net_device *net_dev = efx->net_dev;
1121 	struct ef100_nic_data *nic_data;
1122 	char fw_version[32];
1123 	int i, rc;
1124 
1125 	if (WARN_ON(bar_size == 0))
1126 		return -EIO;
1127 
1128 	nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1129 	if (!nic_data)
1130 		return -ENOMEM;
1131 	efx->nic_data = nic_data;
1132 	nic_data->efx = efx;
1133 	net_dev->features |= efx->type->offload_features;
1134 	net_dev->hw_features |= efx->type->offload_features;
1135 	net_dev->hw_enc_features |= efx->type->offload_features;
1136 	net_dev->vlan_features |= NETIF_F_HW_CSUM | NETIF_F_SG |
1137 				  NETIF_F_HIGHDMA | NETIF_F_ALL_TSO;
1138 
1139 	/* Populate design-parameter defaults */
1140 	nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
1141 	nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
1142 	nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
1143 	nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
1144 	netif_set_tso_max_segs(net_dev,
1145 			       ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT);
1146 	/* Read design parameters */
1147 	rc = ef100_check_design_params(efx);
1148 	if (rc) {
1149 		netif_err(efx, probe, efx->net_dev,
1150 			  "Unsupported design parameters\n");
1151 		goto fail;
1152 	}
1153 
1154 	/* we assume later that we can copy from this buffer in dwords */
1155 	BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
1156 
1157 	/* MCDI buffers must be 256 byte aligned. */
1158 	rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN,
1159 				  GFP_KERNEL);
1160 	if (rc)
1161 		goto fail;
1162 
1163 	/* Get the MC's warm boot count.  In case it's rebooting right
1164 	 * now, be prepared to retry.
1165 	 */
1166 	i = 0;
1167 	for (;;) {
1168 		rc = ef100_get_warm_boot_count(efx);
1169 		if (rc >= 0)
1170 			break;
1171 		if (++i == 5)
1172 			goto fail;
1173 		ssleep(1);
1174 	}
1175 	nic_data->warm_boot_count = rc;
1176 
1177 	/* In case we're recovering from a crash (kexec), we want to
1178 	 * cancel any outstanding request by the previous user of this
1179 	 * function.  We send a special message using the least
1180 	 * significant bits of the 'high' (doorbell) register.
1181 	 */
1182 	_efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD));
1183 
1184 	/* Post-IO section. */
1185 
1186 	rc = efx_mcdi_init(efx);
1187 	if (!rc && efx->mcdi->fn_flags &
1188 		   (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT)) {
1189 		netif_info(efx, probe, efx->net_dev,
1190 			   "No network port on this PCI function");
1191 		rc = -ENODEV;
1192 	}
1193 	if (rc)
1194 		goto fail;
1195 	/* Reset (most) configuration for this function */
1196 	rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
1197 	if (rc)
1198 		goto fail;
1199 	/* Enable event logging */
1200 	rc = efx_mcdi_log_ctrl(efx, true, false, 0);
1201 	if (rc)
1202 		goto fail;
1203 
1204 	rc = efx_get_pf_index(efx, &nic_data->pf_index);
1205 	if (rc)
1206 		goto fail;
1207 
1208 	rc = efx_ef100_init_datapath_caps(efx);
1209 	if (rc < 0)
1210 		goto fail;
1211 
1212 	efx->max_vis = EF100_MAX_VIS;
1213 
1214 	rc = efx_mcdi_port_get_number(efx);
1215 	if (rc < 0)
1216 		goto fail;
1217 	efx->port_num = rc;
1218 
1219 	efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version));
1220 	netif_dbg(efx, drv, efx->net_dev, "Firmware version %s\n", fw_version);
1221 
1222 	if (compare_versions(fw_version, "1.1.0.1000") < 0) {
1223 		netif_info(efx, drv, efx->net_dev, "Firmware uses old event descriptors\n");
1224 		rc = -EINVAL;
1225 		goto fail;
1226 	}
1227 
1228 	if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) {
1229 		netif_info(efx, drv, efx->net_dev, "Firmware uses unsolicited-event credits\n");
1230 		rc = -EINVAL;
1231 		goto fail;
1232 	}
1233 
1234 	rc = ef100_phy_probe(efx);
1235 	if (rc)
1236 		goto fail;
1237 
1238 	down_write(&efx->filter_sem);
1239 	rc = ef100_filter_table_probe(efx);
1240 	up_write(&efx->filter_sem);
1241 	if (rc)
1242 		goto fail;
1243 
1244 	netdev_rss_key_fill(efx->rss_context.rx_hash_key,
1245 			    sizeof(efx->rss_context.rx_hash_key));
1246 
1247 	/* Don't fail init if RSS setup doesn't work. */
1248 	efx_mcdi_push_default_indir_table(efx, efx->n_rx_channels);
1249 
1250 	rc = ef100_register_netdev(efx);
1251 	if (rc)
1252 		goto fail;
1253 
1254 	return 0;
1255 fail:
1256 	return rc;
1257 }
1258 
1259 int ef100_probe_pf(struct efx_nic *efx)
1260 {
1261 	struct net_device *net_dev = efx->net_dev;
1262 	struct ef100_nic_data *nic_data;
1263 	int rc = ef100_probe_main(efx);
1264 
1265 	if (rc)
1266 		goto fail;
1267 
1268 	nic_data = efx->nic_data;
1269 	rc = ef100_get_mac_address(efx, net_dev->perm_addr);
1270 	if (rc)
1271 		goto fail;
1272 	/* Assign MAC address */
1273 	eth_hw_addr_set(net_dev, net_dev->perm_addr);
1274 	memcpy(nic_data->port_id, net_dev->perm_addr, ETH_ALEN);
1275 
1276 	return 0;
1277 
1278 fail:
1279 	return rc;
1280 }
1281 
1282 int ef100_probe_vf(struct efx_nic *efx)
1283 {
1284 	return ef100_probe_main(efx);
1285 }
1286 
1287 void ef100_remove(struct efx_nic *efx)
1288 {
1289 	struct ef100_nic_data *nic_data = efx->nic_data;
1290 
1291 	ef100_unregister_netdev(efx);
1292 
1293 	down_write(&efx->filter_sem);
1294 	efx_mcdi_filter_table_remove(efx);
1295 	up_write(&efx->filter_sem);
1296 	efx_fini_channels(efx);
1297 	kfree(efx->phy_data);
1298 	efx->phy_data = NULL;
1299 	efx_mcdi_detach(efx);
1300 	efx_mcdi_fini(efx);
1301 	if (nic_data)
1302 		efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1303 	kfree(nic_data);
1304 	efx->nic_data = NULL;
1305 }
1306