1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3  * Driver for Solarflare network controllers and boards
4  * Copyright 2018 Solarflare Communications Inc.
5  * Copyright 2019-2022 Xilinx Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published
9  * by the Free Software Foundation, incorporated herein by reference.
10  */
11 
12 #include "ef100_nic.h"
13 #include "efx_common.h"
14 #include "efx_channels.h"
15 #include "io.h"
16 #include "selftest.h"
17 #include "ef100_regs.h"
18 #include "mcdi.h"
19 #include "mcdi_pcol.h"
20 #include "mcdi_port_common.h"
21 #include "mcdi_functions.h"
22 #include "mcdi_filters.h"
23 #include "ef100_rx.h"
24 #include "ef100_tx.h"
25 #include "ef100_sriov.h"
26 #include "ef100_netdev.h"
27 #include "tc.h"
28 #include "mae.h"
29 #include "rx_common.h"
30 
31 #define EF100_MAX_VIS 4096
32 #define EF100_NUM_MCDI_BUFFERS	1
33 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
34 
35 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT)
36 
37 /*	MCDI
38  */
39 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr)
40 {
41 	struct ef100_nic_data *nic_data = efx->nic_data;
42 
43 	if (dma_addr)
44 		*dma_addr = nic_data->mcdi_buf.dma_addr +
45 			    bufid * ALIGN(MCDI_BUF_LEN, 256);
46 	return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256);
47 }
48 
49 static int ef100_get_warm_boot_count(struct efx_nic *efx)
50 {
51 	efx_dword_t reg;
52 
53 	efx_readd(efx, &reg, efx_reg(efx, ER_GZ_MC_SFT_STATUS));
54 
55 	if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) {
56 		netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n");
57 		efx->state = STATE_DISABLED;
58 		return -ENETDOWN;
59 	} else {
60 		return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
61 			EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
62 	}
63 }
64 
65 static void ef100_mcdi_request(struct efx_nic *efx,
66 			       const efx_dword_t *hdr, size_t hdr_len,
67 			       const efx_dword_t *sdu, size_t sdu_len)
68 {
69 	dma_addr_t dma_addr;
70 	u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr);
71 
72 	memcpy(pdu, hdr, hdr_len);
73 	memcpy(pdu + hdr_len, sdu, sdu_len);
74 	wmb();
75 
76 	/* The hardware provides 'low' and 'high' (doorbell) registers
77 	 * for passing the 64-bit address of an MCDI request to
78 	 * firmware.  However the dwords are swapped by firmware.  The
79 	 * least significant bits of the doorbell are then 0 for all
80 	 * MCDI requests due to alignment.
81 	 */
82 	_efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32),  efx_reg(efx, ER_GZ_MC_DB_LWRD));
83 	_efx_writed(efx, cpu_to_le32((u32)dma_addr),  efx_reg(efx, ER_GZ_MC_DB_HWRD));
84 }
85 
86 static bool ef100_mcdi_poll_response(struct efx_nic *efx)
87 {
88 	const efx_dword_t hdr =
89 		*(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL));
90 
91 	rmb();
92 	return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
93 }
94 
95 static void ef100_mcdi_read_response(struct efx_nic *efx,
96 				     efx_dword_t *outbuf, size_t offset,
97 				     size_t outlen)
98 {
99 	const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL);
100 
101 	memcpy(outbuf, pdu + offset, outlen);
102 }
103 
104 static int ef100_mcdi_poll_reboot(struct efx_nic *efx)
105 {
106 	struct ef100_nic_data *nic_data = efx->nic_data;
107 	int rc;
108 
109 	rc = ef100_get_warm_boot_count(efx);
110 	if (rc < 0) {
111 		/* The firmware is presumably in the process of
112 		 * rebooting.  However, we are supposed to report each
113 		 * reboot just once, so we must only do that once we
114 		 * can read and store the updated warm boot count.
115 		 */
116 		return 0;
117 	}
118 
119 	if (rc == nic_data->warm_boot_count)
120 		return 0;
121 
122 	nic_data->warm_boot_count = rc;
123 
124 	return -EIO;
125 }
126 
127 static void ef100_mcdi_reboot_detected(struct efx_nic *efx)
128 {
129 }
130 
131 /*	MCDI calls
132  */
133 int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address,
134 			  int client_handle, bool empty_ok)
135 {
136 	MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(1));
137 	MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN);
138 	size_t outlen;
139 	int rc;
140 
141 	BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
142 	MCDI_SET_DWORD(inbuf, GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE,
143 		       client_handle);
144 
145 	rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLIENT_MAC_ADDRESSES, inbuf,
146 			  sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
147 	if (rc)
148 		return rc;
149 
150 	if (outlen >= MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(1)) {
151 		ether_addr_copy(mac_address,
152 				MCDI_PTR(outbuf, GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS));
153 	} else if (empty_ok) {
154 		pci_warn(efx->pci_dev,
155 			 "No MAC address provisioned for client ID %#x.\n",
156 			 client_handle);
157 		eth_zero_addr(mac_address);
158 	} else {
159 		return -ENOENT;
160 	}
161 	return 0;
162 }
163 
164 int efx_ef100_init_datapath_caps(struct efx_nic *efx)
165 {
166 	MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN);
167 	struct ef100_nic_data *nic_data = efx->nic_data;
168 	u8 vi_window_mode;
169 	size_t outlen;
170 	int rc;
171 
172 	BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
173 
174 	rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
175 			  outbuf, sizeof(outbuf), &outlen);
176 	if (rc)
177 		return rc;
178 	if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
179 		netif_err(efx, drv, efx->net_dev,
180 			  "unable to read datapath firmware capabilities\n");
181 		return -EIO;
182 	}
183 
184 	nic_data->datapath_caps = MCDI_DWORD(outbuf,
185 					     GET_CAPABILITIES_OUT_FLAGS1);
186 	nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
187 					      GET_CAPABILITIES_V2_OUT_FLAGS2);
188 	if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN)
189 		nic_data->datapath_caps3 = 0;
190 	else
191 		nic_data->datapath_caps3 = MCDI_DWORD(outbuf,
192 						      GET_CAPABILITIES_V7_OUT_FLAGS3);
193 
194 	vi_window_mode = MCDI_BYTE(outbuf,
195 				   GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
196 	rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
197 	if (rc)
198 		return rc;
199 
200 	if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3)) {
201 		struct net_device *net_dev = efx->net_dev;
202 		netdev_features_t tso = NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_PARTIAL |
203 					NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
204 					NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM;
205 
206 		net_dev->features |= tso;
207 		net_dev->hw_features |= tso;
208 		net_dev->hw_enc_features |= tso;
209 		/* EF100 HW can only offload outer checksums if they are UDP,
210 		 * so for GRE_CSUM we have to use GSO_PARTIAL.
211 		 */
212 		net_dev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
213 	}
214 	efx->num_mac_stats = MCDI_WORD(outbuf,
215 				       GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
216 	netif_dbg(efx, probe, efx->net_dev,
217 		  "firmware reports num_mac_stats = %u\n",
218 		  efx->num_mac_stats);
219 	return 0;
220 }
221 
222 /*	Event handling
223  */
224 static int ef100_ev_probe(struct efx_channel *channel)
225 {
226 	/* Allocate an extra descriptor for the QMDA status completion entry */
227 	return efx_nic_alloc_buffer(channel->efx, &channel->eventq,
228 				    (channel->eventq_mask + 2) *
229 				    sizeof(efx_qword_t),
230 				    GFP_KERNEL);
231 }
232 
233 static int ef100_ev_init(struct efx_channel *channel)
234 {
235 	struct ef100_nic_data *nic_data = channel->efx->nic_data;
236 
237 	/* initial phase is 0 */
238 	clear_bit(channel->channel, nic_data->evq_phases);
239 
240 	return efx_mcdi_ev_init(channel, false, false);
241 }
242 
243 static void ef100_ev_read_ack(struct efx_channel *channel)
244 {
245 	efx_dword_t evq_prime;
246 
247 	EFX_POPULATE_DWORD_2(evq_prime,
248 			     ERF_GZ_EVQ_ID, channel->channel,
249 			     ERF_GZ_IDX, channel->eventq_read_ptr &
250 					 channel->eventq_mask);
251 
252 	efx_writed(channel->efx, &evq_prime,
253 		   efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME));
254 }
255 
256 #define EFX_NAPI_MAX_TX 512
257 
258 static int ef100_ev_process(struct efx_channel *channel, int quota)
259 {
260 	struct efx_nic *efx = channel->efx;
261 	struct ef100_nic_data *nic_data;
262 	bool evq_phase, old_evq_phase;
263 	unsigned int read_ptr;
264 	efx_qword_t *p_event;
265 	int spent_tx = 0;
266 	int spent = 0;
267 	bool ev_phase;
268 	int ev_type;
269 
270 	if (unlikely(!channel->enabled))
271 		return 0;
272 
273 	nic_data = efx->nic_data;
274 	evq_phase = test_bit(channel->channel, nic_data->evq_phases);
275 	old_evq_phase = evq_phase;
276 	read_ptr = channel->eventq_read_ptr;
277 	BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN);
278 
279 	while (spent < quota) {
280 		p_event = efx_event(channel, read_ptr);
281 
282 		ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE);
283 		if (ev_phase != evq_phase)
284 			break;
285 
286 		netif_vdbg(efx, drv, efx->net_dev,
287 			   "processing event on %d " EFX_QWORD_FMT "\n",
288 			   channel->channel, EFX_QWORD_VAL(*p_event));
289 
290 		ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE);
291 
292 		switch (ev_type) {
293 		case ESE_GZ_EF100_EV_RX_PKTS:
294 			efx_ef100_ev_rx(channel, p_event);
295 			++spent;
296 			break;
297 		case ESE_GZ_EF100_EV_MCDI:
298 			efx_mcdi_process_event(channel, p_event);
299 			break;
300 		case ESE_GZ_EF100_EV_TX_COMPLETION:
301 			spent_tx += ef100_ev_tx(channel, p_event);
302 			if (spent_tx >= EFX_NAPI_MAX_TX)
303 				spent = quota;
304 			break;
305 		case ESE_GZ_EF100_EV_DRIVER:
306 			netif_info(efx, drv, efx->net_dev,
307 				   "Driver initiated event " EFX_QWORD_FMT "\n",
308 				   EFX_QWORD_VAL(*p_event));
309 			break;
310 		default:
311 			netif_info(efx, drv, efx->net_dev,
312 				   "Unhandled event " EFX_QWORD_FMT "\n",
313 				   EFX_QWORD_VAL(*p_event));
314 		}
315 
316 		++read_ptr;
317 		if ((read_ptr & channel->eventq_mask) == 0)
318 			evq_phase = !evq_phase;
319 	}
320 
321 	channel->eventq_read_ptr = read_ptr;
322 	if (evq_phase != old_evq_phase)
323 		change_bit(channel->channel, nic_data->evq_phases);
324 
325 	return spent;
326 }
327 
328 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id)
329 {
330 	struct efx_msi_context *context = dev_id;
331 	struct efx_nic *efx = context->efx;
332 
333 	netif_vdbg(efx, intr, efx->net_dev,
334 		   "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
335 
336 	if (likely(READ_ONCE(efx->irq_soft_enabled))) {
337 		/* Note test interrupts */
338 		if (context->index == efx->irq_level)
339 			efx->last_irq_cpu = raw_smp_processor_id();
340 
341 		/* Schedule processing of the channel */
342 		efx_schedule_channel_irq(efx->channel[context->index]);
343 	}
344 
345 	return IRQ_HANDLED;
346 }
347 
348 int ef100_phy_probe(struct efx_nic *efx)
349 {
350 	struct efx_mcdi_phy_data *phy_data;
351 	int rc;
352 
353 	/* Probe for the PHY */
354 	efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL);
355 	if (!efx->phy_data)
356 		return -ENOMEM;
357 
358 	rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data);
359 	if (rc)
360 		return rc;
361 
362 	/* Populate driver and ethtool settings */
363 	phy_data = efx->phy_data;
364 	mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap,
365 				efx->link_advertising);
366 	efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap,
367 						   false);
368 
369 	/* Default to Autonegotiated flow control if the PHY supports it */
370 	efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
371 	if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
372 		efx->wanted_fc |= EFX_FC_AUTO;
373 	efx_link_set_wanted_fc(efx, efx->wanted_fc);
374 
375 	/* Push settings to the PHY. Failure is not fatal, the user can try to
376 	 * fix it using ethtool.
377 	 */
378 	rc = efx_mcdi_port_reconfigure(efx);
379 	if (rc && rc != -EPERM)
380 		netif_warn(efx, drv, efx->net_dev,
381 			   "could not initialise PHY settings\n");
382 
383 	return 0;
384 }
385 
386 int ef100_filter_table_probe(struct efx_nic *efx)
387 {
388 	return efx_mcdi_filter_table_probe(efx, true);
389 }
390 
391 static int ef100_filter_table_up(struct efx_nic *efx)
392 {
393 	int rc;
394 
395 	down_write(&efx->filter_sem);
396 	rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
397 	if (rc)
398 		goto fail_unspec;
399 
400 	rc = efx_mcdi_filter_add_vlan(efx, 0);
401 	if (rc)
402 		goto fail_vlan0;
403 	/* Drop the lock: we've finished altering table existence, and
404 	 * filter insertion will need to take the lock for read.
405 	 */
406 	up_write(&efx->filter_sem);
407 	if (IS_ENABLED(CONFIG_SFC_SRIOV))
408 		rc = efx_tc_insert_rep_filters(efx);
409 
410 	/* Rep filter failure is nonfatal */
411 	if (rc)
412 		netif_warn(efx, drv, efx->net_dev,
413 			   "Failed to insert representor filters, rc %d\n",
414 			   rc);
415 	return 0;
416 
417 fail_vlan0:
418 	efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
419 fail_unspec:
420 	efx_mcdi_filter_table_down(efx);
421 	up_write(&efx->filter_sem);
422 	return rc;
423 }
424 
425 static void ef100_filter_table_down(struct efx_nic *efx)
426 {
427 	if (IS_ENABLED(CONFIG_SFC_SRIOV))
428 		efx_tc_remove_rep_filters(efx);
429 	down_write(&efx->filter_sem);
430 	efx_mcdi_filter_del_vlan(efx, 0);
431 	efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
432 	efx_mcdi_filter_table_down(efx);
433 	up_write(&efx->filter_sem);
434 }
435 
436 /*	Other
437  */
438 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only)
439 {
440 	WARN_ON(!mutex_is_locked(&efx->mac_lock));
441 
442 	efx_mcdi_filter_sync_rx_mode(efx);
443 
444 	if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
445 		return efx_mcdi_set_mtu(efx);
446 	return efx_mcdi_set_mac(efx);
447 }
448 
449 static enum reset_type ef100_map_reset_reason(enum reset_type reason)
450 {
451 	if (reason == RESET_TYPE_TX_WATCHDOG)
452 		return reason;
453 	return RESET_TYPE_DISABLE;
454 }
455 
456 static int ef100_map_reset_flags(u32 *flags)
457 {
458 	/* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */
459 	if ((*flags & EF100_RESET_PORT)) {
460 		*flags &= ~EF100_RESET_PORT;
461 		return RESET_TYPE_ALL;
462 	}
463 	if (*flags & ETH_RESET_MGMT) {
464 		*flags &= ~ETH_RESET_MGMT;
465 		return RESET_TYPE_DISABLE;
466 	}
467 
468 	return -EINVAL;
469 }
470 
471 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type)
472 {
473 	int rc;
474 
475 	dev_close(efx->net_dev);
476 
477 	if (reset_type == RESET_TYPE_TX_WATCHDOG) {
478 		netif_device_attach(efx->net_dev);
479 		__clear_bit(reset_type, &efx->reset_pending);
480 		rc = dev_open(efx->net_dev, NULL);
481 	} else if (reset_type == RESET_TYPE_ALL) {
482 		rc = efx_mcdi_reset(efx, reset_type);
483 		if (rc)
484 			return rc;
485 
486 		netif_device_attach(efx->net_dev);
487 
488 		rc = dev_open(efx->net_dev, NULL);
489 	} else {
490 		rc = 1;	/* Leave the device closed */
491 	}
492 	return rc;
493 }
494 
495 static void ef100_common_stat_mask(unsigned long *mask)
496 {
497 	__set_bit(EF100_STAT_port_rx_packets, mask);
498 	__set_bit(EF100_STAT_port_tx_packets, mask);
499 	__set_bit(EF100_STAT_port_rx_bytes, mask);
500 	__set_bit(EF100_STAT_port_tx_bytes, mask);
501 	__set_bit(EF100_STAT_port_rx_multicast, mask);
502 	__set_bit(EF100_STAT_port_rx_bad, mask);
503 	__set_bit(EF100_STAT_port_rx_align_error, mask);
504 	__set_bit(EF100_STAT_port_rx_overflow, mask);
505 }
506 
507 static void ef100_ethtool_stat_mask(unsigned long *mask)
508 {
509 	__set_bit(EF100_STAT_port_tx_pause, mask);
510 	__set_bit(EF100_STAT_port_tx_unicast, mask);
511 	__set_bit(EF100_STAT_port_tx_multicast, mask);
512 	__set_bit(EF100_STAT_port_tx_broadcast, mask);
513 	__set_bit(EF100_STAT_port_tx_lt64, mask);
514 	__set_bit(EF100_STAT_port_tx_64, mask);
515 	__set_bit(EF100_STAT_port_tx_65_to_127, mask);
516 	__set_bit(EF100_STAT_port_tx_128_to_255, mask);
517 	__set_bit(EF100_STAT_port_tx_256_to_511, mask);
518 	__set_bit(EF100_STAT_port_tx_512_to_1023, mask);
519 	__set_bit(EF100_STAT_port_tx_1024_to_15xx, mask);
520 	__set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask);
521 	__set_bit(EF100_STAT_port_rx_good, mask);
522 	__set_bit(EF100_STAT_port_rx_pause, mask);
523 	__set_bit(EF100_STAT_port_rx_unicast, mask);
524 	__set_bit(EF100_STAT_port_rx_broadcast, mask);
525 	__set_bit(EF100_STAT_port_rx_lt64, mask);
526 	__set_bit(EF100_STAT_port_rx_64, mask);
527 	__set_bit(EF100_STAT_port_rx_65_to_127, mask);
528 	__set_bit(EF100_STAT_port_rx_128_to_255, mask);
529 	__set_bit(EF100_STAT_port_rx_256_to_511, mask);
530 	__set_bit(EF100_STAT_port_rx_512_to_1023, mask);
531 	__set_bit(EF100_STAT_port_rx_1024_to_15xx, mask);
532 	__set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask);
533 	__set_bit(EF100_STAT_port_rx_gtjumbo, mask);
534 	__set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask);
535 	__set_bit(EF100_STAT_port_rx_length_error, mask);
536 	__set_bit(EF100_STAT_port_rx_nodesc_drops, mask);
537 	__set_bit(GENERIC_STAT_rx_nodesc_trunc, mask);
538 	__set_bit(GENERIC_STAT_rx_noskb_drops, mask);
539 }
540 
541 #define EF100_DMA_STAT(ext_name, mcdi_name)			\
542 	[EF100_STAT_ ## ext_name] =				\
543 	{ #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
544 
545 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = {
546 	EF100_DMA_STAT(port_tx_bytes, TX_BYTES),
547 	EF100_DMA_STAT(port_tx_packets, TX_PKTS),
548 	EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
549 	EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
550 	EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
551 	EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
552 	EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
553 	EF100_DMA_STAT(port_tx_64, TX_64_PKTS),
554 	EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
555 	EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
556 	EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
557 	EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
558 	EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
559 	EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
560 	EF100_DMA_STAT(port_rx_bytes, RX_BYTES),
561 	EF100_DMA_STAT(port_rx_packets, RX_PKTS),
562 	EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
563 	EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
564 	EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
565 	EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
566 	EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
567 	EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
568 	EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
569 	EF100_DMA_STAT(port_rx_64, RX_64_PKTS),
570 	EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
571 	EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
572 	EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
573 	EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
574 	EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
575 	EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
576 	EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
577 	EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
578 	EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
579 	EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
580 	EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
581 	EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
582 	EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
583 	EFX_GENERIC_SW_STAT(rx_noskb_drops),
584 };
585 
586 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names)
587 {
588 	DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
589 
590 	ef100_ethtool_stat_mask(mask);
591 	return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT,
592 				      mask, names);
593 }
594 
595 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats,
596 					struct rtnl_link_stats64 *core_stats)
597 {
598 	struct ef100_nic_data *nic_data = efx->nic_data;
599 	DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
600 	size_t stats_count = 0, index;
601 	u64 *stats = nic_data->stats;
602 
603 	ef100_ethtool_stat_mask(mask);
604 
605 	if (full_stats) {
606 		for_each_set_bit(index, mask, EF100_STAT_COUNT) {
607 			if (ef100_stat_desc[index].name) {
608 				*full_stats++ = stats[index];
609 				++stats_count;
610 			}
611 		}
612 	}
613 
614 	if (!core_stats)
615 		return stats_count;
616 
617 	core_stats->rx_packets = stats[EF100_STAT_port_rx_packets];
618 	core_stats->tx_packets = stats[EF100_STAT_port_tx_packets];
619 	core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes];
620 	core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes];
621 	core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] +
622 				 stats[GENERIC_STAT_rx_nodesc_trunc] +
623 				 stats[GENERIC_STAT_rx_noskb_drops];
624 	core_stats->multicast = stats[EF100_STAT_port_rx_multicast];
625 	core_stats->rx_length_errors =
626 			stats[EF100_STAT_port_rx_gtjumbo] +
627 			stats[EF100_STAT_port_rx_length_error];
628 	core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad];
629 	core_stats->rx_frame_errors =
630 			stats[EF100_STAT_port_rx_align_error];
631 	core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow];
632 	core_stats->rx_errors = (core_stats->rx_length_errors +
633 				 core_stats->rx_crc_errors +
634 				 core_stats->rx_frame_errors);
635 
636 	return stats_count;
637 }
638 
639 static size_t ef100_update_stats(struct efx_nic *efx,
640 				 u64 *full_stats,
641 				 struct rtnl_link_stats64 *core_stats)
642 {
643 	__le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC);
644 	struct ef100_nic_data *nic_data = efx->nic_data;
645 	DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
646 	u64 *stats = nic_data->stats;
647 
648 	ef100_common_stat_mask(mask);
649 	ef100_ethtool_stat_mask(mask);
650 
651 	if (!mc_stats)
652 		return 0;
653 
654 	efx_nic_copy_stats(efx, mc_stats);
655 	efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask,
656 			     stats, mc_stats, false);
657 
658 	kfree(mc_stats);
659 
660 	return ef100_update_stats_common(efx, full_stats, core_stats);
661 }
662 
663 static int efx_ef100_get_phys_port_id(struct efx_nic *efx,
664 				      struct netdev_phys_item_id *ppid)
665 {
666 	struct ef100_nic_data *nic_data = efx->nic_data;
667 
668 	if (!is_valid_ether_addr(nic_data->port_id))
669 		return -EOPNOTSUPP;
670 
671 	ppid->id_len = ETH_ALEN;
672 	memcpy(ppid->id, nic_data->port_id, ppid->id_len);
673 
674 	return 0;
675 }
676 
677 static int efx_ef100_irq_test_generate(struct efx_nic *efx)
678 {
679 	MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
680 
681 	BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
682 
683 	MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
684 	return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT,
685 				  inbuf, sizeof(inbuf), NULL, 0, NULL);
686 }
687 
688 #define EFX_EF100_TEST 1
689 
690 static void efx_ef100_ev_test_generate(struct efx_channel *channel)
691 {
692 	MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
693 	struct efx_nic *efx = channel->efx;
694 	efx_qword_t event;
695 	int rc;
696 
697 	EFX_POPULATE_QWORD_2(event,
698 			     ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER,
699 			     ESF_GZ_DRIVER_DATA, EFX_EF100_TEST);
700 
701 	MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
702 
703 	/* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
704 	 * already swapped the data to little-endian order.
705 	 */
706 	memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
707 	       sizeof(efx_qword_t));
708 
709 	rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
710 			  NULL, 0, NULL);
711 	if (rc && (rc != -ENETDOWN))
712 		goto fail;
713 
714 	return;
715 
716 fail:
717 	WARN_ON(true);
718 	netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
719 }
720 
721 static unsigned int ef100_check_caps(const struct efx_nic *efx,
722 				     u8 flag, u32 offset)
723 {
724 	const struct ef100_nic_data *nic_data = efx->nic_data;
725 
726 	switch (offset) {
727 	case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST:
728 		return nic_data->datapath_caps & BIT_ULL(flag);
729 	case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST:
730 		return nic_data->datapath_caps2 & BIT_ULL(flag);
731 	case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST:
732 		return nic_data->datapath_caps3 & BIT_ULL(flag);
733 	default:
734 		return 0;
735 	}
736 }
737 
738 static unsigned int efx_ef100_recycle_ring_size(const struct efx_nic *efx)
739 {
740 	/* Maximum link speed for Riverhead is 100G */
741 	return 10 * EFX_RECYCLE_RING_SIZE_10G;
742 }
743 
744 static int efx_ef100_get_base_mport(struct efx_nic *efx)
745 {
746 	struct ef100_nic_data *nic_data = efx->nic_data;
747 	u32 selector, id;
748 	int rc;
749 
750 	/* Construct mport selector for "physical network port" */
751 	efx_mae_mport_wire(efx, &selector);
752 	/* Look up actual mport ID */
753 	rc = efx_mae_fw_lookup_mport(efx, selector, &id);
754 	if (rc)
755 		return rc;
756 	/* The ID should always fit in 16 bits, because that's how wide the
757 	 * corresponding fields in the RX prefix & TX override descriptor are
758 	 */
759 	if (id >> 16)
760 		netif_warn(efx, probe, efx->net_dev, "Bad base m-port id %#x\n",
761 			   id);
762 	nic_data->base_mport = id;
763 	nic_data->have_mport = true;
764 
765 	/* Construct mport selector for "calling PF" */
766 	efx_mae_mport_uplink(efx, &selector);
767 	/* Look up actual mport ID */
768 	rc = efx_mae_fw_lookup_mport(efx, selector, &id);
769 	if (rc)
770 		return rc;
771 	if (id >> 16)
772 		netif_warn(efx, probe, efx->net_dev, "Bad own m-port id %#x\n",
773 			   id);
774 	nic_data->own_mport = id;
775 	nic_data->have_own_mport = true;
776 
777 	return 0;
778 }
779 
780 static int compare_versions(const char *a, const char *b)
781 {
782 	int a_major, a_minor, a_point, a_patch;
783 	int b_major, b_minor, b_point, b_patch;
784 	int a_matched, b_matched;
785 
786 	a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch);
787 	b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch);
788 
789 	if (a_matched == 4 && b_matched != 4)
790 		return +1;
791 
792 	if (a_matched != 4 && b_matched == 4)
793 		return -1;
794 
795 	if (a_matched != 4 && b_matched != 4)
796 		return 0;
797 
798 	if (a_major != b_major)
799 		return a_major - b_major;
800 
801 	if (a_minor != b_minor)
802 		return a_minor - b_minor;
803 
804 	if (a_point != b_point)
805 		return a_point - b_point;
806 
807 	return a_patch - b_patch;
808 }
809 
810 enum ef100_tlv_state_machine {
811 	EF100_TLV_TYPE,
812 	EF100_TLV_TYPE_CONT,
813 	EF100_TLV_LENGTH,
814 	EF100_TLV_VALUE
815 };
816 
817 struct ef100_tlv_state {
818 	enum ef100_tlv_state_machine state;
819 	u64 value;
820 	u32 value_offset;
821 	u16 type;
822 	u8 len;
823 };
824 
825 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte)
826 {
827 	switch (state->state) {
828 	case EF100_TLV_TYPE:
829 		state->type = byte & 0x7f;
830 		state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT
831 					     : EF100_TLV_LENGTH;
832 		/* Clear ready to read in a new entry */
833 		state->value = 0;
834 		state->value_offset = 0;
835 		return 0;
836 	case EF100_TLV_TYPE_CONT:
837 		state->type |= byte << 7;
838 		state->state = EF100_TLV_LENGTH;
839 		return 0;
840 	case EF100_TLV_LENGTH:
841 		state->len = byte;
842 		/* We only handle TLVs that fit in a u64 */
843 		if (state->len > sizeof(state->value))
844 			return -EOPNOTSUPP;
845 		/* len may be zero, implying a value of zero */
846 		state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE;
847 		return 0;
848 	case EF100_TLV_VALUE:
849 		state->value |= ((u64)byte) << (state->value_offset * 8);
850 		state->value_offset++;
851 		if (state->value_offset >= state->len)
852 			state->state = EF100_TLV_TYPE;
853 		return 0;
854 	default: /* state machine error, can't happen */
855 		WARN_ON_ONCE(1);
856 		return -EIO;
857 	}
858 }
859 
860 static int ef100_process_design_param(struct efx_nic *efx,
861 				      const struct ef100_tlv_state *reader)
862 {
863 	struct ef100_nic_data *nic_data = efx->nic_data;
864 
865 	switch (reader->type) {
866 	case ESE_EF100_DP_GZ_PAD: /* padding, skip it */
867 		return 0;
868 	case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS:
869 		/* Driver doesn't support timestamping yet, so we don't care */
870 		return 0;
871 	case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS:
872 		/* Driver doesn't support unsolicited-event credits yet, so
873 		 * we don't care
874 		 */
875 		return 0;
876 	case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE:
877 		/* Driver doesn't manage the NMMU (so we don't care) */
878 		return 0;
879 	case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS:
880 		/* Driver uses CHECKSUM_COMPLETE, so we don't care about
881 		 * protocol checksum validation
882 		 */
883 		return 0;
884 	case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN:
885 		nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff);
886 		return 0;
887 	case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS:
888 		/* We always put HDR_NUM_SEGS=1 in our TSO descriptors */
889 		if (!reader->value) {
890 			netif_err(efx, probe, efx->net_dev,
891 				  "TSO_MAX_HDR_NUM_SEGS < 1\n");
892 			return -EOPNOTSUPP;
893 		}
894 		return 0;
895 	case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY:
896 	case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY:
897 		/* Our TXQ and RXQ sizes are always power-of-two and thus divisible by
898 		 * EFX_MIN_DMAQ_SIZE, so we just need to check that
899 		 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY.
900 		 * This is very unlikely to fail.
901 		 */
902 		if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE ||
903 		    EFX_MIN_DMAQ_SIZE % (u32)reader->value) {
904 			netif_err(efx, probe, efx->net_dev,
905 				  "%s size granularity is %llu, can't guarantee safety\n",
906 				  reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ",
907 				  reader->value);
908 			return -EOPNOTSUPP;
909 		}
910 		return 0;
911 	case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN:
912 		nic_data->tso_max_payload_len = min_t(u64, reader->value,
913 						      GSO_LEGACY_MAX_SIZE);
914 		netif_set_tso_max_size(efx->net_dev,
915 				       nic_data->tso_max_payload_len);
916 		return 0;
917 	case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS:
918 		nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff);
919 		netif_set_tso_max_segs(efx->net_dev,
920 				       nic_data->tso_max_payload_num_segs);
921 		return 0;
922 	case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES:
923 		nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff);
924 		return 0;
925 	case ESE_EF100_DP_GZ_COMPAT:
926 		if (reader->value) {
927 			netif_err(efx, probe, efx->net_dev,
928 				  "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n",
929 				  reader->value);
930 			return -EOPNOTSUPP;
931 		}
932 		return 0;
933 	case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN:
934 		/* Driver doesn't use mem2mem transfers */
935 		return 0;
936 	case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS:
937 		/* Driver doesn't currently use EVQ_TIMER */
938 		return 0;
939 	case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES:
940 		/* Driver doesn't manage the NMMU (so we don't care) */
941 		return 0;
942 	case ESE_EF100_DP_GZ_VI_STRIDES:
943 		/* We never try to set the VI stride, and we don't rely on
944 		 * being able to find VIs past VI 0 until after we've learned
945 		 * the current stride from MC_CMD_GET_CAPABILITIES.
946 		 * So the value of this shouldn't matter.
947 		 */
948 		if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT)
949 			netif_dbg(efx, probe, efx->net_dev,
950 				  "NIC has other than default VI_STRIDES (mask "
951 				  "%#llx), early probing might use wrong one\n",
952 				  reader->value);
953 		return 0;
954 	case ESE_EF100_DP_GZ_RX_MAX_RUNT:
955 		/* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't
956 		 * care whether it indicates runt or overlength for any given
957 		 * packet, so we don't care about this parameter.
958 		 */
959 		return 0;
960 	default:
961 		/* Host interface says "Drivers should ignore design parameters
962 		 * that they do not recognise."
963 		 */
964 		netif_dbg(efx, probe, efx->net_dev,
965 			  "Ignoring unrecognised design parameter %u\n",
966 			  reader->type);
967 		return 0;
968 	}
969 }
970 
971 static int ef100_check_design_params(struct efx_nic *efx)
972 {
973 	struct ef100_tlv_state reader = {};
974 	u32 total_len, offset = 0;
975 	efx_dword_t reg;
976 	int rc = 0, i;
977 	u32 data;
978 
979 	efx_readd(efx, &reg, ER_GZ_PARAMS_TLV_LEN);
980 	total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
981 	pci_dbg(efx->pci_dev, "%u bytes of design parameters\n", total_len);
982 	while (offset < total_len) {
983 		efx_readd(efx, &reg, ER_GZ_PARAMS_TLV + offset);
984 		data = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
985 		for (i = 0; i < sizeof(data); i++) {
986 			rc = ef100_tlv_feed(&reader, data);
987 			/* Got a complete value? */
988 			if (!rc && reader.state == EF100_TLV_TYPE)
989 				rc = ef100_process_design_param(efx, &reader);
990 			if (rc)
991 				goto out;
992 			data >>= 8;
993 			offset++;
994 		}
995 	}
996 	/* Check we didn't end halfway through a TLV entry, which could either
997 	 * mean that the TLV stream is truncated or just that it's corrupted
998 	 * and our state machine is out of sync.
999 	 */
1000 	if (reader.state != EF100_TLV_TYPE) {
1001 		if (reader.state == EF100_TLV_TYPE_CONT)
1002 			netif_err(efx, probe, efx->net_dev,
1003 				  "truncated design parameter (incomplete type %u)\n",
1004 				  reader.type);
1005 		else
1006 			netif_err(efx, probe, efx->net_dev,
1007 				  "truncated design parameter %u\n",
1008 				  reader.type);
1009 		rc = -EIO;
1010 	}
1011 out:
1012 	return rc;
1013 }
1014 
1015 /*	NIC probe and remove
1016  */
1017 static int ef100_probe_main(struct efx_nic *efx)
1018 {
1019 	unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]);
1020 	struct ef100_nic_data *nic_data;
1021 	char fw_version[32];
1022 	u32 priv_mask = 0;
1023 	int i, rc;
1024 
1025 	if (WARN_ON(bar_size == 0))
1026 		return -EIO;
1027 
1028 	nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1029 	if (!nic_data)
1030 		return -ENOMEM;
1031 	efx->nic_data = nic_data;
1032 	nic_data->efx = efx;
1033 	efx->max_vis = EF100_MAX_VIS;
1034 
1035 	/* Populate design-parameter defaults */
1036 	nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
1037 	nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
1038 	nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
1039 	nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
1040 
1041 	/* Read design parameters */
1042 	rc = ef100_check_design_params(efx);
1043 	if (rc) {
1044 		pci_err(efx->pci_dev, "Unsupported design parameters\n");
1045 		goto fail;
1046 	}
1047 
1048 	/* we assume later that we can copy from this buffer in dwords */
1049 	BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
1050 
1051 	/* MCDI buffers must be 256 byte aligned. */
1052 	rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN,
1053 				  GFP_KERNEL);
1054 	if (rc)
1055 		goto fail;
1056 
1057 	/* Get the MC's warm boot count.  In case it's rebooting right
1058 	 * now, be prepared to retry.
1059 	 */
1060 	i = 0;
1061 	for (;;) {
1062 		rc = ef100_get_warm_boot_count(efx);
1063 		if (rc >= 0)
1064 			break;
1065 		if (++i == 5)
1066 			goto fail;
1067 		ssleep(1);
1068 	}
1069 	nic_data->warm_boot_count = rc;
1070 
1071 	/* In case we're recovering from a crash (kexec), we want to
1072 	 * cancel any outstanding request by the previous user of this
1073 	 * function.  We send a special message using the least
1074 	 * significant bits of the 'high' (doorbell) register.
1075 	 */
1076 	_efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD));
1077 
1078 	/* Post-IO section. */
1079 
1080 	rc = efx_mcdi_init(efx);
1081 	if (rc)
1082 		goto fail;
1083 	/* Reset (most) configuration for this function */
1084 	rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
1085 	if (rc)
1086 		goto fail;
1087 	/* Enable event logging */
1088 	rc = efx_mcdi_log_ctrl(efx, true, false, 0);
1089 	if (rc)
1090 		goto fail;
1091 
1092 	rc = efx_get_pf_index(efx, &nic_data->pf_index);
1093 	if (rc)
1094 		goto fail;
1095 
1096 	rc = efx_mcdi_port_get_number(efx);
1097 	if (rc < 0)
1098 		goto fail;
1099 	efx->port_num = rc;
1100 
1101 	efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version));
1102 	pci_dbg(efx->pci_dev, "Firmware version %s\n", fw_version);
1103 
1104 	rc = efx_mcdi_get_privilege_mask(efx, &priv_mask);
1105 	if (rc) /* non-fatal, and priv_mask will still be 0 */
1106 		pci_info(efx->pci_dev,
1107 			 "Failed to get privilege mask from FW, rc %d\n", rc);
1108 	nic_data->grp_mae = !!(priv_mask & MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE);
1109 
1110 	if (compare_versions(fw_version, "1.1.0.1000") < 0) {
1111 		pci_info(efx->pci_dev, "Firmware uses old event descriptors\n");
1112 		rc = -EINVAL;
1113 		goto fail;
1114 	}
1115 
1116 	if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) {
1117 		pci_info(efx->pci_dev, "Firmware uses unsolicited-event credits\n");
1118 		rc = -EINVAL;
1119 		goto fail;
1120 	}
1121 
1122 	return 0;
1123 fail:
1124 	return rc;
1125 }
1126 
1127 /* MCDI commands are related to the same device issuing them. This function
1128  * allows to do an MCDI command on behalf of another device, mainly PFs setting
1129  * things for VFs.
1130  */
1131 int efx_ef100_lookup_client_id(struct efx_nic *efx, efx_qword_t pciefn, u32 *id)
1132 {
1133 	MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLIENT_HANDLE_OUT_LEN);
1134 	MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_CLIENT_HANDLE_IN_LEN);
1135 	u64 pciefn_flat = le64_to_cpu(pciefn.u64[0]);
1136 	size_t outlen;
1137 	int rc;
1138 
1139 	MCDI_SET_DWORD(inbuf, GET_CLIENT_HANDLE_IN_TYPE,
1140 		       MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_FUNC);
1141 	MCDI_SET_QWORD(inbuf, GET_CLIENT_HANDLE_IN_FUNC,
1142 		       pciefn_flat);
1143 
1144 	rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLIENT_HANDLE, inbuf, sizeof(inbuf),
1145 			  outbuf, sizeof(outbuf), &outlen);
1146 	if (rc)
1147 		return rc;
1148 	if (outlen < sizeof(outbuf))
1149 		return -EIO;
1150 	*id = MCDI_DWORD(outbuf, GET_CLIENT_HANDLE_OUT_HANDLE);
1151 	return 0;
1152 }
1153 
1154 int ef100_probe_netdev_pf(struct efx_nic *efx)
1155 {
1156 	struct ef100_nic_data *nic_data = efx->nic_data;
1157 	struct net_device *net_dev = efx->net_dev;
1158 	int rc;
1159 
1160 	if (!IS_ENABLED(CONFIG_SFC_SRIOV) || !nic_data->grp_mae)
1161 		return 0;
1162 
1163 	rc = efx_init_struct_tc(efx);
1164 	if (rc)
1165 		return rc;
1166 
1167 	rc = efx_ef100_get_base_mport(efx);
1168 	if (rc) {
1169 		netif_warn(efx, probe, net_dev,
1170 			   "Failed to probe base mport rc %d; representors will not function\n",
1171 			   rc);
1172 	}
1173 
1174 	rc = efx_init_mae(efx);
1175 	if (rc)
1176 		netif_warn(efx, probe, net_dev,
1177 			   "Failed to init MAE rc %d; representors will not function\n",
1178 			   rc);
1179 	else
1180 		efx_ef100_init_reps(efx);
1181 
1182 	rc = efx_init_tc(efx);
1183 	if (rc) {
1184 		/* Either we don't have an MAE at all (i.e. legacy v-switching),
1185 		 * or we do but we failed to probe it.  In the latter case, we
1186 		 * may not have set up default rules, in which case we won't be
1187 		 * able to pass any traffic.  However, we don't fail the probe,
1188 		 * because the user might need to use the netdevice to apply
1189 		 * configuration changes to fix whatever's wrong with the MAE.
1190 		 */
1191 		netif_warn(efx, probe, net_dev, "Failed to probe MAE rc %d\n",
1192 			   rc);
1193 	} else {
1194 		net_dev->features |= NETIF_F_HW_TC;
1195 		efx->fixed_features |= NETIF_F_HW_TC;
1196 	}
1197 	return 0;
1198 }
1199 
1200 int ef100_probe_vf(struct efx_nic *efx)
1201 {
1202 	return ef100_probe_main(efx);
1203 }
1204 
1205 void ef100_remove(struct efx_nic *efx)
1206 {
1207 	struct ef100_nic_data *nic_data = efx->nic_data;
1208 
1209 	if (IS_ENABLED(CONFIG_SFC_SRIOV) && efx->mae) {
1210 		efx_ef100_fini_reps(efx);
1211 		efx_fini_mae(efx);
1212 	}
1213 
1214 	efx_mcdi_detach(efx);
1215 	efx_mcdi_fini(efx);
1216 	if (nic_data)
1217 		efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1218 	kfree(nic_data);
1219 	efx->nic_data = NULL;
1220 }
1221 
1222 /*	NIC level access functions
1223  */
1224 #define EF100_OFFLOAD_FEATURES	(NETIF_F_HW_CSUM | NETIF_F_RXCSUM |	\
1225 	NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \
1226 	NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \
1227 	NETIF_F_HW_VLAN_CTAG_TX)
1228 
1229 const struct efx_nic_type ef100_pf_nic_type = {
1230 	.revision = EFX_REV_EF100,
1231 	.is_vf = false,
1232 	.probe = ef100_probe_main,
1233 	.offload_features = EF100_OFFLOAD_FEATURES,
1234 	.mcdi_max_ver = 2,
1235 	.mcdi_request = ef100_mcdi_request,
1236 	.mcdi_poll_response = ef100_mcdi_poll_response,
1237 	.mcdi_read_response = ef100_mcdi_read_response,
1238 	.mcdi_poll_reboot = ef100_mcdi_poll_reboot,
1239 	.mcdi_reboot_detected = ef100_mcdi_reboot_detected,
1240 	.irq_enable_master = efx_port_dummy_op_void,
1241 	.irq_test_generate = efx_ef100_irq_test_generate,
1242 	.irq_disable_non_ev = efx_port_dummy_op_void,
1243 	.push_irq_moderation = efx_channel_dummy_op_void,
1244 	.min_interrupt_mode = EFX_INT_MODE_MSIX,
1245 	.map_reset_reason = ef100_map_reset_reason,
1246 	.map_reset_flags = ef100_map_reset_flags,
1247 	.reset = ef100_reset,
1248 
1249 	.check_caps = ef100_check_caps,
1250 
1251 	.ev_probe = ef100_ev_probe,
1252 	.ev_init = ef100_ev_init,
1253 	.ev_fini = efx_mcdi_ev_fini,
1254 	.ev_remove = efx_mcdi_ev_remove,
1255 	.irq_handle_msi = ef100_msi_interrupt,
1256 	.ev_process = ef100_ev_process,
1257 	.ev_read_ack = ef100_ev_read_ack,
1258 	.ev_test_generate = efx_ef100_ev_test_generate,
1259 	.tx_probe = ef100_tx_probe,
1260 	.tx_init = ef100_tx_init,
1261 	.tx_write = ef100_tx_write,
1262 	.tx_enqueue = ef100_enqueue_skb,
1263 	.rx_probe = efx_mcdi_rx_probe,
1264 	.rx_init = efx_mcdi_rx_init,
1265 	.rx_remove = efx_mcdi_rx_remove,
1266 	.rx_write = ef100_rx_write,
1267 	.rx_packet = __ef100_rx_packet,
1268 	.rx_buf_hash_valid = ef100_rx_buf_hash_valid,
1269 	.fini_dmaq = efx_fini_dmaq,
1270 	.max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
1271 	.filter_table_probe = ef100_filter_table_up,
1272 	.filter_table_restore = efx_mcdi_filter_table_restore,
1273 	.filter_table_remove = ef100_filter_table_down,
1274 	.filter_insert = efx_mcdi_filter_insert,
1275 	.filter_remove_safe = efx_mcdi_filter_remove_safe,
1276 	.filter_get_safe = efx_mcdi_filter_get_safe,
1277 	.filter_clear_rx = efx_mcdi_filter_clear_rx,
1278 	.filter_count_rx_used = efx_mcdi_filter_count_rx_used,
1279 	.filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
1280 	.filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
1281 #ifdef CONFIG_RFS_ACCEL
1282 	.filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
1283 #endif
1284 
1285 	.get_phys_port_id = efx_ef100_get_phys_port_id,
1286 
1287 	.rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
1288 	.rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
1289 	.rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
1290 	.rx_hash_key_size = 40,
1291 	.rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
1292 	.rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
1293 	.rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
1294 	.rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
1295 	.rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
1296 	.rx_recycle_ring_size = efx_ef100_recycle_ring_size,
1297 
1298 	.reconfigure_mac = ef100_reconfigure_mac,
1299 	.reconfigure_port = efx_mcdi_port_reconfigure,
1300 	.test_nvram = efx_new_mcdi_nvram_test_all,
1301 	.describe_stats = ef100_describe_stats,
1302 	.start_stats = efx_mcdi_mac_start_stats,
1303 	.update_stats = ef100_update_stats,
1304 	.pull_stats = efx_mcdi_mac_pull_stats,
1305 	.stop_stats = efx_mcdi_mac_stop_stats,
1306 	.sriov_configure = IS_ENABLED(CONFIG_SFC_SRIOV) ?
1307 		efx_ef100_sriov_configure : NULL,
1308 
1309 	/* Per-type bar/size configuration not used on ef100. Location of
1310 	 * registers is defined by extended capabilities.
1311 	 */
1312 	.mem_bar = NULL,
1313 	.mem_map_size = NULL,
1314 
1315 };
1316 
1317 const struct efx_nic_type ef100_vf_nic_type = {
1318 	.revision = EFX_REV_EF100,
1319 	.is_vf = true,
1320 	.probe = ef100_probe_vf,
1321 	.offload_features = EF100_OFFLOAD_FEATURES,
1322 	.mcdi_max_ver = 2,
1323 	.mcdi_request = ef100_mcdi_request,
1324 	.mcdi_poll_response = ef100_mcdi_poll_response,
1325 	.mcdi_read_response = ef100_mcdi_read_response,
1326 	.mcdi_poll_reboot = ef100_mcdi_poll_reboot,
1327 	.mcdi_reboot_detected = ef100_mcdi_reboot_detected,
1328 	.irq_enable_master = efx_port_dummy_op_void,
1329 	.irq_test_generate = efx_ef100_irq_test_generate,
1330 	.irq_disable_non_ev = efx_port_dummy_op_void,
1331 	.push_irq_moderation = efx_channel_dummy_op_void,
1332 	.min_interrupt_mode = EFX_INT_MODE_MSIX,
1333 	.map_reset_reason = ef100_map_reset_reason,
1334 	.map_reset_flags = ef100_map_reset_flags,
1335 	.reset = ef100_reset,
1336 	.check_caps = ef100_check_caps,
1337 	.ev_probe = ef100_ev_probe,
1338 	.ev_init = ef100_ev_init,
1339 	.ev_fini = efx_mcdi_ev_fini,
1340 	.ev_remove = efx_mcdi_ev_remove,
1341 	.irq_handle_msi = ef100_msi_interrupt,
1342 	.ev_process = ef100_ev_process,
1343 	.ev_read_ack = ef100_ev_read_ack,
1344 	.ev_test_generate = efx_ef100_ev_test_generate,
1345 	.tx_probe = ef100_tx_probe,
1346 	.tx_init = ef100_tx_init,
1347 	.tx_write = ef100_tx_write,
1348 	.tx_enqueue = ef100_enqueue_skb,
1349 	.rx_probe = efx_mcdi_rx_probe,
1350 	.rx_init = efx_mcdi_rx_init,
1351 	.rx_remove = efx_mcdi_rx_remove,
1352 	.rx_write = ef100_rx_write,
1353 	.rx_packet = __ef100_rx_packet,
1354 	.rx_buf_hash_valid = ef100_rx_buf_hash_valid,
1355 	.fini_dmaq = efx_fini_dmaq,
1356 	.max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
1357 	.filter_table_probe = ef100_filter_table_up,
1358 	.filter_table_restore = efx_mcdi_filter_table_restore,
1359 	.filter_table_remove = ef100_filter_table_down,
1360 	.filter_insert = efx_mcdi_filter_insert,
1361 	.filter_remove_safe = efx_mcdi_filter_remove_safe,
1362 	.filter_get_safe = efx_mcdi_filter_get_safe,
1363 	.filter_clear_rx = efx_mcdi_filter_clear_rx,
1364 	.filter_count_rx_used = efx_mcdi_filter_count_rx_used,
1365 	.filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
1366 	.filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
1367 #ifdef CONFIG_RFS_ACCEL
1368 	.filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
1369 #endif
1370 
1371 	.rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
1372 	.rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
1373 	.rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
1374 	.rx_hash_key_size = 40,
1375 	.rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
1376 	.rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
1377 	.rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
1378 	.rx_recycle_ring_size = efx_ef100_recycle_ring_size,
1379 
1380 	.reconfigure_mac = ef100_reconfigure_mac,
1381 	.test_nvram = efx_new_mcdi_nvram_test_all,
1382 	.describe_stats = ef100_describe_stats,
1383 	.start_stats = efx_mcdi_mac_start_stats,
1384 	.update_stats = ef100_update_stats,
1385 	.pull_stats = efx_mcdi_mac_pull_stats,
1386 	.stop_stats = efx_mcdi_mac_stop_stats,
1387 
1388 	.mem_bar = NULL,
1389 	.mem_map_size = NULL,
1390 
1391 };
1392