1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2012-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 #include "net_driver.h" 11 #include "ef10_regs.h" 12 #include "io.h" 13 #include "mcdi.h" 14 #include "mcdi_pcol.h" 15 #include "nic.h" 16 #include "workarounds.h" 17 #include "selftest.h" 18 #include "ef10_sriov.h" 19 #include <linux/in.h> 20 #include <linux/jhash.h> 21 #include <linux/wait.h> 22 #include <linux/workqueue.h> 23 24 /* Hardware control for EF10 architecture including 'Huntington'. */ 25 26 #define EFX_EF10_DRVGEN_EV 7 27 enum { 28 EFX_EF10_TEST = 1, 29 EFX_EF10_REFILL, 30 }; 31 32 /* The reserved RSS context value */ 33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff 34 /* The maximum size of a shared RSS context */ 35 /* TODO: this should really be from the mcdi protocol export */ 36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL 37 38 /* The filter table(s) are managed by firmware and we have write-only 39 * access. When removing filters we must identify them to the 40 * firmware by a 64-bit handle, but this is too wide for Linux kernel 41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to 42 * be able to tell in advance whether a requested insertion will 43 * replace an existing filter. Therefore we maintain a software hash 44 * table, which should be at least as large as the hardware hash 45 * table. 46 * 47 * Huntington has a single 8K filter table shared between all filter 48 * types and both ports. 49 */ 50 #define HUNT_FILTER_TBL_ROWS 8192 51 52 struct efx_ef10_filter_table { 53 /* The RX match field masks supported by this fw & hw, in order of priority */ 54 enum efx_filter_match_flags rx_match_flags[ 55 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM]; 56 unsigned int rx_match_count; 57 58 struct { 59 unsigned long spec; /* pointer to spec plus flag bits */ 60 /* BUSY flag indicates that an update is in progress. AUTO_OLD is 61 * used to mark and sweep MAC filters for the device address lists. 62 */ 63 #define EFX_EF10_FILTER_FLAG_BUSY 1UL 64 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL 65 #define EFX_EF10_FILTER_FLAGS 3UL 66 u64 handle; /* firmware handle */ 67 } *entry; 68 wait_queue_head_t waitq; 69 /* Shadow of net_device address lists, guarded by mac_lock */ 70 #define EFX_EF10_FILTER_DEV_UC_MAX 32 71 #define EFX_EF10_FILTER_DEV_MC_MAX 256 72 struct { 73 u8 addr[ETH_ALEN]; 74 u16 id; 75 } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX], 76 dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX]; 77 int dev_uc_count; /* negative for PROMISC */ 78 int dev_mc_count; /* negative for PROMISC/ALLMULTI */ 79 }; 80 81 /* An arbitrary search limit for the software hash table */ 82 #define EFX_EF10_FILTER_SEARCH_LIMIT 200 83 84 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx); 85 static void efx_ef10_filter_table_remove(struct efx_nic *efx); 86 87 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 88 { 89 efx_dword_t reg; 90 91 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 92 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 93 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 94 } 95 96 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 97 { 98 int bar; 99 100 bar = efx->type->mem_bar; 101 return resource_size(&efx->pci_dev->resource[bar]); 102 } 103 104 static bool efx_ef10_is_vf(struct efx_nic *efx) 105 { 106 return efx->type->is_vf; 107 } 108 109 static int efx_ef10_get_pf_index(struct efx_nic *efx) 110 { 111 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 112 struct efx_ef10_nic_data *nic_data = efx->nic_data; 113 size_t outlen; 114 int rc; 115 116 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 117 sizeof(outbuf), &outlen); 118 if (rc) 119 return rc; 120 if (outlen < sizeof(outbuf)) 121 return -EIO; 122 123 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF); 124 return 0; 125 } 126 127 #ifdef CONFIG_SFC_SRIOV 128 static int efx_ef10_get_vf_index(struct efx_nic *efx) 129 { 130 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 131 struct efx_ef10_nic_data *nic_data = efx->nic_data; 132 size_t outlen; 133 int rc; 134 135 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 136 sizeof(outbuf), &outlen); 137 if (rc) 138 return rc; 139 if (outlen < sizeof(outbuf)) 140 return -EIO; 141 142 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 143 return 0; 144 } 145 #endif 146 147 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 148 { 149 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN); 150 struct efx_ef10_nic_data *nic_data = efx->nic_data; 151 size_t outlen; 152 int rc; 153 154 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 155 156 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 157 outbuf, sizeof(outbuf), &outlen); 158 if (rc) 159 return rc; 160 if (outlen < sizeof(outbuf)) { 161 netif_err(efx, drv, efx->net_dev, 162 "unable to read datapath firmware capabilities\n"); 163 return -EIO; 164 } 165 166 nic_data->datapath_caps = 167 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 168 169 /* record the DPCPU firmware IDs to determine VEB vswitching support. 170 */ 171 nic_data->rx_dpcpu_fw_id = 172 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 173 nic_data->tx_dpcpu_fw_id = 174 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 175 176 if (!(nic_data->datapath_caps & 177 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) { 178 netif_err(efx, drv, efx->net_dev, 179 "current firmware does not support TSO\n"); 180 return -ENODEV; 181 } 182 183 if (!(nic_data->datapath_caps & 184 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 185 netif_err(efx, probe, efx->net_dev, 186 "current firmware does not support an RX prefix\n"); 187 return -ENODEV; 188 } 189 190 return 0; 191 } 192 193 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 194 { 195 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 196 int rc; 197 198 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 199 outbuf, sizeof(outbuf), NULL); 200 if (rc) 201 return rc; 202 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 203 return rc > 0 ? rc : -ERANGE; 204 } 205 206 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 207 { 208 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 209 size_t outlen; 210 int rc; 211 212 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 213 214 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 215 outbuf, sizeof(outbuf), &outlen); 216 if (rc) 217 return rc; 218 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 219 return -EIO; 220 221 ether_addr_copy(mac_address, 222 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 223 return 0; 224 } 225 226 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 227 { 228 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 229 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 230 size_t outlen; 231 int num_addrs, rc; 232 233 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 234 EVB_PORT_ID_ASSIGNED); 235 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 236 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 237 238 if (rc) 239 return rc; 240 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 241 return -EIO; 242 243 num_addrs = MCDI_DWORD(outbuf, 244 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 245 246 WARN_ON(num_addrs != 1); 247 248 ether_addr_copy(mac_address, 249 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 250 251 return 0; 252 } 253 254 static ssize_t efx_ef10_show_link_control_flag(struct device *dev, 255 struct device_attribute *attr, 256 char *buf) 257 { 258 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 259 260 return sprintf(buf, "%d\n", 261 ((efx->mcdi->fn_flags) & 262 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 263 ? 1 : 0); 264 } 265 266 static ssize_t efx_ef10_show_primary_flag(struct device *dev, 267 struct device_attribute *attr, 268 char *buf) 269 { 270 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 271 272 return sprintf(buf, "%d\n", 273 ((efx->mcdi->fn_flags) & 274 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 275 ? 1 : 0); 276 } 277 278 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag, 279 NULL); 280 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL); 281 282 static int efx_ef10_probe(struct efx_nic *efx) 283 { 284 struct efx_ef10_nic_data *nic_data; 285 struct net_device *net_dev = efx->net_dev; 286 int i, rc; 287 288 /* We can have one VI for each 8K region. However, until we 289 * use TX option descriptors we need two TX queues per channel. 290 */ 291 efx->max_channels = 292 min_t(unsigned int, 293 EFX_MAX_CHANNELS, 294 efx_ef10_mem_map_size(efx) / 295 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES)); 296 if (WARN_ON(efx->max_channels == 0)) 297 return -EIO; 298 299 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 300 if (!nic_data) 301 return -ENOMEM; 302 efx->nic_data = nic_data; 303 304 /* we assume later that we can copy from this buffer in dwords */ 305 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 306 307 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 308 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 309 if (rc) 310 goto fail1; 311 312 /* Get the MC's warm boot count. In case it's rebooting right 313 * now, be prepared to retry. 314 */ 315 i = 0; 316 for (;;) { 317 rc = efx_ef10_get_warm_boot_count(efx); 318 if (rc >= 0) 319 break; 320 if (++i == 5) 321 goto fail2; 322 ssleep(1); 323 } 324 nic_data->warm_boot_count = rc; 325 326 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 327 328 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 329 330 /* In case we're recovering from a crash (kexec), we want to 331 * cancel any outstanding request by the previous user of this 332 * function. We send a special message using the least 333 * significant bits of the 'high' (doorbell) register. 334 */ 335 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 336 337 rc = efx_mcdi_init(efx); 338 if (rc) 339 goto fail2; 340 341 /* Reset (most) configuration for this function */ 342 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 343 if (rc) 344 goto fail3; 345 346 /* Enable event logging */ 347 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 348 if (rc) 349 goto fail3; 350 351 rc = device_create_file(&efx->pci_dev->dev, 352 &dev_attr_link_control_flag); 353 if (rc) 354 goto fail3; 355 356 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 357 if (rc) 358 goto fail4; 359 360 rc = efx_ef10_get_pf_index(efx); 361 if (rc) 362 goto fail5; 363 364 rc = efx_ef10_init_datapath_caps(efx); 365 if (rc < 0) 366 goto fail5; 367 368 efx->rx_packet_len_offset = 369 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 370 371 rc = efx_mcdi_port_get_number(efx); 372 if (rc < 0) 373 goto fail5; 374 efx->port_num = rc; 375 net_dev->dev_port = rc; 376 377 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 378 if (rc) 379 goto fail5; 380 381 rc = efx_ef10_get_sysclk_freq(efx); 382 if (rc < 0) 383 goto fail5; 384 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */ 385 386 /* Check whether firmware supports bug 35388 workaround. 387 * First try to enable it, then if we get EPERM, just 388 * ask if it's already enabled 389 */ 390 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true); 391 if (rc == 0) { 392 nic_data->workaround_35388 = true; 393 } else if (rc == -EPERM) { 394 unsigned int enabled; 395 396 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled); 397 if (rc) 398 goto fail3; 399 nic_data->workaround_35388 = enabled & 400 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388; 401 } else if (rc != -ENOSYS && rc != -ENOENT) { 402 goto fail5; 403 } 404 netif_dbg(efx, probe, efx->net_dev, 405 "workaround for bug 35388 is %sabled\n", 406 nic_data->workaround_35388 ? "en" : "dis"); 407 408 rc = efx_mcdi_mon_probe(efx); 409 if (rc && rc != -EPERM) 410 goto fail5; 411 412 efx_ptp_probe(efx, NULL); 413 414 #ifdef CONFIG_SFC_SRIOV 415 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 416 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 417 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 418 419 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 420 } else 421 #endif 422 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 423 424 return 0; 425 426 fail5: 427 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 428 fail4: 429 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 430 fail3: 431 efx_mcdi_fini(efx); 432 fail2: 433 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 434 fail1: 435 kfree(nic_data); 436 efx->nic_data = NULL; 437 return rc; 438 } 439 440 static int efx_ef10_free_vis(struct efx_nic *efx) 441 { 442 MCDI_DECLARE_BUF_ERR(outbuf); 443 size_t outlen; 444 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, 445 outbuf, sizeof(outbuf), &outlen); 446 447 /* -EALREADY means nothing to free, so ignore */ 448 if (rc == -EALREADY) 449 rc = 0; 450 if (rc) 451 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, 452 rc); 453 return rc; 454 } 455 456 #ifdef EFX_USE_PIO 457 458 static void efx_ef10_free_piobufs(struct efx_nic *efx) 459 { 460 struct efx_ef10_nic_data *nic_data = efx->nic_data; 461 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 462 unsigned int i; 463 int rc; 464 465 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 466 467 for (i = 0; i < nic_data->n_piobufs; i++) { 468 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 469 nic_data->piobuf_handle[i]); 470 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 471 NULL, 0, NULL); 472 WARN_ON(rc); 473 } 474 475 nic_data->n_piobufs = 0; 476 } 477 478 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 479 { 480 struct efx_ef10_nic_data *nic_data = efx->nic_data; 481 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 482 unsigned int i; 483 size_t outlen; 484 int rc = 0; 485 486 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 487 488 for (i = 0; i < n; i++) { 489 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 490 outbuf, sizeof(outbuf), &outlen); 491 if (rc) 492 break; 493 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 494 rc = -EIO; 495 break; 496 } 497 nic_data->piobuf_handle[i] = 498 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 499 netif_dbg(efx, probe, efx->net_dev, 500 "allocated PIO buffer %u handle %x\n", i, 501 nic_data->piobuf_handle[i]); 502 } 503 504 nic_data->n_piobufs = i; 505 if (rc) 506 efx_ef10_free_piobufs(efx); 507 return rc; 508 } 509 510 static int efx_ef10_link_piobufs(struct efx_nic *efx) 511 { 512 struct efx_ef10_nic_data *nic_data = efx->nic_data; 513 _MCDI_DECLARE_BUF(inbuf, 514 max(MC_CMD_LINK_PIOBUF_IN_LEN, 515 MC_CMD_UNLINK_PIOBUF_IN_LEN)); 516 struct efx_channel *channel; 517 struct efx_tx_queue *tx_queue; 518 unsigned int offset, index; 519 int rc; 520 521 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 522 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 523 524 memset(inbuf, 0, sizeof(inbuf)); 525 526 /* Link a buffer to each VI in the write-combining mapping */ 527 for (index = 0; index < nic_data->n_piobufs; ++index) { 528 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 529 nic_data->piobuf_handle[index]); 530 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 531 nic_data->pio_write_vi_base + index); 532 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 533 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 534 NULL, 0, NULL); 535 if (rc) { 536 netif_err(efx, drv, efx->net_dev, 537 "failed to link VI %u to PIO buffer %u (%d)\n", 538 nic_data->pio_write_vi_base + index, index, 539 rc); 540 goto fail; 541 } 542 netif_dbg(efx, probe, efx->net_dev, 543 "linked VI %u to PIO buffer %u\n", 544 nic_data->pio_write_vi_base + index, index); 545 } 546 547 /* Link a buffer to each TX queue */ 548 efx_for_each_channel(channel, efx) { 549 efx_for_each_channel_tx_queue(tx_queue, channel) { 550 /* We assign the PIO buffers to queues in 551 * reverse order to allow for the following 552 * special case. 553 */ 554 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 555 tx_queue->channel->channel - 1) * 556 efx_piobuf_size); 557 index = offset / ER_DZ_TX_PIOBUF_SIZE; 558 offset = offset % ER_DZ_TX_PIOBUF_SIZE; 559 560 /* When the host page size is 4K, the first 561 * host page in the WC mapping may be within 562 * the same VI page as the last TX queue. We 563 * can only link one buffer to each VI. 564 */ 565 if (tx_queue->queue == nic_data->pio_write_vi_base) { 566 BUG_ON(index != 0); 567 rc = 0; 568 } else { 569 MCDI_SET_DWORD(inbuf, 570 LINK_PIOBUF_IN_PIOBUF_HANDLE, 571 nic_data->piobuf_handle[index]); 572 MCDI_SET_DWORD(inbuf, 573 LINK_PIOBUF_IN_TXQ_INSTANCE, 574 tx_queue->queue); 575 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 576 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 577 NULL, 0, NULL); 578 } 579 580 if (rc) { 581 /* This is non-fatal; the TX path just 582 * won't use PIO for this queue 583 */ 584 netif_err(efx, drv, efx->net_dev, 585 "failed to link VI %u to PIO buffer %u (%d)\n", 586 tx_queue->queue, index, rc); 587 tx_queue->piobuf = NULL; 588 } else { 589 tx_queue->piobuf = 590 nic_data->pio_write_base + 591 index * EFX_VI_PAGE_SIZE + offset; 592 tx_queue->piobuf_offset = offset; 593 netif_dbg(efx, probe, efx->net_dev, 594 "linked VI %u to PIO buffer %u offset %x addr %p\n", 595 tx_queue->queue, index, 596 tx_queue->piobuf_offset, 597 tx_queue->piobuf); 598 } 599 } 600 } 601 602 return 0; 603 604 fail: 605 while (index--) { 606 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 607 nic_data->pio_write_vi_base + index); 608 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 609 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 610 NULL, 0, NULL); 611 } 612 return rc; 613 } 614 615 #else /* !EFX_USE_PIO */ 616 617 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 618 { 619 return n == 0 ? 0 : -ENOBUFS; 620 } 621 622 static int efx_ef10_link_piobufs(struct efx_nic *efx) 623 { 624 return 0; 625 } 626 627 static void efx_ef10_free_piobufs(struct efx_nic *efx) 628 { 629 } 630 631 #endif /* EFX_USE_PIO */ 632 633 static void efx_ef10_remove(struct efx_nic *efx) 634 { 635 struct efx_ef10_nic_data *nic_data = efx->nic_data; 636 int rc; 637 638 #ifdef CONFIG_SFC_SRIOV 639 struct efx_ef10_nic_data *nic_data_pf; 640 struct pci_dev *pci_dev_pf; 641 struct efx_nic *efx_pf; 642 struct ef10_vf *vf; 643 644 if (efx->pci_dev->is_virtfn) { 645 pci_dev_pf = efx->pci_dev->physfn; 646 if (pci_dev_pf) { 647 efx_pf = pci_get_drvdata(pci_dev_pf); 648 nic_data_pf = efx_pf->nic_data; 649 vf = nic_data_pf->vf + nic_data->vf_index; 650 vf->efx = NULL; 651 } else 652 netif_info(efx, drv, efx->net_dev, 653 "Could not get the PF id from VF\n"); 654 } 655 #endif 656 657 efx_ptp_remove(efx); 658 659 efx_mcdi_mon_remove(efx); 660 661 efx_ef10_rx_free_indir_table(efx); 662 663 if (nic_data->wc_membase) 664 iounmap(nic_data->wc_membase); 665 666 rc = efx_ef10_free_vis(efx); 667 WARN_ON(rc != 0); 668 669 if (!nic_data->must_restore_piobufs) 670 efx_ef10_free_piobufs(efx); 671 672 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 673 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 674 675 efx_mcdi_fini(efx); 676 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 677 kfree(nic_data); 678 } 679 680 static int efx_ef10_probe_pf(struct efx_nic *efx) 681 { 682 return efx_ef10_probe(efx); 683 } 684 685 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 686 { 687 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 688 689 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 690 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 691 NULL, 0, NULL); 692 } 693 694 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 695 { 696 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 697 698 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 699 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 700 NULL, 0, NULL); 701 } 702 703 int efx_ef10_vport_add_mac(struct efx_nic *efx, 704 unsigned int port_id, u8 *mac) 705 { 706 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 707 708 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 709 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 710 711 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 712 sizeof(inbuf), NULL, 0, NULL); 713 } 714 715 int efx_ef10_vport_del_mac(struct efx_nic *efx, 716 unsigned int port_id, u8 *mac) 717 { 718 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 719 720 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 721 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 722 723 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 724 sizeof(inbuf), NULL, 0, NULL); 725 } 726 727 #ifdef CONFIG_SFC_SRIOV 728 static int efx_ef10_probe_vf(struct efx_nic *efx) 729 { 730 int rc; 731 struct pci_dev *pci_dev_pf; 732 733 /* If the parent PF has no VF data structure, it doesn't know about this 734 * VF so fail probe. The VF needs to be re-created. This can happen 735 * if the PF driver is unloaded while the VF is assigned to a guest. 736 */ 737 pci_dev_pf = efx->pci_dev->physfn; 738 if (pci_dev_pf) { 739 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 740 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 741 742 if (!nic_data_pf->vf) { 743 netif_info(efx, drv, efx->net_dev, 744 "The VF cannot link to its parent PF; " 745 "please destroy and re-create the VF\n"); 746 return -EBUSY; 747 } 748 } 749 750 rc = efx_ef10_probe(efx); 751 if (rc) 752 return rc; 753 754 rc = efx_ef10_get_vf_index(efx); 755 if (rc) 756 goto fail; 757 758 if (efx->pci_dev->is_virtfn) { 759 if (efx->pci_dev->physfn) { 760 struct efx_nic *efx_pf = 761 pci_get_drvdata(efx->pci_dev->physfn); 762 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 763 struct efx_ef10_nic_data *nic_data = efx->nic_data; 764 765 nic_data_p->vf[nic_data->vf_index].efx = efx; 766 nic_data_p->vf[nic_data->vf_index].pci_dev = 767 efx->pci_dev; 768 } else 769 netif_info(efx, drv, efx->net_dev, 770 "Could not get the PF id from VF\n"); 771 } 772 773 return 0; 774 775 fail: 776 efx_ef10_remove(efx); 777 return rc; 778 } 779 #else 780 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 781 { 782 return 0; 783 } 784 #endif 785 786 static int efx_ef10_alloc_vis(struct efx_nic *efx, 787 unsigned int min_vis, unsigned int max_vis) 788 { 789 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); 790 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); 791 struct efx_ef10_nic_data *nic_data = efx->nic_data; 792 size_t outlen; 793 int rc; 794 795 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); 796 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); 797 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), 798 outbuf, sizeof(outbuf), &outlen); 799 if (rc != 0) 800 return rc; 801 802 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) 803 return -EIO; 804 805 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", 806 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); 807 808 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); 809 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); 810 return 0; 811 } 812 813 /* Note that the failure path of this function does not free 814 * resources, as this will be done by efx_ef10_remove(). 815 */ 816 static int efx_ef10_dimension_resources(struct efx_nic *efx) 817 { 818 struct efx_ef10_nic_data *nic_data = efx->nic_data; 819 unsigned int uc_mem_map_size, wc_mem_map_size; 820 unsigned int min_vis, pio_write_vi_base, max_vis; 821 void __iomem *membase; 822 int rc; 823 824 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); 825 826 #ifdef EFX_USE_PIO 827 /* Try to allocate PIO buffers if wanted and if the full 828 * number of PIO buffers would be sufficient to allocate one 829 * copy-buffer per TX channel. Failure is non-fatal, as there 830 * are only a small number of PIO buffers shared between all 831 * functions of the controller. 832 */ 833 if (efx_piobuf_size != 0 && 834 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 835 efx->n_tx_channels) { 836 unsigned int n_piobufs = 837 DIV_ROUND_UP(efx->n_tx_channels, 838 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size); 839 840 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 841 if (rc) 842 netif_err(efx, probe, efx->net_dev, 843 "failed to allocate PIO buffers (%d)\n", rc); 844 else 845 netif_dbg(efx, probe, efx->net_dev, 846 "allocated %u PIO buffers\n", n_piobufs); 847 } 848 #else 849 nic_data->n_piobufs = 0; 850 #endif 851 852 /* PIO buffers should be mapped with write-combining enabled, 853 * and we want to make single UC and WC mappings rather than 854 * several of each (in fact that's the only option if host 855 * page size is >4K). So we may allocate some extra VIs just 856 * for writing PIO buffers through. 857 * 858 * The UC mapping contains (min_vis - 1) complete VIs and the 859 * first half of the next VI. Then the WC mapping begins with 860 * the second half of this last VI. 861 */ 862 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE + 863 ER_DZ_TX_PIOBUF); 864 if (nic_data->n_piobufs) { 865 /* pio_write_vi_base rounds down to give the number of complete 866 * VIs inside the UC mapping. 867 */ 868 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; 869 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 870 nic_data->n_piobufs) * 871 EFX_VI_PAGE_SIZE) - 872 uc_mem_map_size); 873 max_vis = pio_write_vi_base + nic_data->n_piobufs; 874 } else { 875 pio_write_vi_base = 0; 876 wc_mem_map_size = 0; 877 max_vis = min_vis; 878 } 879 880 /* In case the last attached driver failed to free VIs, do it now */ 881 rc = efx_ef10_free_vis(efx); 882 if (rc != 0) 883 return rc; 884 885 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 886 if (rc != 0) 887 return rc; 888 889 /* If we didn't get enough VIs to map all the PIO buffers, free the 890 * PIO buffers 891 */ 892 if (nic_data->n_piobufs && 893 nic_data->n_allocated_vis < 894 pio_write_vi_base + nic_data->n_piobufs) { 895 netif_dbg(efx, probe, efx->net_dev, 896 "%u VIs are not sufficient to map %u PIO buffers\n", 897 nic_data->n_allocated_vis, nic_data->n_piobufs); 898 efx_ef10_free_piobufs(efx); 899 } 900 901 /* Shrink the original UC mapping of the memory BAR */ 902 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); 903 if (!membase) { 904 netif_err(efx, probe, efx->net_dev, 905 "could not shrink memory BAR to %x\n", 906 uc_mem_map_size); 907 return -ENOMEM; 908 } 909 iounmap(efx->membase); 910 efx->membase = membase; 911 912 /* Set up the WC mapping if needed */ 913 if (wc_mem_map_size) { 914 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 915 uc_mem_map_size, 916 wc_mem_map_size); 917 if (!nic_data->wc_membase) { 918 netif_err(efx, probe, efx->net_dev, 919 "could not allocate WC mapping of size %x\n", 920 wc_mem_map_size); 921 return -ENOMEM; 922 } 923 nic_data->pio_write_vi_base = pio_write_vi_base; 924 nic_data->pio_write_base = 925 nic_data->wc_membase + 926 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF - 927 uc_mem_map_size); 928 929 rc = efx_ef10_link_piobufs(efx); 930 if (rc) 931 efx_ef10_free_piobufs(efx); 932 } 933 934 netif_dbg(efx, probe, efx->net_dev, 935 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 936 &efx->membase_phys, efx->membase, uc_mem_map_size, 937 nic_data->wc_membase, wc_mem_map_size); 938 939 return 0; 940 } 941 942 static int efx_ef10_init_nic(struct efx_nic *efx) 943 { 944 struct efx_ef10_nic_data *nic_data = efx->nic_data; 945 int rc; 946 947 if (nic_data->must_check_datapath_caps) { 948 rc = efx_ef10_init_datapath_caps(efx); 949 if (rc) 950 return rc; 951 nic_data->must_check_datapath_caps = false; 952 } 953 954 if (nic_data->must_realloc_vis) { 955 /* We cannot let the number of VIs change now */ 956 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 957 nic_data->n_allocated_vis); 958 if (rc) 959 return rc; 960 nic_data->must_realloc_vis = false; 961 } 962 963 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 964 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 965 if (rc == 0) { 966 rc = efx_ef10_link_piobufs(efx); 967 if (rc) 968 efx_ef10_free_piobufs(efx); 969 } 970 971 /* Log an error on failure, but this is non-fatal */ 972 if (rc) 973 netif_err(efx, drv, efx->net_dev, 974 "failed to restore PIO buffers (%d)\n", rc); 975 nic_data->must_restore_piobufs = false; 976 } 977 978 /* don't fail init if RSS setup doesn't work */ 979 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table); 980 981 return 0; 982 } 983 984 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx) 985 { 986 struct efx_ef10_nic_data *nic_data = efx->nic_data; 987 988 /* All our allocations have been reset */ 989 nic_data->must_realloc_vis = true; 990 nic_data->must_restore_filters = true; 991 nic_data->must_restore_piobufs = true; 992 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 993 } 994 995 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 996 { 997 if (reason == RESET_TYPE_MC_FAILURE) 998 return RESET_TYPE_DATAPATH; 999 1000 return efx_mcdi_map_reset_reason(reason); 1001 } 1002 1003 static int efx_ef10_map_reset_flags(u32 *flags) 1004 { 1005 enum { 1006 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1007 ETH_RESET_SHARED_SHIFT), 1008 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1009 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1010 ETH_RESET_PHY | ETH_RESET_MGMT) << 1011 ETH_RESET_SHARED_SHIFT) 1012 }; 1013 1014 /* We assume for now that our PCI function is permitted to 1015 * reset everything. 1016 */ 1017 1018 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1019 *flags &= ~EF10_RESET_MC; 1020 return RESET_TYPE_WORLD; 1021 } 1022 1023 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1024 *flags &= ~EF10_RESET_PORT; 1025 return RESET_TYPE_ALL; 1026 } 1027 1028 /* no invisible reset implemented */ 1029 1030 return -EINVAL; 1031 } 1032 1033 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1034 { 1035 int rc = efx_mcdi_reset(efx, reset_type); 1036 1037 /* If it was a port reset, trigger reallocation of MC resources. 1038 * Note that on an MC reset nothing needs to be done now because we'll 1039 * detect the MC reset later and handle it then. 1040 * For an FLR, we never get an MC reset event, but the MC has reset all 1041 * resources assigned to us, so we have to trigger reallocation now. 1042 */ 1043 if ((reset_type == RESET_TYPE_ALL || 1044 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1045 efx_ef10_reset_mc_allocations(efx); 1046 return rc; 1047 } 1048 1049 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1050 [EF10_STAT_ ## ext_name] = \ 1051 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1052 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1053 [EF10_STAT_ ## int_name] = \ 1054 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1055 #define EF10_OTHER_STAT(ext_name) \ 1056 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1057 #define GENERIC_SW_STAT(ext_name) \ 1058 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1059 1060 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1061 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1062 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1063 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1064 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1065 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1066 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1067 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1068 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1069 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1070 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1071 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1072 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1073 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1074 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1075 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1076 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1077 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1078 EF10_OTHER_STAT(port_rx_good_bytes), 1079 EF10_OTHER_STAT(port_rx_bad_bytes), 1080 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1081 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1082 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1083 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1084 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1085 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1086 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1087 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1088 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1089 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1090 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1091 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1092 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1093 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1094 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1095 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1096 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1097 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1098 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1099 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1100 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1101 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1102 GENERIC_SW_STAT(rx_nodesc_trunc), 1103 GENERIC_SW_STAT(rx_noskb_drops), 1104 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1105 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1106 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1107 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1108 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1109 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1110 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1111 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1112 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1113 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1114 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1115 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1116 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1117 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1118 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1119 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1120 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1121 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1122 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1123 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1124 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1125 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1126 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1127 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1128 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1129 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1130 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1131 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1132 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1133 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1134 }; 1135 1136 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1137 (1ULL << EF10_STAT_port_tx_packets) | \ 1138 (1ULL << EF10_STAT_port_tx_pause) | \ 1139 (1ULL << EF10_STAT_port_tx_unicast) | \ 1140 (1ULL << EF10_STAT_port_tx_multicast) | \ 1141 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1142 (1ULL << EF10_STAT_port_rx_bytes) | \ 1143 (1ULL << \ 1144 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1145 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1146 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1147 (1ULL << EF10_STAT_port_rx_packets) | \ 1148 (1ULL << EF10_STAT_port_rx_good) | \ 1149 (1ULL << EF10_STAT_port_rx_bad) | \ 1150 (1ULL << EF10_STAT_port_rx_pause) | \ 1151 (1ULL << EF10_STAT_port_rx_control) | \ 1152 (1ULL << EF10_STAT_port_rx_unicast) | \ 1153 (1ULL << EF10_STAT_port_rx_multicast) | \ 1154 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1155 (1ULL << EF10_STAT_port_rx_lt64) | \ 1156 (1ULL << EF10_STAT_port_rx_64) | \ 1157 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1158 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1159 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1160 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1161 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1162 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1163 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1164 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1165 (1ULL << EF10_STAT_port_rx_overflow) | \ 1166 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1167 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1168 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1169 1170 /* These statistics are only provided by the 10G MAC. For a 10G/40G 1171 * switchable port we do not expose these because they might not 1172 * include all the packets they should. 1173 */ 1174 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1175 (1ULL << EF10_STAT_port_tx_lt64) | \ 1176 (1ULL << EF10_STAT_port_tx_64) | \ 1177 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1178 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1179 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1180 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1181 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1182 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1183 1184 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1185 * switchable port we do expose these because the errors will otherwise 1186 * be silent. 1187 */ 1188 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1189 (1ULL << EF10_STAT_port_rx_length_error)) 1190 1191 /* These statistics are only provided if the firmware supports the 1192 * capability PM_AND_RXDP_COUNTERS. 1193 */ 1194 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1195 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1196 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1197 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1198 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1199 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1200 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1201 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1202 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1203 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1204 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1205 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1206 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1207 1208 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1209 { 1210 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1211 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1212 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1213 1214 if (!(efx->mcdi->fn_flags & 1215 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1216 return 0; 1217 1218 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) 1219 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1220 else 1221 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1222 1223 if (nic_data->datapath_caps & 1224 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1225 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1226 1227 return raw_mask; 1228 } 1229 1230 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1231 { 1232 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1233 u64 raw_mask[2]; 1234 1235 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1236 1237 /* Only show vadaptor stats when EVB capability is present */ 1238 if (nic_data->datapath_caps & 1239 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1240 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1241 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1; 1242 } else { 1243 raw_mask[1] = 0; 1244 } 1245 1246 #if BITS_PER_LONG == 64 1247 mask[0] = raw_mask[0]; 1248 mask[1] = raw_mask[1]; 1249 #else 1250 mask[0] = raw_mask[0] & 0xffffffff; 1251 mask[1] = raw_mask[0] >> 32; 1252 mask[2] = raw_mask[1] & 0xffffffff; 1253 mask[3] = raw_mask[1] >> 32; 1254 #endif 1255 } 1256 1257 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1258 { 1259 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1260 1261 efx_ef10_get_stat_mask(efx, mask); 1262 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1263 mask, names); 1264 } 1265 1266 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1267 struct rtnl_link_stats64 *core_stats) 1268 { 1269 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1270 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1271 u64 *stats = nic_data->stats; 1272 size_t stats_count = 0, index; 1273 1274 efx_ef10_get_stat_mask(efx, mask); 1275 1276 if (full_stats) { 1277 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1278 if (efx_ef10_stat_desc[index].name) { 1279 *full_stats++ = stats[index]; 1280 ++stats_count; 1281 } 1282 } 1283 } 1284 1285 if (core_stats) { 1286 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1287 stats[EF10_STAT_rx_multicast] + 1288 stats[EF10_STAT_rx_broadcast]; 1289 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1290 stats[EF10_STAT_tx_multicast] + 1291 stats[EF10_STAT_tx_broadcast]; 1292 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1293 stats[EF10_STAT_rx_multicast_bytes] + 1294 stats[EF10_STAT_rx_broadcast_bytes]; 1295 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1296 stats[EF10_STAT_tx_multicast_bytes] + 1297 stats[EF10_STAT_tx_broadcast_bytes]; 1298 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1299 stats[GENERIC_STAT_rx_noskb_drops]; 1300 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1301 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1302 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1303 core_stats->rx_errors = core_stats->rx_crc_errors; 1304 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1305 } 1306 1307 return stats_count; 1308 } 1309 1310 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx) 1311 { 1312 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1313 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1314 __le64 generation_start, generation_end; 1315 u64 *stats = nic_data->stats; 1316 __le64 *dma_stats; 1317 1318 efx_ef10_get_stat_mask(efx, mask); 1319 1320 dma_stats = efx->stats_buffer.addr; 1321 nic_data = efx->nic_data; 1322 1323 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1324 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 1325 return 0; 1326 rmb(); 1327 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1328 stats, efx->stats_buffer.addr, false); 1329 rmb(); 1330 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1331 if (generation_end != generation_start) 1332 return -EAGAIN; 1333 1334 /* Update derived statistics */ 1335 efx_nic_fix_nodesc_drop_stat(efx, 1336 &stats[EF10_STAT_port_rx_nodesc_drops]); 1337 stats[EF10_STAT_port_rx_good_bytes] = 1338 stats[EF10_STAT_port_rx_bytes] - 1339 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1340 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1341 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1342 efx_update_sw_stats(efx, stats); 1343 return 0; 1344 } 1345 1346 1347 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1348 struct rtnl_link_stats64 *core_stats) 1349 { 1350 int retry; 1351 1352 /* If we're unlucky enough to read statistics during the DMA, wait 1353 * up to 10ms for it to finish (typically takes <500us) 1354 */ 1355 for (retry = 0; retry < 100; ++retry) { 1356 if (efx_ef10_try_update_nic_stats_pf(efx) == 0) 1357 break; 1358 udelay(100); 1359 } 1360 1361 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1362 } 1363 1364 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1365 { 1366 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1367 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1368 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1369 __le64 generation_start, generation_end; 1370 u64 *stats = nic_data->stats; 1371 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64); 1372 struct efx_buffer stats_buf; 1373 __le64 *dma_stats; 1374 int rc; 1375 1376 spin_unlock_bh(&efx->stats_lock); 1377 1378 if (in_interrupt()) { 1379 /* If in atomic context, cannot update stats. Just update the 1380 * software stats and return so the caller can continue. 1381 */ 1382 spin_lock_bh(&efx->stats_lock); 1383 efx_update_sw_stats(efx, stats); 1384 return 0; 1385 } 1386 1387 efx_ef10_get_stat_mask(efx, mask); 1388 1389 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC); 1390 if (rc) { 1391 spin_lock_bh(&efx->stats_lock); 1392 return rc; 1393 } 1394 1395 dma_stats = stats_buf.addr; 1396 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID; 1397 1398 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1399 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1400 MAC_STATS_IN_DMA, 1); 1401 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1402 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1403 1404 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1405 NULL, 0, NULL); 1406 spin_lock_bh(&efx->stats_lock); 1407 if (rc) { 1408 /* Expect ENOENT if DMA queues have not been set up */ 1409 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1410 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1411 sizeof(inbuf), NULL, 0, rc); 1412 goto out; 1413 } 1414 1415 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1416 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1417 WARN_ON_ONCE(1); 1418 goto out; 1419 } 1420 rmb(); 1421 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1422 stats, stats_buf.addr, false); 1423 rmb(); 1424 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1425 if (generation_end != generation_start) { 1426 rc = -EAGAIN; 1427 goto out; 1428 } 1429 1430 efx_update_sw_stats(efx, stats); 1431 out: 1432 efx_nic_free_buffer(efx, &stats_buf); 1433 return rc; 1434 } 1435 1436 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1437 struct rtnl_link_stats64 *core_stats) 1438 { 1439 if (efx_ef10_try_update_nic_stats_vf(efx)) 1440 return 0; 1441 1442 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1443 } 1444 1445 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1446 { 1447 struct efx_nic *efx = channel->efx; 1448 unsigned int mode, value; 1449 efx_dword_t timer_cmd; 1450 1451 if (channel->irq_moderation) { 1452 mode = 3; 1453 value = channel->irq_moderation - 1; 1454 } else { 1455 mode = 0; 1456 value = 0; 1457 } 1458 1459 if (EFX_EF10_WORKAROUND_35388(efx)) { 1460 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1461 EFE_DD_EVQ_IND_TIMER_FLAGS, 1462 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1463 ERF_DD_EVQ_IND_TIMER_VAL, value); 1464 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1465 channel->channel); 1466 } else { 1467 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1468 ERF_DZ_TC_TIMER_VAL, value); 1469 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1470 channel->channel); 1471 } 1472 } 1473 1474 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 1475 struct ethtool_wolinfo *wol) {} 1476 1477 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 1478 { 1479 return -EOPNOTSUPP; 1480 } 1481 1482 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1483 { 1484 wol->supported = 0; 1485 wol->wolopts = 0; 1486 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1487 } 1488 1489 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 1490 { 1491 if (type != 0) 1492 return -EINVAL; 1493 return 0; 1494 } 1495 1496 static void efx_ef10_mcdi_request(struct efx_nic *efx, 1497 const efx_dword_t *hdr, size_t hdr_len, 1498 const efx_dword_t *sdu, size_t sdu_len) 1499 { 1500 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1501 u8 *pdu = nic_data->mcdi_buf.addr; 1502 1503 memcpy(pdu, hdr, hdr_len); 1504 memcpy(pdu + hdr_len, sdu, sdu_len); 1505 wmb(); 1506 1507 /* The hardware provides 'low' and 'high' (doorbell) registers 1508 * for passing the 64-bit address of an MCDI request to 1509 * firmware. However the dwords are swapped by firmware. The 1510 * least significant bits of the doorbell are then 0 for all 1511 * MCDI requests due to alignment. 1512 */ 1513 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 1514 ER_DZ_MC_DB_LWRD); 1515 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 1516 ER_DZ_MC_DB_HWRD); 1517 } 1518 1519 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 1520 { 1521 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1522 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 1523 1524 rmb(); 1525 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 1526 } 1527 1528 static void 1529 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 1530 size_t offset, size_t outlen) 1531 { 1532 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1533 const u8 *pdu = nic_data->mcdi_buf.addr; 1534 1535 memcpy(outbuf, pdu + offset, outlen); 1536 } 1537 1538 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 1539 { 1540 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1541 int rc; 1542 1543 rc = efx_ef10_get_warm_boot_count(efx); 1544 if (rc < 0) { 1545 /* The firmware is presumably in the process of 1546 * rebooting. However, we are supposed to report each 1547 * reboot just once, so we must only do that once we 1548 * can read and store the updated warm boot count. 1549 */ 1550 return 0; 1551 } 1552 1553 if (rc == nic_data->warm_boot_count) 1554 return 0; 1555 1556 nic_data->warm_boot_count = rc; 1557 1558 /* All our allocations have been reset */ 1559 efx_ef10_reset_mc_allocations(efx); 1560 1561 /* Driver-created vswitches and vports must be re-created */ 1562 nic_data->must_probe_vswitching = true; 1563 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 1564 1565 /* The datapath firmware might have been changed */ 1566 nic_data->must_check_datapath_caps = true; 1567 1568 /* MAC statistics have been cleared on the NIC; clear the local 1569 * statistic that we update with efx_update_diff_stat(). 1570 */ 1571 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 1572 1573 return -EIO; 1574 } 1575 1576 /* Handle an MSI interrupt 1577 * 1578 * Handle an MSI hardware interrupt. This routine schedules event 1579 * queue processing. No interrupt acknowledgement cycle is necessary. 1580 * Also, we never need to check that the interrupt is for us, since 1581 * MSI interrupts cannot be shared. 1582 */ 1583 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 1584 { 1585 struct efx_msi_context *context = dev_id; 1586 struct efx_nic *efx = context->efx; 1587 1588 netif_vdbg(efx, intr, efx->net_dev, 1589 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 1590 1591 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) { 1592 /* Note test interrupts */ 1593 if (context->index == efx->irq_level) 1594 efx->last_irq_cpu = raw_smp_processor_id(); 1595 1596 /* Schedule processing of the channel */ 1597 efx_schedule_channel_irq(efx->channel[context->index]); 1598 } 1599 1600 return IRQ_HANDLED; 1601 } 1602 1603 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 1604 { 1605 struct efx_nic *efx = dev_id; 1606 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); 1607 struct efx_channel *channel; 1608 efx_dword_t reg; 1609 u32 queues; 1610 1611 /* Read the ISR which also ACKs the interrupts */ 1612 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 1613 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 1614 1615 if (queues == 0) 1616 return IRQ_NONE; 1617 1618 if (likely(soft_enabled)) { 1619 /* Note test interrupts */ 1620 if (queues & (1U << efx->irq_level)) 1621 efx->last_irq_cpu = raw_smp_processor_id(); 1622 1623 efx_for_each_channel(channel, efx) { 1624 if (queues & 1) 1625 efx_schedule_channel_irq(channel); 1626 queues >>= 1; 1627 } 1628 } 1629 1630 netif_vdbg(efx, intr, efx->net_dev, 1631 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 1632 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 1633 1634 return IRQ_HANDLED; 1635 } 1636 1637 static void efx_ef10_irq_test_generate(struct efx_nic *efx) 1638 { 1639 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 1640 1641 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 1642 1643 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 1644 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 1645 inbuf, sizeof(inbuf), NULL, 0, NULL); 1646 } 1647 1648 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 1649 { 1650 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 1651 (tx_queue->ptr_mask + 1) * 1652 sizeof(efx_qword_t), 1653 GFP_KERNEL); 1654 } 1655 1656 /* This writes to the TX_DESC_WPTR and also pushes data */ 1657 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 1658 const efx_qword_t *txd) 1659 { 1660 unsigned int write_ptr; 1661 efx_oword_t reg; 1662 1663 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1664 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 1665 reg.qword[0] = *txd; 1666 efx_writeo_page(tx_queue->efx, ®, 1667 ER_DZ_TX_DESC_UPD, tx_queue->queue); 1668 } 1669 1670 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 1671 { 1672 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 1673 EFX_BUF_SIZE)); 1674 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 1675 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; 1676 struct efx_channel *channel = tx_queue->channel; 1677 struct efx_nic *efx = tx_queue->efx; 1678 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1679 size_t inlen; 1680 dma_addr_t dma_addr; 1681 efx_qword_t *txd; 1682 int rc; 1683 int i; 1684 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0); 1685 1686 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); 1687 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); 1688 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); 1689 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); 1690 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS, 1691 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, 1692 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload); 1693 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); 1694 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id); 1695 1696 dma_addr = tx_queue->txd.buf.dma_addr; 1697 1698 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", 1699 tx_queue->queue, entries, (u64)dma_addr); 1700 1701 for (i = 0; i < entries; ++i) { 1702 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); 1703 dma_addr += EFX_BUF_SIZE; 1704 } 1705 1706 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); 1707 1708 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen, 1709 NULL, 0, NULL); 1710 if (rc) 1711 goto fail; 1712 1713 /* A previous user of this TX queue might have set us up the 1714 * bomb by writing a descriptor to the TX push collector but 1715 * not the doorbell. (Each collector belongs to a port, not a 1716 * queue or function, so cannot easily be reset.) We must 1717 * attempt to push a no-op descriptor in its place. 1718 */ 1719 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 1720 tx_queue->insert_count = 1; 1721 txd = efx_tx_desc(tx_queue, 0); 1722 EFX_POPULATE_QWORD_4(*txd, 1723 ESF_DZ_TX_DESC_IS_OPT, true, 1724 ESF_DZ_TX_OPTION_TYPE, 1725 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 1726 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 1727 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload); 1728 tx_queue->write_count = 1; 1729 wmb(); 1730 efx_ef10_push_tx_desc(tx_queue, txd); 1731 1732 return; 1733 1734 fail: 1735 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 1736 tx_queue->queue); 1737 } 1738 1739 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue) 1740 { 1741 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); 1742 MCDI_DECLARE_BUF_ERR(outbuf); 1743 struct efx_nic *efx = tx_queue->efx; 1744 size_t outlen; 1745 int rc; 1746 1747 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, 1748 tx_queue->queue); 1749 1750 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), 1751 outbuf, sizeof(outbuf), &outlen); 1752 1753 if (rc && rc != -EALREADY) 1754 goto fail; 1755 1756 return; 1757 1758 fail: 1759 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, 1760 outbuf, outlen, rc); 1761 } 1762 1763 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue) 1764 { 1765 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); 1766 } 1767 1768 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 1769 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 1770 { 1771 unsigned int write_ptr; 1772 efx_dword_t reg; 1773 1774 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1775 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 1776 efx_writed_page(tx_queue->efx, ®, 1777 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 1778 } 1779 1780 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 1781 { 1782 unsigned int old_write_count = tx_queue->write_count; 1783 struct efx_tx_buffer *buffer; 1784 unsigned int write_ptr; 1785 efx_qword_t *txd; 1786 1787 BUG_ON(tx_queue->write_count == tx_queue->insert_count); 1788 1789 do { 1790 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1791 buffer = &tx_queue->buffer[write_ptr]; 1792 txd = efx_tx_desc(tx_queue, write_ptr); 1793 ++tx_queue->write_count; 1794 1795 /* Create TX descriptor ring entry */ 1796 if (buffer->flags & EFX_TX_BUF_OPTION) { 1797 *txd = buffer->option; 1798 } else { 1799 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 1800 EFX_POPULATE_QWORD_3( 1801 *txd, 1802 ESF_DZ_TX_KER_CONT, 1803 buffer->flags & EFX_TX_BUF_CONT, 1804 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 1805 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 1806 } 1807 } while (tx_queue->write_count != tx_queue->insert_count); 1808 1809 wmb(); /* Ensure descriptors are written before they are fetched */ 1810 1811 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 1812 txd = efx_tx_desc(tx_queue, 1813 old_write_count & tx_queue->ptr_mask); 1814 efx_ef10_push_tx_desc(tx_queue, txd); 1815 ++tx_queue->pushes; 1816 } else { 1817 efx_ef10_notify_tx_desc(tx_queue); 1818 } 1819 } 1820 1821 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context, 1822 bool exclusive, unsigned *context_size) 1823 { 1824 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN); 1825 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN); 1826 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1827 size_t outlen; 1828 int rc; 1829 u32 alloc_type = exclusive ? 1830 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE : 1831 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED; 1832 unsigned rss_spread = exclusive ? 1833 efx->rss_spread : 1834 min(rounddown_pow_of_two(efx->rss_spread), 1835 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE); 1836 1837 if (!exclusive && rss_spread == 1) { 1838 *context = EFX_EF10_RSS_CONTEXT_INVALID; 1839 if (context_size) 1840 *context_size = 1; 1841 return 0; 1842 } 1843 1844 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, 1845 nic_data->vport_id); 1846 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type); 1847 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread); 1848 1849 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf), 1850 outbuf, sizeof(outbuf), &outlen); 1851 if (rc != 0) 1852 return rc; 1853 1854 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) 1855 return -EIO; 1856 1857 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); 1858 1859 if (context_size) 1860 *context_size = rss_spread; 1861 1862 return 0; 1863 } 1864 1865 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context) 1866 { 1867 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN); 1868 int rc; 1869 1870 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, 1871 context); 1872 1873 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf), 1874 NULL, 0, NULL); 1875 WARN_ON(rc != 0); 1876 } 1877 1878 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context, 1879 const u32 *rx_indir_table) 1880 { 1881 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN); 1882 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN); 1883 int i, rc; 1884 1885 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, 1886 context); 1887 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != 1888 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN); 1889 1890 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i) 1891 MCDI_PTR(tablebuf, 1892 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] = 1893 (u8) rx_indir_table[i]; 1894 1895 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf, 1896 sizeof(tablebuf), NULL, 0, NULL); 1897 if (rc != 0) 1898 return rc; 1899 1900 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, 1901 context); 1902 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) != 1903 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); 1904 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i) 1905 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = 1906 efx->rx_hash_key[i]; 1907 1908 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf, 1909 sizeof(keybuf), NULL, 0, NULL); 1910 } 1911 1912 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx) 1913 { 1914 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1915 1916 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 1917 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context); 1918 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 1919 } 1920 1921 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx, 1922 unsigned *context_size) 1923 { 1924 u32 new_rx_rss_context; 1925 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1926 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 1927 false, context_size); 1928 1929 if (rc != 0) 1930 return rc; 1931 1932 nic_data->rx_rss_context = new_rx_rss_context; 1933 nic_data->rx_rss_context_exclusive = false; 1934 efx_set_default_rx_indir_table(efx); 1935 return 0; 1936 } 1937 1938 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx, 1939 const u32 *rx_indir_table) 1940 { 1941 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1942 int rc; 1943 u32 new_rx_rss_context; 1944 1945 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID || 1946 !nic_data->rx_rss_context_exclusive) { 1947 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 1948 true, NULL); 1949 if (rc == -EOPNOTSUPP) 1950 return rc; 1951 else if (rc != 0) 1952 goto fail1; 1953 } else { 1954 new_rx_rss_context = nic_data->rx_rss_context; 1955 } 1956 1957 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context, 1958 rx_indir_table); 1959 if (rc != 0) 1960 goto fail2; 1961 1962 if (nic_data->rx_rss_context != new_rx_rss_context) 1963 efx_ef10_rx_free_indir_table(efx); 1964 nic_data->rx_rss_context = new_rx_rss_context; 1965 nic_data->rx_rss_context_exclusive = true; 1966 if (rx_indir_table != efx->rx_indir_table) 1967 memcpy(efx->rx_indir_table, rx_indir_table, 1968 sizeof(efx->rx_indir_table)); 1969 return 0; 1970 1971 fail2: 1972 if (new_rx_rss_context != nic_data->rx_rss_context) 1973 efx_ef10_free_rss_context(efx, new_rx_rss_context); 1974 fail1: 1975 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 1976 return rc; 1977 } 1978 1979 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user, 1980 const u32 *rx_indir_table) 1981 { 1982 int rc; 1983 1984 if (efx->rss_spread == 1) 1985 return 0; 1986 1987 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table); 1988 1989 if (rc == -ENOBUFS && !user) { 1990 unsigned context_size; 1991 bool mismatch = false; 1992 size_t i; 1993 1994 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch; 1995 i++) 1996 mismatch = rx_indir_table[i] != 1997 ethtool_rxfh_indir_default(i, efx->rss_spread); 1998 1999 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size); 2000 if (rc == 0) { 2001 if (context_size != efx->rss_spread) 2002 netif_warn(efx, probe, efx->net_dev, 2003 "Could not allocate an exclusive RSS" 2004 " context; allocated a shared one of" 2005 " different size." 2006 " Wanted %u, got %u.\n", 2007 efx->rss_spread, context_size); 2008 else if (mismatch) 2009 netif_warn(efx, probe, efx->net_dev, 2010 "Could not allocate an exclusive RSS" 2011 " context; allocated a shared one but" 2012 " could not apply custom" 2013 " indirection.\n"); 2014 else 2015 netif_info(efx, probe, efx->net_dev, 2016 "Could not allocate an exclusive RSS" 2017 " context; allocated a shared one.\n"); 2018 } 2019 } 2020 return rc; 2021 } 2022 2023 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user, 2024 const u32 *rx_indir_table 2025 __attribute__ ((unused))) 2026 { 2027 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2028 2029 if (user) 2030 return -EOPNOTSUPP; 2031 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 2032 return 0; 2033 return efx_ef10_rx_push_shared_rss_config(efx, NULL); 2034 } 2035 2036 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue) 2037 { 2038 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, 2039 (rx_queue->ptr_mask + 1) * 2040 sizeof(efx_qword_t), 2041 GFP_KERNEL); 2042 } 2043 2044 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue) 2045 { 2046 MCDI_DECLARE_BUF(inbuf, 2047 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 2048 EFX_BUF_SIZE)); 2049 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2050 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; 2051 struct efx_nic *efx = rx_queue->efx; 2052 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2053 size_t inlen; 2054 dma_addr_t dma_addr; 2055 int rc; 2056 int i; 2057 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0); 2058 2059 rx_queue->scatter_n = 0; 2060 rx_queue->scatter_len = 0; 2061 2062 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); 2063 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); 2064 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); 2065 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, 2066 efx_rx_queue_index(rx_queue)); 2067 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, 2068 INIT_RXQ_IN_FLAG_PREFIX, 1, 2069 INIT_RXQ_IN_FLAG_TIMESTAMP, 1); 2070 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); 2071 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id); 2072 2073 dma_addr = rx_queue->rxd.buf.dma_addr; 2074 2075 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", 2076 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); 2077 2078 for (i = 0; i < entries; ++i) { 2079 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); 2080 dma_addr += EFX_BUF_SIZE; 2081 } 2082 2083 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); 2084 2085 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, 2086 NULL, 0, NULL); 2087 if (rc) 2088 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", 2089 efx_rx_queue_index(rx_queue)); 2090 } 2091 2092 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue) 2093 { 2094 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); 2095 MCDI_DECLARE_BUF_ERR(outbuf); 2096 struct efx_nic *efx = rx_queue->efx; 2097 size_t outlen; 2098 int rc; 2099 2100 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, 2101 efx_rx_queue_index(rx_queue)); 2102 2103 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), 2104 outbuf, sizeof(outbuf), &outlen); 2105 2106 if (rc && rc != -EALREADY) 2107 goto fail; 2108 2109 return; 2110 2111 fail: 2112 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, 2113 outbuf, outlen, rc); 2114 } 2115 2116 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue) 2117 { 2118 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); 2119 } 2120 2121 /* This creates an entry in the RX descriptor queue */ 2122 static inline void 2123 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2124 { 2125 struct efx_rx_buffer *rx_buf; 2126 efx_qword_t *rxd; 2127 2128 rxd = efx_rx_desc(rx_queue, index); 2129 rx_buf = efx_rx_buffer(rx_queue, index); 2130 EFX_POPULATE_QWORD_2(*rxd, 2131 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2132 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2133 } 2134 2135 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2136 { 2137 struct efx_nic *efx = rx_queue->efx; 2138 unsigned int write_count; 2139 efx_dword_t reg; 2140 2141 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2142 write_count = rx_queue->added_count & ~7; 2143 if (rx_queue->notified_count == write_count) 2144 return; 2145 2146 do 2147 efx_ef10_build_rx_desc( 2148 rx_queue, 2149 rx_queue->notified_count & rx_queue->ptr_mask); 2150 while (++rx_queue->notified_count != write_count); 2151 2152 wmb(); 2153 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2154 write_count & rx_queue->ptr_mask); 2155 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2156 efx_rx_queue_index(rx_queue)); 2157 } 2158 2159 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2160 2161 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2162 { 2163 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2164 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2165 efx_qword_t event; 2166 2167 EFX_POPULATE_QWORD_2(event, 2168 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2169 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2170 2171 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2172 2173 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2174 * already swapped the data to little-endian order. 2175 */ 2176 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2177 sizeof(efx_qword_t)); 2178 2179 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2180 inbuf, sizeof(inbuf), 0, 2181 efx_ef10_rx_defer_refill_complete, 0); 2182 } 2183 2184 static void 2185 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2186 int rc, efx_dword_t *outbuf, 2187 size_t outlen_actual) 2188 { 2189 /* nothing to do */ 2190 } 2191 2192 static int efx_ef10_ev_probe(struct efx_channel *channel) 2193 { 2194 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 2195 (channel->eventq_mask + 1) * 2196 sizeof(efx_qword_t), 2197 GFP_KERNEL); 2198 } 2199 2200 static int efx_ef10_ev_init(struct efx_channel *channel) 2201 { 2202 MCDI_DECLARE_BUF(inbuf, 2203 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / 2204 EFX_BUF_SIZE)); 2205 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN); 2206 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; 2207 struct efx_nic *efx = channel->efx; 2208 struct efx_ef10_nic_data *nic_data; 2209 bool supports_rx_merge; 2210 size_t inlen, outlen; 2211 dma_addr_t dma_addr; 2212 int rc; 2213 int i; 2214 2215 nic_data = efx->nic_data; 2216 supports_rx_merge = 2217 !!(nic_data->datapath_caps & 2218 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2219 2220 /* Fill event queue with all ones (i.e. empty events) */ 2221 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); 2222 2223 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); 2224 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); 2225 /* INIT_EVQ expects index in vector table, not absolute */ 2226 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); 2227 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, 2228 INIT_EVQ_IN_FLAG_INTERRUPTING, 1, 2229 INIT_EVQ_IN_FLAG_RX_MERGE, 1, 2230 INIT_EVQ_IN_FLAG_TX_MERGE, 1, 2231 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge); 2232 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, 2233 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); 2234 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); 2235 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); 2236 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, 2237 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); 2238 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); 2239 2240 dma_addr = channel->eventq.buf.dma_addr; 2241 for (i = 0; i < entries; ++i) { 2242 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); 2243 dma_addr += EFX_BUF_SIZE; 2244 } 2245 2246 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); 2247 2248 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, 2249 outbuf, sizeof(outbuf), &outlen); 2250 /* IRQ return is ignored */ 2251 return rc; 2252 } 2253 2254 static void efx_ef10_ev_fini(struct efx_channel *channel) 2255 { 2256 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); 2257 MCDI_DECLARE_BUF_ERR(outbuf); 2258 struct efx_nic *efx = channel->efx; 2259 size_t outlen; 2260 int rc; 2261 2262 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); 2263 2264 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), 2265 outbuf, sizeof(outbuf), &outlen); 2266 2267 if (rc && rc != -EALREADY) 2268 goto fail; 2269 2270 return; 2271 2272 fail: 2273 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, 2274 outbuf, outlen, rc); 2275 } 2276 2277 static void efx_ef10_ev_remove(struct efx_channel *channel) 2278 { 2279 efx_nic_free_buffer(channel->efx, &channel->eventq.buf); 2280 } 2281 2282 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2283 unsigned int rx_queue_label) 2284 { 2285 struct efx_nic *efx = rx_queue->efx; 2286 2287 netif_info(efx, hw, efx->net_dev, 2288 "rx event arrived on queue %d labeled as queue %u\n", 2289 efx_rx_queue_index(rx_queue), rx_queue_label); 2290 2291 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2292 } 2293 2294 static void 2295 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2296 unsigned int actual, unsigned int expected) 2297 { 2298 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2299 struct efx_nic *efx = rx_queue->efx; 2300 2301 netif_info(efx, hw, efx->net_dev, 2302 "dropped %d events (index=%d expected=%d)\n", 2303 dropped, actual, expected); 2304 2305 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2306 } 2307 2308 /* partially received RX was aborted. clean up. */ 2309 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2310 { 2311 unsigned int rx_desc_ptr; 2312 2313 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2314 "scattered RX aborted (dropping %u buffers)\n", 2315 rx_queue->scatter_n); 2316 2317 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2318 2319 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2320 0, EFX_RX_PKT_DISCARD); 2321 2322 rx_queue->removed_count += rx_queue->scatter_n; 2323 rx_queue->scatter_n = 0; 2324 rx_queue->scatter_len = 0; 2325 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2326 } 2327 2328 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2329 const efx_qword_t *event) 2330 { 2331 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class; 2332 unsigned int n_descs, n_packets, i; 2333 struct efx_nic *efx = channel->efx; 2334 struct efx_rx_queue *rx_queue; 2335 bool rx_cont; 2336 u16 flags = 0; 2337 2338 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 2339 return 0; 2340 2341 /* Basic packet information */ 2342 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2343 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2344 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2345 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); 2346 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2347 2348 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2349 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2350 EFX_QWORD_FMT "\n", 2351 EFX_QWORD_VAL(*event)); 2352 2353 rx_queue = efx_channel_get_rx_queue(channel); 2354 2355 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2356 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2357 2358 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2359 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2360 2361 if (n_descs != rx_queue->scatter_n + 1) { 2362 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2363 2364 /* detect rx abort */ 2365 if (unlikely(n_descs == rx_queue->scatter_n)) { 2366 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2367 netdev_WARN(efx->net_dev, 2368 "invalid RX abort: scatter_n=%u event=" 2369 EFX_QWORD_FMT "\n", 2370 rx_queue->scatter_n, 2371 EFX_QWORD_VAL(*event)); 2372 efx_ef10_handle_rx_abort(rx_queue); 2373 return 0; 2374 } 2375 2376 /* Check that RX completion merging is valid, i.e. 2377 * the current firmware supports it and this is a 2378 * non-scattered packet. 2379 */ 2380 if (!(nic_data->datapath_caps & 2381 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2382 rx_queue->scatter_n != 0 || rx_cont) { 2383 efx_ef10_handle_rx_bad_lbits( 2384 rx_queue, next_ptr_lbits, 2385 (rx_queue->removed_count + 2386 rx_queue->scatter_n + 1) & 2387 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2388 return 0; 2389 } 2390 2391 /* Merged completion for multiple non-scattered packets */ 2392 rx_queue->scatter_n = 1; 2393 rx_queue->scatter_len = 0; 2394 n_packets = n_descs; 2395 ++channel->n_rx_merge_events; 2396 channel->n_rx_merge_packets += n_packets; 2397 flags |= EFX_RX_PKT_PREFIX_LEN; 2398 } else { 2399 ++rx_queue->scatter_n; 2400 rx_queue->scatter_len += rx_bytes; 2401 if (rx_cont) 2402 return 0; 2403 n_packets = 1; 2404 } 2405 2406 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR))) 2407 flags |= EFX_RX_PKT_DISCARD; 2408 2409 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) { 2410 channel->n_rx_ip_hdr_chksum_err += n_packets; 2411 } else if (unlikely(EFX_QWORD_FIELD(*event, 2412 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) { 2413 channel->n_rx_tcp_udp_chksum_err += n_packets; 2414 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP || 2415 rx_l4_class == ESE_DZ_L4_CLASS_UDP) { 2416 flags |= EFX_RX_PKT_CSUMMED; 2417 } 2418 2419 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) 2420 flags |= EFX_RX_PKT_TCP; 2421 2422 channel->irq_mod_score += 2 * n_packets; 2423 2424 /* Handle received packet(s) */ 2425 for (i = 0; i < n_packets; i++) { 2426 efx_rx_packet(rx_queue, 2427 rx_queue->removed_count & rx_queue->ptr_mask, 2428 rx_queue->scatter_n, rx_queue->scatter_len, 2429 flags); 2430 rx_queue->removed_count += rx_queue->scatter_n; 2431 } 2432 2433 rx_queue->scatter_n = 0; 2434 rx_queue->scatter_len = 0; 2435 2436 return n_packets; 2437 } 2438 2439 static int 2440 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2441 { 2442 struct efx_nic *efx = channel->efx; 2443 struct efx_tx_queue *tx_queue; 2444 unsigned int tx_ev_desc_ptr; 2445 unsigned int tx_ev_q_label; 2446 int tx_descs = 0; 2447 2448 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 2449 return 0; 2450 2451 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2452 return 0; 2453 2454 /* Transmit completion */ 2455 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2456 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2457 tx_queue = efx_channel_get_tx_queue(channel, 2458 tx_ev_q_label % EFX_TXQ_TYPES); 2459 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) & 2460 tx_queue->ptr_mask); 2461 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2462 2463 return tx_descs; 2464 } 2465 2466 static void 2467 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 2468 { 2469 struct efx_nic *efx = channel->efx; 2470 int subcode; 2471 2472 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 2473 2474 switch (subcode) { 2475 case ESE_DZ_DRV_TIMER_EV: 2476 case ESE_DZ_DRV_WAKE_UP_EV: 2477 break; 2478 case ESE_DZ_DRV_START_UP_EV: 2479 /* event queue init complete. ok. */ 2480 break; 2481 default: 2482 netif_err(efx, hw, efx->net_dev, 2483 "channel %d unknown driver event type %d" 2484 " (data " EFX_QWORD_FMT ")\n", 2485 channel->channel, subcode, 2486 EFX_QWORD_VAL(*event)); 2487 2488 } 2489 } 2490 2491 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 2492 efx_qword_t *event) 2493 { 2494 struct efx_nic *efx = channel->efx; 2495 u32 subcode; 2496 2497 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 2498 2499 switch (subcode) { 2500 case EFX_EF10_TEST: 2501 channel->event_test_cpu = raw_smp_processor_id(); 2502 break; 2503 case EFX_EF10_REFILL: 2504 /* The queue must be empty, so we won't receive any rx 2505 * events, so efx_process_channel() won't refill the 2506 * queue. Refill it here 2507 */ 2508 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 2509 break; 2510 default: 2511 netif_err(efx, hw, efx->net_dev, 2512 "channel %d unknown driver event type %u" 2513 " (data " EFX_QWORD_FMT ")\n", 2514 channel->channel, (unsigned) subcode, 2515 EFX_QWORD_VAL(*event)); 2516 } 2517 } 2518 2519 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 2520 { 2521 struct efx_nic *efx = channel->efx; 2522 efx_qword_t event, *p_event; 2523 unsigned int read_ptr; 2524 int ev_code; 2525 int tx_descs = 0; 2526 int spent = 0; 2527 2528 if (quota <= 0) 2529 return spent; 2530 2531 read_ptr = channel->eventq_read_ptr; 2532 2533 for (;;) { 2534 p_event = efx_event(channel, read_ptr); 2535 event = *p_event; 2536 2537 if (!efx_event_present(&event)) 2538 break; 2539 2540 EFX_SET_QWORD(*p_event); 2541 2542 ++read_ptr; 2543 2544 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 2545 2546 netif_vdbg(efx, drv, efx->net_dev, 2547 "processing event on %d " EFX_QWORD_FMT "\n", 2548 channel->channel, EFX_QWORD_VAL(event)); 2549 2550 switch (ev_code) { 2551 case ESE_DZ_EV_CODE_MCDI_EV: 2552 efx_mcdi_process_event(channel, &event); 2553 break; 2554 case ESE_DZ_EV_CODE_RX_EV: 2555 spent += efx_ef10_handle_rx_event(channel, &event); 2556 if (spent >= quota) { 2557 /* XXX can we split a merged event to 2558 * avoid going over-quota? 2559 */ 2560 spent = quota; 2561 goto out; 2562 } 2563 break; 2564 case ESE_DZ_EV_CODE_TX_EV: 2565 tx_descs += efx_ef10_handle_tx_event(channel, &event); 2566 if (tx_descs > efx->txq_entries) { 2567 spent = quota; 2568 goto out; 2569 } else if (++spent == quota) { 2570 goto out; 2571 } 2572 break; 2573 case ESE_DZ_EV_CODE_DRIVER_EV: 2574 efx_ef10_handle_driver_event(channel, &event); 2575 if (++spent == quota) 2576 goto out; 2577 break; 2578 case EFX_EF10_DRVGEN_EV: 2579 efx_ef10_handle_driver_generated_event(channel, &event); 2580 break; 2581 default: 2582 netif_err(efx, hw, efx->net_dev, 2583 "channel %d unknown event type %d" 2584 " (data " EFX_QWORD_FMT ")\n", 2585 channel->channel, ev_code, 2586 EFX_QWORD_VAL(event)); 2587 } 2588 } 2589 2590 out: 2591 channel->eventq_read_ptr = read_ptr; 2592 return spent; 2593 } 2594 2595 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 2596 { 2597 struct efx_nic *efx = channel->efx; 2598 efx_dword_t rptr; 2599 2600 if (EFX_EF10_WORKAROUND_35388(efx)) { 2601 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 2602 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 2603 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 2604 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 2605 2606 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2607 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 2608 ERF_DD_EVQ_IND_RPTR, 2609 (channel->eventq_read_ptr & 2610 channel->eventq_mask) >> 2611 ERF_DD_EVQ_IND_RPTR_WIDTH); 2612 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2613 channel->channel); 2614 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2615 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 2616 ERF_DD_EVQ_IND_RPTR, 2617 channel->eventq_read_ptr & 2618 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 2619 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2620 channel->channel); 2621 } else { 2622 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 2623 channel->eventq_read_ptr & 2624 channel->eventq_mask); 2625 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 2626 } 2627 } 2628 2629 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 2630 { 2631 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2632 struct efx_nic *efx = channel->efx; 2633 efx_qword_t event; 2634 int rc; 2635 2636 EFX_POPULATE_QWORD_2(event, 2637 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2638 ESF_DZ_EV_DATA, EFX_EF10_TEST); 2639 2640 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2641 2642 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2643 * already swapped the data to little-endian order. 2644 */ 2645 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2646 sizeof(efx_qword_t)); 2647 2648 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 2649 NULL, 0, NULL); 2650 if (rc != 0) 2651 goto fail; 2652 2653 return; 2654 2655 fail: 2656 WARN_ON(true); 2657 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 2658 } 2659 2660 void efx_ef10_handle_drain_event(struct efx_nic *efx) 2661 { 2662 if (atomic_dec_and_test(&efx->active_queues)) 2663 wake_up(&efx->flush_wq); 2664 2665 WARN_ON(atomic_read(&efx->active_queues) < 0); 2666 } 2667 2668 static int efx_ef10_fini_dmaq(struct efx_nic *efx) 2669 { 2670 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2671 struct efx_channel *channel; 2672 struct efx_tx_queue *tx_queue; 2673 struct efx_rx_queue *rx_queue; 2674 int pending; 2675 2676 /* If the MC has just rebooted, the TX/RX queues will have already been 2677 * torn down, but efx->active_queues needs to be set to zero. 2678 */ 2679 if (nic_data->must_realloc_vis) { 2680 atomic_set(&efx->active_queues, 0); 2681 return 0; 2682 } 2683 2684 /* Do not attempt to write to the NIC during EEH recovery */ 2685 if (efx->state != STATE_RECOVERY) { 2686 efx_for_each_channel(channel, efx) { 2687 efx_for_each_channel_rx_queue(rx_queue, channel) 2688 efx_ef10_rx_fini(rx_queue); 2689 efx_for_each_channel_tx_queue(tx_queue, channel) 2690 efx_ef10_tx_fini(tx_queue); 2691 } 2692 2693 wait_event_timeout(efx->flush_wq, 2694 atomic_read(&efx->active_queues) == 0, 2695 msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); 2696 pending = atomic_read(&efx->active_queues); 2697 if (pending) { 2698 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", 2699 pending); 2700 return -ETIMEDOUT; 2701 } 2702 } 2703 2704 return 0; 2705 } 2706 2707 static void efx_ef10_prepare_flr(struct efx_nic *efx) 2708 { 2709 atomic_set(&efx->active_queues, 0); 2710 } 2711 2712 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left, 2713 const struct efx_filter_spec *right) 2714 { 2715 if ((left->match_flags ^ right->match_flags) | 2716 ((left->flags ^ right->flags) & 2717 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX))) 2718 return false; 2719 2720 return memcmp(&left->outer_vid, &right->outer_vid, 2721 sizeof(struct efx_filter_spec) - 2722 offsetof(struct efx_filter_spec, outer_vid)) == 0; 2723 } 2724 2725 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec) 2726 { 2727 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3); 2728 return jhash2((const u32 *)&spec->outer_vid, 2729 (sizeof(struct efx_filter_spec) - 2730 offsetof(struct efx_filter_spec, outer_vid)) / 4, 2731 0); 2732 /* XXX should we randomise the initval? */ 2733 } 2734 2735 /* Decide whether a filter should be exclusive or else should allow 2736 * delivery to additional recipients. Currently we decide that 2737 * filters for specific local unicast MAC and IP addresses are 2738 * exclusive. 2739 */ 2740 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec) 2741 { 2742 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC && 2743 !is_multicast_ether_addr(spec->loc_mac)) 2744 return true; 2745 2746 if ((spec->match_flags & 2747 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == 2748 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { 2749 if (spec->ether_type == htons(ETH_P_IP) && 2750 !ipv4_is_multicast(spec->loc_host[0])) 2751 return true; 2752 if (spec->ether_type == htons(ETH_P_IPV6) && 2753 ((const u8 *)spec->loc_host)[0] != 0xff) 2754 return true; 2755 } 2756 2757 return false; 2758 } 2759 2760 static struct efx_filter_spec * 2761 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table, 2762 unsigned int filter_idx) 2763 { 2764 return (struct efx_filter_spec *)(table->entry[filter_idx].spec & 2765 ~EFX_EF10_FILTER_FLAGS); 2766 } 2767 2768 static unsigned int 2769 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table, 2770 unsigned int filter_idx) 2771 { 2772 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS; 2773 } 2774 2775 static void 2776 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table, 2777 unsigned int filter_idx, 2778 const struct efx_filter_spec *spec, 2779 unsigned int flags) 2780 { 2781 table->entry[filter_idx].spec = (unsigned long)spec | flags; 2782 } 2783 2784 static void efx_ef10_filter_push_prep(struct efx_nic *efx, 2785 const struct efx_filter_spec *spec, 2786 efx_dword_t *inbuf, u64 handle, 2787 bool replacing) 2788 { 2789 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2790 2791 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN); 2792 2793 if (replacing) { 2794 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2795 MC_CMD_FILTER_OP_IN_OP_REPLACE); 2796 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle); 2797 } else { 2798 u32 match_fields = 0; 2799 2800 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2801 efx_ef10_filter_is_exclusive(spec) ? 2802 MC_CMD_FILTER_OP_IN_OP_INSERT : 2803 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE); 2804 2805 /* Convert match flags and values. Unlike almost 2806 * everything else in MCDI, these fields are in 2807 * network byte order. 2808 */ 2809 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) 2810 match_fields |= 2811 is_multicast_ether_addr(spec->loc_mac) ? 2812 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN : 2813 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; 2814 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \ 2815 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \ 2816 match_fields |= \ 2817 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 2818 mcdi_field ## _LBN; \ 2819 BUILD_BUG_ON( \ 2820 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \ 2821 sizeof(spec->gen_field)); \ 2822 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \ 2823 &spec->gen_field, sizeof(spec->gen_field)); \ 2824 } 2825 COPY_FIELD(REM_HOST, rem_host, SRC_IP); 2826 COPY_FIELD(LOC_HOST, loc_host, DST_IP); 2827 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC); 2828 COPY_FIELD(REM_PORT, rem_port, SRC_PORT); 2829 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC); 2830 COPY_FIELD(LOC_PORT, loc_port, DST_PORT); 2831 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE); 2832 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN); 2833 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN); 2834 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO); 2835 #undef COPY_FIELD 2836 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS, 2837 match_fields); 2838 } 2839 2840 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id); 2841 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST, 2842 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2843 MC_CMD_FILTER_OP_IN_RX_DEST_DROP : 2844 MC_CMD_FILTER_OP_IN_RX_DEST_HOST); 2845 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0); 2846 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST, 2847 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); 2848 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, 2849 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2850 0 : spec->dmaq_id); 2851 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE, 2852 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ? 2853 MC_CMD_FILTER_OP_IN_RX_MODE_RSS : 2854 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); 2855 if (spec->flags & EFX_FILTER_FLAG_RX_RSS) 2856 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, 2857 spec->rss_context != 2858 EFX_FILTER_RSS_CONTEXT_DEFAULT ? 2859 spec->rss_context : nic_data->rx_rss_context); 2860 } 2861 2862 static int efx_ef10_filter_push(struct efx_nic *efx, 2863 const struct efx_filter_spec *spec, 2864 u64 *handle, bool replacing) 2865 { 2866 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 2867 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN); 2868 int rc; 2869 2870 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing); 2871 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 2872 outbuf, sizeof(outbuf), NULL); 2873 if (rc == 0) 2874 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 2875 if (rc == -ENOSPC) 2876 rc = -EBUSY; /* to match efx_farch_filter_insert() */ 2877 return rc; 2878 } 2879 2880 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table, 2881 enum efx_filter_match_flags match_flags) 2882 { 2883 unsigned int match_pri; 2884 2885 for (match_pri = 0; 2886 match_pri < table->rx_match_count; 2887 match_pri++) 2888 if (table->rx_match_flags[match_pri] == match_flags) 2889 return match_pri; 2890 2891 return -EPROTONOSUPPORT; 2892 } 2893 2894 static s32 efx_ef10_filter_insert(struct efx_nic *efx, 2895 struct efx_filter_spec *spec, 2896 bool replace_equal) 2897 { 2898 struct efx_ef10_filter_table *table = efx->filter_state; 2899 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 2900 struct efx_filter_spec *saved_spec; 2901 unsigned int match_pri, hash; 2902 unsigned int priv_flags; 2903 bool replacing = false; 2904 int ins_index = -1; 2905 DEFINE_WAIT(wait); 2906 bool is_mc_recip; 2907 s32 rc; 2908 2909 /* For now, only support RX filters */ 2910 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) != 2911 EFX_FILTER_FLAG_RX) 2912 return -EINVAL; 2913 2914 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags); 2915 if (rc < 0) 2916 return rc; 2917 match_pri = rc; 2918 2919 hash = efx_ef10_filter_hash(spec); 2920 is_mc_recip = efx_filter_is_mc_recipient(spec); 2921 if (is_mc_recip) 2922 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 2923 2924 /* Find any existing filters with the same match tuple or 2925 * else a free slot to insert at. If any of them are busy, 2926 * we have to wait and retry. 2927 */ 2928 for (;;) { 2929 unsigned int depth = 1; 2930 unsigned int i; 2931 2932 spin_lock_bh(&efx->filter_lock); 2933 2934 for (;;) { 2935 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 2936 saved_spec = efx_ef10_filter_entry_spec(table, i); 2937 2938 if (!saved_spec) { 2939 if (ins_index < 0) 2940 ins_index = i; 2941 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 2942 if (table->entry[i].spec & 2943 EFX_EF10_FILTER_FLAG_BUSY) 2944 break; 2945 if (spec->priority < saved_spec->priority && 2946 spec->priority != EFX_FILTER_PRI_AUTO) { 2947 rc = -EPERM; 2948 goto out_unlock; 2949 } 2950 if (!is_mc_recip) { 2951 /* This is the only one */ 2952 if (spec->priority == 2953 saved_spec->priority && 2954 !replace_equal) { 2955 rc = -EEXIST; 2956 goto out_unlock; 2957 } 2958 ins_index = i; 2959 goto found; 2960 } else if (spec->priority > 2961 saved_spec->priority || 2962 (spec->priority == 2963 saved_spec->priority && 2964 replace_equal)) { 2965 if (ins_index < 0) 2966 ins_index = i; 2967 else 2968 __set_bit(depth, mc_rem_map); 2969 } 2970 } 2971 2972 /* Once we reach the maximum search depth, use 2973 * the first suitable slot or return -EBUSY if 2974 * there was none 2975 */ 2976 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 2977 if (ins_index < 0) { 2978 rc = -EBUSY; 2979 goto out_unlock; 2980 } 2981 goto found; 2982 } 2983 2984 ++depth; 2985 } 2986 2987 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 2988 spin_unlock_bh(&efx->filter_lock); 2989 schedule(); 2990 } 2991 2992 found: 2993 /* Create a software table entry if necessary, and mark it 2994 * busy. We might yet fail to insert, but any attempt to 2995 * insert a conflicting filter while we're waiting for the 2996 * firmware must find the busy entry. 2997 */ 2998 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 2999 if (saved_spec) { 3000 if (spec->priority == EFX_FILTER_PRI_AUTO && 3001 saved_spec->priority >= EFX_FILTER_PRI_AUTO) { 3002 /* Just make sure it won't be removed */ 3003 if (saved_spec->priority > EFX_FILTER_PRI_AUTO) 3004 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; 3005 table->entry[ins_index].spec &= 3006 ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3007 rc = ins_index; 3008 goto out_unlock; 3009 } 3010 replacing = true; 3011 priv_flags = efx_ef10_filter_entry_flags(table, ins_index); 3012 } else { 3013 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 3014 if (!saved_spec) { 3015 rc = -ENOMEM; 3016 goto out_unlock; 3017 } 3018 *saved_spec = *spec; 3019 priv_flags = 0; 3020 } 3021 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 3022 priv_flags | EFX_EF10_FILTER_FLAG_BUSY); 3023 3024 /* Mark lower-priority multicast recipients busy prior to removal */ 3025 if (is_mc_recip) { 3026 unsigned int depth, i; 3027 3028 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3029 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3030 if (test_bit(depth, mc_rem_map)) 3031 table->entry[i].spec |= 3032 EFX_EF10_FILTER_FLAG_BUSY; 3033 } 3034 } 3035 3036 spin_unlock_bh(&efx->filter_lock); 3037 3038 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle, 3039 replacing); 3040 3041 /* Finalise the software table entry */ 3042 spin_lock_bh(&efx->filter_lock); 3043 if (rc == 0) { 3044 if (replacing) { 3045 /* Update the fields that may differ */ 3046 if (saved_spec->priority == EFX_FILTER_PRI_AUTO) 3047 saved_spec->flags |= 3048 EFX_FILTER_FLAG_RX_OVER_AUTO; 3049 saved_spec->priority = spec->priority; 3050 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO; 3051 saved_spec->flags |= spec->flags; 3052 saved_spec->rss_context = spec->rss_context; 3053 saved_spec->dmaq_id = spec->dmaq_id; 3054 } 3055 } else if (!replacing) { 3056 kfree(saved_spec); 3057 saved_spec = NULL; 3058 } 3059 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags); 3060 3061 /* Remove and finalise entries for lower-priority multicast 3062 * recipients 3063 */ 3064 if (is_mc_recip) { 3065 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3066 unsigned int depth, i; 3067 3068 memset(inbuf, 0, sizeof(inbuf)); 3069 3070 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3071 if (!test_bit(depth, mc_rem_map)) 3072 continue; 3073 3074 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3075 saved_spec = efx_ef10_filter_entry_spec(table, i); 3076 priv_flags = efx_ef10_filter_entry_flags(table, i); 3077 3078 if (rc == 0) { 3079 spin_unlock_bh(&efx->filter_lock); 3080 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3081 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3082 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3083 table->entry[i].handle); 3084 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3085 inbuf, sizeof(inbuf), 3086 NULL, 0, NULL); 3087 spin_lock_bh(&efx->filter_lock); 3088 } 3089 3090 if (rc == 0) { 3091 kfree(saved_spec); 3092 saved_spec = NULL; 3093 priv_flags = 0; 3094 } else { 3095 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY; 3096 } 3097 efx_ef10_filter_set_entry(table, i, saved_spec, 3098 priv_flags); 3099 } 3100 } 3101 3102 /* If successful, return the inserted filter ID */ 3103 if (rc == 0) 3104 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index; 3105 3106 wake_up_all(&table->waitq); 3107 out_unlock: 3108 spin_unlock_bh(&efx->filter_lock); 3109 finish_wait(&table->waitq, &wait); 3110 return rc; 3111 } 3112 3113 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx) 3114 { 3115 /* no need to do anything here on EF10 */ 3116 } 3117 3118 /* Remove a filter. 3119 * If !by_index, remove by ID 3120 * If by_index, remove by index 3121 * Filter ID may come from userland and must be range-checked. 3122 */ 3123 static int efx_ef10_filter_remove_internal(struct efx_nic *efx, 3124 unsigned int priority_mask, 3125 u32 filter_id, bool by_index) 3126 { 3127 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 3128 struct efx_ef10_filter_table *table = efx->filter_state; 3129 MCDI_DECLARE_BUF(inbuf, 3130 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 3131 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 3132 struct efx_filter_spec *spec; 3133 DEFINE_WAIT(wait); 3134 int rc; 3135 3136 /* Find the software table entry and mark it busy. Don't 3137 * remove it yet; any attempt to update while we're waiting 3138 * for the firmware must find the busy entry. 3139 */ 3140 for (;;) { 3141 spin_lock_bh(&efx->filter_lock); 3142 if (!(table->entry[filter_idx].spec & 3143 EFX_EF10_FILTER_FLAG_BUSY)) 3144 break; 3145 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 3146 spin_unlock_bh(&efx->filter_lock); 3147 schedule(); 3148 } 3149 3150 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3151 if (!spec || 3152 (!by_index && 3153 efx_ef10_filter_rx_match_pri(table, spec->match_flags) != 3154 filter_id / HUNT_FILTER_TBL_ROWS)) { 3155 rc = -ENOENT; 3156 goto out_unlock; 3157 } 3158 3159 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO && 3160 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) { 3161 /* Just remove flags */ 3162 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO; 3163 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3164 rc = 0; 3165 goto out_unlock; 3166 } 3167 3168 if (!(priority_mask & (1U << spec->priority))) { 3169 rc = -ENOENT; 3170 goto out_unlock; 3171 } 3172 3173 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3174 spin_unlock_bh(&efx->filter_lock); 3175 3176 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { 3177 /* Reset to an automatic filter */ 3178 3179 struct efx_filter_spec new_spec = *spec; 3180 3181 new_spec.priority = EFX_FILTER_PRI_AUTO; 3182 new_spec.flags = (EFX_FILTER_FLAG_RX | 3183 EFX_FILTER_FLAG_RX_RSS); 3184 new_spec.dmaq_id = 0; 3185 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT; 3186 rc = efx_ef10_filter_push(efx, &new_spec, 3187 &table->entry[filter_idx].handle, 3188 true); 3189 3190 spin_lock_bh(&efx->filter_lock); 3191 if (rc == 0) 3192 *spec = new_spec; 3193 } else { 3194 /* Really remove the filter */ 3195 3196 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3197 efx_ef10_filter_is_exclusive(spec) ? 3198 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3199 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3200 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3201 table->entry[filter_idx].handle); 3202 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3203 inbuf, sizeof(inbuf), NULL, 0, NULL); 3204 3205 spin_lock_bh(&efx->filter_lock); 3206 if (rc == 0) { 3207 kfree(spec); 3208 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3209 } 3210 } 3211 3212 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 3213 wake_up_all(&table->waitq); 3214 out_unlock: 3215 spin_unlock_bh(&efx->filter_lock); 3216 finish_wait(&table->waitq, &wait); 3217 return rc; 3218 } 3219 3220 static int efx_ef10_filter_remove_safe(struct efx_nic *efx, 3221 enum efx_filter_priority priority, 3222 u32 filter_id) 3223 { 3224 return efx_ef10_filter_remove_internal(efx, 1U << priority, 3225 filter_id, false); 3226 } 3227 3228 static int efx_ef10_filter_get_safe(struct efx_nic *efx, 3229 enum efx_filter_priority priority, 3230 u32 filter_id, struct efx_filter_spec *spec) 3231 { 3232 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 3233 struct efx_ef10_filter_table *table = efx->filter_state; 3234 const struct efx_filter_spec *saved_spec; 3235 int rc; 3236 3237 spin_lock_bh(&efx->filter_lock); 3238 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx); 3239 if (saved_spec && saved_spec->priority == priority && 3240 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) == 3241 filter_id / HUNT_FILTER_TBL_ROWS) { 3242 *spec = *saved_spec; 3243 rc = 0; 3244 } else { 3245 rc = -ENOENT; 3246 } 3247 spin_unlock_bh(&efx->filter_lock); 3248 return rc; 3249 } 3250 3251 static int efx_ef10_filter_clear_rx(struct efx_nic *efx, 3252 enum efx_filter_priority priority) 3253 { 3254 unsigned int priority_mask; 3255 unsigned int i; 3256 int rc; 3257 3258 priority_mask = (((1U << (priority + 1)) - 1) & 3259 ~(1U << EFX_FILTER_PRI_AUTO)); 3260 3261 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 3262 rc = efx_ef10_filter_remove_internal(efx, priority_mask, 3263 i, true); 3264 if (rc && rc != -ENOENT) 3265 return rc; 3266 } 3267 3268 return 0; 3269 } 3270 3271 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx, 3272 enum efx_filter_priority priority) 3273 { 3274 struct efx_ef10_filter_table *table = efx->filter_state; 3275 unsigned int filter_idx; 3276 s32 count = 0; 3277 3278 spin_lock_bh(&efx->filter_lock); 3279 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3280 if (table->entry[filter_idx].spec && 3281 efx_ef10_filter_entry_spec(table, filter_idx)->priority == 3282 priority) 3283 ++count; 3284 } 3285 spin_unlock_bh(&efx->filter_lock); 3286 return count; 3287 } 3288 3289 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx) 3290 { 3291 struct efx_ef10_filter_table *table = efx->filter_state; 3292 3293 return table->rx_match_count * HUNT_FILTER_TBL_ROWS; 3294 } 3295 3296 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx, 3297 enum efx_filter_priority priority, 3298 u32 *buf, u32 size) 3299 { 3300 struct efx_ef10_filter_table *table = efx->filter_state; 3301 struct efx_filter_spec *spec; 3302 unsigned int filter_idx; 3303 s32 count = 0; 3304 3305 spin_lock_bh(&efx->filter_lock); 3306 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3307 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3308 if (spec && spec->priority == priority) { 3309 if (count == size) { 3310 count = -EMSGSIZE; 3311 break; 3312 } 3313 buf[count++] = (efx_ef10_filter_rx_match_pri( 3314 table, spec->match_flags) * 3315 HUNT_FILTER_TBL_ROWS + 3316 filter_idx); 3317 } 3318 } 3319 spin_unlock_bh(&efx->filter_lock); 3320 return count; 3321 } 3322 3323 #ifdef CONFIG_RFS_ACCEL 3324 3325 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete; 3326 3327 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx, 3328 struct efx_filter_spec *spec) 3329 { 3330 struct efx_ef10_filter_table *table = efx->filter_state; 3331 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3332 struct efx_filter_spec *saved_spec; 3333 unsigned int hash, i, depth = 1; 3334 bool replacing = false; 3335 int ins_index = -1; 3336 u64 cookie; 3337 s32 rc; 3338 3339 /* Must be an RX filter without RSS and not for a multicast 3340 * destination address (RFS only works for connected sockets). 3341 * These restrictions allow us to pass only a tiny amount of 3342 * data through to the completion function. 3343 */ 3344 EFX_WARN_ON_PARANOID(spec->flags != 3345 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER)); 3346 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT); 3347 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec)); 3348 3349 hash = efx_ef10_filter_hash(spec); 3350 3351 spin_lock_bh(&efx->filter_lock); 3352 3353 /* Find any existing filter with the same match tuple or else 3354 * a free slot to insert at. If an existing filter is busy, 3355 * we have to give up. 3356 */ 3357 for (;;) { 3358 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3359 saved_spec = efx_ef10_filter_entry_spec(table, i); 3360 3361 if (!saved_spec) { 3362 if (ins_index < 0) 3363 ins_index = i; 3364 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 3365 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) { 3366 rc = -EBUSY; 3367 goto fail_unlock; 3368 } 3369 if (spec->priority < saved_spec->priority) { 3370 rc = -EPERM; 3371 goto fail_unlock; 3372 } 3373 ins_index = i; 3374 break; 3375 } 3376 3377 /* Once we reach the maximum search depth, use the 3378 * first suitable slot or return -EBUSY if there was 3379 * none 3380 */ 3381 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 3382 if (ins_index < 0) { 3383 rc = -EBUSY; 3384 goto fail_unlock; 3385 } 3386 break; 3387 } 3388 3389 ++depth; 3390 } 3391 3392 /* Create a software table entry if necessary, and mark it 3393 * busy. We might yet fail to insert, but any attempt to 3394 * insert a conflicting filter while we're waiting for the 3395 * firmware must find the busy entry. 3396 */ 3397 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 3398 if (saved_spec) { 3399 replacing = true; 3400 } else { 3401 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 3402 if (!saved_spec) { 3403 rc = -ENOMEM; 3404 goto fail_unlock; 3405 } 3406 *saved_spec = *spec; 3407 } 3408 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 3409 EFX_EF10_FILTER_FLAG_BUSY); 3410 3411 spin_unlock_bh(&efx->filter_lock); 3412 3413 /* Pack up the variables needed on completion */ 3414 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id; 3415 3416 efx_ef10_filter_push_prep(efx, spec, inbuf, 3417 table->entry[ins_index].handle, replacing); 3418 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3419 MC_CMD_FILTER_OP_OUT_LEN, 3420 efx_ef10_filter_rfs_insert_complete, cookie); 3421 3422 return ins_index; 3423 3424 fail_unlock: 3425 spin_unlock_bh(&efx->filter_lock); 3426 return rc; 3427 } 3428 3429 static void 3430 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie, 3431 int rc, efx_dword_t *outbuf, 3432 size_t outlen_actual) 3433 { 3434 struct efx_ef10_filter_table *table = efx->filter_state; 3435 unsigned int ins_index, dmaq_id; 3436 struct efx_filter_spec *spec; 3437 bool replacing; 3438 3439 /* Unpack the cookie */ 3440 replacing = cookie >> 31; 3441 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1); 3442 dmaq_id = cookie & 0xffff; 3443 3444 spin_lock_bh(&efx->filter_lock); 3445 spec = efx_ef10_filter_entry_spec(table, ins_index); 3446 if (rc == 0) { 3447 table->entry[ins_index].handle = 3448 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 3449 if (replacing) 3450 spec->dmaq_id = dmaq_id; 3451 } else if (!replacing) { 3452 kfree(spec); 3453 spec = NULL; 3454 } 3455 efx_ef10_filter_set_entry(table, ins_index, spec, 0); 3456 spin_unlock_bh(&efx->filter_lock); 3457 3458 wake_up_all(&table->waitq); 3459 } 3460 3461 static void 3462 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 3463 unsigned long filter_idx, 3464 int rc, efx_dword_t *outbuf, 3465 size_t outlen_actual); 3466 3467 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, 3468 unsigned int filter_idx) 3469 { 3470 struct efx_ef10_filter_table *table = efx->filter_state; 3471 struct efx_filter_spec *spec = 3472 efx_ef10_filter_entry_spec(table, filter_idx); 3473 MCDI_DECLARE_BUF(inbuf, 3474 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 3475 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 3476 3477 if (!spec || 3478 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) || 3479 spec->priority != EFX_FILTER_PRI_HINT || 3480 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id, 3481 flow_id, filter_idx)) 3482 return false; 3483 3484 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3485 MC_CMD_FILTER_OP_IN_OP_REMOVE); 3486 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3487 table->entry[filter_idx].handle); 3488 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0, 3489 efx_ef10_filter_rfs_expire_complete, filter_idx)) 3490 return false; 3491 3492 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3493 return true; 3494 } 3495 3496 static void 3497 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 3498 unsigned long filter_idx, 3499 int rc, efx_dword_t *outbuf, 3500 size_t outlen_actual) 3501 { 3502 struct efx_ef10_filter_table *table = efx->filter_state; 3503 struct efx_filter_spec *spec = 3504 efx_ef10_filter_entry_spec(table, filter_idx); 3505 3506 spin_lock_bh(&efx->filter_lock); 3507 if (rc == 0) { 3508 kfree(spec); 3509 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3510 } 3511 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 3512 wake_up_all(&table->waitq); 3513 spin_unlock_bh(&efx->filter_lock); 3514 } 3515 3516 #endif /* CONFIG_RFS_ACCEL */ 3517 3518 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags) 3519 { 3520 int match_flags = 0; 3521 3522 #define MAP_FLAG(gen_flag, mcdi_field) { \ 3523 u32 old_mcdi_flags = mcdi_flags; \ 3524 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 3525 mcdi_field ## _LBN); \ 3526 if (mcdi_flags != old_mcdi_flags) \ 3527 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \ 3528 } 3529 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST); 3530 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST); 3531 MAP_FLAG(REM_HOST, SRC_IP); 3532 MAP_FLAG(LOC_HOST, DST_IP); 3533 MAP_FLAG(REM_MAC, SRC_MAC); 3534 MAP_FLAG(REM_PORT, SRC_PORT); 3535 MAP_FLAG(LOC_MAC, DST_MAC); 3536 MAP_FLAG(LOC_PORT, DST_PORT); 3537 MAP_FLAG(ETHER_TYPE, ETHER_TYPE); 3538 MAP_FLAG(INNER_VID, INNER_VLAN); 3539 MAP_FLAG(OUTER_VID, OUTER_VLAN); 3540 MAP_FLAG(IP_PROTO, IP_PROTO); 3541 #undef MAP_FLAG 3542 3543 /* Did we map them all? */ 3544 if (mcdi_flags) 3545 return -EINVAL; 3546 3547 return match_flags; 3548 } 3549 3550 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 3551 { 3552 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN); 3553 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX); 3554 unsigned int pd_match_pri, pd_match_count; 3555 struct efx_ef10_filter_table *table; 3556 size_t outlen; 3557 int rc; 3558 3559 table = kzalloc(sizeof(*table), GFP_KERNEL); 3560 if (!table) 3561 return -ENOMEM; 3562 3563 /* Find out which RX filter types are supported, and their priorities */ 3564 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP, 3565 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); 3566 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO, 3567 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf), 3568 &outlen); 3569 if (rc) 3570 goto fail; 3571 pd_match_count = MCDI_VAR_ARRAY_LEN( 3572 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES); 3573 table->rx_match_count = 0; 3574 3575 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) { 3576 u32 mcdi_flags = 3577 MCDI_ARRAY_DWORD( 3578 outbuf, 3579 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES, 3580 pd_match_pri); 3581 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags); 3582 if (rc < 0) { 3583 netif_dbg(efx, probe, efx->net_dev, 3584 "%s: fw flags %#x pri %u not supported in driver\n", 3585 __func__, mcdi_flags, pd_match_pri); 3586 } else { 3587 netif_dbg(efx, probe, efx->net_dev, 3588 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n", 3589 __func__, mcdi_flags, pd_match_pri, 3590 rc, table->rx_match_count); 3591 table->rx_match_flags[table->rx_match_count++] = rc; 3592 } 3593 } 3594 3595 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry)); 3596 if (!table->entry) { 3597 rc = -ENOMEM; 3598 goto fail; 3599 } 3600 3601 efx->filter_state = table; 3602 init_waitqueue_head(&table->waitq); 3603 return 0; 3604 3605 fail: 3606 kfree(table); 3607 return rc; 3608 } 3609 3610 /* Caller must hold efx->filter_sem for read if race against 3611 * efx_ef10_filter_table_remove() is possible 3612 */ 3613 static void efx_ef10_filter_table_restore(struct efx_nic *efx) 3614 { 3615 struct efx_ef10_filter_table *table = efx->filter_state; 3616 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3617 struct efx_filter_spec *spec; 3618 unsigned int filter_idx; 3619 bool failed = false; 3620 int rc; 3621 3622 WARN_ON(!rwsem_is_locked(&efx->filter_sem)); 3623 3624 if (!nic_data->must_restore_filters) 3625 return; 3626 3627 if (!table) 3628 return; 3629 3630 spin_lock_bh(&efx->filter_lock); 3631 3632 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3633 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3634 if (!spec) 3635 continue; 3636 3637 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3638 spin_unlock_bh(&efx->filter_lock); 3639 3640 rc = efx_ef10_filter_push(efx, spec, 3641 &table->entry[filter_idx].handle, 3642 false); 3643 if (rc) 3644 failed = true; 3645 3646 spin_lock_bh(&efx->filter_lock); 3647 if (rc) { 3648 kfree(spec); 3649 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3650 } else { 3651 table->entry[filter_idx].spec &= 3652 ~EFX_EF10_FILTER_FLAG_BUSY; 3653 } 3654 } 3655 3656 spin_unlock_bh(&efx->filter_lock); 3657 3658 if (failed) 3659 netif_err(efx, hw, efx->net_dev, 3660 "unable to restore all filters\n"); 3661 else 3662 nic_data->must_restore_filters = false; 3663 } 3664 3665 /* Caller must hold efx->filter_sem for write */ 3666 static void efx_ef10_filter_table_remove(struct efx_nic *efx) 3667 { 3668 struct efx_ef10_filter_table *table = efx->filter_state; 3669 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3670 struct efx_filter_spec *spec; 3671 unsigned int filter_idx; 3672 int rc; 3673 3674 efx->filter_state = NULL; 3675 if (!table) 3676 return; 3677 3678 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3679 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3680 if (!spec) 3681 continue; 3682 3683 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3684 efx_ef10_filter_is_exclusive(spec) ? 3685 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3686 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3687 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3688 table->entry[filter_idx].handle); 3689 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3690 NULL, 0, NULL); 3691 if (rc) 3692 netdev_WARN(efx->net_dev, 3693 "filter_idx=%#x handle=%#llx\n", 3694 filter_idx, 3695 table->entry[filter_idx].handle); 3696 kfree(spec); 3697 } 3698 3699 vfree(table->entry); 3700 kfree(table); 3701 } 3702 3703 /* Caller must hold efx->filter_sem for read if race against 3704 * efx_ef10_filter_table_remove() is possible 3705 */ 3706 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx) 3707 { 3708 struct efx_ef10_filter_table *table = efx->filter_state; 3709 struct net_device *net_dev = efx->net_dev; 3710 struct efx_filter_spec spec; 3711 bool remove_failed = false; 3712 struct netdev_hw_addr *uc; 3713 struct netdev_hw_addr *mc; 3714 unsigned int filter_idx; 3715 int i, n, rc; 3716 3717 if (!efx_dev_registered(efx)) 3718 return; 3719 3720 if (!table) 3721 return; 3722 3723 /* Mark old filters that may need to be removed */ 3724 spin_lock_bh(&efx->filter_lock); 3725 n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count; 3726 for (i = 0; i < n; i++) { 3727 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS; 3728 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; 3729 } 3730 n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count; 3731 for (i = 0; i < n; i++) { 3732 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS; 3733 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; 3734 } 3735 spin_unlock_bh(&efx->filter_lock); 3736 3737 /* Copy/convert the address lists; add the primary station 3738 * address and broadcast address 3739 */ 3740 netif_addr_lock_bh(net_dev); 3741 if (net_dev->flags & IFF_PROMISC || 3742 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) { 3743 table->dev_uc_count = -1; 3744 } else { 3745 table->dev_uc_count = 1 + netdev_uc_count(net_dev); 3746 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr); 3747 i = 1; 3748 netdev_for_each_uc_addr(uc, net_dev) { 3749 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr); 3750 i++; 3751 } 3752 } 3753 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) || 3754 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) { 3755 table->dev_mc_count = -1; 3756 } else { 3757 table->dev_mc_count = 1 + netdev_mc_count(net_dev); 3758 eth_broadcast_addr(table->dev_mc_list[0].addr); 3759 i = 1; 3760 netdev_for_each_mc_addr(mc, net_dev) { 3761 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr); 3762 i++; 3763 } 3764 } 3765 netif_addr_unlock_bh(net_dev); 3766 3767 /* Insert/renew unicast filters */ 3768 if (table->dev_uc_count >= 0) { 3769 for (i = 0; i < table->dev_uc_count; i++) { 3770 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3771 EFX_FILTER_FLAG_RX_RSS, 3772 0); 3773 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 3774 table->dev_uc_list[i].addr); 3775 rc = efx_ef10_filter_insert(efx, &spec, true); 3776 if (rc < 0) { 3777 /* Fall back to unicast-promisc */ 3778 while (i--) 3779 efx_ef10_filter_remove_safe( 3780 efx, EFX_FILTER_PRI_AUTO, 3781 table->dev_uc_list[i].id); 3782 table->dev_uc_count = -1; 3783 break; 3784 } 3785 table->dev_uc_list[i].id = rc; 3786 } 3787 } 3788 if (table->dev_uc_count < 0) { 3789 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3790 EFX_FILTER_FLAG_RX_RSS, 3791 0); 3792 efx_filter_set_uc_def(&spec); 3793 rc = efx_ef10_filter_insert(efx, &spec, true); 3794 if (rc < 0) { 3795 WARN_ON(1); 3796 table->dev_uc_count = 0; 3797 } else { 3798 table->dev_uc_list[0].id = rc; 3799 } 3800 } 3801 3802 /* Insert/renew multicast filters */ 3803 if (table->dev_mc_count >= 0) { 3804 for (i = 0; i < table->dev_mc_count; i++) { 3805 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3806 EFX_FILTER_FLAG_RX_RSS, 3807 0); 3808 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 3809 table->dev_mc_list[i].addr); 3810 rc = efx_ef10_filter_insert(efx, &spec, true); 3811 if (rc < 0) { 3812 /* Fall back to multicast-promisc */ 3813 while (i--) 3814 efx_ef10_filter_remove_safe( 3815 efx, EFX_FILTER_PRI_AUTO, 3816 table->dev_mc_list[i].id); 3817 table->dev_mc_count = -1; 3818 break; 3819 } 3820 table->dev_mc_list[i].id = rc; 3821 } 3822 } 3823 if (table->dev_mc_count < 0) { 3824 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3825 EFX_FILTER_FLAG_RX_RSS, 3826 0); 3827 efx_filter_set_mc_def(&spec); 3828 rc = efx_ef10_filter_insert(efx, &spec, true); 3829 if (rc < 0) { 3830 WARN_ON(1); 3831 table->dev_mc_count = 0; 3832 } else { 3833 table->dev_mc_list[0].id = rc; 3834 } 3835 } 3836 3837 /* Remove filters that weren't renewed. Since nothing else 3838 * changes the AUTO_OLD flag or removes these filters, we 3839 * don't need to hold the filter_lock while scanning for 3840 * these filters. 3841 */ 3842 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 3843 if (ACCESS_ONCE(table->entry[i].spec) & 3844 EFX_EF10_FILTER_FLAG_AUTO_OLD) { 3845 if (efx_ef10_filter_remove_internal( 3846 efx, 1U << EFX_FILTER_PRI_AUTO, 3847 i, true) < 0) 3848 remove_failed = true; 3849 } 3850 } 3851 WARN_ON(remove_failed); 3852 } 3853 3854 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 3855 { 3856 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3857 u8 mac_old[ETH_ALEN]; 3858 int rc, rc2; 3859 3860 /* Only reconfigure a PF-created vport */ 3861 if (is_zero_ether_addr(nic_data->vport_mac)) 3862 return 0; 3863 3864 efx_device_detach_sync(efx); 3865 efx_net_stop(efx->net_dev); 3866 down_write(&efx->filter_sem); 3867 efx_ef10_filter_table_remove(efx); 3868 up_write(&efx->filter_sem); 3869 3870 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id); 3871 if (rc) 3872 goto restore_filters; 3873 3874 ether_addr_copy(mac_old, nic_data->vport_mac); 3875 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id, 3876 nic_data->vport_mac); 3877 if (rc) 3878 goto restore_vadaptor; 3879 3880 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id, 3881 efx->net_dev->dev_addr); 3882 if (!rc) { 3883 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 3884 } else { 3885 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old); 3886 if (rc2) { 3887 /* Failed to add original MAC, so clear vport_mac */ 3888 eth_zero_addr(nic_data->vport_mac); 3889 goto reset_nic; 3890 } 3891 } 3892 3893 restore_vadaptor: 3894 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id); 3895 if (rc2) 3896 goto reset_nic; 3897 restore_filters: 3898 down_write(&efx->filter_sem); 3899 rc2 = efx_ef10_filter_table_probe(efx); 3900 up_write(&efx->filter_sem); 3901 if (rc2) 3902 goto reset_nic; 3903 3904 rc2 = efx_net_open(efx->net_dev); 3905 if (rc2) 3906 goto reset_nic; 3907 3908 netif_device_attach(efx->net_dev); 3909 3910 return rc; 3911 3912 reset_nic: 3913 netif_err(efx, drv, efx->net_dev, 3914 "Failed to restore when changing MAC address - scheduling reset\n"); 3915 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 3916 3917 return rc ? rc : rc2; 3918 } 3919 3920 static int efx_ef10_set_mac_address(struct efx_nic *efx) 3921 { 3922 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 3923 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3924 bool was_enabled = efx->port_enabled; 3925 int rc; 3926 3927 efx_device_detach_sync(efx); 3928 efx_net_stop(efx->net_dev); 3929 down_write(&efx->filter_sem); 3930 efx_ef10_filter_table_remove(efx); 3931 3932 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 3933 efx->net_dev->dev_addr); 3934 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 3935 nic_data->vport_id); 3936 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 3937 sizeof(inbuf), NULL, 0, NULL); 3938 3939 efx_ef10_filter_table_probe(efx); 3940 up_write(&efx->filter_sem); 3941 if (was_enabled) 3942 efx_net_open(efx->net_dev); 3943 netif_device_attach(efx->net_dev); 3944 3945 #ifdef CONFIG_SFC_SRIOV 3946 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 3947 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 3948 3949 if (rc == -EPERM) { 3950 struct efx_nic *efx_pf; 3951 3952 /* Switch to PF and change MAC address on vport */ 3953 efx_pf = pci_get_drvdata(pci_dev_pf); 3954 3955 rc = efx_ef10_sriov_set_vf_mac(efx_pf, 3956 nic_data->vf_index, 3957 efx->net_dev->dev_addr); 3958 } else if (!rc) { 3959 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 3960 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data; 3961 unsigned int i; 3962 3963 /* MAC address successfully changed by VF (with MAC 3964 * spoofing) so update the parent PF if possible. 3965 */ 3966 for (i = 0; i < efx_pf->vf_count; ++i) { 3967 struct ef10_vf *vf = nic_data->vf + i; 3968 3969 if (vf->efx == efx) { 3970 ether_addr_copy(vf->mac, 3971 efx->net_dev->dev_addr); 3972 return 0; 3973 } 3974 } 3975 } 3976 } else 3977 #endif 3978 if (rc == -EPERM) { 3979 netif_err(efx, drv, efx->net_dev, 3980 "Cannot change MAC address; use sfboot to enable" 3981 " mac-spoofing on this interface\n"); 3982 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 3983 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 3984 * fall-back to the method of changing the MAC address on the 3985 * vport. This only applies to PFs because such versions of 3986 * MCFW do not support VFs. 3987 */ 3988 rc = efx_ef10_vport_set_mac_address(efx); 3989 } else { 3990 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 3991 sizeof(inbuf), NULL, 0, rc); 3992 } 3993 3994 return rc; 3995 } 3996 3997 static int efx_ef10_mac_reconfigure(struct efx_nic *efx) 3998 { 3999 efx_ef10_filter_sync_rx_mode(efx); 4000 4001 return efx_mcdi_set_mac(efx); 4002 } 4003 4004 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx) 4005 { 4006 efx_ef10_filter_sync_rx_mode(efx); 4007 4008 return 0; 4009 } 4010 4011 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 4012 { 4013 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 4014 4015 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 4016 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 4017 NULL, 0, NULL); 4018 } 4019 4020 /* MC BISTs follow a different poll mechanism to phy BISTs. 4021 * The BIST is done in the poll handler on the MC, and the MCDI command 4022 * will block until the BIST is done. 4023 */ 4024 static int efx_ef10_poll_bist(struct efx_nic *efx) 4025 { 4026 int rc; 4027 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 4028 size_t outlen; 4029 u32 result; 4030 4031 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 4032 outbuf, sizeof(outbuf), &outlen); 4033 if (rc != 0) 4034 return rc; 4035 4036 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 4037 return -EIO; 4038 4039 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 4040 switch (result) { 4041 case MC_CMD_POLL_BIST_PASSED: 4042 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 4043 return 0; 4044 case MC_CMD_POLL_BIST_TIMEOUT: 4045 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 4046 return -EIO; 4047 case MC_CMD_POLL_BIST_FAILED: 4048 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 4049 return -EIO; 4050 default: 4051 netif_err(efx, hw, efx->net_dev, 4052 "BIST returned unknown result %u", result); 4053 return -EIO; 4054 } 4055 } 4056 4057 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 4058 { 4059 int rc; 4060 4061 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 4062 4063 rc = efx_ef10_start_bist(efx, bist_type); 4064 if (rc != 0) 4065 return rc; 4066 4067 return efx_ef10_poll_bist(efx); 4068 } 4069 4070 static int 4071 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 4072 { 4073 int rc, rc2; 4074 4075 efx_reset_down(efx, RESET_TYPE_WORLD); 4076 4077 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 4078 NULL, 0, NULL, 0, NULL); 4079 if (rc != 0) 4080 goto out; 4081 4082 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 4083 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 4084 4085 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 4086 4087 out: 4088 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 4089 return rc ? rc : rc2; 4090 } 4091 4092 #ifdef CONFIG_SFC_MTD 4093 4094 struct efx_ef10_nvram_type_info { 4095 u16 type, type_mask; 4096 u8 port; 4097 const char *name; 4098 }; 4099 4100 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 4101 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 4102 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 4103 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 4104 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 4105 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 4106 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 4107 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 4108 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 4109 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 4110 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 4111 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 4112 }; 4113 4114 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 4115 struct efx_mcdi_mtd_partition *part, 4116 unsigned int type) 4117 { 4118 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 4119 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 4120 const struct efx_ef10_nvram_type_info *info; 4121 size_t size, erase_size, outlen; 4122 bool protected; 4123 int rc; 4124 4125 for (info = efx_ef10_nvram_types; ; info++) { 4126 if (info == 4127 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types)) 4128 return -ENODEV; 4129 if ((type & ~info->type_mask) == info->type) 4130 break; 4131 } 4132 if (info->port != efx_port_num(efx)) 4133 return -ENODEV; 4134 4135 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 4136 if (rc) 4137 return rc; 4138 if (protected) 4139 return -ENODEV; /* hide it */ 4140 4141 part->nvram_type = type; 4142 4143 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 4144 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 4145 outbuf, sizeof(outbuf), &outlen); 4146 if (rc) 4147 return rc; 4148 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 4149 return -EIO; 4150 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 4151 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 4152 part->fw_subtype = MCDI_DWORD(outbuf, 4153 NVRAM_METADATA_OUT_SUBTYPE); 4154 4155 part->common.dev_type_name = "EF10 NVRAM manager"; 4156 part->common.type_name = info->name; 4157 4158 part->common.mtd.type = MTD_NORFLASH; 4159 part->common.mtd.flags = MTD_CAP_NORFLASH; 4160 part->common.mtd.size = size; 4161 part->common.mtd.erasesize = erase_size; 4162 4163 return 0; 4164 } 4165 4166 static int efx_ef10_mtd_probe(struct efx_nic *efx) 4167 { 4168 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 4169 struct efx_mcdi_mtd_partition *parts; 4170 size_t outlen, n_parts_total, i, n_parts; 4171 unsigned int type; 4172 int rc; 4173 4174 ASSERT_RTNL(); 4175 4176 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 4177 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 4178 outbuf, sizeof(outbuf), &outlen); 4179 if (rc) 4180 return rc; 4181 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 4182 return -EIO; 4183 4184 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 4185 if (n_parts_total > 4186 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 4187 return -EIO; 4188 4189 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 4190 if (!parts) 4191 return -ENOMEM; 4192 4193 n_parts = 0; 4194 for (i = 0; i < n_parts_total; i++) { 4195 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 4196 i); 4197 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type); 4198 if (rc == 0) 4199 n_parts++; 4200 else if (rc != -ENODEV) 4201 goto fail; 4202 } 4203 4204 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 4205 fail: 4206 if (rc) 4207 kfree(parts); 4208 return rc; 4209 } 4210 4211 #endif /* CONFIG_SFC_MTD */ 4212 4213 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 4214 { 4215 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 4216 } 4217 4218 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 4219 u32 host_time) {} 4220 4221 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 4222 bool temp) 4223 { 4224 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 4225 int rc; 4226 4227 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 4228 channel->sync_events_state == SYNC_EVENTS_VALID || 4229 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 4230 return 0; 4231 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 4232 4233 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 4234 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 4235 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 4236 channel->channel); 4237 4238 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 4239 inbuf, sizeof(inbuf), NULL, 0, NULL); 4240 4241 if (rc != 0) 4242 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 4243 SYNC_EVENTS_DISABLED; 4244 4245 return rc; 4246 } 4247 4248 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 4249 bool temp) 4250 { 4251 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 4252 int rc; 4253 4254 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 4255 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 4256 return 0; 4257 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 4258 channel->sync_events_state = SYNC_EVENTS_DISABLED; 4259 return 0; 4260 } 4261 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 4262 SYNC_EVENTS_DISABLED; 4263 4264 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 4265 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 4266 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 4267 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 4268 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 4269 channel->channel); 4270 4271 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 4272 inbuf, sizeof(inbuf), NULL, 0, NULL); 4273 4274 return rc; 4275 } 4276 4277 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 4278 bool temp) 4279 { 4280 int (*set)(struct efx_channel *channel, bool temp); 4281 struct efx_channel *channel; 4282 4283 set = en ? 4284 efx_ef10_rx_enable_timestamping : 4285 efx_ef10_rx_disable_timestamping; 4286 4287 efx_for_each_channel(channel, efx) { 4288 int rc = set(channel, temp); 4289 if (en && rc != 0) { 4290 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 4291 return rc; 4292 } 4293 } 4294 4295 return 0; 4296 } 4297 4298 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 4299 struct hwtstamp_config *init) 4300 { 4301 return -EOPNOTSUPP; 4302 } 4303 4304 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 4305 struct hwtstamp_config *init) 4306 { 4307 int rc; 4308 4309 switch (init->rx_filter) { 4310 case HWTSTAMP_FILTER_NONE: 4311 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 4312 /* if TX timestamping is still requested then leave PTP on */ 4313 return efx_ptp_change_mode(efx, 4314 init->tx_type != HWTSTAMP_TX_OFF, 0); 4315 case HWTSTAMP_FILTER_ALL: 4316 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 4317 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 4318 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 4319 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 4320 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 4321 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 4322 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 4323 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 4324 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 4325 case HWTSTAMP_FILTER_PTP_V2_EVENT: 4326 case HWTSTAMP_FILTER_PTP_V2_SYNC: 4327 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 4328 init->rx_filter = HWTSTAMP_FILTER_ALL; 4329 rc = efx_ptp_change_mode(efx, true, 0); 4330 if (!rc) 4331 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 4332 if (rc) 4333 efx_ptp_change_mode(efx, false, 0); 4334 return rc; 4335 default: 4336 return -ERANGE; 4337 } 4338 } 4339 4340 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 4341 .is_vf = true, 4342 .mem_bar = EFX_MEM_VF_BAR, 4343 .mem_map_size = efx_ef10_mem_map_size, 4344 .probe = efx_ef10_probe_vf, 4345 .remove = efx_ef10_remove, 4346 .dimension_resources = efx_ef10_dimension_resources, 4347 .init = efx_ef10_init_nic, 4348 .fini = efx_port_dummy_op_void, 4349 .map_reset_reason = efx_ef10_map_reset_reason, 4350 .map_reset_flags = efx_ef10_map_reset_flags, 4351 .reset = efx_ef10_reset, 4352 .probe_port = efx_mcdi_port_probe, 4353 .remove_port = efx_mcdi_port_remove, 4354 .fini_dmaq = efx_ef10_fini_dmaq, 4355 .prepare_flr = efx_ef10_prepare_flr, 4356 .finish_flr = efx_port_dummy_op_void, 4357 .describe_stats = efx_ef10_describe_stats, 4358 .update_stats = efx_ef10_update_stats_vf, 4359 .start_stats = efx_port_dummy_op_void, 4360 .pull_stats = efx_port_dummy_op_void, 4361 .stop_stats = efx_port_dummy_op_void, 4362 .set_id_led = efx_mcdi_set_id_led, 4363 .push_irq_moderation = efx_ef10_push_irq_moderation, 4364 .reconfigure_mac = efx_ef10_mac_reconfigure_vf, 4365 .check_mac_fault = efx_mcdi_mac_check_fault, 4366 .reconfigure_port = efx_mcdi_port_reconfigure, 4367 .get_wol = efx_ef10_get_wol_vf, 4368 .set_wol = efx_ef10_set_wol_vf, 4369 .resume_wol = efx_port_dummy_op_void, 4370 .mcdi_request = efx_ef10_mcdi_request, 4371 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4372 .mcdi_read_response = efx_ef10_mcdi_read_response, 4373 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4374 .irq_enable_master = efx_port_dummy_op_void, 4375 .irq_test_generate = efx_ef10_irq_test_generate, 4376 .irq_disable_non_ev = efx_port_dummy_op_void, 4377 .irq_handle_msi = efx_ef10_msi_interrupt, 4378 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4379 .tx_probe = efx_ef10_tx_probe, 4380 .tx_init = efx_ef10_tx_init, 4381 .tx_remove = efx_ef10_tx_remove, 4382 .tx_write = efx_ef10_tx_write, 4383 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config, 4384 .rx_probe = efx_ef10_rx_probe, 4385 .rx_init = efx_ef10_rx_init, 4386 .rx_remove = efx_ef10_rx_remove, 4387 .rx_write = efx_ef10_rx_write, 4388 .rx_defer_refill = efx_ef10_rx_defer_refill, 4389 .ev_probe = efx_ef10_ev_probe, 4390 .ev_init = efx_ef10_ev_init, 4391 .ev_fini = efx_ef10_ev_fini, 4392 .ev_remove = efx_ef10_ev_remove, 4393 .ev_process = efx_ef10_ev_process, 4394 .ev_read_ack = efx_ef10_ev_read_ack, 4395 .ev_test_generate = efx_ef10_ev_test_generate, 4396 .filter_table_probe = efx_ef10_filter_table_probe, 4397 .filter_table_restore = efx_ef10_filter_table_restore, 4398 .filter_table_remove = efx_ef10_filter_table_remove, 4399 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 4400 .filter_insert = efx_ef10_filter_insert, 4401 .filter_remove_safe = efx_ef10_filter_remove_safe, 4402 .filter_get_safe = efx_ef10_filter_get_safe, 4403 .filter_clear_rx = efx_ef10_filter_clear_rx, 4404 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 4405 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 4406 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 4407 #ifdef CONFIG_RFS_ACCEL 4408 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 4409 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 4410 #endif 4411 #ifdef CONFIG_SFC_MTD 4412 .mtd_probe = efx_port_dummy_op_int, 4413 #endif 4414 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4415 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4416 #ifdef CONFIG_SFC_SRIOV 4417 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4418 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4419 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4420 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id, 4421 #endif 4422 .get_mac_address = efx_ef10_get_mac_address_vf, 4423 .set_mac_address = efx_ef10_set_mac_address, 4424 4425 .revision = EFX_REV_HUNT_A0, 4426 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4427 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4428 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4429 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4430 .can_rx_scatter = true, 4431 .always_rx_scatter = true, 4432 .max_interrupt_mode = EFX_INT_MODE_MSIX, 4433 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4434 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4435 NETIF_F_RXHASH | NETIF_F_NTUPLE), 4436 .mcdi_max_ver = 2, 4437 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 4438 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4439 1 << HWTSTAMP_FILTER_ALL, 4440 }; 4441 4442 const struct efx_nic_type efx_hunt_a0_nic_type = { 4443 .is_vf = false, 4444 .mem_bar = EFX_MEM_BAR, 4445 .mem_map_size = efx_ef10_mem_map_size, 4446 .probe = efx_ef10_probe_pf, 4447 .remove = efx_ef10_remove, 4448 .dimension_resources = efx_ef10_dimension_resources, 4449 .init = efx_ef10_init_nic, 4450 .fini = efx_port_dummy_op_void, 4451 .map_reset_reason = efx_ef10_map_reset_reason, 4452 .map_reset_flags = efx_ef10_map_reset_flags, 4453 .reset = efx_ef10_reset, 4454 .probe_port = efx_mcdi_port_probe, 4455 .remove_port = efx_mcdi_port_remove, 4456 .fini_dmaq = efx_ef10_fini_dmaq, 4457 .prepare_flr = efx_ef10_prepare_flr, 4458 .finish_flr = efx_port_dummy_op_void, 4459 .describe_stats = efx_ef10_describe_stats, 4460 .update_stats = efx_ef10_update_stats_pf, 4461 .start_stats = efx_mcdi_mac_start_stats, 4462 .pull_stats = efx_mcdi_mac_pull_stats, 4463 .stop_stats = efx_mcdi_mac_stop_stats, 4464 .set_id_led = efx_mcdi_set_id_led, 4465 .push_irq_moderation = efx_ef10_push_irq_moderation, 4466 .reconfigure_mac = efx_ef10_mac_reconfigure, 4467 .check_mac_fault = efx_mcdi_mac_check_fault, 4468 .reconfigure_port = efx_mcdi_port_reconfigure, 4469 .get_wol = efx_ef10_get_wol, 4470 .set_wol = efx_ef10_set_wol, 4471 .resume_wol = efx_port_dummy_op_void, 4472 .test_chip = efx_ef10_test_chip, 4473 .test_nvram = efx_mcdi_nvram_test_all, 4474 .mcdi_request = efx_ef10_mcdi_request, 4475 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4476 .mcdi_read_response = efx_ef10_mcdi_read_response, 4477 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4478 .irq_enable_master = efx_port_dummy_op_void, 4479 .irq_test_generate = efx_ef10_irq_test_generate, 4480 .irq_disable_non_ev = efx_port_dummy_op_void, 4481 .irq_handle_msi = efx_ef10_msi_interrupt, 4482 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4483 .tx_probe = efx_ef10_tx_probe, 4484 .tx_init = efx_ef10_tx_init, 4485 .tx_remove = efx_ef10_tx_remove, 4486 .tx_write = efx_ef10_tx_write, 4487 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config, 4488 .rx_probe = efx_ef10_rx_probe, 4489 .rx_init = efx_ef10_rx_init, 4490 .rx_remove = efx_ef10_rx_remove, 4491 .rx_write = efx_ef10_rx_write, 4492 .rx_defer_refill = efx_ef10_rx_defer_refill, 4493 .ev_probe = efx_ef10_ev_probe, 4494 .ev_init = efx_ef10_ev_init, 4495 .ev_fini = efx_ef10_ev_fini, 4496 .ev_remove = efx_ef10_ev_remove, 4497 .ev_process = efx_ef10_ev_process, 4498 .ev_read_ack = efx_ef10_ev_read_ack, 4499 .ev_test_generate = efx_ef10_ev_test_generate, 4500 .filter_table_probe = efx_ef10_filter_table_probe, 4501 .filter_table_restore = efx_ef10_filter_table_restore, 4502 .filter_table_remove = efx_ef10_filter_table_remove, 4503 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 4504 .filter_insert = efx_ef10_filter_insert, 4505 .filter_remove_safe = efx_ef10_filter_remove_safe, 4506 .filter_get_safe = efx_ef10_filter_get_safe, 4507 .filter_clear_rx = efx_ef10_filter_clear_rx, 4508 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 4509 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 4510 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 4511 #ifdef CONFIG_RFS_ACCEL 4512 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 4513 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 4514 #endif 4515 #ifdef CONFIG_SFC_MTD 4516 .mtd_probe = efx_ef10_mtd_probe, 4517 .mtd_rename = efx_mcdi_mtd_rename, 4518 .mtd_read = efx_mcdi_mtd_read, 4519 .mtd_erase = efx_mcdi_mtd_erase, 4520 .mtd_write = efx_mcdi_mtd_write, 4521 .mtd_sync = efx_mcdi_mtd_sync, 4522 #endif 4523 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4524 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4525 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4526 #ifdef CONFIG_SFC_SRIOV 4527 .sriov_configure = efx_ef10_sriov_configure, 4528 .sriov_init = efx_ef10_sriov_init, 4529 .sriov_fini = efx_ef10_sriov_fini, 4530 .sriov_wanted = efx_ef10_sriov_wanted, 4531 .sriov_reset = efx_ef10_sriov_reset, 4532 .sriov_flr = efx_ef10_sriov_flr, 4533 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4534 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4535 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4536 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4537 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4538 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4539 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4540 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4541 #endif 4542 .get_mac_address = efx_ef10_get_mac_address_pf, 4543 .set_mac_address = efx_ef10_set_mac_address, 4544 4545 .revision = EFX_REV_HUNT_A0, 4546 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4547 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4548 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4549 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4550 .can_rx_scatter = true, 4551 .always_rx_scatter = true, 4552 .max_interrupt_mode = EFX_INT_MODE_MSIX, 4553 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4554 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4555 NETIF_F_RXHASH | NETIF_F_NTUPLE), 4556 .mcdi_max_ver = 2, 4557 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 4558 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4559 1 << HWTSTAMP_FILTER_ALL, 4560 }; 4561