1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2012-2013 Solarflare Communications Inc. 5 */ 6 7 #include "net_driver.h" 8 #include "rx_common.h" 9 #include "tx_common.h" 10 #include "ef10_regs.h" 11 #include "io.h" 12 #include "mcdi.h" 13 #include "mcdi_pcol.h" 14 #include "mcdi_port.h" 15 #include "mcdi_port_common.h" 16 #include "mcdi_functions.h" 17 #include "nic.h" 18 #include "mcdi_filters.h" 19 #include "workarounds.h" 20 #include "selftest.h" 21 #include "ef10_sriov.h" 22 #include <linux/in.h> 23 #include <linux/jhash.h> 24 #include <linux/wait.h> 25 #include <linux/workqueue.h> 26 #include <net/udp_tunnel.h> 27 28 /* Hardware control for EF10 architecture including 'Huntington'. */ 29 30 #define EFX_EF10_DRVGEN_EV 7 31 enum { 32 EFX_EF10_TEST = 1, 33 EFX_EF10_REFILL, 34 }; 35 36 /* VLAN list entry */ 37 struct efx_ef10_vlan { 38 struct list_head list; 39 u16 vid; 40 }; 41 42 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading); 43 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels; 44 45 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 46 { 47 efx_dword_t reg; 48 49 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 50 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 51 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 52 } 53 54 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for 55 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O 56 * bar; PFs use BAR 0/1 for memory. 57 */ 58 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx) 59 { 60 switch (efx->pci_dev->device) { 61 case 0x0b03: /* SFC9250 PF */ 62 return 0; 63 default: 64 return 2; 65 } 66 } 67 68 /* All VFs use BAR 0/1 for memory */ 69 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx) 70 { 71 return 0; 72 } 73 74 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 75 { 76 int bar; 77 78 bar = efx->type->mem_bar(efx); 79 return resource_size(&efx->pci_dev->resource[bar]); 80 } 81 82 static bool efx_ef10_is_vf(struct efx_nic *efx) 83 { 84 return efx->type->is_vf; 85 } 86 87 #ifdef CONFIG_SFC_SRIOV 88 static int efx_ef10_get_vf_index(struct efx_nic *efx) 89 { 90 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 91 struct efx_ef10_nic_data *nic_data = efx->nic_data; 92 size_t outlen; 93 int rc; 94 95 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 96 sizeof(outbuf), &outlen); 97 if (rc) 98 return rc; 99 if (outlen < sizeof(outbuf)) 100 return -EIO; 101 102 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 103 return 0; 104 } 105 #endif 106 107 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 108 { 109 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN); 110 struct efx_ef10_nic_data *nic_data = efx->nic_data; 111 size_t outlen; 112 int rc; 113 114 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 115 116 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 117 outbuf, sizeof(outbuf), &outlen); 118 if (rc) 119 return rc; 120 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 121 netif_err(efx, drv, efx->net_dev, 122 "unable to read datapath firmware capabilities\n"); 123 return -EIO; 124 } 125 126 nic_data->datapath_caps = 127 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 128 129 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) { 130 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 131 GET_CAPABILITIES_V2_OUT_FLAGS2); 132 nic_data->piobuf_size = MCDI_WORD(outbuf, 133 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF); 134 } else { 135 nic_data->datapath_caps2 = 0; 136 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE; 137 } 138 139 /* record the DPCPU firmware IDs to determine VEB vswitching support. 140 */ 141 nic_data->rx_dpcpu_fw_id = 142 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 143 nic_data->tx_dpcpu_fw_id = 144 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 145 146 if (!(nic_data->datapath_caps & 147 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 148 netif_err(efx, probe, efx->net_dev, 149 "current firmware does not support an RX prefix\n"); 150 return -ENODEV; 151 } 152 153 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { 154 u8 vi_window_mode = MCDI_BYTE(outbuf, 155 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 156 157 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 158 if (rc) 159 return rc; 160 } else { 161 /* keep default VI stride */ 162 netif_dbg(efx, probe, efx->net_dev, 163 "firmware did not report VI window mode, assuming vi_stride = %u\n", 164 efx->vi_stride); 165 } 166 167 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 168 efx->num_mac_stats = MCDI_WORD(outbuf, 169 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 170 netif_dbg(efx, probe, efx->net_dev, 171 "firmware reports num_mac_stats = %u\n", 172 efx->num_mac_stats); 173 } else { 174 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */ 175 netif_dbg(efx, probe, efx->net_dev, 176 "firmware did not report num_mac_stats, assuming %u\n", 177 efx->num_mac_stats); 178 } 179 180 return 0; 181 } 182 183 static void efx_ef10_read_licensed_features(struct efx_nic *efx) 184 { 185 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN); 186 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN); 187 struct efx_ef10_nic_data *nic_data = efx->nic_data; 188 size_t outlen; 189 int rc; 190 191 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP, 192 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE); 193 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf), 194 outbuf, sizeof(outbuf), &outlen); 195 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN)) 196 return; 197 198 nic_data->licensed_features = MCDI_QWORD(outbuf, 199 LICENSING_V3_OUT_LICENSED_FEATURES); 200 } 201 202 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 203 { 204 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 205 int rc; 206 207 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 208 outbuf, sizeof(outbuf), NULL); 209 if (rc) 210 return rc; 211 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 212 return rc > 0 ? rc : -ERANGE; 213 } 214 215 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx) 216 { 217 struct efx_ef10_nic_data *nic_data = efx->nic_data; 218 unsigned int implemented; 219 unsigned int enabled; 220 int rc; 221 222 nic_data->workaround_35388 = false; 223 nic_data->workaround_61265 = false; 224 225 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 226 227 if (rc == -ENOSYS) { 228 /* Firmware without GET_WORKAROUNDS - not a problem. */ 229 rc = 0; 230 } else if (rc == 0) { 231 /* Bug61265 workaround is always enabled if implemented. */ 232 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265) 233 nic_data->workaround_61265 = true; 234 235 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 236 nic_data->workaround_35388 = true; 237 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 238 /* Workaround is implemented but not enabled. 239 * Try to enable it. 240 */ 241 rc = efx_mcdi_set_workaround(efx, 242 MC_CMD_WORKAROUND_BUG35388, 243 true, NULL); 244 if (rc == 0) 245 nic_data->workaround_35388 = true; 246 /* If we failed to set the workaround just carry on. */ 247 rc = 0; 248 } 249 } 250 251 netif_dbg(efx, probe, efx->net_dev, 252 "workaround for bug 35388 is %sabled\n", 253 nic_data->workaround_35388 ? "en" : "dis"); 254 netif_dbg(efx, probe, efx->net_dev, 255 "workaround for bug 61265 is %sabled\n", 256 nic_data->workaround_61265 ? "en" : "dis"); 257 258 return rc; 259 } 260 261 static void efx_ef10_process_timer_config(struct efx_nic *efx, 262 const efx_dword_t *data) 263 { 264 unsigned int max_count; 265 266 if (EFX_EF10_WORKAROUND_61265(efx)) { 267 efx->timer_quantum_ns = MCDI_DWORD(data, 268 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS); 269 efx->timer_max_ns = MCDI_DWORD(data, 270 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS); 271 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 272 efx->timer_quantum_ns = MCDI_DWORD(data, 273 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT); 274 max_count = MCDI_DWORD(data, 275 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT); 276 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 277 } else { 278 efx->timer_quantum_ns = MCDI_DWORD(data, 279 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT); 280 max_count = MCDI_DWORD(data, 281 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT); 282 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 283 } 284 285 netif_dbg(efx, probe, efx->net_dev, 286 "got timer properties from MC: quantum %u ns; max %u ns\n", 287 efx->timer_quantum_ns, efx->timer_max_ns); 288 } 289 290 static int efx_ef10_get_timer_config(struct efx_nic *efx) 291 { 292 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN); 293 int rc; 294 295 rc = efx_ef10_get_timer_workarounds(efx); 296 if (rc) 297 return rc; 298 299 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0, 300 outbuf, sizeof(outbuf), NULL); 301 302 if (rc == 0) { 303 efx_ef10_process_timer_config(efx, outbuf); 304 } else if (rc == -ENOSYS || rc == -EPERM) { 305 /* Not available - fall back to Huntington defaults. */ 306 unsigned int quantum; 307 308 rc = efx_ef10_get_sysclk_freq(efx); 309 if (rc < 0) 310 return rc; 311 312 quantum = 1536000 / rc; /* 1536 cycles */ 313 efx->timer_quantum_ns = quantum; 314 efx->timer_max_ns = efx->type->timer_period_max * quantum; 315 rc = 0; 316 } else { 317 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, 318 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN, 319 NULL, 0, rc); 320 } 321 322 return rc; 323 } 324 325 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 326 { 327 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 328 size_t outlen; 329 int rc; 330 331 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 332 333 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 334 outbuf, sizeof(outbuf), &outlen); 335 if (rc) 336 return rc; 337 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 338 return -EIO; 339 340 ether_addr_copy(mac_address, 341 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 342 return 0; 343 } 344 345 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 346 { 347 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 348 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 349 size_t outlen; 350 int num_addrs, rc; 351 352 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 353 EVB_PORT_ID_ASSIGNED); 354 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 355 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 356 357 if (rc) 358 return rc; 359 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 360 return -EIO; 361 362 num_addrs = MCDI_DWORD(outbuf, 363 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 364 365 WARN_ON(num_addrs != 1); 366 367 ether_addr_copy(mac_address, 368 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 369 370 return 0; 371 } 372 373 static ssize_t link_control_flag_show(struct device *dev, 374 struct device_attribute *attr, 375 char *buf) 376 { 377 struct efx_nic *efx = dev_get_drvdata(dev); 378 379 return sprintf(buf, "%d\n", 380 ((efx->mcdi->fn_flags) & 381 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 382 ? 1 : 0); 383 } 384 385 static ssize_t primary_flag_show(struct device *dev, 386 struct device_attribute *attr, 387 char *buf) 388 { 389 struct efx_nic *efx = dev_get_drvdata(dev); 390 391 return sprintf(buf, "%d\n", 392 ((efx->mcdi->fn_flags) & 393 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 394 ? 1 : 0); 395 } 396 397 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid) 398 { 399 struct efx_ef10_nic_data *nic_data = efx->nic_data; 400 struct efx_ef10_vlan *vlan; 401 402 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 403 404 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 405 if (vlan->vid == vid) 406 return vlan; 407 } 408 409 return NULL; 410 } 411 412 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid) 413 { 414 struct efx_ef10_nic_data *nic_data = efx->nic_data; 415 struct efx_ef10_vlan *vlan; 416 int rc; 417 418 mutex_lock(&nic_data->vlan_lock); 419 420 vlan = efx_ef10_find_vlan(efx, vid); 421 if (vlan) { 422 /* We add VID 0 on init. 8021q adds it on module init 423 * for all interfaces with VLAN filtring feature. 424 */ 425 if (vid == 0) 426 goto done_unlock; 427 netif_warn(efx, drv, efx->net_dev, 428 "VLAN %u already added\n", vid); 429 rc = -EALREADY; 430 goto fail_exist; 431 } 432 433 rc = -ENOMEM; 434 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 435 if (!vlan) 436 goto fail_alloc; 437 438 vlan->vid = vid; 439 440 list_add_tail(&vlan->list, &nic_data->vlan_list); 441 442 if (efx->filter_state) { 443 mutex_lock(&efx->mac_lock); 444 down_write(&efx->filter_sem); 445 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 446 up_write(&efx->filter_sem); 447 mutex_unlock(&efx->mac_lock); 448 if (rc) 449 goto fail_filter_add_vlan; 450 } 451 452 done_unlock: 453 mutex_unlock(&nic_data->vlan_lock); 454 return 0; 455 456 fail_filter_add_vlan: 457 list_del(&vlan->list); 458 kfree(vlan); 459 fail_alloc: 460 fail_exist: 461 mutex_unlock(&nic_data->vlan_lock); 462 return rc; 463 } 464 465 static void efx_ef10_del_vlan_internal(struct efx_nic *efx, 466 struct efx_ef10_vlan *vlan) 467 { 468 struct efx_ef10_nic_data *nic_data = efx->nic_data; 469 470 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 471 472 if (efx->filter_state) { 473 down_write(&efx->filter_sem); 474 efx_mcdi_filter_del_vlan(efx, vlan->vid); 475 up_write(&efx->filter_sem); 476 } 477 478 list_del(&vlan->list); 479 kfree(vlan); 480 } 481 482 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid) 483 { 484 struct efx_ef10_nic_data *nic_data = efx->nic_data; 485 struct efx_ef10_vlan *vlan; 486 int rc = 0; 487 488 /* 8021q removes VID 0 on module unload for all interfaces 489 * with VLAN filtering feature. We need to keep it to receive 490 * untagged traffic. 491 */ 492 if (vid == 0) 493 return 0; 494 495 mutex_lock(&nic_data->vlan_lock); 496 497 vlan = efx_ef10_find_vlan(efx, vid); 498 if (!vlan) { 499 netif_err(efx, drv, efx->net_dev, 500 "VLAN %u to be deleted not found\n", vid); 501 rc = -ENOENT; 502 } else { 503 efx_ef10_del_vlan_internal(efx, vlan); 504 } 505 506 mutex_unlock(&nic_data->vlan_lock); 507 508 return rc; 509 } 510 511 static void efx_ef10_cleanup_vlans(struct efx_nic *efx) 512 { 513 struct efx_ef10_nic_data *nic_data = efx->nic_data; 514 struct efx_ef10_vlan *vlan, *next_vlan; 515 516 mutex_lock(&nic_data->vlan_lock); 517 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list) 518 efx_ef10_del_vlan_internal(efx, vlan); 519 mutex_unlock(&nic_data->vlan_lock); 520 } 521 522 static DEVICE_ATTR_RO(link_control_flag); 523 static DEVICE_ATTR_RO(primary_flag); 524 525 static int efx_ef10_probe(struct efx_nic *efx) 526 { 527 struct efx_ef10_nic_data *nic_data; 528 int i, rc; 529 530 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 531 if (!nic_data) 532 return -ENOMEM; 533 efx->nic_data = nic_data; 534 535 /* we assume later that we can copy from this buffer in dwords */ 536 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 537 538 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 539 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 540 if (rc) 541 goto fail1; 542 543 /* Get the MC's warm boot count. In case it's rebooting right 544 * now, be prepared to retry. 545 */ 546 i = 0; 547 for (;;) { 548 rc = efx_ef10_get_warm_boot_count(efx); 549 if (rc >= 0) 550 break; 551 if (++i == 5) 552 goto fail2; 553 ssleep(1); 554 } 555 nic_data->warm_boot_count = rc; 556 557 /* In case we're recovering from a crash (kexec), we want to 558 * cancel any outstanding request by the previous user of this 559 * function. We send a special message using the least 560 * significant bits of the 'high' (doorbell) register. 561 */ 562 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 563 564 rc = efx_mcdi_init(efx); 565 if (rc) 566 goto fail2; 567 568 mutex_init(&nic_data->udp_tunnels_lock); 569 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 570 nic_data->udp_tunnels[i].type = 571 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 572 573 /* Reset (most) configuration for this function */ 574 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 575 if (rc) 576 goto fail3; 577 578 /* Enable event logging */ 579 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 580 if (rc) 581 goto fail3; 582 583 rc = device_create_file(&efx->pci_dev->dev, 584 &dev_attr_link_control_flag); 585 if (rc) 586 goto fail3; 587 588 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 589 if (rc) 590 goto fail4; 591 592 rc = efx_get_pf_index(efx, &nic_data->pf_index); 593 if (rc) 594 goto fail5; 595 596 rc = efx_ef10_init_datapath_caps(efx); 597 if (rc < 0) 598 goto fail5; 599 600 efx_ef10_read_licensed_features(efx); 601 602 /* We can have one VI for each vi_stride-byte region. 603 * However, until we use TX option descriptors we need up to four 604 * TX queues per channel for different checksumming combinations. 605 */ 606 if (nic_data->datapath_caps & 607 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)) 608 efx->tx_queues_per_channel = 4; 609 else 610 efx->tx_queues_per_channel = 2; 611 efx->max_vis = efx_ef10_mem_map_size(efx) / efx->vi_stride; 612 if (!efx->max_vis) { 613 netif_err(efx, drv, efx->net_dev, "error determining max VIs\n"); 614 rc = -EIO; 615 goto fail5; 616 } 617 efx->max_channels = min_t(unsigned int, EFX_MAX_CHANNELS, 618 efx->max_vis / efx->tx_queues_per_channel); 619 efx->max_tx_channels = efx->max_channels; 620 if (WARN_ON(efx->max_channels == 0)) { 621 rc = -EIO; 622 goto fail5; 623 } 624 625 efx->rx_packet_len_offset = 626 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 627 628 if (nic_data->datapath_caps & 629 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN)) 630 efx->net_dev->hw_features |= NETIF_F_RXFCS; 631 632 rc = efx_mcdi_port_get_number(efx); 633 if (rc < 0) 634 goto fail5; 635 efx->port_num = rc; 636 637 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 638 if (rc) 639 goto fail5; 640 641 rc = efx_ef10_get_timer_config(efx); 642 if (rc < 0) 643 goto fail5; 644 645 rc = efx_mcdi_mon_probe(efx); 646 if (rc && rc != -EPERM) 647 goto fail5; 648 649 efx_ptp_defer_probe_with_channel(efx); 650 651 #ifdef CONFIG_SFC_SRIOV 652 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 653 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 654 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 655 656 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 657 } else 658 #endif 659 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 660 661 INIT_LIST_HEAD(&nic_data->vlan_list); 662 mutex_init(&nic_data->vlan_lock); 663 664 /* Add unspecified VID to support VLAN filtering being disabled */ 665 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 666 if (rc) 667 goto fail_add_vid_unspec; 668 669 /* If VLAN filtering is enabled, we need VID 0 to get untagged 670 * traffic. It is added automatically if 8021q module is loaded, 671 * but we can't rely on it since module may be not loaded. 672 */ 673 rc = efx_ef10_add_vlan(efx, 0); 674 if (rc) 675 goto fail_add_vid_0; 676 677 if (nic_data->datapath_caps & 678 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) && 679 efx->mcdi->fn_flags & 680 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) 681 efx->net_dev->udp_tunnel_nic_info = &efx_ef10_udp_tunnels; 682 683 return 0; 684 685 fail_add_vid_0: 686 efx_ef10_cleanup_vlans(efx); 687 fail_add_vid_unspec: 688 mutex_destroy(&nic_data->vlan_lock); 689 efx_ptp_remove(efx); 690 efx_mcdi_mon_remove(efx); 691 fail5: 692 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 693 fail4: 694 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 695 fail3: 696 efx_mcdi_detach(efx); 697 698 mutex_lock(&nic_data->udp_tunnels_lock); 699 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 700 (void)efx_ef10_set_udp_tnl_ports(efx, true); 701 mutex_unlock(&nic_data->udp_tunnels_lock); 702 mutex_destroy(&nic_data->udp_tunnels_lock); 703 704 efx_mcdi_fini(efx); 705 fail2: 706 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 707 fail1: 708 kfree(nic_data); 709 efx->nic_data = NULL; 710 return rc; 711 } 712 713 #ifdef EFX_USE_PIO 714 715 static void efx_ef10_free_piobufs(struct efx_nic *efx) 716 { 717 struct efx_ef10_nic_data *nic_data = efx->nic_data; 718 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 719 unsigned int i; 720 int rc; 721 722 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 723 724 for (i = 0; i < nic_data->n_piobufs; i++) { 725 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 726 nic_data->piobuf_handle[i]); 727 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 728 NULL, 0, NULL); 729 WARN_ON(rc); 730 } 731 732 nic_data->n_piobufs = 0; 733 } 734 735 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 736 { 737 struct efx_ef10_nic_data *nic_data = efx->nic_data; 738 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 739 unsigned int i; 740 size_t outlen; 741 int rc = 0; 742 743 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 744 745 for (i = 0; i < n; i++) { 746 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 747 outbuf, sizeof(outbuf), &outlen); 748 if (rc) { 749 /* Don't display the MC error if we didn't have space 750 * for a VF. 751 */ 752 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC)) 753 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF, 754 0, outbuf, outlen, rc); 755 break; 756 } 757 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 758 rc = -EIO; 759 break; 760 } 761 nic_data->piobuf_handle[i] = 762 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 763 netif_dbg(efx, probe, efx->net_dev, 764 "allocated PIO buffer %u handle %x\n", i, 765 nic_data->piobuf_handle[i]); 766 } 767 768 nic_data->n_piobufs = i; 769 if (rc) 770 efx_ef10_free_piobufs(efx); 771 return rc; 772 } 773 774 static int efx_ef10_link_piobufs(struct efx_nic *efx) 775 { 776 struct efx_ef10_nic_data *nic_data = efx->nic_data; 777 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN); 778 struct efx_channel *channel; 779 struct efx_tx_queue *tx_queue; 780 unsigned int offset, index; 781 int rc; 782 783 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 784 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 785 786 /* Link a buffer to each VI in the write-combining mapping */ 787 for (index = 0; index < nic_data->n_piobufs; ++index) { 788 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 789 nic_data->piobuf_handle[index]); 790 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 791 nic_data->pio_write_vi_base + index); 792 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 793 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 794 NULL, 0, NULL); 795 if (rc) { 796 netif_err(efx, drv, efx->net_dev, 797 "failed to link VI %u to PIO buffer %u (%d)\n", 798 nic_data->pio_write_vi_base + index, index, 799 rc); 800 goto fail; 801 } 802 netif_dbg(efx, probe, efx->net_dev, 803 "linked VI %u to PIO buffer %u\n", 804 nic_data->pio_write_vi_base + index, index); 805 } 806 807 /* Link a buffer to each TX queue */ 808 efx_for_each_channel(channel, efx) { 809 /* Extra channels, even those with TXQs (PTP), do not require 810 * PIO resources. 811 */ 812 if (!channel->type->want_pio || 813 channel->channel >= efx->xdp_channel_offset) 814 continue; 815 816 efx_for_each_channel_tx_queue(tx_queue, channel) { 817 /* We assign the PIO buffers to queues in 818 * reverse order to allow for the following 819 * special case. 820 */ 821 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 822 tx_queue->channel->channel - 1) * 823 efx_piobuf_size); 824 index = offset / nic_data->piobuf_size; 825 offset = offset % nic_data->piobuf_size; 826 827 /* When the host page size is 4K, the first 828 * host page in the WC mapping may be within 829 * the same VI page as the last TX queue. We 830 * can only link one buffer to each VI. 831 */ 832 if (tx_queue->queue == nic_data->pio_write_vi_base) { 833 BUG_ON(index != 0); 834 rc = 0; 835 } else { 836 MCDI_SET_DWORD(inbuf, 837 LINK_PIOBUF_IN_PIOBUF_HANDLE, 838 nic_data->piobuf_handle[index]); 839 MCDI_SET_DWORD(inbuf, 840 LINK_PIOBUF_IN_TXQ_INSTANCE, 841 tx_queue->queue); 842 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 843 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 844 NULL, 0, NULL); 845 } 846 847 if (rc) { 848 /* This is non-fatal; the TX path just 849 * won't use PIO for this queue 850 */ 851 netif_err(efx, drv, efx->net_dev, 852 "failed to link VI %u to PIO buffer %u (%d)\n", 853 tx_queue->queue, index, rc); 854 tx_queue->piobuf = NULL; 855 } else { 856 tx_queue->piobuf = 857 nic_data->pio_write_base + 858 index * efx->vi_stride + offset; 859 tx_queue->piobuf_offset = offset; 860 netif_dbg(efx, probe, efx->net_dev, 861 "linked VI %u to PIO buffer %u offset %x addr %p\n", 862 tx_queue->queue, index, 863 tx_queue->piobuf_offset, 864 tx_queue->piobuf); 865 } 866 } 867 } 868 869 return 0; 870 871 fail: 872 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same 873 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter. 874 */ 875 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN); 876 while (index--) { 877 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 878 nic_data->pio_write_vi_base + index); 879 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 880 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 881 NULL, 0, NULL); 882 } 883 return rc; 884 } 885 886 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 887 { 888 struct efx_channel *channel; 889 struct efx_tx_queue *tx_queue; 890 891 /* All our existing PIO buffers went away */ 892 efx_for_each_channel(channel, efx) 893 efx_for_each_channel_tx_queue(tx_queue, channel) 894 tx_queue->piobuf = NULL; 895 } 896 897 #else /* !EFX_USE_PIO */ 898 899 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 900 { 901 return n == 0 ? 0 : -ENOBUFS; 902 } 903 904 static int efx_ef10_link_piobufs(struct efx_nic *efx) 905 { 906 return 0; 907 } 908 909 static void efx_ef10_free_piobufs(struct efx_nic *efx) 910 { 911 } 912 913 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 914 { 915 } 916 917 #endif /* EFX_USE_PIO */ 918 919 static void efx_ef10_remove(struct efx_nic *efx) 920 { 921 struct efx_ef10_nic_data *nic_data = efx->nic_data; 922 int rc; 923 924 #ifdef CONFIG_SFC_SRIOV 925 struct efx_ef10_nic_data *nic_data_pf; 926 struct pci_dev *pci_dev_pf; 927 struct efx_nic *efx_pf; 928 struct ef10_vf *vf; 929 930 if (efx->pci_dev->is_virtfn) { 931 pci_dev_pf = efx->pci_dev->physfn; 932 if (pci_dev_pf) { 933 efx_pf = pci_get_drvdata(pci_dev_pf); 934 nic_data_pf = efx_pf->nic_data; 935 vf = nic_data_pf->vf + nic_data->vf_index; 936 vf->efx = NULL; 937 } else 938 netif_info(efx, drv, efx->net_dev, 939 "Could not get the PF id from VF\n"); 940 } 941 #endif 942 943 efx_ef10_cleanup_vlans(efx); 944 mutex_destroy(&nic_data->vlan_lock); 945 946 efx_ptp_remove(efx); 947 948 efx_mcdi_mon_remove(efx); 949 950 efx_mcdi_rx_free_indir_table(efx); 951 952 if (nic_data->wc_membase) 953 iounmap(nic_data->wc_membase); 954 955 rc = efx_mcdi_free_vis(efx); 956 WARN_ON(rc != 0); 957 958 if (!nic_data->must_restore_piobufs) 959 efx_ef10_free_piobufs(efx); 960 961 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 962 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 963 964 efx_mcdi_detach(efx); 965 966 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 967 mutex_lock(&nic_data->udp_tunnels_lock); 968 (void)efx_ef10_set_udp_tnl_ports(efx, true); 969 mutex_unlock(&nic_data->udp_tunnels_lock); 970 971 mutex_destroy(&nic_data->udp_tunnels_lock); 972 973 efx_mcdi_fini(efx); 974 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 975 kfree(nic_data); 976 } 977 978 static int efx_ef10_probe_pf(struct efx_nic *efx) 979 { 980 return efx_ef10_probe(efx); 981 } 982 983 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id, 984 u32 *port_flags, u32 *vadaptor_flags, 985 unsigned int *vlan_tags) 986 { 987 struct efx_ef10_nic_data *nic_data = efx->nic_data; 988 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN); 989 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN); 990 size_t outlen; 991 int rc; 992 993 if (nic_data->datapath_caps & 994 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) { 995 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID, 996 port_id); 997 998 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf), 999 outbuf, sizeof(outbuf), &outlen); 1000 if (rc) 1001 return rc; 1002 1003 if (outlen < sizeof(outbuf)) { 1004 rc = -EIO; 1005 return rc; 1006 } 1007 } 1008 1009 if (port_flags) 1010 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS); 1011 if (vadaptor_flags) 1012 *vadaptor_flags = 1013 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS); 1014 if (vlan_tags) 1015 *vlan_tags = 1016 MCDI_DWORD(outbuf, 1017 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS); 1018 1019 return 0; 1020 } 1021 1022 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 1023 { 1024 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 1025 1026 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 1027 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 1028 NULL, 0, NULL); 1029 } 1030 1031 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 1032 { 1033 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 1034 1035 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 1036 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 1037 NULL, 0, NULL); 1038 } 1039 1040 int efx_ef10_vport_add_mac(struct efx_nic *efx, 1041 unsigned int port_id, const u8 *mac) 1042 { 1043 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 1044 1045 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 1046 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 1047 1048 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 1049 sizeof(inbuf), NULL, 0, NULL); 1050 } 1051 1052 int efx_ef10_vport_del_mac(struct efx_nic *efx, 1053 unsigned int port_id, const u8 *mac) 1054 { 1055 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 1056 1057 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 1058 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 1059 1060 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 1061 sizeof(inbuf), NULL, 0, NULL); 1062 } 1063 1064 #ifdef CONFIG_SFC_SRIOV 1065 static int efx_ef10_probe_vf(struct efx_nic *efx) 1066 { 1067 int rc; 1068 struct pci_dev *pci_dev_pf; 1069 1070 /* If the parent PF has no VF data structure, it doesn't know about this 1071 * VF so fail probe. The VF needs to be re-created. This can happen 1072 * if the PF driver was unloaded while any VF was assigned to a guest 1073 * (using Xen, only). 1074 */ 1075 pci_dev_pf = efx->pci_dev->physfn; 1076 if (pci_dev_pf) { 1077 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 1078 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 1079 1080 if (!nic_data_pf->vf) { 1081 netif_info(efx, drv, efx->net_dev, 1082 "The VF cannot link to its parent PF; " 1083 "please destroy and re-create the VF\n"); 1084 return -EBUSY; 1085 } 1086 } 1087 1088 rc = efx_ef10_probe(efx); 1089 if (rc) 1090 return rc; 1091 1092 rc = efx_ef10_get_vf_index(efx); 1093 if (rc) 1094 goto fail; 1095 1096 if (efx->pci_dev->is_virtfn) { 1097 if (efx->pci_dev->physfn) { 1098 struct efx_nic *efx_pf = 1099 pci_get_drvdata(efx->pci_dev->physfn); 1100 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 1101 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1102 1103 nic_data_p->vf[nic_data->vf_index].efx = efx; 1104 nic_data_p->vf[nic_data->vf_index].pci_dev = 1105 efx->pci_dev; 1106 } else 1107 netif_info(efx, drv, efx->net_dev, 1108 "Could not get the PF id from VF\n"); 1109 } 1110 1111 return 0; 1112 1113 fail: 1114 efx_ef10_remove(efx); 1115 return rc; 1116 } 1117 #else 1118 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 1119 { 1120 return 0; 1121 } 1122 #endif 1123 1124 static int efx_ef10_alloc_vis(struct efx_nic *efx, 1125 unsigned int min_vis, unsigned int max_vis) 1126 { 1127 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1128 1129 return efx_mcdi_alloc_vis(efx, min_vis, max_vis, &nic_data->vi_base, 1130 &nic_data->n_allocated_vis); 1131 } 1132 1133 /* Note that the failure path of this function does not free 1134 * resources, as this will be done by efx_ef10_remove(). 1135 */ 1136 static int efx_ef10_dimension_resources(struct efx_nic *efx) 1137 { 1138 unsigned int min_vis = max_t(unsigned int, efx->tx_queues_per_channel, 1139 efx_separate_tx_channels ? 2 : 1); 1140 unsigned int channel_vis, pio_write_vi_base, max_vis; 1141 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1142 unsigned int uc_mem_map_size, wc_mem_map_size; 1143 void __iomem *membase; 1144 int rc; 1145 1146 channel_vis = max(efx->n_channels, 1147 ((efx->n_tx_channels + efx->n_extra_tx_channels) * 1148 efx->tx_queues_per_channel) + 1149 efx->n_xdp_channels * efx->xdp_tx_per_channel); 1150 if (efx->max_vis && efx->max_vis < channel_vis) { 1151 netif_dbg(efx, drv, efx->net_dev, 1152 "Reducing channel VIs from %u to %u\n", 1153 channel_vis, efx->max_vis); 1154 channel_vis = efx->max_vis; 1155 } 1156 1157 #ifdef EFX_USE_PIO 1158 /* Try to allocate PIO buffers if wanted and if the full 1159 * number of PIO buffers would be sufficient to allocate one 1160 * copy-buffer per TX channel. Failure is non-fatal, as there 1161 * are only a small number of PIO buffers shared between all 1162 * functions of the controller. 1163 */ 1164 if (efx_piobuf_size != 0 && 1165 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 1166 efx->n_tx_channels) { 1167 unsigned int n_piobufs = 1168 DIV_ROUND_UP(efx->n_tx_channels, 1169 nic_data->piobuf_size / efx_piobuf_size); 1170 1171 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 1172 if (rc == -ENOSPC) 1173 netif_dbg(efx, probe, efx->net_dev, 1174 "out of PIO buffers; cannot allocate more\n"); 1175 else if (rc == -EPERM) 1176 netif_dbg(efx, probe, efx->net_dev, 1177 "not permitted to allocate PIO buffers\n"); 1178 else if (rc) 1179 netif_err(efx, probe, efx->net_dev, 1180 "failed to allocate PIO buffers (%d)\n", rc); 1181 else 1182 netif_dbg(efx, probe, efx->net_dev, 1183 "allocated %u PIO buffers\n", n_piobufs); 1184 } 1185 #else 1186 nic_data->n_piobufs = 0; 1187 #endif 1188 1189 /* PIO buffers should be mapped with write-combining enabled, 1190 * and we want to make single UC and WC mappings rather than 1191 * several of each (in fact that's the only option if host 1192 * page size is >4K). So we may allocate some extra VIs just 1193 * for writing PIO buffers through. 1194 * 1195 * The UC mapping contains (channel_vis - 1) complete VIs and the 1196 * first 4K of the next VI. Then the WC mapping begins with 1197 * the remainder of this last VI. 1198 */ 1199 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride + 1200 ER_DZ_TX_PIOBUF); 1201 if (nic_data->n_piobufs) { 1202 /* pio_write_vi_base rounds down to give the number of complete 1203 * VIs inside the UC mapping. 1204 */ 1205 pio_write_vi_base = uc_mem_map_size / efx->vi_stride; 1206 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 1207 nic_data->n_piobufs) * 1208 efx->vi_stride) - 1209 uc_mem_map_size); 1210 max_vis = pio_write_vi_base + nic_data->n_piobufs; 1211 } else { 1212 pio_write_vi_base = 0; 1213 wc_mem_map_size = 0; 1214 max_vis = channel_vis; 1215 } 1216 1217 /* In case the last attached driver failed to free VIs, do it now */ 1218 rc = efx_mcdi_free_vis(efx); 1219 if (rc != 0) 1220 return rc; 1221 1222 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 1223 if (rc != 0) 1224 return rc; 1225 1226 if (nic_data->n_allocated_vis < channel_vis) { 1227 netif_info(efx, drv, efx->net_dev, 1228 "Could not allocate enough VIs to satisfy RSS" 1229 " requirements. Performance may not be optimal.\n"); 1230 /* We didn't get the VIs to populate our channels. 1231 * We could keep what we got but then we'd have more 1232 * interrupts than we need. 1233 * Instead calculate new max_channels and restart 1234 */ 1235 efx->max_channels = nic_data->n_allocated_vis; 1236 efx->max_tx_channels = 1237 nic_data->n_allocated_vis / efx->tx_queues_per_channel; 1238 1239 efx_mcdi_free_vis(efx); 1240 return -EAGAIN; 1241 } 1242 1243 /* If we didn't get enough VIs to map all the PIO buffers, free the 1244 * PIO buffers 1245 */ 1246 if (nic_data->n_piobufs && 1247 nic_data->n_allocated_vis < 1248 pio_write_vi_base + nic_data->n_piobufs) { 1249 netif_dbg(efx, probe, efx->net_dev, 1250 "%u VIs are not sufficient to map %u PIO buffers\n", 1251 nic_data->n_allocated_vis, nic_data->n_piobufs); 1252 efx_ef10_free_piobufs(efx); 1253 } 1254 1255 /* Shrink the original UC mapping of the memory BAR */ 1256 membase = ioremap(efx->membase_phys, uc_mem_map_size); 1257 if (!membase) { 1258 netif_err(efx, probe, efx->net_dev, 1259 "could not shrink memory BAR to %x\n", 1260 uc_mem_map_size); 1261 return -ENOMEM; 1262 } 1263 iounmap(efx->membase); 1264 efx->membase = membase; 1265 1266 /* Set up the WC mapping if needed */ 1267 if (wc_mem_map_size) { 1268 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 1269 uc_mem_map_size, 1270 wc_mem_map_size); 1271 if (!nic_data->wc_membase) { 1272 netif_err(efx, probe, efx->net_dev, 1273 "could not allocate WC mapping of size %x\n", 1274 wc_mem_map_size); 1275 return -ENOMEM; 1276 } 1277 nic_data->pio_write_vi_base = pio_write_vi_base; 1278 nic_data->pio_write_base = 1279 nic_data->wc_membase + 1280 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF - 1281 uc_mem_map_size); 1282 1283 rc = efx_ef10_link_piobufs(efx); 1284 if (rc) 1285 efx_ef10_free_piobufs(efx); 1286 } 1287 1288 netif_dbg(efx, probe, efx->net_dev, 1289 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 1290 &efx->membase_phys, efx->membase, uc_mem_map_size, 1291 nic_data->wc_membase, wc_mem_map_size); 1292 1293 return 0; 1294 } 1295 1296 static void efx_ef10_fini_nic(struct efx_nic *efx) 1297 { 1298 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1299 1300 kfree(nic_data->mc_stats); 1301 nic_data->mc_stats = NULL; 1302 } 1303 1304 static int efx_ef10_init_nic(struct efx_nic *efx) 1305 { 1306 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1307 struct net_device *net_dev = efx->net_dev; 1308 netdev_features_t tun_feats, tso_feats; 1309 int rc; 1310 1311 if (nic_data->must_check_datapath_caps) { 1312 rc = efx_ef10_init_datapath_caps(efx); 1313 if (rc) 1314 return rc; 1315 nic_data->must_check_datapath_caps = false; 1316 } 1317 1318 if (efx->must_realloc_vis) { 1319 /* We cannot let the number of VIs change now */ 1320 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 1321 nic_data->n_allocated_vis); 1322 if (rc) 1323 return rc; 1324 efx->must_realloc_vis = false; 1325 } 1326 1327 nic_data->mc_stats = kmalloc(efx->num_mac_stats * sizeof(__le64), 1328 GFP_KERNEL); 1329 if (!nic_data->mc_stats) 1330 return -ENOMEM; 1331 1332 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 1333 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 1334 if (rc == 0) { 1335 rc = efx_ef10_link_piobufs(efx); 1336 if (rc) 1337 efx_ef10_free_piobufs(efx); 1338 } 1339 1340 /* Log an error on failure, but this is non-fatal. 1341 * Permission errors are less important - we've presumably 1342 * had the PIO buffer licence removed. 1343 */ 1344 if (rc == -EPERM) 1345 netif_dbg(efx, drv, efx->net_dev, 1346 "not permitted to restore PIO buffers\n"); 1347 else if (rc) 1348 netif_err(efx, drv, efx->net_dev, 1349 "failed to restore PIO buffers (%d)\n", rc); 1350 nic_data->must_restore_piobufs = false; 1351 } 1352 1353 /* encap features might change during reset if fw variant changed */ 1354 if (efx_has_cap(efx, VXLAN_NVGRE) && !efx_ef10_is_vf(efx)) 1355 net_dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1356 else 1357 net_dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 1358 1359 tun_feats = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 1360 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM; 1361 tso_feats = NETIF_F_TSO | NETIF_F_TSO6; 1362 1363 if (efx_has_cap(efx, TX_TSO_V2_ENCAP)) { 1364 /* If this is first nic_init, or if it is a reset and a new fw 1365 * variant has added new features, enable them by default. 1366 * If the features are not new, maintain their current value. 1367 */ 1368 if (!(net_dev->hw_features & tun_feats)) 1369 net_dev->features |= tun_feats; 1370 net_dev->hw_enc_features |= tun_feats | tso_feats; 1371 net_dev->hw_features |= tun_feats; 1372 } else { 1373 net_dev->hw_enc_features &= ~(tun_feats | tso_feats); 1374 net_dev->hw_features &= ~tun_feats; 1375 net_dev->features &= ~tun_feats; 1376 } 1377 1378 /* don't fail init if RSS setup doesn't work */ 1379 rc = efx->type->rx_push_rss_config(efx, false, 1380 efx->rss_context.rx_indir_table, NULL); 1381 1382 return 0; 1383 } 1384 1385 static void efx_ef10_table_reset_mc_allocations(struct efx_nic *efx) 1386 { 1387 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1388 #ifdef CONFIG_SFC_SRIOV 1389 unsigned int i; 1390 #endif 1391 1392 /* All our allocations have been reset */ 1393 efx->must_realloc_vis = true; 1394 efx_mcdi_filter_table_reset_mc_allocations(efx); 1395 nic_data->must_restore_piobufs = true; 1396 efx_ef10_forget_old_piobufs(efx); 1397 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID; 1398 1399 /* Driver-created vswitches and vports must be re-created */ 1400 nic_data->must_probe_vswitching = true; 1401 efx->vport_id = EVB_PORT_ID_ASSIGNED; 1402 #ifdef CONFIG_SFC_SRIOV 1403 if (nic_data->vf) 1404 for (i = 0; i < efx->vf_count; i++) 1405 nic_data->vf[i].vport_id = 0; 1406 #endif 1407 } 1408 1409 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1410 { 1411 if (reason == RESET_TYPE_MC_FAILURE) 1412 return RESET_TYPE_DATAPATH; 1413 1414 return efx_mcdi_map_reset_reason(reason); 1415 } 1416 1417 static int efx_ef10_map_reset_flags(u32 *flags) 1418 { 1419 enum { 1420 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1421 ETH_RESET_SHARED_SHIFT), 1422 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1423 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1424 ETH_RESET_PHY | ETH_RESET_MGMT) << 1425 ETH_RESET_SHARED_SHIFT) 1426 }; 1427 1428 /* We assume for now that our PCI function is permitted to 1429 * reset everything. 1430 */ 1431 1432 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1433 *flags &= ~EF10_RESET_MC; 1434 return RESET_TYPE_WORLD; 1435 } 1436 1437 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1438 *flags &= ~EF10_RESET_PORT; 1439 return RESET_TYPE_ALL; 1440 } 1441 1442 /* no invisible reset implemented */ 1443 1444 return -EINVAL; 1445 } 1446 1447 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1448 { 1449 int rc = efx_mcdi_reset(efx, reset_type); 1450 1451 /* Unprivileged functions return -EPERM, but need to return success 1452 * here so that the datapath is brought back up. 1453 */ 1454 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1455 rc = 0; 1456 1457 /* If it was a port reset, trigger reallocation of MC resources. 1458 * Note that on an MC reset nothing needs to be done now because we'll 1459 * detect the MC reset later and handle it then. 1460 * For an FLR, we never get an MC reset event, but the MC has reset all 1461 * resources assigned to us, so we have to trigger reallocation now. 1462 */ 1463 if ((reset_type == RESET_TYPE_ALL || 1464 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1465 efx_ef10_table_reset_mc_allocations(efx); 1466 return rc; 1467 } 1468 1469 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1470 [EF10_STAT_ ## ext_name] = \ 1471 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1472 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1473 [EF10_STAT_ ## int_name] = \ 1474 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1475 #define EF10_OTHER_STAT(ext_name) \ 1476 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1477 1478 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1479 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1480 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1481 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1482 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1483 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1484 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1485 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1486 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1487 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1488 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1489 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1490 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1491 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1492 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1493 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1494 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1495 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1496 EF10_OTHER_STAT(port_rx_good_bytes), 1497 EF10_OTHER_STAT(port_rx_bad_bytes), 1498 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1499 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1500 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1501 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1502 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1503 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1504 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1505 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1506 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1507 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1508 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1509 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1510 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1511 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1512 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1513 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1514 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1515 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1516 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1517 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1518 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1519 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1520 EFX_GENERIC_SW_STAT(rx_nodesc_trunc), 1521 EFX_GENERIC_SW_STAT(rx_noskb_drops), 1522 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1523 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1524 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1525 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1526 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1527 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1528 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1529 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1530 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1531 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1532 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1533 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1534 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1535 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1536 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1537 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1538 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1539 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1540 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1541 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1542 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1543 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1544 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1545 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1546 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1547 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1548 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1549 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1550 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1551 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1552 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS), 1553 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS), 1554 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0), 1555 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1), 1556 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2), 1557 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3), 1558 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK), 1559 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS), 1560 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL), 1561 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL), 1562 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL), 1563 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL), 1564 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL), 1565 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL), 1566 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL), 1567 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK), 1568 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK), 1569 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK), 1570 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS), 1571 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK), 1572 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON), 1573 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE), 1574 }; 1575 1576 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1577 (1ULL << EF10_STAT_port_tx_packets) | \ 1578 (1ULL << EF10_STAT_port_tx_pause) | \ 1579 (1ULL << EF10_STAT_port_tx_unicast) | \ 1580 (1ULL << EF10_STAT_port_tx_multicast) | \ 1581 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1582 (1ULL << EF10_STAT_port_rx_bytes) | \ 1583 (1ULL << \ 1584 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1585 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1586 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1587 (1ULL << EF10_STAT_port_rx_packets) | \ 1588 (1ULL << EF10_STAT_port_rx_good) | \ 1589 (1ULL << EF10_STAT_port_rx_bad) | \ 1590 (1ULL << EF10_STAT_port_rx_pause) | \ 1591 (1ULL << EF10_STAT_port_rx_control) | \ 1592 (1ULL << EF10_STAT_port_rx_unicast) | \ 1593 (1ULL << EF10_STAT_port_rx_multicast) | \ 1594 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1595 (1ULL << EF10_STAT_port_rx_lt64) | \ 1596 (1ULL << EF10_STAT_port_rx_64) | \ 1597 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1598 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1599 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1600 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1601 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1602 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1603 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1604 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1605 (1ULL << EF10_STAT_port_rx_overflow) | \ 1606 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1607 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1608 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1609 1610 /* On 7000 series NICs, these statistics are only provided by the 10G MAC. 1611 * For a 10G/40G switchable port we do not expose these because they might 1612 * not include all the packets they should. 1613 * On 8000 series NICs these statistics are always provided. 1614 */ 1615 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1616 (1ULL << EF10_STAT_port_tx_lt64) | \ 1617 (1ULL << EF10_STAT_port_tx_64) | \ 1618 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1619 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1620 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1621 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1622 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1623 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1624 1625 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1626 * switchable port we do expose these because the errors will otherwise 1627 * be silent. 1628 */ 1629 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1630 (1ULL << EF10_STAT_port_rx_length_error)) 1631 1632 /* These statistics are only provided if the firmware supports the 1633 * capability PM_AND_RXDP_COUNTERS. 1634 */ 1635 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1636 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1637 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1638 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1639 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1640 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1641 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1642 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1643 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1644 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1645 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1646 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1647 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1648 1649 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2, 1650 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in 1651 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1652 * These bits are in the second u64 of the raw mask. 1653 */ 1654 #define EF10_FEC_STAT_MASK ( \ 1655 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \ 1656 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \ 1657 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \ 1658 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \ 1659 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \ 1660 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64))) 1661 1662 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3, 1663 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in 1664 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1665 * These bits are in the second u64 of the raw mask. 1666 */ 1667 #define EF10_CTPIO_STAT_MASK ( \ 1668 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \ 1669 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \ 1670 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \ 1671 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \ 1672 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \ 1673 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \ 1674 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \ 1675 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \ 1676 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \ 1677 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \ 1678 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \ 1679 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \ 1680 (1ULL << (EF10_STAT_ctpio_success - 64)) | \ 1681 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \ 1682 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \ 1683 (1ULL << (EF10_STAT_ctpio_erase - 64))) 1684 1685 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1686 { 1687 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1688 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1689 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1690 1691 if (!(efx->mcdi->fn_flags & 1692 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1693 return 0; 1694 1695 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) { 1696 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1697 /* 8000 series have everything even at 40G */ 1698 if (nic_data->datapath_caps2 & 1699 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN)) 1700 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1701 } else { 1702 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1703 } 1704 1705 if (nic_data->datapath_caps & 1706 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1707 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1708 1709 return raw_mask; 1710 } 1711 1712 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1713 { 1714 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1715 u64 raw_mask[2]; 1716 1717 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1718 1719 /* Only show vadaptor stats when EVB capability is present */ 1720 if (nic_data->datapath_caps & 1721 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1722 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1723 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1; 1724 } else { 1725 raw_mask[1] = 0; 1726 } 1727 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */ 1728 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2) 1729 raw_mask[1] |= EF10_FEC_STAT_MASK; 1730 1731 /* CTPIO stats appear in V3. Only show them on devices that actually 1732 * support CTPIO. Although this driver doesn't use CTPIO others might, 1733 * and we may be reporting the stats for the underlying port. 1734 */ 1735 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 && 1736 (nic_data->datapath_caps2 & 1737 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN))) 1738 raw_mask[1] |= EF10_CTPIO_STAT_MASK; 1739 1740 #if BITS_PER_LONG == 64 1741 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2); 1742 mask[0] = raw_mask[0]; 1743 mask[1] = raw_mask[1]; 1744 #else 1745 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3); 1746 mask[0] = raw_mask[0] & 0xffffffff; 1747 mask[1] = raw_mask[0] >> 32; 1748 mask[2] = raw_mask[1] & 0xffffffff; 1749 #endif 1750 } 1751 1752 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1753 { 1754 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1755 1756 efx_ef10_get_stat_mask(efx, mask); 1757 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1758 mask, names); 1759 } 1760 1761 static void efx_ef10_get_fec_stats(struct efx_nic *efx, 1762 struct ethtool_fec_stats *fec_stats) 1763 { 1764 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1765 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1766 u64 *stats = nic_data->stats; 1767 1768 efx_ef10_get_stat_mask(efx, mask); 1769 if (test_bit(EF10_STAT_fec_corrected_errors, mask)) 1770 fec_stats->corrected_blocks.total = 1771 stats[EF10_STAT_fec_corrected_errors]; 1772 if (test_bit(EF10_STAT_fec_uncorrected_errors, mask)) 1773 fec_stats->uncorrectable_blocks.total = 1774 stats[EF10_STAT_fec_uncorrected_errors]; 1775 } 1776 1777 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1778 struct rtnl_link_stats64 *core_stats) 1779 { 1780 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1781 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1782 u64 *stats = nic_data->stats; 1783 size_t stats_count = 0, index; 1784 1785 efx_ef10_get_stat_mask(efx, mask); 1786 1787 if (full_stats) { 1788 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1789 if (efx_ef10_stat_desc[index].name) { 1790 *full_stats++ = stats[index]; 1791 ++stats_count; 1792 } 1793 } 1794 } 1795 1796 if (!core_stats) 1797 return stats_count; 1798 1799 if (nic_data->datapath_caps & 1800 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1801 /* Use vadaptor stats. */ 1802 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1803 stats[EF10_STAT_rx_multicast] + 1804 stats[EF10_STAT_rx_broadcast]; 1805 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1806 stats[EF10_STAT_tx_multicast] + 1807 stats[EF10_STAT_tx_broadcast]; 1808 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1809 stats[EF10_STAT_rx_multicast_bytes] + 1810 stats[EF10_STAT_rx_broadcast_bytes]; 1811 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1812 stats[EF10_STAT_tx_multicast_bytes] + 1813 stats[EF10_STAT_tx_broadcast_bytes]; 1814 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1815 stats[GENERIC_STAT_rx_noskb_drops]; 1816 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1817 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1818 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1819 core_stats->rx_errors = core_stats->rx_crc_errors; 1820 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1821 } else { 1822 /* Use port stats. */ 1823 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1824 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1825 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1826 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1827 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1828 stats[GENERIC_STAT_rx_nodesc_trunc] + 1829 stats[GENERIC_STAT_rx_noskb_drops]; 1830 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1831 core_stats->rx_length_errors = 1832 stats[EF10_STAT_port_rx_gtjumbo] + 1833 stats[EF10_STAT_port_rx_length_error]; 1834 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1835 core_stats->rx_frame_errors = 1836 stats[EF10_STAT_port_rx_align_error]; 1837 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1838 core_stats->rx_errors = (core_stats->rx_length_errors + 1839 core_stats->rx_crc_errors + 1840 core_stats->rx_frame_errors); 1841 } 1842 1843 return stats_count; 1844 } 1845 1846 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1847 struct rtnl_link_stats64 *core_stats) 1848 { 1849 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1850 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1851 u64 *stats = nic_data->stats; 1852 1853 efx_ef10_get_stat_mask(efx, mask); 1854 1855 efx_nic_copy_stats(efx, nic_data->mc_stats); 1856 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1857 mask, stats, nic_data->mc_stats, false); 1858 1859 /* Update derived statistics */ 1860 efx_nic_fix_nodesc_drop_stat(efx, 1861 &stats[EF10_STAT_port_rx_nodesc_drops]); 1862 /* MC Firmware reads RX_BYTES and RX_GOOD_BYTES from the MAC. 1863 * It then calculates RX_BAD_BYTES and DMAs it to us with RX_BYTES. 1864 * We report these as port_rx_ stats. We are not given RX_GOOD_BYTES. 1865 * Here we calculate port_rx_good_bytes. 1866 */ 1867 stats[EF10_STAT_port_rx_good_bytes] = 1868 stats[EF10_STAT_port_rx_bytes] - 1869 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1870 1871 /* The asynchronous reads used to calculate RX_BAD_BYTES in 1872 * MC Firmware are done such that we should not see an increase in 1873 * RX_BAD_BYTES when a good packet has arrived. Unfortunately this 1874 * does mean that the stat can decrease at times. Here we do not 1875 * update the stat unless it has increased or has gone to zero 1876 * (In the case of the NIC rebooting). 1877 * Please see Bug 33781 for a discussion of why things work this way. 1878 */ 1879 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1880 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1881 efx_update_sw_stats(efx, stats); 1882 1883 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1884 } 1885 1886 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1887 __must_hold(&efx->stats_lock) 1888 { 1889 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1890 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1891 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1892 __le64 generation_start, generation_end; 1893 u64 *stats = nic_data->stats; 1894 u32 dma_len = efx->num_mac_stats * sizeof(u64); 1895 struct efx_buffer stats_buf; 1896 __le64 *dma_stats; 1897 int rc; 1898 1899 spin_unlock_bh(&efx->stats_lock); 1900 1901 efx_ef10_get_stat_mask(efx, mask); 1902 1903 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_KERNEL); 1904 if (rc) { 1905 spin_lock_bh(&efx->stats_lock); 1906 return rc; 1907 } 1908 1909 dma_stats = stats_buf.addr; 1910 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID; 1911 1912 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1913 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1914 MAC_STATS_IN_DMA, 1); 1915 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1916 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1917 1918 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1919 NULL, 0, NULL); 1920 spin_lock_bh(&efx->stats_lock); 1921 if (rc) { 1922 /* Expect ENOENT if DMA queues have not been set up */ 1923 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1924 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1925 sizeof(inbuf), NULL, 0, rc); 1926 goto out; 1927 } 1928 1929 generation_end = dma_stats[efx->num_mac_stats - 1]; 1930 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1931 WARN_ON_ONCE(1); 1932 goto out; 1933 } 1934 rmb(); 1935 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1936 stats, stats_buf.addr, false); 1937 rmb(); 1938 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1939 if (generation_end != generation_start) { 1940 rc = -EAGAIN; 1941 goto out; 1942 } 1943 1944 efx_update_sw_stats(efx, stats); 1945 out: 1946 /* releasing a DMA coherent buffer with BH disabled can panic */ 1947 spin_unlock_bh(&efx->stats_lock); 1948 efx_nic_free_buffer(efx, &stats_buf); 1949 spin_lock_bh(&efx->stats_lock); 1950 return rc; 1951 } 1952 1953 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1954 struct rtnl_link_stats64 *core_stats) 1955 { 1956 if (efx_ef10_try_update_nic_stats_vf(efx)) 1957 return 0; 1958 1959 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1960 } 1961 1962 static size_t efx_ef10_update_stats_atomic_vf(struct efx_nic *efx, u64 *full_stats, 1963 struct rtnl_link_stats64 *core_stats) 1964 { 1965 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1966 1967 /* In atomic context, cannot update HW stats. Just update the 1968 * software stats and return so the caller can continue. 1969 */ 1970 efx_update_sw_stats(efx, nic_data->stats); 1971 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1972 } 1973 1974 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1975 { 1976 struct efx_nic *efx = channel->efx; 1977 unsigned int mode, usecs; 1978 efx_dword_t timer_cmd; 1979 1980 if (channel->irq_moderation_us) { 1981 mode = 3; 1982 usecs = channel->irq_moderation_us; 1983 } else { 1984 mode = 0; 1985 usecs = 0; 1986 } 1987 1988 if (EFX_EF10_WORKAROUND_61265(efx)) { 1989 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN); 1990 unsigned int ns = usecs * 1000; 1991 1992 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE, 1993 channel->channel); 1994 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns); 1995 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns); 1996 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode); 1997 1998 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR, 1999 inbuf, sizeof(inbuf), 0, NULL, 0); 2000 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 2001 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 2002 2003 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 2004 EFE_DD_EVQ_IND_TIMER_FLAGS, 2005 ERF_DD_EVQ_IND_TIMER_MODE, mode, 2006 ERF_DD_EVQ_IND_TIMER_VAL, ticks); 2007 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 2008 channel->channel); 2009 } else { 2010 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 2011 2012 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 2013 ERF_DZ_TC_TIMER_VAL, ticks, 2014 ERF_FZ_TC_TMR_REL_VAL, ticks); 2015 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 2016 channel->channel); 2017 } 2018 } 2019 2020 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 2021 struct ethtool_wolinfo *wol) {} 2022 2023 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 2024 { 2025 return -EOPNOTSUPP; 2026 } 2027 2028 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 2029 { 2030 wol->supported = 0; 2031 wol->wolopts = 0; 2032 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2033 } 2034 2035 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 2036 { 2037 if (type != 0) 2038 return -EINVAL; 2039 return 0; 2040 } 2041 2042 static void efx_ef10_mcdi_request(struct efx_nic *efx, 2043 const efx_dword_t *hdr, size_t hdr_len, 2044 const efx_dword_t *sdu, size_t sdu_len) 2045 { 2046 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2047 u8 *pdu = nic_data->mcdi_buf.addr; 2048 2049 memcpy(pdu, hdr, hdr_len); 2050 memcpy(pdu + hdr_len, sdu, sdu_len); 2051 wmb(); 2052 2053 /* The hardware provides 'low' and 'high' (doorbell) registers 2054 * for passing the 64-bit address of an MCDI request to 2055 * firmware. However the dwords are swapped by firmware. The 2056 * least significant bits of the doorbell are then 0 for all 2057 * MCDI requests due to alignment. 2058 */ 2059 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 2060 ER_DZ_MC_DB_LWRD); 2061 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 2062 ER_DZ_MC_DB_HWRD); 2063 } 2064 2065 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 2066 { 2067 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2068 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 2069 2070 rmb(); 2071 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 2072 } 2073 2074 static void 2075 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 2076 size_t offset, size_t outlen) 2077 { 2078 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2079 const u8 *pdu = nic_data->mcdi_buf.addr; 2080 2081 memcpy(outbuf, pdu + offset, outlen); 2082 } 2083 2084 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 2085 { 2086 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2087 2088 /* All our allocations have been reset */ 2089 efx_ef10_table_reset_mc_allocations(efx); 2090 2091 /* The datapath firmware might have been changed */ 2092 nic_data->must_check_datapath_caps = true; 2093 2094 /* MAC statistics have been cleared on the NIC; clear the local 2095 * statistic that we update with efx_update_diff_stat(). 2096 */ 2097 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 2098 } 2099 2100 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 2101 { 2102 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2103 int rc; 2104 2105 rc = efx_ef10_get_warm_boot_count(efx); 2106 if (rc < 0) { 2107 /* The firmware is presumably in the process of 2108 * rebooting. However, we are supposed to report each 2109 * reboot just once, so we must only do that once we 2110 * can read and store the updated warm boot count. 2111 */ 2112 return 0; 2113 } 2114 2115 if (rc == nic_data->warm_boot_count) 2116 return 0; 2117 2118 nic_data->warm_boot_count = rc; 2119 efx_ef10_mcdi_reboot_detected(efx); 2120 2121 return -EIO; 2122 } 2123 2124 /* Handle an MSI interrupt 2125 * 2126 * Handle an MSI hardware interrupt. This routine schedules event 2127 * queue processing. No interrupt acknowledgement cycle is necessary. 2128 * Also, we never need to check that the interrupt is for us, since 2129 * MSI interrupts cannot be shared. 2130 */ 2131 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 2132 { 2133 struct efx_msi_context *context = dev_id; 2134 struct efx_nic *efx = context->efx; 2135 2136 netif_vdbg(efx, intr, efx->net_dev, 2137 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 2138 2139 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 2140 /* Note test interrupts */ 2141 if (context->index == efx->irq_level) 2142 efx->last_irq_cpu = raw_smp_processor_id(); 2143 2144 /* Schedule processing of the channel */ 2145 efx_schedule_channel_irq(efx->channel[context->index]); 2146 } 2147 2148 return IRQ_HANDLED; 2149 } 2150 2151 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 2152 { 2153 struct efx_nic *efx = dev_id; 2154 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled); 2155 struct efx_channel *channel; 2156 efx_dword_t reg; 2157 u32 queues; 2158 2159 /* Read the ISR which also ACKs the interrupts */ 2160 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 2161 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 2162 2163 if (queues == 0) 2164 return IRQ_NONE; 2165 2166 if (likely(soft_enabled)) { 2167 /* Note test interrupts */ 2168 if (queues & (1U << efx->irq_level)) 2169 efx->last_irq_cpu = raw_smp_processor_id(); 2170 2171 efx_for_each_channel(channel, efx) { 2172 if (queues & 1) 2173 efx_schedule_channel_irq(channel); 2174 queues >>= 1; 2175 } 2176 } 2177 2178 netif_vdbg(efx, intr, efx->net_dev, 2179 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 2180 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 2181 2182 return IRQ_HANDLED; 2183 } 2184 2185 static int efx_ef10_irq_test_generate(struct efx_nic *efx) 2186 { 2187 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 2188 2189 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true, 2190 NULL) == 0) 2191 return -ENOTSUPP; 2192 2193 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 2194 2195 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 2196 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 2197 inbuf, sizeof(inbuf), NULL, 0, NULL); 2198 } 2199 2200 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 2201 { 2202 /* low two bits of label are what we want for type */ 2203 BUILD_BUG_ON((EFX_TXQ_TYPE_OUTER_CSUM | EFX_TXQ_TYPE_INNER_CSUM) != 3); 2204 tx_queue->type = tx_queue->label & 3; 2205 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 2206 (tx_queue->ptr_mask + 1) * 2207 sizeof(efx_qword_t), 2208 GFP_KERNEL); 2209 } 2210 2211 /* This writes to the TX_DESC_WPTR and also pushes data */ 2212 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 2213 const efx_qword_t *txd) 2214 { 2215 unsigned int write_ptr; 2216 efx_oword_t reg; 2217 2218 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2219 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 2220 reg.qword[0] = *txd; 2221 efx_writeo_page(tx_queue->efx, ®, 2222 ER_DZ_TX_DESC_UPD, tx_queue->queue); 2223 } 2224 2225 /* Add Firmware-Assisted TSO v2 option descriptors to a queue. 2226 */ 2227 int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 2228 bool *data_mapped) 2229 { 2230 struct efx_tx_buffer *buffer; 2231 u16 inner_ipv4_id = 0; 2232 u16 outer_ipv4_id = 0; 2233 struct tcphdr *tcp; 2234 struct iphdr *ip; 2235 u16 ip_tot_len; 2236 u32 seqnum; 2237 u32 mss; 2238 2239 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2); 2240 2241 mss = skb_shinfo(skb)->gso_size; 2242 2243 if (unlikely(mss < 4)) { 2244 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss); 2245 return -EINVAL; 2246 } 2247 2248 if (skb->encapsulation) { 2249 if (!tx_queue->tso_encap) 2250 return -EINVAL; 2251 ip = ip_hdr(skb); 2252 if (ip->version == 4) 2253 outer_ipv4_id = ntohs(ip->id); 2254 2255 ip = inner_ip_hdr(skb); 2256 tcp = inner_tcp_hdr(skb); 2257 } else { 2258 ip = ip_hdr(skb); 2259 tcp = tcp_hdr(skb); 2260 } 2261 2262 /* 8000-series EF10 hardware requires that IP Total Length be 2263 * greater than or equal to the value it will have in each segment 2264 * (which is at most mss + 208 + TCP header length), but also less 2265 * than (0x10000 - inner_network_header). Otherwise the TCP 2266 * checksum calculation will be broken for encapsulated packets. 2267 * We fill in ip->tot_len with 0xff30, which should satisfy the 2268 * first requirement unless the MSS is ridiculously large (which 2269 * should be impossible as the driver max MTU is 9216); it is 2270 * guaranteed to satisfy the second as we only attempt TSO if 2271 * inner_network_header <= 208. 2272 */ 2273 ip_tot_len = 0x10000 - EFX_TSO2_MAX_HDRLEN; 2274 EFX_WARN_ON_ONCE_PARANOID(mss + EFX_TSO2_MAX_HDRLEN + 2275 (tcp->doff << 2u) > ip_tot_len); 2276 2277 if (ip->version == 4) { 2278 ip->tot_len = htons(ip_tot_len); 2279 ip->check = 0; 2280 inner_ipv4_id = ntohs(ip->id); 2281 } else { 2282 ((struct ipv6hdr *)ip)->payload_len = htons(ip_tot_len); 2283 } 2284 2285 seqnum = ntohl(tcp->seq); 2286 2287 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2288 2289 buffer->flags = EFX_TX_BUF_OPTION; 2290 buffer->len = 0; 2291 buffer->unmap_len = 0; 2292 EFX_POPULATE_QWORD_5(buffer->option, 2293 ESF_DZ_TX_DESC_IS_OPT, 1, 2294 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2295 ESF_DZ_TX_TSO_OPTION_TYPE, 2296 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A, 2297 ESF_DZ_TX_TSO_IP_ID, inner_ipv4_id, 2298 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum 2299 ); 2300 ++tx_queue->insert_count; 2301 2302 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2303 2304 buffer->flags = EFX_TX_BUF_OPTION; 2305 buffer->len = 0; 2306 buffer->unmap_len = 0; 2307 EFX_POPULATE_QWORD_5(buffer->option, 2308 ESF_DZ_TX_DESC_IS_OPT, 1, 2309 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2310 ESF_DZ_TX_TSO_OPTION_TYPE, 2311 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B, 2312 ESF_DZ_TX_TSO_OUTER_IPID, outer_ipv4_id, 2313 ESF_DZ_TX_TSO_TCP_MSS, mss 2314 ); 2315 ++tx_queue->insert_count; 2316 2317 return 0; 2318 } 2319 2320 static u32 efx_ef10_tso_versions(struct efx_nic *efx) 2321 { 2322 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2323 u32 tso_versions = 0; 2324 2325 if (nic_data->datapath_caps & 2326 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) 2327 tso_versions |= BIT(1); 2328 if (nic_data->datapath_caps2 & 2329 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) 2330 tso_versions |= BIT(2); 2331 return tso_versions; 2332 } 2333 2334 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 2335 { 2336 bool csum_offload = tx_queue->type & EFX_TXQ_TYPE_OUTER_CSUM; 2337 bool inner_csum = tx_queue->type & EFX_TXQ_TYPE_INNER_CSUM; 2338 struct efx_channel *channel = tx_queue->channel; 2339 struct efx_nic *efx = tx_queue->efx; 2340 struct efx_ef10_nic_data *nic_data; 2341 efx_qword_t *txd; 2342 int rc; 2343 2344 nic_data = efx->nic_data; 2345 2346 /* Only attempt to enable TX timestamping if we have the license for it, 2347 * otherwise TXQ init will fail 2348 */ 2349 if (!(nic_data->licensed_features & 2350 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) { 2351 tx_queue->timestamping = false; 2352 /* Disable sync events on this channel. */ 2353 if (efx->type->ptp_set_ts_sync_events) 2354 efx->type->ptp_set_ts_sync_events(efx, false, false); 2355 } 2356 2357 /* TSOv2 is a limited resource that can only be configured on a limited 2358 * number of queues. TSO without checksum offload is not really a thing, 2359 * so we only enable it for those queues. 2360 * TSOv2 cannot be used with Hardware timestamping, and is never needed 2361 * for XDP tx. 2362 */ 2363 if (efx_has_cap(efx, TX_TSO_V2)) { 2364 if ((csum_offload || inner_csum) && 2365 !tx_queue->timestamping && !tx_queue->xdp_tx) { 2366 tx_queue->tso_version = 2; 2367 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n", 2368 channel->channel); 2369 } 2370 } else if (efx_has_cap(efx, TX_TSO)) { 2371 tx_queue->tso_version = 1; 2372 } 2373 2374 rc = efx_mcdi_tx_init(tx_queue); 2375 if (rc) 2376 goto fail; 2377 2378 /* A previous user of this TX queue might have set us up the 2379 * bomb by writing a descriptor to the TX push collector but 2380 * not the doorbell. (Each collector belongs to a port, not a 2381 * queue or function, so cannot easily be reset.) We must 2382 * attempt to push a no-op descriptor in its place. 2383 */ 2384 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 2385 tx_queue->insert_count = 1; 2386 txd = efx_tx_desc(tx_queue, 0); 2387 EFX_POPULATE_QWORD_7(*txd, 2388 ESF_DZ_TX_DESC_IS_OPT, true, 2389 ESF_DZ_TX_OPTION_TYPE, 2390 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 2391 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 2392 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload && tx_queue->tso_version != 2, 2393 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM, inner_csum, 2394 ESF_DZ_TX_OPTION_INNER_IP_CSUM, inner_csum && tx_queue->tso_version != 2, 2395 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping); 2396 tx_queue->write_count = 1; 2397 2398 if (tx_queue->tso_version == 2 && efx_has_cap(efx, TX_TSO_V2_ENCAP)) 2399 tx_queue->tso_encap = true; 2400 2401 wmb(); 2402 efx_ef10_push_tx_desc(tx_queue, txd); 2403 2404 return; 2405 2406 fail: 2407 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 2408 tx_queue->queue); 2409 } 2410 2411 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 2412 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 2413 { 2414 unsigned int write_ptr; 2415 efx_dword_t reg; 2416 2417 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2418 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 2419 efx_writed_page(tx_queue->efx, ®, 2420 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 2421 } 2422 2423 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff 2424 2425 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue, 2426 dma_addr_t dma_addr, unsigned int len) 2427 { 2428 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) { 2429 /* If we need to break across multiple descriptors we should 2430 * stop at a page boundary. This assumes the length limit is 2431 * greater than the page size. 2432 */ 2433 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN; 2434 2435 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE); 2436 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr; 2437 } 2438 2439 return len; 2440 } 2441 2442 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 2443 { 2444 unsigned int old_write_count = tx_queue->write_count; 2445 struct efx_tx_buffer *buffer; 2446 unsigned int write_ptr; 2447 efx_qword_t *txd; 2448 2449 tx_queue->xmit_pending = false; 2450 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 2451 return; 2452 2453 do { 2454 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2455 buffer = &tx_queue->buffer[write_ptr]; 2456 txd = efx_tx_desc(tx_queue, write_ptr); 2457 ++tx_queue->write_count; 2458 2459 /* Create TX descriptor ring entry */ 2460 if (buffer->flags & EFX_TX_BUF_OPTION) { 2461 *txd = buffer->option; 2462 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1) 2463 /* PIO descriptor */ 2464 tx_queue->packet_write_count = tx_queue->write_count; 2465 } else { 2466 tx_queue->packet_write_count = tx_queue->write_count; 2467 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 2468 EFX_POPULATE_QWORD_3( 2469 *txd, 2470 ESF_DZ_TX_KER_CONT, 2471 buffer->flags & EFX_TX_BUF_CONT, 2472 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 2473 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 2474 } 2475 } while (tx_queue->write_count != tx_queue->insert_count); 2476 2477 wmb(); /* Ensure descriptors are written before they are fetched */ 2478 2479 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 2480 txd = efx_tx_desc(tx_queue, 2481 old_write_count & tx_queue->ptr_mask); 2482 efx_ef10_push_tx_desc(tx_queue, txd); 2483 ++tx_queue->pushes; 2484 } else { 2485 efx_ef10_notify_tx_desc(tx_queue); 2486 } 2487 } 2488 2489 static int efx_ef10_probe_multicast_chaining(struct efx_nic *efx) 2490 { 2491 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2492 unsigned int enabled, implemented; 2493 bool want_workaround_26807; 2494 int rc; 2495 2496 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2497 if (rc == -ENOSYS) { 2498 /* GET_WORKAROUNDS was implemented before this workaround, 2499 * thus it must be unavailable in this firmware. 2500 */ 2501 nic_data->workaround_26807 = false; 2502 return 0; 2503 } 2504 if (rc) 2505 return rc; 2506 want_workaround_26807 = 2507 implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807; 2508 nic_data->workaround_26807 = 2509 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2510 2511 if (want_workaround_26807 && !nic_data->workaround_26807) { 2512 unsigned int flags; 2513 2514 rc = efx_mcdi_set_workaround(efx, 2515 MC_CMD_WORKAROUND_BUG26807, 2516 true, &flags); 2517 if (!rc) { 2518 if (flags & 2519 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2520 netif_info(efx, drv, efx->net_dev, 2521 "other functions on NIC have been reset\n"); 2522 2523 /* With MCFW v4.6.x and earlier, the 2524 * boot count will have incremented, 2525 * so re-read the warm_boot_count 2526 * value now to ensure this function 2527 * doesn't think it has changed next 2528 * time it checks. 2529 */ 2530 rc = efx_ef10_get_warm_boot_count(efx); 2531 if (rc >= 0) { 2532 nic_data->warm_boot_count = rc; 2533 rc = 0; 2534 } 2535 } 2536 nic_data->workaround_26807 = true; 2537 } else if (rc == -EPERM) { 2538 rc = 0; 2539 } 2540 } 2541 return rc; 2542 } 2543 2544 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 2545 { 2546 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2547 int rc = efx_ef10_probe_multicast_chaining(efx); 2548 struct efx_mcdi_filter_vlan *vlan; 2549 2550 if (rc) 2551 return rc; 2552 down_write(&efx->filter_sem); 2553 rc = efx_mcdi_filter_table_probe(efx, nic_data->workaround_26807); 2554 2555 if (rc) 2556 goto out_unlock; 2557 2558 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 2559 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 2560 if (rc) 2561 goto fail_add_vlan; 2562 } 2563 goto out_unlock; 2564 2565 fail_add_vlan: 2566 efx_mcdi_filter_table_remove(efx); 2567 out_unlock: 2568 up_write(&efx->filter_sem); 2569 return rc; 2570 } 2571 2572 static void efx_ef10_filter_table_remove(struct efx_nic *efx) 2573 { 2574 down_write(&efx->filter_sem); 2575 efx_mcdi_filter_table_remove(efx); 2576 up_write(&efx->filter_sem); 2577 } 2578 2579 /* This creates an entry in the RX descriptor queue */ 2580 static inline void 2581 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2582 { 2583 struct efx_rx_buffer *rx_buf; 2584 efx_qword_t *rxd; 2585 2586 rxd = efx_rx_desc(rx_queue, index); 2587 rx_buf = efx_rx_buffer(rx_queue, index); 2588 EFX_POPULATE_QWORD_2(*rxd, 2589 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2590 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2591 } 2592 2593 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2594 { 2595 struct efx_nic *efx = rx_queue->efx; 2596 unsigned int write_count; 2597 efx_dword_t reg; 2598 2599 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2600 write_count = rx_queue->added_count & ~7; 2601 if (rx_queue->notified_count == write_count) 2602 return; 2603 2604 do 2605 efx_ef10_build_rx_desc( 2606 rx_queue, 2607 rx_queue->notified_count & rx_queue->ptr_mask); 2608 while (++rx_queue->notified_count != write_count); 2609 2610 wmb(); 2611 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2612 write_count & rx_queue->ptr_mask); 2613 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2614 efx_rx_queue_index(rx_queue)); 2615 } 2616 2617 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2618 2619 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2620 { 2621 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2622 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2623 efx_qword_t event; 2624 2625 EFX_POPULATE_QWORD_2(event, 2626 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2627 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2628 2629 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2630 2631 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2632 * already swapped the data to little-endian order. 2633 */ 2634 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2635 sizeof(efx_qword_t)); 2636 2637 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2638 inbuf, sizeof(inbuf), 0, 2639 efx_ef10_rx_defer_refill_complete, 0); 2640 } 2641 2642 static void 2643 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2644 int rc, efx_dword_t *outbuf, 2645 size_t outlen_actual) 2646 { 2647 /* nothing to do */ 2648 } 2649 2650 static int efx_ef10_ev_init(struct efx_channel *channel) 2651 { 2652 struct efx_nic *efx = channel->efx; 2653 struct efx_ef10_nic_data *nic_data; 2654 bool use_v2, cut_thru; 2655 2656 nic_data = efx->nic_data; 2657 use_v2 = nic_data->datapath_caps2 & 2658 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN; 2659 cut_thru = !(nic_data->datapath_caps & 2660 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2661 return efx_mcdi_ev_init(channel, cut_thru, use_v2); 2662 } 2663 2664 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2665 unsigned int rx_queue_label) 2666 { 2667 struct efx_nic *efx = rx_queue->efx; 2668 2669 netif_info(efx, hw, efx->net_dev, 2670 "rx event arrived on queue %d labeled as queue %u\n", 2671 efx_rx_queue_index(rx_queue), rx_queue_label); 2672 2673 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2674 } 2675 2676 static void 2677 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2678 unsigned int actual, unsigned int expected) 2679 { 2680 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2681 struct efx_nic *efx = rx_queue->efx; 2682 2683 netif_info(efx, hw, efx->net_dev, 2684 "dropped %d events (index=%d expected=%d)\n", 2685 dropped, actual, expected); 2686 2687 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2688 } 2689 2690 /* partially received RX was aborted. clean up. */ 2691 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2692 { 2693 unsigned int rx_desc_ptr; 2694 2695 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2696 "scattered RX aborted (dropping %u buffers)\n", 2697 rx_queue->scatter_n); 2698 2699 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2700 2701 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2702 0, EFX_RX_PKT_DISCARD); 2703 2704 rx_queue->removed_count += rx_queue->scatter_n; 2705 rx_queue->scatter_n = 0; 2706 rx_queue->scatter_len = 0; 2707 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2708 } 2709 2710 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel, 2711 unsigned int n_packets, 2712 unsigned int rx_encap_hdr, 2713 unsigned int rx_l3_class, 2714 unsigned int rx_l4_class, 2715 const efx_qword_t *event) 2716 { 2717 struct efx_nic *efx = channel->efx; 2718 bool handled = false; 2719 2720 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) { 2721 if (!(efx->net_dev->features & NETIF_F_RXALL)) { 2722 if (!efx->loopback_selftest) 2723 channel->n_rx_eth_crc_err += n_packets; 2724 return EFX_RX_PKT_DISCARD; 2725 } 2726 handled = true; 2727 } 2728 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) { 2729 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2730 rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2731 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2732 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2733 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2734 netdev_WARN(efx->net_dev, 2735 "invalid class for RX_IPCKSUM_ERR: event=" 2736 EFX_QWORD_FMT "\n", 2737 EFX_QWORD_VAL(*event)); 2738 if (!efx->loopback_selftest) 2739 *(rx_encap_hdr ? 2740 &channel->n_rx_outer_ip_hdr_chksum_err : 2741 &channel->n_rx_ip_hdr_chksum_err) += n_packets; 2742 return 0; 2743 } 2744 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) { 2745 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2746 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2747 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2748 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2749 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))) 2750 netdev_WARN(efx->net_dev, 2751 "invalid class for RX_TCPUDP_CKSUM_ERR: event=" 2752 EFX_QWORD_FMT "\n", 2753 EFX_QWORD_VAL(*event)); 2754 if (!efx->loopback_selftest) 2755 *(rx_encap_hdr ? 2756 &channel->n_rx_outer_tcp_udp_chksum_err : 2757 &channel->n_rx_tcp_udp_chksum_err) += n_packets; 2758 return 0; 2759 } 2760 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) { 2761 if (unlikely(!rx_encap_hdr)) 2762 netdev_WARN(efx->net_dev, 2763 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event=" 2764 EFX_QWORD_FMT "\n", 2765 EFX_QWORD_VAL(*event)); 2766 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2767 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2768 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2769 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2770 netdev_WARN(efx->net_dev, 2771 "invalid class for RX_IP_INNER_CHKSUM_ERR: event=" 2772 EFX_QWORD_FMT "\n", 2773 EFX_QWORD_VAL(*event)); 2774 if (!efx->loopback_selftest) 2775 channel->n_rx_inner_ip_hdr_chksum_err += n_packets; 2776 return 0; 2777 } 2778 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) { 2779 if (unlikely(!rx_encap_hdr)) 2780 netdev_WARN(efx->net_dev, 2781 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2782 EFX_QWORD_FMT "\n", 2783 EFX_QWORD_VAL(*event)); 2784 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2785 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2786 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2787 rx_l4_class != ESE_FZ_L4_CLASS_UDP))) 2788 netdev_WARN(efx->net_dev, 2789 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2790 EFX_QWORD_FMT "\n", 2791 EFX_QWORD_VAL(*event)); 2792 if (!efx->loopback_selftest) 2793 channel->n_rx_inner_tcp_udp_chksum_err += n_packets; 2794 return 0; 2795 } 2796 2797 WARN_ON(!handled); /* No error bits were recognised */ 2798 return 0; 2799 } 2800 2801 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2802 const efx_qword_t *event) 2803 { 2804 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label; 2805 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr; 2806 unsigned int n_descs, n_packets, i; 2807 struct efx_nic *efx = channel->efx; 2808 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2809 struct efx_rx_queue *rx_queue; 2810 efx_qword_t errors; 2811 bool rx_cont; 2812 u16 flags = 0; 2813 2814 if (unlikely(READ_ONCE(efx->reset_pending))) 2815 return 0; 2816 2817 /* Basic packet information */ 2818 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2819 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2820 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2821 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS); 2822 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS); 2823 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2824 rx_encap_hdr = 2825 nic_data->datapath_caps & 2826 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ? 2827 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) : 2828 ESE_EZ_ENCAP_HDR_NONE; 2829 2830 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2831 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2832 EFX_QWORD_FMT "\n", 2833 EFX_QWORD_VAL(*event)); 2834 2835 rx_queue = efx_channel_get_rx_queue(channel); 2836 2837 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2838 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2839 2840 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2841 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2842 2843 if (n_descs != rx_queue->scatter_n + 1) { 2844 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2845 2846 /* detect rx abort */ 2847 if (unlikely(n_descs == rx_queue->scatter_n)) { 2848 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2849 netdev_WARN(efx->net_dev, 2850 "invalid RX abort: scatter_n=%u event=" 2851 EFX_QWORD_FMT "\n", 2852 rx_queue->scatter_n, 2853 EFX_QWORD_VAL(*event)); 2854 efx_ef10_handle_rx_abort(rx_queue); 2855 return 0; 2856 } 2857 2858 /* Check that RX completion merging is valid, i.e. 2859 * the current firmware supports it and this is a 2860 * non-scattered packet. 2861 */ 2862 if (!(nic_data->datapath_caps & 2863 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2864 rx_queue->scatter_n != 0 || rx_cont) { 2865 efx_ef10_handle_rx_bad_lbits( 2866 rx_queue, next_ptr_lbits, 2867 (rx_queue->removed_count + 2868 rx_queue->scatter_n + 1) & 2869 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2870 return 0; 2871 } 2872 2873 /* Merged completion for multiple non-scattered packets */ 2874 rx_queue->scatter_n = 1; 2875 rx_queue->scatter_len = 0; 2876 n_packets = n_descs; 2877 ++channel->n_rx_merge_events; 2878 channel->n_rx_merge_packets += n_packets; 2879 flags |= EFX_RX_PKT_PREFIX_LEN; 2880 } else { 2881 ++rx_queue->scatter_n; 2882 rx_queue->scatter_len += rx_bytes; 2883 if (rx_cont) 2884 return 0; 2885 n_packets = 1; 2886 } 2887 2888 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1, 2889 ESF_DZ_RX_IPCKSUM_ERR, 1, 2890 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1, 2891 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1, 2892 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1); 2893 EFX_AND_QWORD(errors, *event, errors); 2894 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) { 2895 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets, 2896 rx_encap_hdr, 2897 rx_l3_class, rx_l4_class, 2898 event); 2899 } else { 2900 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP || 2901 rx_l4_class == ESE_FZ_L4_CLASS_UDP; 2902 2903 switch (rx_encap_hdr) { 2904 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */ 2905 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */ 2906 if (tcpudp) 2907 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */ 2908 break; 2909 case ESE_EZ_ENCAP_HDR_GRE: 2910 case ESE_EZ_ENCAP_HDR_NONE: 2911 if (tcpudp) 2912 flags |= EFX_RX_PKT_CSUMMED; 2913 break; 2914 default: 2915 netdev_WARN(efx->net_dev, 2916 "unknown encapsulation type: event=" 2917 EFX_QWORD_FMT "\n", 2918 EFX_QWORD_VAL(*event)); 2919 } 2920 } 2921 2922 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP) 2923 flags |= EFX_RX_PKT_TCP; 2924 2925 channel->irq_mod_score += 2 * n_packets; 2926 2927 /* Handle received packet(s) */ 2928 for (i = 0; i < n_packets; i++) { 2929 efx_rx_packet(rx_queue, 2930 rx_queue->removed_count & rx_queue->ptr_mask, 2931 rx_queue->scatter_n, rx_queue->scatter_len, 2932 flags); 2933 rx_queue->removed_count += rx_queue->scatter_n; 2934 } 2935 2936 rx_queue->scatter_n = 0; 2937 rx_queue->scatter_len = 0; 2938 2939 return n_packets; 2940 } 2941 2942 static u32 efx_ef10_extract_event_ts(efx_qword_t *event) 2943 { 2944 u32 tstamp; 2945 2946 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI); 2947 tstamp <<= 16; 2948 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO); 2949 2950 return tstamp; 2951 } 2952 2953 static void 2954 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2955 { 2956 struct efx_nic *efx = channel->efx; 2957 struct efx_tx_queue *tx_queue; 2958 unsigned int tx_ev_desc_ptr; 2959 unsigned int tx_ev_q_label; 2960 unsigned int tx_ev_type; 2961 u64 ts_part; 2962 2963 if (unlikely(READ_ONCE(efx->reset_pending))) 2964 return; 2965 2966 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2967 return; 2968 2969 /* Get the transmit queue */ 2970 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2971 tx_queue = channel->tx_queue + (tx_ev_q_label % EFX_MAX_TXQ_PER_CHANNEL); 2972 2973 if (!tx_queue->timestamping) { 2974 /* Transmit completion */ 2975 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2976 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2977 return; 2978 } 2979 2980 /* Transmit timestamps are only available for 8XXX series. They result 2981 * in up to three events per packet. These occur in order, and are: 2982 * - the normal completion event (may be omitted) 2983 * - the low part of the timestamp 2984 * - the high part of the timestamp 2985 * 2986 * It's possible for multiple completion events to appear before the 2987 * corresponding timestamps. So we can for example get: 2988 * COMP N 2989 * COMP N+1 2990 * TS_LO N 2991 * TS_HI N 2992 * TS_LO N+1 2993 * TS_HI N+1 2994 * 2995 * In addition it's also possible for the adjacent completions to be 2996 * merged, so we may not see COMP N above. As such, the completion 2997 * events are not very useful here. 2998 * 2999 * Each part of the timestamp is itself split across two 16 bit 3000 * fields in the event. 3001 */ 3002 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1); 3003 3004 switch (tx_ev_type) { 3005 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION: 3006 /* Ignore this event - see above. */ 3007 break; 3008 3009 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO: 3010 ts_part = efx_ef10_extract_event_ts(event); 3011 tx_queue->completed_timestamp_minor = ts_part; 3012 break; 3013 3014 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI: 3015 ts_part = efx_ef10_extract_event_ts(event); 3016 tx_queue->completed_timestamp_major = ts_part; 3017 3018 efx_xmit_done_single(tx_queue); 3019 break; 3020 3021 default: 3022 netif_err(efx, hw, efx->net_dev, 3023 "channel %d unknown tx event type %d (data " 3024 EFX_QWORD_FMT ")\n", 3025 channel->channel, tx_ev_type, 3026 EFX_QWORD_VAL(*event)); 3027 break; 3028 } 3029 } 3030 3031 static void 3032 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 3033 { 3034 struct efx_nic *efx = channel->efx; 3035 int subcode; 3036 3037 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 3038 3039 switch (subcode) { 3040 case ESE_DZ_DRV_TIMER_EV: 3041 case ESE_DZ_DRV_WAKE_UP_EV: 3042 break; 3043 case ESE_DZ_DRV_START_UP_EV: 3044 /* event queue init complete. ok. */ 3045 break; 3046 default: 3047 netif_err(efx, hw, efx->net_dev, 3048 "channel %d unknown driver event type %d" 3049 " (data " EFX_QWORD_FMT ")\n", 3050 channel->channel, subcode, 3051 EFX_QWORD_VAL(*event)); 3052 3053 } 3054 } 3055 3056 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 3057 efx_qword_t *event) 3058 { 3059 struct efx_nic *efx = channel->efx; 3060 u32 subcode; 3061 3062 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 3063 3064 switch (subcode) { 3065 case EFX_EF10_TEST: 3066 channel->event_test_cpu = raw_smp_processor_id(); 3067 break; 3068 case EFX_EF10_REFILL: 3069 /* The queue must be empty, so we won't receive any rx 3070 * events, so efx_process_channel() won't refill the 3071 * queue. Refill it here 3072 */ 3073 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 3074 break; 3075 default: 3076 netif_err(efx, hw, efx->net_dev, 3077 "channel %d unknown driver event type %u" 3078 " (data " EFX_QWORD_FMT ")\n", 3079 channel->channel, (unsigned) subcode, 3080 EFX_QWORD_VAL(*event)); 3081 } 3082 } 3083 3084 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 3085 { 3086 struct efx_nic *efx = channel->efx; 3087 efx_qword_t event, *p_event; 3088 unsigned int read_ptr; 3089 int ev_code; 3090 int spent = 0; 3091 3092 if (quota <= 0) 3093 return spent; 3094 3095 read_ptr = channel->eventq_read_ptr; 3096 3097 for (;;) { 3098 p_event = efx_event(channel, read_ptr); 3099 event = *p_event; 3100 3101 if (!efx_event_present(&event)) 3102 break; 3103 3104 EFX_SET_QWORD(*p_event); 3105 3106 ++read_ptr; 3107 3108 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 3109 3110 netif_vdbg(efx, drv, efx->net_dev, 3111 "processing event on %d " EFX_QWORD_FMT "\n", 3112 channel->channel, EFX_QWORD_VAL(event)); 3113 3114 switch (ev_code) { 3115 case ESE_DZ_EV_CODE_MCDI_EV: 3116 efx_mcdi_process_event(channel, &event); 3117 break; 3118 case ESE_DZ_EV_CODE_RX_EV: 3119 spent += efx_ef10_handle_rx_event(channel, &event); 3120 if (spent >= quota) { 3121 /* XXX can we split a merged event to 3122 * avoid going over-quota? 3123 */ 3124 spent = quota; 3125 goto out; 3126 } 3127 break; 3128 case ESE_DZ_EV_CODE_TX_EV: 3129 efx_ef10_handle_tx_event(channel, &event); 3130 break; 3131 case ESE_DZ_EV_CODE_DRIVER_EV: 3132 efx_ef10_handle_driver_event(channel, &event); 3133 if (++spent == quota) 3134 goto out; 3135 break; 3136 case EFX_EF10_DRVGEN_EV: 3137 efx_ef10_handle_driver_generated_event(channel, &event); 3138 break; 3139 default: 3140 netif_err(efx, hw, efx->net_dev, 3141 "channel %d unknown event type %d" 3142 " (data " EFX_QWORD_FMT ")\n", 3143 channel->channel, ev_code, 3144 EFX_QWORD_VAL(event)); 3145 } 3146 } 3147 3148 out: 3149 channel->eventq_read_ptr = read_ptr; 3150 return spent; 3151 } 3152 3153 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 3154 { 3155 struct efx_nic *efx = channel->efx; 3156 efx_dword_t rptr; 3157 3158 if (EFX_EF10_WORKAROUND_35388(efx)) { 3159 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 3160 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 3161 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 3162 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 3163 3164 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3165 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 3166 ERF_DD_EVQ_IND_RPTR, 3167 (channel->eventq_read_ptr & 3168 channel->eventq_mask) >> 3169 ERF_DD_EVQ_IND_RPTR_WIDTH); 3170 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3171 channel->channel); 3172 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3173 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 3174 ERF_DD_EVQ_IND_RPTR, 3175 channel->eventq_read_ptr & 3176 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 3177 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3178 channel->channel); 3179 } else { 3180 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 3181 channel->eventq_read_ptr & 3182 channel->eventq_mask); 3183 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 3184 } 3185 } 3186 3187 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 3188 { 3189 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 3190 struct efx_nic *efx = channel->efx; 3191 efx_qword_t event; 3192 int rc; 3193 3194 EFX_POPULATE_QWORD_2(event, 3195 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 3196 ESF_DZ_EV_DATA, EFX_EF10_TEST); 3197 3198 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 3199 3200 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 3201 * already swapped the data to little-endian order. 3202 */ 3203 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 3204 sizeof(efx_qword_t)); 3205 3206 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 3207 NULL, 0, NULL); 3208 if (rc != 0) 3209 goto fail; 3210 3211 return; 3212 3213 fail: 3214 WARN_ON(true); 3215 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 3216 } 3217 3218 static void efx_ef10_prepare_flr(struct efx_nic *efx) 3219 { 3220 atomic_set(&efx->active_queues, 0); 3221 } 3222 3223 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 3224 { 3225 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3226 u8 mac_old[ETH_ALEN]; 3227 int rc, rc2; 3228 3229 /* Only reconfigure a PF-created vport */ 3230 if (is_zero_ether_addr(nic_data->vport_mac)) 3231 return 0; 3232 3233 efx_device_detach_sync(efx); 3234 efx_net_stop(efx->net_dev); 3235 efx_ef10_filter_table_remove(efx); 3236 3237 rc = efx_ef10_vadaptor_free(efx, efx->vport_id); 3238 if (rc) 3239 goto restore_filters; 3240 3241 ether_addr_copy(mac_old, nic_data->vport_mac); 3242 rc = efx_ef10_vport_del_mac(efx, efx->vport_id, 3243 nic_data->vport_mac); 3244 if (rc) 3245 goto restore_vadaptor; 3246 3247 rc = efx_ef10_vport_add_mac(efx, efx->vport_id, 3248 efx->net_dev->dev_addr); 3249 if (!rc) { 3250 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 3251 } else { 3252 rc2 = efx_ef10_vport_add_mac(efx, efx->vport_id, mac_old); 3253 if (rc2) { 3254 /* Failed to add original MAC, so clear vport_mac */ 3255 eth_zero_addr(nic_data->vport_mac); 3256 goto reset_nic; 3257 } 3258 } 3259 3260 restore_vadaptor: 3261 rc2 = efx_ef10_vadaptor_alloc(efx, efx->vport_id); 3262 if (rc2) 3263 goto reset_nic; 3264 restore_filters: 3265 rc2 = efx_ef10_filter_table_probe(efx); 3266 if (rc2) 3267 goto reset_nic; 3268 3269 rc2 = efx_net_open(efx->net_dev); 3270 if (rc2) 3271 goto reset_nic; 3272 3273 efx_device_attach_if_not_resetting(efx); 3274 3275 return rc; 3276 3277 reset_nic: 3278 netif_err(efx, drv, efx->net_dev, 3279 "Failed to restore when changing MAC address - scheduling reset\n"); 3280 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 3281 3282 return rc ? rc : rc2; 3283 } 3284 3285 static int efx_ef10_set_mac_address(struct efx_nic *efx) 3286 { 3287 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 3288 bool was_enabled = efx->port_enabled; 3289 int rc; 3290 3291 #ifdef CONFIG_SFC_SRIOV 3292 /* If this function is a VF and we have access to the parent PF, 3293 * then use the PF control path to attempt to change the VF MAC address. 3294 */ 3295 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 3296 struct efx_nic *efx_pf = pci_get_drvdata(efx->pci_dev->physfn); 3297 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3298 u8 mac[ETH_ALEN]; 3299 3300 /* net_dev->dev_addr can be zeroed by efx_net_stop in 3301 * efx_ef10_sriov_set_vf_mac, so pass in a copy. 3302 */ 3303 ether_addr_copy(mac, efx->net_dev->dev_addr); 3304 3305 rc = efx_ef10_sriov_set_vf_mac(efx_pf, nic_data->vf_index, mac); 3306 if (!rc) 3307 return 0; 3308 3309 netif_dbg(efx, drv, efx->net_dev, 3310 "Updating VF mac via PF failed (%d), setting directly\n", 3311 rc); 3312 } 3313 #endif 3314 3315 efx_device_detach_sync(efx); 3316 efx_net_stop(efx->net_dev); 3317 3318 mutex_lock(&efx->mac_lock); 3319 efx_ef10_filter_table_remove(efx); 3320 3321 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 3322 efx->net_dev->dev_addr); 3323 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 3324 efx->vport_id); 3325 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 3326 sizeof(inbuf), NULL, 0, NULL); 3327 3328 efx_ef10_filter_table_probe(efx); 3329 mutex_unlock(&efx->mac_lock); 3330 3331 if (was_enabled) 3332 efx_net_open(efx->net_dev); 3333 efx_device_attach_if_not_resetting(efx); 3334 3335 if (rc == -EPERM) { 3336 netif_err(efx, drv, efx->net_dev, 3337 "Cannot change MAC address; use sfboot to enable" 3338 " mac-spoofing on this interface\n"); 3339 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 3340 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 3341 * fall-back to the method of changing the MAC address on the 3342 * vport. This only applies to PFs because such versions of 3343 * MCFW do not support VFs. 3344 */ 3345 rc = efx_ef10_vport_set_mac_address(efx); 3346 } else if (rc) { 3347 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 3348 sizeof(inbuf), NULL, 0, rc); 3349 } 3350 3351 return rc; 3352 } 3353 3354 static int efx_ef10_mac_reconfigure(struct efx_nic *efx, bool mtu_only) 3355 { 3356 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 3357 3358 efx_mcdi_filter_sync_rx_mode(efx); 3359 3360 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED)) 3361 return efx_mcdi_set_mtu(efx); 3362 return efx_mcdi_set_mac(efx); 3363 } 3364 3365 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 3366 { 3367 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 3368 3369 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 3370 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 3371 NULL, 0, NULL); 3372 } 3373 3374 /* MC BISTs follow a different poll mechanism to phy BISTs. 3375 * The BIST is done in the poll handler on the MC, and the MCDI command 3376 * will block until the BIST is done. 3377 */ 3378 static int efx_ef10_poll_bist(struct efx_nic *efx) 3379 { 3380 int rc; 3381 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 3382 size_t outlen; 3383 u32 result; 3384 3385 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 3386 outbuf, sizeof(outbuf), &outlen); 3387 if (rc != 0) 3388 return rc; 3389 3390 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 3391 return -EIO; 3392 3393 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 3394 switch (result) { 3395 case MC_CMD_POLL_BIST_PASSED: 3396 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 3397 return 0; 3398 case MC_CMD_POLL_BIST_TIMEOUT: 3399 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 3400 return -EIO; 3401 case MC_CMD_POLL_BIST_FAILED: 3402 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 3403 return -EIO; 3404 default: 3405 netif_err(efx, hw, efx->net_dev, 3406 "BIST returned unknown result %u", result); 3407 return -EIO; 3408 } 3409 } 3410 3411 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 3412 { 3413 int rc; 3414 3415 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 3416 3417 rc = efx_ef10_start_bist(efx, bist_type); 3418 if (rc != 0) 3419 return rc; 3420 3421 return efx_ef10_poll_bist(efx); 3422 } 3423 3424 static int 3425 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 3426 { 3427 int rc, rc2; 3428 3429 efx_reset_down(efx, RESET_TYPE_WORLD); 3430 3431 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 3432 NULL, 0, NULL, 0, NULL); 3433 if (rc != 0) 3434 goto out; 3435 3436 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 3437 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 3438 3439 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 3440 3441 out: 3442 if (rc == -EPERM) 3443 rc = 0; 3444 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 3445 return rc ? rc : rc2; 3446 } 3447 3448 #ifdef CONFIG_SFC_MTD 3449 3450 struct efx_ef10_nvram_type_info { 3451 u16 type, type_mask; 3452 u8 port; 3453 const char *name; 3454 }; 3455 3456 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 3457 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 3458 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 3459 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 3460 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 3461 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 3462 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 3463 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 3464 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 3465 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 3466 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 3467 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 3468 { NVRAM_PARTITION_TYPE_MUM_FIRMWARE, 0, 0, "sfc_mumfw" }, 3469 { NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 0, 0, "sfc_uefi" }, 3470 { NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS, 0, 0, "sfc_dynamic_cfg_dflt" }, 3471 { NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS, 0, 0, "sfc_exp_rom_cfg_dflt" }, 3472 { NVRAM_PARTITION_TYPE_STATUS, 0, 0, "sfc_status" }, 3473 { NVRAM_PARTITION_TYPE_BUNDLE, 0, 0, "sfc_bundle" }, 3474 { NVRAM_PARTITION_TYPE_BUNDLE_METADATA, 0, 0, "sfc_bundle_metadata" }, 3475 }; 3476 #define EF10_NVRAM_PARTITION_COUNT ARRAY_SIZE(efx_ef10_nvram_types) 3477 3478 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 3479 struct efx_mcdi_mtd_partition *part, 3480 unsigned int type, 3481 unsigned long *found) 3482 { 3483 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 3484 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 3485 const struct efx_ef10_nvram_type_info *info; 3486 size_t size, erase_size, outlen; 3487 int type_idx = 0; 3488 bool protected; 3489 int rc; 3490 3491 for (type_idx = 0; ; type_idx++) { 3492 if (type_idx == EF10_NVRAM_PARTITION_COUNT) 3493 return -ENODEV; 3494 info = efx_ef10_nvram_types + type_idx; 3495 if ((type & ~info->type_mask) == info->type) 3496 break; 3497 } 3498 if (info->port != efx_port_num(efx)) 3499 return -ENODEV; 3500 3501 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 3502 if (rc) 3503 return rc; 3504 if (protected && 3505 (type != NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS && 3506 type != NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS)) 3507 /* Hide protected partitions that don't provide defaults. */ 3508 return -ENODEV; 3509 3510 if (protected) 3511 /* Protected partitions are read only. */ 3512 erase_size = 0; 3513 3514 /* If we've already exposed a partition of this type, hide this 3515 * duplicate. All operations on MTDs are keyed by the type anyway, 3516 * so we can't act on the duplicate. 3517 */ 3518 if (__test_and_set_bit(type_idx, found)) 3519 return -EEXIST; 3520 3521 part->nvram_type = type; 3522 3523 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 3524 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 3525 outbuf, sizeof(outbuf), &outlen); 3526 if (rc) 3527 return rc; 3528 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 3529 return -EIO; 3530 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 3531 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 3532 part->fw_subtype = MCDI_DWORD(outbuf, 3533 NVRAM_METADATA_OUT_SUBTYPE); 3534 3535 part->common.dev_type_name = "EF10 NVRAM manager"; 3536 part->common.type_name = info->name; 3537 3538 part->common.mtd.type = MTD_NORFLASH; 3539 part->common.mtd.flags = MTD_CAP_NORFLASH; 3540 part->common.mtd.size = size; 3541 part->common.mtd.erasesize = erase_size; 3542 /* sfc_status is read-only */ 3543 if (!erase_size) 3544 part->common.mtd.flags |= MTD_NO_ERASE; 3545 3546 return 0; 3547 } 3548 3549 static int efx_ef10_mtd_probe(struct efx_nic *efx) 3550 { 3551 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 3552 DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 }; 3553 struct efx_mcdi_mtd_partition *parts; 3554 size_t outlen, n_parts_total, i, n_parts; 3555 unsigned int type; 3556 int rc; 3557 3558 ASSERT_RTNL(); 3559 3560 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 3561 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 3562 outbuf, sizeof(outbuf), &outlen); 3563 if (rc) 3564 return rc; 3565 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 3566 return -EIO; 3567 3568 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 3569 if (n_parts_total > 3570 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 3571 return -EIO; 3572 3573 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 3574 if (!parts) 3575 return -ENOMEM; 3576 3577 n_parts = 0; 3578 for (i = 0; i < n_parts_total; i++) { 3579 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 3580 i); 3581 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type, 3582 found); 3583 if (rc == -EEXIST || rc == -ENODEV) 3584 continue; 3585 if (rc) 3586 goto fail; 3587 n_parts++; 3588 } 3589 3590 if (!n_parts) { 3591 kfree(parts); 3592 return 0; 3593 } 3594 3595 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 3596 fail: 3597 if (rc) 3598 kfree(parts); 3599 return rc; 3600 } 3601 3602 #endif /* CONFIG_SFC_MTD */ 3603 3604 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 3605 { 3606 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 3607 } 3608 3609 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 3610 u32 host_time) {} 3611 3612 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 3613 bool temp) 3614 { 3615 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 3616 int rc; 3617 3618 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 3619 channel->sync_events_state == SYNC_EVENTS_VALID || 3620 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 3621 return 0; 3622 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 3623 3624 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 3625 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3626 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 3627 channel->channel); 3628 3629 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3630 inbuf, sizeof(inbuf), NULL, 0, NULL); 3631 3632 if (rc != 0) 3633 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3634 SYNC_EVENTS_DISABLED; 3635 3636 return rc; 3637 } 3638 3639 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 3640 bool temp) 3641 { 3642 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 3643 int rc; 3644 3645 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 3646 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 3647 return 0; 3648 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 3649 channel->sync_events_state = SYNC_EVENTS_DISABLED; 3650 return 0; 3651 } 3652 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3653 SYNC_EVENTS_DISABLED; 3654 3655 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 3656 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3657 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 3658 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 3659 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 3660 channel->channel); 3661 3662 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3663 inbuf, sizeof(inbuf), NULL, 0, NULL); 3664 3665 return rc; 3666 } 3667 3668 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 3669 bool temp) 3670 { 3671 int (*set)(struct efx_channel *channel, bool temp); 3672 struct efx_channel *channel; 3673 3674 set = en ? 3675 efx_ef10_rx_enable_timestamping : 3676 efx_ef10_rx_disable_timestamping; 3677 3678 channel = efx_ptp_channel(efx); 3679 if (channel) { 3680 int rc = set(channel, temp); 3681 if (en && rc != 0) { 3682 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 3683 return rc; 3684 } 3685 } 3686 3687 return 0; 3688 } 3689 3690 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 3691 struct hwtstamp_config *init) 3692 { 3693 return -EOPNOTSUPP; 3694 } 3695 3696 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 3697 struct hwtstamp_config *init) 3698 { 3699 int rc; 3700 3701 switch (init->rx_filter) { 3702 case HWTSTAMP_FILTER_NONE: 3703 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 3704 /* if TX timestamping is still requested then leave PTP on */ 3705 return efx_ptp_change_mode(efx, 3706 init->tx_type != HWTSTAMP_TX_OFF, 0); 3707 case HWTSTAMP_FILTER_ALL: 3708 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3709 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3710 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3711 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3712 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3713 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3714 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3715 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3716 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3717 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3718 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3719 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3720 case HWTSTAMP_FILTER_NTP_ALL: 3721 init->rx_filter = HWTSTAMP_FILTER_ALL; 3722 rc = efx_ptp_change_mode(efx, true, 0); 3723 if (!rc) 3724 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 3725 if (rc) 3726 efx_ptp_change_mode(efx, false, 0); 3727 return rc; 3728 default: 3729 return -ERANGE; 3730 } 3731 } 3732 3733 static int efx_ef10_get_phys_port_id(struct efx_nic *efx, 3734 struct netdev_phys_item_id *ppid) 3735 { 3736 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3737 3738 if (!is_valid_ether_addr(nic_data->port_id)) 3739 return -EOPNOTSUPP; 3740 3741 ppid->id_len = ETH_ALEN; 3742 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 3743 3744 return 0; 3745 } 3746 3747 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3748 { 3749 if (proto != htons(ETH_P_8021Q)) 3750 return -EINVAL; 3751 3752 return efx_ef10_add_vlan(efx, vid); 3753 } 3754 3755 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3756 { 3757 if (proto != htons(ETH_P_8021Q)) 3758 return -EINVAL; 3759 3760 return efx_ef10_del_vlan(efx, vid); 3761 } 3762 3763 /* We rely on the MCDI wiping out our TX rings if it made any changes to the 3764 * ports table, ensuring that any TSO descriptors that were made on a now- 3765 * removed tunnel port will be blown away and won't break things when we try 3766 * to transmit them using the new ports table. 3767 */ 3768 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading) 3769 { 3770 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3771 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX); 3772 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN); 3773 bool will_reset = false; 3774 size_t num_entries = 0; 3775 size_t inlen, outlen; 3776 size_t i; 3777 int rc; 3778 efx_dword_t flags_and_num_entries; 3779 3780 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock)); 3781 3782 nic_data->udp_tunnels_dirty = false; 3783 3784 if (!(nic_data->datapath_caps & 3785 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) { 3786 efx_device_attach_if_not_resetting(efx); 3787 return 0; 3788 } 3789 3790 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) > 3791 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM); 3792 3793 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) { 3794 if (nic_data->udp_tunnels[i].type != 3795 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID) { 3796 efx_dword_t entry; 3797 3798 EFX_POPULATE_DWORD_2(entry, 3799 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT, 3800 ntohs(nic_data->udp_tunnels[i].port), 3801 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL, 3802 nic_data->udp_tunnels[i].type); 3803 *_MCDI_ARRAY_DWORD(inbuf, 3804 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES, 3805 num_entries++) = entry; 3806 } 3807 } 3808 3809 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST - 3810 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 != 3811 EFX_WORD_1_LBN); 3812 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 != 3813 EFX_WORD_1_WIDTH); 3814 EFX_POPULATE_DWORD_2(flags_and_num_entries, 3815 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING, 3816 !!unloading, 3817 EFX_WORD_1, num_entries); 3818 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) = 3819 flags_and_num_entries; 3820 3821 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries); 3822 3823 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS, 3824 inbuf, inlen, outbuf, sizeof(outbuf), &outlen); 3825 if (rc == -EIO) { 3826 /* Most likely the MC rebooted due to another function also 3827 * setting its tunnel port list. Mark the tunnel port list as 3828 * dirty, so it will be pushed upon coming up from the reboot. 3829 */ 3830 nic_data->udp_tunnels_dirty = true; 3831 return 0; 3832 } 3833 3834 if (rc) { 3835 /* expected not available on unprivileged functions */ 3836 if (rc != -EPERM) 3837 netif_warn(efx, drv, efx->net_dev, 3838 "Unable to set UDP tunnel ports; rc=%d.\n", rc); 3839 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) & 3840 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) { 3841 netif_info(efx, drv, efx->net_dev, 3842 "Rebooting MC due to UDP tunnel port list change\n"); 3843 will_reset = true; 3844 if (unloading) 3845 /* Delay for the MC reset to complete. This will make 3846 * unloading other functions a bit smoother. This is a 3847 * race, but the other unload will work whichever way 3848 * it goes, this just avoids an unnecessary error 3849 * message. 3850 */ 3851 msleep(100); 3852 } 3853 if (!will_reset && !unloading) { 3854 /* The caller will have detached, relying on the MC reset to 3855 * trigger a re-attach. Since there won't be an MC reset, we 3856 * have to do the attach ourselves. 3857 */ 3858 efx_device_attach_if_not_resetting(efx); 3859 } 3860 3861 return rc; 3862 } 3863 3864 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx) 3865 { 3866 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3867 int rc = 0; 3868 3869 mutex_lock(&nic_data->udp_tunnels_lock); 3870 if (nic_data->udp_tunnels_dirty) { 3871 /* Make sure all TX are stopped while we modify the table, else 3872 * we might race against an efx_features_check(). 3873 */ 3874 efx_device_detach_sync(efx); 3875 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3876 } 3877 mutex_unlock(&nic_data->udp_tunnels_lock); 3878 return rc; 3879 } 3880 3881 static int efx_ef10_udp_tnl_set_port(struct net_device *dev, 3882 unsigned int table, unsigned int entry, 3883 struct udp_tunnel_info *ti) 3884 { 3885 struct efx_nic *efx = efx_netdev_priv(dev); 3886 struct efx_ef10_nic_data *nic_data; 3887 int efx_tunnel_type, rc; 3888 3889 if (ti->type == UDP_TUNNEL_TYPE_VXLAN) 3890 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN; 3891 else 3892 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE; 3893 3894 nic_data = efx->nic_data; 3895 if (!(nic_data->datapath_caps & 3896 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3897 return -EOPNOTSUPP; 3898 3899 mutex_lock(&nic_data->udp_tunnels_lock); 3900 /* Make sure all TX are stopped while we add to the table, else we 3901 * might race against an efx_features_check(). 3902 */ 3903 efx_device_detach_sync(efx); 3904 nic_data->udp_tunnels[entry].type = efx_tunnel_type; 3905 nic_data->udp_tunnels[entry].port = ti->port; 3906 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3907 mutex_unlock(&nic_data->udp_tunnels_lock); 3908 3909 return rc; 3910 } 3911 3912 /* Called under the TX lock with the TX queue running, hence no-one can be 3913 * in the middle of updating the UDP tunnels table. However, they could 3914 * have tried and failed the MCDI, in which case they'll have set the dirty 3915 * flag before dropping their locks. 3916 */ 3917 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port) 3918 { 3919 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3920 size_t i; 3921 3922 if (!(nic_data->datapath_caps & 3923 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3924 return false; 3925 3926 if (nic_data->udp_tunnels_dirty) 3927 /* SW table may not match HW state, so just assume we can't 3928 * use any UDP tunnel offloads. 3929 */ 3930 return false; 3931 3932 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 3933 if (nic_data->udp_tunnels[i].type != 3934 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID && 3935 nic_data->udp_tunnels[i].port == port) 3936 return true; 3937 3938 return false; 3939 } 3940 3941 static int efx_ef10_udp_tnl_unset_port(struct net_device *dev, 3942 unsigned int table, unsigned int entry, 3943 struct udp_tunnel_info *ti) 3944 { 3945 struct efx_nic *efx = efx_netdev_priv(dev); 3946 struct efx_ef10_nic_data *nic_data; 3947 int rc; 3948 3949 nic_data = efx->nic_data; 3950 3951 mutex_lock(&nic_data->udp_tunnels_lock); 3952 /* Make sure all TX are stopped while we remove from the table, else we 3953 * might race against an efx_features_check(). 3954 */ 3955 efx_device_detach_sync(efx); 3956 nic_data->udp_tunnels[entry].type = TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 3957 nic_data->udp_tunnels[entry].port = 0; 3958 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3959 mutex_unlock(&nic_data->udp_tunnels_lock); 3960 3961 return rc; 3962 } 3963 3964 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels = { 3965 .set_port = efx_ef10_udp_tnl_set_port, 3966 .unset_port = efx_ef10_udp_tnl_unset_port, 3967 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP, 3968 .tables = { 3969 { 3970 .n_entries = 16, 3971 .tunnel_types = UDP_TUNNEL_TYPE_VXLAN | 3972 UDP_TUNNEL_TYPE_GENEVE, 3973 }, 3974 }, 3975 }; 3976 3977 /* EF10 may have multiple datapath firmware variants within a 3978 * single version. Report which variants are running. 3979 */ 3980 static size_t efx_ef10_print_additional_fwver(struct efx_nic *efx, char *buf, 3981 size_t len) 3982 { 3983 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3984 3985 return scnprintf(buf, len, " rx%x tx%x", 3986 nic_data->rx_dpcpu_fw_id, 3987 nic_data->tx_dpcpu_fw_id); 3988 } 3989 3990 static unsigned int ef10_check_caps(const struct efx_nic *efx, 3991 u8 flag, 3992 u32 offset) 3993 { 3994 const struct efx_ef10_nic_data *nic_data = efx->nic_data; 3995 3996 switch (offset) { 3997 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST): 3998 return nic_data->datapath_caps & BIT_ULL(flag); 3999 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST): 4000 return nic_data->datapath_caps2 & BIT_ULL(flag); 4001 default: 4002 return 0; 4003 } 4004 } 4005 4006 static unsigned int efx_ef10_recycle_ring_size(const struct efx_nic *efx) 4007 { 4008 unsigned int ret = EFX_RECYCLE_RING_SIZE_10G; 4009 4010 /* There is no difference between PFs and VFs. The side is based on 4011 * the maximum link speed of a given NIC. 4012 */ 4013 switch (efx->pci_dev->device & 0xfff) { 4014 case 0x0903: /* Farmingdale can do up to 10G */ 4015 break; 4016 case 0x0923: /* Greenport can do up to 40G */ 4017 case 0x0a03: /* Medford can do up to 40G */ 4018 ret *= 4; 4019 break; 4020 default: /* Medford2 can do up to 100G */ 4021 ret *= 10; 4022 } 4023 4024 if (IS_ENABLED(CONFIG_PPC64)) 4025 ret *= 4; 4026 4027 return ret; 4028 } 4029 4030 #define EF10_OFFLOAD_FEATURES \ 4031 (NETIF_F_IP_CSUM | \ 4032 NETIF_F_HW_VLAN_CTAG_FILTER | \ 4033 NETIF_F_IPV6_CSUM | \ 4034 NETIF_F_RXHASH | \ 4035 NETIF_F_NTUPLE | \ 4036 NETIF_F_SG | \ 4037 NETIF_F_RXCSUM | \ 4038 NETIF_F_RXALL) 4039 4040 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 4041 .is_vf = true, 4042 .mem_bar = efx_ef10_vf_mem_bar, 4043 .mem_map_size = efx_ef10_mem_map_size, 4044 .probe = efx_ef10_probe_vf, 4045 .remove = efx_ef10_remove, 4046 .dimension_resources = efx_ef10_dimension_resources, 4047 .init = efx_ef10_init_nic, 4048 .fini = efx_ef10_fini_nic, 4049 .map_reset_reason = efx_ef10_map_reset_reason, 4050 .map_reset_flags = efx_ef10_map_reset_flags, 4051 .reset = efx_ef10_reset, 4052 .probe_port = efx_mcdi_port_probe, 4053 .remove_port = efx_mcdi_port_remove, 4054 .fini_dmaq = efx_fini_dmaq, 4055 .prepare_flr = efx_ef10_prepare_flr, 4056 .finish_flr = efx_port_dummy_op_void, 4057 .describe_stats = efx_ef10_describe_stats, 4058 .update_stats = efx_ef10_update_stats_vf, 4059 .update_stats_atomic = efx_ef10_update_stats_atomic_vf, 4060 .start_stats = efx_port_dummy_op_void, 4061 .pull_stats = efx_port_dummy_op_void, 4062 .stop_stats = efx_port_dummy_op_void, 4063 .push_irq_moderation = efx_ef10_push_irq_moderation, 4064 .reconfigure_mac = efx_ef10_mac_reconfigure, 4065 .check_mac_fault = efx_mcdi_mac_check_fault, 4066 .reconfigure_port = efx_mcdi_port_reconfigure, 4067 .get_wol = efx_ef10_get_wol_vf, 4068 .set_wol = efx_ef10_set_wol_vf, 4069 .resume_wol = efx_port_dummy_op_void, 4070 .mcdi_request = efx_ef10_mcdi_request, 4071 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4072 .mcdi_read_response = efx_ef10_mcdi_read_response, 4073 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4074 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4075 .irq_enable_master = efx_port_dummy_op_void, 4076 .irq_test_generate = efx_ef10_irq_test_generate, 4077 .irq_disable_non_ev = efx_port_dummy_op_void, 4078 .irq_handle_msi = efx_ef10_msi_interrupt, 4079 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4080 .tx_probe = efx_ef10_tx_probe, 4081 .tx_init = efx_ef10_tx_init, 4082 .tx_remove = efx_mcdi_tx_remove, 4083 .tx_write = efx_ef10_tx_write, 4084 .tx_limit_len = efx_ef10_tx_limit_len, 4085 .tx_enqueue = __efx_enqueue_skb, 4086 .rx_push_rss_config = efx_mcdi_vf_rx_push_rss_config, 4087 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4088 .rx_probe = efx_mcdi_rx_probe, 4089 .rx_init = efx_mcdi_rx_init, 4090 .rx_remove = efx_mcdi_rx_remove, 4091 .rx_write = efx_ef10_rx_write, 4092 .rx_defer_refill = efx_ef10_rx_defer_refill, 4093 .rx_packet = __efx_rx_packet, 4094 .ev_probe = efx_mcdi_ev_probe, 4095 .ev_init = efx_ef10_ev_init, 4096 .ev_fini = efx_mcdi_ev_fini, 4097 .ev_remove = efx_mcdi_ev_remove, 4098 .ev_process = efx_ef10_ev_process, 4099 .ev_read_ack = efx_ef10_ev_read_ack, 4100 .ev_test_generate = efx_ef10_ev_test_generate, 4101 .filter_table_probe = efx_ef10_filter_table_probe, 4102 .filter_table_restore = efx_mcdi_filter_table_restore, 4103 .filter_table_remove = efx_ef10_filter_table_remove, 4104 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4105 .filter_insert = efx_mcdi_filter_insert, 4106 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4107 .filter_get_safe = efx_mcdi_filter_get_safe, 4108 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4109 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4110 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4111 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4112 #ifdef CONFIG_RFS_ACCEL 4113 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4114 #endif 4115 #ifdef CONFIG_SFC_MTD 4116 .mtd_probe = efx_port_dummy_op_int, 4117 #endif 4118 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4119 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4120 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4121 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4122 #ifdef CONFIG_SFC_SRIOV 4123 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4124 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4125 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4126 #endif 4127 .get_mac_address = efx_ef10_get_mac_address_vf, 4128 .set_mac_address = efx_ef10_set_mac_address, 4129 4130 .get_phys_port_id = efx_ef10_get_phys_port_id, 4131 .revision = EFX_REV_HUNT_A0, 4132 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4133 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4134 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4135 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4136 .can_rx_scatter = true, 4137 .always_rx_scatter = true, 4138 .min_interrupt_mode = EFX_INT_MODE_MSIX, 4139 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4140 .offload_features = EF10_OFFLOAD_FEATURES, 4141 .mcdi_max_ver = 2, 4142 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4143 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4144 1 << HWTSTAMP_FILTER_ALL, 4145 .rx_hash_key_size = 40, 4146 .check_caps = ef10_check_caps, 4147 .print_additional_fwver = efx_ef10_print_additional_fwver, 4148 .sensor_event = efx_mcdi_sensor_event, 4149 .rx_recycle_ring_size = efx_ef10_recycle_ring_size, 4150 }; 4151 4152 const struct efx_nic_type efx_hunt_a0_nic_type = { 4153 .is_vf = false, 4154 .mem_bar = efx_ef10_pf_mem_bar, 4155 .mem_map_size = efx_ef10_mem_map_size, 4156 .probe = efx_ef10_probe_pf, 4157 .remove = efx_ef10_remove, 4158 .dimension_resources = efx_ef10_dimension_resources, 4159 .init = efx_ef10_init_nic, 4160 .fini = efx_ef10_fini_nic, 4161 .map_reset_reason = efx_ef10_map_reset_reason, 4162 .map_reset_flags = efx_ef10_map_reset_flags, 4163 .reset = efx_ef10_reset, 4164 .probe_port = efx_mcdi_port_probe, 4165 .remove_port = efx_mcdi_port_remove, 4166 .fini_dmaq = efx_fini_dmaq, 4167 .prepare_flr = efx_ef10_prepare_flr, 4168 .finish_flr = efx_port_dummy_op_void, 4169 .describe_stats = efx_ef10_describe_stats, 4170 .update_stats = efx_ef10_update_stats_pf, 4171 .start_stats = efx_mcdi_mac_start_stats, 4172 .pull_stats = efx_mcdi_mac_pull_stats, 4173 .stop_stats = efx_mcdi_mac_stop_stats, 4174 .push_irq_moderation = efx_ef10_push_irq_moderation, 4175 .reconfigure_mac = efx_ef10_mac_reconfigure, 4176 .check_mac_fault = efx_mcdi_mac_check_fault, 4177 .reconfigure_port = efx_mcdi_port_reconfigure, 4178 .get_wol = efx_ef10_get_wol, 4179 .set_wol = efx_ef10_set_wol, 4180 .resume_wol = efx_port_dummy_op_void, 4181 .get_fec_stats = efx_ef10_get_fec_stats, 4182 .test_chip = efx_ef10_test_chip, 4183 .test_nvram = efx_mcdi_nvram_test_all, 4184 .mcdi_request = efx_ef10_mcdi_request, 4185 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4186 .mcdi_read_response = efx_ef10_mcdi_read_response, 4187 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4188 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4189 .irq_enable_master = efx_port_dummy_op_void, 4190 .irq_test_generate = efx_ef10_irq_test_generate, 4191 .irq_disable_non_ev = efx_port_dummy_op_void, 4192 .irq_handle_msi = efx_ef10_msi_interrupt, 4193 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4194 .tx_probe = efx_ef10_tx_probe, 4195 .tx_init = efx_ef10_tx_init, 4196 .tx_remove = efx_mcdi_tx_remove, 4197 .tx_write = efx_ef10_tx_write, 4198 .tx_limit_len = efx_ef10_tx_limit_len, 4199 .tx_enqueue = __efx_enqueue_skb, 4200 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 4201 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4202 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 4203 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 4204 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 4205 .rx_probe = efx_mcdi_rx_probe, 4206 .rx_init = efx_mcdi_rx_init, 4207 .rx_remove = efx_mcdi_rx_remove, 4208 .rx_write = efx_ef10_rx_write, 4209 .rx_defer_refill = efx_ef10_rx_defer_refill, 4210 .rx_packet = __efx_rx_packet, 4211 .ev_probe = efx_mcdi_ev_probe, 4212 .ev_init = efx_ef10_ev_init, 4213 .ev_fini = efx_mcdi_ev_fini, 4214 .ev_remove = efx_mcdi_ev_remove, 4215 .ev_process = efx_ef10_ev_process, 4216 .ev_read_ack = efx_ef10_ev_read_ack, 4217 .ev_test_generate = efx_ef10_ev_test_generate, 4218 .filter_table_probe = efx_ef10_filter_table_probe, 4219 .filter_table_restore = efx_mcdi_filter_table_restore, 4220 .filter_table_remove = efx_ef10_filter_table_remove, 4221 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4222 .filter_insert = efx_mcdi_filter_insert, 4223 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4224 .filter_get_safe = efx_mcdi_filter_get_safe, 4225 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4226 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4227 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4228 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4229 #ifdef CONFIG_RFS_ACCEL 4230 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4231 #endif 4232 #ifdef CONFIG_SFC_MTD 4233 .mtd_probe = efx_ef10_mtd_probe, 4234 .mtd_rename = efx_mcdi_mtd_rename, 4235 .mtd_read = efx_mcdi_mtd_read, 4236 .mtd_erase = efx_mcdi_mtd_erase, 4237 .mtd_write = efx_mcdi_mtd_write, 4238 .mtd_sync = efx_mcdi_mtd_sync, 4239 #endif 4240 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4241 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4242 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4243 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4244 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4245 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports, 4246 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port, 4247 #ifdef CONFIG_SFC_SRIOV 4248 .sriov_configure = efx_ef10_sriov_configure, 4249 .sriov_init = efx_ef10_sriov_init, 4250 .sriov_fini = efx_ef10_sriov_fini, 4251 .sriov_wanted = efx_ef10_sriov_wanted, 4252 .sriov_reset = efx_ef10_sriov_reset, 4253 .sriov_flr = efx_ef10_sriov_flr, 4254 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4255 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4256 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4257 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4258 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4259 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4260 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4261 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4262 #endif 4263 .get_mac_address = efx_ef10_get_mac_address_pf, 4264 .set_mac_address = efx_ef10_set_mac_address, 4265 .tso_versions = efx_ef10_tso_versions, 4266 4267 .get_phys_port_id = efx_ef10_get_phys_port_id, 4268 .revision = EFX_REV_HUNT_A0, 4269 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4270 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4271 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4272 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4273 .can_rx_scatter = true, 4274 .always_rx_scatter = true, 4275 .option_descriptors = true, 4276 .min_interrupt_mode = EFX_INT_MODE_LEGACY, 4277 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4278 .offload_features = EF10_OFFLOAD_FEATURES, 4279 .mcdi_max_ver = 2, 4280 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4281 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4282 1 << HWTSTAMP_FILTER_ALL, 4283 .rx_hash_key_size = 40, 4284 .check_caps = ef10_check_caps, 4285 .print_additional_fwver = efx_ef10_print_additional_fwver, 4286 .sensor_event = efx_mcdi_sensor_event, 4287 .rx_recycle_ring_size = efx_ef10_recycle_ring_size, 4288 }; 4289