1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2012-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 #include "net_driver.h" 11 #include "ef10_regs.h" 12 #include "io.h" 13 #include "mcdi.h" 14 #include "mcdi_pcol.h" 15 #include "nic.h" 16 #include "workarounds.h" 17 #include "selftest.h" 18 #include "ef10_sriov.h" 19 #include <linux/in.h> 20 #include <linux/jhash.h> 21 #include <linux/wait.h> 22 #include <linux/workqueue.h> 23 24 /* Hardware control for EF10 architecture including 'Huntington'. */ 25 26 #define EFX_EF10_DRVGEN_EV 7 27 enum { 28 EFX_EF10_TEST = 1, 29 EFX_EF10_REFILL, 30 }; 31 32 /* The reserved RSS context value */ 33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff 34 /* The maximum size of a shared RSS context */ 35 /* TODO: this should really be from the mcdi protocol export */ 36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL 37 38 /* The filter table(s) are managed by firmware and we have write-only 39 * access. When removing filters we must identify them to the 40 * firmware by a 64-bit handle, but this is too wide for Linux kernel 41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to 42 * be able to tell in advance whether a requested insertion will 43 * replace an existing filter. Therefore we maintain a software hash 44 * table, which should be at least as large as the hardware hash 45 * table. 46 * 47 * Huntington has a single 8K filter table shared between all filter 48 * types and both ports. 49 */ 50 #define HUNT_FILTER_TBL_ROWS 8192 51 52 #define EFX_EF10_FILTER_ID_INVALID 0xffff 53 struct efx_ef10_dev_addr { 54 u8 addr[ETH_ALEN]; 55 u16 id; 56 }; 57 58 struct efx_ef10_filter_table { 59 /* The RX match field masks supported by this fw & hw, in order of priority */ 60 enum efx_filter_match_flags rx_match_flags[ 61 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM]; 62 unsigned int rx_match_count; 63 64 struct { 65 unsigned long spec; /* pointer to spec plus flag bits */ 66 /* BUSY flag indicates that an update is in progress. AUTO_OLD is 67 * used to mark and sweep MAC filters for the device address lists. 68 */ 69 #define EFX_EF10_FILTER_FLAG_BUSY 1UL 70 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL 71 #define EFX_EF10_FILTER_FLAGS 3UL 72 u64 handle; /* firmware handle */ 73 } *entry; 74 wait_queue_head_t waitq; 75 /* Shadow of net_device address lists, guarded by mac_lock */ 76 #define EFX_EF10_FILTER_DEV_UC_MAX 32 77 #define EFX_EF10_FILTER_DEV_MC_MAX 256 78 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX]; 79 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX]; 80 int dev_uc_count; 81 int dev_mc_count; 82 /* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */ 83 u16 ucdef_id; 84 u16 bcast_id; 85 u16 mcdef_id; 86 }; 87 88 /* An arbitrary search limit for the software hash table */ 89 #define EFX_EF10_FILTER_SEARCH_LIMIT 200 90 91 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx); 92 static void efx_ef10_filter_table_remove(struct efx_nic *efx); 93 94 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 95 { 96 efx_dword_t reg; 97 98 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 99 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 100 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 101 } 102 103 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 104 { 105 int bar; 106 107 bar = efx->type->mem_bar; 108 return resource_size(&efx->pci_dev->resource[bar]); 109 } 110 111 static bool efx_ef10_is_vf(struct efx_nic *efx) 112 { 113 return efx->type->is_vf; 114 } 115 116 static int efx_ef10_get_pf_index(struct efx_nic *efx) 117 { 118 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 119 struct efx_ef10_nic_data *nic_data = efx->nic_data; 120 size_t outlen; 121 int rc; 122 123 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 124 sizeof(outbuf), &outlen); 125 if (rc) 126 return rc; 127 if (outlen < sizeof(outbuf)) 128 return -EIO; 129 130 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF); 131 return 0; 132 } 133 134 #ifdef CONFIG_SFC_SRIOV 135 static int efx_ef10_get_vf_index(struct efx_nic *efx) 136 { 137 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 138 struct efx_ef10_nic_data *nic_data = efx->nic_data; 139 size_t outlen; 140 int rc; 141 142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 143 sizeof(outbuf), &outlen); 144 if (rc) 145 return rc; 146 if (outlen < sizeof(outbuf)) 147 return -EIO; 148 149 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 150 return 0; 151 } 152 #endif 153 154 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 155 { 156 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN); 157 struct efx_ef10_nic_data *nic_data = efx->nic_data; 158 size_t outlen; 159 int rc; 160 161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 162 163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 164 outbuf, sizeof(outbuf), &outlen); 165 if (rc) 166 return rc; 167 if (outlen < sizeof(outbuf)) { 168 netif_err(efx, drv, efx->net_dev, 169 "unable to read datapath firmware capabilities\n"); 170 return -EIO; 171 } 172 173 nic_data->datapath_caps = 174 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 175 176 /* record the DPCPU firmware IDs to determine VEB vswitching support. 177 */ 178 nic_data->rx_dpcpu_fw_id = 179 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 180 nic_data->tx_dpcpu_fw_id = 181 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 182 183 if (!(nic_data->datapath_caps & 184 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) { 185 netif_err(efx, drv, efx->net_dev, 186 "current firmware does not support TSO\n"); 187 return -ENODEV; 188 } 189 190 if (!(nic_data->datapath_caps & 191 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 192 netif_err(efx, probe, efx->net_dev, 193 "current firmware does not support an RX prefix\n"); 194 return -ENODEV; 195 } 196 197 return 0; 198 } 199 200 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 201 { 202 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 203 int rc; 204 205 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 206 outbuf, sizeof(outbuf), NULL); 207 if (rc) 208 return rc; 209 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 210 return rc > 0 ? rc : -ERANGE; 211 } 212 213 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 214 { 215 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 216 size_t outlen; 217 int rc; 218 219 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 220 221 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 222 outbuf, sizeof(outbuf), &outlen); 223 if (rc) 224 return rc; 225 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 226 return -EIO; 227 228 ether_addr_copy(mac_address, 229 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 230 return 0; 231 } 232 233 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 234 { 235 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 236 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 237 size_t outlen; 238 int num_addrs, rc; 239 240 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 241 EVB_PORT_ID_ASSIGNED); 242 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 243 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 244 245 if (rc) 246 return rc; 247 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 248 return -EIO; 249 250 num_addrs = MCDI_DWORD(outbuf, 251 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 252 253 WARN_ON(num_addrs != 1); 254 255 ether_addr_copy(mac_address, 256 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 257 258 return 0; 259 } 260 261 static ssize_t efx_ef10_show_link_control_flag(struct device *dev, 262 struct device_attribute *attr, 263 char *buf) 264 { 265 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 266 267 return sprintf(buf, "%d\n", 268 ((efx->mcdi->fn_flags) & 269 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 270 ? 1 : 0); 271 } 272 273 static ssize_t efx_ef10_show_primary_flag(struct device *dev, 274 struct device_attribute *attr, 275 char *buf) 276 { 277 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 278 279 return sprintf(buf, "%d\n", 280 ((efx->mcdi->fn_flags) & 281 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 282 ? 1 : 0); 283 } 284 285 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag, 286 NULL); 287 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL); 288 289 static int efx_ef10_probe(struct efx_nic *efx) 290 { 291 struct efx_ef10_nic_data *nic_data; 292 struct net_device *net_dev = efx->net_dev; 293 int i, rc; 294 295 /* We can have one VI for each 8K region. However, until we 296 * use TX option descriptors we need two TX queues per channel. 297 */ 298 efx->max_channels = 299 min_t(unsigned int, 300 EFX_MAX_CHANNELS, 301 efx_ef10_mem_map_size(efx) / 302 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES)); 303 if (WARN_ON(efx->max_channels == 0)) 304 return -EIO; 305 306 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 307 if (!nic_data) 308 return -ENOMEM; 309 efx->nic_data = nic_data; 310 311 /* we assume later that we can copy from this buffer in dwords */ 312 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 313 314 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 315 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 316 if (rc) 317 goto fail1; 318 319 /* Get the MC's warm boot count. In case it's rebooting right 320 * now, be prepared to retry. 321 */ 322 i = 0; 323 for (;;) { 324 rc = efx_ef10_get_warm_boot_count(efx); 325 if (rc >= 0) 326 break; 327 if (++i == 5) 328 goto fail2; 329 ssleep(1); 330 } 331 nic_data->warm_boot_count = rc; 332 333 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 334 335 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 336 337 /* In case we're recovering from a crash (kexec), we want to 338 * cancel any outstanding request by the previous user of this 339 * function. We send a special message using the least 340 * significant bits of the 'high' (doorbell) register. 341 */ 342 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 343 344 rc = efx_mcdi_init(efx); 345 if (rc) 346 goto fail2; 347 348 /* Reset (most) configuration for this function */ 349 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 350 if (rc) 351 goto fail3; 352 353 /* Enable event logging */ 354 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 355 if (rc) 356 goto fail3; 357 358 rc = device_create_file(&efx->pci_dev->dev, 359 &dev_attr_link_control_flag); 360 if (rc) 361 goto fail3; 362 363 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 364 if (rc) 365 goto fail4; 366 367 rc = efx_ef10_get_pf_index(efx); 368 if (rc) 369 goto fail5; 370 371 rc = efx_ef10_init_datapath_caps(efx); 372 if (rc < 0) 373 goto fail5; 374 375 efx->rx_packet_len_offset = 376 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 377 378 rc = efx_mcdi_port_get_number(efx); 379 if (rc < 0) 380 goto fail5; 381 efx->port_num = rc; 382 net_dev->dev_port = rc; 383 384 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 385 if (rc) 386 goto fail5; 387 388 rc = efx_ef10_get_sysclk_freq(efx); 389 if (rc < 0) 390 goto fail5; 391 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */ 392 393 /* Check whether firmware supports bug 35388 workaround. 394 * First try to enable it, then if we get EPERM, just 395 * ask if it's already enabled 396 */ 397 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL); 398 if (rc == 0) { 399 nic_data->workaround_35388 = true; 400 } else if (rc == -EPERM) { 401 unsigned int enabled; 402 403 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled); 404 if (rc) 405 goto fail3; 406 nic_data->workaround_35388 = enabled & 407 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388; 408 } else if (rc != -ENOSYS && rc != -ENOENT) { 409 goto fail5; 410 } 411 netif_dbg(efx, probe, efx->net_dev, 412 "workaround for bug 35388 is %sabled\n", 413 nic_data->workaround_35388 ? "en" : "dis"); 414 415 rc = efx_mcdi_mon_probe(efx); 416 if (rc && rc != -EPERM) 417 goto fail5; 418 419 efx_ptp_probe(efx, NULL); 420 421 #ifdef CONFIG_SFC_SRIOV 422 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 423 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 424 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 425 426 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 427 } else 428 #endif 429 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 430 431 return 0; 432 433 fail5: 434 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 435 fail4: 436 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 437 fail3: 438 efx_mcdi_fini(efx); 439 fail2: 440 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 441 fail1: 442 kfree(nic_data); 443 efx->nic_data = NULL; 444 return rc; 445 } 446 447 static int efx_ef10_free_vis(struct efx_nic *efx) 448 { 449 MCDI_DECLARE_BUF_ERR(outbuf); 450 size_t outlen; 451 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, 452 outbuf, sizeof(outbuf), &outlen); 453 454 /* -EALREADY means nothing to free, so ignore */ 455 if (rc == -EALREADY) 456 rc = 0; 457 if (rc) 458 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, 459 rc); 460 return rc; 461 } 462 463 #ifdef EFX_USE_PIO 464 465 static void efx_ef10_free_piobufs(struct efx_nic *efx) 466 { 467 struct efx_ef10_nic_data *nic_data = efx->nic_data; 468 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 469 unsigned int i; 470 int rc; 471 472 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 473 474 for (i = 0; i < nic_data->n_piobufs; i++) { 475 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 476 nic_data->piobuf_handle[i]); 477 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 478 NULL, 0, NULL); 479 WARN_ON(rc); 480 } 481 482 nic_data->n_piobufs = 0; 483 } 484 485 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 486 { 487 struct efx_ef10_nic_data *nic_data = efx->nic_data; 488 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 489 unsigned int i; 490 size_t outlen; 491 int rc = 0; 492 493 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 494 495 for (i = 0; i < n; i++) { 496 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 497 outbuf, sizeof(outbuf), &outlen); 498 if (rc) 499 break; 500 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 501 rc = -EIO; 502 break; 503 } 504 nic_data->piobuf_handle[i] = 505 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 506 netif_dbg(efx, probe, efx->net_dev, 507 "allocated PIO buffer %u handle %x\n", i, 508 nic_data->piobuf_handle[i]); 509 } 510 511 nic_data->n_piobufs = i; 512 if (rc) 513 efx_ef10_free_piobufs(efx); 514 return rc; 515 } 516 517 static int efx_ef10_link_piobufs(struct efx_nic *efx) 518 { 519 struct efx_ef10_nic_data *nic_data = efx->nic_data; 520 _MCDI_DECLARE_BUF(inbuf, 521 max(MC_CMD_LINK_PIOBUF_IN_LEN, 522 MC_CMD_UNLINK_PIOBUF_IN_LEN)); 523 struct efx_channel *channel; 524 struct efx_tx_queue *tx_queue; 525 unsigned int offset, index; 526 int rc; 527 528 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 529 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 530 531 memset(inbuf, 0, sizeof(inbuf)); 532 533 /* Link a buffer to each VI in the write-combining mapping */ 534 for (index = 0; index < nic_data->n_piobufs; ++index) { 535 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 536 nic_data->piobuf_handle[index]); 537 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 538 nic_data->pio_write_vi_base + index); 539 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 540 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 541 NULL, 0, NULL); 542 if (rc) { 543 netif_err(efx, drv, efx->net_dev, 544 "failed to link VI %u to PIO buffer %u (%d)\n", 545 nic_data->pio_write_vi_base + index, index, 546 rc); 547 goto fail; 548 } 549 netif_dbg(efx, probe, efx->net_dev, 550 "linked VI %u to PIO buffer %u\n", 551 nic_data->pio_write_vi_base + index, index); 552 } 553 554 /* Link a buffer to each TX queue */ 555 efx_for_each_channel(channel, efx) { 556 efx_for_each_channel_tx_queue(tx_queue, channel) { 557 /* We assign the PIO buffers to queues in 558 * reverse order to allow for the following 559 * special case. 560 */ 561 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 562 tx_queue->channel->channel - 1) * 563 efx_piobuf_size); 564 index = offset / ER_DZ_TX_PIOBUF_SIZE; 565 offset = offset % ER_DZ_TX_PIOBUF_SIZE; 566 567 /* When the host page size is 4K, the first 568 * host page in the WC mapping may be within 569 * the same VI page as the last TX queue. We 570 * can only link one buffer to each VI. 571 */ 572 if (tx_queue->queue == nic_data->pio_write_vi_base) { 573 BUG_ON(index != 0); 574 rc = 0; 575 } else { 576 MCDI_SET_DWORD(inbuf, 577 LINK_PIOBUF_IN_PIOBUF_HANDLE, 578 nic_data->piobuf_handle[index]); 579 MCDI_SET_DWORD(inbuf, 580 LINK_PIOBUF_IN_TXQ_INSTANCE, 581 tx_queue->queue); 582 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 583 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 584 NULL, 0, NULL); 585 } 586 587 if (rc) { 588 /* This is non-fatal; the TX path just 589 * won't use PIO for this queue 590 */ 591 netif_err(efx, drv, efx->net_dev, 592 "failed to link VI %u to PIO buffer %u (%d)\n", 593 tx_queue->queue, index, rc); 594 tx_queue->piobuf = NULL; 595 } else { 596 tx_queue->piobuf = 597 nic_data->pio_write_base + 598 index * EFX_VI_PAGE_SIZE + offset; 599 tx_queue->piobuf_offset = offset; 600 netif_dbg(efx, probe, efx->net_dev, 601 "linked VI %u to PIO buffer %u offset %x addr %p\n", 602 tx_queue->queue, index, 603 tx_queue->piobuf_offset, 604 tx_queue->piobuf); 605 } 606 } 607 } 608 609 return 0; 610 611 fail: 612 while (index--) { 613 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 614 nic_data->pio_write_vi_base + index); 615 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 616 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 617 NULL, 0, NULL); 618 } 619 return rc; 620 } 621 622 #else /* !EFX_USE_PIO */ 623 624 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 625 { 626 return n == 0 ? 0 : -ENOBUFS; 627 } 628 629 static int efx_ef10_link_piobufs(struct efx_nic *efx) 630 { 631 return 0; 632 } 633 634 static void efx_ef10_free_piobufs(struct efx_nic *efx) 635 { 636 } 637 638 #endif /* EFX_USE_PIO */ 639 640 static void efx_ef10_remove(struct efx_nic *efx) 641 { 642 struct efx_ef10_nic_data *nic_data = efx->nic_data; 643 int rc; 644 645 #ifdef CONFIG_SFC_SRIOV 646 struct efx_ef10_nic_data *nic_data_pf; 647 struct pci_dev *pci_dev_pf; 648 struct efx_nic *efx_pf; 649 struct ef10_vf *vf; 650 651 if (efx->pci_dev->is_virtfn) { 652 pci_dev_pf = efx->pci_dev->physfn; 653 if (pci_dev_pf) { 654 efx_pf = pci_get_drvdata(pci_dev_pf); 655 nic_data_pf = efx_pf->nic_data; 656 vf = nic_data_pf->vf + nic_data->vf_index; 657 vf->efx = NULL; 658 } else 659 netif_info(efx, drv, efx->net_dev, 660 "Could not get the PF id from VF\n"); 661 } 662 #endif 663 664 efx_ptp_remove(efx); 665 666 efx_mcdi_mon_remove(efx); 667 668 efx_ef10_rx_free_indir_table(efx); 669 670 if (nic_data->wc_membase) 671 iounmap(nic_data->wc_membase); 672 673 rc = efx_ef10_free_vis(efx); 674 WARN_ON(rc != 0); 675 676 if (!nic_data->must_restore_piobufs) 677 efx_ef10_free_piobufs(efx); 678 679 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 680 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 681 682 efx_mcdi_fini(efx); 683 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 684 kfree(nic_data); 685 } 686 687 static int efx_ef10_probe_pf(struct efx_nic *efx) 688 { 689 return efx_ef10_probe(efx); 690 } 691 692 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 693 { 694 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 695 696 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 697 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 698 NULL, 0, NULL); 699 } 700 701 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 702 { 703 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 704 705 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 706 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 707 NULL, 0, NULL); 708 } 709 710 int efx_ef10_vport_add_mac(struct efx_nic *efx, 711 unsigned int port_id, u8 *mac) 712 { 713 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 714 715 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 716 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 717 718 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 719 sizeof(inbuf), NULL, 0, NULL); 720 } 721 722 int efx_ef10_vport_del_mac(struct efx_nic *efx, 723 unsigned int port_id, u8 *mac) 724 { 725 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 726 727 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 728 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 729 730 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 731 sizeof(inbuf), NULL, 0, NULL); 732 } 733 734 #ifdef CONFIG_SFC_SRIOV 735 static int efx_ef10_probe_vf(struct efx_nic *efx) 736 { 737 int rc; 738 struct pci_dev *pci_dev_pf; 739 740 /* If the parent PF has no VF data structure, it doesn't know about this 741 * VF so fail probe. The VF needs to be re-created. This can happen 742 * if the PF driver is unloaded while the VF is assigned to a guest. 743 */ 744 pci_dev_pf = efx->pci_dev->physfn; 745 if (pci_dev_pf) { 746 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 747 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 748 749 if (!nic_data_pf->vf) { 750 netif_info(efx, drv, efx->net_dev, 751 "The VF cannot link to its parent PF; " 752 "please destroy and re-create the VF\n"); 753 return -EBUSY; 754 } 755 } 756 757 rc = efx_ef10_probe(efx); 758 if (rc) 759 return rc; 760 761 rc = efx_ef10_get_vf_index(efx); 762 if (rc) 763 goto fail; 764 765 if (efx->pci_dev->is_virtfn) { 766 if (efx->pci_dev->physfn) { 767 struct efx_nic *efx_pf = 768 pci_get_drvdata(efx->pci_dev->physfn); 769 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 770 struct efx_ef10_nic_data *nic_data = efx->nic_data; 771 772 nic_data_p->vf[nic_data->vf_index].efx = efx; 773 nic_data_p->vf[nic_data->vf_index].pci_dev = 774 efx->pci_dev; 775 } else 776 netif_info(efx, drv, efx->net_dev, 777 "Could not get the PF id from VF\n"); 778 } 779 780 return 0; 781 782 fail: 783 efx_ef10_remove(efx); 784 return rc; 785 } 786 #else 787 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 788 { 789 return 0; 790 } 791 #endif 792 793 static int efx_ef10_alloc_vis(struct efx_nic *efx, 794 unsigned int min_vis, unsigned int max_vis) 795 { 796 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); 797 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); 798 struct efx_ef10_nic_data *nic_data = efx->nic_data; 799 size_t outlen; 800 int rc; 801 802 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); 803 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); 804 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), 805 outbuf, sizeof(outbuf), &outlen); 806 if (rc != 0) 807 return rc; 808 809 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) 810 return -EIO; 811 812 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", 813 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); 814 815 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); 816 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); 817 return 0; 818 } 819 820 /* Note that the failure path of this function does not free 821 * resources, as this will be done by efx_ef10_remove(). 822 */ 823 static int efx_ef10_dimension_resources(struct efx_nic *efx) 824 { 825 struct efx_ef10_nic_data *nic_data = efx->nic_data; 826 unsigned int uc_mem_map_size, wc_mem_map_size; 827 unsigned int min_vis, pio_write_vi_base, max_vis; 828 void __iomem *membase; 829 int rc; 830 831 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); 832 833 #ifdef EFX_USE_PIO 834 /* Try to allocate PIO buffers if wanted and if the full 835 * number of PIO buffers would be sufficient to allocate one 836 * copy-buffer per TX channel. Failure is non-fatal, as there 837 * are only a small number of PIO buffers shared between all 838 * functions of the controller. 839 */ 840 if (efx_piobuf_size != 0 && 841 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 842 efx->n_tx_channels) { 843 unsigned int n_piobufs = 844 DIV_ROUND_UP(efx->n_tx_channels, 845 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size); 846 847 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 848 if (rc) 849 netif_err(efx, probe, efx->net_dev, 850 "failed to allocate PIO buffers (%d)\n", rc); 851 else 852 netif_dbg(efx, probe, efx->net_dev, 853 "allocated %u PIO buffers\n", n_piobufs); 854 } 855 #else 856 nic_data->n_piobufs = 0; 857 #endif 858 859 /* PIO buffers should be mapped with write-combining enabled, 860 * and we want to make single UC and WC mappings rather than 861 * several of each (in fact that's the only option if host 862 * page size is >4K). So we may allocate some extra VIs just 863 * for writing PIO buffers through. 864 * 865 * The UC mapping contains (min_vis - 1) complete VIs and the 866 * first half of the next VI. Then the WC mapping begins with 867 * the second half of this last VI. 868 */ 869 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE + 870 ER_DZ_TX_PIOBUF); 871 if (nic_data->n_piobufs) { 872 /* pio_write_vi_base rounds down to give the number of complete 873 * VIs inside the UC mapping. 874 */ 875 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; 876 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 877 nic_data->n_piobufs) * 878 EFX_VI_PAGE_SIZE) - 879 uc_mem_map_size); 880 max_vis = pio_write_vi_base + nic_data->n_piobufs; 881 } else { 882 pio_write_vi_base = 0; 883 wc_mem_map_size = 0; 884 max_vis = min_vis; 885 } 886 887 /* In case the last attached driver failed to free VIs, do it now */ 888 rc = efx_ef10_free_vis(efx); 889 if (rc != 0) 890 return rc; 891 892 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 893 if (rc != 0) 894 return rc; 895 896 /* If we didn't get enough VIs to map all the PIO buffers, free the 897 * PIO buffers 898 */ 899 if (nic_data->n_piobufs && 900 nic_data->n_allocated_vis < 901 pio_write_vi_base + nic_data->n_piobufs) { 902 netif_dbg(efx, probe, efx->net_dev, 903 "%u VIs are not sufficient to map %u PIO buffers\n", 904 nic_data->n_allocated_vis, nic_data->n_piobufs); 905 efx_ef10_free_piobufs(efx); 906 } 907 908 /* Shrink the original UC mapping of the memory BAR */ 909 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); 910 if (!membase) { 911 netif_err(efx, probe, efx->net_dev, 912 "could not shrink memory BAR to %x\n", 913 uc_mem_map_size); 914 return -ENOMEM; 915 } 916 iounmap(efx->membase); 917 efx->membase = membase; 918 919 /* Set up the WC mapping if needed */ 920 if (wc_mem_map_size) { 921 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 922 uc_mem_map_size, 923 wc_mem_map_size); 924 if (!nic_data->wc_membase) { 925 netif_err(efx, probe, efx->net_dev, 926 "could not allocate WC mapping of size %x\n", 927 wc_mem_map_size); 928 return -ENOMEM; 929 } 930 nic_data->pio_write_vi_base = pio_write_vi_base; 931 nic_data->pio_write_base = 932 nic_data->wc_membase + 933 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF - 934 uc_mem_map_size); 935 936 rc = efx_ef10_link_piobufs(efx); 937 if (rc) 938 efx_ef10_free_piobufs(efx); 939 } 940 941 netif_dbg(efx, probe, efx->net_dev, 942 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 943 &efx->membase_phys, efx->membase, uc_mem_map_size, 944 nic_data->wc_membase, wc_mem_map_size); 945 946 return 0; 947 } 948 949 static int efx_ef10_init_nic(struct efx_nic *efx) 950 { 951 struct efx_ef10_nic_data *nic_data = efx->nic_data; 952 int rc; 953 954 if (nic_data->must_check_datapath_caps) { 955 rc = efx_ef10_init_datapath_caps(efx); 956 if (rc) 957 return rc; 958 nic_data->must_check_datapath_caps = false; 959 } 960 961 if (nic_data->must_realloc_vis) { 962 /* We cannot let the number of VIs change now */ 963 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 964 nic_data->n_allocated_vis); 965 if (rc) 966 return rc; 967 nic_data->must_realloc_vis = false; 968 } 969 970 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 971 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 972 if (rc == 0) { 973 rc = efx_ef10_link_piobufs(efx); 974 if (rc) 975 efx_ef10_free_piobufs(efx); 976 } 977 978 /* Log an error on failure, but this is non-fatal */ 979 if (rc) 980 netif_err(efx, drv, efx->net_dev, 981 "failed to restore PIO buffers (%d)\n", rc); 982 nic_data->must_restore_piobufs = false; 983 } 984 985 /* don't fail init if RSS setup doesn't work */ 986 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table); 987 988 return 0; 989 } 990 991 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx) 992 { 993 struct efx_ef10_nic_data *nic_data = efx->nic_data; 994 #ifdef CONFIG_SFC_SRIOV 995 unsigned int i; 996 #endif 997 998 /* All our allocations have been reset */ 999 nic_data->must_realloc_vis = true; 1000 nic_data->must_restore_filters = true; 1001 nic_data->must_restore_piobufs = true; 1002 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 1003 1004 /* Driver-created vswitches and vports must be re-created */ 1005 nic_data->must_probe_vswitching = true; 1006 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 1007 #ifdef CONFIG_SFC_SRIOV 1008 if (nic_data->vf) 1009 for (i = 0; i < efx->vf_count; i++) 1010 nic_data->vf[i].vport_id = 0; 1011 #endif 1012 } 1013 1014 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1015 { 1016 if (reason == RESET_TYPE_MC_FAILURE) 1017 return RESET_TYPE_DATAPATH; 1018 1019 return efx_mcdi_map_reset_reason(reason); 1020 } 1021 1022 static int efx_ef10_map_reset_flags(u32 *flags) 1023 { 1024 enum { 1025 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1026 ETH_RESET_SHARED_SHIFT), 1027 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1028 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1029 ETH_RESET_PHY | ETH_RESET_MGMT) << 1030 ETH_RESET_SHARED_SHIFT) 1031 }; 1032 1033 /* We assume for now that our PCI function is permitted to 1034 * reset everything. 1035 */ 1036 1037 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1038 *flags &= ~EF10_RESET_MC; 1039 return RESET_TYPE_WORLD; 1040 } 1041 1042 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1043 *flags &= ~EF10_RESET_PORT; 1044 return RESET_TYPE_ALL; 1045 } 1046 1047 /* no invisible reset implemented */ 1048 1049 return -EINVAL; 1050 } 1051 1052 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1053 { 1054 int rc = efx_mcdi_reset(efx, reset_type); 1055 1056 /* Unprivileged functions return -EPERM, but need to return success 1057 * here so that the datapath is brought back up. 1058 */ 1059 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1060 rc = 0; 1061 1062 /* If it was a port reset, trigger reallocation of MC resources. 1063 * Note that on an MC reset nothing needs to be done now because we'll 1064 * detect the MC reset later and handle it then. 1065 * For an FLR, we never get an MC reset event, but the MC has reset all 1066 * resources assigned to us, so we have to trigger reallocation now. 1067 */ 1068 if ((reset_type == RESET_TYPE_ALL || 1069 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1070 efx_ef10_reset_mc_allocations(efx); 1071 return rc; 1072 } 1073 1074 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1075 [EF10_STAT_ ## ext_name] = \ 1076 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1077 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1078 [EF10_STAT_ ## int_name] = \ 1079 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1080 #define EF10_OTHER_STAT(ext_name) \ 1081 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1082 #define GENERIC_SW_STAT(ext_name) \ 1083 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1084 1085 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1086 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1087 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1088 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1089 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1090 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1091 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1092 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1093 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1094 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1095 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1096 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1097 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1098 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1099 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1100 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1101 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1102 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1103 EF10_OTHER_STAT(port_rx_good_bytes), 1104 EF10_OTHER_STAT(port_rx_bad_bytes), 1105 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1106 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1107 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1108 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1109 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1110 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1111 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1112 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1113 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1114 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1115 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1116 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1117 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1118 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1119 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1120 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1121 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1122 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1123 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1124 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1125 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1126 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1127 GENERIC_SW_STAT(rx_nodesc_trunc), 1128 GENERIC_SW_STAT(rx_noskb_drops), 1129 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1130 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1131 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1132 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1133 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1134 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1135 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1136 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1137 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1138 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1139 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1140 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1141 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1142 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1143 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1144 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1145 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1146 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1147 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1148 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1149 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1150 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1151 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1152 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1153 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1154 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1155 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1156 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1157 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1158 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1159 }; 1160 1161 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1162 (1ULL << EF10_STAT_port_tx_packets) | \ 1163 (1ULL << EF10_STAT_port_tx_pause) | \ 1164 (1ULL << EF10_STAT_port_tx_unicast) | \ 1165 (1ULL << EF10_STAT_port_tx_multicast) | \ 1166 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1167 (1ULL << EF10_STAT_port_rx_bytes) | \ 1168 (1ULL << \ 1169 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1170 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1171 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1172 (1ULL << EF10_STAT_port_rx_packets) | \ 1173 (1ULL << EF10_STAT_port_rx_good) | \ 1174 (1ULL << EF10_STAT_port_rx_bad) | \ 1175 (1ULL << EF10_STAT_port_rx_pause) | \ 1176 (1ULL << EF10_STAT_port_rx_control) | \ 1177 (1ULL << EF10_STAT_port_rx_unicast) | \ 1178 (1ULL << EF10_STAT_port_rx_multicast) | \ 1179 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1180 (1ULL << EF10_STAT_port_rx_lt64) | \ 1181 (1ULL << EF10_STAT_port_rx_64) | \ 1182 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1183 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1184 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1185 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1186 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1187 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1188 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1189 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1190 (1ULL << EF10_STAT_port_rx_overflow) | \ 1191 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1192 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1193 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1194 1195 /* These statistics are only provided by the 10G MAC. For a 10G/40G 1196 * switchable port we do not expose these because they might not 1197 * include all the packets they should. 1198 */ 1199 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1200 (1ULL << EF10_STAT_port_tx_lt64) | \ 1201 (1ULL << EF10_STAT_port_tx_64) | \ 1202 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1203 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1204 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1205 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1206 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1207 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1208 1209 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1210 * switchable port we do expose these because the errors will otherwise 1211 * be silent. 1212 */ 1213 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1214 (1ULL << EF10_STAT_port_rx_length_error)) 1215 1216 /* These statistics are only provided if the firmware supports the 1217 * capability PM_AND_RXDP_COUNTERS. 1218 */ 1219 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1220 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1221 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1222 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1223 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1224 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1225 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1226 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1227 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1228 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1229 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1230 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1231 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1232 1233 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1234 { 1235 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1236 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1237 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1238 1239 if (!(efx->mcdi->fn_flags & 1240 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1241 return 0; 1242 1243 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) 1244 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1245 else 1246 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1247 1248 if (nic_data->datapath_caps & 1249 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1250 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1251 1252 return raw_mask; 1253 } 1254 1255 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1256 { 1257 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1258 u64 raw_mask[2]; 1259 1260 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1261 1262 /* Only show vadaptor stats when EVB capability is present */ 1263 if (nic_data->datapath_caps & 1264 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1265 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1266 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1; 1267 } else { 1268 raw_mask[1] = 0; 1269 } 1270 1271 #if BITS_PER_LONG == 64 1272 mask[0] = raw_mask[0]; 1273 mask[1] = raw_mask[1]; 1274 #else 1275 mask[0] = raw_mask[0] & 0xffffffff; 1276 mask[1] = raw_mask[0] >> 32; 1277 mask[2] = raw_mask[1] & 0xffffffff; 1278 mask[3] = raw_mask[1] >> 32; 1279 #endif 1280 } 1281 1282 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1283 { 1284 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1285 1286 efx_ef10_get_stat_mask(efx, mask); 1287 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1288 mask, names); 1289 } 1290 1291 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1292 struct rtnl_link_stats64 *core_stats) 1293 { 1294 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1295 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1296 u64 *stats = nic_data->stats; 1297 size_t stats_count = 0, index; 1298 1299 efx_ef10_get_stat_mask(efx, mask); 1300 1301 if (full_stats) { 1302 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1303 if (efx_ef10_stat_desc[index].name) { 1304 *full_stats++ = stats[index]; 1305 ++stats_count; 1306 } 1307 } 1308 } 1309 1310 if (core_stats) { 1311 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1312 stats[EF10_STAT_rx_multicast] + 1313 stats[EF10_STAT_rx_broadcast]; 1314 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1315 stats[EF10_STAT_tx_multicast] + 1316 stats[EF10_STAT_tx_broadcast]; 1317 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1318 stats[EF10_STAT_rx_multicast_bytes] + 1319 stats[EF10_STAT_rx_broadcast_bytes]; 1320 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1321 stats[EF10_STAT_tx_multicast_bytes] + 1322 stats[EF10_STAT_tx_broadcast_bytes]; 1323 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1324 stats[GENERIC_STAT_rx_noskb_drops]; 1325 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1326 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1327 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1328 core_stats->rx_errors = core_stats->rx_crc_errors; 1329 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1330 } 1331 1332 return stats_count; 1333 } 1334 1335 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx) 1336 { 1337 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1338 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1339 __le64 generation_start, generation_end; 1340 u64 *stats = nic_data->stats; 1341 __le64 *dma_stats; 1342 1343 efx_ef10_get_stat_mask(efx, mask); 1344 1345 dma_stats = efx->stats_buffer.addr; 1346 nic_data = efx->nic_data; 1347 1348 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1349 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 1350 return 0; 1351 rmb(); 1352 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1353 stats, efx->stats_buffer.addr, false); 1354 rmb(); 1355 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1356 if (generation_end != generation_start) 1357 return -EAGAIN; 1358 1359 /* Update derived statistics */ 1360 efx_nic_fix_nodesc_drop_stat(efx, 1361 &stats[EF10_STAT_port_rx_nodesc_drops]); 1362 stats[EF10_STAT_port_rx_good_bytes] = 1363 stats[EF10_STAT_port_rx_bytes] - 1364 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1365 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1366 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1367 efx_update_sw_stats(efx, stats); 1368 return 0; 1369 } 1370 1371 1372 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1373 struct rtnl_link_stats64 *core_stats) 1374 { 1375 int retry; 1376 1377 /* If we're unlucky enough to read statistics during the DMA, wait 1378 * up to 10ms for it to finish (typically takes <500us) 1379 */ 1380 for (retry = 0; retry < 100; ++retry) { 1381 if (efx_ef10_try_update_nic_stats_pf(efx) == 0) 1382 break; 1383 udelay(100); 1384 } 1385 1386 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1387 } 1388 1389 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1390 { 1391 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1392 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1393 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1394 __le64 generation_start, generation_end; 1395 u64 *stats = nic_data->stats; 1396 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64); 1397 struct efx_buffer stats_buf; 1398 __le64 *dma_stats; 1399 int rc; 1400 1401 spin_unlock_bh(&efx->stats_lock); 1402 1403 if (in_interrupt()) { 1404 /* If in atomic context, cannot update stats. Just update the 1405 * software stats and return so the caller can continue. 1406 */ 1407 spin_lock_bh(&efx->stats_lock); 1408 efx_update_sw_stats(efx, stats); 1409 return 0; 1410 } 1411 1412 efx_ef10_get_stat_mask(efx, mask); 1413 1414 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC); 1415 if (rc) { 1416 spin_lock_bh(&efx->stats_lock); 1417 return rc; 1418 } 1419 1420 dma_stats = stats_buf.addr; 1421 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID; 1422 1423 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1424 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1425 MAC_STATS_IN_DMA, 1); 1426 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1427 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1428 1429 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1430 NULL, 0, NULL); 1431 spin_lock_bh(&efx->stats_lock); 1432 if (rc) { 1433 /* Expect ENOENT if DMA queues have not been set up */ 1434 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1435 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1436 sizeof(inbuf), NULL, 0, rc); 1437 goto out; 1438 } 1439 1440 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1441 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1442 WARN_ON_ONCE(1); 1443 goto out; 1444 } 1445 rmb(); 1446 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1447 stats, stats_buf.addr, false); 1448 rmb(); 1449 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1450 if (generation_end != generation_start) { 1451 rc = -EAGAIN; 1452 goto out; 1453 } 1454 1455 efx_update_sw_stats(efx, stats); 1456 out: 1457 efx_nic_free_buffer(efx, &stats_buf); 1458 return rc; 1459 } 1460 1461 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1462 struct rtnl_link_stats64 *core_stats) 1463 { 1464 if (efx_ef10_try_update_nic_stats_vf(efx)) 1465 return 0; 1466 1467 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1468 } 1469 1470 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1471 { 1472 struct efx_nic *efx = channel->efx; 1473 unsigned int mode, value; 1474 efx_dword_t timer_cmd; 1475 1476 if (channel->irq_moderation) { 1477 mode = 3; 1478 value = channel->irq_moderation - 1; 1479 } else { 1480 mode = 0; 1481 value = 0; 1482 } 1483 1484 if (EFX_EF10_WORKAROUND_35388(efx)) { 1485 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1486 EFE_DD_EVQ_IND_TIMER_FLAGS, 1487 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1488 ERF_DD_EVQ_IND_TIMER_VAL, value); 1489 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1490 channel->channel); 1491 } else { 1492 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1493 ERF_DZ_TC_TIMER_VAL, value); 1494 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1495 channel->channel); 1496 } 1497 } 1498 1499 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 1500 struct ethtool_wolinfo *wol) {} 1501 1502 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 1503 { 1504 return -EOPNOTSUPP; 1505 } 1506 1507 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1508 { 1509 wol->supported = 0; 1510 wol->wolopts = 0; 1511 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1512 } 1513 1514 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 1515 { 1516 if (type != 0) 1517 return -EINVAL; 1518 return 0; 1519 } 1520 1521 static void efx_ef10_mcdi_request(struct efx_nic *efx, 1522 const efx_dword_t *hdr, size_t hdr_len, 1523 const efx_dword_t *sdu, size_t sdu_len) 1524 { 1525 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1526 u8 *pdu = nic_data->mcdi_buf.addr; 1527 1528 memcpy(pdu, hdr, hdr_len); 1529 memcpy(pdu + hdr_len, sdu, sdu_len); 1530 wmb(); 1531 1532 /* The hardware provides 'low' and 'high' (doorbell) registers 1533 * for passing the 64-bit address of an MCDI request to 1534 * firmware. However the dwords are swapped by firmware. The 1535 * least significant bits of the doorbell are then 0 for all 1536 * MCDI requests due to alignment. 1537 */ 1538 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 1539 ER_DZ_MC_DB_LWRD); 1540 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 1541 ER_DZ_MC_DB_HWRD); 1542 } 1543 1544 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 1545 { 1546 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1547 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 1548 1549 rmb(); 1550 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 1551 } 1552 1553 static void 1554 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 1555 size_t offset, size_t outlen) 1556 { 1557 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1558 const u8 *pdu = nic_data->mcdi_buf.addr; 1559 1560 memcpy(outbuf, pdu + offset, outlen); 1561 } 1562 1563 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 1564 { 1565 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1566 int rc; 1567 1568 rc = efx_ef10_get_warm_boot_count(efx); 1569 if (rc < 0) { 1570 /* The firmware is presumably in the process of 1571 * rebooting. However, we are supposed to report each 1572 * reboot just once, so we must only do that once we 1573 * can read and store the updated warm boot count. 1574 */ 1575 return 0; 1576 } 1577 1578 if (rc == nic_data->warm_boot_count) 1579 return 0; 1580 1581 nic_data->warm_boot_count = rc; 1582 1583 /* All our allocations have been reset */ 1584 efx_ef10_reset_mc_allocations(efx); 1585 1586 /* The datapath firmware might have been changed */ 1587 nic_data->must_check_datapath_caps = true; 1588 1589 /* MAC statistics have been cleared on the NIC; clear the local 1590 * statistic that we update with efx_update_diff_stat(). 1591 */ 1592 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 1593 1594 return -EIO; 1595 } 1596 1597 /* Handle an MSI interrupt 1598 * 1599 * Handle an MSI hardware interrupt. This routine schedules event 1600 * queue processing. No interrupt acknowledgement cycle is necessary. 1601 * Also, we never need to check that the interrupt is for us, since 1602 * MSI interrupts cannot be shared. 1603 */ 1604 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 1605 { 1606 struct efx_msi_context *context = dev_id; 1607 struct efx_nic *efx = context->efx; 1608 1609 netif_vdbg(efx, intr, efx->net_dev, 1610 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 1611 1612 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) { 1613 /* Note test interrupts */ 1614 if (context->index == efx->irq_level) 1615 efx->last_irq_cpu = raw_smp_processor_id(); 1616 1617 /* Schedule processing of the channel */ 1618 efx_schedule_channel_irq(efx->channel[context->index]); 1619 } 1620 1621 return IRQ_HANDLED; 1622 } 1623 1624 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 1625 { 1626 struct efx_nic *efx = dev_id; 1627 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); 1628 struct efx_channel *channel; 1629 efx_dword_t reg; 1630 u32 queues; 1631 1632 /* Read the ISR which also ACKs the interrupts */ 1633 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 1634 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 1635 1636 if (queues == 0) 1637 return IRQ_NONE; 1638 1639 if (likely(soft_enabled)) { 1640 /* Note test interrupts */ 1641 if (queues & (1U << efx->irq_level)) 1642 efx->last_irq_cpu = raw_smp_processor_id(); 1643 1644 efx_for_each_channel(channel, efx) { 1645 if (queues & 1) 1646 efx_schedule_channel_irq(channel); 1647 queues >>= 1; 1648 } 1649 } 1650 1651 netif_vdbg(efx, intr, efx->net_dev, 1652 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 1653 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 1654 1655 return IRQ_HANDLED; 1656 } 1657 1658 static void efx_ef10_irq_test_generate(struct efx_nic *efx) 1659 { 1660 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 1661 1662 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 1663 1664 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 1665 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 1666 inbuf, sizeof(inbuf), NULL, 0, NULL); 1667 } 1668 1669 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 1670 { 1671 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 1672 (tx_queue->ptr_mask + 1) * 1673 sizeof(efx_qword_t), 1674 GFP_KERNEL); 1675 } 1676 1677 /* This writes to the TX_DESC_WPTR and also pushes data */ 1678 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 1679 const efx_qword_t *txd) 1680 { 1681 unsigned int write_ptr; 1682 efx_oword_t reg; 1683 1684 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1685 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 1686 reg.qword[0] = *txd; 1687 efx_writeo_page(tx_queue->efx, ®, 1688 ER_DZ_TX_DESC_UPD, tx_queue->queue); 1689 } 1690 1691 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 1692 { 1693 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 1694 EFX_BUF_SIZE)); 1695 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 1696 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; 1697 struct efx_channel *channel = tx_queue->channel; 1698 struct efx_nic *efx = tx_queue->efx; 1699 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1700 size_t inlen; 1701 dma_addr_t dma_addr; 1702 efx_qword_t *txd; 1703 int rc; 1704 int i; 1705 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0); 1706 1707 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); 1708 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); 1709 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); 1710 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); 1711 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS, 1712 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, 1713 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload); 1714 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); 1715 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id); 1716 1717 dma_addr = tx_queue->txd.buf.dma_addr; 1718 1719 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", 1720 tx_queue->queue, entries, (u64)dma_addr); 1721 1722 for (i = 0; i < entries; ++i) { 1723 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); 1724 dma_addr += EFX_BUF_SIZE; 1725 } 1726 1727 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); 1728 1729 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen, 1730 NULL, 0, NULL); 1731 if (rc) 1732 goto fail; 1733 1734 /* A previous user of this TX queue might have set us up the 1735 * bomb by writing a descriptor to the TX push collector but 1736 * not the doorbell. (Each collector belongs to a port, not a 1737 * queue or function, so cannot easily be reset.) We must 1738 * attempt to push a no-op descriptor in its place. 1739 */ 1740 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 1741 tx_queue->insert_count = 1; 1742 txd = efx_tx_desc(tx_queue, 0); 1743 EFX_POPULATE_QWORD_4(*txd, 1744 ESF_DZ_TX_DESC_IS_OPT, true, 1745 ESF_DZ_TX_OPTION_TYPE, 1746 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 1747 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 1748 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload); 1749 tx_queue->write_count = 1; 1750 wmb(); 1751 efx_ef10_push_tx_desc(tx_queue, txd); 1752 1753 return; 1754 1755 fail: 1756 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 1757 tx_queue->queue); 1758 } 1759 1760 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue) 1761 { 1762 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); 1763 MCDI_DECLARE_BUF_ERR(outbuf); 1764 struct efx_nic *efx = tx_queue->efx; 1765 size_t outlen; 1766 int rc; 1767 1768 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, 1769 tx_queue->queue); 1770 1771 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), 1772 outbuf, sizeof(outbuf), &outlen); 1773 1774 if (rc && rc != -EALREADY) 1775 goto fail; 1776 1777 return; 1778 1779 fail: 1780 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, 1781 outbuf, outlen, rc); 1782 } 1783 1784 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue) 1785 { 1786 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); 1787 } 1788 1789 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 1790 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 1791 { 1792 unsigned int write_ptr; 1793 efx_dword_t reg; 1794 1795 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1796 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 1797 efx_writed_page(tx_queue->efx, ®, 1798 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 1799 } 1800 1801 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 1802 { 1803 unsigned int old_write_count = tx_queue->write_count; 1804 struct efx_tx_buffer *buffer; 1805 unsigned int write_ptr; 1806 efx_qword_t *txd; 1807 1808 BUG_ON(tx_queue->write_count == tx_queue->insert_count); 1809 1810 do { 1811 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1812 buffer = &tx_queue->buffer[write_ptr]; 1813 txd = efx_tx_desc(tx_queue, write_ptr); 1814 ++tx_queue->write_count; 1815 1816 /* Create TX descriptor ring entry */ 1817 if (buffer->flags & EFX_TX_BUF_OPTION) { 1818 *txd = buffer->option; 1819 } else { 1820 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 1821 EFX_POPULATE_QWORD_3( 1822 *txd, 1823 ESF_DZ_TX_KER_CONT, 1824 buffer->flags & EFX_TX_BUF_CONT, 1825 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 1826 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 1827 } 1828 } while (tx_queue->write_count != tx_queue->insert_count); 1829 1830 wmb(); /* Ensure descriptors are written before they are fetched */ 1831 1832 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 1833 txd = efx_tx_desc(tx_queue, 1834 old_write_count & tx_queue->ptr_mask); 1835 efx_ef10_push_tx_desc(tx_queue, txd); 1836 ++tx_queue->pushes; 1837 } else { 1838 efx_ef10_notify_tx_desc(tx_queue); 1839 } 1840 } 1841 1842 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context, 1843 bool exclusive, unsigned *context_size) 1844 { 1845 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN); 1846 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN); 1847 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1848 size_t outlen; 1849 int rc; 1850 u32 alloc_type = exclusive ? 1851 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE : 1852 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED; 1853 unsigned rss_spread = exclusive ? 1854 efx->rss_spread : 1855 min(rounddown_pow_of_two(efx->rss_spread), 1856 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE); 1857 1858 if (!exclusive && rss_spread == 1) { 1859 *context = EFX_EF10_RSS_CONTEXT_INVALID; 1860 if (context_size) 1861 *context_size = 1; 1862 return 0; 1863 } 1864 1865 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, 1866 nic_data->vport_id); 1867 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type); 1868 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread); 1869 1870 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf), 1871 outbuf, sizeof(outbuf), &outlen); 1872 if (rc != 0) 1873 return rc; 1874 1875 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) 1876 return -EIO; 1877 1878 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); 1879 1880 if (context_size) 1881 *context_size = rss_spread; 1882 1883 return 0; 1884 } 1885 1886 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context) 1887 { 1888 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN); 1889 int rc; 1890 1891 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, 1892 context); 1893 1894 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf), 1895 NULL, 0, NULL); 1896 WARN_ON(rc != 0); 1897 } 1898 1899 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context, 1900 const u32 *rx_indir_table) 1901 { 1902 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN); 1903 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN); 1904 int i, rc; 1905 1906 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, 1907 context); 1908 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != 1909 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN); 1910 1911 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i) 1912 MCDI_PTR(tablebuf, 1913 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] = 1914 (u8) rx_indir_table[i]; 1915 1916 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf, 1917 sizeof(tablebuf), NULL, 0, NULL); 1918 if (rc != 0) 1919 return rc; 1920 1921 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, 1922 context); 1923 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) != 1924 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); 1925 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i) 1926 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = 1927 efx->rx_hash_key[i]; 1928 1929 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf, 1930 sizeof(keybuf), NULL, 0, NULL); 1931 } 1932 1933 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx) 1934 { 1935 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1936 1937 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 1938 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context); 1939 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 1940 } 1941 1942 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx, 1943 unsigned *context_size) 1944 { 1945 u32 new_rx_rss_context; 1946 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1947 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 1948 false, context_size); 1949 1950 if (rc != 0) 1951 return rc; 1952 1953 nic_data->rx_rss_context = new_rx_rss_context; 1954 nic_data->rx_rss_context_exclusive = false; 1955 efx_set_default_rx_indir_table(efx); 1956 return 0; 1957 } 1958 1959 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx, 1960 const u32 *rx_indir_table) 1961 { 1962 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1963 int rc; 1964 u32 new_rx_rss_context; 1965 1966 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID || 1967 !nic_data->rx_rss_context_exclusive) { 1968 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 1969 true, NULL); 1970 if (rc == -EOPNOTSUPP) 1971 return rc; 1972 else if (rc != 0) 1973 goto fail1; 1974 } else { 1975 new_rx_rss_context = nic_data->rx_rss_context; 1976 } 1977 1978 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context, 1979 rx_indir_table); 1980 if (rc != 0) 1981 goto fail2; 1982 1983 if (nic_data->rx_rss_context != new_rx_rss_context) 1984 efx_ef10_rx_free_indir_table(efx); 1985 nic_data->rx_rss_context = new_rx_rss_context; 1986 nic_data->rx_rss_context_exclusive = true; 1987 if (rx_indir_table != efx->rx_indir_table) 1988 memcpy(efx->rx_indir_table, rx_indir_table, 1989 sizeof(efx->rx_indir_table)); 1990 return 0; 1991 1992 fail2: 1993 if (new_rx_rss_context != nic_data->rx_rss_context) 1994 efx_ef10_free_rss_context(efx, new_rx_rss_context); 1995 fail1: 1996 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 1997 return rc; 1998 } 1999 2000 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user, 2001 const u32 *rx_indir_table) 2002 { 2003 int rc; 2004 2005 if (efx->rss_spread == 1) 2006 return 0; 2007 2008 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table); 2009 2010 if (rc == -ENOBUFS && !user) { 2011 unsigned context_size; 2012 bool mismatch = false; 2013 size_t i; 2014 2015 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch; 2016 i++) 2017 mismatch = rx_indir_table[i] != 2018 ethtool_rxfh_indir_default(i, efx->rss_spread); 2019 2020 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size); 2021 if (rc == 0) { 2022 if (context_size != efx->rss_spread) 2023 netif_warn(efx, probe, efx->net_dev, 2024 "Could not allocate an exclusive RSS" 2025 " context; allocated a shared one of" 2026 " different size." 2027 " Wanted %u, got %u.\n", 2028 efx->rss_spread, context_size); 2029 else if (mismatch) 2030 netif_warn(efx, probe, efx->net_dev, 2031 "Could not allocate an exclusive RSS" 2032 " context; allocated a shared one but" 2033 " could not apply custom" 2034 " indirection.\n"); 2035 else 2036 netif_info(efx, probe, efx->net_dev, 2037 "Could not allocate an exclusive RSS" 2038 " context; allocated a shared one.\n"); 2039 } 2040 } 2041 return rc; 2042 } 2043 2044 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user, 2045 const u32 *rx_indir_table 2046 __attribute__ ((unused))) 2047 { 2048 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2049 2050 if (user) 2051 return -EOPNOTSUPP; 2052 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 2053 return 0; 2054 return efx_ef10_rx_push_shared_rss_config(efx, NULL); 2055 } 2056 2057 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue) 2058 { 2059 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, 2060 (rx_queue->ptr_mask + 1) * 2061 sizeof(efx_qword_t), 2062 GFP_KERNEL); 2063 } 2064 2065 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue) 2066 { 2067 MCDI_DECLARE_BUF(inbuf, 2068 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 2069 EFX_BUF_SIZE)); 2070 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2071 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; 2072 struct efx_nic *efx = rx_queue->efx; 2073 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2074 size_t inlen; 2075 dma_addr_t dma_addr; 2076 int rc; 2077 int i; 2078 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0); 2079 2080 rx_queue->scatter_n = 0; 2081 rx_queue->scatter_len = 0; 2082 2083 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); 2084 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); 2085 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); 2086 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, 2087 efx_rx_queue_index(rx_queue)); 2088 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, 2089 INIT_RXQ_IN_FLAG_PREFIX, 1, 2090 INIT_RXQ_IN_FLAG_TIMESTAMP, 1); 2091 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); 2092 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id); 2093 2094 dma_addr = rx_queue->rxd.buf.dma_addr; 2095 2096 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", 2097 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); 2098 2099 for (i = 0; i < entries; ++i) { 2100 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); 2101 dma_addr += EFX_BUF_SIZE; 2102 } 2103 2104 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); 2105 2106 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, 2107 NULL, 0, NULL); 2108 if (rc) 2109 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", 2110 efx_rx_queue_index(rx_queue)); 2111 } 2112 2113 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue) 2114 { 2115 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); 2116 MCDI_DECLARE_BUF_ERR(outbuf); 2117 struct efx_nic *efx = rx_queue->efx; 2118 size_t outlen; 2119 int rc; 2120 2121 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, 2122 efx_rx_queue_index(rx_queue)); 2123 2124 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), 2125 outbuf, sizeof(outbuf), &outlen); 2126 2127 if (rc && rc != -EALREADY) 2128 goto fail; 2129 2130 return; 2131 2132 fail: 2133 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, 2134 outbuf, outlen, rc); 2135 } 2136 2137 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue) 2138 { 2139 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); 2140 } 2141 2142 /* This creates an entry in the RX descriptor queue */ 2143 static inline void 2144 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2145 { 2146 struct efx_rx_buffer *rx_buf; 2147 efx_qword_t *rxd; 2148 2149 rxd = efx_rx_desc(rx_queue, index); 2150 rx_buf = efx_rx_buffer(rx_queue, index); 2151 EFX_POPULATE_QWORD_2(*rxd, 2152 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2153 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2154 } 2155 2156 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2157 { 2158 struct efx_nic *efx = rx_queue->efx; 2159 unsigned int write_count; 2160 efx_dword_t reg; 2161 2162 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2163 write_count = rx_queue->added_count & ~7; 2164 if (rx_queue->notified_count == write_count) 2165 return; 2166 2167 do 2168 efx_ef10_build_rx_desc( 2169 rx_queue, 2170 rx_queue->notified_count & rx_queue->ptr_mask); 2171 while (++rx_queue->notified_count != write_count); 2172 2173 wmb(); 2174 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2175 write_count & rx_queue->ptr_mask); 2176 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2177 efx_rx_queue_index(rx_queue)); 2178 } 2179 2180 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2181 2182 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2183 { 2184 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2185 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2186 efx_qword_t event; 2187 2188 EFX_POPULATE_QWORD_2(event, 2189 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2190 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2191 2192 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2193 2194 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2195 * already swapped the data to little-endian order. 2196 */ 2197 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2198 sizeof(efx_qword_t)); 2199 2200 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2201 inbuf, sizeof(inbuf), 0, 2202 efx_ef10_rx_defer_refill_complete, 0); 2203 } 2204 2205 static void 2206 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2207 int rc, efx_dword_t *outbuf, 2208 size_t outlen_actual) 2209 { 2210 /* nothing to do */ 2211 } 2212 2213 static int efx_ef10_ev_probe(struct efx_channel *channel) 2214 { 2215 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 2216 (channel->eventq_mask + 1) * 2217 sizeof(efx_qword_t), 2218 GFP_KERNEL); 2219 } 2220 2221 static void efx_ef10_ev_fini(struct efx_channel *channel) 2222 { 2223 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); 2224 MCDI_DECLARE_BUF_ERR(outbuf); 2225 struct efx_nic *efx = channel->efx; 2226 size_t outlen; 2227 int rc; 2228 2229 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); 2230 2231 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), 2232 outbuf, sizeof(outbuf), &outlen); 2233 2234 if (rc && rc != -EALREADY) 2235 goto fail; 2236 2237 return; 2238 2239 fail: 2240 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, 2241 outbuf, outlen, rc); 2242 } 2243 2244 static int efx_ef10_ev_init(struct efx_channel *channel) 2245 { 2246 MCDI_DECLARE_BUF(inbuf, 2247 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / 2248 EFX_BUF_SIZE)); 2249 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN); 2250 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; 2251 struct efx_nic *efx = channel->efx; 2252 struct efx_ef10_nic_data *nic_data; 2253 bool supports_rx_merge; 2254 size_t inlen, outlen; 2255 unsigned int enabled, implemented; 2256 dma_addr_t dma_addr; 2257 int rc; 2258 int i; 2259 2260 nic_data = efx->nic_data; 2261 supports_rx_merge = 2262 !!(nic_data->datapath_caps & 2263 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2264 2265 /* Fill event queue with all ones (i.e. empty events) */ 2266 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); 2267 2268 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); 2269 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); 2270 /* INIT_EVQ expects index in vector table, not absolute */ 2271 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); 2272 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, 2273 INIT_EVQ_IN_FLAG_INTERRUPTING, 1, 2274 INIT_EVQ_IN_FLAG_RX_MERGE, 1, 2275 INIT_EVQ_IN_FLAG_TX_MERGE, 1, 2276 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge); 2277 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, 2278 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); 2279 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); 2280 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); 2281 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, 2282 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); 2283 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); 2284 2285 dma_addr = channel->eventq.buf.dma_addr; 2286 for (i = 0; i < entries; ++i) { 2287 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); 2288 dma_addr += EFX_BUF_SIZE; 2289 } 2290 2291 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); 2292 2293 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, 2294 outbuf, sizeof(outbuf), &outlen); 2295 /* IRQ return is ignored */ 2296 if (channel->channel || rc) 2297 return rc; 2298 2299 /* Successfully created event queue on channel 0 */ 2300 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2301 if (rc == -ENOSYS) { 2302 /* GET_WORKAROUNDS was implemented before the bug26807 2303 * workaround, thus the latter must be unavailable in this fw 2304 */ 2305 nic_data->workaround_26807 = false; 2306 rc = 0; 2307 } else if (rc) { 2308 goto fail; 2309 } else { 2310 nic_data->workaround_26807 = 2311 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2312 2313 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 && 2314 !nic_data->workaround_26807) { 2315 unsigned int flags; 2316 2317 rc = efx_mcdi_set_workaround(efx, 2318 MC_CMD_WORKAROUND_BUG26807, 2319 true, &flags); 2320 2321 if (!rc) { 2322 if (flags & 2323 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2324 netif_info(efx, drv, efx->net_dev, 2325 "other functions on NIC have been reset\n"); 2326 /* MC's boot count has incremented */ 2327 ++nic_data->warm_boot_count; 2328 } 2329 nic_data->workaround_26807 = true; 2330 } else if (rc == -EPERM) { 2331 rc = 0; 2332 } 2333 } 2334 } 2335 2336 if (!rc) 2337 return 0; 2338 2339 fail: 2340 efx_ef10_ev_fini(channel); 2341 return rc; 2342 } 2343 2344 static void efx_ef10_ev_remove(struct efx_channel *channel) 2345 { 2346 efx_nic_free_buffer(channel->efx, &channel->eventq.buf); 2347 } 2348 2349 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2350 unsigned int rx_queue_label) 2351 { 2352 struct efx_nic *efx = rx_queue->efx; 2353 2354 netif_info(efx, hw, efx->net_dev, 2355 "rx event arrived on queue %d labeled as queue %u\n", 2356 efx_rx_queue_index(rx_queue), rx_queue_label); 2357 2358 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2359 } 2360 2361 static void 2362 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2363 unsigned int actual, unsigned int expected) 2364 { 2365 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2366 struct efx_nic *efx = rx_queue->efx; 2367 2368 netif_info(efx, hw, efx->net_dev, 2369 "dropped %d events (index=%d expected=%d)\n", 2370 dropped, actual, expected); 2371 2372 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2373 } 2374 2375 /* partially received RX was aborted. clean up. */ 2376 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2377 { 2378 unsigned int rx_desc_ptr; 2379 2380 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2381 "scattered RX aborted (dropping %u buffers)\n", 2382 rx_queue->scatter_n); 2383 2384 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2385 2386 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2387 0, EFX_RX_PKT_DISCARD); 2388 2389 rx_queue->removed_count += rx_queue->scatter_n; 2390 rx_queue->scatter_n = 0; 2391 rx_queue->scatter_len = 0; 2392 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2393 } 2394 2395 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2396 const efx_qword_t *event) 2397 { 2398 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class; 2399 unsigned int n_descs, n_packets, i; 2400 struct efx_nic *efx = channel->efx; 2401 struct efx_rx_queue *rx_queue; 2402 bool rx_cont; 2403 u16 flags = 0; 2404 2405 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 2406 return 0; 2407 2408 /* Basic packet information */ 2409 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2410 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2411 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2412 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); 2413 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2414 2415 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2416 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2417 EFX_QWORD_FMT "\n", 2418 EFX_QWORD_VAL(*event)); 2419 2420 rx_queue = efx_channel_get_rx_queue(channel); 2421 2422 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2423 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2424 2425 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2426 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2427 2428 if (n_descs != rx_queue->scatter_n + 1) { 2429 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2430 2431 /* detect rx abort */ 2432 if (unlikely(n_descs == rx_queue->scatter_n)) { 2433 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2434 netdev_WARN(efx->net_dev, 2435 "invalid RX abort: scatter_n=%u event=" 2436 EFX_QWORD_FMT "\n", 2437 rx_queue->scatter_n, 2438 EFX_QWORD_VAL(*event)); 2439 efx_ef10_handle_rx_abort(rx_queue); 2440 return 0; 2441 } 2442 2443 /* Check that RX completion merging is valid, i.e. 2444 * the current firmware supports it and this is a 2445 * non-scattered packet. 2446 */ 2447 if (!(nic_data->datapath_caps & 2448 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2449 rx_queue->scatter_n != 0 || rx_cont) { 2450 efx_ef10_handle_rx_bad_lbits( 2451 rx_queue, next_ptr_lbits, 2452 (rx_queue->removed_count + 2453 rx_queue->scatter_n + 1) & 2454 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2455 return 0; 2456 } 2457 2458 /* Merged completion for multiple non-scattered packets */ 2459 rx_queue->scatter_n = 1; 2460 rx_queue->scatter_len = 0; 2461 n_packets = n_descs; 2462 ++channel->n_rx_merge_events; 2463 channel->n_rx_merge_packets += n_packets; 2464 flags |= EFX_RX_PKT_PREFIX_LEN; 2465 } else { 2466 ++rx_queue->scatter_n; 2467 rx_queue->scatter_len += rx_bytes; 2468 if (rx_cont) 2469 return 0; 2470 n_packets = 1; 2471 } 2472 2473 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR))) 2474 flags |= EFX_RX_PKT_DISCARD; 2475 2476 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) { 2477 channel->n_rx_ip_hdr_chksum_err += n_packets; 2478 } else if (unlikely(EFX_QWORD_FIELD(*event, 2479 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) { 2480 channel->n_rx_tcp_udp_chksum_err += n_packets; 2481 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP || 2482 rx_l4_class == ESE_DZ_L4_CLASS_UDP) { 2483 flags |= EFX_RX_PKT_CSUMMED; 2484 } 2485 2486 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) 2487 flags |= EFX_RX_PKT_TCP; 2488 2489 channel->irq_mod_score += 2 * n_packets; 2490 2491 /* Handle received packet(s) */ 2492 for (i = 0; i < n_packets; i++) { 2493 efx_rx_packet(rx_queue, 2494 rx_queue->removed_count & rx_queue->ptr_mask, 2495 rx_queue->scatter_n, rx_queue->scatter_len, 2496 flags); 2497 rx_queue->removed_count += rx_queue->scatter_n; 2498 } 2499 2500 rx_queue->scatter_n = 0; 2501 rx_queue->scatter_len = 0; 2502 2503 return n_packets; 2504 } 2505 2506 static int 2507 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2508 { 2509 struct efx_nic *efx = channel->efx; 2510 struct efx_tx_queue *tx_queue; 2511 unsigned int tx_ev_desc_ptr; 2512 unsigned int tx_ev_q_label; 2513 int tx_descs = 0; 2514 2515 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 2516 return 0; 2517 2518 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2519 return 0; 2520 2521 /* Transmit completion */ 2522 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2523 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2524 tx_queue = efx_channel_get_tx_queue(channel, 2525 tx_ev_q_label % EFX_TXQ_TYPES); 2526 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) & 2527 tx_queue->ptr_mask); 2528 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2529 2530 return tx_descs; 2531 } 2532 2533 static void 2534 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 2535 { 2536 struct efx_nic *efx = channel->efx; 2537 int subcode; 2538 2539 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 2540 2541 switch (subcode) { 2542 case ESE_DZ_DRV_TIMER_EV: 2543 case ESE_DZ_DRV_WAKE_UP_EV: 2544 break; 2545 case ESE_DZ_DRV_START_UP_EV: 2546 /* event queue init complete. ok. */ 2547 break; 2548 default: 2549 netif_err(efx, hw, efx->net_dev, 2550 "channel %d unknown driver event type %d" 2551 " (data " EFX_QWORD_FMT ")\n", 2552 channel->channel, subcode, 2553 EFX_QWORD_VAL(*event)); 2554 2555 } 2556 } 2557 2558 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 2559 efx_qword_t *event) 2560 { 2561 struct efx_nic *efx = channel->efx; 2562 u32 subcode; 2563 2564 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 2565 2566 switch (subcode) { 2567 case EFX_EF10_TEST: 2568 channel->event_test_cpu = raw_smp_processor_id(); 2569 break; 2570 case EFX_EF10_REFILL: 2571 /* The queue must be empty, so we won't receive any rx 2572 * events, so efx_process_channel() won't refill the 2573 * queue. Refill it here 2574 */ 2575 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 2576 break; 2577 default: 2578 netif_err(efx, hw, efx->net_dev, 2579 "channel %d unknown driver event type %u" 2580 " (data " EFX_QWORD_FMT ")\n", 2581 channel->channel, (unsigned) subcode, 2582 EFX_QWORD_VAL(*event)); 2583 } 2584 } 2585 2586 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 2587 { 2588 struct efx_nic *efx = channel->efx; 2589 efx_qword_t event, *p_event; 2590 unsigned int read_ptr; 2591 int ev_code; 2592 int tx_descs = 0; 2593 int spent = 0; 2594 2595 if (quota <= 0) 2596 return spent; 2597 2598 read_ptr = channel->eventq_read_ptr; 2599 2600 for (;;) { 2601 p_event = efx_event(channel, read_ptr); 2602 event = *p_event; 2603 2604 if (!efx_event_present(&event)) 2605 break; 2606 2607 EFX_SET_QWORD(*p_event); 2608 2609 ++read_ptr; 2610 2611 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 2612 2613 netif_vdbg(efx, drv, efx->net_dev, 2614 "processing event on %d " EFX_QWORD_FMT "\n", 2615 channel->channel, EFX_QWORD_VAL(event)); 2616 2617 switch (ev_code) { 2618 case ESE_DZ_EV_CODE_MCDI_EV: 2619 efx_mcdi_process_event(channel, &event); 2620 break; 2621 case ESE_DZ_EV_CODE_RX_EV: 2622 spent += efx_ef10_handle_rx_event(channel, &event); 2623 if (spent >= quota) { 2624 /* XXX can we split a merged event to 2625 * avoid going over-quota? 2626 */ 2627 spent = quota; 2628 goto out; 2629 } 2630 break; 2631 case ESE_DZ_EV_CODE_TX_EV: 2632 tx_descs += efx_ef10_handle_tx_event(channel, &event); 2633 if (tx_descs > efx->txq_entries) { 2634 spent = quota; 2635 goto out; 2636 } else if (++spent == quota) { 2637 goto out; 2638 } 2639 break; 2640 case ESE_DZ_EV_CODE_DRIVER_EV: 2641 efx_ef10_handle_driver_event(channel, &event); 2642 if (++spent == quota) 2643 goto out; 2644 break; 2645 case EFX_EF10_DRVGEN_EV: 2646 efx_ef10_handle_driver_generated_event(channel, &event); 2647 break; 2648 default: 2649 netif_err(efx, hw, efx->net_dev, 2650 "channel %d unknown event type %d" 2651 " (data " EFX_QWORD_FMT ")\n", 2652 channel->channel, ev_code, 2653 EFX_QWORD_VAL(event)); 2654 } 2655 } 2656 2657 out: 2658 channel->eventq_read_ptr = read_ptr; 2659 return spent; 2660 } 2661 2662 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 2663 { 2664 struct efx_nic *efx = channel->efx; 2665 efx_dword_t rptr; 2666 2667 if (EFX_EF10_WORKAROUND_35388(efx)) { 2668 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 2669 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 2670 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 2671 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 2672 2673 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2674 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 2675 ERF_DD_EVQ_IND_RPTR, 2676 (channel->eventq_read_ptr & 2677 channel->eventq_mask) >> 2678 ERF_DD_EVQ_IND_RPTR_WIDTH); 2679 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2680 channel->channel); 2681 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2682 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 2683 ERF_DD_EVQ_IND_RPTR, 2684 channel->eventq_read_ptr & 2685 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 2686 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2687 channel->channel); 2688 } else { 2689 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 2690 channel->eventq_read_ptr & 2691 channel->eventq_mask); 2692 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 2693 } 2694 } 2695 2696 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 2697 { 2698 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2699 struct efx_nic *efx = channel->efx; 2700 efx_qword_t event; 2701 int rc; 2702 2703 EFX_POPULATE_QWORD_2(event, 2704 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2705 ESF_DZ_EV_DATA, EFX_EF10_TEST); 2706 2707 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2708 2709 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2710 * already swapped the data to little-endian order. 2711 */ 2712 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2713 sizeof(efx_qword_t)); 2714 2715 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 2716 NULL, 0, NULL); 2717 if (rc != 0) 2718 goto fail; 2719 2720 return; 2721 2722 fail: 2723 WARN_ON(true); 2724 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 2725 } 2726 2727 void efx_ef10_handle_drain_event(struct efx_nic *efx) 2728 { 2729 if (atomic_dec_and_test(&efx->active_queues)) 2730 wake_up(&efx->flush_wq); 2731 2732 WARN_ON(atomic_read(&efx->active_queues) < 0); 2733 } 2734 2735 static int efx_ef10_fini_dmaq(struct efx_nic *efx) 2736 { 2737 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2738 struct efx_channel *channel; 2739 struct efx_tx_queue *tx_queue; 2740 struct efx_rx_queue *rx_queue; 2741 int pending; 2742 2743 /* If the MC has just rebooted, the TX/RX queues will have already been 2744 * torn down, but efx->active_queues needs to be set to zero. 2745 */ 2746 if (nic_data->must_realloc_vis) { 2747 atomic_set(&efx->active_queues, 0); 2748 return 0; 2749 } 2750 2751 /* Do not attempt to write to the NIC during EEH recovery */ 2752 if (efx->state != STATE_RECOVERY) { 2753 efx_for_each_channel(channel, efx) { 2754 efx_for_each_channel_rx_queue(rx_queue, channel) 2755 efx_ef10_rx_fini(rx_queue); 2756 efx_for_each_channel_tx_queue(tx_queue, channel) 2757 efx_ef10_tx_fini(tx_queue); 2758 } 2759 2760 wait_event_timeout(efx->flush_wq, 2761 atomic_read(&efx->active_queues) == 0, 2762 msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); 2763 pending = atomic_read(&efx->active_queues); 2764 if (pending) { 2765 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", 2766 pending); 2767 return -ETIMEDOUT; 2768 } 2769 } 2770 2771 return 0; 2772 } 2773 2774 static void efx_ef10_prepare_flr(struct efx_nic *efx) 2775 { 2776 atomic_set(&efx->active_queues, 0); 2777 } 2778 2779 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left, 2780 const struct efx_filter_spec *right) 2781 { 2782 if ((left->match_flags ^ right->match_flags) | 2783 ((left->flags ^ right->flags) & 2784 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX))) 2785 return false; 2786 2787 return memcmp(&left->outer_vid, &right->outer_vid, 2788 sizeof(struct efx_filter_spec) - 2789 offsetof(struct efx_filter_spec, outer_vid)) == 0; 2790 } 2791 2792 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec) 2793 { 2794 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3); 2795 return jhash2((const u32 *)&spec->outer_vid, 2796 (sizeof(struct efx_filter_spec) - 2797 offsetof(struct efx_filter_spec, outer_vid)) / 4, 2798 0); 2799 /* XXX should we randomise the initval? */ 2800 } 2801 2802 /* Decide whether a filter should be exclusive or else should allow 2803 * delivery to additional recipients. Currently we decide that 2804 * filters for specific local unicast MAC and IP addresses are 2805 * exclusive. 2806 */ 2807 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec) 2808 { 2809 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC && 2810 !is_multicast_ether_addr(spec->loc_mac)) 2811 return true; 2812 2813 if ((spec->match_flags & 2814 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == 2815 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { 2816 if (spec->ether_type == htons(ETH_P_IP) && 2817 !ipv4_is_multicast(spec->loc_host[0])) 2818 return true; 2819 if (spec->ether_type == htons(ETH_P_IPV6) && 2820 ((const u8 *)spec->loc_host)[0] != 0xff) 2821 return true; 2822 } 2823 2824 return false; 2825 } 2826 2827 static struct efx_filter_spec * 2828 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table, 2829 unsigned int filter_idx) 2830 { 2831 return (struct efx_filter_spec *)(table->entry[filter_idx].spec & 2832 ~EFX_EF10_FILTER_FLAGS); 2833 } 2834 2835 static unsigned int 2836 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table, 2837 unsigned int filter_idx) 2838 { 2839 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS; 2840 } 2841 2842 static void 2843 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table, 2844 unsigned int filter_idx, 2845 const struct efx_filter_spec *spec, 2846 unsigned int flags) 2847 { 2848 table->entry[filter_idx].spec = (unsigned long)spec | flags; 2849 } 2850 2851 static void efx_ef10_filter_push_prep(struct efx_nic *efx, 2852 const struct efx_filter_spec *spec, 2853 efx_dword_t *inbuf, u64 handle, 2854 bool replacing) 2855 { 2856 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2857 2858 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN); 2859 2860 if (replacing) { 2861 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2862 MC_CMD_FILTER_OP_IN_OP_REPLACE); 2863 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle); 2864 } else { 2865 u32 match_fields = 0; 2866 2867 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2868 efx_ef10_filter_is_exclusive(spec) ? 2869 MC_CMD_FILTER_OP_IN_OP_INSERT : 2870 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE); 2871 2872 /* Convert match flags and values. Unlike almost 2873 * everything else in MCDI, these fields are in 2874 * network byte order. 2875 */ 2876 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) 2877 match_fields |= 2878 is_multicast_ether_addr(spec->loc_mac) ? 2879 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN : 2880 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; 2881 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \ 2882 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \ 2883 match_fields |= \ 2884 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 2885 mcdi_field ## _LBN; \ 2886 BUILD_BUG_ON( \ 2887 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \ 2888 sizeof(spec->gen_field)); \ 2889 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \ 2890 &spec->gen_field, sizeof(spec->gen_field)); \ 2891 } 2892 COPY_FIELD(REM_HOST, rem_host, SRC_IP); 2893 COPY_FIELD(LOC_HOST, loc_host, DST_IP); 2894 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC); 2895 COPY_FIELD(REM_PORT, rem_port, SRC_PORT); 2896 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC); 2897 COPY_FIELD(LOC_PORT, loc_port, DST_PORT); 2898 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE); 2899 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN); 2900 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN); 2901 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO); 2902 #undef COPY_FIELD 2903 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS, 2904 match_fields); 2905 } 2906 2907 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id); 2908 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST, 2909 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2910 MC_CMD_FILTER_OP_IN_RX_DEST_DROP : 2911 MC_CMD_FILTER_OP_IN_RX_DEST_HOST); 2912 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0); 2913 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST, 2914 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); 2915 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, 2916 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2917 0 : spec->dmaq_id); 2918 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE, 2919 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ? 2920 MC_CMD_FILTER_OP_IN_RX_MODE_RSS : 2921 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); 2922 if (spec->flags & EFX_FILTER_FLAG_RX_RSS) 2923 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, 2924 spec->rss_context != 2925 EFX_FILTER_RSS_CONTEXT_DEFAULT ? 2926 spec->rss_context : nic_data->rx_rss_context); 2927 } 2928 2929 static int efx_ef10_filter_push(struct efx_nic *efx, 2930 const struct efx_filter_spec *spec, 2931 u64 *handle, bool replacing) 2932 { 2933 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 2934 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN); 2935 int rc; 2936 2937 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing); 2938 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 2939 outbuf, sizeof(outbuf), NULL); 2940 if (rc == 0) 2941 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 2942 if (rc == -ENOSPC) 2943 rc = -EBUSY; /* to match efx_farch_filter_insert() */ 2944 return rc; 2945 } 2946 2947 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table, 2948 enum efx_filter_match_flags match_flags) 2949 { 2950 unsigned int match_pri; 2951 2952 for (match_pri = 0; 2953 match_pri < table->rx_match_count; 2954 match_pri++) 2955 if (table->rx_match_flags[match_pri] == match_flags) 2956 return match_pri; 2957 2958 return -EPROTONOSUPPORT; 2959 } 2960 2961 static s32 efx_ef10_filter_insert(struct efx_nic *efx, 2962 struct efx_filter_spec *spec, 2963 bool replace_equal) 2964 { 2965 struct efx_ef10_filter_table *table = efx->filter_state; 2966 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 2967 struct efx_filter_spec *saved_spec; 2968 unsigned int match_pri, hash; 2969 unsigned int priv_flags; 2970 bool replacing = false; 2971 int ins_index = -1; 2972 DEFINE_WAIT(wait); 2973 bool is_mc_recip; 2974 s32 rc; 2975 2976 /* For now, only support RX filters */ 2977 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) != 2978 EFX_FILTER_FLAG_RX) 2979 return -EINVAL; 2980 2981 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags); 2982 if (rc < 0) 2983 return rc; 2984 match_pri = rc; 2985 2986 hash = efx_ef10_filter_hash(spec); 2987 is_mc_recip = efx_filter_is_mc_recipient(spec); 2988 if (is_mc_recip) 2989 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 2990 2991 /* Find any existing filters with the same match tuple or 2992 * else a free slot to insert at. If any of them are busy, 2993 * we have to wait and retry. 2994 */ 2995 for (;;) { 2996 unsigned int depth = 1; 2997 unsigned int i; 2998 2999 spin_lock_bh(&efx->filter_lock); 3000 3001 for (;;) { 3002 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3003 saved_spec = efx_ef10_filter_entry_spec(table, i); 3004 3005 if (!saved_spec) { 3006 if (ins_index < 0) 3007 ins_index = i; 3008 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 3009 if (table->entry[i].spec & 3010 EFX_EF10_FILTER_FLAG_BUSY) 3011 break; 3012 if (spec->priority < saved_spec->priority && 3013 spec->priority != EFX_FILTER_PRI_AUTO) { 3014 rc = -EPERM; 3015 goto out_unlock; 3016 } 3017 if (!is_mc_recip) { 3018 /* This is the only one */ 3019 if (spec->priority == 3020 saved_spec->priority && 3021 !replace_equal) { 3022 rc = -EEXIST; 3023 goto out_unlock; 3024 } 3025 ins_index = i; 3026 goto found; 3027 } else if (spec->priority > 3028 saved_spec->priority || 3029 (spec->priority == 3030 saved_spec->priority && 3031 replace_equal)) { 3032 if (ins_index < 0) 3033 ins_index = i; 3034 else 3035 __set_bit(depth, mc_rem_map); 3036 } 3037 } 3038 3039 /* Once we reach the maximum search depth, use 3040 * the first suitable slot or return -EBUSY if 3041 * there was none 3042 */ 3043 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 3044 if (ins_index < 0) { 3045 rc = -EBUSY; 3046 goto out_unlock; 3047 } 3048 goto found; 3049 } 3050 3051 ++depth; 3052 } 3053 3054 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 3055 spin_unlock_bh(&efx->filter_lock); 3056 schedule(); 3057 } 3058 3059 found: 3060 /* Create a software table entry if necessary, and mark it 3061 * busy. We might yet fail to insert, but any attempt to 3062 * insert a conflicting filter while we're waiting for the 3063 * firmware must find the busy entry. 3064 */ 3065 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 3066 if (saved_spec) { 3067 if (spec->priority == EFX_FILTER_PRI_AUTO && 3068 saved_spec->priority >= EFX_FILTER_PRI_AUTO) { 3069 /* Just make sure it won't be removed */ 3070 if (saved_spec->priority > EFX_FILTER_PRI_AUTO) 3071 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; 3072 table->entry[ins_index].spec &= 3073 ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3074 rc = ins_index; 3075 goto out_unlock; 3076 } 3077 replacing = true; 3078 priv_flags = efx_ef10_filter_entry_flags(table, ins_index); 3079 } else { 3080 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 3081 if (!saved_spec) { 3082 rc = -ENOMEM; 3083 goto out_unlock; 3084 } 3085 *saved_spec = *spec; 3086 priv_flags = 0; 3087 } 3088 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 3089 priv_flags | EFX_EF10_FILTER_FLAG_BUSY); 3090 3091 /* Mark lower-priority multicast recipients busy prior to removal */ 3092 if (is_mc_recip) { 3093 unsigned int depth, i; 3094 3095 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3096 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3097 if (test_bit(depth, mc_rem_map)) 3098 table->entry[i].spec |= 3099 EFX_EF10_FILTER_FLAG_BUSY; 3100 } 3101 } 3102 3103 spin_unlock_bh(&efx->filter_lock); 3104 3105 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle, 3106 replacing); 3107 3108 /* Finalise the software table entry */ 3109 spin_lock_bh(&efx->filter_lock); 3110 if (rc == 0) { 3111 if (replacing) { 3112 /* Update the fields that may differ */ 3113 if (saved_spec->priority == EFX_FILTER_PRI_AUTO) 3114 saved_spec->flags |= 3115 EFX_FILTER_FLAG_RX_OVER_AUTO; 3116 saved_spec->priority = spec->priority; 3117 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO; 3118 saved_spec->flags |= spec->flags; 3119 saved_spec->rss_context = spec->rss_context; 3120 saved_spec->dmaq_id = spec->dmaq_id; 3121 } 3122 } else if (!replacing) { 3123 kfree(saved_spec); 3124 saved_spec = NULL; 3125 } 3126 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags); 3127 3128 /* Remove and finalise entries for lower-priority multicast 3129 * recipients 3130 */ 3131 if (is_mc_recip) { 3132 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3133 unsigned int depth, i; 3134 3135 memset(inbuf, 0, sizeof(inbuf)); 3136 3137 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3138 if (!test_bit(depth, mc_rem_map)) 3139 continue; 3140 3141 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3142 saved_spec = efx_ef10_filter_entry_spec(table, i); 3143 priv_flags = efx_ef10_filter_entry_flags(table, i); 3144 3145 if (rc == 0) { 3146 spin_unlock_bh(&efx->filter_lock); 3147 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3148 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3149 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3150 table->entry[i].handle); 3151 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3152 inbuf, sizeof(inbuf), 3153 NULL, 0, NULL); 3154 spin_lock_bh(&efx->filter_lock); 3155 } 3156 3157 if (rc == 0) { 3158 kfree(saved_spec); 3159 saved_spec = NULL; 3160 priv_flags = 0; 3161 } else { 3162 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY; 3163 } 3164 efx_ef10_filter_set_entry(table, i, saved_spec, 3165 priv_flags); 3166 } 3167 } 3168 3169 /* If successful, return the inserted filter ID */ 3170 if (rc == 0) 3171 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index; 3172 3173 wake_up_all(&table->waitq); 3174 out_unlock: 3175 spin_unlock_bh(&efx->filter_lock); 3176 finish_wait(&table->waitq, &wait); 3177 return rc; 3178 } 3179 3180 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx) 3181 { 3182 /* no need to do anything here on EF10 */ 3183 } 3184 3185 /* Remove a filter. 3186 * If !by_index, remove by ID 3187 * If by_index, remove by index 3188 * Filter ID may come from userland and must be range-checked. 3189 */ 3190 static int efx_ef10_filter_remove_internal(struct efx_nic *efx, 3191 unsigned int priority_mask, 3192 u32 filter_id, bool by_index) 3193 { 3194 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 3195 struct efx_ef10_filter_table *table = efx->filter_state; 3196 MCDI_DECLARE_BUF(inbuf, 3197 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 3198 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 3199 struct efx_filter_spec *spec; 3200 DEFINE_WAIT(wait); 3201 int rc; 3202 3203 /* Find the software table entry and mark it busy. Don't 3204 * remove it yet; any attempt to update while we're waiting 3205 * for the firmware must find the busy entry. 3206 */ 3207 for (;;) { 3208 spin_lock_bh(&efx->filter_lock); 3209 if (!(table->entry[filter_idx].spec & 3210 EFX_EF10_FILTER_FLAG_BUSY)) 3211 break; 3212 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 3213 spin_unlock_bh(&efx->filter_lock); 3214 schedule(); 3215 } 3216 3217 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3218 if (!spec || 3219 (!by_index && 3220 efx_ef10_filter_rx_match_pri(table, spec->match_flags) != 3221 filter_id / HUNT_FILTER_TBL_ROWS)) { 3222 rc = -ENOENT; 3223 goto out_unlock; 3224 } 3225 3226 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO && 3227 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) { 3228 /* Just remove flags */ 3229 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO; 3230 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3231 rc = 0; 3232 goto out_unlock; 3233 } 3234 3235 if (!(priority_mask & (1U << spec->priority))) { 3236 rc = -ENOENT; 3237 goto out_unlock; 3238 } 3239 3240 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3241 spin_unlock_bh(&efx->filter_lock); 3242 3243 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { 3244 /* Reset to an automatic filter */ 3245 3246 struct efx_filter_spec new_spec = *spec; 3247 3248 new_spec.priority = EFX_FILTER_PRI_AUTO; 3249 new_spec.flags = (EFX_FILTER_FLAG_RX | 3250 EFX_FILTER_FLAG_RX_RSS); 3251 new_spec.dmaq_id = 0; 3252 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT; 3253 rc = efx_ef10_filter_push(efx, &new_spec, 3254 &table->entry[filter_idx].handle, 3255 true); 3256 3257 spin_lock_bh(&efx->filter_lock); 3258 if (rc == 0) 3259 *spec = new_spec; 3260 } else { 3261 /* Really remove the filter */ 3262 3263 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3264 efx_ef10_filter_is_exclusive(spec) ? 3265 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3266 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3267 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3268 table->entry[filter_idx].handle); 3269 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3270 inbuf, sizeof(inbuf), NULL, 0, NULL); 3271 3272 spin_lock_bh(&efx->filter_lock); 3273 if (rc == 0) { 3274 kfree(spec); 3275 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3276 } 3277 } 3278 3279 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 3280 wake_up_all(&table->waitq); 3281 out_unlock: 3282 spin_unlock_bh(&efx->filter_lock); 3283 finish_wait(&table->waitq, &wait); 3284 return rc; 3285 } 3286 3287 static int efx_ef10_filter_remove_safe(struct efx_nic *efx, 3288 enum efx_filter_priority priority, 3289 u32 filter_id) 3290 { 3291 return efx_ef10_filter_remove_internal(efx, 1U << priority, 3292 filter_id, false); 3293 } 3294 3295 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id) 3296 { 3297 return filter_id % HUNT_FILTER_TBL_ROWS; 3298 } 3299 3300 static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx, 3301 enum efx_filter_priority priority, 3302 u32 filter_id) 3303 { 3304 return efx_ef10_filter_remove_internal(efx, 1U << priority, 3305 filter_id, true); 3306 } 3307 3308 static int efx_ef10_filter_get_safe(struct efx_nic *efx, 3309 enum efx_filter_priority priority, 3310 u32 filter_id, struct efx_filter_spec *spec) 3311 { 3312 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 3313 struct efx_ef10_filter_table *table = efx->filter_state; 3314 const struct efx_filter_spec *saved_spec; 3315 int rc; 3316 3317 spin_lock_bh(&efx->filter_lock); 3318 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx); 3319 if (saved_spec && saved_spec->priority == priority && 3320 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) == 3321 filter_id / HUNT_FILTER_TBL_ROWS) { 3322 *spec = *saved_spec; 3323 rc = 0; 3324 } else { 3325 rc = -ENOENT; 3326 } 3327 spin_unlock_bh(&efx->filter_lock); 3328 return rc; 3329 } 3330 3331 static int efx_ef10_filter_clear_rx(struct efx_nic *efx, 3332 enum efx_filter_priority priority) 3333 { 3334 unsigned int priority_mask; 3335 unsigned int i; 3336 int rc; 3337 3338 priority_mask = (((1U << (priority + 1)) - 1) & 3339 ~(1U << EFX_FILTER_PRI_AUTO)); 3340 3341 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 3342 rc = efx_ef10_filter_remove_internal(efx, priority_mask, 3343 i, true); 3344 if (rc && rc != -ENOENT) 3345 return rc; 3346 } 3347 3348 return 0; 3349 } 3350 3351 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx, 3352 enum efx_filter_priority priority) 3353 { 3354 struct efx_ef10_filter_table *table = efx->filter_state; 3355 unsigned int filter_idx; 3356 s32 count = 0; 3357 3358 spin_lock_bh(&efx->filter_lock); 3359 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3360 if (table->entry[filter_idx].spec && 3361 efx_ef10_filter_entry_spec(table, filter_idx)->priority == 3362 priority) 3363 ++count; 3364 } 3365 spin_unlock_bh(&efx->filter_lock); 3366 return count; 3367 } 3368 3369 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx) 3370 { 3371 struct efx_ef10_filter_table *table = efx->filter_state; 3372 3373 return table->rx_match_count * HUNT_FILTER_TBL_ROWS; 3374 } 3375 3376 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx, 3377 enum efx_filter_priority priority, 3378 u32 *buf, u32 size) 3379 { 3380 struct efx_ef10_filter_table *table = efx->filter_state; 3381 struct efx_filter_spec *spec; 3382 unsigned int filter_idx; 3383 s32 count = 0; 3384 3385 spin_lock_bh(&efx->filter_lock); 3386 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3387 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3388 if (spec && spec->priority == priority) { 3389 if (count == size) { 3390 count = -EMSGSIZE; 3391 break; 3392 } 3393 buf[count++] = (efx_ef10_filter_rx_match_pri( 3394 table, spec->match_flags) * 3395 HUNT_FILTER_TBL_ROWS + 3396 filter_idx); 3397 } 3398 } 3399 spin_unlock_bh(&efx->filter_lock); 3400 return count; 3401 } 3402 3403 #ifdef CONFIG_RFS_ACCEL 3404 3405 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete; 3406 3407 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx, 3408 struct efx_filter_spec *spec) 3409 { 3410 struct efx_ef10_filter_table *table = efx->filter_state; 3411 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3412 struct efx_filter_spec *saved_spec; 3413 unsigned int hash, i, depth = 1; 3414 bool replacing = false; 3415 int ins_index = -1; 3416 u64 cookie; 3417 s32 rc; 3418 3419 /* Must be an RX filter without RSS and not for a multicast 3420 * destination address (RFS only works for connected sockets). 3421 * These restrictions allow us to pass only a tiny amount of 3422 * data through to the completion function. 3423 */ 3424 EFX_WARN_ON_PARANOID(spec->flags != 3425 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER)); 3426 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT); 3427 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec)); 3428 3429 hash = efx_ef10_filter_hash(spec); 3430 3431 spin_lock_bh(&efx->filter_lock); 3432 3433 /* Find any existing filter with the same match tuple or else 3434 * a free slot to insert at. If an existing filter is busy, 3435 * we have to give up. 3436 */ 3437 for (;;) { 3438 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3439 saved_spec = efx_ef10_filter_entry_spec(table, i); 3440 3441 if (!saved_spec) { 3442 if (ins_index < 0) 3443 ins_index = i; 3444 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 3445 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) { 3446 rc = -EBUSY; 3447 goto fail_unlock; 3448 } 3449 if (spec->priority < saved_spec->priority) { 3450 rc = -EPERM; 3451 goto fail_unlock; 3452 } 3453 ins_index = i; 3454 break; 3455 } 3456 3457 /* Once we reach the maximum search depth, use the 3458 * first suitable slot or return -EBUSY if there was 3459 * none 3460 */ 3461 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 3462 if (ins_index < 0) { 3463 rc = -EBUSY; 3464 goto fail_unlock; 3465 } 3466 break; 3467 } 3468 3469 ++depth; 3470 } 3471 3472 /* Create a software table entry if necessary, and mark it 3473 * busy. We might yet fail to insert, but any attempt to 3474 * insert a conflicting filter while we're waiting for the 3475 * firmware must find the busy entry. 3476 */ 3477 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 3478 if (saved_spec) { 3479 replacing = true; 3480 } else { 3481 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 3482 if (!saved_spec) { 3483 rc = -ENOMEM; 3484 goto fail_unlock; 3485 } 3486 *saved_spec = *spec; 3487 } 3488 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 3489 EFX_EF10_FILTER_FLAG_BUSY); 3490 3491 spin_unlock_bh(&efx->filter_lock); 3492 3493 /* Pack up the variables needed on completion */ 3494 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id; 3495 3496 efx_ef10_filter_push_prep(efx, spec, inbuf, 3497 table->entry[ins_index].handle, replacing); 3498 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3499 MC_CMD_FILTER_OP_OUT_LEN, 3500 efx_ef10_filter_rfs_insert_complete, cookie); 3501 3502 return ins_index; 3503 3504 fail_unlock: 3505 spin_unlock_bh(&efx->filter_lock); 3506 return rc; 3507 } 3508 3509 static void 3510 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie, 3511 int rc, efx_dword_t *outbuf, 3512 size_t outlen_actual) 3513 { 3514 struct efx_ef10_filter_table *table = efx->filter_state; 3515 unsigned int ins_index, dmaq_id; 3516 struct efx_filter_spec *spec; 3517 bool replacing; 3518 3519 /* Unpack the cookie */ 3520 replacing = cookie >> 31; 3521 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1); 3522 dmaq_id = cookie & 0xffff; 3523 3524 spin_lock_bh(&efx->filter_lock); 3525 spec = efx_ef10_filter_entry_spec(table, ins_index); 3526 if (rc == 0) { 3527 table->entry[ins_index].handle = 3528 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 3529 if (replacing) 3530 spec->dmaq_id = dmaq_id; 3531 } else if (!replacing) { 3532 kfree(spec); 3533 spec = NULL; 3534 } 3535 efx_ef10_filter_set_entry(table, ins_index, spec, 0); 3536 spin_unlock_bh(&efx->filter_lock); 3537 3538 wake_up_all(&table->waitq); 3539 } 3540 3541 static void 3542 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 3543 unsigned long filter_idx, 3544 int rc, efx_dword_t *outbuf, 3545 size_t outlen_actual); 3546 3547 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, 3548 unsigned int filter_idx) 3549 { 3550 struct efx_ef10_filter_table *table = efx->filter_state; 3551 struct efx_filter_spec *spec = 3552 efx_ef10_filter_entry_spec(table, filter_idx); 3553 MCDI_DECLARE_BUF(inbuf, 3554 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 3555 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 3556 3557 if (!spec || 3558 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) || 3559 spec->priority != EFX_FILTER_PRI_HINT || 3560 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id, 3561 flow_id, filter_idx)) 3562 return false; 3563 3564 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3565 MC_CMD_FILTER_OP_IN_OP_REMOVE); 3566 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3567 table->entry[filter_idx].handle); 3568 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0, 3569 efx_ef10_filter_rfs_expire_complete, filter_idx)) 3570 return false; 3571 3572 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3573 return true; 3574 } 3575 3576 static void 3577 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 3578 unsigned long filter_idx, 3579 int rc, efx_dword_t *outbuf, 3580 size_t outlen_actual) 3581 { 3582 struct efx_ef10_filter_table *table = efx->filter_state; 3583 struct efx_filter_spec *spec = 3584 efx_ef10_filter_entry_spec(table, filter_idx); 3585 3586 spin_lock_bh(&efx->filter_lock); 3587 if (rc == 0) { 3588 kfree(spec); 3589 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3590 } 3591 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 3592 wake_up_all(&table->waitq); 3593 spin_unlock_bh(&efx->filter_lock); 3594 } 3595 3596 #endif /* CONFIG_RFS_ACCEL */ 3597 3598 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags) 3599 { 3600 int match_flags = 0; 3601 3602 #define MAP_FLAG(gen_flag, mcdi_field) { \ 3603 u32 old_mcdi_flags = mcdi_flags; \ 3604 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 3605 mcdi_field ## _LBN); \ 3606 if (mcdi_flags != old_mcdi_flags) \ 3607 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \ 3608 } 3609 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST); 3610 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST); 3611 MAP_FLAG(REM_HOST, SRC_IP); 3612 MAP_FLAG(LOC_HOST, DST_IP); 3613 MAP_FLAG(REM_MAC, SRC_MAC); 3614 MAP_FLAG(REM_PORT, SRC_PORT); 3615 MAP_FLAG(LOC_MAC, DST_MAC); 3616 MAP_FLAG(LOC_PORT, DST_PORT); 3617 MAP_FLAG(ETHER_TYPE, ETHER_TYPE); 3618 MAP_FLAG(INNER_VID, INNER_VLAN); 3619 MAP_FLAG(OUTER_VID, OUTER_VLAN); 3620 MAP_FLAG(IP_PROTO, IP_PROTO); 3621 #undef MAP_FLAG 3622 3623 /* Did we map them all? */ 3624 if (mcdi_flags) 3625 return -EINVAL; 3626 3627 return match_flags; 3628 } 3629 3630 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 3631 { 3632 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN); 3633 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX); 3634 unsigned int pd_match_pri, pd_match_count; 3635 struct efx_ef10_filter_table *table; 3636 size_t outlen; 3637 int rc; 3638 3639 table = kzalloc(sizeof(*table), GFP_KERNEL); 3640 if (!table) 3641 return -ENOMEM; 3642 3643 /* Find out which RX filter types are supported, and their priorities */ 3644 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP, 3645 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); 3646 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO, 3647 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf), 3648 &outlen); 3649 if (rc) 3650 goto fail; 3651 pd_match_count = MCDI_VAR_ARRAY_LEN( 3652 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES); 3653 table->rx_match_count = 0; 3654 3655 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) { 3656 u32 mcdi_flags = 3657 MCDI_ARRAY_DWORD( 3658 outbuf, 3659 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES, 3660 pd_match_pri); 3661 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags); 3662 if (rc < 0) { 3663 netif_dbg(efx, probe, efx->net_dev, 3664 "%s: fw flags %#x pri %u not supported in driver\n", 3665 __func__, mcdi_flags, pd_match_pri); 3666 } else { 3667 netif_dbg(efx, probe, efx->net_dev, 3668 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n", 3669 __func__, mcdi_flags, pd_match_pri, 3670 rc, table->rx_match_count); 3671 table->rx_match_flags[table->rx_match_count++] = rc; 3672 } 3673 } 3674 3675 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry)); 3676 if (!table->entry) { 3677 rc = -ENOMEM; 3678 goto fail; 3679 } 3680 3681 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID; 3682 table->bcast_id = EFX_EF10_FILTER_ID_INVALID; 3683 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID; 3684 3685 efx->filter_state = table; 3686 init_waitqueue_head(&table->waitq); 3687 return 0; 3688 3689 fail: 3690 kfree(table); 3691 return rc; 3692 } 3693 3694 /* Caller must hold efx->filter_sem for read if race against 3695 * efx_ef10_filter_table_remove() is possible 3696 */ 3697 static void efx_ef10_filter_table_restore(struct efx_nic *efx) 3698 { 3699 struct efx_ef10_filter_table *table = efx->filter_state; 3700 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3701 struct efx_filter_spec *spec; 3702 unsigned int filter_idx; 3703 bool failed = false; 3704 int rc; 3705 3706 WARN_ON(!rwsem_is_locked(&efx->filter_sem)); 3707 3708 if (!nic_data->must_restore_filters) 3709 return; 3710 3711 if (!table) 3712 return; 3713 3714 spin_lock_bh(&efx->filter_lock); 3715 3716 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3717 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3718 if (!spec) 3719 continue; 3720 3721 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3722 spin_unlock_bh(&efx->filter_lock); 3723 3724 rc = efx_ef10_filter_push(efx, spec, 3725 &table->entry[filter_idx].handle, 3726 false); 3727 if (rc) 3728 failed = true; 3729 3730 spin_lock_bh(&efx->filter_lock); 3731 if (rc) { 3732 kfree(spec); 3733 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3734 } else { 3735 table->entry[filter_idx].spec &= 3736 ~EFX_EF10_FILTER_FLAG_BUSY; 3737 } 3738 } 3739 3740 spin_unlock_bh(&efx->filter_lock); 3741 3742 if (failed) 3743 netif_err(efx, hw, efx->net_dev, 3744 "unable to restore all filters\n"); 3745 else 3746 nic_data->must_restore_filters = false; 3747 } 3748 3749 /* Caller must hold efx->filter_sem for write */ 3750 static void efx_ef10_filter_table_remove(struct efx_nic *efx) 3751 { 3752 struct efx_ef10_filter_table *table = efx->filter_state; 3753 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3754 struct efx_filter_spec *spec; 3755 unsigned int filter_idx; 3756 int rc; 3757 3758 efx->filter_state = NULL; 3759 if (!table) 3760 return; 3761 3762 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3763 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3764 if (!spec) 3765 continue; 3766 3767 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3768 efx_ef10_filter_is_exclusive(spec) ? 3769 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3770 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3771 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3772 table->entry[filter_idx].handle); 3773 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3774 NULL, 0, NULL); 3775 if (rc) 3776 netdev_WARN(efx->net_dev, 3777 "filter_idx=%#x handle=%#llx\n", 3778 filter_idx, 3779 table->entry[filter_idx].handle); 3780 kfree(spec); 3781 } 3782 3783 vfree(table->entry); 3784 kfree(table); 3785 } 3786 3787 #define EFX_EF10_FILTER_DO_MARK_OLD(id) \ 3788 if (id != EFX_EF10_FILTER_ID_INVALID) { \ 3789 filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \ 3790 WARN_ON(!table->entry[filter_idx].spec); \ 3791 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; \ 3792 } 3793 static void efx_ef10_filter_mark_old(struct efx_nic *efx) 3794 { 3795 struct efx_ef10_filter_table *table = efx->filter_state; 3796 unsigned int filter_idx, i; 3797 3798 if (!table) 3799 return; 3800 3801 /* Mark old filters that may need to be removed */ 3802 spin_lock_bh(&efx->filter_lock); 3803 for (i = 0; i < table->dev_uc_count; i++) 3804 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id); 3805 for (i = 0; i < table->dev_mc_count; i++) 3806 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id); 3807 EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id); 3808 EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id); 3809 EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id); 3810 spin_unlock_bh(&efx->filter_lock); 3811 } 3812 #undef EFX_EF10_FILTER_DO_MARK_OLD 3813 3814 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc) 3815 { 3816 struct efx_ef10_filter_table *table = efx->filter_state; 3817 struct net_device *net_dev = efx->net_dev; 3818 struct netdev_hw_addr *uc; 3819 int addr_count; 3820 unsigned int i; 3821 3822 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID; 3823 addr_count = netdev_uc_count(net_dev); 3824 if (net_dev->flags & IFF_PROMISC) 3825 *promisc = true; 3826 table->dev_uc_count = 1 + addr_count; 3827 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr); 3828 i = 1; 3829 netdev_for_each_uc_addr(uc, net_dev) { 3830 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) { 3831 *promisc = true; 3832 break; 3833 } 3834 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr); 3835 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID; 3836 i++; 3837 } 3838 } 3839 3840 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc) 3841 { 3842 struct efx_ef10_filter_table *table = efx->filter_state; 3843 struct net_device *net_dev = efx->net_dev; 3844 struct netdev_hw_addr *mc; 3845 unsigned int i, addr_count; 3846 3847 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID; 3848 table->bcast_id = EFX_EF10_FILTER_ID_INVALID; 3849 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) 3850 *promisc = true; 3851 3852 addr_count = netdev_mc_count(net_dev); 3853 i = 0; 3854 netdev_for_each_mc_addr(mc, net_dev) { 3855 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) { 3856 *promisc = true; 3857 break; 3858 } 3859 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr); 3860 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID; 3861 i++; 3862 } 3863 3864 table->dev_mc_count = i; 3865 } 3866 3867 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx, 3868 bool multicast, bool rollback) 3869 { 3870 struct efx_ef10_filter_table *table = efx->filter_state; 3871 struct efx_ef10_dev_addr *addr_list; 3872 struct efx_filter_spec spec; 3873 u8 baddr[ETH_ALEN]; 3874 unsigned int i, j; 3875 int addr_count; 3876 int rc; 3877 3878 if (multicast) { 3879 addr_list = table->dev_mc_list; 3880 addr_count = table->dev_mc_count; 3881 } else { 3882 addr_list = table->dev_uc_list; 3883 addr_count = table->dev_uc_count; 3884 } 3885 3886 /* Insert/renew filters */ 3887 for (i = 0; i < addr_count; i++) { 3888 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3889 EFX_FILTER_FLAG_RX_RSS, 3890 0); 3891 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 3892 addr_list[i].addr); 3893 rc = efx_ef10_filter_insert(efx, &spec, true); 3894 if (rc < 0) { 3895 if (rollback) { 3896 netif_info(efx, drv, efx->net_dev, 3897 "efx_ef10_filter_insert failed rc=%d\n", 3898 rc); 3899 /* Fall back to promiscuous */ 3900 for (j = 0; j < i; j++) { 3901 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID) 3902 continue; 3903 efx_ef10_filter_remove_unsafe( 3904 efx, EFX_FILTER_PRI_AUTO, 3905 addr_list[j].id); 3906 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID; 3907 } 3908 return rc; 3909 } else { 3910 /* mark as not inserted, and carry on */ 3911 rc = EFX_EF10_FILTER_ID_INVALID; 3912 } 3913 } 3914 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc); 3915 } 3916 3917 if (multicast && rollback) { 3918 /* Also need an Ethernet broadcast filter */ 3919 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3920 EFX_FILTER_FLAG_RX_RSS, 3921 0); 3922 eth_broadcast_addr(baddr); 3923 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr); 3924 rc = efx_ef10_filter_insert(efx, &spec, true); 3925 if (rc < 0) { 3926 netif_warn(efx, drv, efx->net_dev, 3927 "Broadcast filter insert failed rc=%d\n", rc); 3928 /* Fall back to promiscuous */ 3929 for (j = 0; j < i; j++) { 3930 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID) 3931 continue; 3932 efx_ef10_filter_remove_unsafe( 3933 efx, EFX_FILTER_PRI_AUTO, 3934 addr_list[j].id); 3935 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID; 3936 } 3937 return rc; 3938 } else { 3939 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc); 3940 } 3941 } 3942 3943 return 0; 3944 } 3945 3946 static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast, 3947 bool rollback) 3948 { 3949 struct efx_ef10_filter_table *table = efx->filter_state; 3950 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3951 struct efx_filter_spec spec; 3952 u8 baddr[ETH_ALEN]; 3953 int rc; 3954 3955 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3956 EFX_FILTER_FLAG_RX_RSS, 3957 0); 3958 3959 if (multicast) 3960 efx_filter_set_mc_def(&spec); 3961 else 3962 efx_filter_set_uc_def(&spec); 3963 3964 rc = efx_ef10_filter_insert(efx, &spec, true); 3965 if (rc < 0) { 3966 netif_warn(efx, drv, efx->net_dev, 3967 "%scast mismatch filter insert failed rc=%d\n", 3968 multicast ? "Multi" : "Uni", rc); 3969 } else if (multicast) { 3970 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc); 3971 if (!nic_data->workaround_26807) { 3972 /* Also need an Ethernet broadcast filter */ 3973 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3974 EFX_FILTER_FLAG_RX_RSS, 3975 0); 3976 eth_broadcast_addr(baddr); 3977 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 3978 baddr); 3979 rc = efx_ef10_filter_insert(efx, &spec, true); 3980 if (rc < 0) { 3981 netif_warn(efx, drv, efx->net_dev, 3982 "Broadcast filter insert failed rc=%d\n", 3983 rc); 3984 if (rollback) { 3985 /* Roll back the mc_def filter */ 3986 efx_ef10_filter_remove_unsafe( 3987 efx, EFX_FILTER_PRI_AUTO, 3988 table->mcdef_id); 3989 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID; 3990 return rc; 3991 } 3992 } else { 3993 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc); 3994 } 3995 } 3996 rc = 0; 3997 } else { 3998 table->ucdef_id = rc; 3999 rc = 0; 4000 } 4001 return rc; 4002 } 4003 4004 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD 4005 * flag or removes these filters, we don't need to hold the filter_lock while 4006 * scanning for these filters. 4007 */ 4008 static void efx_ef10_filter_remove_old(struct efx_nic *efx) 4009 { 4010 struct efx_ef10_filter_table *table = efx->filter_state; 4011 bool remove_failed = false; 4012 int i; 4013 4014 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 4015 if (ACCESS_ONCE(table->entry[i].spec) & 4016 EFX_EF10_FILTER_FLAG_AUTO_OLD) { 4017 if (efx_ef10_filter_remove_internal( 4018 efx, 1U << EFX_FILTER_PRI_AUTO, 4019 i, true) < 0) 4020 remove_failed = true; 4021 } 4022 } 4023 WARN_ON(remove_failed); 4024 } 4025 4026 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 4027 { 4028 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4029 u8 mac_old[ETH_ALEN]; 4030 int rc, rc2; 4031 4032 /* Only reconfigure a PF-created vport */ 4033 if (is_zero_ether_addr(nic_data->vport_mac)) 4034 return 0; 4035 4036 efx_device_detach_sync(efx); 4037 efx_net_stop(efx->net_dev); 4038 down_write(&efx->filter_sem); 4039 efx_ef10_filter_table_remove(efx); 4040 up_write(&efx->filter_sem); 4041 4042 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id); 4043 if (rc) 4044 goto restore_filters; 4045 4046 ether_addr_copy(mac_old, nic_data->vport_mac); 4047 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id, 4048 nic_data->vport_mac); 4049 if (rc) 4050 goto restore_vadaptor; 4051 4052 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id, 4053 efx->net_dev->dev_addr); 4054 if (!rc) { 4055 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 4056 } else { 4057 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old); 4058 if (rc2) { 4059 /* Failed to add original MAC, so clear vport_mac */ 4060 eth_zero_addr(nic_data->vport_mac); 4061 goto reset_nic; 4062 } 4063 } 4064 4065 restore_vadaptor: 4066 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id); 4067 if (rc2) 4068 goto reset_nic; 4069 restore_filters: 4070 down_write(&efx->filter_sem); 4071 rc2 = efx_ef10_filter_table_probe(efx); 4072 up_write(&efx->filter_sem); 4073 if (rc2) 4074 goto reset_nic; 4075 4076 rc2 = efx_net_open(efx->net_dev); 4077 if (rc2) 4078 goto reset_nic; 4079 4080 netif_device_attach(efx->net_dev); 4081 4082 return rc; 4083 4084 reset_nic: 4085 netif_err(efx, drv, efx->net_dev, 4086 "Failed to restore when changing MAC address - scheduling reset\n"); 4087 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 4088 4089 return rc ? rc : rc2; 4090 } 4091 4092 /* Caller must hold efx->filter_sem for read if race against 4093 * efx_ef10_filter_table_remove() is possible 4094 */ 4095 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx) 4096 { 4097 struct efx_ef10_filter_table *table = efx->filter_state; 4098 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4099 struct net_device *net_dev = efx->net_dev; 4100 bool uc_promisc = false, mc_promisc = false; 4101 4102 if (!efx_dev_registered(efx)) 4103 return; 4104 4105 if (!table) 4106 return; 4107 4108 efx_ef10_filter_mark_old(efx); 4109 4110 /* Copy/convert the address lists; add the primary station 4111 * address and broadcast address 4112 */ 4113 netif_addr_lock_bh(net_dev); 4114 efx_ef10_filter_uc_addr_list(efx, &uc_promisc); 4115 efx_ef10_filter_mc_addr_list(efx, &mc_promisc); 4116 netif_addr_unlock_bh(net_dev); 4117 4118 /* Insert/renew unicast filters */ 4119 if (uc_promisc) { 4120 efx_ef10_filter_insert_def(efx, false, false); 4121 efx_ef10_filter_insert_addr_list(efx, false, false); 4122 } else { 4123 /* If any of the filters failed to insert, fall back to 4124 * promiscuous mode - add in the uc_def filter. But keep 4125 * our individual unicast filters. 4126 */ 4127 if (efx_ef10_filter_insert_addr_list(efx, false, false)) 4128 efx_ef10_filter_insert_def(efx, false, false); 4129 } 4130 4131 /* Insert/renew multicast filters */ 4132 /* If changing promiscuous state with cascaded multicast filters, remove 4133 * old filters first, so that packets are dropped rather than duplicated 4134 */ 4135 if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc) 4136 efx_ef10_filter_remove_old(efx); 4137 if (mc_promisc) { 4138 if (nic_data->workaround_26807) { 4139 /* If we failed to insert promiscuous filters, rollback 4140 * and fall back to individual multicast filters 4141 */ 4142 if (efx_ef10_filter_insert_def(efx, true, true)) { 4143 /* Changing promisc state, so remove old filters */ 4144 efx_ef10_filter_remove_old(efx); 4145 efx_ef10_filter_insert_addr_list(efx, true, false); 4146 } 4147 } else { 4148 /* If we failed to insert promiscuous filters, don't 4149 * rollback. Regardless, also insert the mc_list 4150 */ 4151 efx_ef10_filter_insert_def(efx, true, false); 4152 efx_ef10_filter_insert_addr_list(efx, true, false); 4153 } 4154 } else { 4155 /* If any filters failed to insert, rollback and fall back to 4156 * promiscuous mode - mc_def filter and maybe broadcast. If 4157 * that fails, roll back again and insert as many of our 4158 * individual multicast filters as we can. 4159 */ 4160 if (efx_ef10_filter_insert_addr_list(efx, true, true)) { 4161 /* Changing promisc state, so remove old filters */ 4162 if (nic_data->workaround_26807) 4163 efx_ef10_filter_remove_old(efx); 4164 if (efx_ef10_filter_insert_def(efx, true, true)) 4165 efx_ef10_filter_insert_addr_list(efx, true, false); 4166 } 4167 } 4168 4169 efx_ef10_filter_remove_old(efx); 4170 efx->mc_promisc = mc_promisc; 4171 } 4172 4173 static int efx_ef10_set_mac_address(struct efx_nic *efx) 4174 { 4175 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 4176 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4177 bool was_enabled = efx->port_enabled; 4178 int rc; 4179 4180 efx_device_detach_sync(efx); 4181 efx_net_stop(efx->net_dev); 4182 down_write(&efx->filter_sem); 4183 efx_ef10_filter_table_remove(efx); 4184 4185 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 4186 efx->net_dev->dev_addr); 4187 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 4188 nic_data->vport_id); 4189 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 4190 sizeof(inbuf), NULL, 0, NULL); 4191 4192 efx_ef10_filter_table_probe(efx); 4193 up_write(&efx->filter_sem); 4194 if (was_enabled) 4195 efx_net_open(efx->net_dev); 4196 netif_device_attach(efx->net_dev); 4197 4198 #ifdef CONFIG_SFC_SRIOV 4199 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 4200 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 4201 4202 if (rc == -EPERM) { 4203 struct efx_nic *efx_pf; 4204 4205 /* Switch to PF and change MAC address on vport */ 4206 efx_pf = pci_get_drvdata(pci_dev_pf); 4207 4208 rc = efx_ef10_sriov_set_vf_mac(efx_pf, 4209 nic_data->vf_index, 4210 efx->net_dev->dev_addr); 4211 } else if (!rc) { 4212 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 4213 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data; 4214 unsigned int i; 4215 4216 /* MAC address successfully changed by VF (with MAC 4217 * spoofing) so update the parent PF if possible. 4218 */ 4219 for (i = 0; i < efx_pf->vf_count; ++i) { 4220 struct ef10_vf *vf = nic_data->vf + i; 4221 4222 if (vf->efx == efx) { 4223 ether_addr_copy(vf->mac, 4224 efx->net_dev->dev_addr); 4225 return 0; 4226 } 4227 } 4228 } 4229 } else 4230 #endif 4231 if (rc == -EPERM) { 4232 netif_err(efx, drv, efx->net_dev, 4233 "Cannot change MAC address; use sfboot to enable" 4234 " mac-spoofing on this interface\n"); 4235 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 4236 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 4237 * fall-back to the method of changing the MAC address on the 4238 * vport. This only applies to PFs because such versions of 4239 * MCFW do not support VFs. 4240 */ 4241 rc = efx_ef10_vport_set_mac_address(efx); 4242 } else { 4243 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 4244 sizeof(inbuf), NULL, 0, rc); 4245 } 4246 4247 return rc; 4248 } 4249 4250 static int efx_ef10_mac_reconfigure(struct efx_nic *efx) 4251 { 4252 efx_ef10_filter_sync_rx_mode(efx); 4253 4254 return efx_mcdi_set_mac(efx); 4255 } 4256 4257 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx) 4258 { 4259 efx_ef10_filter_sync_rx_mode(efx); 4260 4261 return 0; 4262 } 4263 4264 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 4265 { 4266 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 4267 4268 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 4269 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 4270 NULL, 0, NULL); 4271 } 4272 4273 /* MC BISTs follow a different poll mechanism to phy BISTs. 4274 * The BIST is done in the poll handler on the MC, and the MCDI command 4275 * will block until the BIST is done. 4276 */ 4277 static int efx_ef10_poll_bist(struct efx_nic *efx) 4278 { 4279 int rc; 4280 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 4281 size_t outlen; 4282 u32 result; 4283 4284 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 4285 outbuf, sizeof(outbuf), &outlen); 4286 if (rc != 0) 4287 return rc; 4288 4289 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 4290 return -EIO; 4291 4292 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 4293 switch (result) { 4294 case MC_CMD_POLL_BIST_PASSED: 4295 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 4296 return 0; 4297 case MC_CMD_POLL_BIST_TIMEOUT: 4298 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 4299 return -EIO; 4300 case MC_CMD_POLL_BIST_FAILED: 4301 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 4302 return -EIO; 4303 default: 4304 netif_err(efx, hw, efx->net_dev, 4305 "BIST returned unknown result %u", result); 4306 return -EIO; 4307 } 4308 } 4309 4310 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 4311 { 4312 int rc; 4313 4314 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 4315 4316 rc = efx_ef10_start_bist(efx, bist_type); 4317 if (rc != 0) 4318 return rc; 4319 4320 return efx_ef10_poll_bist(efx); 4321 } 4322 4323 static int 4324 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 4325 { 4326 int rc, rc2; 4327 4328 efx_reset_down(efx, RESET_TYPE_WORLD); 4329 4330 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 4331 NULL, 0, NULL, 0, NULL); 4332 if (rc != 0) 4333 goto out; 4334 4335 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 4336 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 4337 4338 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 4339 4340 out: 4341 if (rc == -EPERM) 4342 rc = 0; 4343 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 4344 return rc ? rc : rc2; 4345 } 4346 4347 #ifdef CONFIG_SFC_MTD 4348 4349 struct efx_ef10_nvram_type_info { 4350 u16 type, type_mask; 4351 u8 port; 4352 const char *name; 4353 }; 4354 4355 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 4356 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 4357 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 4358 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 4359 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 4360 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 4361 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 4362 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 4363 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 4364 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 4365 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 4366 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 4367 }; 4368 4369 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 4370 struct efx_mcdi_mtd_partition *part, 4371 unsigned int type) 4372 { 4373 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 4374 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 4375 const struct efx_ef10_nvram_type_info *info; 4376 size_t size, erase_size, outlen; 4377 bool protected; 4378 int rc; 4379 4380 for (info = efx_ef10_nvram_types; ; info++) { 4381 if (info == 4382 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types)) 4383 return -ENODEV; 4384 if ((type & ~info->type_mask) == info->type) 4385 break; 4386 } 4387 if (info->port != efx_port_num(efx)) 4388 return -ENODEV; 4389 4390 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 4391 if (rc) 4392 return rc; 4393 if (protected) 4394 return -ENODEV; /* hide it */ 4395 4396 part->nvram_type = type; 4397 4398 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 4399 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 4400 outbuf, sizeof(outbuf), &outlen); 4401 if (rc) 4402 return rc; 4403 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 4404 return -EIO; 4405 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 4406 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 4407 part->fw_subtype = MCDI_DWORD(outbuf, 4408 NVRAM_METADATA_OUT_SUBTYPE); 4409 4410 part->common.dev_type_name = "EF10 NVRAM manager"; 4411 part->common.type_name = info->name; 4412 4413 part->common.mtd.type = MTD_NORFLASH; 4414 part->common.mtd.flags = MTD_CAP_NORFLASH; 4415 part->common.mtd.size = size; 4416 part->common.mtd.erasesize = erase_size; 4417 4418 return 0; 4419 } 4420 4421 static int efx_ef10_mtd_probe(struct efx_nic *efx) 4422 { 4423 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 4424 struct efx_mcdi_mtd_partition *parts; 4425 size_t outlen, n_parts_total, i, n_parts; 4426 unsigned int type; 4427 int rc; 4428 4429 ASSERT_RTNL(); 4430 4431 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 4432 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 4433 outbuf, sizeof(outbuf), &outlen); 4434 if (rc) 4435 return rc; 4436 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 4437 return -EIO; 4438 4439 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 4440 if (n_parts_total > 4441 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 4442 return -EIO; 4443 4444 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 4445 if (!parts) 4446 return -ENOMEM; 4447 4448 n_parts = 0; 4449 for (i = 0; i < n_parts_total; i++) { 4450 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 4451 i); 4452 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type); 4453 if (rc == 0) 4454 n_parts++; 4455 else if (rc != -ENODEV) 4456 goto fail; 4457 } 4458 4459 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 4460 fail: 4461 if (rc) 4462 kfree(parts); 4463 return rc; 4464 } 4465 4466 #endif /* CONFIG_SFC_MTD */ 4467 4468 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 4469 { 4470 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 4471 } 4472 4473 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 4474 u32 host_time) {} 4475 4476 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 4477 bool temp) 4478 { 4479 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 4480 int rc; 4481 4482 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 4483 channel->sync_events_state == SYNC_EVENTS_VALID || 4484 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 4485 return 0; 4486 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 4487 4488 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 4489 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 4490 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 4491 channel->channel); 4492 4493 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 4494 inbuf, sizeof(inbuf), NULL, 0, NULL); 4495 4496 if (rc != 0) 4497 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 4498 SYNC_EVENTS_DISABLED; 4499 4500 return rc; 4501 } 4502 4503 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 4504 bool temp) 4505 { 4506 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 4507 int rc; 4508 4509 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 4510 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 4511 return 0; 4512 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 4513 channel->sync_events_state = SYNC_EVENTS_DISABLED; 4514 return 0; 4515 } 4516 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 4517 SYNC_EVENTS_DISABLED; 4518 4519 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 4520 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 4521 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 4522 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 4523 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 4524 channel->channel); 4525 4526 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 4527 inbuf, sizeof(inbuf), NULL, 0, NULL); 4528 4529 return rc; 4530 } 4531 4532 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 4533 bool temp) 4534 { 4535 int (*set)(struct efx_channel *channel, bool temp); 4536 struct efx_channel *channel; 4537 4538 set = en ? 4539 efx_ef10_rx_enable_timestamping : 4540 efx_ef10_rx_disable_timestamping; 4541 4542 efx_for_each_channel(channel, efx) { 4543 int rc = set(channel, temp); 4544 if (en && rc != 0) { 4545 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 4546 return rc; 4547 } 4548 } 4549 4550 return 0; 4551 } 4552 4553 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 4554 struct hwtstamp_config *init) 4555 { 4556 return -EOPNOTSUPP; 4557 } 4558 4559 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 4560 struct hwtstamp_config *init) 4561 { 4562 int rc; 4563 4564 switch (init->rx_filter) { 4565 case HWTSTAMP_FILTER_NONE: 4566 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 4567 /* if TX timestamping is still requested then leave PTP on */ 4568 return efx_ptp_change_mode(efx, 4569 init->tx_type != HWTSTAMP_TX_OFF, 0); 4570 case HWTSTAMP_FILTER_ALL: 4571 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 4572 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 4573 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 4574 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 4575 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 4576 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 4577 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 4578 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 4579 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 4580 case HWTSTAMP_FILTER_PTP_V2_EVENT: 4581 case HWTSTAMP_FILTER_PTP_V2_SYNC: 4582 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 4583 init->rx_filter = HWTSTAMP_FILTER_ALL; 4584 rc = efx_ptp_change_mode(efx, true, 0); 4585 if (!rc) 4586 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 4587 if (rc) 4588 efx_ptp_change_mode(efx, false, 0); 4589 return rc; 4590 default: 4591 return -ERANGE; 4592 } 4593 } 4594 4595 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 4596 .is_vf = true, 4597 .mem_bar = EFX_MEM_VF_BAR, 4598 .mem_map_size = efx_ef10_mem_map_size, 4599 .probe = efx_ef10_probe_vf, 4600 .remove = efx_ef10_remove, 4601 .dimension_resources = efx_ef10_dimension_resources, 4602 .init = efx_ef10_init_nic, 4603 .fini = efx_port_dummy_op_void, 4604 .map_reset_reason = efx_ef10_map_reset_reason, 4605 .map_reset_flags = efx_ef10_map_reset_flags, 4606 .reset = efx_ef10_reset, 4607 .probe_port = efx_mcdi_port_probe, 4608 .remove_port = efx_mcdi_port_remove, 4609 .fini_dmaq = efx_ef10_fini_dmaq, 4610 .prepare_flr = efx_ef10_prepare_flr, 4611 .finish_flr = efx_port_dummy_op_void, 4612 .describe_stats = efx_ef10_describe_stats, 4613 .update_stats = efx_ef10_update_stats_vf, 4614 .start_stats = efx_port_dummy_op_void, 4615 .pull_stats = efx_port_dummy_op_void, 4616 .stop_stats = efx_port_dummy_op_void, 4617 .set_id_led = efx_mcdi_set_id_led, 4618 .push_irq_moderation = efx_ef10_push_irq_moderation, 4619 .reconfigure_mac = efx_ef10_mac_reconfigure_vf, 4620 .check_mac_fault = efx_mcdi_mac_check_fault, 4621 .reconfigure_port = efx_mcdi_port_reconfigure, 4622 .get_wol = efx_ef10_get_wol_vf, 4623 .set_wol = efx_ef10_set_wol_vf, 4624 .resume_wol = efx_port_dummy_op_void, 4625 .mcdi_request = efx_ef10_mcdi_request, 4626 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4627 .mcdi_read_response = efx_ef10_mcdi_read_response, 4628 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4629 .irq_enable_master = efx_port_dummy_op_void, 4630 .irq_test_generate = efx_ef10_irq_test_generate, 4631 .irq_disable_non_ev = efx_port_dummy_op_void, 4632 .irq_handle_msi = efx_ef10_msi_interrupt, 4633 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4634 .tx_probe = efx_ef10_tx_probe, 4635 .tx_init = efx_ef10_tx_init, 4636 .tx_remove = efx_ef10_tx_remove, 4637 .tx_write = efx_ef10_tx_write, 4638 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config, 4639 .rx_probe = efx_ef10_rx_probe, 4640 .rx_init = efx_ef10_rx_init, 4641 .rx_remove = efx_ef10_rx_remove, 4642 .rx_write = efx_ef10_rx_write, 4643 .rx_defer_refill = efx_ef10_rx_defer_refill, 4644 .ev_probe = efx_ef10_ev_probe, 4645 .ev_init = efx_ef10_ev_init, 4646 .ev_fini = efx_ef10_ev_fini, 4647 .ev_remove = efx_ef10_ev_remove, 4648 .ev_process = efx_ef10_ev_process, 4649 .ev_read_ack = efx_ef10_ev_read_ack, 4650 .ev_test_generate = efx_ef10_ev_test_generate, 4651 .filter_table_probe = efx_ef10_filter_table_probe, 4652 .filter_table_restore = efx_ef10_filter_table_restore, 4653 .filter_table_remove = efx_ef10_filter_table_remove, 4654 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 4655 .filter_insert = efx_ef10_filter_insert, 4656 .filter_remove_safe = efx_ef10_filter_remove_safe, 4657 .filter_get_safe = efx_ef10_filter_get_safe, 4658 .filter_clear_rx = efx_ef10_filter_clear_rx, 4659 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 4660 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 4661 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 4662 #ifdef CONFIG_RFS_ACCEL 4663 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 4664 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 4665 #endif 4666 #ifdef CONFIG_SFC_MTD 4667 .mtd_probe = efx_port_dummy_op_int, 4668 #endif 4669 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4670 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4671 #ifdef CONFIG_SFC_SRIOV 4672 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4673 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4674 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4675 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id, 4676 #endif 4677 .get_mac_address = efx_ef10_get_mac_address_vf, 4678 .set_mac_address = efx_ef10_set_mac_address, 4679 4680 .revision = EFX_REV_HUNT_A0, 4681 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4682 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4683 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4684 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4685 .can_rx_scatter = true, 4686 .always_rx_scatter = true, 4687 .max_interrupt_mode = EFX_INT_MODE_MSIX, 4688 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4689 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4690 NETIF_F_RXHASH | NETIF_F_NTUPLE), 4691 .mcdi_max_ver = 2, 4692 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 4693 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4694 1 << HWTSTAMP_FILTER_ALL, 4695 }; 4696 4697 const struct efx_nic_type efx_hunt_a0_nic_type = { 4698 .is_vf = false, 4699 .mem_bar = EFX_MEM_BAR, 4700 .mem_map_size = efx_ef10_mem_map_size, 4701 .probe = efx_ef10_probe_pf, 4702 .remove = efx_ef10_remove, 4703 .dimension_resources = efx_ef10_dimension_resources, 4704 .init = efx_ef10_init_nic, 4705 .fini = efx_port_dummy_op_void, 4706 .map_reset_reason = efx_ef10_map_reset_reason, 4707 .map_reset_flags = efx_ef10_map_reset_flags, 4708 .reset = efx_ef10_reset, 4709 .probe_port = efx_mcdi_port_probe, 4710 .remove_port = efx_mcdi_port_remove, 4711 .fini_dmaq = efx_ef10_fini_dmaq, 4712 .prepare_flr = efx_ef10_prepare_flr, 4713 .finish_flr = efx_port_dummy_op_void, 4714 .describe_stats = efx_ef10_describe_stats, 4715 .update_stats = efx_ef10_update_stats_pf, 4716 .start_stats = efx_mcdi_mac_start_stats, 4717 .pull_stats = efx_mcdi_mac_pull_stats, 4718 .stop_stats = efx_mcdi_mac_stop_stats, 4719 .set_id_led = efx_mcdi_set_id_led, 4720 .push_irq_moderation = efx_ef10_push_irq_moderation, 4721 .reconfigure_mac = efx_ef10_mac_reconfigure, 4722 .check_mac_fault = efx_mcdi_mac_check_fault, 4723 .reconfigure_port = efx_mcdi_port_reconfigure, 4724 .get_wol = efx_ef10_get_wol, 4725 .set_wol = efx_ef10_set_wol, 4726 .resume_wol = efx_port_dummy_op_void, 4727 .test_chip = efx_ef10_test_chip, 4728 .test_nvram = efx_mcdi_nvram_test_all, 4729 .mcdi_request = efx_ef10_mcdi_request, 4730 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4731 .mcdi_read_response = efx_ef10_mcdi_read_response, 4732 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4733 .irq_enable_master = efx_port_dummy_op_void, 4734 .irq_test_generate = efx_ef10_irq_test_generate, 4735 .irq_disable_non_ev = efx_port_dummy_op_void, 4736 .irq_handle_msi = efx_ef10_msi_interrupt, 4737 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4738 .tx_probe = efx_ef10_tx_probe, 4739 .tx_init = efx_ef10_tx_init, 4740 .tx_remove = efx_ef10_tx_remove, 4741 .tx_write = efx_ef10_tx_write, 4742 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config, 4743 .rx_probe = efx_ef10_rx_probe, 4744 .rx_init = efx_ef10_rx_init, 4745 .rx_remove = efx_ef10_rx_remove, 4746 .rx_write = efx_ef10_rx_write, 4747 .rx_defer_refill = efx_ef10_rx_defer_refill, 4748 .ev_probe = efx_ef10_ev_probe, 4749 .ev_init = efx_ef10_ev_init, 4750 .ev_fini = efx_ef10_ev_fini, 4751 .ev_remove = efx_ef10_ev_remove, 4752 .ev_process = efx_ef10_ev_process, 4753 .ev_read_ack = efx_ef10_ev_read_ack, 4754 .ev_test_generate = efx_ef10_ev_test_generate, 4755 .filter_table_probe = efx_ef10_filter_table_probe, 4756 .filter_table_restore = efx_ef10_filter_table_restore, 4757 .filter_table_remove = efx_ef10_filter_table_remove, 4758 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 4759 .filter_insert = efx_ef10_filter_insert, 4760 .filter_remove_safe = efx_ef10_filter_remove_safe, 4761 .filter_get_safe = efx_ef10_filter_get_safe, 4762 .filter_clear_rx = efx_ef10_filter_clear_rx, 4763 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 4764 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 4765 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 4766 #ifdef CONFIG_RFS_ACCEL 4767 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 4768 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 4769 #endif 4770 #ifdef CONFIG_SFC_MTD 4771 .mtd_probe = efx_ef10_mtd_probe, 4772 .mtd_rename = efx_mcdi_mtd_rename, 4773 .mtd_read = efx_mcdi_mtd_read, 4774 .mtd_erase = efx_mcdi_mtd_erase, 4775 .mtd_write = efx_mcdi_mtd_write, 4776 .mtd_sync = efx_mcdi_mtd_sync, 4777 #endif 4778 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4779 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4780 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4781 #ifdef CONFIG_SFC_SRIOV 4782 .sriov_configure = efx_ef10_sriov_configure, 4783 .sriov_init = efx_ef10_sriov_init, 4784 .sriov_fini = efx_ef10_sriov_fini, 4785 .sriov_wanted = efx_ef10_sriov_wanted, 4786 .sriov_reset = efx_ef10_sriov_reset, 4787 .sriov_flr = efx_ef10_sriov_flr, 4788 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4789 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4790 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4791 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4792 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4793 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4794 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4795 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4796 #endif 4797 .get_mac_address = efx_ef10_get_mac_address_pf, 4798 .set_mac_address = efx_ef10_set_mac_address, 4799 4800 .revision = EFX_REV_HUNT_A0, 4801 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4802 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4803 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4804 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4805 .can_rx_scatter = true, 4806 .always_rx_scatter = true, 4807 .max_interrupt_mode = EFX_INT_MODE_MSIX, 4808 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4809 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4810 NETIF_F_RXHASH | NETIF_F_NTUPLE), 4811 .mcdi_max_ver = 2, 4812 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 4813 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4814 1 << HWTSTAMP_FILTER_ALL, 4815 }; 4816