1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2012-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 #include "net_driver.h" 11 #include "ef10_regs.h" 12 #include "io.h" 13 #include "mcdi.h" 14 #include "mcdi_pcol.h" 15 #include "nic.h" 16 #include "workarounds.h" 17 #include "selftest.h" 18 #include <linux/in.h> 19 #include <linux/jhash.h> 20 #include <linux/wait.h> 21 #include <linux/workqueue.h> 22 23 /* Hardware control for EF10 architecture including 'Huntington'. */ 24 25 #define EFX_EF10_DRVGEN_EV 7 26 enum { 27 EFX_EF10_TEST = 1, 28 EFX_EF10_REFILL, 29 }; 30 31 /* The reserved RSS context value */ 32 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff 33 34 /* The filter table(s) are managed by firmware and we have write-only 35 * access. When removing filters we must identify them to the 36 * firmware by a 64-bit handle, but this is too wide for Linux kernel 37 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to 38 * be able to tell in advance whether a requested insertion will 39 * replace an existing filter. Therefore we maintain a software hash 40 * table, which should be at least as large as the hardware hash 41 * table. 42 * 43 * Huntington has a single 8K filter table shared between all filter 44 * types and both ports. 45 */ 46 #define HUNT_FILTER_TBL_ROWS 8192 47 48 struct efx_ef10_filter_table { 49 /* The RX match field masks supported by this fw & hw, in order of priority */ 50 enum efx_filter_match_flags rx_match_flags[ 51 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM]; 52 unsigned int rx_match_count; 53 54 struct { 55 unsigned long spec; /* pointer to spec plus flag bits */ 56 /* BUSY flag indicates that an update is in progress. AUTO_OLD is 57 * used to mark and sweep MAC filters for the device address lists. 58 */ 59 #define EFX_EF10_FILTER_FLAG_BUSY 1UL 60 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL 61 #define EFX_EF10_FILTER_FLAGS 3UL 62 u64 handle; /* firmware handle */ 63 } *entry; 64 wait_queue_head_t waitq; 65 /* Shadow of net_device address lists, guarded by mac_lock */ 66 #define EFX_EF10_FILTER_DEV_UC_MAX 32 67 #define EFX_EF10_FILTER_DEV_MC_MAX 256 68 struct { 69 u8 addr[ETH_ALEN]; 70 u16 id; 71 } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX], 72 dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX]; 73 int dev_uc_count; /* negative for PROMISC */ 74 int dev_mc_count; /* negative for PROMISC/ALLMULTI */ 75 }; 76 77 /* An arbitrary search limit for the software hash table */ 78 #define EFX_EF10_FILTER_SEARCH_LIMIT 200 79 80 static void efx_ef10_rx_push_rss_config(struct efx_nic *efx); 81 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx); 82 static void efx_ef10_filter_table_remove(struct efx_nic *efx); 83 84 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 85 { 86 efx_dword_t reg; 87 88 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 89 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 90 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 91 } 92 93 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 94 { 95 return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]); 96 } 97 98 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 99 { 100 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN); 101 struct efx_ef10_nic_data *nic_data = efx->nic_data; 102 size_t outlen; 103 int rc; 104 105 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 106 107 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 108 outbuf, sizeof(outbuf), &outlen); 109 if (rc) 110 return rc; 111 if (outlen < sizeof(outbuf)) { 112 netif_err(efx, drv, efx->net_dev, 113 "unable to read datapath firmware capabilities\n"); 114 return -EIO; 115 } 116 117 nic_data->datapath_caps = 118 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 119 120 if (!(nic_data->datapath_caps & 121 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) { 122 netif_err(efx, drv, efx->net_dev, 123 "current firmware does not support TSO\n"); 124 return -ENODEV; 125 } 126 127 if (!(nic_data->datapath_caps & 128 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 129 netif_err(efx, probe, efx->net_dev, 130 "current firmware does not support an RX prefix\n"); 131 return -ENODEV; 132 } 133 134 return 0; 135 } 136 137 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 138 { 139 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 140 int rc; 141 142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 143 outbuf, sizeof(outbuf), NULL); 144 if (rc) 145 return rc; 146 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 147 return rc > 0 ? rc : -ERANGE; 148 } 149 150 static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address) 151 { 152 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 153 size_t outlen; 154 int rc; 155 156 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 157 158 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 159 outbuf, sizeof(outbuf), &outlen); 160 if (rc) 161 return rc; 162 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 163 return -EIO; 164 165 ether_addr_copy(mac_address, 166 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 167 return 0; 168 } 169 170 static int efx_ef10_probe(struct efx_nic *efx) 171 { 172 struct efx_ef10_nic_data *nic_data; 173 int i, rc; 174 175 /* We can have one VI for each 8K region. However, until we 176 * use TX option descriptors we need two TX queues per channel. 177 */ 178 efx->max_channels = 179 min_t(unsigned int, 180 EFX_MAX_CHANNELS, 181 resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) / 182 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES)); 183 BUG_ON(efx->max_channels == 0); 184 185 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 186 if (!nic_data) 187 return -ENOMEM; 188 efx->nic_data = nic_data; 189 190 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 191 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 192 if (rc) 193 goto fail1; 194 195 /* Get the MC's warm boot count. In case it's rebooting right 196 * now, be prepared to retry. 197 */ 198 i = 0; 199 for (;;) { 200 rc = efx_ef10_get_warm_boot_count(efx); 201 if (rc >= 0) 202 break; 203 if (++i == 5) 204 goto fail2; 205 ssleep(1); 206 } 207 nic_data->warm_boot_count = rc; 208 209 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 210 211 /* In case we're recovering from a crash (kexec), we want to 212 * cancel any outstanding request by the previous user of this 213 * function. We send a special message using the least 214 * significant bits of the 'high' (doorbell) register. 215 */ 216 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 217 218 rc = efx_mcdi_init(efx); 219 if (rc) 220 goto fail2; 221 222 /* Reset (most) configuration for this function */ 223 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 224 if (rc) 225 goto fail3; 226 227 /* Enable event logging */ 228 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 229 if (rc) 230 goto fail3; 231 232 rc = efx_ef10_init_datapath_caps(efx); 233 if (rc < 0) 234 goto fail3; 235 236 efx->rx_packet_len_offset = 237 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 238 239 rc = efx_mcdi_port_get_number(efx); 240 if (rc < 0) 241 goto fail3; 242 efx->port_num = rc; 243 244 rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr); 245 if (rc) 246 goto fail3; 247 248 rc = efx_ef10_get_sysclk_freq(efx); 249 if (rc < 0) 250 goto fail3; 251 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */ 252 253 /* Check whether firmware supports bug 35388 workaround */ 254 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true); 255 if (rc == 0) 256 nic_data->workaround_35388 = true; 257 else if (rc != -ENOSYS && rc != -ENOENT) 258 goto fail3; 259 netif_dbg(efx, probe, efx->net_dev, 260 "workaround for bug 35388 is %sabled\n", 261 nic_data->workaround_35388 ? "en" : "dis"); 262 263 rc = efx_mcdi_mon_probe(efx); 264 if (rc) 265 goto fail3; 266 267 efx_ptp_probe(efx, NULL); 268 269 return 0; 270 271 fail3: 272 efx_mcdi_fini(efx); 273 fail2: 274 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 275 fail1: 276 kfree(nic_data); 277 efx->nic_data = NULL; 278 return rc; 279 } 280 281 static int efx_ef10_free_vis(struct efx_nic *efx) 282 { 283 MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0); 284 size_t outlen; 285 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, 286 outbuf, sizeof(outbuf), &outlen); 287 288 /* -EALREADY means nothing to free, so ignore */ 289 if (rc == -EALREADY) 290 rc = 0; 291 if (rc) 292 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, 293 rc); 294 return rc; 295 } 296 297 #ifdef EFX_USE_PIO 298 299 static void efx_ef10_free_piobufs(struct efx_nic *efx) 300 { 301 struct efx_ef10_nic_data *nic_data = efx->nic_data; 302 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 303 unsigned int i; 304 int rc; 305 306 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 307 308 for (i = 0; i < nic_data->n_piobufs; i++) { 309 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 310 nic_data->piobuf_handle[i]); 311 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 312 NULL, 0, NULL); 313 WARN_ON(rc); 314 } 315 316 nic_data->n_piobufs = 0; 317 } 318 319 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 320 { 321 struct efx_ef10_nic_data *nic_data = efx->nic_data; 322 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 323 unsigned int i; 324 size_t outlen; 325 int rc = 0; 326 327 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 328 329 for (i = 0; i < n; i++) { 330 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 331 outbuf, sizeof(outbuf), &outlen); 332 if (rc) 333 break; 334 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 335 rc = -EIO; 336 break; 337 } 338 nic_data->piobuf_handle[i] = 339 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 340 netif_dbg(efx, probe, efx->net_dev, 341 "allocated PIO buffer %u handle %x\n", i, 342 nic_data->piobuf_handle[i]); 343 } 344 345 nic_data->n_piobufs = i; 346 if (rc) 347 efx_ef10_free_piobufs(efx); 348 return rc; 349 } 350 351 static int efx_ef10_link_piobufs(struct efx_nic *efx) 352 { 353 struct efx_ef10_nic_data *nic_data = efx->nic_data; 354 MCDI_DECLARE_BUF(inbuf, 355 max(MC_CMD_LINK_PIOBUF_IN_LEN, 356 MC_CMD_UNLINK_PIOBUF_IN_LEN)); 357 struct efx_channel *channel; 358 struct efx_tx_queue *tx_queue; 359 unsigned int offset, index; 360 int rc; 361 362 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 363 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 364 365 /* Link a buffer to each VI in the write-combining mapping */ 366 for (index = 0; index < nic_data->n_piobufs; ++index) { 367 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 368 nic_data->piobuf_handle[index]); 369 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 370 nic_data->pio_write_vi_base + index); 371 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 372 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 373 NULL, 0, NULL); 374 if (rc) { 375 netif_err(efx, drv, efx->net_dev, 376 "failed to link VI %u to PIO buffer %u (%d)\n", 377 nic_data->pio_write_vi_base + index, index, 378 rc); 379 goto fail; 380 } 381 netif_dbg(efx, probe, efx->net_dev, 382 "linked VI %u to PIO buffer %u\n", 383 nic_data->pio_write_vi_base + index, index); 384 } 385 386 /* Link a buffer to each TX queue */ 387 efx_for_each_channel(channel, efx) { 388 efx_for_each_channel_tx_queue(tx_queue, channel) { 389 /* We assign the PIO buffers to queues in 390 * reverse order to allow for the following 391 * special case. 392 */ 393 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 394 tx_queue->channel->channel - 1) * 395 efx_piobuf_size); 396 index = offset / ER_DZ_TX_PIOBUF_SIZE; 397 offset = offset % ER_DZ_TX_PIOBUF_SIZE; 398 399 /* When the host page size is 4K, the first 400 * host page in the WC mapping may be within 401 * the same VI page as the last TX queue. We 402 * can only link one buffer to each VI. 403 */ 404 if (tx_queue->queue == nic_data->pio_write_vi_base) { 405 BUG_ON(index != 0); 406 rc = 0; 407 } else { 408 MCDI_SET_DWORD(inbuf, 409 LINK_PIOBUF_IN_PIOBUF_HANDLE, 410 nic_data->piobuf_handle[index]); 411 MCDI_SET_DWORD(inbuf, 412 LINK_PIOBUF_IN_TXQ_INSTANCE, 413 tx_queue->queue); 414 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 415 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 416 NULL, 0, NULL); 417 } 418 419 if (rc) { 420 /* This is non-fatal; the TX path just 421 * won't use PIO for this queue 422 */ 423 netif_err(efx, drv, efx->net_dev, 424 "failed to link VI %u to PIO buffer %u (%d)\n", 425 tx_queue->queue, index, rc); 426 tx_queue->piobuf = NULL; 427 } else { 428 tx_queue->piobuf = 429 nic_data->pio_write_base + 430 index * EFX_VI_PAGE_SIZE + offset; 431 tx_queue->piobuf_offset = offset; 432 netif_dbg(efx, probe, efx->net_dev, 433 "linked VI %u to PIO buffer %u offset %x addr %p\n", 434 tx_queue->queue, index, 435 tx_queue->piobuf_offset, 436 tx_queue->piobuf); 437 } 438 } 439 } 440 441 return 0; 442 443 fail: 444 while (index--) { 445 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 446 nic_data->pio_write_vi_base + index); 447 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 448 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 449 NULL, 0, NULL); 450 } 451 return rc; 452 } 453 454 #else /* !EFX_USE_PIO */ 455 456 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 457 { 458 return n == 0 ? 0 : -ENOBUFS; 459 } 460 461 static int efx_ef10_link_piobufs(struct efx_nic *efx) 462 { 463 return 0; 464 } 465 466 static void efx_ef10_free_piobufs(struct efx_nic *efx) 467 { 468 } 469 470 #endif /* EFX_USE_PIO */ 471 472 static void efx_ef10_remove(struct efx_nic *efx) 473 { 474 struct efx_ef10_nic_data *nic_data = efx->nic_data; 475 int rc; 476 477 efx_ptp_remove(efx); 478 479 efx_mcdi_mon_remove(efx); 480 481 efx_ef10_rx_free_indir_table(efx); 482 483 if (nic_data->wc_membase) 484 iounmap(nic_data->wc_membase); 485 486 rc = efx_ef10_free_vis(efx); 487 WARN_ON(rc != 0); 488 489 if (!nic_data->must_restore_piobufs) 490 efx_ef10_free_piobufs(efx); 491 492 efx_mcdi_fini(efx); 493 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 494 kfree(nic_data); 495 } 496 497 static int efx_ef10_alloc_vis(struct efx_nic *efx, 498 unsigned int min_vis, unsigned int max_vis) 499 { 500 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); 501 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); 502 struct efx_ef10_nic_data *nic_data = efx->nic_data; 503 size_t outlen; 504 int rc; 505 506 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); 507 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); 508 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), 509 outbuf, sizeof(outbuf), &outlen); 510 if (rc != 0) 511 return rc; 512 513 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) 514 return -EIO; 515 516 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", 517 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); 518 519 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); 520 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); 521 return 0; 522 } 523 524 /* Note that the failure path of this function does not free 525 * resources, as this will be done by efx_ef10_remove(). 526 */ 527 static int efx_ef10_dimension_resources(struct efx_nic *efx) 528 { 529 struct efx_ef10_nic_data *nic_data = efx->nic_data; 530 unsigned int uc_mem_map_size, wc_mem_map_size; 531 unsigned int min_vis, pio_write_vi_base, max_vis; 532 void __iomem *membase; 533 int rc; 534 535 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); 536 537 #ifdef EFX_USE_PIO 538 /* Try to allocate PIO buffers if wanted and if the full 539 * number of PIO buffers would be sufficient to allocate one 540 * copy-buffer per TX channel. Failure is non-fatal, as there 541 * are only a small number of PIO buffers shared between all 542 * functions of the controller. 543 */ 544 if (efx_piobuf_size != 0 && 545 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 546 efx->n_tx_channels) { 547 unsigned int n_piobufs = 548 DIV_ROUND_UP(efx->n_tx_channels, 549 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size); 550 551 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 552 if (rc) 553 netif_err(efx, probe, efx->net_dev, 554 "failed to allocate PIO buffers (%d)\n", rc); 555 else 556 netif_dbg(efx, probe, efx->net_dev, 557 "allocated %u PIO buffers\n", n_piobufs); 558 } 559 #else 560 nic_data->n_piobufs = 0; 561 #endif 562 563 /* PIO buffers should be mapped with write-combining enabled, 564 * and we want to make single UC and WC mappings rather than 565 * several of each (in fact that's the only option if host 566 * page size is >4K). So we may allocate some extra VIs just 567 * for writing PIO buffers through. 568 * 569 * The UC mapping contains (min_vis - 1) complete VIs and the 570 * first half of the next VI. Then the WC mapping begins with 571 * the second half of this last VI. 572 */ 573 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE + 574 ER_DZ_TX_PIOBUF); 575 if (nic_data->n_piobufs) { 576 /* pio_write_vi_base rounds down to give the number of complete 577 * VIs inside the UC mapping. 578 */ 579 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; 580 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 581 nic_data->n_piobufs) * 582 EFX_VI_PAGE_SIZE) - 583 uc_mem_map_size); 584 max_vis = pio_write_vi_base + nic_data->n_piobufs; 585 } else { 586 pio_write_vi_base = 0; 587 wc_mem_map_size = 0; 588 max_vis = min_vis; 589 } 590 591 /* In case the last attached driver failed to free VIs, do it now */ 592 rc = efx_ef10_free_vis(efx); 593 if (rc != 0) 594 return rc; 595 596 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 597 if (rc != 0) 598 return rc; 599 600 /* If we didn't get enough VIs to map all the PIO buffers, free the 601 * PIO buffers 602 */ 603 if (nic_data->n_piobufs && 604 nic_data->n_allocated_vis < 605 pio_write_vi_base + nic_data->n_piobufs) { 606 netif_dbg(efx, probe, efx->net_dev, 607 "%u VIs are not sufficient to map %u PIO buffers\n", 608 nic_data->n_allocated_vis, nic_data->n_piobufs); 609 efx_ef10_free_piobufs(efx); 610 } 611 612 /* Shrink the original UC mapping of the memory BAR */ 613 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); 614 if (!membase) { 615 netif_err(efx, probe, efx->net_dev, 616 "could not shrink memory BAR to %x\n", 617 uc_mem_map_size); 618 return -ENOMEM; 619 } 620 iounmap(efx->membase); 621 efx->membase = membase; 622 623 /* Set up the WC mapping if needed */ 624 if (wc_mem_map_size) { 625 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 626 uc_mem_map_size, 627 wc_mem_map_size); 628 if (!nic_data->wc_membase) { 629 netif_err(efx, probe, efx->net_dev, 630 "could not allocate WC mapping of size %x\n", 631 wc_mem_map_size); 632 return -ENOMEM; 633 } 634 nic_data->pio_write_vi_base = pio_write_vi_base; 635 nic_data->pio_write_base = 636 nic_data->wc_membase + 637 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF - 638 uc_mem_map_size); 639 640 rc = efx_ef10_link_piobufs(efx); 641 if (rc) 642 efx_ef10_free_piobufs(efx); 643 } 644 645 netif_dbg(efx, probe, efx->net_dev, 646 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 647 &efx->membase_phys, efx->membase, uc_mem_map_size, 648 nic_data->wc_membase, wc_mem_map_size); 649 650 return 0; 651 } 652 653 static int efx_ef10_init_nic(struct efx_nic *efx) 654 { 655 struct efx_ef10_nic_data *nic_data = efx->nic_data; 656 int rc; 657 658 if (nic_data->must_check_datapath_caps) { 659 rc = efx_ef10_init_datapath_caps(efx); 660 if (rc) 661 return rc; 662 nic_data->must_check_datapath_caps = false; 663 } 664 665 if (nic_data->must_realloc_vis) { 666 /* We cannot let the number of VIs change now */ 667 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 668 nic_data->n_allocated_vis); 669 if (rc) 670 return rc; 671 nic_data->must_realloc_vis = false; 672 } 673 674 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 675 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 676 if (rc == 0) { 677 rc = efx_ef10_link_piobufs(efx); 678 if (rc) 679 efx_ef10_free_piobufs(efx); 680 } 681 682 /* Log an error on failure, but this is non-fatal */ 683 if (rc) 684 netif_err(efx, drv, efx->net_dev, 685 "failed to restore PIO buffers (%d)\n", rc); 686 nic_data->must_restore_piobufs = false; 687 } 688 689 efx_ef10_rx_push_rss_config(efx); 690 return 0; 691 } 692 693 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx) 694 { 695 struct efx_ef10_nic_data *nic_data = efx->nic_data; 696 697 /* All our allocations have been reset */ 698 nic_data->must_realloc_vis = true; 699 nic_data->must_restore_filters = true; 700 nic_data->must_restore_piobufs = true; 701 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 702 } 703 704 static int efx_ef10_map_reset_flags(u32 *flags) 705 { 706 enum { 707 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 708 ETH_RESET_SHARED_SHIFT), 709 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 710 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 711 ETH_RESET_PHY | ETH_RESET_MGMT) << 712 ETH_RESET_SHARED_SHIFT) 713 }; 714 715 /* We assume for now that our PCI function is permitted to 716 * reset everything. 717 */ 718 719 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 720 *flags &= ~EF10_RESET_MC; 721 return RESET_TYPE_WORLD; 722 } 723 724 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 725 *flags &= ~EF10_RESET_PORT; 726 return RESET_TYPE_ALL; 727 } 728 729 /* no invisible reset implemented */ 730 731 return -EINVAL; 732 } 733 734 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 735 { 736 int rc = efx_mcdi_reset(efx, reset_type); 737 738 /* If it was a port reset, trigger reallocation of MC resources. 739 * Note that on an MC reset nothing needs to be done now because we'll 740 * detect the MC reset later and handle it then. 741 */ 742 if (reset_type == RESET_TYPE_ALL && !rc) 743 efx_ef10_reset_mc_allocations(efx); 744 return rc; 745 } 746 747 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 748 [EF10_STAT_ ## ext_name] = \ 749 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 750 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 751 [EF10_STAT_ ## int_name] = \ 752 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 753 #define EF10_OTHER_STAT(ext_name) \ 754 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 755 756 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 757 EF10_DMA_STAT(tx_bytes, TX_BYTES), 758 EF10_DMA_STAT(tx_packets, TX_PKTS), 759 EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS), 760 EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS), 761 EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS), 762 EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS), 763 EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS), 764 EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS), 765 EF10_DMA_STAT(tx_64, TX_64_PKTS), 766 EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS), 767 EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS), 768 EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS), 769 EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS), 770 EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 771 EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 772 EF10_DMA_STAT(rx_bytes, RX_BYTES), 773 EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES), 774 EF10_OTHER_STAT(rx_good_bytes), 775 EF10_OTHER_STAT(rx_bad_bytes), 776 EF10_DMA_STAT(rx_packets, RX_PKTS), 777 EF10_DMA_STAT(rx_good, RX_GOOD_PKTS), 778 EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS), 779 EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS), 780 EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS), 781 EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS), 782 EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS), 783 EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS), 784 EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS), 785 EF10_DMA_STAT(rx_64, RX_64_PKTS), 786 EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS), 787 EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS), 788 EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS), 789 EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS), 790 EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 791 EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 792 EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS), 793 EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS), 794 EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS), 795 EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS), 796 EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS), 797 EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS), 798 EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 799 EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 800 EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 801 EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 802 EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB), 803 EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB), 804 EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING), 805 EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 806 EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 807 EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 808 EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS), 809 EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS), 810 }; 811 812 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \ 813 (1ULL << EF10_STAT_tx_packets) | \ 814 (1ULL << EF10_STAT_tx_pause) | \ 815 (1ULL << EF10_STAT_tx_unicast) | \ 816 (1ULL << EF10_STAT_tx_multicast) | \ 817 (1ULL << EF10_STAT_tx_broadcast) | \ 818 (1ULL << EF10_STAT_rx_bytes) | \ 819 (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \ 820 (1ULL << EF10_STAT_rx_good_bytes) | \ 821 (1ULL << EF10_STAT_rx_bad_bytes) | \ 822 (1ULL << EF10_STAT_rx_packets) | \ 823 (1ULL << EF10_STAT_rx_good) | \ 824 (1ULL << EF10_STAT_rx_bad) | \ 825 (1ULL << EF10_STAT_rx_pause) | \ 826 (1ULL << EF10_STAT_rx_control) | \ 827 (1ULL << EF10_STAT_rx_unicast) | \ 828 (1ULL << EF10_STAT_rx_multicast) | \ 829 (1ULL << EF10_STAT_rx_broadcast) | \ 830 (1ULL << EF10_STAT_rx_lt64) | \ 831 (1ULL << EF10_STAT_rx_64) | \ 832 (1ULL << EF10_STAT_rx_65_to_127) | \ 833 (1ULL << EF10_STAT_rx_128_to_255) | \ 834 (1ULL << EF10_STAT_rx_256_to_511) | \ 835 (1ULL << EF10_STAT_rx_512_to_1023) | \ 836 (1ULL << EF10_STAT_rx_1024_to_15xx) | \ 837 (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \ 838 (1ULL << EF10_STAT_rx_gtjumbo) | \ 839 (1ULL << EF10_STAT_rx_bad_gtjumbo) | \ 840 (1ULL << EF10_STAT_rx_overflow) | \ 841 (1ULL << EF10_STAT_rx_nodesc_drops)) 842 843 /* These statistics are only provided by the 10G MAC. For a 10G/40G 844 * switchable port we do not expose these because they might not 845 * include all the packets they should. 846 */ 847 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \ 848 (1ULL << EF10_STAT_tx_lt64) | \ 849 (1ULL << EF10_STAT_tx_64) | \ 850 (1ULL << EF10_STAT_tx_65_to_127) | \ 851 (1ULL << EF10_STAT_tx_128_to_255) | \ 852 (1ULL << EF10_STAT_tx_256_to_511) | \ 853 (1ULL << EF10_STAT_tx_512_to_1023) | \ 854 (1ULL << EF10_STAT_tx_1024_to_15xx) | \ 855 (1ULL << EF10_STAT_tx_15xx_to_jumbo)) 856 857 /* These statistics are only provided by the 40G MAC. For a 10G/40G 858 * switchable port we do expose these because the errors will otherwise 859 * be silent. 860 */ 861 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \ 862 (1ULL << EF10_STAT_rx_length_error)) 863 864 /* These statistics are only provided if the firmware supports the 865 * capability PM_AND_RXDP_COUNTERS. 866 */ 867 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 868 (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \ 869 (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \ 870 (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \ 871 (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \ 872 (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \ 873 (1ULL << EF10_STAT_rx_pm_discard_qbb) | \ 874 (1ULL << EF10_STAT_rx_pm_discard_mapping) | \ 875 (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \ 876 (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \ 877 (1ULL << EF10_STAT_rx_dp_streaming_packets) | \ 878 (1ULL << EF10_STAT_rx_dp_hlb_fetch) | \ 879 (1ULL << EF10_STAT_rx_dp_hlb_wait)) 880 881 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 882 { 883 u64 raw_mask = HUNT_COMMON_STAT_MASK; 884 u32 port_caps = efx_mcdi_phy_get_caps(efx); 885 struct efx_ef10_nic_data *nic_data = efx->nic_data; 886 887 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) 888 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 889 else 890 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 891 892 if (nic_data->datapath_caps & 893 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 894 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 895 896 return raw_mask; 897 } 898 899 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 900 { 901 u64 raw_mask = efx_ef10_raw_stat_mask(efx); 902 903 #if BITS_PER_LONG == 64 904 mask[0] = raw_mask; 905 #else 906 mask[0] = raw_mask & 0xffffffff; 907 mask[1] = raw_mask >> 32; 908 #endif 909 } 910 911 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 912 { 913 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 914 915 efx_ef10_get_stat_mask(efx, mask); 916 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 917 mask, names); 918 } 919 920 static int efx_ef10_try_update_nic_stats(struct efx_nic *efx) 921 { 922 struct efx_ef10_nic_data *nic_data = efx->nic_data; 923 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 924 __le64 generation_start, generation_end; 925 u64 *stats = nic_data->stats; 926 __le64 *dma_stats; 927 928 efx_ef10_get_stat_mask(efx, mask); 929 930 dma_stats = efx->stats_buffer.addr; 931 nic_data = efx->nic_data; 932 933 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 934 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 935 return 0; 936 rmb(); 937 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 938 stats, efx->stats_buffer.addr, false); 939 rmb(); 940 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 941 if (generation_end != generation_start) 942 return -EAGAIN; 943 944 /* Update derived statistics */ 945 efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]); 946 stats[EF10_STAT_rx_good_bytes] = 947 stats[EF10_STAT_rx_bytes] - 948 stats[EF10_STAT_rx_bytes_minus_good_bytes]; 949 efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes], 950 stats[EF10_STAT_rx_bytes_minus_good_bytes]); 951 952 return 0; 953 } 954 955 956 static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats, 957 struct rtnl_link_stats64 *core_stats) 958 { 959 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 960 struct efx_ef10_nic_data *nic_data = efx->nic_data; 961 u64 *stats = nic_data->stats; 962 size_t stats_count = 0, index; 963 int retry; 964 965 efx_ef10_get_stat_mask(efx, mask); 966 967 /* If we're unlucky enough to read statistics during the DMA, wait 968 * up to 10ms for it to finish (typically takes <500us) 969 */ 970 for (retry = 0; retry < 100; ++retry) { 971 if (efx_ef10_try_update_nic_stats(efx) == 0) 972 break; 973 udelay(100); 974 } 975 976 if (full_stats) { 977 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 978 if (efx_ef10_stat_desc[index].name) { 979 *full_stats++ = stats[index]; 980 ++stats_count; 981 } 982 } 983 } 984 985 if (core_stats) { 986 core_stats->rx_packets = stats[EF10_STAT_rx_packets]; 987 core_stats->tx_packets = stats[EF10_STAT_tx_packets]; 988 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes]; 989 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes]; 990 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops]; 991 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 992 core_stats->rx_length_errors = 993 stats[EF10_STAT_rx_gtjumbo] + 994 stats[EF10_STAT_rx_length_error]; 995 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 996 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error]; 997 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 998 core_stats->rx_errors = (core_stats->rx_length_errors + 999 core_stats->rx_crc_errors + 1000 core_stats->rx_frame_errors); 1001 } 1002 1003 return stats_count; 1004 } 1005 1006 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1007 { 1008 struct efx_nic *efx = channel->efx; 1009 unsigned int mode, value; 1010 efx_dword_t timer_cmd; 1011 1012 if (channel->irq_moderation) { 1013 mode = 3; 1014 value = channel->irq_moderation - 1; 1015 } else { 1016 mode = 0; 1017 value = 0; 1018 } 1019 1020 if (EFX_EF10_WORKAROUND_35388(efx)) { 1021 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1022 EFE_DD_EVQ_IND_TIMER_FLAGS, 1023 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1024 ERF_DD_EVQ_IND_TIMER_VAL, value); 1025 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1026 channel->channel); 1027 } else { 1028 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1029 ERF_DZ_TC_TIMER_VAL, value); 1030 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1031 channel->channel); 1032 } 1033 } 1034 1035 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1036 { 1037 wol->supported = 0; 1038 wol->wolopts = 0; 1039 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1040 } 1041 1042 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 1043 { 1044 if (type != 0) 1045 return -EINVAL; 1046 return 0; 1047 } 1048 1049 static void efx_ef10_mcdi_request(struct efx_nic *efx, 1050 const efx_dword_t *hdr, size_t hdr_len, 1051 const efx_dword_t *sdu, size_t sdu_len) 1052 { 1053 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1054 u8 *pdu = nic_data->mcdi_buf.addr; 1055 1056 memcpy(pdu, hdr, hdr_len); 1057 memcpy(pdu + hdr_len, sdu, sdu_len); 1058 wmb(); 1059 1060 /* The hardware provides 'low' and 'high' (doorbell) registers 1061 * for passing the 64-bit address of an MCDI request to 1062 * firmware. However the dwords are swapped by firmware. The 1063 * least significant bits of the doorbell are then 0 for all 1064 * MCDI requests due to alignment. 1065 */ 1066 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 1067 ER_DZ_MC_DB_LWRD); 1068 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 1069 ER_DZ_MC_DB_HWRD); 1070 } 1071 1072 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 1073 { 1074 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1075 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 1076 1077 rmb(); 1078 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 1079 } 1080 1081 static void 1082 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 1083 size_t offset, size_t outlen) 1084 { 1085 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1086 const u8 *pdu = nic_data->mcdi_buf.addr; 1087 1088 memcpy(outbuf, pdu + offset, outlen); 1089 } 1090 1091 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 1092 { 1093 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1094 int rc; 1095 1096 rc = efx_ef10_get_warm_boot_count(efx); 1097 if (rc < 0) { 1098 /* The firmware is presumably in the process of 1099 * rebooting. However, we are supposed to report each 1100 * reboot just once, so we must only do that once we 1101 * can read and store the updated warm boot count. 1102 */ 1103 return 0; 1104 } 1105 1106 if (rc == nic_data->warm_boot_count) 1107 return 0; 1108 1109 nic_data->warm_boot_count = rc; 1110 1111 /* All our allocations have been reset */ 1112 efx_ef10_reset_mc_allocations(efx); 1113 1114 /* The datapath firmware might have been changed */ 1115 nic_data->must_check_datapath_caps = true; 1116 1117 /* MAC statistics have been cleared on the NIC; clear the local 1118 * statistic that we update with efx_update_diff_stat(). 1119 */ 1120 nic_data->stats[EF10_STAT_rx_bad_bytes] = 0; 1121 1122 return -EIO; 1123 } 1124 1125 /* Handle an MSI interrupt 1126 * 1127 * Handle an MSI hardware interrupt. This routine schedules event 1128 * queue processing. No interrupt acknowledgement cycle is necessary. 1129 * Also, we never need to check that the interrupt is for us, since 1130 * MSI interrupts cannot be shared. 1131 */ 1132 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 1133 { 1134 struct efx_msi_context *context = dev_id; 1135 struct efx_nic *efx = context->efx; 1136 1137 netif_vdbg(efx, intr, efx->net_dev, 1138 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 1139 1140 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) { 1141 /* Note test interrupts */ 1142 if (context->index == efx->irq_level) 1143 efx->last_irq_cpu = raw_smp_processor_id(); 1144 1145 /* Schedule processing of the channel */ 1146 efx_schedule_channel_irq(efx->channel[context->index]); 1147 } 1148 1149 return IRQ_HANDLED; 1150 } 1151 1152 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 1153 { 1154 struct efx_nic *efx = dev_id; 1155 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); 1156 struct efx_channel *channel; 1157 efx_dword_t reg; 1158 u32 queues; 1159 1160 /* Read the ISR which also ACKs the interrupts */ 1161 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 1162 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 1163 1164 if (queues == 0) 1165 return IRQ_NONE; 1166 1167 if (likely(soft_enabled)) { 1168 /* Note test interrupts */ 1169 if (queues & (1U << efx->irq_level)) 1170 efx->last_irq_cpu = raw_smp_processor_id(); 1171 1172 efx_for_each_channel(channel, efx) { 1173 if (queues & 1) 1174 efx_schedule_channel_irq(channel); 1175 queues >>= 1; 1176 } 1177 } 1178 1179 netif_vdbg(efx, intr, efx->net_dev, 1180 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 1181 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 1182 1183 return IRQ_HANDLED; 1184 } 1185 1186 static void efx_ef10_irq_test_generate(struct efx_nic *efx) 1187 { 1188 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 1189 1190 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 1191 1192 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 1193 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 1194 inbuf, sizeof(inbuf), NULL, 0, NULL); 1195 } 1196 1197 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 1198 { 1199 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 1200 (tx_queue->ptr_mask + 1) * 1201 sizeof(efx_qword_t), 1202 GFP_KERNEL); 1203 } 1204 1205 /* This writes to the TX_DESC_WPTR and also pushes data */ 1206 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 1207 const efx_qword_t *txd) 1208 { 1209 unsigned int write_ptr; 1210 efx_oword_t reg; 1211 1212 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1213 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 1214 reg.qword[0] = *txd; 1215 efx_writeo_page(tx_queue->efx, ®, 1216 ER_DZ_TX_DESC_UPD, tx_queue->queue); 1217 } 1218 1219 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 1220 { 1221 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 1222 EFX_BUF_SIZE)); 1223 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN); 1224 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 1225 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; 1226 struct efx_channel *channel = tx_queue->channel; 1227 struct efx_nic *efx = tx_queue->efx; 1228 size_t inlen, outlen; 1229 dma_addr_t dma_addr; 1230 efx_qword_t *txd; 1231 int rc; 1232 int i; 1233 1234 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); 1235 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); 1236 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); 1237 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); 1238 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS, 1239 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, 1240 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload); 1241 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); 1242 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1243 1244 dma_addr = tx_queue->txd.buf.dma_addr; 1245 1246 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", 1247 tx_queue->queue, entries, (u64)dma_addr); 1248 1249 for (i = 0; i < entries; ++i) { 1250 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); 1251 dma_addr += EFX_BUF_SIZE; 1252 } 1253 1254 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); 1255 1256 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen, 1257 outbuf, sizeof(outbuf), &outlen); 1258 if (rc) 1259 goto fail; 1260 1261 /* A previous user of this TX queue might have set us up the 1262 * bomb by writing a descriptor to the TX push collector but 1263 * not the doorbell. (Each collector belongs to a port, not a 1264 * queue or function, so cannot easily be reset.) We must 1265 * attempt to push a no-op descriptor in its place. 1266 */ 1267 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 1268 tx_queue->insert_count = 1; 1269 txd = efx_tx_desc(tx_queue, 0); 1270 EFX_POPULATE_QWORD_4(*txd, 1271 ESF_DZ_TX_DESC_IS_OPT, true, 1272 ESF_DZ_TX_OPTION_TYPE, 1273 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 1274 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 1275 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload); 1276 tx_queue->write_count = 1; 1277 wmb(); 1278 efx_ef10_push_tx_desc(tx_queue, txd); 1279 1280 return; 1281 1282 fail: 1283 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 1284 tx_queue->queue); 1285 } 1286 1287 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue) 1288 { 1289 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); 1290 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN); 1291 struct efx_nic *efx = tx_queue->efx; 1292 size_t outlen; 1293 int rc; 1294 1295 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, 1296 tx_queue->queue); 1297 1298 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), 1299 outbuf, sizeof(outbuf), &outlen); 1300 1301 if (rc && rc != -EALREADY) 1302 goto fail; 1303 1304 return; 1305 1306 fail: 1307 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, 1308 outbuf, outlen, rc); 1309 } 1310 1311 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue) 1312 { 1313 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); 1314 } 1315 1316 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 1317 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 1318 { 1319 unsigned int write_ptr; 1320 efx_dword_t reg; 1321 1322 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1323 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 1324 efx_writed_page(tx_queue->efx, ®, 1325 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 1326 } 1327 1328 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 1329 { 1330 unsigned int old_write_count = tx_queue->write_count; 1331 struct efx_tx_buffer *buffer; 1332 unsigned int write_ptr; 1333 efx_qword_t *txd; 1334 1335 BUG_ON(tx_queue->write_count == tx_queue->insert_count); 1336 1337 do { 1338 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1339 buffer = &tx_queue->buffer[write_ptr]; 1340 txd = efx_tx_desc(tx_queue, write_ptr); 1341 ++tx_queue->write_count; 1342 1343 /* Create TX descriptor ring entry */ 1344 if (buffer->flags & EFX_TX_BUF_OPTION) { 1345 *txd = buffer->option; 1346 } else { 1347 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 1348 EFX_POPULATE_QWORD_3( 1349 *txd, 1350 ESF_DZ_TX_KER_CONT, 1351 buffer->flags & EFX_TX_BUF_CONT, 1352 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 1353 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 1354 } 1355 } while (tx_queue->write_count != tx_queue->insert_count); 1356 1357 wmb(); /* Ensure descriptors are written before they are fetched */ 1358 1359 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 1360 txd = efx_tx_desc(tx_queue, 1361 old_write_count & tx_queue->ptr_mask); 1362 efx_ef10_push_tx_desc(tx_queue, txd); 1363 ++tx_queue->pushes; 1364 } else { 1365 efx_ef10_notify_tx_desc(tx_queue); 1366 } 1367 } 1368 1369 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context) 1370 { 1371 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN); 1372 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN); 1373 size_t outlen; 1374 int rc; 1375 1376 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, 1377 EVB_PORT_ID_ASSIGNED); 1378 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, 1379 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE); 1380 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, 1381 EFX_MAX_CHANNELS); 1382 1383 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf), 1384 outbuf, sizeof(outbuf), &outlen); 1385 if (rc != 0) 1386 return rc; 1387 1388 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) 1389 return -EIO; 1390 1391 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); 1392 1393 return 0; 1394 } 1395 1396 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context) 1397 { 1398 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN); 1399 int rc; 1400 1401 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, 1402 context); 1403 1404 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf), 1405 NULL, 0, NULL); 1406 WARN_ON(rc != 0); 1407 } 1408 1409 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context) 1410 { 1411 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN); 1412 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN); 1413 int i, rc; 1414 1415 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, 1416 context); 1417 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != 1418 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN); 1419 1420 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i) 1421 MCDI_PTR(tablebuf, 1422 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] = 1423 (u8) efx->rx_indir_table[i]; 1424 1425 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf, 1426 sizeof(tablebuf), NULL, 0, NULL); 1427 if (rc != 0) 1428 return rc; 1429 1430 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, 1431 context); 1432 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) != 1433 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); 1434 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i) 1435 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = 1436 efx->rx_hash_key[i]; 1437 1438 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf, 1439 sizeof(keybuf), NULL, 0, NULL); 1440 } 1441 1442 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx) 1443 { 1444 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1445 1446 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 1447 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context); 1448 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 1449 } 1450 1451 static void efx_ef10_rx_push_rss_config(struct efx_nic *efx) 1452 { 1453 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1454 int rc; 1455 1456 netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n"); 1457 1458 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) { 1459 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context); 1460 if (rc != 0) 1461 goto fail; 1462 } 1463 1464 rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context); 1465 if (rc != 0) 1466 goto fail; 1467 1468 return; 1469 1470 fail: 1471 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 1472 } 1473 1474 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue) 1475 { 1476 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, 1477 (rx_queue->ptr_mask + 1) * 1478 sizeof(efx_qword_t), 1479 GFP_KERNEL); 1480 } 1481 1482 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue) 1483 { 1484 MCDI_DECLARE_BUF(inbuf, 1485 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 1486 EFX_BUF_SIZE)); 1487 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN); 1488 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 1489 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; 1490 struct efx_nic *efx = rx_queue->efx; 1491 size_t inlen, outlen; 1492 dma_addr_t dma_addr; 1493 int rc; 1494 int i; 1495 1496 rx_queue->scatter_n = 0; 1497 rx_queue->scatter_len = 0; 1498 1499 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); 1500 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); 1501 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); 1502 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, 1503 efx_rx_queue_index(rx_queue)); 1504 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, 1505 INIT_RXQ_IN_FLAG_PREFIX, 1, 1506 INIT_RXQ_IN_FLAG_TIMESTAMP, 1); 1507 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); 1508 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1509 1510 dma_addr = rx_queue->rxd.buf.dma_addr; 1511 1512 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", 1513 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); 1514 1515 for (i = 0; i < entries; ++i) { 1516 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); 1517 dma_addr += EFX_BUF_SIZE; 1518 } 1519 1520 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); 1521 1522 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, 1523 outbuf, sizeof(outbuf), &outlen); 1524 if (rc) 1525 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", 1526 efx_rx_queue_index(rx_queue)); 1527 } 1528 1529 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue) 1530 { 1531 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); 1532 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN); 1533 struct efx_nic *efx = rx_queue->efx; 1534 size_t outlen; 1535 int rc; 1536 1537 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, 1538 efx_rx_queue_index(rx_queue)); 1539 1540 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), 1541 outbuf, sizeof(outbuf), &outlen); 1542 1543 if (rc && rc != -EALREADY) 1544 goto fail; 1545 1546 return; 1547 1548 fail: 1549 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, 1550 outbuf, outlen, rc); 1551 } 1552 1553 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue) 1554 { 1555 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); 1556 } 1557 1558 /* This creates an entry in the RX descriptor queue */ 1559 static inline void 1560 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 1561 { 1562 struct efx_rx_buffer *rx_buf; 1563 efx_qword_t *rxd; 1564 1565 rxd = efx_rx_desc(rx_queue, index); 1566 rx_buf = efx_rx_buffer(rx_queue, index); 1567 EFX_POPULATE_QWORD_2(*rxd, 1568 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 1569 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 1570 } 1571 1572 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 1573 { 1574 struct efx_nic *efx = rx_queue->efx; 1575 unsigned int write_count; 1576 efx_dword_t reg; 1577 1578 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 1579 write_count = rx_queue->added_count & ~7; 1580 if (rx_queue->notified_count == write_count) 1581 return; 1582 1583 do 1584 efx_ef10_build_rx_desc( 1585 rx_queue, 1586 rx_queue->notified_count & rx_queue->ptr_mask); 1587 while (++rx_queue->notified_count != write_count); 1588 1589 wmb(); 1590 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 1591 write_count & rx_queue->ptr_mask); 1592 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 1593 efx_rx_queue_index(rx_queue)); 1594 } 1595 1596 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 1597 1598 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 1599 { 1600 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 1601 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 1602 efx_qword_t event; 1603 1604 EFX_POPULATE_QWORD_2(event, 1605 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 1606 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 1607 1608 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 1609 1610 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 1611 * already swapped the data to little-endian order. 1612 */ 1613 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 1614 sizeof(efx_qword_t)); 1615 1616 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 1617 inbuf, sizeof(inbuf), 0, 1618 efx_ef10_rx_defer_refill_complete, 0); 1619 } 1620 1621 static void 1622 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 1623 int rc, efx_dword_t *outbuf, 1624 size_t outlen_actual) 1625 { 1626 /* nothing to do */ 1627 } 1628 1629 static int efx_ef10_ev_probe(struct efx_channel *channel) 1630 { 1631 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 1632 (channel->eventq_mask + 1) * 1633 sizeof(efx_qword_t), 1634 GFP_KERNEL); 1635 } 1636 1637 static int efx_ef10_ev_init(struct efx_channel *channel) 1638 { 1639 MCDI_DECLARE_BUF(inbuf, 1640 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / 1641 EFX_BUF_SIZE)); 1642 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN); 1643 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; 1644 struct efx_nic *efx = channel->efx; 1645 struct efx_ef10_nic_data *nic_data; 1646 bool supports_rx_merge; 1647 size_t inlen, outlen; 1648 dma_addr_t dma_addr; 1649 int rc; 1650 int i; 1651 1652 nic_data = efx->nic_data; 1653 supports_rx_merge = 1654 !!(nic_data->datapath_caps & 1655 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 1656 1657 /* Fill event queue with all ones (i.e. empty events) */ 1658 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); 1659 1660 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); 1661 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); 1662 /* INIT_EVQ expects index in vector table, not absolute */ 1663 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); 1664 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, 1665 INIT_EVQ_IN_FLAG_INTERRUPTING, 1, 1666 INIT_EVQ_IN_FLAG_RX_MERGE, 1, 1667 INIT_EVQ_IN_FLAG_TX_MERGE, 1, 1668 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge); 1669 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, 1670 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); 1671 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); 1672 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); 1673 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, 1674 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); 1675 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); 1676 1677 dma_addr = channel->eventq.buf.dma_addr; 1678 for (i = 0; i < entries; ++i) { 1679 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); 1680 dma_addr += EFX_BUF_SIZE; 1681 } 1682 1683 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); 1684 1685 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, 1686 outbuf, sizeof(outbuf), &outlen); 1687 /* IRQ return is ignored */ 1688 return rc; 1689 } 1690 1691 static void efx_ef10_ev_fini(struct efx_channel *channel) 1692 { 1693 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); 1694 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN); 1695 struct efx_nic *efx = channel->efx; 1696 size_t outlen; 1697 int rc; 1698 1699 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); 1700 1701 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), 1702 outbuf, sizeof(outbuf), &outlen); 1703 1704 if (rc && rc != -EALREADY) 1705 goto fail; 1706 1707 return; 1708 1709 fail: 1710 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, 1711 outbuf, outlen, rc); 1712 } 1713 1714 static void efx_ef10_ev_remove(struct efx_channel *channel) 1715 { 1716 efx_nic_free_buffer(channel->efx, &channel->eventq.buf); 1717 } 1718 1719 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 1720 unsigned int rx_queue_label) 1721 { 1722 struct efx_nic *efx = rx_queue->efx; 1723 1724 netif_info(efx, hw, efx->net_dev, 1725 "rx event arrived on queue %d labeled as queue %u\n", 1726 efx_rx_queue_index(rx_queue), rx_queue_label); 1727 1728 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 1729 } 1730 1731 static void 1732 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 1733 unsigned int actual, unsigned int expected) 1734 { 1735 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 1736 struct efx_nic *efx = rx_queue->efx; 1737 1738 netif_info(efx, hw, efx->net_dev, 1739 "dropped %d events (index=%d expected=%d)\n", 1740 dropped, actual, expected); 1741 1742 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 1743 } 1744 1745 /* partially received RX was aborted. clean up. */ 1746 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 1747 { 1748 unsigned int rx_desc_ptr; 1749 1750 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 1751 "scattered RX aborted (dropping %u buffers)\n", 1752 rx_queue->scatter_n); 1753 1754 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 1755 1756 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 1757 0, EFX_RX_PKT_DISCARD); 1758 1759 rx_queue->removed_count += rx_queue->scatter_n; 1760 rx_queue->scatter_n = 0; 1761 rx_queue->scatter_len = 0; 1762 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 1763 } 1764 1765 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 1766 const efx_qword_t *event) 1767 { 1768 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class; 1769 unsigned int n_descs, n_packets, i; 1770 struct efx_nic *efx = channel->efx; 1771 struct efx_rx_queue *rx_queue; 1772 bool rx_cont; 1773 u16 flags = 0; 1774 1775 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 1776 return 0; 1777 1778 /* Basic packet information */ 1779 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 1780 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 1781 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 1782 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); 1783 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 1784 1785 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 1786 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 1787 EFX_QWORD_FMT "\n", 1788 EFX_QWORD_VAL(*event)); 1789 1790 rx_queue = efx_channel_get_rx_queue(channel); 1791 1792 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 1793 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 1794 1795 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 1796 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 1797 1798 if (n_descs != rx_queue->scatter_n + 1) { 1799 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1800 1801 /* detect rx abort */ 1802 if (unlikely(n_descs == rx_queue->scatter_n)) { 1803 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 1804 netdev_WARN(efx->net_dev, 1805 "invalid RX abort: scatter_n=%u event=" 1806 EFX_QWORD_FMT "\n", 1807 rx_queue->scatter_n, 1808 EFX_QWORD_VAL(*event)); 1809 efx_ef10_handle_rx_abort(rx_queue); 1810 return 0; 1811 } 1812 1813 /* Check that RX completion merging is valid, i.e. 1814 * the current firmware supports it and this is a 1815 * non-scattered packet. 1816 */ 1817 if (!(nic_data->datapath_caps & 1818 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 1819 rx_queue->scatter_n != 0 || rx_cont) { 1820 efx_ef10_handle_rx_bad_lbits( 1821 rx_queue, next_ptr_lbits, 1822 (rx_queue->removed_count + 1823 rx_queue->scatter_n + 1) & 1824 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 1825 return 0; 1826 } 1827 1828 /* Merged completion for multiple non-scattered packets */ 1829 rx_queue->scatter_n = 1; 1830 rx_queue->scatter_len = 0; 1831 n_packets = n_descs; 1832 ++channel->n_rx_merge_events; 1833 channel->n_rx_merge_packets += n_packets; 1834 flags |= EFX_RX_PKT_PREFIX_LEN; 1835 } else { 1836 ++rx_queue->scatter_n; 1837 rx_queue->scatter_len += rx_bytes; 1838 if (rx_cont) 1839 return 0; 1840 n_packets = 1; 1841 } 1842 1843 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR))) 1844 flags |= EFX_RX_PKT_DISCARD; 1845 1846 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) { 1847 channel->n_rx_ip_hdr_chksum_err += n_packets; 1848 } else if (unlikely(EFX_QWORD_FIELD(*event, 1849 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) { 1850 channel->n_rx_tcp_udp_chksum_err += n_packets; 1851 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP || 1852 rx_l4_class == ESE_DZ_L4_CLASS_UDP) { 1853 flags |= EFX_RX_PKT_CSUMMED; 1854 } 1855 1856 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) 1857 flags |= EFX_RX_PKT_TCP; 1858 1859 channel->irq_mod_score += 2 * n_packets; 1860 1861 /* Handle received packet(s) */ 1862 for (i = 0; i < n_packets; i++) { 1863 efx_rx_packet(rx_queue, 1864 rx_queue->removed_count & rx_queue->ptr_mask, 1865 rx_queue->scatter_n, rx_queue->scatter_len, 1866 flags); 1867 rx_queue->removed_count += rx_queue->scatter_n; 1868 } 1869 1870 rx_queue->scatter_n = 0; 1871 rx_queue->scatter_len = 0; 1872 1873 return n_packets; 1874 } 1875 1876 static int 1877 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 1878 { 1879 struct efx_nic *efx = channel->efx; 1880 struct efx_tx_queue *tx_queue; 1881 unsigned int tx_ev_desc_ptr; 1882 unsigned int tx_ev_q_label; 1883 int tx_descs = 0; 1884 1885 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 1886 return 0; 1887 1888 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 1889 return 0; 1890 1891 /* Transmit completion */ 1892 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 1893 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 1894 tx_queue = efx_channel_get_tx_queue(channel, 1895 tx_ev_q_label % EFX_TXQ_TYPES); 1896 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) & 1897 tx_queue->ptr_mask); 1898 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 1899 1900 return tx_descs; 1901 } 1902 1903 static void 1904 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 1905 { 1906 struct efx_nic *efx = channel->efx; 1907 int subcode; 1908 1909 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 1910 1911 switch (subcode) { 1912 case ESE_DZ_DRV_TIMER_EV: 1913 case ESE_DZ_DRV_WAKE_UP_EV: 1914 break; 1915 case ESE_DZ_DRV_START_UP_EV: 1916 /* event queue init complete. ok. */ 1917 break; 1918 default: 1919 netif_err(efx, hw, efx->net_dev, 1920 "channel %d unknown driver event type %d" 1921 " (data " EFX_QWORD_FMT ")\n", 1922 channel->channel, subcode, 1923 EFX_QWORD_VAL(*event)); 1924 1925 } 1926 } 1927 1928 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 1929 efx_qword_t *event) 1930 { 1931 struct efx_nic *efx = channel->efx; 1932 u32 subcode; 1933 1934 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 1935 1936 switch (subcode) { 1937 case EFX_EF10_TEST: 1938 channel->event_test_cpu = raw_smp_processor_id(); 1939 break; 1940 case EFX_EF10_REFILL: 1941 /* The queue must be empty, so we won't receive any rx 1942 * events, so efx_process_channel() won't refill the 1943 * queue. Refill it here 1944 */ 1945 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 1946 break; 1947 default: 1948 netif_err(efx, hw, efx->net_dev, 1949 "channel %d unknown driver event type %u" 1950 " (data " EFX_QWORD_FMT ")\n", 1951 channel->channel, (unsigned) subcode, 1952 EFX_QWORD_VAL(*event)); 1953 } 1954 } 1955 1956 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 1957 { 1958 struct efx_nic *efx = channel->efx; 1959 efx_qword_t event, *p_event; 1960 unsigned int read_ptr; 1961 int ev_code; 1962 int tx_descs = 0; 1963 int spent = 0; 1964 1965 if (quota <= 0) 1966 return spent; 1967 1968 read_ptr = channel->eventq_read_ptr; 1969 1970 for (;;) { 1971 p_event = efx_event(channel, read_ptr); 1972 event = *p_event; 1973 1974 if (!efx_event_present(&event)) 1975 break; 1976 1977 EFX_SET_QWORD(*p_event); 1978 1979 ++read_ptr; 1980 1981 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 1982 1983 netif_vdbg(efx, drv, efx->net_dev, 1984 "processing event on %d " EFX_QWORD_FMT "\n", 1985 channel->channel, EFX_QWORD_VAL(event)); 1986 1987 switch (ev_code) { 1988 case ESE_DZ_EV_CODE_MCDI_EV: 1989 efx_mcdi_process_event(channel, &event); 1990 break; 1991 case ESE_DZ_EV_CODE_RX_EV: 1992 spent += efx_ef10_handle_rx_event(channel, &event); 1993 if (spent >= quota) { 1994 /* XXX can we split a merged event to 1995 * avoid going over-quota? 1996 */ 1997 spent = quota; 1998 goto out; 1999 } 2000 break; 2001 case ESE_DZ_EV_CODE_TX_EV: 2002 tx_descs += efx_ef10_handle_tx_event(channel, &event); 2003 if (tx_descs > efx->txq_entries) { 2004 spent = quota; 2005 goto out; 2006 } else if (++spent == quota) { 2007 goto out; 2008 } 2009 break; 2010 case ESE_DZ_EV_CODE_DRIVER_EV: 2011 efx_ef10_handle_driver_event(channel, &event); 2012 if (++spent == quota) 2013 goto out; 2014 break; 2015 case EFX_EF10_DRVGEN_EV: 2016 efx_ef10_handle_driver_generated_event(channel, &event); 2017 break; 2018 default: 2019 netif_err(efx, hw, efx->net_dev, 2020 "channel %d unknown event type %d" 2021 " (data " EFX_QWORD_FMT ")\n", 2022 channel->channel, ev_code, 2023 EFX_QWORD_VAL(event)); 2024 } 2025 } 2026 2027 out: 2028 channel->eventq_read_ptr = read_ptr; 2029 return spent; 2030 } 2031 2032 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 2033 { 2034 struct efx_nic *efx = channel->efx; 2035 efx_dword_t rptr; 2036 2037 if (EFX_EF10_WORKAROUND_35388(efx)) { 2038 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 2039 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 2040 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 2041 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 2042 2043 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2044 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 2045 ERF_DD_EVQ_IND_RPTR, 2046 (channel->eventq_read_ptr & 2047 channel->eventq_mask) >> 2048 ERF_DD_EVQ_IND_RPTR_WIDTH); 2049 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2050 channel->channel); 2051 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2052 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 2053 ERF_DD_EVQ_IND_RPTR, 2054 channel->eventq_read_ptr & 2055 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 2056 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2057 channel->channel); 2058 } else { 2059 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 2060 channel->eventq_read_ptr & 2061 channel->eventq_mask); 2062 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 2063 } 2064 } 2065 2066 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 2067 { 2068 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2069 struct efx_nic *efx = channel->efx; 2070 efx_qword_t event; 2071 int rc; 2072 2073 EFX_POPULATE_QWORD_2(event, 2074 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2075 ESF_DZ_EV_DATA, EFX_EF10_TEST); 2076 2077 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2078 2079 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2080 * already swapped the data to little-endian order. 2081 */ 2082 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2083 sizeof(efx_qword_t)); 2084 2085 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 2086 NULL, 0, NULL); 2087 if (rc != 0) 2088 goto fail; 2089 2090 return; 2091 2092 fail: 2093 WARN_ON(true); 2094 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 2095 } 2096 2097 void efx_ef10_handle_drain_event(struct efx_nic *efx) 2098 { 2099 if (atomic_dec_and_test(&efx->active_queues)) 2100 wake_up(&efx->flush_wq); 2101 2102 WARN_ON(atomic_read(&efx->active_queues) < 0); 2103 } 2104 2105 static int efx_ef10_fini_dmaq(struct efx_nic *efx) 2106 { 2107 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2108 struct efx_channel *channel; 2109 struct efx_tx_queue *tx_queue; 2110 struct efx_rx_queue *rx_queue; 2111 int pending; 2112 2113 /* If the MC has just rebooted, the TX/RX queues will have already been 2114 * torn down, but efx->active_queues needs to be set to zero. 2115 */ 2116 if (nic_data->must_realloc_vis) { 2117 atomic_set(&efx->active_queues, 0); 2118 return 0; 2119 } 2120 2121 /* Do not attempt to write to the NIC during EEH recovery */ 2122 if (efx->state != STATE_RECOVERY) { 2123 efx_for_each_channel(channel, efx) { 2124 efx_for_each_channel_rx_queue(rx_queue, channel) 2125 efx_ef10_rx_fini(rx_queue); 2126 efx_for_each_channel_tx_queue(tx_queue, channel) 2127 efx_ef10_tx_fini(tx_queue); 2128 } 2129 2130 wait_event_timeout(efx->flush_wq, 2131 atomic_read(&efx->active_queues) == 0, 2132 msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); 2133 pending = atomic_read(&efx->active_queues); 2134 if (pending) { 2135 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", 2136 pending); 2137 return -ETIMEDOUT; 2138 } 2139 } 2140 2141 return 0; 2142 } 2143 2144 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left, 2145 const struct efx_filter_spec *right) 2146 { 2147 if ((left->match_flags ^ right->match_flags) | 2148 ((left->flags ^ right->flags) & 2149 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX))) 2150 return false; 2151 2152 return memcmp(&left->outer_vid, &right->outer_vid, 2153 sizeof(struct efx_filter_spec) - 2154 offsetof(struct efx_filter_spec, outer_vid)) == 0; 2155 } 2156 2157 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec) 2158 { 2159 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3); 2160 return jhash2((const u32 *)&spec->outer_vid, 2161 (sizeof(struct efx_filter_spec) - 2162 offsetof(struct efx_filter_spec, outer_vid)) / 4, 2163 0); 2164 /* XXX should we randomise the initval? */ 2165 } 2166 2167 /* Decide whether a filter should be exclusive or else should allow 2168 * delivery to additional recipients. Currently we decide that 2169 * filters for specific local unicast MAC and IP addresses are 2170 * exclusive. 2171 */ 2172 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec) 2173 { 2174 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC && 2175 !is_multicast_ether_addr(spec->loc_mac)) 2176 return true; 2177 2178 if ((spec->match_flags & 2179 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == 2180 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { 2181 if (spec->ether_type == htons(ETH_P_IP) && 2182 !ipv4_is_multicast(spec->loc_host[0])) 2183 return true; 2184 if (spec->ether_type == htons(ETH_P_IPV6) && 2185 ((const u8 *)spec->loc_host)[0] != 0xff) 2186 return true; 2187 } 2188 2189 return false; 2190 } 2191 2192 static struct efx_filter_spec * 2193 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table, 2194 unsigned int filter_idx) 2195 { 2196 return (struct efx_filter_spec *)(table->entry[filter_idx].spec & 2197 ~EFX_EF10_FILTER_FLAGS); 2198 } 2199 2200 static unsigned int 2201 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table, 2202 unsigned int filter_idx) 2203 { 2204 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS; 2205 } 2206 2207 static void 2208 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table, 2209 unsigned int filter_idx, 2210 const struct efx_filter_spec *spec, 2211 unsigned int flags) 2212 { 2213 table->entry[filter_idx].spec = (unsigned long)spec | flags; 2214 } 2215 2216 static void efx_ef10_filter_push_prep(struct efx_nic *efx, 2217 const struct efx_filter_spec *spec, 2218 efx_dword_t *inbuf, u64 handle, 2219 bool replacing) 2220 { 2221 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2222 2223 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN); 2224 2225 if (replacing) { 2226 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2227 MC_CMD_FILTER_OP_IN_OP_REPLACE); 2228 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle); 2229 } else { 2230 u32 match_fields = 0; 2231 2232 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2233 efx_ef10_filter_is_exclusive(spec) ? 2234 MC_CMD_FILTER_OP_IN_OP_INSERT : 2235 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE); 2236 2237 /* Convert match flags and values. Unlike almost 2238 * everything else in MCDI, these fields are in 2239 * network byte order. 2240 */ 2241 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) 2242 match_fields |= 2243 is_multicast_ether_addr(spec->loc_mac) ? 2244 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN : 2245 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; 2246 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \ 2247 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \ 2248 match_fields |= \ 2249 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 2250 mcdi_field ## _LBN; \ 2251 BUILD_BUG_ON( \ 2252 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \ 2253 sizeof(spec->gen_field)); \ 2254 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \ 2255 &spec->gen_field, sizeof(spec->gen_field)); \ 2256 } 2257 COPY_FIELD(REM_HOST, rem_host, SRC_IP); 2258 COPY_FIELD(LOC_HOST, loc_host, DST_IP); 2259 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC); 2260 COPY_FIELD(REM_PORT, rem_port, SRC_PORT); 2261 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC); 2262 COPY_FIELD(LOC_PORT, loc_port, DST_PORT); 2263 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE); 2264 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN); 2265 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN); 2266 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO); 2267 #undef COPY_FIELD 2268 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS, 2269 match_fields); 2270 } 2271 2272 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 2273 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST, 2274 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2275 MC_CMD_FILTER_OP_IN_RX_DEST_DROP : 2276 MC_CMD_FILTER_OP_IN_RX_DEST_HOST); 2277 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST, 2278 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); 2279 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, 2280 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2281 0 : spec->dmaq_id); 2282 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE, 2283 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ? 2284 MC_CMD_FILTER_OP_IN_RX_MODE_RSS : 2285 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); 2286 if (spec->flags & EFX_FILTER_FLAG_RX_RSS) 2287 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, 2288 spec->rss_context != 2289 EFX_FILTER_RSS_CONTEXT_DEFAULT ? 2290 spec->rss_context : nic_data->rx_rss_context); 2291 } 2292 2293 static int efx_ef10_filter_push(struct efx_nic *efx, 2294 const struct efx_filter_spec *spec, 2295 u64 *handle, bool replacing) 2296 { 2297 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 2298 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN); 2299 int rc; 2300 2301 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing); 2302 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 2303 outbuf, sizeof(outbuf), NULL); 2304 if (rc == 0) 2305 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 2306 if (rc == -ENOSPC) 2307 rc = -EBUSY; /* to match efx_farch_filter_insert() */ 2308 return rc; 2309 } 2310 2311 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table, 2312 enum efx_filter_match_flags match_flags) 2313 { 2314 unsigned int match_pri; 2315 2316 for (match_pri = 0; 2317 match_pri < table->rx_match_count; 2318 match_pri++) 2319 if (table->rx_match_flags[match_pri] == match_flags) 2320 return match_pri; 2321 2322 return -EPROTONOSUPPORT; 2323 } 2324 2325 static s32 efx_ef10_filter_insert(struct efx_nic *efx, 2326 struct efx_filter_spec *spec, 2327 bool replace_equal) 2328 { 2329 struct efx_ef10_filter_table *table = efx->filter_state; 2330 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 2331 struct efx_filter_spec *saved_spec; 2332 unsigned int match_pri, hash; 2333 unsigned int priv_flags; 2334 bool replacing = false; 2335 int ins_index = -1; 2336 DEFINE_WAIT(wait); 2337 bool is_mc_recip; 2338 s32 rc; 2339 2340 /* For now, only support RX filters */ 2341 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) != 2342 EFX_FILTER_FLAG_RX) 2343 return -EINVAL; 2344 2345 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags); 2346 if (rc < 0) 2347 return rc; 2348 match_pri = rc; 2349 2350 hash = efx_ef10_filter_hash(spec); 2351 is_mc_recip = efx_filter_is_mc_recipient(spec); 2352 if (is_mc_recip) 2353 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 2354 2355 /* Find any existing filters with the same match tuple or 2356 * else a free slot to insert at. If any of them are busy, 2357 * we have to wait and retry. 2358 */ 2359 for (;;) { 2360 unsigned int depth = 1; 2361 unsigned int i; 2362 2363 spin_lock_bh(&efx->filter_lock); 2364 2365 for (;;) { 2366 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 2367 saved_spec = efx_ef10_filter_entry_spec(table, i); 2368 2369 if (!saved_spec) { 2370 if (ins_index < 0) 2371 ins_index = i; 2372 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 2373 if (table->entry[i].spec & 2374 EFX_EF10_FILTER_FLAG_BUSY) 2375 break; 2376 if (spec->priority < saved_spec->priority && 2377 spec->priority != EFX_FILTER_PRI_AUTO) { 2378 rc = -EPERM; 2379 goto out_unlock; 2380 } 2381 if (!is_mc_recip) { 2382 /* This is the only one */ 2383 if (spec->priority == 2384 saved_spec->priority && 2385 !replace_equal) { 2386 rc = -EEXIST; 2387 goto out_unlock; 2388 } 2389 ins_index = i; 2390 goto found; 2391 } else if (spec->priority > 2392 saved_spec->priority || 2393 (spec->priority == 2394 saved_spec->priority && 2395 replace_equal)) { 2396 if (ins_index < 0) 2397 ins_index = i; 2398 else 2399 __set_bit(depth, mc_rem_map); 2400 } 2401 } 2402 2403 /* Once we reach the maximum search depth, use 2404 * the first suitable slot or return -EBUSY if 2405 * there was none 2406 */ 2407 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 2408 if (ins_index < 0) { 2409 rc = -EBUSY; 2410 goto out_unlock; 2411 } 2412 goto found; 2413 } 2414 2415 ++depth; 2416 } 2417 2418 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 2419 spin_unlock_bh(&efx->filter_lock); 2420 schedule(); 2421 } 2422 2423 found: 2424 /* Create a software table entry if necessary, and mark it 2425 * busy. We might yet fail to insert, but any attempt to 2426 * insert a conflicting filter while we're waiting for the 2427 * firmware must find the busy entry. 2428 */ 2429 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 2430 if (saved_spec) { 2431 if (spec->priority == EFX_FILTER_PRI_AUTO && 2432 saved_spec->priority >= EFX_FILTER_PRI_AUTO) { 2433 /* Just make sure it won't be removed */ 2434 if (saved_spec->priority > EFX_FILTER_PRI_AUTO) 2435 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; 2436 table->entry[ins_index].spec &= 2437 ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 2438 rc = ins_index; 2439 goto out_unlock; 2440 } 2441 replacing = true; 2442 priv_flags = efx_ef10_filter_entry_flags(table, ins_index); 2443 } else { 2444 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 2445 if (!saved_spec) { 2446 rc = -ENOMEM; 2447 goto out_unlock; 2448 } 2449 *saved_spec = *spec; 2450 priv_flags = 0; 2451 } 2452 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 2453 priv_flags | EFX_EF10_FILTER_FLAG_BUSY); 2454 2455 /* Mark lower-priority multicast recipients busy prior to removal */ 2456 if (is_mc_recip) { 2457 unsigned int depth, i; 2458 2459 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 2460 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 2461 if (test_bit(depth, mc_rem_map)) 2462 table->entry[i].spec |= 2463 EFX_EF10_FILTER_FLAG_BUSY; 2464 } 2465 } 2466 2467 spin_unlock_bh(&efx->filter_lock); 2468 2469 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle, 2470 replacing); 2471 2472 /* Finalise the software table entry */ 2473 spin_lock_bh(&efx->filter_lock); 2474 if (rc == 0) { 2475 if (replacing) { 2476 /* Update the fields that may differ */ 2477 if (saved_spec->priority == EFX_FILTER_PRI_AUTO) 2478 saved_spec->flags |= 2479 EFX_FILTER_FLAG_RX_OVER_AUTO; 2480 saved_spec->priority = spec->priority; 2481 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO; 2482 saved_spec->flags |= spec->flags; 2483 saved_spec->rss_context = spec->rss_context; 2484 saved_spec->dmaq_id = spec->dmaq_id; 2485 } 2486 } else if (!replacing) { 2487 kfree(saved_spec); 2488 saved_spec = NULL; 2489 } 2490 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags); 2491 2492 /* Remove and finalise entries for lower-priority multicast 2493 * recipients 2494 */ 2495 if (is_mc_recip) { 2496 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 2497 unsigned int depth, i; 2498 2499 memset(inbuf, 0, sizeof(inbuf)); 2500 2501 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 2502 if (!test_bit(depth, mc_rem_map)) 2503 continue; 2504 2505 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 2506 saved_spec = efx_ef10_filter_entry_spec(table, i); 2507 priv_flags = efx_ef10_filter_entry_flags(table, i); 2508 2509 if (rc == 0) { 2510 spin_unlock_bh(&efx->filter_lock); 2511 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2512 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 2513 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 2514 table->entry[i].handle); 2515 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 2516 inbuf, sizeof(inbuf), 2517 NULL, 0, NULL); 2518 spin_lock_bh(&efx->filter_lock); 2519 } 2520 2521 if (rc == 0) { 2522 kfree(saved_spec); 2523 saved_spec = NULL; 2524 priv_flags = 0; 2525 } else { 2526 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY; 2527 } 2528 efx_ef10_filter_set_entry(table, i, saved_spec, 2529 priv_flags); 2530 } 2531 } 2532 2533 /* If successful, return the inserted filter ID */ 2534 if (rc == 0) 2535 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index; 2536 2537 wake_up_all(&table->waitq); 2538 out_unlock: 2539 spin_unlock_bh(&efx->filter_lock); 2540 finish_wait(&table->waitq, &wait); 2541 return rc; 2542 } 2543 2544 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx) 2545 { 2546 /* no need to do anything here on EF10 */ 2547 } 2548 2549 /* Remove a filter. 2550 * If !by_index, remove by ID 2551 * If by_index, remove by index 2552 * Filter ID may come from userland and must be range-checked. 2553 */ 2554 static int efx_ef10_filter_remove_internal(struct efx_nic *efx, 2555 unsigned int priority_mask, 2556 u32 filter_id, bool by_index) 2557 { 2558 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 2559 struct efx_ef10_filter_table *table = efx->filter_state; 2560 MCDI_DECLARE_BUF(inbuf, 2561 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 2562 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 2563 struct efx_filter_spec *spec; 2564 DEFINE_WAIT(wait); 2565 int rc; 2566 2567 /* Find the software table entry and mark it busy. Don't 2568 * remove it yet; any attempt to update while we're waiting 2569 * for the firmware must find the busy entry. 2570 */ 2571 for (;;) { 2572 spin_lock_bh(&efx->filter_lock); 2573 if (!(table->entry[filter_idx].spec & 2574 EFX_EF10_FILTER_FLAG_BUSY)) 2575 break; 2576 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 2577 spin_unlock_bh(&efx->filter_lock); 2578 schedule(); 2579 } 2580 2581 spec = efx_ef10_filter_entry_spec(table, filter_idx); 2582 if (!spec || 2583 (!by_index && 2584 efx_ef10_filter_rx_match_pri(table, spec->match_flags) != 2585 filter_id / HUNT_FILTER_TBL_ROWS)) { 2586 rc = -ENOENT; 2587 goto out_unlock; 2588 } 2589 2590 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO && 2591 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) { 2592 /* Just remove flags */ 2593 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO; 2594 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 2595 rc = 0; 2596 goto out_unlock; 2597 } 2598 2599 if (!(priority_mask & (1U << spec->priority))) { 2600 rc = -ENOENT; 2601 goto out_unlock; 2602 } 2603 2604 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 2605 spin_unlock_bh(&efx->filter_lock); 2606 2607 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { 2608 /* Reset to an automatic filter */ 2609 2610 struct efx_filter_spec new_spec = *spec; 2611 2612 new_spec.priority = EFX_FILTER_PRI_AUTO; 2613 new_spec.flags = (EFX_FILTER_FLAG_RX | 2614 EFX_FILTER_FLAG_RX_RSS); 2615 new_spec.dmaq_id = 0; 2616 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT; 2617 rc = efx_ef10_filter_push(efx, &new_spec, 2618 &table->entry[filter_idx].handle, 2619 true); 2620 2621 spin_lock_bh(&efx->filter_lock); 2622 if (rc == 0) 2623 *spec = new_spec; 2624 } else { 2625 /* Really remove the filter */ 2626 2627 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2628 efx_ef10_filter_is_exclusive(spec) ? 2629 MC_CMD_FILTER_OP_IN_OP_REMOVE : 2630 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 2631 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 2632 table->entry[filter_idx].handle); 2633 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 2634 inbuf, sizeof(inbuf), NULL, 0, NULL); 2635 2636 spin_lock_bh(&efx->filter_lock); 2637 if (rc == 0) { 2638 kfree(spec); 2639 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 2640 } 2641 } 2642 2643 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 2644 wake_up_all(&table->waitq); 2645 out_unlock: 2646 spin_unlock_bh(&efx->filter_lock); 2647 finish_wait(&table->waitq, &wait); 2648 return rc; 2649 } 2650 2651 static int efx_ef10_filter_remove_safe(struct efx_nic *efx, 2652 enum efx_filter_priority priority, 2653 u32 filter_id) 2654 { 2655 return efx_ef10_filter_remove_internal(efx, 1U << priority, 2656 filter_id, false); 2657 } 2658 2659 static int efx_ef10_filter_get_safe(struct efx_nic *efx, 2660 enum efx_filter_priority priority, 2661 u32 filter_id, struct efx_filter_spec *spec) 2662 { 2663 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 2664 struct efx_ef10_filter_table *table = efx->filter_state; 2665 const struct efx_filter_spec *saved_spec; 2666 int rc; 2667 2668 spin_lock_bh(&efx->filter_lock); 2669 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx); 2670 if (saved_spec && saved_spec->priority == priority && 2671 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) == 2672 filter_id / HUNT_FILTER_TBL_ROWS) { 2673 *spec = *saved_spec; 2674 rc = 0; 2675 } else { 2676 rc = -ENOENT; 2677 } 2678 spin_unlock_bh(&efx->filter_lock); 2679 return rc; 2680 } 2681 2682 static int efx_ef10_filter_clear_rx(struct efx_nic *efx, 2683 enum efx_filter_priority priority) 2684 { 2685 unsigned int priority_mask; 2686 unsigned int i; 2687 int rc; 2688 2689 priority_mask = (((1U << (priority + 1)) - 1) & 2690 ~(1U << EFX_FILTER_PRI_AUTO)); 2691 2692 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 2693 rc = efx_ef10_filter_remove_internal(efx, priority_mask, 2694 i, true); 2695 if (rc && rc != -ENOENT) 2696 return rc; 2697 } 2698 2699 return 0; 2700 } 2701 2702 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx, 2703 enum efx_filter_priority priority) 2704 { 2705 struct efx_ef10_filter_table *table = efx->filter_state; 2706 unsigned int filter_idx; 2707 s32 count = 0; 2708 2709 spin_lock_bh(&efx->filter_lock); 2710 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 2711 if (table->entry[filter_idx].spec && 2712 efx_ef10_filter_entry_spec(table, filter_idx)->priority == 2713 priority) 2714 ++count; 2715 } 2716 spin_unlock_bh(&efx->filter_lock); 2717 return count; 2718 } 2719 2720 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx) 2721 { 2722 struct efx_ef10_filter_table *table = efx->filter_state; 2723 2724 return table->rx_match_count * HUNT_FILTER_TBL_ROWS; 2725 } 2726 2727 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx, 2728 enum efx_filter_priority priority, 2729 u32 *buf, u32 size) 2730 { 2731 struct efx_ef10_filter_table *table = efx->filter_state; 2732 struct efx_filter_spec *spec; 2733 unsigned int filter_idx; 2734 s32 count = 0; 2735 2736 spin_lock_bh(&efx->filter_lock); 2737 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 2738 spec = efx_ef10_filter_entry_spec(table, filter_idx); 2739 if (spec && spec->priority == priority) { 2740 if (count == size) { 2741 count = -EMSGSIZE; 2742 break; 2743 } 2744 buf[count++] = (efx_ef10_filter_rx_match_pri( 2745 table, spec->match_flags) * 2746 HUNT_FILTER_TBL_ROWS + 2747 filter_idx); 2748 } 2749 } 2750 spin_unlock_bh(&efx->filter_lock); 2751 return count; 2752 } 2753 2754 #ifdef CONFIG_RFS_ACCEL 2755 2756 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete; 2757 2758 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx, 2759 struct efx_filter_spec *spec) 2760 { 2761 struct efx_ef10_filter_table *table = efx->filter_state; 2762 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 2763 struct efx_filter_spec *saved_spec; 2764 unsigned int hash, i, depth = 1; 2765 bool replacing = false; 2766 int ins_index = -1; 2767 u64 cookie; 2768 s32 rc; 2769 2770 /* Must be an RX filter without RSS and not for a multicast 2771 * destination address (RFS only works for connected sockets). 2772 * These restrictions allow us to pass only a tiny amount of 2773 * data through to the completion function. 2774 */ 2775 EFX_WARN_ON_PARANOID(spec->flags != 2776 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER)); 2777 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT); 2778 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec)); 2779 2780 hash = efx_ef10_filter_hash(spec); 2781 2782 spin_lock_bh(&efx->filter_lock); 2783 2784 /* Find any existing filter with the same match tuple or else 2785 * a free slot to insert at. If an existing filter is busy, 2786 * we have to give up. 2787 */ 2788 for (;;) { 2789 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 2790 saved_spec = efx_ef10_filter_entry_spec(table, i); 2791 2792 if (!saved_spec) { 2793 if (ins_index < 0) 2794 ins_index = i; 2795 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 2796 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) { 2797 rc = -EBUSY; 2798 goto fail_unlock; 2799 } 2800 if (spec->priority < saved_spec->priority) { 2801 rc = -EPERM; 2802 goto fail_unlock; 2803 } 2804 ins_index = i; 2805 break; 2806 } 2807 2808 /* Once we reach the maximum search depth, use the 2809 * first suitable slot or return -EBUSY if there was 2810 * none 2811 */ 2812 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 2813 if (ins_index < 0) { 2814 rc = -EBUSY; 2815 goto fail_unlock; 2816 } 2817 break; 2818 } 2819 2820 ++depth; 2821 } 2822 2823 /* Create a software table entry if necessary, and mark it 2824 * busy. We might yet fail to insert, but any attempt to 2825 * insert a conflicting filter while we're waiting for the 2826 * firmware must find the busy entry. 2827 */ 2828 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 2829 if (saved_spec) { 2830 replacing = true; 2831 } else { 2832 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 2833 if (!saved_spec) { 2834 rc = -ENOMEM; 2835 goto fail_unlock; 2836 } 2837 *saved_spec = *spec; 2838 } 2839 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 2840 EFX_EF10_FILTER_FLAG_BUSY); 2841 2842 spin_unlock_bh(&efx->filter_lock); 2843 2844 /* Pack up the variables needed on completion */ 2845 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id; 2846 2847 efx_ef10_filter_push_prep(efx, spec, inbuf, 2848 table->entry[ins_index].handle, replacing); 2849 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 2850 MC_CMD_FILTER_OP_OUT_LEN, 2851 efx_ef10_filter_rfs_insert_complete, cookie); 2852 2853 return ins_index; 2854 2855 fail_unlock: 2856 spin_unlock_bh(&efx->filter_lock); 2857 return rc; 2858 } 2859 2860 static void 2861 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie, 2862 int rc, efx_dword_t *outbuf, 2863 size_t outlen_actual) 2864 { 2865 struct efx_ef10_filter_table *table = efx->filter_state; 2866 unsigned int ins_index, dmaq_id; 2867 struct efx_filter_spec *spec; 2868 bool replacing; 2869 2870 /* Unpack the cookie */ 2871 replacing = cookie >> 31; 2872 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1); 2873 dmaq_id = cookie & 0xffff; 2874 2875 spin_lock_bh(&efx->filter_lock); 2876 spec = efx_ef10_filter_entry_spec(table, ins_index); 2877 if (rc == 0) { 2878 table->entry[ins_index].handle = 2879 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 2880 if (replacing) 2881 spec->dmaq_id = dmaq_id; 2882 } else if (!replacing) { 2883 kfree(spec); 2884 spec = NULL; 2885 } 2886 efx_ef10_filter_set_entry(table, ins_index, spec, 0); 2887 spin_unlock_bh(&efx->filter_lock); 2888 2889 wake_up_all(&table->waitq); 2890 } 2891 2892 static void 2893 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 2894 unsigned long filter_idx, 2895 int rc, efx_dword_t *outbuf, 2896 size_t outlen_actual); 2897 2898 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, 2899 unsigned int filter_idx) 2900 { 2901 struct efx_ef10_filter_table *table = efx->filter_state; 2902 struct efx_filter_spec *spec = 2903 efx_ef10_filter_entry_spec(table, filter_idx); 2904 MCDI_DECLARE_BUF(inbuf, 2905 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 2906 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 2907 2908 if (!spec || 2909 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) || 2910 spec->priority != EFX_FILTER_PRI_HINT || 2911 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id, 2912 flow_id, filter_idx)) 2913 return false; 2914 2915 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2916 MC_CMD_FILTER_OP_IN_OP_REMOVE); 2917 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 2918 table->entry[filter_idx].handle); 2919 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0, 2920 efx_ef10_filter_rfs_expire_complete, filter_idx)) 2921 return false; 2922 2923 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 2924 return true; 2925 } 2926 2927 static void 2928 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 2929 unsigned long filter_idx, 2930 int rc, efx_dword_t *outbuf, 2931 size_t outlen_actual) 2932 { 2933 struct efx_ef10_filter_table *table = efx->filter_state; 2934 struct efx_filter_spec *spec = 2935 efx_ef10_filter_entry_spec(table, filter_idx); 2936 2937 spin_lock_bh(&efx->filter_lock); 2938 if (rc == 0) { 2939 kfree(spec); 2940 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 2941 } 2942 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 2943 wake_up_all(&table->waitq); 2944 spin_unlock_bh(&efx->filter_lock); 2945 } 2946 2947 #endif /* CONFIG_RFS_ACCEL */ 2948 2949 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags) 2950 { 2951 int match_flags = 0; 2952 2953 #define MAP_FLAG(gen_flag, mcdi_field) { \ 2954 u32 old_mcdi_flags = mcdi_flags; \ 2955 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 2956 mcdi_field ## _LBN); \ 2957 if (mcdi_flags != old_mcdi_flags) \ 2958 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \ 2959 } 2960 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST); 2961 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST); 2962 MAP_FLAG(REM_HOST, SRC_IP); 2963 MAP_FLAG(LOC_HOST, DST_IP); 2964 MAP_FLAG(REM_MAC, SRC_MAC); 2965 MAP_FLAG(REM_PORT, SRC_PORT); 2966 MAP_FLAG(LOC_MAC, DST_MAC); 2967 MAP_FLAG(LOC_PORT, DST_PORT); 2968 MAP_FLAG(ETHER_TYPE, ETHER_TYPE); 2969 MAP_FLAG(INNER_VID, INNER_VLAN); 2970 MAP_FLAG(OUTER_VID, OUTER_VLAN); 2971 MAP_FLAG(IP_PROTO, IP_PROTO); 2972 #undef MAP_FLAG 2973 2974 /* Did we map them all? */ 2975 if (mcdi_flags) 2976 return -EINVAL; 2977 2978 return match_flags; 2979 } 2980 2981 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 2982 { 2983 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN); 2984 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX); 2985 unsigned int pd_match_pri, pd_match_count; 2986 struct efx_ef10_filter_table *table; 2987 size_t outlen; 2988 int rc; 2989 2990 table = kzalloc(sizeof(*table), GFP_KERNEL); 2991 if (!table) 2992 return -ENOMEM; 2993 2994 /* Find out which RX filter types are supported, and their priorities */ 2995 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP, 2996 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); 2997 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO, 2998 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf), 2999 &outlen); 3000 if (rc) 3001 goto fail; 3002 pd_match_count = MCDI_VAR_ARRAY_LEN( 3003 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES); 3004 table->rx_match_count = 0; 3005 3006 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) { 3007 u32 mcdi_flags = 3008 MCDI_ARRAY_DWORD( 3009 outbuf, 3010 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES, 3011 pd_match_pri); 3012 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags); 3013 if (rc < 0) { 3014 netif_dbg(efx, probe, efx->net_dev, 3015 "%s: fw flags %#x pri %u not supported in driver\n", 3016 __func__, mcdi_flags, pd_match_pri); 3017 } else { 3018 netif_dbg(efx, probe, efx->net_dev, 3019 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n", 3020 __func__, mcdi_flags, pd_match_pri, 3021 rc, table->rx_match_count); 3022 table->rx_match_flags[table->rx_match_count++] = rc; 3023 } 3024 } 3025 3026 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry)); 3027 if (!table->entry) { 3028 rc = -ENOMEM; 3029 goto fail; 3030 } 3031 3032 efx->filter_state = table; 3033 init_waitqueue_head(&table->waitq); 3034 return 0; 3035 3036 fail: 3037 kfree(table); 3038 return rc; 3039 } 3040 3041 static void efx_ef10_filter_table_restore(struct efx_nic *efx) 3042 { 3043 struct efx_ef10_filter_table *table = efx->filter_state; 3044 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3045 struct efx_filter_spec *spec; 3046 unsigned int filter_idx; 3047 bool failed = false; 3048 int rc; 3049 3050 if (!nic_data->must_restore_filters) 3051 return; 3052 3053 spin_lock_bh(&efx->filter_lock); 3054 3055 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3056 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3057 if (!spec) 3058 continue; 3059 3060 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3061 spin_unlock_bh(&efx->filter_lock); 3062 3063 rc = efx_ef10_filter_push(efx, spec, 3064 &table->entry[filter_idx].handle, 3065 false); 3066 if (rc) 3067 failed = true; 3068 3069 spin_lock_bh(&efx->filter_lock); 3070 if (rc) { 3071 kfree(spec); 3072 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3073 } else { 3074 table->entry[filter_idx].spec &= 3075 ~EFX_EF10_FILTER_FLAG_BUSY; 3076 } 3077 } 3078 3079 spin_unlock_bh(&efx->filter_lock); 3080 3081 if (failed) 3082 netif_err(efx, hw, efx->net_dev, 3083 "unable to restore all filters\n"); 3084 else 3085 nic_data->must_restore_filters = false; 3086 } 3087 3088 static void efx_ef10_filter_table_remove(struct efx_nic *efx) 3089 { 3090 struct efx_ef10_filter_table *table = efx->filter_state; 3091 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3092 struct efx_filter_spec *spec; 3093 unsigned int filter_idx; 3094 int rc; 3095 3096 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3097 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3098 if (!spec) 3099 continue; 3100 3101 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3102 efx_ef10_filter_is_exclusive(spec) ? 3103 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3104 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3105 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3106 table->entry[filter_idx].handle); 3107 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3108 NULL, 0, NULL); 3109 if (rc) 3110 netdev_WARN(efx->net_dev, 3111 "filter_idx=%#x handle=%#llx\n", 3112 filter_idx, 3113 table->entry[filter_idx].handle); 3114 kfree(spec); 3115 } 3116 3117 vfree(table->entry); 3118 kfree(table); 3119 } 3120 3121 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx) 3122 { 3123 struct efx_ef10_filter_table *table = efx->filter_state; 3124 struct net_device *net_dev = efx->net_dev; 3125 struct efx_filter_spec spec; 3126 bool remove_failed = false; 3127 struct netdev_hw_addr *uc; 3128 struct netdev_hw_addr *mc; 3129 unsigned int filter_idx; 3130 int i, n, rc; 3131 3132 if (!efx_dev_registered(efx)) 3133 return; 3134 3135 /* Mark old filters that may need to be removed */ 3136 spin_lock_bh(&efx->filter_lock); 3137 n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count; 3138 for (i = 0; i < n; i++) { 3139 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS; 3140 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; 3141 } 3142 n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count; 3143 for (i = 0; i < n; i++) { 3144 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS; 3145 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; 3146 } 3147 spin_unlock_bh(&efx->filter_lock); 3148 3149 /* Copy/convert the address lists; add the primary station 3150 * address and broadcast address 3151 */ 3152 netif_addr_lock_bh(net_dev); 3153 if (net_dev->flags & IFF_PROMISC || 3154 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) { 3155 table->dev_uc_count = -1; 3156 } else { 3157 table->dev_uc_count = 1 + netdev_uc_count(net_dev); 3158 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr); 3159 i = 1; 3160 netdev_for_each_uc_addr(uc, net_dev) { 3161 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr); 3162 i++; 3163 } 3164 } 3165 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) || 3166 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) { 3167 table->dev_mc_count = -1; 3168 } else { 3169 table->dev_mc_count = 1 + netdev_mc_count(net_dev); 3170 eth_broadcast_addr(table->dev_mc_list[0].addr); 3171 i = 1; 3172 netdev_for_each_mc_addr(mc, net_dev) { 3173 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr); 3174 i++; 3175 } 3176 } 3177 netif_addr_unlock_bh(net_dev); 3178 3179 /* Insert/renew unicast filters */ 3180 if (table->dev_uc_count >= 0) { 3181 for (i = 0; i < table->dev_uc_count; i++) { 3182 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3183 EFX_FILTER_FLAG_RX_RSS, 3184 0); 3185 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 3186 table->dev_uc_list[i].addr); 3187 rc = efx_ef10_filter_insert(efx, &spec, true); 3188 if (rc < 0) { 3189 /* Fall back to unicast-promisc */ 3190 while (i--) 3191 efx_ef10_filter_remove_safe( 3192 efx, EFX_FILTER_PRI_AUTO, 3193 table->dev_uc_list[i].id); 3194 table->dev_uc_count = -1; 3195 break; 3196 } 3197 table->dev_uc_list[i].id = rc; 3198 } 3199 } 3200 if (table->dev_uc_count < 0) { 3201 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3202 EFX_FILTER_FLAG_RX_RSS, 3203 0); 3204 efx_filter_set_uc_def(&spec); 3205 rc = efx_ef10_filter_insert(efx, &spec, true); 3206 if (rc < 0) { 3207 WARN_ON(1); 3208 table->dev_uc_count = 0; 3209 } else { 3210 table->dev_uc_list[0].id = rc; 3211 } 3212 } 3213 3214 /* Insert/renew multicast filters */ 3215 if (table->dev_mc_count >= 0) { 3216 for (i = 0; i < table->dev_mc_count; i++) { 3217 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3218 EFX_FILTER_FLAG_RX_RSS, 3219 0); 3220 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 3221 table->dev_mc_list[i].addr); 3222 rc = efx_ef10_filter_insert(efx, &spec, true); 3223 if (rc < 0) { 3224 /* Fall back to multicast-promisc */ 3225 while (i--) 3226 efx_ef10_filter_remove_safe( 3227 efx, EFX_FILTER_PRI_AUTO, 3228 table->dev_mc_list[i].id); 3229 table->dev_mc_count = -1; 3230 break; 3231 } 3232 table->dev_mc_list[i].id = rc; 3233 } 3234 } 3235 if (table->dev_mc_count < 0) { 3236 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3237 EFX_FILTER_FLAG_RX_RSS, 3238 0); 3239 efx_filter_set_mc_def(&spec); 3240 rc = efx_ef10_filter_insert(efx, &spec, true); 3241 if (rc < 0) { 3242 WARN_ON(1); 3243 table->dev_mc_count = 0; 3244 } else { 3245 table->dev_mc_list[0].id = rc; 3246 } 3247 } 3248 3249 /* Remove filters that weren't renewed. Since nothing else 3250 * changes the AUTO_OLD flag or removes these filters, we 3251 * don't need to hold the filter_lock while scanning for 3252 * these filters. 3253 */ 3254 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 3255 if (ACCESS_ONCE(table->entry[i].spec) & 3256 EFX_EF10_FILTER_FLAG_AUTO_OLD) { 3257 if (efx_ef10_filter_remove_internal( 3258 efx, 1U << EFX_FILTER_PRI_AUTO, 3259 i, true) < 0) 3260 remove_failed = true; 3261 } 3262 } 3263 WARN_ON(remove_failed); 3264 } 3265 3266 static int efx_ef10_mac_reconfigure(struct efx_nic *efx) 3267 { 3268 efx_ef10_filter_sync_rx_mode(efx); 3269 3270 return efx_mcdi_set_mac(efx); 3271 } 3272 3273 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 3274 { 3275 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 3276 3277 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 3278 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 3279 NULL, 0, NULL); 3280 } 3281 3282 /* MC BISTs follow a different poll mechanism to phy BISTs. 3283 * The BIST is done in the poll handler on the MC, and the MCDI command 3284 * will block until the BIST is done. 3285 */ 3286 static int efx_ef10_poll_bist(struct efx_nic *efx) 3287 { 3288 int rc; 3289 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 3290 size_t outlen; 3291 u32 result; 3292 3293 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 3294 outbuf, sizeof(outbuf), &outlen); 3295 if (rc != 0) 3296 return rc; 3297 3298 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 3299 return -EIO; 3300 3301 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 3302 switch (result) { 3303 case MC_CMD_POLL_BIST_PASSED: 3304 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 3305 return 0; 3306 case MC_CMD_POLL_BIST_TIMEOUT: 3307 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 3308 return -EIO; 3309 case MC_CMD_POLL_BIST_FAILED: 3310 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 3311 return -EIO; 3312 default: 3313 netif_err(efx, hw, efx->net_dev, 3314 "BIST returned unknown result %u", result); 3315 return -EIO; 3316 } 3317 } 3318 3319 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 3320 { 3321 int rc; 3322 3323 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 3324 3325 rc = efx_ef10_start_bist(efx, bist_type); 3326 if (rc != 0) 3327 return rc; 3328 3329 return efx_ef10_poll_bist(efx); 3330 } 3331 3332 static int 3333 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 3334 { 3335 int rc, rc2; 3336 3337 efx_reset_down(efx, RESET_TYPE_WORLD); 3338 3339 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 3340 NULL, 0, NULL, 0, NULL); 3341 if (rc != 0) 3342 goto out; 3343 3344 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 3345 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 3346 3347 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 3348 3349 out: 3350 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 3351 return rc ? rc : rc2; 3352 } 3353 3354 #ifdef CONFIG_SFC_MTD 3355 3356 struct efx_ef10_nvram_type_info { 3357 u16 type, type_mask; 3358 u8 port; 3359 const char *name; 3360 }; 3361 3362 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 3363 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 3364 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 3365 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 3366 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 3367 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 3368 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 3369 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 3370 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 3371 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 3372 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 3373 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 3374 }; 3375 3376 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 3377 struct efx_mcdi_mtd_partition *part, 3378 unsigned int type) 3379 { 3380 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 3381 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 3382 const struct efx_ef10_nvram_type_info *info; 3383 size_t size, erase_size, outlen; 3384 bool protected; 3385 int rc; 3386 3387 for (info = efx_ef10_nvram_types; ; info++) { 3388 if (info == 3389 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types)) 3390 return -ENODEV; 3391 if ((type & ~info->type_mask) == info->type) 3392 break; 3393 } 3394 if (info->port != efx_port_num(efx)) 3395 return -ENODEV; 3396 3397 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 3398 if (rc) 3399 return rc; 3400 if (protected) 3401 return -ENODEV; /* hide it */ 3402 3403 part->nvram_type = type; 3404 3405 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 3406 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 3407 outbuf, sizeof(outbuf), &outlen); 3408 if (rc) 3409 return rc; 3410 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 3411 return -EIO; 3412 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 3413 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 3414 part->fw_subtype = MCDI_DWORD(outbuf, 3415 NVRAM_METADATA_OUT_SUBTYPE); 3416 3417 part->common.dev_type_name = "EF10 NVRAM manager"; 3418 part->common.type_name = info->name; 3419 3420 part->common.mtd.type = MTD_NORFLASH; 3421 part->common.mtd.flags = MTD_CAP_NORFLASH; 3422 part->common.mtd.size = size; 3423 part->common.mtd.erasesize = erase_size; 3424 3425 return 0; 3426 } 3427 3428 static int efx_ef10_mtd_probe(struct efx_nic *efx) 3429 { 3430 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 3431 struct efx_mcdi_mtd_partition *parts; 3432 size_t outlen, n_parts_total, i, n_parts; 3433 unsigned int type; 3434 int rc; 3435 3436 ASSERT_RTNL(); 3437 3438 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 3439 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 3440 outbuf, sizeof(outbuf), &outlen); 3441 if (rc) 3442 return rc; 3443 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 3444 return -EIO; 3445 3446 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 3447 if (n_parts_total > 3448 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 3449 return -EIO; 3450 3451 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 3452 if (!parts) 3453 return -ENOMEM; 3454 3455 n_parts = 0; 3456 for (i = 0; i < n_parts_total; i++) { 3457 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 3458 i); 3459 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type); 3460 if (rc == 0) 3461 n_parts++; 3462 else if (rc != -ENODEV) 3463 goto fail; 3464 } 3465 3466 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 3467 fail: 3468 if (rc) 3469 kfree(parts); 3470 return rc; 3471 } 3472 3473 #endif /* CONFIG_SFC_MTD */ 3474 3475 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 3476 { 3477 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 3478 } 3479 3480 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 3481 bool temp) 3482 { 3483 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 3484 int rc; 3485 3486 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 3487 channel->sync_events_state == SYNC_EVENTS_VALID || 3488 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 3489 return 0; 3490 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 3491 3492 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 3493 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3494 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 3495 channel->channel); 3496 3497 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3498 inbuf, sizeof(inbuf), NULL, 0, NULL); 3499 3500 if (rc != 0) 3501 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3502 SYNC_EVENTS_DISABLED; 3503 3504 return rc; 3505 } 3506 3507 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 3508 bool temp) 3509 { 3510 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 3511 int rc; 3512 3513 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 3514 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 3515 return 0; 3516 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 3517 channel->sync_events_state = SYNC_EVENTS_DISABLED; 3518 return 0; 3519 } 3520 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3521 SYNC_EVENTS_DISABLED; 3522 3523 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 3524 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3525 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 3526 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 3527 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 3528 channel->channel); 3529 3530 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3531 inbuf, sizeof(inbuf), NULL, 0, NULL); 3532 3533 return rc; 3534 } 3535 3536 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 3537 bool temp) 3538 { 3539 int (*set)(struct efx_channel *channel, bool temp); 3540 struct efx_channel *channel; 3541 3542 set = en ? 3543 efx_ef10_rx_enable_timestamping : 3544 efx_ef10_rx_disable_timestamping; 3545 3546 efx_for_each_channel(channel, efx) { 3547 int rc = set(channel, temp); 3548 if (en && rc != 0) { 3549 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 3550 return rc; 3551 } 3552 } 3553 3554 return 0; 3555 } 3556 3557 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 3558 struct hwtstamp_config *init) 3559 { 3560 int rc; 3561 3562 switch (init->rx_filter) { 3563 case HWTSTAMP_FILTER_NONE: 3564 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 3565 /* if TX timestamping is still requested then leave PTP on */ 3566 return efx_ptp_change_mode(efx, 3567 init->tx_type != HWTSTAMP_TX_OFF, 0); 3568 case HWTSTAMP_FILTER_ALL: 3569 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3570 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3571 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3572 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3573 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3574 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3575 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3576 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3577 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3578 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3579 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3580 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3581 init->rx_filter = HWTSTAMP_FILTER_ALL; 3582 rc = efx_ptp_change_mode(efx, true, 0); 3583 if (!rc) 3584 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 3585 if (rc) 3586 efx_ptp_change_mode(efx, false, 0); 3587 return rc; 3588 default: 3589 return -ERANGE; 3590 } 3591 } 3592 3593 const struct efx_nic_type efx_hunt_a0_nic_type = { 3594 .mem_map_size = efx_ef10_mem_map_size, 3595 .probe = efx_ef10_probe, 3596 .remove = efx_ef10_remove, 3597 .dimension_resources = efx_ef10_dimension_resources, 3598 .init = efx_ef10_init_nic, 3599 .fini = efx_port_dummy_op_void, 3600 .map_reset_reason = efx_mcdi_map_reset_reason, 3601 .map_reset_flags = efx_ef10_map_reset_flags, 3602 .reset = efx_ef10_reset, 3603 .probe_port = efx_mcdi_port_probe, 3604 .remove_port = efx_mcdi_port_remove, 3605 .fini_dmaq = efx_ef10_fini_dmaq, 3606 .describe_stats = efx_ef10_describe_stats, 3607 .update_stats = efx_ef10_update_stats, 3608 .start_stats = efx_mcdi_mac_start_stats, 3609 .pull_stats = efx_mcdi_mac_pull_stats, 3610 .stop_stats = efx_mcdi_mac_stop_stats, 3611 .set_id_led = efx_mcdi_set_id_led, 3612 .push_irq_moderation = efx_ef10_push_irq_moderation, 3613 .reconfigure_mac = efx_ef10_mac_reconfigure, 3614 .check_mac_fault = efx_mcdi_mac_check_fault, 3615 .reconfigure_port = efx_mcdi_port_reconfigure, 3616 .get_wol = efx_ef10_get_wol, 3617 .set_wol = efx_ef10_set_wol, 3618 .resume_wol = efx_port_dummy_op_void, 3619 .test_chip = efx_ef10_test_chip, 3620 .test_nvram = efx_mcdi_nvram_test_all, 3621 .mcdi_request = efx_ef10_mcdi_request, 3622 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 3623 .mcdi_read_response = efx_ef10_mcdi_read_response, 3624 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 3625 .irq_enable_master = efx_port_dummy_op_void, 3626 .irq_test_generate = efx_ef10_irq_test_generate, 3627 .irq_disable_non_ev = efx_port_dummy_op_void, 3628 .irq_handle_msi = efx_ef10_msi_interrupt, 3629 .irq_handle_legacy = efx_ef10_legacy_interrupt, 3630 .tx_probe = efx_ef10_tx_probe, 3631 .tx_init = efx_ef10_tx_init, 3632 .tx_remove = efx_ef10_tx_remove, 3633 .tx_write = efx_ef10_tx_write, 3634 .rx_push_rss_config = efx_ef10_rx_push_rss_config, 3635 .rx_probe = efx_ef10_rx_probe, 3636 .rx_init = efx_ef10_rx_init, 3637 .rx_remove = efx_ef10_rx_remove, 3638 .rx_write = efx_ef10_rx_write, 3639 .rx_defer_refill = efx_ef10_rx_defer_refill, 3640 .ev_probe = efx_ef10_ev_probe, 3641 .ev_init = efx_ef10_ev_init, 3642 .ev_fini = efx_ef10_ev_fini, 3643 .ev_remove = efx_ef10_ev_remove, 3644 .ev_process = efx_ef10_ev_process, 3645 .ev_read_ack = efx_ef10_ev_read_ack, 3646 .ev_test_generate = efx_ef10_ev_test_generate, 3647 .filter_table_probe = efx_ef10_filter_table_probe, 3648 .filter_table_restore = efx_ef10_filter_table_restore, 3649 .filter_table_remove = efx_ef10_filter_table_remove, 3650 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 3651 .filter_insert = efx_ef10_filter_insert, 3652 .filter_remove_safe = efx_ef10_filter_remove_safe, 3653 .filter_get_safe = efx_ef10_filter_get_safe, 3654 .filter_clear_rx = efx_ef10_filter_clear_rx, 3655 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 3656 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 3657 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 3658 #ifdef CONFIG_RFS_ACCEL 3659 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 3660 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 3661 #endif 3662 #ifdef CONFIG_SFC_MTD 3663 .mtd_probe = efx_ef10_mtd_probe, 3664 .mtd_rename = efx_mcdi_mtd_rename, 3665 .mtd_read = efx_mcdi_mtd_read, 3666 .mtd_erase = efx_mcdi_mtd_erase, 3667 .mtd_write = efx_mcdi_mtd_write, 3668 .mtd_sync = efx_mcdi_mtd_sync, 3669 #endif 3670 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 3671 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 3672 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 3673 3674 .revision = EFX_REV_HUNT_A0, 3675 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 3676 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 3677 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 3678 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 3679 .can_rx_scatter = true, 3680 .always_rx_scatter = true, 3681 .max_interrupt_mode = EFX_INT_MODE_MSIX, 3682 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 3683 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3684 NETIF_F_RXHASH | NETIF_F_NTUPLE), 3685 .mcdi_max_ver = 2, 3686 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 3687 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 3688 1 << HWTSTAMP_FILTER_ALL, 3689 }; 3690