1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2012-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 #include "net_driver.h" 11 #include "ef10_regs.h" 12 #include "io.h" 13 #include "mcdi.h" 14 #include "mcdi_pcol.h" 15 #include "nic.h" 16 #include "workarounds.h" 17 #include "selftest.h" 18 #include "ef10_sriov.h" 19 #include <linux/in.h> 20 #include <linux/jhash.h> 21 #include <linux/wait.h> 22 #include <linux/workqueue.h> 23 24 /* Hardware control for EF10 architecture including 'Huntington'. */ 25 26 #define EFX_EF10_DRVGEN_EV 7 27 enum { 28 EFX_EF10_TEST = 1, 29 EFX_EF10_REFILL, 30 }; 31 32 /* The reserved RSS context value */ 33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff 34 /* The maximum size of a shared RSS context */ 35 /* TODO: this should really be from the mcdi protocol export */ 36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL 37 38 /* The filter table(s) are managed by firmware and we have write-only 39 * access. When removing filters we must identify them to the 40 * firmware by a 64-bit handle, but this is too wide for Linux kernel 41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to 42 * be able to tell in advance whether a requested insertion will 43 * replace an existing filter. Therefore we maintain a software hash 44 * table, which should be at least as large as the hardware hash 45 * table. 46 * 47 * Huntington has a single 8K filter table shared between all filter 48 * types and both ports. 49 */ 50 #define HUNT_FILTER_TBL_ROWS 8192 51 52 #define EFX_EF10_FILTER_ID_INVALID 0xffff 53 54 #define EFX_EF10_FILTER_DEV_UC_MAX 32 55 #define EFX_EF10_FILTER_DEV_MC_MAX 256 56 57 /* VLAN list entry */ 58 struct efx_ef10_vlan { 59 struct list_head list; 60 u16 vid; 61 }; 62 63 /* Per-VLAN filters information */ 64 struct efx_ef10_filter_vlan { 65 struct list_head list; 66 u16 vid; 67 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX]; 68 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX]; 69 u16 ucdef; 70 u16 bcast; 71 u16 mcdef; 72 }; 73 74 struct efx_ef10_dev_addr { 75 u8 addr[ETH_ALEN]; 76 }; 77 78 struct efx_ef10_filter_table { 79 /* The MCDI match masks supported by this fw & hw, in order of priority */ 80 u32 rx_match_mcdi_flags[ 81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM]; 82 unsigned int rx_match_count; 83 84 struct { 85 unsigned long spec; /* pointer to spec plus flag bits */ 86 /* BUSY flag indicates that an update is in progress. AUTO_OLD is 87 * used to mark and sweep MAC filters for the device address lists. 88 */ 89 #define EFX_EF10_FILTER_FLAG_BUSY 1UL 90 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL 91 #define EFX_EF10_FILTER_FLAGS 3UL 92 u64 handle; /* firmware handle */ 93 } *entry; 94 wait_queue_head_t waitq; 95 /* Shadow of net_device address lists, guarded by mac_lock */ 96 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX]; 97 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX]; 98 int dev_uc_count; 99 int dev_mc_count; 100 bool uc_promisc; 101 bool mc_promisc; 102 /* Whether in multicast promiscuous mode when last changed */ 103 bool mc_promisc_last; 104 bool vlan_filter; 105 struct list_head vlan_list; 106 }; 107 108 /* An arbitrary search limit for the software hash table */ 109 #define EFX_EF10_FILTER_SEARCH_LIMIT 200 110 111 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx); 112 static void efx_ef10_filter_table_remove(struct efx_nic *efx); 113 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid); 114 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx, 115 struct efx_ef10_filter_vlan *vlan); 116 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid); 117 118 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 119 { 120 efx_dword_t reg; 121 122 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 123 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 124 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 125 } 126 127 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 128 { 129 int bar; 130 131 bar = efx->type->mem_bar; 132 return resource_size(&efx->pci_dev->resource[bar]); 133 } 134 135 static bool efx_ef10_is_vf(struct efx_nic *efx) 136 { 137 return efx->type->is_vf; 138 } 139 140 static int efx_ef10_get_pf_index(struct efx_nic *efx) 141 { 142 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 143 struct efx_ef10_nic_data *nic_data = efx->nic_data; 144 size_t outlen; 145 int rc; 146 147 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 148 sizeof(outbuf), &outlen); 149 if (rc) 150 return rc; 151 if (outlen < sizeof(outbuf)) 152 return -EIO; 153 154 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF); 155 return 0; 156 } 157 158 #ifdef CONFIG_SFC_SRIOV 159 static int efx_ef10_get_vf_index(struct efx_nic *efx) 160 { 161 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 162 struct efx_ef10_nic_data *nic_data = efx->nic_data; 163 size_t outlen; 164 int rc; 165 166 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 167 sizeof(outbuf), &outlen); 168 if (rc) 169 return rc; 170 if (outlen < sizeof(outbuf)) 171 return -EIO; 172 173 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 174 return 0; 175 } 176 #endif 177 178 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 179 { 180 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN); 181 struct efx_ef10_nic_data *nic_data = efx->nic_data; 182 size_t outlen; 183 int rc; 184 185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 186 187 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 188 outbuf, sizeof(outbuf), &outlen); 189 if (rc) 190 return rc; 191 if (outlen < sizeof(outbuf)) { 192 netif_err(efx, drv, efx->net_dev, 193 "unable to read datapath firmware capabilities\n"); 194 return -EIO; 195 } 196 197 nic_data->datapath_caps = 198 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 199 200 /* record the DPCPU firmware IDs to determine VEB vswitching support. 201 */ 202 nic_data->rx_dpcpu_fw_id = 203 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 204 nic_data->tx_dpcpu_fw_id = 205 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 206 207 if (!(nic_data->datapath_caps & 208 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 209 netif_err(efx, probe, efx->net_dev, 210 "current firmware does not support an RX prefix\n"); 211 return -ENODEV; 212 } 213 214 return 0; 215 } 216 217 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 218 { 219 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 220 int rc; 221 222 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 223 outbuf, sizeof(outbuf), NULL); 224 if (rc) 225 return rc; 226 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 227 return rc > 0 ? rc : -ERANGE; 228 } 229 230 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 231 { 232 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 233 size_t outlen; 234 int rc; 235 236 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 237 238 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 239 outbuf, sizeof(outbuf), &outlen); 240 if (rc) 241 return rc; 242 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 243 return -EIO; 244 245 ether_addr_copy(mac_address, 246 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 247 return 0; 248 } 249 250 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 251 { 252 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 253 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 254 size_t outlen; 255 int num_addrs, rc; 256 257 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 258 EVB_PORT_ID_ASSIGNED); 259 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 260 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 261 262 if (rc) 263 return rc; 264 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 265 return -EIO; 266 267 num_addrs = MCDI_DWORD(outbuf, 268 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 269 270 WARN_ON(num_addrs != 1); 271 272 ether_addr_copy(mac_address, 273 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 274 275 return 0; 276 } 277 278 static ssize_t efx_ef10_show_link_control_flag(struct device *dev, 279 struct device_attribute *attr, 280 char *buf) 281 { 282 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 283 284 return sprintf(buf, "%d\n", 285 ((efx->mcdi->fn_flags) & 286 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 287 ? 1 : 0); 288 } 289 290 static ssize_t efx_ef10_show_primary_flag(struct device *dev, 291 struct device_attribute *attr, 292 char *buf) 293 { 294 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 295 296 return sprintf(buf, "%d\n", 297 ((efx->mcdi->fn_flags) & 298 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 299 ? 1 : 0); 300 } 301 302 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid) 303 { 304 struct efx_ef10_nic_data *nic_data = efx->nic_data; 305 struct efx_ef10_vlan *vlan; 306 307 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 308 309 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 310 if (vlan->vid == vid) 311 return vlan; 312 } 313 314 return NULL; 315 } 316 317 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid) 318 { 319 struct efx_ef10_nic_data *nic_data = efx->nic_data; 320 struct efx_ef10_vlan *vlan; 321 int rc; 322 323 mutex_lock(&nic_data->vlan_lock); 324 325 vlan = efx_ef10_find_vlan(efx, vid); 326 if (vlan) { 327 /* We add VID 0 on init. 8021q adds it on module init 328 * for all interfaces with VLAN filtring feature. 329 */ 330 if (vid == 0) 331 goto done_unlock; 332 netif_warn(efx, drv, efx->net_dev, 333 "VLAN %u already added\n", vid); 334 rc = -EALREADY; 335 goto fail_exist; 336 } 337 338 rc = -ENOMEM; 339 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 340 if (!vlan) 341 goto fail_alloc; 342 343 vlan->vid = vid; 344 345 list_add_tail(&vlan->list, &nic_data->vlan_list); 346 347 if (efx->filter_state) { 348 mutex_lock(&efx->mac_lock); 349 down_write(&efx->filter_sem); 350 rc = efx_ef10_filter_add_vlan(efx, vlan->vid); 351 up_write(&efx->filter_sem); 352 mutex_unlock(&efx->mac_lock); 353 if (rc) 354 goto fail_filter_add_vlan; 355 } 356 357 done_unlock: 358 mutex_unlock(&nic_data->vlan_lock); 359 return 0; 360 361 fail_filter_add_vlan: 362 list_del(&vlan->list); 363 kfree(vlan); 364 fail_alloc: 365 fail_exist: 366 mutex_unlock(&nic_data->vlan_lock); 367 return rc; 368 } 369 370 static void efx_ef10_del_vlan_internal(struct efx_nic *efx, 371 struct efx_ef10_vlan *vlan) 372 { 373 struct efx_ef10_nic_data *nic_data = efx->nic_data; 374 375 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 376 377 if (efx->filter_state) { 378 down_write(&efx->filter_sem); 379 efx_ef10_filter_del_vlan(efx, vlan->vid); 380 up_write(&efx->filter_sem); 381 } 382 383 list_del(&vlan->list); 384 kfree(vlan); 385 } 386 387 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid) 388 { 389 struct efx_ef10_nic_data *nic_data = efx->nic_data; 390 struct efx_ef10_vlan *vlan; 391 int rc = 0; 392 393 /* 8021q removes VID 0 on module unload for all interfaces 394 * with VLAN filtering feature. We need to keep it to receive 395 * untagged traffic. 396 */ 397 if (vid == 0) 398 return 0; 399 400 mutex_lock(&nic_data->vlan_lock); 401 402 vlan = efx_ef10_find_vlan(efx, vid); 403 if (!vlan) { 404 netif_err(efx, drv, efx->net_dev, 405 "VLAN %u to be deleted not found\n", vid); 406 rc = -ENOENT; 407 } else { 408 efx_ef10_del_vlan_internal(efx, vlan); 409 } 410 411 mutex_unlock(&nic_data->vlan_lock); 412 413 return rc; 414 } 415 416 static void efx_ef10_cleanup_vlans(struct efx_nic *efx) 417 { 418 struct efx_ef10_nic_data *nic_data = efx->nic_data; 419 struct efx_ef10_vlan *vlan, *next_vlan; 420 421 mutex_lock(&nic_data->vlan_lock); 422 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list) 423 efx_ef10_del_vlan_internal(efx, vlan); 424 mutex_unlock(&nic_data->vlan_lock); 425 } 426 427 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag, 428 NULL); 429 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL); 430 431 static int efx_ef10_probe(struct efx_nic *efx) 432 { 433 struct efx_ef10_nic_data *nic_data; 434 struct net_device *net_dev = efx->net_dev; 435 int i, rc; 436 437 /* We can have one VI for each 8K region. However, until we 438 * use TX option descriptors we need two TX queues per channel. 439 */ 440 efx->max_channels = min_t(unsigned int, 441 EFX_MAX_CHANNELS, 442 efx_ef10_mem_map_size(efx) / 443 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES)); 444 efx->max_tx_channels = efx->max_channels; 445 if (WARN_ON(efx->max_channels == 0)) 446 return -EIO; 447 448 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 449 if (!nic_data) 450 return -ENOMEM; 451 efx->nic_data = nic_data; 452 453 /* we assume later that we can copy from this buffer in dwords */ 454 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 455 456 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 457 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 458 if (rc) 459 goto fail1; 460 461 /* Get the MC's warm boot count. In case it's rebooting right 462 * now, be prepared to retry. 463 */ 464 i = 0; 465 for (;;) { 466 rc = efx_ef10_get_warm_boot_count(efx); 467 if (rc >= 0) 468 break; 469 if (++i == 5) 470 goto fail2; 471 ssleep(1); 472 } 473 nic_data->warm_boot_count = rc; 474 475 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 476 477 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 478 479 /* In case we're recovering from a crash (kexec), we want to 480 * cancel any outstanding request by the previous user of this 481 * function. We send a special message using the least 482 * significant bits of the 'high' (doorbell) register. 483 */ 484 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 485 486 rc = efx_mcdi_init(efx); 487 if (rc) 488 goto fail2; 489 490 /* Reset (most) configuration for this function */ 491 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 492 if (rc) 493 goto fail3; 494 495 /* Enable event logging */ 496 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 497 if (rc) 498 goto fail3; 499 500 rc = device_create_file(&efx->pci_dev->dev, 501 &dev_attr_link_control_flag); 502 if (rc) 503 goto fail3; 504 505 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 506 if (rc) 507 goto fail4; 508 509 rc = efx_ef10_get_pf_index(efx); 510 if (rc) 511 goto fail5; 512 513 rc = efx_ef10_init_datapath_caps(efx); 514 if (rc < 0) 515 goto fail5; 516 517 efx->rx_packet_len_offset = 518 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 519 520 rc = efx_mcdi_port_get_number(efx); 521 if (rc < 0) 522 goto fail5; 523 efx->port_num = rc; 524 net_dev->dev_port = rc; 525 526 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 527 if (rc) 528 goto fail5; 529 530 rc = efx_ef10_get_sysclk_freq(efx); 531 if (rc < 0) 532 goto fail5; 533 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */ 534 535 /* Check whether firmware supports bug 35388 workaround. 536 * First try to enable it, then if we get EPERM, just 537 * ask if it's already enabled 538 */ 539 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL); 540 if (rc == 0) { 541 nic_data->workaround_35388 = true; 542 } else if (rc == -EPERM) { 543 unsigned int enabled; 544 545 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled); 546 if (rc) 547 goto fail3; 548 nic_data->workaround_35388 = enabled & 549 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388; 550 } else if (rc != -ENOSYS && rc != -ENOENT) { 551 goto fail5; 552 } 553 netif_dbg(efx, probe, efx->net_dev, 554 "workaround for bug 35388 is %sabled\n", 555 nic_data->workaround_35388 ? "en" : "dis"); 556 557 rc = efx_mcdi_mon_probe(efx); 558 if (rc && rc != -EPERM) 559 goto fail5; 560 561 efx_ptp_probe(efx, NULL); 562 563 #ifdef CONFIG_SFC_SRIOV 564 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 565 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 566 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 567 568 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 569 } else 570 #endif 571 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 572 573 INIT_LIST_HEAD(&nic_data->vlan_list); 574 mutex_init(&nic_data->vlan_lock); 575 576 /* Add unspecified VID to support VLAN filtering being disabled */ 577 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 578 if (rc) 579 goto fail_add_vid_unspec; 580 581 /* If VLAN filtering is enabled, we need VID 0 to get untagged 582 * traffic. It is added automatically if 8021q module is loaded, 583 * but we can't rely on it since module may be not loaded. 584 */ 585 rc = efx_ef10_add_vlan(efx, 0); 586 if (rc) 587 goto fail_add_vid_0; 588 589 return 0; 590 591 fail_add_vid_0: 592 efx_ef10_cleanup_vlans(efx); 593 fail_add_vid_unspec: 594 mutex_destroy(&nic_data->vlan_lock); 595 efx_ptp_remove(efx); 596 efx_mcdi_mon_remove(efx); 597 fail5: 598 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 599 fail4: 600 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 601 fail3: 602 efx_mcdi_fini(efx); 603 fail2: 604 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 605 fail1: 606 kfree(nic_data); 607 efx->nic_data = NULL; 608 return rc; 609 } 610 611 static int efx_ef10_free_vis(struct efx_nic *efx) 612 { 613 MCDI_DECLARE_BUF_ERR(outbuf); 614 size_t outlen; 615 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, 616 outbuf, sizeof(outbuf), &outlen); 617 618 /* -EALREADY means nothing to free, so ignore */ 619 if (rc == -EALREADY) 620 rc = 0; 621 if (rc) 622 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, 623 rc); 624 return rc; 625 } 626 627 #ifdef EFX_USE_PIO 628 629 static void efx_ef10_free_piobufs(struct efx_nic *efx) 630 { 631 struct efx_ef10_nic_data *nic_data = efx->nic_data; 632 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 633 unsigned int i; 634 int rc; 635 636 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 637 638 for (i = 0; i < nic_data->n_piobufs; i++) { 639 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 640 nic_data->piobuf_handle[i]); 641 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 642 NULL, 0, NULL); 643 WARN_ON(rc); 644 } 645 646 nic_data->n_piobufs = 0; 647 } 648 649 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 650 { 651 struct efx_ef10_nic_data *nic_data = efx->nic_data; 652 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 653 unsigned int i; 654 size_t outlen; 655 int rc = 0; 656 657 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 658 659 for (i = 0; i < n; i++) { 660 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 661 outbuf, sizeof(outbuf), &outlen); 662 if (rc) { 663 /* Don't display the MC error if we didn't have space 664 * for a VF. 665 */ 666 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC)) 667 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF, 668 0, outbuf, outlen, rc); 669 break; 670 } 671 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 672 rc = -EIO; 673 break; 674 } 675 nic_data->piobuf_handle[i] = 676 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 677 netif_dbg(efx, probe, efx->net_dev, 678 "allocated PIO buffer %u handle %x\n", i, 679 nic_data->piobuf_handle[i]); 680 } 681 682 nic_data->n_piobufs = i; 683 if (rc) 684 efx_ef10_free_piobufs(efx); 685 return rc; 686 } 687 688 static int efx_ef10_link_piobufs(struct efx_nic *efx) 689 { 690 struct efx_ef10_nic_data *nic_data = efx->nic_data; 691 _MCDI_DECLARE_BUF(inbuf, 692 max(MC_CMD_LINK_PIOBUF_IN_LEN, 693 MC_CMD_UNLINK_PIOBUF_IN_LEN)); 694 struct efx_channel *channel; 695 struct efx_tx_queue *tx_queue; 696 unsigned int offset, index; 697 int rc; 698 699 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 700 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 701 702 memset(inbuf, 0, sizeof(inbuf)); 703 704 /* Link a buffer to each VI in the write-combining mapping */ 705 for (index = 0; index < nic_data->n_piobufs; ++index) { 706 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 707 nic_data->piobuf_handle[index]); 708 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 709 nic_data->pio_write_vi_base + index); 710 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 711 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 712 NULL, 0, NULL); 713 if (rc) { 714 netif_err(efx, drv, efx->net_dev, 715 "failed to link VI %u to PIO buffer %u (%d)\n", 716 nic_data->pio_write_vi_base + index, index, 717 rc); 718 goto fail; 719 } 720 netif_dbg(efx, probe, efx->net_dev, 721 "linked VI %u to PIO buffer %u\n", 722 nic_data->pio_write_vi_base + index, index); 723 } 724 725 /* Link a buffer to each TX queue */ 726 efx_for_each_channel(channel, efx) { 727 efx_for_each_channel_tx_queue(tx_queue, channel) { 728 /* We assign the PIO buffers to queues in 729 * reverse order to allow for the following 730 * special case. 731 */ 732 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 733 tx_queue->channel->channel - 1) * 734 efx_piobuf_size); 735 index = offset / ER_DZ_TX_PIOBUF_SIZE; 736 offset = offset % ER_DZ_TX_PIOBUF_SIZE; 737 738 /* When the host page size is 4K, the first 739 * host page in the WC mapping may be within 740 * the same VI page as the last TX queue. We 741 * can only link one buffer to each VI. 742 */ 743 if (tx_queue->queue == nic_data->pio_write_vi_base) { 744 BUG_ON(index != 0); 745 rc = 0; 746 } else { 747 MCDI_SET_DWORD(inbuf, 748 LINK_PIOBUF_IN_PIOBUF_HANDLE, 749 nic_data->piobuf_handle[index]); 750 MCDI_SET_DWORD(inbuf, 751 LINK_PIOBUF_IN_TXQ_INSTANCE, 752 tx_queue->queue); 753 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 754 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 755 NULL, 0, NULL); 756 } 757 758 if (rc) { 759 /* This is non-fatal; the TX path just 760 * won't use PIO for this queue 761 */ 762 netif_err(efx, drv, efx->net_dev, 763 "failed to link VI %u to PIO buffer %u (%d)\n", 764 tx_queue->queue, index, rc); 765 tx_queue->piobuf = NULL; 766 } else { 767 tx_queue->piobuf = 768 nic_data->pio_write_base + 769 index * EFX_VI_PAGE_SIZE + offset; 770 tx_queue->piobuf_offset = offset; 771 netif_dbg(efx, probe, efx->net_dev, 772 "linked VI %u to PIO buffer %u offset %x addr %p\n", 773 tx_queue->queue, index, 774 tx_queue->piobuf_offset, 775 tx_queue->piobuf); 776 } 777 } 778 } 779 780 return 0; 781 782 fail: 783 while (index--) { 784 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 785 nic_data->pio_write_vi_base + index); 786 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 787 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 788 NULL, 0, NULL); 789 } 790 return rc; 791 } 792 793 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 794 { 795 struct efx_channel *channel; 796 struct efx_tx_queue *tx_queue; 797 798 /* All our existing PIO buffers went away */ 799 efx_for_each_channel(channel, efx) 800 efx_for_each_channel_tx_queue(tx_queue, channel) 801 tx_queue->piobuf = NULL; 802 } 803 804 #else /* !EFX_USE_PIO */ 805 806 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 807 { 808 return n == 0 ? 0 : -ENOBUFS; 809 } 810 811 static int efx_ef10_link_piobufs(struct efx_nic *efx) 812 { 813 return 0; 814 } 815 816 static void efx_ef10_free_piobufs(struct efx_nic *efx) 817 { 818 } 819 820 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 821 { 822 } 823 824 #endif /* EFX_USE_PIO */ 825 826 static void efx_ef10_remove(struct efx_nic *efx) 827 { 828 struct efx_ef10_nic_data *nic_data = efx->nic_data; 829 int rc; 830 831 #ifdef CONFIG_SFC_SRIOV 832 struct efx_ef10_nic_data *nic_data_pf; 833 struct pci_dev *pci_dev_pf; 834 struct efx_nic *efx_pf; 835 struct ef10_vf *vf; 836 837 if (efx->pci_dev->is_virtfn) { 838 pci_dev_pf = efx->pci_dev->physfn; 839 if (pci_dev_pf) { 840 efx_pf = pci_get_drvdata(pci_dev_pf); 841 nic_data_pf = efx_pf->nic_data; 842 vf = nic_data_pf->vf + nic_data->vf_index; 843 vf->efx = NULL; 844 } else 845 netif_info(efx, drv, efx->net_dev, 846 "Could not get the PF id from VF\n"); 847 } 848 #endif 849 850 efx_ef10_cleanup_vlans(efx); 851 mutex_destroy(&nic_data->vlan_lock); 852 853 efx_ptp_remove(efx); 854 855 efx_mcdi_mon_remove(efx); 856 857 efx_ef10_rx_free_indir_table(efx); 858 859 if (nic_data->wc_membase) 860 iounmap(nic_data->wc_membase); 861 862 rc = efx_ef10_free_vis(efx); 863 WARN_ON(rc != 0); 864 865 if (!nic_data->must_restore_piobufs) 866 efx_ef10_free_piobufs(efx); 867 868 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 869 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 870 871 efx_mcdi_fini(efx); 872 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 873 kfree(nic_data); 874 } 875 876 static int efx_ef10_probe_pf(struct efx_nic *efx) 877 { 878 return efx_ef10_probe(efx); 879 } 880 881 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id, 882 u32 *port_flags, u32 *vadaptor_flags, 883 unsigned int *vlan_tags) 884 { 885 struct efx_ef10_nic_data *nic_data = efx->nic_data; 886 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN); 887 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN); 888 size_t outlen; 889 int rc; 890 891 if (nic_data->datapath_caps & 892 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) { 893 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID, 894 port_id); 895 896 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf), 897 outbuf, sizeof(outbuf), &outlen); 898 if (rc) 899 return rc; 900 901 if (outlen < sizeof(outbuf)) { 902 rc = -EIO; 903 return rc; 904 } 905 } 906 907 if (port_flags) 908 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS); 909 if (vadaptor_flags) 910 *vadaptor_flags = 911 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS); 912 if (vlan_tags) 913 *vlan_tags = 914 MCDI_DWORD(outbuf, 915 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS); 916 917 return 0; 918 } 919 920 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 921 { 922 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 923 924 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 925 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 926 NULL, 0, NULL); 927 } 928 929 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 930 { 931 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 932 933 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 934 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 935 NULL, 0, NULL); 936 } 937 938 int efx_ef10_vport_add_mac(struct efx_nic *efx, 939 unsigned int port_id, u8 *mac) 940 { 941 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 942 943 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 944 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 945 946 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 947 sizeof(inbuf), NULL, 0, NULL); 948 } 949 950 int efx_ef10_vport_del_mac(struct efx_nic *efx, 951 unsigned int port_id, u8 *mac) 952 { 953 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 954 955 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 956 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 957 958 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 959 sizeof(inbuf), NULL, 0, NULL); 960 } 961 962 #ifdef CONFIG_SFC_SRIOV 963 static int efx_ef10_probe_vf(struct efx_nic *efx) 964 { 965 int rc; 966 struct pci_dev *pci_dev_pf; 967 968 /* If the parent PF has no VF data structure, it doesn't know about this 969 * VF so fail probe. The VF needs to be re-created. This can happen 970 * if the PF driver is unloaded while the VF is assigned to a guest. 971 */ 972 pci_dev_pf = efx->pci_dev->physfn; 973 if (pci_dev_pf) { 974 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 975 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 976 977 if (!nic_data_pf->vf) { 978 netif_info(efx, drv, efx->net_dev, 979 "The VF cannot link to its parent PF; " 980 "please destroy and re-create the VF\n"); 981 return -EBUSY; 982 } 983 } 984 985 rc = efx_ef10_probe(efx); 986 if (rc) 987 return rc; 988 989 rc = efx_ef10_get_vf_index(efx); 990 if (rc) 991 goto fail; 992 993 if (efx->pci_dev->is_virtfn) { 994 if (efx->pci_dev->physfn) { 995 struct efx_nic *efx_pf = 996 pci_get_drvdata(efx->pci_dev->physfn); 997 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 998 struct efx_ef10_nic_data *nic_data = efx->nic_data; 999 1000 nic_data_p->vf[nic_data->vf_index].efx = efx; 1001 nic_data_p->vf[nic_data->vf_index].pci_dev = 1002 efx->pci_dev; 1003 } else 1004 netif_info(efx, drv, efx->net_dev, 1005 "Could not get the PF id from VF\n"); 1006 } 1007 1008 return 0; 1009 1010 fail: 1011 efx_ef10_remove(efx); 1012 return rc; 1013 } 1014 #else 1015 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 1016 { 1017 return 0; 1018 } 1019 #endif 1020 1021 static int efx_ef10_alloc_vis(struct efx_nic *efx, 1022 unsigned int min_vis, unsigned int max_vis) 1023 { 1024 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); 1025 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); 1026 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1027 size_t outlen; 1028 int rc; 1029 1030 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); 1031 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); 1032 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), 1033 outbuf, sizeof(outbuf), &outlen); 1034 if (rc != 0) 1035 return rc; 1036 1037 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) 1038 return -EIO; 1039 1040 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", 1041 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); 1042 1043 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); 1044 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); 1045 return 0; 1046 } 1047 1048 /* Note that the failure path of this function does not free 1049 * resources, as this will be done by efx_ef10_remove(). 1050 */ 1051 static int efx_ef10_dimension_resources(struct efx_nic *efx) 1052 { 1053 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1054 unsigned int uc_mem_map_size, wc_mem_map_size; 1055 unsigned int min_vis = max(EFX_TXQ_TYPES, 1056 efx_separate_tx_channels ? 2 : 1); 1057 unsigned int channel_vis, pio_write_vi_base, max_vis; 1058 void __iomem *membase; 1059 int rc; 1060 1061 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); 1062 1063 #ifdef EFX_USE_PIO 1064 /* Try to allocate PIO buffers if wanted and if the full 1065 * number of PIO buffers would be sufficient to allocate one 1066 * copy-buffer per TX channel. Failure is non-fatal, as there 1067 * are only a small number of PIO buffers shared between all 1068 * functions of the controller. 1069 */ 1070 if (efx_piobuf_size != 0 && 1071 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 1072 efx->n_tx_channels) { 1073 unsigned int n_piobufs = 1074 DIV_ROUND_UP(efx->n_tx_channels, 1075 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size); 1076 1077 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 1078 if (rc) 1079 netif_err(efx, probe, efx->net_dev, 1080 "failed to allocate PIO buffers (%d)\n", rc); 1081 else 1082 netif_dbg(efx, probe, efx->net_dev, 1083 "allocated %u PIO buffers\n", n_piobufs); 1084 } 1085 #else 1086 nic_data->n_piobufs = 0; 1087 #endif 1088 1089 /* PIO buffers should be mapped with write-combining enabled, 1090 * and we want to make single UC and WC mappings rather than 1091 * several of each (in fact that's the only option if host 1092 * page size is >4K). So we may allocate some extra VIs just 1093 * for writing PIO buffers through. 1094 * 1095 * The UC mapping contains (channel_vis - 1) complete VIs and the 1096 * first half of the next VI. Then the WC mapping begins with 1097 * the second half of this last VI. 1098 */ 1099 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE + 1100 ER_DZ_TX_PIOBUF); 1101 if (nic_data->n_piobufs) { 1102 /* pio_write_vi_base rounds down to give the number of complete 1103 * VIs inside the UC mapping. 1104 */ 1105 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; 1106 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 1107 nic_data->n_piobufs) * 1108 EFX_VI_PAGE_SIZE) - 1109 uc_mem_map_size); 1110 max_vis = pio_write_vi_base + nic_data->n_piobufs; 1111 } else { 1112 pio_write_vi_base = 0; 1113 wc_mem_map_size = 0; 1114 max_vis = channel_vis; 1115 } 1116 1117 /* In case the last attached driver failed to free VIs, do it now */ 1118 rc = efx_ef10_free_vis(efx); 1119 if (rc != 0) 1120 return rc; 1121 1122 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 1123 if (rc != 0) 1124 return rc; 1125 1126 if (nic_data->n_allocated_vis < channel_vis) { 1127 netif_info(efx, drv, efx->net_dev, 1128 "Could not allocate enough VIs to satisfy RSS" 1129 " requirements. Performance may not be optimal.\n"); 1130 /* We didn't get the VIs to populate our channels. 1131 * We could keep what we got but then we'd have more 1132 * interrupts than we need. 1133 * Instead calculate new max_channels and restart 1134 */ 1135 efx->max_channels = nic_data->n_allocated_vis; 1136 efx->max_tx_channels = 1137 nic_data->n_allocated_vis / EFX_TXQ_TYPES; 1138 1139 efx_ef10_free_vis(efx); 1140 return -EAGAIN; 1141 } 1142 1143 /* If we didn't get enough VIs to map all the PIO buffers, free the 1144 * PIO buffers 1145 */ 1146 if (nic_data->n_piobufs && 1147 nic_data->n_allocated_vis < 1148 pio_write_vi_base + nic_data->n_piobufs) { 1149 netif_dbg(efx, probe, efx->net_dev, 1150 "%u VIs are not sufficient to map %u PIO buffers\n", 1151 nic_data->n_allocated_vis, nic_data->n_piobufs); 1152 efx_ef10_free_piobufs(efx); 1153 } 1154 1155 /* Shrink the original UC mapping of the memory BAR */ 1156 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); 1157 if (!membase) { 1158 netif_err(efx, probe, efx->net_dev, 1159 "could not shrink memory BAR to %x\n", 1160 uc_mem_map_size); 1161 return -ENOMEM; 1162 } 1163 iounmap(efx->membase); 1164 efx->membase = membase; 1165 1166 /* Set up the WC mapping if needed */ 1167 if (wc_mem_map_size) { 1168 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 1169 uc_mem_map_size, 1170 wc_mem_map_size); 1171 if (!nic_data->wc_membase) { 1172 netif_err(efx, probe, efx->net_dev, 1173 "could not allocate WC mapping of size %x\n", 1174 wc_mem_map_size); 1175 return -ENOMEM; 1176 } 1177 nic_data->pio_write_vi_base = pio_write_vi_base; 1178 nic_data->pio_write_base = 1179 nic_data->wc_membase + 1180 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF - 1181 uc_mem_map_size); 1182 1183 rc = efx_ef10_link_piobufs(efx); 1184 if (rc) 1185 efx_ef10_free_piobufs(efx); 1186 } 1187 1188 netif_dbg(efx, probe, efx->net_dev, 1189 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 1190 &efx->membase_phys, efx->membase, uc_mem_map_size, 1191 nic_data->wc_membase, wc_mem_map_size); 1192 1193 return 0; 1194 } 1195 1196 static int efx_ef10_init_nic(struct efx_nic *efx) 1197 { 1198 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1199 int rc; 1200 1201 if (nic_data->must_check_datapath_caps) { 1202 rc = efx_ef10_init_datapath_caps(efx); 1203 if (rc) 1204 return rc; 1205 nic_data->must_check_datapath_caps = false; 1206 } 1207 1208 if (nic_data->must_realloc_vis) { 1209 /* We cannot let the number of VIs change now */ 1210 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 1211 nic_data->n_allocated_vis); 1212 if (rc) 1213 return rc; 1214 nic_data->must_realloc_vis = false; 1215 } 1216 1217 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 1218 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 1219 if (rc == 0) { 1220 rc = efx_ef10_link_piobufs(efx); 1221 if (rc) 1222 efx_ef10_free_piobufs(efx); 1223 } 1224 1225 /* Log an error on failure, but this is non-fatal */ 1226 if (rc) 1227 netif_err(efx, drv, efx->net_dev, 1228 "failed to restore PIO buffers (%d)\n", rc); 1229 nic_data->must_restore_piobufs = false; 1230 } 1231 1232 /* don't fail init if RSS setup doesn't work */ 1233 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table); 1234 1235 return 0; 1236 } 1237 1238 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx) 1239 { 1240 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1241 #ifdef CONFIG_SFC_SRIOV 1242 unsigned int i; 1243 #endif 1244 1245 /* All our allocations have been reset */ 1246 nic_data->must_realloc_vis = true; 1247 nic_data->must_restore_filters = true; 1248 nic_data->must_restore_piobufs = true; 1249 efx_ef10_forget_old_piobufs(efx); 1250 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 1251 1252 /* Driver-created vswitches and vports must be re-created */ 1253 nic_data->must_probe_vswitching = true; 1254 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 1255 #ifdef CONFIG_SFC_SRIOV 1256 if (nic_data->vf) 1257 for (i = 0; i < efx->vf_count; i++) 1258 nic_data->vf[i].vport_id = 0; 1259 #endif 1260 } 1261 1262 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1263 { 1264 if (reason == RESET_TYPE_MC_FAILURE) 1265 return RESET_TYPE_DATAPATH; 1266 1267 return efx_mcdi_map_reset_reason(reason); 1268 } 1269 1270 static int efx_ef10_map_reset_flags(u32 *flags) 1271 { 1272 enum { 1273 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1274 ETH_RESET_SHARED_SHIFT), 1275 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1276 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1277 ETH_RESET_PHY | ETH_RESET_MGMT) << 1278 ETH_RESET_SHARED_SHIFT) 1279 }; 1280 1281 /* We assume for now that our PCI function is permitted to 1282 * reset everything. 1283 */ 1284 1285 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1286 *flags &= ~EF10_RESET_MC; 1287 return RESET_TYPE_WORLD; 1288 } 1289 1290 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1291 *flags &= ~EF10_RESET_PORT; 1292 return RESET_TYPE_ALL; 1293 } 1294 1295 /* no invisible reset implemented */ 1296 1297 return -EINVAL; 1298 } 1299 1300 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1301 { 1302 int rc = efx_mcdi_reset(efx, reset_type); 1303 1304 /* Unprivileged functions return -EPERM, but need to return success 1305 * here so that the datapath is brought back up. 1306 */ 1307 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1308 rc = 0; 1309 1310 /* If it was a port reset, trigger reallocation of MC resources. 1311 * Note that on an MC reset nothing needs to be done now because we'll 1312 * detect the MC reset later and handle it then. 1313 * For an FLR, we never get an MC reset event, but the MC has reset all 1314 * resources assigned to us, so we have to trigger reallocation now. 1315 */ 1316 if ((reset_type == RESET_TYPE_ALL || 1317 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1318 efx_ef10_reset_mc_allocations(efx); 1319 return rc; 1320 } 1321 1322 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1323 [EF10_STAT_ ## ext_name] = \ 1324 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1325 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1326 [EF10_STAT_ ## int_name] = \ 1327 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1328 #define EF10_OTHER_STAT(ext_name) \ 1329 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1330 #define GENERIC_SW_STAT(ext_name) \ 1331 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1332 1333 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1334 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1335 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1336 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1337 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1338 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1339 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1340 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1341 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1342 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1343 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1344 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1345 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1346 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1347 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1348 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1349 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1350 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1351 EF10_OTHER_STAT(port_rx_good_bytes), 1352 EF10_OTHER_STAT(port_rx_bad_bytes), 1353 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1354 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1355 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1356 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1357 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1358 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1359 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1360 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1361 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1362 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1363 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1364 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1365 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1366 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1367 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1368 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1369 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1370 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1371 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1372 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1373 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1374 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1375 GENERIC_SW_STAT(rx_nodesc_trunc), 1376 GENERIC_SW_STAT(rx_noskb_drops), 1377 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1378 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1379 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1380 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1381 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1382 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1383 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1384 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1385 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1386 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1387 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1388 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1389 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1390 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1391 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1392 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1393 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1394 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1395 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1396 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1397 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1398 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1399 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1400 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1401 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1402 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1403 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1404 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1405 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1406 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1407 }; 1408 1409 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1410 (1ULL << EF10_STAT_port_tx_packets) | \ 1411 (1ULL << EF10_STAT_port_tx_pause) | \ 1412 (1ULL << EF10_STAT_port_tx_unicast) | \ 1413 (1ULL << EF10_STAT_port_tx_multicast) | \ 1414 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1415 (1ULL << EF10_STAT_port_rx_bytes) | \ 1416 (1ULL << \ 1417 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1418 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1419 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1420 (1ULL << EF10_STAT_port_rx_packets) | \ 1421 (1ULL << EF10_STAT_port_rx_good) | \ 1422 (1ULL << EF10_STAT_port_rx_bad) | \ 1423 (1ULL << EF10_STAT_port_rx_pause) | \ 1424 (1ULL << EF10_STAT_port_rx_control) | \ 1425 (1ULL << EF10_STAT_port_rx_unicast) | \ 1426 (1ULL << EF10_STAT_port_rx_multicast) | \ 1427 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1428 (1ULL << EF10_STAT_port_rx_lt64) | \ 1429 (1ULL << EF10_STAT_port_rx_64) | \ 1430 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1431 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1432 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1433 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1434 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1435 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1436 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1437 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1438 (1ULL << EF10_STAT_port_rx_overflow) | \ 1439 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1440 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1441 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1442 1443 /* These statistics are only provided by the 10G MAC. For a 10G/40G 1444 * switchable port we do not expose these because they might not 1445 * include all the packets they should. 1446 */ 1447 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1448 (1ULL << EF10_STAT_port_tx_lt64) | \ 1449 (1ULL << EF10_STAT_port_tx_64) | \ 1450 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1451 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1452 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1453 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1454 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1455 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1456 1457 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1458 * switchable port we do expose these because the errors will otherwise 1459 * be silent. 1460 */ 1461 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1462 (1ULL << EF10_STAT_port_rx_length_error)) 1463 1464 /* These statistics are only provided if the firmware supports the 1465 * capability PM_AND_RXDP_COUNTERS. 1466 */ 1467 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1468 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1469 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1470 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1471 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1472 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1473 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1474 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1475 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1476 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1477 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1478 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1479 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1480 1481 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1482 { 1483 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1484 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1485 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1486 1487 if (!(efx->mcdi->fn_flags & 1488 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1489 return 0; 1490 1491 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) 1492 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1493 else 1494 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1495 1496 if (nic_data->datapath_caps & 1497 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1498 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1499 1500 return raw_mask; 1501 } 1502 1503 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1504 { 1505 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1506 u64 raw_mask[2]; 1507 1508 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1509 1510 /* Only show vadaptor stats when EVB capability is present */ 1511 if (nic_data->datapath_caps & 1512 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1513 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1514 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1; 1515 } else { 1516 raw_mask[1] = 0; 1517 } 1518 1519 #if BITS_PER_LONG == 64 1520 mask[0] = raw_mask[0]; 1521 mask[1] = raw_mask[1]; 1522 #else 1523 mask[0] = raw_mask[0] & 0xffffffff; 1524 mask[1] = raw_mask[0] >> 32; 1525 mask[2] = raw_mask[1] & 0xffffffff; 1526 mask[3] = raw_mask[1] >> 32; 1527 #endif 1528 } 1529 1530 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1531 { 1532 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1533 1534 efx_ef10_get_stat_mask(efx, mask); 1535 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1536 mask, names); 1537 } 1538 1539 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1540 struct rtnl_link_stats64 *core_stats) 1541 { 1542 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1543 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1544 u64 *stats = nic_data->stats; 1545 size_t stats_count = 0, index; 1546 1547 efx_ef10_get_stat_mask(efx, mask); 1548 1549 if (full_stats) { 1550 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1551 if (efx_ef10_stat_desc[index].name) { 1552 *full_stats++ = stats[index]; 1553 ++stats_count; 1554 } 1555 } 1556 } 1557 1558 if (!core_stats) 1559 return stats_count; 1560 1561 if (nic_data->datapath_caps & 1562 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1563 /* Use vadaptor stats. */ 1564 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1565 stats[EF10_STAT_rx_multicast] + 1566 stats[EF10_STAT_rx_broadcast]; 1567 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1568 stats[EF10_STAT_tx_multicast] + 1569 stats[EF10_STAT_tx_broadcast]; 1570 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1571 stats[EF10_STAT_rx_multicast_bytes] + 1572 stats[EF10_STAT_rx_broadcast_bytes]; 1573 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1574 stats[EF10_STAT_tx_multicast_bytes] + 1575 stats[EF10_STAT_tx_broadcast_bytes]; 1576 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1577 stats[GENERIC_STAT_rx_noskb_drops]; 1578 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1579 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1580 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1581 core_stats->rx_errors = core_stats->rx_crc_errors; 1582 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1583 } else { 1584 /* Use port stats. */ 1585 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1586 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1587 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1588 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1589 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1590 stats[GENERIC_STAT_rx_nodesc_trunc] + 1591 stats[GENERIC_STAT_rx_noskb_drops]; 1592 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1593 core_stats->rx_length_errors = 1594 stats[EF10_STAT_port_rx_gtjumbo] + 1595 stats[EF10_STAT_port_rx_length_error]; 1596 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1597 core_stats->rx_frame_errors = 1598 stats[EF10_STAT_port_rx_align_error]; 1599 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1600 core_stats->rx_errors = (core_stats->rx_length_errors + 1601 core_stats->rx_crc_errors + 1602 core_stats->rx_frame_errors); 1603 } 1604 1605 return stats_count; 1606 } 1607 1608 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx) 1609 { 1610 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1611 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1612 __le64 generation_start, generation_end; 1613 u64 *stats = nic_data->stats; 1614 __le64 *dma_stats; 1615 1616 efx_ef10_get_stat_mask(efx, mask); 1617 1618 dma_stats = efx->stats_buffer.addr; 1619 nic_data = efx->nic_data; 1620 1621 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1622 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 1623 return 0; 1624 rmb(); 1625 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1626 stats, efx->stats_buffer.addr, false); 1627 rmb(); 1628 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1629 if (generation_end != generation_start) 1630 return -EAGAIN; 1631 1632 /* Update derived statistics */ 1633 efx_nic_fix_nodesc_drop_stat(efx, 1634 &stats[EF10_STAT_port_rx_nodesc_drops]); 1635 stats[EF10_STAT_port_rx_good_bytes] = 1636 stats[EF10_STAT_port_rx_bytes] - 1637 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1638 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1639 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1640 efx_update_sw_stats(efx, stats); 1641 return 0; 1642 } 1643 1644 1645 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1646 struct rtnl_link_stats64 *core_stats) 1647 { 1648 int retry; 1649 1650 /* If we're unlucky enough to read statistics during the DMA, wait 1651 * up to 10ms for it to finish (typically takes <500us) 1652 */ 1653 for (retry = 0; retry < 100; ++retry) { 1654 if (efx_ef10_try_update_nic_stats_pf(efx) == 0) 1655 break; 1656 udelay(100); 1657 } 1658 1659 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1660 } 1661 1662 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1663 { 1664 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1665 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1666 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1667 __le64 generation_start, generation_end; 1668 u64 *stats = nic_data->stats; 1669 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64); 1670 struct efx_buffer stats_buf; 1671 __le64 *dma_stats; 1672 int rc; 1673 1674 spin_unlock_bh(&efx->stats_lock); 1675 1676 if (in_interrupt()) { 1677 /* If in atomic context, cannot update stats. Just update the 1678 * software stats and return so the caller can continue. 1679 */ 1680 spin_lock_bh(&efx->stats_lock); 1681 efx_update_sw_stats(efx, stats); 1682 return 0; 1683 } 1684 1685 efx_ef10_get_stat_mask(efx, mask); 1686 1687 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC); 1688 if (rc) { 1689 spin_lock_bh(&efx->stats_lock); 1690 return rc; 1691 } 1692 1693 dma_stats = stats_buf.addr; 1694 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID; 1695 1696 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1697 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1698 MAC_STATS_IN_DMA, 1); 1699 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1700 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1701 1702 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1703 NULL, 0, NULL); 1704 spin_lock_bh(&efx->stats_lock); 1705 if (rc) { 1706 /* Expect ENOENT if DMA queues have not been set up */ 1707 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1708 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1709 sizeof(inbuf), NULL, 0, rc); 1710 goto out; 1711 } 1712 1713 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1714 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1715 WARN_ON_ONCE(1); 1716 goto out; 1717 } 1718 rmb(); 1719 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1720 stats, stats_buf.addr, false); 1721 rmb(); 1722 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1723 if (generation_end != generation_start) { 1724 rc = -EAGAIN; 1725 goto out; 1726 } 1727 1728 efx_update_sw_stats(efx, stats); 1729 out: 1730 efx_nic_free_buffer(efx, &stats_buf); 1731 return rc; 1732 } 1733 1734 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1735 struct rtnl_link_stats64 *core_stats) 1736 { 1737 if (efx_ef10_try_update_nic_stats_vf(efx)) 1738 return 0; 1739 1740 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1741 } 1742 1743 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1744 { 1745 struct efx_nic *efx = channel->efx; 1746 unsigned int mode, value; 1747 efx_dword_t timer_cmd; 1748 1749 if (channel->irq_moderation) { 1750 mode = 3; 1751 value = channel->irq_moderation - 1; 1752 } else { 1753 mode = 0; 1754 value = 0; 1755 } 1756 1757 if (EFX_EF10_WORKAROUND_35388(efx)) { 1758 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1759 EFE_DD_EVQ_IND_TIMER_FLAGS, 1760 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1761 ERF_DD_EVQ_IND_TIMER_VAL, value); 1762 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1763 channel->channel); 1764 } else { 1765 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1766 ERF_DZ_TC_TIMER_VAL, value); 1767 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1768 channel->channel); 1769 } 1770 } 1771 1772 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 1773 struct ethtool_wolinfo *wol) {} 1774 1775 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 1776 { 1777 return -EOPNOTSUPP; 1778 } 1779 1780 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1781 { 1782 wol->supported = 0; 1783 wol->wolopts = 0; 1784 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1785 } 1786 1787 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 1788 { 1789 if (type != 0) 1790 return -EINVAL; 1791 return 0; 1792 } 1793 1794 static void efx_ef10_mcdi_request(struct efx_nic *efx, 1795 const efx_dword_t *hdr, size_t hdr_len, 1796 const efx_dword_t *sdu, size_t sdu_len) 1797 { 1798 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1799 u8 *pdu = nic_data->mcdi_buf.addr; 1800 1801 memcpy(pdu, hdr, hdr_len); 1802 memcpy(pdu + hdr_len, sdu, sdu_len); 1803 wmb(); 1804 1805 /* The hardware provides 'low' and 'high' (doorbell) registers 1806 * for passing the 64-bit address of an MCDI request to 1807 * firmware. However the dwords are swapped by firmware. The 1808 * least significant bits of the doorbell are then 0 for all 1809 * MCDI requests due to alignment. 1810 */ 1811 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 1812 ER_DZ_MC_DB_LWRD); 1813 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 1814 ER_DZ_MC_DB_HWRD); 1815 } 1816 1817 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 1818 { 1819 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1820 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 1821 1822 rmb(); 1823 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 1824 } 1825 1826 static void 1827 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 1828 size_t offset, size_t outlen) 1829 { 1830 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1831 const u8 *pdu = nic_data->mcdi_buf.addr; 1832 1833 memcpy(outbuf, pdu + offset, outlen); 1834 } 1835 1836 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 1837 { 1838 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1839 1840 /* All our allocations have been reset */ 1841 efx_ef10_reset_mc_allocations(efx); 1842 1843 /* The datapath firmware might have been changed */ 1844 nic_data->must_check_datapath_caps = true; 1845 1846 /* MAC statistics have been cleared on the NIC; clear the local 1847 * statistic that we update with efx_update_diff_stat(). 1848 */ 1849 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 1850 } 1851 1852 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 1853 { 1854 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1855 int rc; 1856 1857 rc = efx_ef10_get_warm_boot_count(efx); 1858 if (rc < 0) { 1859 /* The firmware is presumably in the process of 1860 * rebooting. However, we are supposed to report each 1861 * reboot just once, so we must only do that once we 1862 * can read and store the updated warm boot count. 1863 */ 1864 return 0; 1865 } 1866 1867 if (rc == nic_data->warm_boot_count) 1868 return 0; 1869 1870 nic_data->warm_boot_count = rc; 1871 efx_ef10_mcdi_reboot_detected(efx); 1872 1873 return -EIO; 1874 } 1875 1876 /* Handle an MSI interrupt 1877 * 1878 * Handle an MSI hardware interrupt. This routine schedules event 1879 * queue processing. No interrupt acknowledgement cycle is necessary. 1880 * Also, we never need to check that the interrupt is for us, since 1881 * MSI interrupts cannot be shared. 1882 */ 1883 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 1884 { 1885 struct efx_msi_context *context = dev_id; 1886 struct efx_nic *efx = context->efx; 1887 1888 netif_vdbg(efx, intr, efx->net_dev, 1889 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 1890 1891 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) { 1892 /* Note test interrupts */ 1893 if (context->index == efx->irq_level) 1894 efx->last_irq_cpu = raw_smp_processor_id(); 1895 1896 /* Schedule processing of the channel */ 1897 efx_schedule_channel_irq(efx->channel[context->index]); 1898 } 1899 1900 return IRQ_HANDLED; 1901 } 1902 1903 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 1904 { 1905 struct efx_nic *efx = dev_id; 1906 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); 1907 struct efx_channel *channel; 1908 efx_dword_t reg; 1909 u32 queues; 1910 1911 /* Read the ISR which also ACKs the interrupts */ 1912 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 1913 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 1914 1915 if (queues == 0) 1916 return IRQ_NONE; 1917 1918 if (likely(soft_enabled)) { 1919 /* Note test interrupts */ 1920 if (queues & (1U << efx->irq_level)) 1921 efx->last_irq_cpu = raw_smp_processor_id(); 1922 1923 efx_for_each_channel(channel, efx) { 1924 if (queues & 1) 1925 efx_schedule_channel_irq(channel); 1926 queues >>= 1; 1927 } 1928 } 1929 1930 netif_vdbg(efx, intr, efx->net_dev, 1931 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 1932 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 1933 1934 return IRQ_HANDLED; 1935 } 1936 1937 static void efx_ef10_irq_test_generate(struct efx_nic *efx) 1938 { 1939 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 1940 1941 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 1942 1943 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 1944 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 1945 inbuf, sizeof(inbuf), NULL, 0, NULL); 1946 } 1947 1948 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 1949 { 1950 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 1951 (tx_queue->ptr_mask + 1) * 1952 sizeof(efx_qword_t), 1953 GFP_KERNEL); 1954 } 1955 1956 /* This writes to the TX_DESC_WPTR and also pushes data */ 1957 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 1958 const efx_qword_t *txd) 1959 { 1960 unsigned int write_ptr; 1961 efx_oword_t reg; 1962 1963 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1964 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 1965 reg.qword[0] = *txd; 1966 efx_writeo_page(tx_queue->efx, ®, 1967 ER_DZ_TX_DESC_UPD, tx_queue->queue); 1968 } 1969 1970 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 1971 { 1972 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 1973 EFX_BUF_SIZE)); 1974 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 1975 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; 1976 struct efx_channel *channel = tx_queue->channel; 1977 struct efx_nic *efx = tx_queue->efx; 1978 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1979 size_t inlen; 1980 dma_addr_t dma_addr; 1981 efx_qword_t *txd; 1982 int rc; 1983 int i; 1984 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0); 1985 1986 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); 1987 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); 1988 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); 1989 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); 1990 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS, 1991 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, 1992 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload); 1993 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); 1994 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id); 1995 1996 dma_addr = tx_queue->txd.buf.dma_addr; 1997 1998 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", 1999 tx_queue->queue, entries, (u64)dma_addr); 2000 2001 for (i = 0; i < entries; ++i) { 2002 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); 2003 dma_addr += EFX_BUF_SIZE; 2004 } 2005 2006 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); 2007 2008 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen, 2009 NULL, 0, NULL); 2010 if (rc) 2011 goto fail; 2012 2013 /* A previous user of this TX queue might have set us up the 2014 * bomb by writing a descriptor to the TX push collector but 2015 * not the doorbell. (Each collector belongs to a port, not a 2016 * queue or function, so cannot easily be reset.) We must 2017 * attempt to push a no-op descriptor in its place. 2018 */ 2019 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 2020 tx_queue->insert_count = 1; 2021 txd = efx_tx_desc(tx_queue, 0); 2022 EFX_POPULATE_QWORD_4(*txd, 2023 ESF_DZ_TX_DESC_IS_OPT, true, 2024 ESF_DZ_TX_OPTION_TYPE, 2025 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 2026 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 2027 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload); 2028 tx_queue->write_count = 1; 2029 2030 if (nic_data->datapath_caps & 2031 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) { 2032 tx_queue->tso_version = 1; 2033 } 2034 2035 wmb(); 2036 efx_ef10_push_tx_desc(tx_queue, txd); 2037 2038 return; 2039 2040 fail: 2041 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 2042 tx_queue->queue); 2043 } 2044 2045 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue) 2046 { 2047 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); 2048 MCDI_DECLARE_BUF_ERR(outbuf); 2049 struct efx_nic *efx = tx_queue->efx; 2050 size_t outlen; 2051 int rc; 2052 2053 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, 2054 tx_queue->queue); 2055 2056 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), 2057 outbuf, sizeof(outbuf), &outlen); 2058 2059 if (rc && rc != -EALREADY) 2060 goto fail; 2061 2062 return; 2063 2064 fail: 2065 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, 2066 outbuf, outlen, rc); 2067 } 2068 2069 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue) 2070 { 2071 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); 2072 } 2073 2074 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 2075 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 2076 { 2077 unsigned int write_ptr; 2078 efx_dword_t reg; 2079 2080 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2081 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 2082 efx_writed_page(tx_queue->efx, ®, 2083 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 2084 } 2085 2086 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 2087 { 2088 unsigned int old_write_count = tx_queue->write_count; 2089 struct efx_tx_buffer *buffer; 2090 unsigned int write_ptr; 2091 efx_qword_t *txd; 2092 2093 tx_queue->xmit_more_available = false; 2094 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 2095 return; 2096 2097 do { 2098 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2099 buffer = &tx_queue->buffer[write_ptr]; 2100 txd = efx_tx_desc(tx_queue, write_ptr); 2101 ++tx_queue->write_count; 2102 2103 /* Create TX descriptor ring entry */ 2104 if (buffer->flags & EFX_TX_BUF_OPTION) { 2105 *txd = buffer->option; 2106 } else { 2107 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 2108 EFX_POPULATE_QWORD_3( 2109 *txd, 2110 ESF_DZ_TX_KER_CONT, 2111 buffer->flags & EFX_TX_BUF_CONT, 2112 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 2113 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 2114 } 2115 } while (tx_queue->write_count != tx_queue->insert_count); 2116 2117 wmb(); /* Ensure descriptors are written before they are fetched */ 2118 2119 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 2120 txd = efx_tx_desc(tx_queue, 2121 old_write_count & tx_queue->ptr_mask); 2122 efx_ef10_push_tx_desc(tx_queue, txd); 2123 ++tx_queue->pushes; 2124 } else { 2125 efx_ef10_notify_tx_desc(tx_queue); 2126 } 2127 } 2128 2129 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context, 2130 bool exclusive, unsigned *context_size) 2131 { 2132 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN); 2133 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN); 2134 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2135 size_t outlen; 2136 int rc; 2137 u32 alloc_type = exclusive ? 2138 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE : 2139 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED; 2140 unsigned rss_spread = exclusive ? 2141 efx->rss_spread : 2142 min(rounddown_pow_of_two(efx->rss_spread), 2143 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE); 2144 2145 if (!exclusive && rss_spread == 1) { 2146 *context = EFX_EF10_RSS_CONTEXT_INVALID; 2147 if (context_size) 2148 *context_size = 1; 2149 return 0; 2150 } 2151 2152 if (nic_data->datapath_caps & 2153 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN) 2154 return -EOPNOTSUPP; 2155 2156 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, 2157 nic_data->vport_id); 2158 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type); 2159 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread); 2160 2161 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf), 2162 outbuf, sizeof(outbuf), &outlen); 2163 if (rc != 0) 2164 return rc; 2165 2166 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) 2167 return -EIO; 2168 2169 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); 2170 2171 if (context_size) 2172 *context_size = rss_spread; 2173 2174 return 0; 2175 } 2176 2177 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context) 2178 { 2179 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN); 2180 int rc; 2181 2182 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, 2183 context); 2184 2185 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf), 2186 NULL, 0, NULL); 2187 WARN_ON(rc != 0); 2188 } 2189 2190 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context, 2191 const u32 *rx_indir_table) 2192 { 2193 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN); 2194 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN); 2195 int i, rc; 2196 2197 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, 2198 context); 2199 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != 2200 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN); 2201 2202 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i) 2203 MCDI_PTR(tablebuf, 2204 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] = 2205 (u8) rx_indir_table[i]; 2206 2207 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf, 2208 sizeof(tablebuf), NULL, 0, NULL); 2209 if (rc != 0) 2210 return rc; 2211 2212 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, 2213 context); 2214 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) != 2215 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); 2216 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i) 2217 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = 2218 efx->rx_hash_key[i]; 2219 2220 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf, 2221 sizeof(keybuf), NULL, 0, NULL); 2222 } 2223 2224 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx) 2225 { 2226 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2227 2228 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 2229 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context); 2230 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 2231 } 2232 2233 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx, 2234 unsigned *context_size) 2235 { 2236 u32 new_rx_rss_context; 2237 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2238 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 2239 false, context_size); 2240 2241 if (rc != 0) 2242 return rc; 2243 2244 nic_data->rx_rss_context = new_rx_rss_context; 2245 nic_data->rx_rss_context_exclusive = false; 2246 efx_set_default_rx_indir_table(efx); 2247 return 0; 2248 } 2249 2250 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx, 2251 const u32 *rx_indir_table) 2252 { 2253 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2254 int rc; 2255 u32 new_rx_rss_context; 2256 2257 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID || 2258 !nic_data->rx_rss_context_exclusive) { 2259 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 2260 true, NULL); 2261 if (rc == -EOPNOTSUPP) 2262 return rc; 2263 else if (rc != 0) 2264 goto fail1; 2265 } else { 2266 new_rx_rss_context = nic_data->rx_rss_context; 2267 } 2268 2269 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context, 2270 rx_indir_table); 2271 if (rc != 0) 2272 goto fail2; 2273 2274 if (nic_data->rx_rss_context != new_rx_rss_context) 2275 efx_ef10_rx_free_indir_table(efx); 2276 nic_data->rx_rss_context = new_rx_rss_context; 2277 nic_data->rx_rss_context_exclusive = true; 2278 if (rx_indir_table != efx->rx_indir_table) 2279 memcpy(efx->rx_indir_table, rx_indir_table, 2280 sizeof(efx->rx_indir_table)); 2281 return 0; 2282 2283 fail2: 2284 if (new_rx_rss_context != nic_data->rx_rss_context) 2285 efx_ef10_free_rss_context(efx, new_rx_rss_context); 2286 fail1: 2287 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 2288 return rc; 2289 } 2290 2291 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user, 2292 const u32 *rx_indir_table) 2293 { 2294 int rc; 2295 2296 if (efx->rss_spread == 1) 2297 return 0; 2298 2299 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table); 2300 2301 if (rc == -ENOBUFS && !user) { 2302 unsigned context_size; 2303 bool mismatch = false; 2304 size_t i; 2305 2306 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch; 2307 i++) 2308 mismatch = rx_indir_table[i] != 2309 ethtool_rxfh_indir_default(i, efx->rss_spread); 2310 2311 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size); 2312 if (rc == 0) { 2313 if (context_size != efx->rss_spread) 2314 netif_warn(efx, probe, efx->net_dev, 2315 "Could not allocate an exclusive RSS" 2316 " context; allocated a shared one of" 2317 " different size." 2318 " Wanted %u, got %u.\n", 2319 efx->rss_spread, context_size); 2320 else if (mismatch) 2321 netif_warn(efx, probe, efx->net_dev, 2322 "Could not allocate an exclusive RSS" 2323 " context; allocated a shared one but" 2324 " could not apply custom" 2325 " indirection.\n"); 2326 else 2327 netif_info(efx, probe, efx->net_dev, 2328 "Could not allocate an exclusive RSS" 2329 " context; allocated a shared one.\n"); 2330 } 2331 } 2332 return rc; 2333 } 2334 2335 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user, 2336 const u32 *rx_indir_table 2337 __attribute__ ((unused))) 2338 { 2339 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2340 2341 if (user) 2342 return -EOPNOTSUPP; 2343 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 2344 return 0; 2345 return efx_ef10_rx_push_shared_rss_config(efx, NULL); 2346 } 2347 2348 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue) 2349 { 2350 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, 2351 (rx_queue->ptr_mask + 1) * 2352 sizeof(efx_qword_t), 2353 GFP_KERNEL); 2354 } 2355 2356 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue) 2357 { 2358 MCDI_DECLARE_BUF(inbuf, 2359 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 2360 EFX_BUF_SIZE)); 2361 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2362 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; 2363 struct efx_nic *efx = rx_queue->efx; 2364 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2365 size_t inlen; 2366 dma_addr_t dma_addr; 2367 int rc; 2368 int i; 2369 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0); 2370 2371 rx_queue->scatter_n = 0; 2372 rx_queue->scatter_len = 0; 2373 2374 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); 2375 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); 2376 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); 2377 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, 2378 efx_rx_queue_index(rx_queue)); 2379 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, 2380 INIT_RXQ_IN_FLAG_PREFIX, 1, 2381 INIT_RXQ_IN_FLAG_TIMESTAMP, 1); 2382 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); 2383 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id); 2384 2385 dma_addr = rx_queue->rxd.buf.dma_addr; 2386 2387 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", 2388 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); 2389 2390 for (i = 0; i < entries; ++i) { 2391 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); 2392 dma_addr += EFX_BUF_SIZE; 2393 } 2394 2395 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); 2396 2397 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, 2398 NULL, 0, NULL); 2399 if (rc) 2400 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", 2401 efx_rx_queue_index(rx_queue)); 2402 } 2403 2404 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue) 2405 { 2406 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); 2407 MCDI_DECLARE_BUF_ERR(outbuf); 2408 struct efx_nic *efx = rx_queue->efx; 2409 size_t outlen; 2410 int rc; 2411 2412 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, 2413 efx_rx_queue_index(rx_queue)); 2414 2415 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), 2416 outbuf, sizeof(outbuf), &outlen); 2417 2418 if (rc && rc != -EALREADY) 2419 goto fail; 2420 2421 return; 2422 2423 fail: 2424 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, 2425 outbuf, outlen, rc); 2426 } 2427 2428 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue) 2429 { 2430 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); 2431 } 2432 2433 /* This creates an entry in the RX descriptor queue */ 2434 static inline void 2435 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2436 { 2437 struct efx_rx_buffer *rx_buf; 2438 efx_qword_t *rxd; 2439 2440 rxd = efx_rx_desc(rx_queue, index); 2441 rx_buf = efx_rx_buffer(rx_queue, index); 2442 EFX_POPULATE_QWORD_2(*rxd, 2443 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2444 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2445 } 2446 2447 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2448 { 2449 struct efx_nic *efx = rx_queue->efx; 2450 unsigned int write_count; 2451 efx_dword_t reg; 2452 2453 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2454 write_count = rx_queue->added_count & ~7; 2455 if (rx_queue->notified_count == write_count) 2456 return; 2457 2458 do 2459 efx_ef10_build_rx_desc( 2460 rx_queue, 2461 rx_queue->notified_count & rx_queue->ptr_mask); 2462 while (++rx_queue->notified_count != write_count); 2463 2464 wmb(); 2465 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2466 write_count & rx_queue->ptr_mask); 2467 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2468 efx_rx_queue_index(rx_queue)); 2469 } 2470 2471 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2472 2473 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2474 { 2475 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2476 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2477 efx_qword_t event; 2478 2479 EFX_POPULATE_QWORD_2(event, 2480 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2481 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2482 2483 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2484 2485 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2486 * already swapped the data to little-endian order. 2487 */ 2488 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2489 sizeof(efx_qword_t)); 2490 2491 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2492 inbuf, sizeof(inbuf), 0, 2493 efx_ef10_rx_defer_refill_complete, 0); 2494 } 2495 2496 static void 2497 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2498 int rc, efx_dword_t *outbuf, 2499 size_t outlen_actual) 2500 { 2501 /* nothing to do */ 2502 } 2503 2504 static int efx_ef10_ev_probe(struct efx_channel *channel) 2505 { 2506 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 2507 (channel->eventq_mask + 1) * 2508 sizeof(efx_qword_t), 2509 GFP_KERNEL); 2510 } 2511 2512 static void efx_ef10_ev_fini(struct efx_channel *channel) 2513 { 2514 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); 2515 MCDI_DECLARE_BUF_ERR(outbuf); 2516 struct efx_nic *efx = channel->efx; 2517 size_t outlen; 2518 int rc; 2519 2520 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); 2521 2522 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), 2523 outbuf, sizeof(outbuf), &outlen); 2524 2525 if (rc && rc != -EALREADY) 2526 goto fail; 2527 2528 return; 2529 2530 fail: 2531 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, 2532 outbuf, outlen, rc); 2533 } 2534 2535 static int efx_ef10_ev_init(struct efx_channel *channel) 2536 { 2537 MCDI_DECLARE_BUF(inbuf, 2538 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / 2539 EFX_BUF_SIZE)); 2540 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN); 2541 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; 2542 struct efx_nic *efx = channel->efx; 2543 struct efx_ef10_nic_data *nic_data; 2544 bool supports_rx_merge; 2545 size_t inlen, outlen; 2546 unsigned int enabled, implemented; 2547 dma_addr_t dma_addr; 2548 int rc; 2549 int i; 2550 2551 nic_data = efx->nic_data; 2552 supports_rx_merge = 2553 !!(nic_data->datapath_caps & 2554 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2555 2556 /* Fill event queue with all ones (i.e. empty events) */ 2557 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); 2558 2559 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); 2560 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); 2561 /* INIT_EVQ expects index in vector table, not absolute */ 2562 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); 2563 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, 2564 INIT_EVQ_IN_FLAG_INTERRUPTING, 1, 2565 INIT_EVQ_IN_FLAG_RX_MERGE, 1, 2566 INIT_EVQ_IN_FLAG_TX_MERGE, 1, 2567 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge); 2568 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, 2569 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); 2570 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); 2571 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); 2572 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, 2573 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); 2574 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); 2575 2576 dma_addr = channel->eventq.buf.dma_addr; 2577 for (i = 0; i < entries; ++i) { 2578 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); 2579 dma_addr += EFX_BUF_SIZE; 2580 } 2581 2582 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); 2583 2584 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, 2585 outbuf, sizeof(outbuf), &outlen); 2586 /* IRQ return is ignored */ 2587 if (channel->channel || rc) 2588 return rc; 2589 2590 /* Successfully created event queue on channel 0 */ 2591 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2592 if (rc == -ENOSYS) { 2593 /* GET_WORKAROUNDS was implemented before the bug26807 2594 * workaround, thus the latter must be unavailable in this fw 2595 */ 2596 nic_data->workaround_26807 = false; 2597 rc = 0; 2598 } else if (rc) { 2599 goto fail; 2600 } else { 2601 nic_data->workaround_26807 = 2602 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2603 2604 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 && 2605 !nic_data->workaround_26807) { 2606 unsigned int flags; 2607 2608 rc = efx_mcdi_set_workaround(efx, 2609 MC_CMD_WORKAROUND_BUG26807, 2610 true, &flags); 2611 2612 if (!rc) { 2613 if (flags & 2614 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2615 netif_info(efx, drv, efx->net_dev, 2616 "other functions on NIC have been reset\n"); 2617 2618 /* With MCFW v4.6.x and earlier, the 2619 * boot count will have incremented, 2620 * so re-read the warm_boot_count 2621 * value now to ensure this function 2622 * doesn't think it has changed next 2623 * time it checks. 2624 */ 2625 rc = efx_ef10_get_warm_boot_count(efx); 2626 if (rc >= 0) { 2627 nic_data->warm_boot_count = rc; 2628 rc = 0; 2629 } 2630 } 2631 nic_data->workaround_26807 = true; 2632 } else if (rc == -EPERM) { 2633 rc = 0; 2634 } 2635 } 2636 } 2637 2638 if (!rc) 2639 return 0; 2640 2641 fail: 2642 efx_ef10_ev_fini(channel); 2643 return rc; 2644 } 2645 2646 static void efx_ef10_ev_remove(struct efx_channel *channel) 2647 { 2648 efx_nic_free_buffer(channel->efx, &channel->eventq.buf); 2649 } 2650 2651 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2652 unsigned int rx_queue_label) 2653 { 2654 struct efx_nic *efx = rx_queue->efx; 2655 2656 netif_info(efx, hw, efx->net_dev, 2657 "rx event arrived on queue %d labeled as queue %u\n", 2658 efx_rx_queue_index(rx_queue), rx_queue_label); 2659 2660 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2661 } 2662 2663 static void 2664 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2665 unsigned int actual, unsigned int expected) 2666 { 2667 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2668 struct efx_nic *efx = rx_queue->efx; 2669 2670 netif_info(efx, hw, efx->net_dev, 2671 "dropped %d events (index=%d expected=%d)\n", 2672 dropped, actual, expected); 2673 2674 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2675 } 2676 2677 /* partially received RX was aborted. clean up. */ 2678 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2679 { 2680 unsigned int rx_desc_ptr; 2681 2682 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2683 "scattered RX aborted (dropping %u buffers)\n", 2684 rx_queue->scatter_n); 2685 2686 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2687 2688 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2689 0, EFX_RX_PKT_DISCARD); 2690 2691 rx_queue->removed_count += rx_queue->scatter_n; 2692 rx_queue->scatter_n = 0; 2693 rx_queue->scatter_len = 0; 2694 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2695 } 2696 2697 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2698 const efx_qword_t *event) 2699 { 2700 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class; 2701 unsigned int n_descs, n_packets, i; 2702 struct efx_nic *efx = channel->efx; 2703 struct efx_rx_queue *rx_queue; 2704 bool rx_cont; 2705 u16 flags = 0; 2706 2707 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 2708 return 0; 2709 2710 /* Basic packet information */ 2711 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2712 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2713 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2714 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); 2715 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2716 2717 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2718 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2719 EFX_QWORD_FMT "\n", 2720 EFX_QWORD_VAL(*event)); 2721 2722 rx_queue = efx_channel_get_rx_queue(channel); 2723 2724 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2725 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2726 2727 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2728 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2729 2730 if (n_descs != rx_queue->scatter_n + 1) { 2731 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2732 2733 /* detect rx abort */ 2734 if (unlikely(n_descs == rx_queue->scatter_n)) { 2735 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2736 netdev_WARN(efx->net_dev, 2737 "invalid RX abort: scatter_n=%u event=" 2738 EFX_QWORD_FMT "\n", 2739 rx_queue->scatter_n, 2740 EFX_QWORD_VAL(*event)); 2741 efx_ef10_handle_rx_abort(rx_queue); 2742 return 0; 2743 } 2744 2745 /* Check that RX completion merging is valid, i.e. 2746 * the current firmware supports it and this is a 2747 * non-scattered packet. 2748 */ 2749 if (!(nic_data->datapath_caps & 2750 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2751 rx_queue->scatter_n != 0 || rx_cont) { 2752 efx_ef10_handle_rx_bad_lbits( 2753 rx_queue, next_ptr_lbits, 2754 (rx_queue->removed_count + 2755 rx_queue->scatter_n + 1) & 2756 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2757 return 0; 2758 } 2759 2760 /* Merged completion for multiple non-scattered packets */ 2761 rx_queue->scatter_n = 1; 2762 rx_queue->scatter_len = 0; 2763 n_packets = n_descs; 2764 ++channel->n_rx_merge_events; 2765 channel->n_rx_merge_packets += n_packets; 2766 flags |= EFX_RX_PKT_PREFIX_LEN; 2767 } else { 2768 ++rx_queue->scatter_n; 2769 rx_queue->scatter_len += rx_bytes; 2770 if (rx_cont) 2771 return 0; 2772 n_packets = 1; 2773 } 2774 2775 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR))) 2776 flags |= EFX_RX_PKT_DISCARD; 2777 2778 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) { 2779 channel->n_rx_ip_hdr_chksum_err += n_packets; 2780 } else if (unlikely(EFX_QWORD_FIELD(*event, 2781 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) { 2782 channel->n_rx_tcp_udp_chksum_err += n_packets; 2783 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP || 2784 rx_l4_class == ESE_DZ_L4_CLASS_UDP) { 2785 flags |= EFX_RX_PKT_CSUMMED; 2786 } 2787 2788 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) 2789 flags |= EFX_RX_PKT_TCP; 2790 2791 channel->irq_mod_score += 2 * n_packets; 2792 2793 /* Handle received packet(s) */ 2794 for (i = 0; i < n_packets; i++) { 2795 efx_rx_packet(rx_queue, 2796 rx_queue->removed_count & rx_queue->ptr_mask, 2797 rx_queue->scatter_n, rx_queue->scatter_len, 2798 flags); 2799 rx_queue->removed_count += rx_queue->scatter_n; 2800 } 2801 2802 rx_queue->scatter_n = 0; 2803 rx_queue->scatter_len = 0; 2804 2805 return n_packets; 2806 } 2807 2808 static int 2809 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2810 { 2811 struct efx_nic *efx = channel->efx; 2812 struct efx_tx_queue *tx_queue; 2813 unsigned int tx_ev_desc_ptr; 2814 unsigned int tx_ev_q_label; 2815 int tx_descs = 0; 2816 2817 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 2818 return 0; 2819 2820 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2821 return 0; 2822 2823 /* Transmit completion */ 2824 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2825 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2826 tx_queue = efx_channel_get_tx_queue(channel, 2827 tx_ev_q_label % EFX_TXQ_TYPES); 2828 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) & 2829 tx_queue->ptr_mask); 2830 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2831 2832 return tx_descs; 2833 } 2834 2835 static void 2836 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 2837 { 2838 struct efx_nic *efx = channel->efx; 2839 int subcode; 2840 2841 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 2842 2843 switch (subcode) { 2844 case ESE_DZ_DRV_TIMER_EV: 2845 case ESE_DZ_DRV_WAKE_UP_EV: 2846 break; 2847 case ESE_DZ_DRV_START_UP_EV: 2848 /* event queue init complete. ok. */ 2849 break; 2850 default: 2851 netif_err(efx, hw, efx->net_dev, 2852 "channel %d unknown driver event type %d" 2853 " (data " EFX_QWORD_FMT ")\n", 2854 channel->channel, subcode, 2855 EFX_QWORD_VAL(*event)); 2856 2857 } 2858 } 2859 2860 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 2861 efx_qword_t *event) 2862 { 2863 struct efx_nic *efx = channel->efx; 2864 u32 subcode; 2865 2866 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 2867 2868 switch (subcode) { 2869 case EFX_EF10_TEST: 2870 channel->event_test_cpu = raw_smp_processor_id(); 2871 break; 2872 case EFX_EF10_REFILL: 2873 /* The queue must be empty, so we won't receive any rx 2874 * events, so efx_process_channel() won't refill the 2875 * queue. Refill it here 2876 */ 2877 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 2878 break; 2879 default: 2880 netif_err(efx, hw, efx->net_dev, 2881 "channel %d unknown driver event type %u" 2882 " (data " EFX_QWORD_FMT ")\n", 2883 channel->channel, (unsigned) subcode, 2884 EFX_QWORD_VAL(*event)); 2885 } 2886 } 2887 2888 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 2889 { 2890 struct efx_nic *efx = channel->efx; 2891 efx_qword_t event, *p_event; 2892 unsigned int read_ptr; 2893 int ev_code; 2894 int tx_descs = 0; 2895 int spent = 0; 2896 2897 if (quota <= 0) 2898 return spent; 2899 2900 read_ptr = channel->eventq_read_ptr; 2901 2902 for (;;) { 2903 p_event = efx_event(channel, read_ptr); 2904 event = *p_event; 2905 2906 if (!efx_event_present(&event)) 2907 break; 2908 2909 EFX_SET_QWORD(*p_event); 2910 2911 ++read_ptr; 2912 2913 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 2914 2915 netif_vdbg(efx, drv, efx->net_dev, 2916 "processing event on %d " EFX_QWORD_FMT "\n", 2917 channel->channel, EFX_QWORD_VAL(event)); 2918 2919 switch (ev_code) { 2920 case ESE_DZ_EV_CODE_MCDI_EV: 2921 efx_mcdi_process_event(channel, &event); 2922 break; 2923 case ESE_DZ_EV_CODE_RX_EV: 2924 spent += efx_ef10_handle_rx_event(channel, &event); 2925 if (spent >= quota) { 2926 /* XXX can we split a merged event to 2927 * avoid going over-quota? 2928 */ 2929 spent = quota; 2930 goto out; 2931 } 2932 break; 2933 case ESE_DZ_EV_CODE_TX_EV: 2934 tx_descs += efx_ef10_handle_tx_event(channel, &event); 2935 if (tx_descs > efx->txq_entries) { 2936 spent = quota; 2937 goto out; 2938 } else if (++spent == quota) { 2939 goto out; 2940 } 2941 break; 2942 case ESE_DZ_EV_CODE_DRIVER_EV: 2943 efx_ef10_handle_driver_event(channel, &event); 2944 if (++spent == quota) 2945 goto out; 2946 break; 2947 case EFX_EF10_DRVGEN_EV: 2948 efx_ef10_handle_driver_generated_event(channel, &event); 2949 break; 2950 default: 2951 netif_err(efx, hw, efx->net_dev, 2952 "channel %d unknown event type %d" 2953 " (data " EFX_QWORD_FMT ")\n", 2954 channel->channel, ev_code, 2955 EFX_QWORD_VAL(event)); 2956 } 2957 } 2958 2959 out: 2960 channel->eventq_read_ptr = read_ptr; 2961 return spent; 2962 } 2963 2964 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 2965 { 2966 struct efx_nic *efx = channel->efx; 2967 efx_dword_t rptr; 2968 2969 if (EFX_EF10_WORKAROUND_35388(efx)) { 2970 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 2971 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 2972 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 2973 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 2974 2975 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2976 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 2977 ERF_DD_EVQ_IND_RPTR, 2978 (channel->eventq_read_ptr & 2979 channel->eventq_mask) >> 2980 ERF_DD_EVQ_IND_RPTR_WIDTH); 2981 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2982 channel->channel); 2983 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2984 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 2985 ERF_DD_EVQ_IND_RPTR, 2986 channel->eventq_read_ptr & 2987 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 2988 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2989 channel->channel); 2990 } else { 2991 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 2992 channel->eventq_read_ptr & 2993 channel->eventq_mask); 2994 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 2995 } 2996 } 2997 2998 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 2999 { 3000 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 3001 struct efx_nic *efx = channel->efx; 3002 efx_qword_t event; 3003 int rc; 3004 3005 EFX_POPULATE_QWORD_2(event, 3006 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 3007 ESF_DZ_EV_DATA, EFX_EF10_TEST); 3008 3009 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 3010 3011 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 3012 * already swapped the data to little-endian order. 3013 */ 3014 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 3015 sizeof(efx_qword_t)); 3016 3017 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 3018 NULL, 0, NULL); 3019 if (rc != 0) 3020 goto fail; 3021 3022 return; 3023 3024 fail: 3025 WARN_ON(true); 3026 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 3027 } 3028 3029 void efx_ef10_handle_drain_event(struct efx_nic *efx) 3030 { 3031 if (atomic_dec_and_test(&efx->active_queues)) 3032 wake_up(&efx->flush_wq); 3033 3034 WARN_ON(atomic_read(&efx->active_queues) < 0); 3035 } 3036 3037 static int efx_ef10_fini_dmaq(struct efx_nic *efx) 3038 { 3039 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3040 struct efx_channel *channel; 3041 struct efx_tx_queue *tx_queue; 3042 struct efx_rx_queue *rx_queue; 3043 int pending; 3044 3045 /* If the MC has just rebooted, the TX/RX queues will have already been 3046 * torn down, but efx->active_queues needs to be set to zero. 3047 */ 3048 if (nic_data->must_realloc_vis) { 3049 atomic_set(&efx->active_queues, 0); 3050 return 0; 3051 } 3052 3053 /* Do not attempt to write to the NIC during EEH recovery */ 3054 if (efx->state != STATE_RECOVERY) { 3055 efx_for_each_channel(channel, efx) { 3056 efx_for_each_channel_rx_queue(rx_queue, channel) 3057 efx_ef10_rx_fini(rx_queue); 3058 efx_for_each_channel_tx_queue(tx_queue, channel) 3059 efx_ef10_tx_fini(tx_queue); 3060 } 3061 3062 wait_event_timeout(efx->flush_wq, 3063 atomic_read(&efx->active_queues) == 0, 3064 msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); 3065 pending = atomic_read(&efx->active_queues); 3066 if (pending) { 3067 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", 3068 pending); 3069 return -ETIMEDOUT; 3070 } 3071 } 3072 3073 return 0; 3074 } 3075 3076 static void efx_ef10_prepare_flr(struct efx_nic *efx) 3077 { 3078 atomic_set(&efx->active_queues, 0); 3079 } 3080 3081 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left, 3082 const struct efx_filter_spec *right) 3083 { 3084 if ((left->match_flags ^ right->match_flags) | 3085 ((left->flags ^ right->flags) & 3086 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX))) 3087 return false; 3088 3089 return memcmp(&left->outer_vid, &right->outer_vid, 3090 sizeof(struct efx_filter_spec) - 3091 offsetof(struct efx_filter_spec, outer_vid)) == 0; 3092 } 3093 3094 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec) 3095 { 3096 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3); 3097 return jhash2((const u32 *)&spec->outer_vid, 3098 (sizeof(struct efx_filter_spec) - 3099 offsetof(struct efx_filter_spec, outer_vid)) / 4, 3100 0); 3101 /* XXX should we randomise the initval? */ 3102 } 3103 3104 /* Decide whether a filter should be exclusive or else should allow 3105 * delivery to additional recipients. Currently we decide that 3106 * filters for specific local unicast MAC and IP addresses are 3107 * exclusive. 3108 */ 3109 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec) 3110 { 3111 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC && 3112 !is_multicast_ether_addr(spec->loc_mac)) 3113 return true; 3114 3115 if ((spec->match_flags & 3116 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == 3117 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { 3118 if (spec->ether_type == htons(ETH_P_IP) && 3119 !ipv4_is_multicast(spec->loc_host[0])) 3120 return true; 3121 if (spec->ether_type == htons(ETH_P_IPV6) && 3122 ((const u8 *)spec->loc_host)[0] != 0xff) 3123 return true; 3124 } 3125 3126 return false; 3127 } 3128 3129 static struct efx_filter_spec * 3130 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table, 3131 unsigned int filter_idx) 3132 { 3133 return (struct efx_filter_spec *)(table->entry[filter_idx].spec & 3134 ~EFX_EF10_FILTER_FLAGS); 3135 } 3136 3137 static unsigned int 3138 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table, 3139 unsigned int filter_idx) 3140 { 3141 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS; 3142 } 3143 3144 static void 3145 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table, 3146 unsigned int filter_idx, 3147 const struct efx_filter_spec *spec, 3148 unsigned int flags) 3149 { 3150 table->entry[filter_idx].spec = (unsigned long)spec | flags; 3151 } 3152 3153 static void efx_ef10_filter_push_prep(struct efx_nic *efx, 3154 const struct efx_filter_spec *spec, 3155 efx_dword_t *inbuf, u64 handle, 3156 bool replacing) 3157 { 3158 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3159 u32 flags = spec->flags; 3160 3161 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN); 3162 3163 /* Remove RSS flag if we don't have an RSS context. */ 3164 if (flags & EFX_FILTER_FLAG_RX_RSS && 3165 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT && 3166 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) 3167 flags &= ~EFX_FILTER_FLAG_RX_RSS; 3168 3169 if (replacing) { 3170 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3171 MC_CMD_FILTER_OP_IN_OP_REPLACE); 3172 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle); 3173 } else { 3174 u32 match_fields = 0; 3175 3176 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3177 efx_ef10_filter_is_exclusive(spec) ? 3178 MC_CMD_FILTER_OP_IN_OP_INSERT : 3179 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE); 3180 3181 /* Convert match flags and values. Unlike almost 3182 * everything else in MCDI, these fields are in 3183 * network byte order. 3184 */ 3185 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) 3186 match_fields |= 3187 is_multicast_ether_addr(spec->loc_mac) ? 3188 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN : 3189 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; 3190 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \ 3191 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \ 3192 match_fields |= \ 3193 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 3194 mcdi_field ## _LBN; \ 3195 BUILD_BUG_ON( \ 3196 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \ 3197 sizeof(spec->gen_field)); \ 3198 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \ 3199 &spec->gen_field, sizeof(spec->gen_field)); \ 3200 } 3201 COPY_FIELD(REM_HOST, rem_host, SRC_IP); 3202 COPY_FIELD(LOC_HOST, loc_host, DST_IP); 3203 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC); 3204 COPY_FIELD(REM_PORT, rem_port, SRC_PORT); 3205 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC); 3206 COPY_FIELD(LOC_PORT, loc_port, DST_PORT); 3207 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE); 3208 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN); 3209 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN); 3210 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO); 3211 #undef COPY_FIELD 3212 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS, 3213 match_fields); 3214 } 3215 3216 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id); 3217 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST, 3218 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 3219 MC_CMD_FILTER_OP_IN_RX_DEST_DROP : 3220 MC_CMD_FILTER_OP_IN_RX_DEST_HOST); 3221 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0); 3222 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST, 3223 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); 3224 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, 3225 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 3226 0 : spec->dmaq_id); 3227 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE, 3228 (flags & EFX_FILTER_FLAG_RX_RSS) ? 3229 MC_CMD_FILTER_OP_IN_RX_MODE_RSS : 3230 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); 3231 if (flags & EFX_FILTER_FLAG_RX_RSS) 3232 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, 3233 spec->rss_context != 3234 EFX_FILTER_RSS_CONTEXT_DEFAULT ? 3235 spec->rss_context : nic_data->rx_rss_context); 3236 } 3237 3238 static int efx_ef10_filter_push(struct efx_nic *efx, 3239 const struct efx_filter_spec *spec, 3240 u64 *handle, bool replacing) 3241 { 3242 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3243 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN); 3244 int rc; 3245 3246 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing); 3247 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3248 outbuf, sizeof(outbuf), NULL); 3249 if (rc == 0) 3250 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 3251 if (rc == -ENOSPC) 3252 rc = -EBUSY; /* to match efx_farch_filter_insert() */ 3253 return rc; 3254 } 3255 3256 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec) 3257 { 3258 unsigned int match_flags = spec->match_flags; 3259 u32 mcdi_flags = 0; 3260 3261 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) { 3262 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG; 3263 mcdi_flags |= 3264 is_multicast_ether_addr(spec->loc_mac) ? 3265 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) : 3266 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN); 3267 } 3268 3269 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \ 3270 unsigned int old_match_flags = match_flags; \ 3271 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \ 3272 if (match_flags != old_match_flags) \ 3273 mcdi_flags |= \ 3274 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 3275 mcdi_field ## _LBN); \ 3276 } 3277 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP); 3278 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP); 3279 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC); 3280 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT); 3281 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC); 3282 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT); 3283 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE); 3284 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN); 3285 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN); 3286 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO); 3287 #undef MAP_FILTER_TO_MCDI_FLAG 3288 3289 /* Did we map them all? */ 3290 WARN_ON_ONCE(match_flags); 3291 3292 return mcdi_flags; 3293 } 3294 3295 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table, 3296 const struct efx_filter_spec *spec) 3297 { 3298 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec); 3299 unsigned int match_pri; 3300 3301 for (match_pri = 0; 3302 match_pri < table->rx_match_count; 3303 match_pri++) 3304 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags) 3305 return match_pri; 3306 3307 return -EPROTONOSUPPORT; 3308 } 3309 3310 static s32 efx_ef10_filter_insert(struct efx_nic *efx, 3311 struct efx_filter_spec *spec, 3312 bool replace_equal) 3313 { 3314 struct efx_ef10_filter_table *table = efx->filter_state; 3315 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 3316 struct efx_filter_spec *saved_spec; 3317 unsigned int match_pri, hash; 3318 unsigned int priv_flags; 3319 bool replacing = false; 3320 int ins_index = -1; 3321 DEFINE_WAIT(wait); 3322 bool is_mc_recip; 3323 s32 rc; 3324 3325 /* For now, only support RX filters */ 3326 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) != 3327 EFX_FILTER_FLAG_RX) 3328 return -EINVAL; 3329 3330 rc = efx_ef10_filter_pri(table, spec); 3331 if (rc < 0) 3332 return rc; 3333 match_pri = rc; 3334 3335 hash = efx_ef10_filter_hash(spec); 3336 is_mc_recip = efx_filter_is_mc_recipient(spec); 3337 if (is_mc_recip) 3338 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 3339 3340 /* Find any existing filters with the same match tuple or 3341 * else a free slot to insert at. If any of them are busy, 3342 * we have to wait and retry. 3343 */ 3344 for (;;) { 3345 unsigned int depth = 1; 3346 unsigned int i; 3347 3348 spin_lock_bh(&efx->filter_lock); 3349 3350 for (;;) { 3351 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3352 saved_spec = efx_ef10_filter_entry_spec(table, i); 3353 3354 if (!saved_spec) { 3355 if (ins_index < 0) 3356 ins_index = i; 3357 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 3358 if (table->entry[i].spec & 3359 EFX_EF10_FILTER_FLAG_BUSY) 3360 break; 3361 if (spec->priority < saved_spec->priority && 3362 spec->priority != EFX_FILTER_PRI_AUTO) { 3363 rc = -EPERM; 3364 goto out_unlock; 3365 } 3366 if (!is_mc_recip) { 3367 /* This is the only one */ 3368 if (spec->priority == 3369 saved_spec->priority && 3370 !replace_equal) { 3371 rc = -EEXIST; 3372 goto out_unlock; 3373 } 3374 ins_index = i; 3375 goto found; 3376 } else if (spec->priority > 3377 saved_spec->priority || 3378 (spec->priority == 3379 saved_spec->priority && 3380 replace_equal)) { 3381 if (ins_index < 0) 3382 ins_index = i; 3383 else 3384 __set_bit(depth, mc_rem_map); 3385 } 3386 } 3387 3388 /* Once we reach the maximum search depth, use 3389 * the first suitable slot or return -EBUSY if 3390 * there was none 3391 */ 3392 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 3393 if (ins_index < 0) { 3394 rc = -EBUSY; 3395 goto out_unlock; 3396 } 3397 goto found; 3398 } 3399 3400 ++depth; 3401 } 3402 3403 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 3404 spin_unlock_bh(&efx->filter_lock); 3405 schedule(); 3406 } 3407 3408 found: 3409 /* Create a software table entry if necessary, and mark it 3410 * busy. We might yet fail to insert, but any attempt to 3411 * insert a conflicting filter while we're waiting for the 3412 * firmware must find the busy entry. 3413 */ 3414 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 3415 if (saved_spec) { 3416 if (spec->priority == EFX_FILTER_PRI_AUTO && 3417 saved_spec->priority >= EFX_FILTER_PRI_AUTO) { 3418 /* Just make sure it won't be removed */ 3419 if (saved_spec->priority > EFX_FILTER_PRI_AUTO) 3420 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; 3421 table->entry[ins_index].spec &= 3422 ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3423 rc = ins_index; 3424 goto out_unlock; 3425 } 3426 replacing = true; 3427 priv_flags = efx_ef10_filter_entry_flags(table, ins_index); 3428 } else { 3429 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 3430 if (!saved_spec) { 3431 rc = -ENOMEM; 3432 goto out_unlock; 3433 } 3434 *saved_spec = *spec; 3435 priv_flags = 0; 3436 } 3437 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 3438 priv_flags | EFX_EF10_FILTER_FLAG_BUSY); 3439 3440 /* Mark lower-priority multicast recipients busy prior to removal */ 3441 if (is_mc_recip) { 3442 unsigned int depth, i; 3443 3444 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3445 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3446 if (test_bit(depth, mc_rem_map)) 3447 table->entry[i].spec |= 3448 EFX_EF10_FILTER_FLAG_BUSY; 3449 } 3450 } 3451 3452 spin_unlock_bh(&efx->filter_lock); 3453 3454 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle, 3455 replacing); 3456 3457 /* Finalise the software table entry */ 3458 spin_lock_bh(&efx->filter_lock); 3459 if (rc == 0) { 3460 if (replacing) { 3461 /* Update the fields that may differ */ 3462 if (saved_spec->priority == EFX_FILTER_PRI_AUTO) 3463 saved_spec->flags |= 3464 EFX_FILTER_FLAG_RX_OVER_AUTO; 3465 saved_spec->priority = spec->priority; 3466 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO; 3467 saved_spec->flags |= spec->flags; 3468 saved_spec->rss_context = spec->rss_context; 3469 saved_spec->dmaq_id = spec->dmaq_id; 3470 } 3471 } else if (!replacing) { 3472 kfree(saved_spec); 3473 saved_spec = NULL; 3474 } 3475 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags); 3476 3477 /* Remove and finalise entries for lower-priority multicast 3478 * recipients 3479 */ 3480 if (is_mc_recip) { 3481 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3482 unsigned int depth, i; 3483 3484 memset(inbuf, 0, sizeof(inbuf)); 3485 3486 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3487 if (!test_bit(depth, mc_rem_map)) 3488 continue; 3489 3490 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3491 saved_spec = efx_ef10_filter_entry_spec(table, i); 3492 priv_flags = efx_ef10_filter_entry_flags(table, i); 3493 3494 if (rc == 0) { 3495 spin_unlock_bh(&efx->filter_lock); 3496 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3497 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3498 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3499 table->entry[i].handle); 3500 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3501 inbuf, sizeof(inbuf), 3502 NULL, 0, NULL); 3503 spin_lock_bh(&efx->filter_lock); 3504 } 3505 3506 if (rc == 0) { 3507 kfree(saved_spec); 3508 saved_spec = NULL; 3509 priv_flags = 0; 3510 } else { 3511 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY; 3512 } 3513 efx_ef10_filter_set_entry(table, i, saved_spec, 3514 priv_flags); 3515 } 3516 } 3517 3518 /* If successful, return the inserted filter ID */ 3519 if (rc == 0) 3520 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index; 3521 3522 wake_up_all(&table->waitq); 3523 out_unlock: 3524 spin_unlock_bh(&efx->filter_lock); 3525 finish_wait(&table->waitq, &wait); 3526 return rc; 3527 } 3528 3529 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx) 3530 { 3531 /* no need to do anything here on EF10 */ 3532 } 3533 3534 /* Remove a filter. 3535 * If !by_index, remove by ID 3536 * If by_index, remove by index 3537 * Filter ID may come from userland and must be range-checked. 3538 */ 3539 static int efx_ef10_filter_remove_internal(struct efx_nic *efx, 3540 unsigned int priority_mask, 3541 u32 filter_id, bool by_index) 3542 { 3543 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 3544 struct efx_ef10_filter_table *table = efx->filter_state; 3545 MCDI_DECLARE_BUF(inbuf, 3546 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 3547 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 3548 struct efx_filter_spec *spec; 3549 DEFINE_WAIT(wait); 3550 int rc; 3551 3552 /* Find the software table entry and mark it busy. Don't 3553 * remove it yet; any attempt to update while we're waiting 3554 * for the firmware must find the busy entry. 3555 */ 3556 for (;;) { 3557 spin_lock_bh(&efx->filter_lock); 3558 if (!(table->entry[filter_idx].spec & 3559 EFX_EF10_FILTER_FLAG_BUSY)) 3560 break; 3561 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 3562 spin_unlock_bh(&efx->filter_lock); 3563 schedule(); 3564 } 3565 3566 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3567 if (!spec || 3568 (!by_index && 3569 efx_ef10_filter_pri(table, spec) != 3570 filter_id / HUNT_FILTER_TBL_ROWS)) { 3571 rc = -ENOENT; 3572 goto out_unlock; 3573 } 3574 3575 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO && 3576 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) { 3577 /* Just remove flags */ 3578 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO; 3579 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3580 rc = 0; 3581 goto out_unlock; 3582 } 3583 3584 if (!(priority_mask & (1U << spec->priority))) { 3585 rc = -ENOENT; 3586 goto out_unlock; 3587 } 3588 3589 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3590 spin_unlock_bh(&efx->filter_lock); 3591 3592 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { 3593 /* Reset to an automatic filter */ 3594 3595 struct efx_filter_spec new_spec = *spec; 3596 3597 new_spec.priority = EFX_FILTER_PRI_AUTO; 3598 new_spec.flags = (EFX_FILTER_FLAG_RX | 3599 (efx_rss_enabled(efx) ? 3600 EFX_FILTER_FLAG_RX_RSS : 0)); 3601 new_spec.dmaq_id = 0; 3602 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT; 3603 rc = efx_ef10_filter_push(efx, &new_spec, 3604 &table->entry[filter_idx].handle, 3605 true); 3606 3607 spin_lock_bh(&efx->filter_lock); 3608 if (rc == 0) 3609 *spec = new_spec; 3610 } else { 3611 /* Really remove the filter */ 3612 3613 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3614 efx_ef10_filter_is_exclusive(spec) ? 3615 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3616 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3617 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3618 table->entry[filter_idx].handle); 3619 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3620 inbuf, sizeof(inbuf), NULL, 0, NULL); 3621 3622 spin_lock_bh(&efx->filter_lock); 3623 if (rc == 0) { 3624 kfree(spec); 3625 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3626 } 3627 } 3628 3629 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 3630 wake_up_all(&table->waitq); 3631 out_unlock: 3632 spin_unlock_bh(&efx->filter_lock); 3633 finish_wait(&table->waitq, &wait); 3634 return rc; 3635 } 3636 3637 static int efx_ef10_filter_remove_safe(struct efx_nic *efx, 3638 enum efx_filter_priority priority, 3639 u32 filter_id) 3640 { 3641 return efx_ef10_filter_remove_internal(efx, 1U << priority, 3642 filter_id, false); 3643 } 3644 3645 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id) 3646 { 3647 return filter_id % HUNT_FILTER_TBL_ROWS; 3648 } 3649 3650 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx, 3651 enum efx_filter_priority priority, 3652 u32 filter_id) 3653 { 3654 if (filter_id == EFX_EF10_FILTER_ID_INVALID) 3655 return; 3656 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true); 3657 } 3658 3659 static int efx_ef10_filter_get_safe(struct efx_nic *efx, 3660 enum efx_filter_priority priority, 3661 u32 filter_id, struct efx_filter_spec *spec) 3662 { 3663 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 3664 struct efx_ef10_filter_table *table = efx->filter_state; 3665 const struct efx_filter_spec *saved_spec; 3666 int rc; 3667 3668 spin_lock_bh(&efx->filter_lock); 3669 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx); 3670 if (saved_spec && saved_spec->priority == priority && 3671 efx_ef10_filter_pri(table, saved_spec) == 3672 filter_id / HUNT_FILTER_TBL_ROWS) { 3673 *spec = *saved_spec; 3674 rc = 0; 3675 } else { 3676 rc = -ENOENT; 3677 } 3678 spin_unlock_bh(&efx->filter_lock); 3679 return rc; 3680 } 3681 3682 static int efx_ef10_filter_clear_rx(struct efx_nic *efx, 3683 enum efx_filter_priority priority) 3684 { 3685 unsigned int priority_mask; 3686 unsigned int i; 3687 int rc; 3688 3689 priority_mask = (((1U << (priority + 1)) - 1) & 3690 ~(1U << EFX_FILTER_PRI_AUTO)); 3691 3692 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 3693 rc = efx_ef10_filter_remove_internal(efx, priority_mask, 3694 i, true); 3695 if (rc && rc != -ENOENT) 3696 return rc; 3697 } 3698 3699 return 0; 3700 } 3701 3702 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx, 3703 enum efx_filter_priority priority) 3704 { 3705 struct efx_ef10_filter_table *table = efx->filter_state; 3706 unsigned int filter_idx; 3707 s32 count = 0; 3708 3709 spin_lock_bh(&efx->filter_lock); 3710 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3711 if (table->entry[filter_idx].spec && 3712 efx_ef10_filter_entry_spec(table, filter_idx)->priority == 3713 priority) 3714 ++count; 3715 } 3716 spin_unlock_bh(&efx->filter_lock); 3717 return count; 3718 } 3719 3720 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx) 3721 { 3722 struct efx_ef10_filter_table *table = efx->filter_state; 3723 3724 return table->rx_match_count * HUNT_FILTER_TBL_ROWS; 3725 } 3726 3727 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx, 3728 enum efx_filter_priority priority, 3729 u32 *buf, u32 size) 3730 { 3731 struct efx_ef10_filter_table *table = efx->filter_state; 3732 struct efx_filter_spec *spec; 3733 unsigned int filter_idx; 3734 s32 count = 0; 3735 3736 spin_lock_bh(&efx->filter_lock); 3737 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3738 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3739 if (spec && spec->priority == priority) { 3740 if (count == size) { 3741 count = -EMSGSIZE; 3742 break; 3743 } 3744 buf[count++] = (efx_ef10_filter_pri(table, spec) * 3745 HUNT_FILTER_TBL_ROWS + 3746 filter_idx); 3747 } 3748 } 3749 spin_unlock_bh(&efx->filter_lock); 3750 return count; 3751 } 3752 3753 #ifdef CONFIG_RFS_ACCEL 3754 3755 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete; 3756 3757 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx, 3758 struct efx_filter_spec *spec) 3759 { 3760 struct efx_ef10_filter_table *table = efx->filter_state; 3761 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3762 struct efx_filter_spec *saved_spec; 3763 unsigned int hash, i, depth = 1; 3764 bool replacing = false; 3765 int ins_index = -1; 3766 u64 cookie; 3767 s32 rc; 3768 3769 /* Must be an RX filter without RSS and not for a multicast 3770 * destination address (RFS only works for connected sockets). 3771 * These restrictions allow us to pass only a tiny amount of 3772 * data through to the completion function. 3773 */ 3774 EFX_WARN_ON_PARANOID(spec->flags != 3775 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER)); 3776 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT); 3777 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec)); 3778 3779 hash = efx_ef10_filter_hash(spec); 3780 3781 spin_lock_bh(&efx->filter_lock); 3782 3783 /* Find any existing filter with the same match tuple or else 3784 * a free slot to insert at. If an existing filter is busy, 3785 * we have to give up. 3786 */ 3787 for (;;) { 3788 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3789 saved_spec = efx_ef10_filter_entry_spec(table, i); 3790 3791 if (!saved_spec) { 3792 if (ins_index < 0) 3793 ins_index = i; 3794 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 3795 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) { 3796 rc = -EBUSY; 3797 goto fail_unlock; 3798 } 3799 if (spec->priority < saved_spec->priority) { 3800 rc = -EPERM; 3801 goto fail_unlock; 3802 } 3803 ins_index = i; 3804 break; 3805 } 3806 3807 /* Once we reach the maximum search depth, use the 3808 * first suitable slot or return -EBUSY if there was 3809 * none 3810 */ 3811 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 3812 if (ins_index < 0) { 3813 rc = -EBUSY; 3814 goto fail_unlock; 3815 } 3816 break; 3817 } 3818 3819 ++depth; 3820 } 3821 3822 /* Create a software table entry if necessary, and mark it 3823 * busy. We might yet fail to insert, but any attempt to 3824 * insert a conflicting filter while we're waiting for the 3825 * firmware must find the busy entry. 3826 */ 3827 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 3828 if (saved_spec) { 3829 replacing = true; 3830 } else { 3831 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 3832 if (!saved_spec) { 3833 rc = -ENOMEM; 3834 goto fail_unlock; 3835 } 3836 *saved_spec = *spec; 3837 } 3838 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 3839 EFX_EF10_FILTER_FLAG_BUSY); 3840 3841 spin_unlock_bh(&efx->filter_lock); 3842 3843 /* Pack up the variables needed on completion */ 3844 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id; 3845 3846 efx_ef10_filter_push_prep(efx, spec, inbuf, 3847 table->entry[ins_index].handle, replacing); 3848 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3849 MC_CMD_FILTER_OP_OUT_LEN, 3850 efx_ef10_filter_rfs_insert_complete, cookie); 3851 3852 return ins_index; 3853 3854 fail_unlock: 3855 spin_unlock_bh(&efx->filter_lock); 3856 return rc; 3857 } 3858 3859 static void 3860 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie, 3861 int rc, efx_dword_t *outbuf, 3862 size_t outlen_actual) 3863 { 3864 struct efx_ef10_filter_table *table = efx->filter_state; 3865 unsigned int ins_index, dmaq_id; 3866 struct efx_filter_spec *spec; 3867 bool replacing; 3868 3869 /* Unpack the cookie */ 3870 replacing = cookie >> 31; 3871 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1); 3872 dmaq_id = cookie & 0xffff; 3873 3874 spin_lock_bh(&efx->filter_lock); 3875 spec = efx_ef10_filter_entry_spec(table, ins_index); 3876 if (rc == 0) { 3877 table->entry[ins_index].handle = 3878 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 3879 if (replacing) 3880 spec->dmaq_id = dmaq_id; 3881 } else if (!replacing) { 3882 kfree(spec); 3883 spec = NULL; 3884 } 3885 efx_ef10_filter_set_entry(table, ins_index, spec, 0); 3886 spin_unlock_bh(&efx->filter_lock); 3887 3888 wake_up_all(&table->waitq); 3889 } 3890 3891 static void 3892 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 3893 unsigned long filter_idx, 3894 int rc, efx_dword_t *outbuf, 3895 size_t outlen_actual); 3896 3897 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, 3898 unsigned int filter_idx) 3899 { 3900 struct efx_ef10_filter_table *table = efx->filter_state; 3901 struct efx_filter_spec *spec = 3902 efx_ef10_filter_entry_spec(table, filter_idx); 3903 MCDI_DECLARE_BUF(inbuf, 3904 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 3905 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 3906 3907 if (!spec || 3908 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) || 3909 spec->priority != EFX_FILTER_PRI_HINT || 3910 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id, 3911 flow_id, filter_idx)) 3912 return false; 3913 3914 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3915 MC_CMD_FILTER_OP_IN_OP_REMOVE); 3916 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3917 table->entry[filter_idx].handle); 3918 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0, 3919 efx_ef10_filter_rfs_expire_complete, filter_idx)) 3920 return false; 3921 3922 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3923 return true; 3924 } 3925 3926 static void 3927 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 3928 unsigned long filter_idx, 3929 int rc, efx_dword_t *outbuf, 3930 size_t outlen_actual) 3931 { 3932 struct efx_ef10_filter_table *table = efx->filter_state; 3933 struct efx_filter_spec *spec = 3934 efx_ef10_filter_entry_spec(table, filter_idx); 3935 3936 spin_lock_bh(&efx->filter_lock); 3937 if (rc == 0) { 3938 kfree(spec); 3939 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3940 } 3941 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 3942 wake_up_all(&table->waitq); 3943 spin_unlock_bh(&efx->filter_lock); 3944 } 3945 3946 #endif /* CONFIG_RFS_ACCEL */ 3947 3948 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags) 3949 { 3950 int match_flags = 0; 3951 3952 #define MAP_FLAG(gen_flag, mcdi_field) { \ 3953 u32 old_mcdi_flags = mcdi_flags; \ 3954 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 3955 mcdi_field ## _LBN); \ 3956 if (mcdi_flags != old_mcdi_flags) \ 3957 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \ 3958 } 3959 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST); 3960 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST); 3961 MAP_FLAG(REM_HOST, SRC_IP); 3962 MAP_FLAG(LOC_HOST, DST_IP); 3963 MAP_FLAG(REM_MAC, SRC_MAC); 3964 MAP_FLAG(REM_PORT, SRC_PORT); 3965 MAP_FLAG(LOC_MAC, DST_MAC); 3966 MAP_FLAG(LOC_PORT, DST_PORT); 3967 MAP_FLAG(ETHER_TYPE, ETHER_TYPE); 3968 MAP_FLAG(INNER_VID, INNER_VLAN); 3969 MAP_FLAG(OUTER_VID, OUTER_VLAN); 3970 MAP_FLAG(IP_PROTO, IP_PROTO); 3971 #undef MAP_FLAG 3972 3973 /* Did we map them all? */ 3974 if (mcdi_flags) 3975 return -EINVAL; 3976 3977 return match_flags; 3978 } 3979 3980 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx) 3981 { 3982 struct efx_ef10_filter_table *table = efx->filter_state; 3983 struct efx_ef10_filter_vlan *vlan, *next_vlan; 3984 3985 /* See comment in efx_ef10_filter_table_remove() */ 3986 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 3987 return; 3988 3989 if (!table) 3990 return; 3991 3992 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list) 3993 efx_ef10_filter_del_vlan_internal(efx, vlan); 3994 } 3995 3996 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table, 3997 enum efx_filter_match_flags match_flags) 3998 { 3999 unsigned int match_pri; 4000 int mf; 4001 4002 for (match_pri = 0; 4003 match_pri < table->rx_match_count; 4004 match_pri++) { 4005 mf = efx_ef10_filter_match_flags_from_mcdi( 4006 table->rx_match_mcdi_flags[match_pri]); 4007 if (mf == match_flags) 4008 return true; 4009 } 4010 4011 return false; 4012 } 4013 4014 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 4015 { 4016 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN); 4017 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX); 4018 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4019 struct net_device *net_dev = efx->net_dev; 4020 unsigned int pd_match_pri, pd_match_count; 4021 struct efx_ef10_filter_table *table; 4022 struct efx_ef10_vlan *vlan; 4023 size_t outlen; 4024 int rc; 4025 4026 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 4027 return -EINVAL; 4028 4029 if (efx->filter_state) /* already probed */ 4030 return 0; 4031 4032 table = kzalloc(sizeof(*table), GFP_KERNEL); 4033 if (!table) 4034 return -ENOMEM; 4035 4036 /* Find out which RX filter types are supported, and their priorities */ 4037 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP, 4038 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); 4039 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO, 4040 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf), 4041 &outlen); 4042 if (rc) 4043 goto fail; 4044 pd_match_count = MCDI_VAR_ARRAY_LEN( 4045 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES); 4046 table->rx_match_count = 0; 4047 4048 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) { 4049 u32 mcdi_flags = 4050 MCDI_ARRAY_DWORD( 4051 outbuf, 4052 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES, 4053 pd_match_pri); 4054 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags); 4055 if (rc < 0) { 4056 netif_dbg(efx, probe, efx->net_dev, 4057 "%s: fw flags %#x pri %u not supported in driver\n", 4058 __func__, mcdi_flags, pd_match_pri); 4059 } else { 4060 netif_dbg(efx, probe, efx->net_dev, 4061 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n", 4062 __func__, mcdi_flags, pd_match_pri, 4063 rc, table->rx_match_count); 4064 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags; 4065 table->rx_match_count++; 4066 } 4067 } 4068 4069 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) && 4070 !(efx_ef10_filter_match_supported(table, 4071 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) && 4072 efx_ef10_filter_match_supported(table, 4073 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) { 4074 netif_info(efx, probe, net_dev, 4075 "VLAN filters are not supported in this firmware variant\n"); 4076 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4077 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4078 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4079 } 4080 4081 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry)); 4082 if (!table->entry) { 4083 rc = -ENOMEM; 4084 goto fail; 4085 } 4086 4087 table->mc_promisc_last = false; 4088 table->vlan_filter = 4089 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER); 4090 INIT_LIST_HEAD(&table->vlan_list); 4091 4092 efx->filter_state = table; 4093 init_waitqueue_head(&table->waitq); 4094 4095 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 4096 rc = efx_ef10_filter_add_vlan(efx, vlan->vid); 4097 if (rc) 4098 goto fail_add_vlan; 4099 } 4100 4101 return 0; 4102 4103 fail_add_vlan: 4104 efx_ef10_filter_cleanup_vlans(efx); 4105 efx->filter_state = NULL; 4106 fail: 4107 kfree(table); 4108 return rc; 4109 } 4110 4111 /* Caller must hold efx->filter_sem for read if race against 4112 * efx_ef10_filter_table_remove() is possible 4113 */ 4114 static void efx_ef10_filter_table_restore(struct efx_nic *efx) 4115 { 4116 struct efx_ef10_filter_table *table = efx->filter_state; 4117 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4118 struct efx_filter_spec *spec; 4119 unsigned int filter_idx; 4120 bool failed = false; 4121 int rc; 4122 4123 WARN_ON(!rwsem_is_locked(&efx->filter_sem)); 4124 4125 if (!nic_data->must_restore_filters) 4126 return; 4127 4128 if (!table) 4129 return; 4130 4131 spin_lock_bh(&efx->filter_lock); 4132 4133 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 4134 spec = efx_ef10_filter_entry_spec(table, filter_idx); 4135 if (!spec) 4136 continue; 4137 4138 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 4139 spin_unlock_bh(&efx->filter_lock); 4140 4141 rc = efx_ef10_filter_push(efx, spec, 4142 &table->entry[filter_idx].handle, 4143 false); 4144 if (rc) 4145 failed = true; 4146 4147 spin_lock_bh(&efx->filter_lock); 4148 if (rc) { 4149 kfree(spec); 4150 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 4151 } else { 4152 table->entry[filter_idx].spec &= 4153 ~EFX_EF10_FILTER_FLAG_BUSY; 4154 } 4155 } 4156 4157 spin_unlock_bh(&efx->filter_lock); 4158 4159 if (failed) 4160 netif_err(efx, hw, efx->net_dev, 4161 "unable to restore all filters\n"); 4162 else 4163 nic_data->must_restore_filters = false; 4164 } 4165 4166 static void efx_ef10_filter_table_remove(struct efx_nic *efx) 4167 { 4168 struct efx_ef10_filter_table *table = efx->filter_state; 4169 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 4170 struct efx_filter_spec *spec; 4171 unsigned int filter_idx; 4172 int rc; 4173 4174 efx_ef10_filter_cleanup_vlans(efx); 4175 efx->filter_state = NULL; 4176 /* If we were called without locking, then it's not safe to free 4177 * the table as others might be using it. So we just WARN, leak 4178 * the memory, and potentially get an inconsistent filter table 4179 * state. 4180 * This should never actually happen. 4181 */ 4182 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 4183 return; 4184 4185 if (!table) 4186 return; 4187 4188 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 4189 spec = efx_ef10_filter_entry_spec(table, filter_idx); 4190 if (!spec) 4191 continue; 4192 4193 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 4194 efx_ef10_filter_is_exclusive(spec) ? 4195 MC_CMD_FILTER_OP_IN_OP_REMOVE : 4196 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 4197 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 4198 table->entry[filter_idx].handle); 4199 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf, 4200 sizeof(inbuf), NULL, 0, NULL); 4201 if (rc) 4202 netif_info(efx, drv, efx->net_dev, 4203 "%s: filter %04x remove failed\n", 4204 __func__, filter_idx); 4205 kfree(spec); 4206 } 4207 4208 vfree(table->entry); 4209 kfree(table); 4210 } 4211 4212 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id) 4213 { 4214 struct efx_ef10_filter_table *table = efx->filter_state; 4215 unsigned int filter_idx; 4216 4217 if (*id != EFX_EF10_FILTER_ID_INVALID) { 4218 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id); 4219 if (!table->entry[filter_idx].spec) 4220 netif_dbg(efx, drv, efx->net_dev, 4221 "marked null spec old %04x:%04x\n", *id, 4222 filter_idx); 4223 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; 4224 *id = EFX_EF10_FILTER_ID_INVALID; 4225 } 4226 } 4227 4228 /* Mark old per-VLAN filters that may need to be removed */ 4229 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx, 4230 struct efx_ef10_filter_vlan *vlan) 4231 { 4232 struct efx_ef10_filter_table *table = efx->filter_state; 4233 unsigned int i; 4234 4235 for (i = 0; i < table->dev_uc_count; i++) 4236 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]); 4237 for (i = 0; i < table->dev_mc_count; i++) 4238 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]); 4239 efx_ef10_filter_mark_one_old(efx, &vlan->ucdef); 4240 efx_ef10_filter_mark_one_old(efx, &vlan->bcast); 4241 efx_ef10_filter_mark_one_old(efx, &vlan->mcdef); 4242 } 4243 4244 /* Mark old filters that may need to be removed. 4245 * Caller must hold efx->filter_sem for read if race against 4246 * efx_ef10_filter_table_remove() is possible 4247 */ 4248 static void efx_ef10_filter_mark_old(struct efx_nic *efx) 4249 { 4250 struct efx_ef10_filter_table *table = efx->filter_state; 4251 struct efx_ef10_filter_vlan *vlan; 4252 4253 spin_lock_bh(&efx->filter_lock); 4254 list_for_each_entry(vlan, &table->vlan_list, list) 4255 _efx_ef10_filter_vlan_mark_old(efx, vlan); 4256 spin_unlock_bh(&efx->filter_lock); 4257 } 4258 4259 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx) 4260 { 4261 struct efx_ef10_filter_table *table = efx->filter_state; 4262 struct net_device *net_dev = efx->net_dev; 4263 struct netdev_hw_addr *uc; 4264 int addr_count; 4265 unsigned int i; 4266 4267 addr_count = netdev_uc_count(net_dev); 4268 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC); 4269 table->dev_uc_count = 1 + addr_count; 4270 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr); 4271 i = 1; 4272 netdev_for_each_uc_addr(uc, net_dev) { 4273 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) { 4274 table->uc_promisc = true; 4275 break; 4276 } 4277 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr); 4278 i++; 4279 } 4280 } 4281 4282 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx) 4283 { 4284 struct efx_ef10_filter_table *table = efx->filter_state; 4285 struct net_device *net_dev = efx->net_dev; 4286 struct netdev_hw_addr *mc; 4287 unsigned int i, addr_count; 4288 4289 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)); 4290 4291 addr_count = netdev_mc_count(net_dev); 4292 i = 0; 4293 netdev_for_each_mc_addr(mc, net_dev) { 4294 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) { 4295 table->mc_promisc = true; 4296 break; 4297 } 4298 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr); 4299 i++; 4300 } 4301 4302 table->dev_mc_count = i; 4303 } 4304 4305 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx, 4306 struct efx_ef10_filter_vlan *vlan, 4307 bool multicast, bool rollback) 4308 { 4309 struct efx_ef10_filter_table *table = efx->filter_state; 4310 struct efx_ef10_dev_addr *addr_list; 4311 enum efx_filter_flags filter_flags; 4312 struct efx_filter_spec spec; 4313 u8 baddr[ETH_ALEN]; 4314 unsigned int i, j; 4315 int addr_count; 4316 u16 *ids; 4317 int rc; 4318 4319 if (multicast) { 4320 addr_list = table->dev_mc_list; 4321 addr_count = table->dev_mc_count; 4322 ids = vlan->mc; 4323 } else { 4324 addr_list = table->dev_uc_list; 4325 addr_count = table->dev_uc_count; 4326 ids = vlan->uc; 4327 } 4328 4329 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0; 4330 4331 /* Insert/renew filters */ 4332 for (i = 0; i < addr_count; i++) { 4333 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 4334 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr); 4335 rc = efx_ef10_filter_insert(efx, &spec, true); 4336 if (rc < 0) { 4337 if (rollback) { 4338 netif_info(efx, drv, efx->net_dev, 4339 "efx_ef10_filter_insert failed rc=%d\n", 4340 rc); 4341 /* Fall back to promiscuous */ 4342 for (j = 0; j < i; j++) { 4343 efx_ef10_filter_remove_unsafe( 4344 efx, EFX_FILTER_PRI_AUTO, 4345 ids[j]); 4346 ids[j] = EFX_EF10_FILTER_ID_INVALID; 4347 } 4348 return rc; 4349 } else { 4350 /* mark as not inserted, and carry on */ 4351 rc = EFX_EF10_FILTER_ID_INVALID; 4352 } 4353 } 4354 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc); 4355 } 4356 4357 if (multicast && rollback) { 4358 /* Also need an Ethernet broadcast filter */ 4359 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 4360 eth_broadcast_addr(baddr); 4361 efx_filter_set_eth_local(&spec, vlan->vid, baddr); 4362 rc = efx_ef10_filter_insert(efx, &spec, true); 4363 if (rc < 0) { 4364 netif_warn(efx, drv, efx->net_dev, 4365 "Broadcast filter insert failed rc=%d\n", rc); 4366 /* Fall back to promiscuous */ 4367 for (j = 0; j < i; j++) { 4368 efx_ef10_filter_remove_unsafe( 4369 efx, EFX_FILTER_PRI_AUTO, 4370 ids[j]); 4371 ids[j] = EFX_EF10_FILTER_ID_INVALID; 4372 } 4373 return rc; 4374 } else { 4375 EFX_WARN_ON_PARANOID(vlan->bcast != 4376 EFX_EF10_FILTER_ID_INVALID); 4377 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc); 4378 } 4379 } 4380 4381 return 0; 4382 } 4383 4384 static int efx_ef10_filter_insert_def(struct efx_nic *efx, 4385 struct efx_ef10_filter_vlan *vlan, 4386 bool multicast, bool rollback) 4387 { 4388 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4389 enum efx_filter_flags filter_flags; 4390 struct efx_filter_spec spec; 4391 u8 baddr[ETH_ALEN]; 4392 int rc; 4393 4394 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0; 4395 4396 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 4397 4398 if (multicast) 4399 efx_filter_set_mc_def(&spec); 4400 else 4401 efx_filter_set_uc_def(&spec); 4402 4403 if (vlan->vid != EFX_FILTER_VID_UNSPEC) 4404 efx_filter_set_eth_local(&spec, vlan->vid, NULL); 4405 4406 rc = efx_ef10_filter_insert(efx, &spec, true); 4407 if (rc < 0) { 4408 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING, 4409 efx->net_dev, 4410 "%scast mismatch filter insert failed rc=%d\n", 4411 multicast ? "Multi" : "Uni", rc); 4412 } else if (multicast) { 4413 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID); 4414 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc); 4415 if (!nic_data->workaround_26807) { 4416 /* Also need an Ethernet broadcast filter */ 4417 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 4418 filter_flags, 0); 4419 eth_broadcast_addr(baddr); 4420 efx_filter_set_eth_local(&spec, vlan->vid, baddr); 4421 rc = efx_ef10_filter_insert(efx, &spec, true); 4422 if (rc < 0) { 4423 netif_warn(efx, drv, efx->net_dev, 4424 "Broadcast filter insert failed rc=%d\n", 4425 rc); 4426 if (rollback) { 4427 /* Roll back the mc_def filter */ 4428 efx_ef10_filter_remove_unsafe( 4429 efx, EFX_FILTER_PRI_AUTO, 4430 vlan->mcdef); 4431 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID; 4432 return rc; 4433 } 4434 } else { 4435 EFX_WARN_ON_PARANOID(vlan->bcast != 4436 EFX_EF10_FILTER_ID_INVALID); 4437 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc); 4438 } 4439 } 4440 rc = 0; 4441 } else { 4442 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID); 4443 vlan->ucdef = rc; 4444 rc = 0; 4445 } 4446 return rc; 4447 } 4448 4449 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD 4450 * flag or removes these filters, we don't need to hold the filter_lock while 4451 * scanning for these filters. 4452 */ 4453 static void efx_ef10_filter_remove_old(struct efx_nic *efx) 4454 { 4455 struct efx_ef10_filter_table *table = efx->filter_state; 4456 int remove_failed = 0; 4457 int remove_noent = 0; 4458 int rc; 4459 int i; 4460 4461 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 4462 if (ACCESS_ONCE(table->entry[i].spec) & 4463 EFX_EF10_FILTER_FLAG_AUTO_OLD) { 4464 rc = efx_ef10_filter_remove_internal(efx, 4465 1U << EFX_FILTER_PRI_AUTO, i, true); 4466 if (rc == -ENOENT) 4467 remove_noent++; 4468 else if (rc) 4469 remove_failed++; 4470 } 4471 } 4472 4473 if (remove_failed) 4474 netif_info(efx, drv, efx->net_dev, 4475 "%s: failed to remove %d filters\n", 4476 __func__, remove_failed); 4477 if (remove_noent) 4478 netif_info(efx, drv, efx->net_dev, 4479 "%s: failed to remove %d non-existent filters\n", 4480 __func__, remove_noent); 4481 } 4482 4483 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 4484 { 4485 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4486 u8 mac_old[ETH_ALEN]; 4487 int rc, rc2; 4488 4489 /* Only reconfigure a PF-created vport */ 4490 if (is_zero_ether_addr(nic_data->vport_mac)) 4491 return 0; 4492 4493 efx_device_detach_sync(efx); 4494 efx_net_stop(efx->net_dev); 4495 down_write(&efx->filter_sem); 4496 efx_ef10_filter_table_remove(efx); 4497 up_write(&efx->filter_sem); 4498 4499 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id); 4500 if (rc) 4501 goto restore_filters; 4502 4503 ether_addr_copy(mac_old, nic_data->vport_mac); 4504 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id, 4505 nic_data->vport_mac); 4506 if (rc) 4507 goto restore_vadaptor; 4508 4509 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id, 4510 efx->net_dev->dev_addr); 4511 if (!rc) { 4512 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 4513 } else { 4514 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old); 4515 if (rc2) { 4516 /* Failed to add original MAC, so clear vport_mac */ 4517 eth_zero_addr(nic_data->vport_mac); 4518 goto reset_nic; 4519 } 4520 } 4521 4522 restore_vadaptor: 4523 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id); 4524 if (rc2) 4525 goto reset_nic; 4526 restore_filters: 4527 down_write(&efx->filter_sem); 4528 rc2 = efx_ef10_filter_table_probe(efx); 4529 up_write(&efx->filter_sem); 4530 if (rc2) 4531 goto reset_nic; 4532 4533 rc2 = efx_net_open(efx->net_dev); 4534 if (rc2) 4535 goto reset_nic; 4536 4537 netif_device_attach(efx->net_dev); 4538 4539 return rc; 4540 4541 reset_nic: 4542 netif_err(efx, drv, efx->net_dev, 4543 "Failed to restore when changing MAC address - scheduling reset\n"); 4544 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 4545 4546 return rc ? rc : rc2; 4547 } 4548 4549 /* Caller must hold efx->filter_sem for read if race against 4550 * efx_ef10_filter_table_remove() is possible 4551 */ 4552 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx, 4553 struct efx_ef10_filter_vlan *vlan) 4554 { 4555 struct efx_ef10_filter_table *table = efx->filter_state; 4556 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4557 4558 /* Do not install unspecified VID if VLAN filtering is enabled. 4559 * Do not install all specified VIDs if VLAN filtering is disabled. 4560 */ 4561 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter) 4562 return; 4563 4564 /* Insert/renew unicast filters */ 4565 if (table->uc_promisc) { 4566 efx_ef10_filter_insert_def(efx, vlan, false, false); 4567 efx_ef10_filter_insert_addr_list(efx, vlan, false, false); 4568 } else { 4569 /* If any of the filters failed to insert, fall back to 4570 * promiscuous mode - add in the uc_def filter. But keep 4571 * our individual unicast filters. 4572 */ 4573 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false)) 4574 efx_ef10_filter_insert_def(efx, vlan, false, false); 4575 } 4576 4577 /* Insert/renew multicast filters */ 4578 /* If changing promiscuous state with cascaded multicast filters, remove 4579 * old filters first, so that packets are dropped rather than duplicated 4580 */ 4581 if (nic_data->workaround_26807 && 4582 table->mc_promisc_last != table->mc_promisc) 4583 efx_ef10_filter_remove_old(efx); 4584 if (table->mc_promisc) { 4585 if (nic_data->workaround_26807) { 4586 /* If we failed to insert promiscuous filters, rollback 4587 * and fall back to individual multicast filters 4588 */ 4589 if (efx_ef10_filter_insert_def(efx, vlan, true, true)) { 4590 /* Changing promisc state, so remove old filters */ 4591 efx_ef10_filter_remove_old(efx); 4592 efx_ef10_filter_insert_addr_list(efx, vlan, 4593 true, false); 4594 } 4595 } else { 4596 /* If we failed to insert promiscuous filters, don't 4597 * rollback. Regardless, also insert the mc_list 4598 */ 4599 efx_ef10_filter_insert_def(efx, vlan, true, false); 4600 efx_ef10_filter_insert_addr_list(efx, vlan, true, false); 4601 } 4602 } else { 4603 /* If any filters failed to insert, rollback and fall back to 4604 * promiscuous mode - mc_def filter and maybe broadcast. If 4605 * that fails, roll back again and insert as many of our 4606 * individual multicast filters as we can. 4607 */ 4608 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) { 4609 /* Changing promisc state, so remove old filters */ 4610 if (nic_data->workaround_26807) 4611 efx_ef10_filter_remove_old(efx); 4612 if (efx_ef10_filter_insert_def(efx, vlan, true, true)) 4613 efx_ef10_filter_insert_addr_list(efx, vlan, 4614 true, false); 4615 } 4616 } 4617 } 4618 4619 /* Caller must hold efx->filter_sem for read if race against 4620 * efx_ef10_filter_table_remove() is possible 4621 */ 4622 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx) 4623 { 4624 struct efx_ef10_filter_table *table = efx->filter_state; 4625 struct net_device *net_dev = efx->net_dev; 4626 struct efx_ef10_filter_vlan *vlan; 4627 bool vlan_filter; 4628 4629 if (!efx_dev_registered(efx)) 4630 return; 4631 4632 if (!table) 4633 return; 4634 4635 efx_ef10_filter_mark_old(efx); 4636 4637 /* Copy/convert the address lists; add the primary station 4638 * address and broadcast address 4639 */ 4640 netif_addr_lock_bh(net_dev); 4641 efx_ef10_filter_uc_addr_list(efx); 4642 efx_ef10_filter_mc_addr_list(efx); 4643 netif_addr_unlock_bh(net_dev); 4644 4645 /* If VLAN filtering changes, all old filters are finally removed. 4646 * Do it in advance to avoid conflicts for unicast untagged and 4647 * VLAN 0 tagged filters. 4648 */ 4649 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER); 4650 if (table->vlan_filter != vlan_filter) { 4651 table->vlan_filter = vlan_filter; 4652 efx_ef10_filter_remove_old(efx); 4653 } 4654 4655 list_for_each_entry(vlan, &table->vlan_list, list) 4656 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan); 4657 4658 efx_ef10_filter_remove_old(efx); 4659 table->mc_promisc_last = table->mc_promisc; 4660 } 4661 4662 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid) 4663 { 4664 struct efx_ef10_filter_table *table = efx->filter_state; 4665 struct efx_ef10_filter_vlan *vlan; 4666 4667 WARN_ON(!rwsem_is_locked(&efx->filter_sem)); 4668 4669 list_for_each_entry(vlan, &table->vlan_list, list) { 4670 if (vlan->vid == vid) 4671 return vlan; 4672 } 4673 4674 return NULL; 4675 } 4676 4677 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid) 4678 { 4679 struct efx_ef10_filter_table *table = efx->filter_state; 4680 struct efx_ef10_filter_vlan *vlan; 4681 unsigned int i; 4682 4683 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 4684 return -EINVAL; 4685 4686 vlan = efx_ef10_filter_find_vlan(efx, vid); 4687 if (WARN_ON(vlan)) { 4688 netif_err(efx, drv, efx->net_dev, 4689 "VLAN %u already added\n", vid); 4690 return -EALREADY; 4691 } 4692 4693 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 4694 if (!vlan) 4695 return -ENOMEM; 4696 4697 vlan->vid = vid; 4698 4699 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++) 4700 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID; 4701 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++) 4702 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID; 4703 vlan->ucdef = EFX_EF10_FILTER_ID_INVALID; 4704 vlan->bcast = EFX_EF10_FILTER_ID_INVALID; 4705 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID; 4706 4707 list_add_tail(&vlan->list, &table->vlan_list); 4708 4709 if (efx_dev_registered(efx)) 4710 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan); 4711 4712 return 0; 4713 } 4714 4715 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx, 4716 struct efx_ef10_filter_vlan *vlan) 4717 { 4718 unsigned int i; 4719 4720 /* See comment in efx_ef10_filter_table_remove() */ 4721 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 4722 return; 4723 4724 list_del(&vlan->list); 4725 4726 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++) 4727 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, 4728 vlan->uc[i]); 4729 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++) 4730 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, 4731 vlan->mc[i]); 4732 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef); 4733 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast); 4734 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef); 4735 4736 kfree(vlan); 4737 } 4738 4739 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid) 4740 { 4741 struct efx_ef10_filter_vlan *vlan; 4742 4743 /* See comment in efx_ef10_filter_table_remove() */ 4744 if (!efx_rwsem_assert_write_locked(&efx->filter_sem)) 4745 return; 4746 4747 vlan = efx_ef10_filter_find_vlan(efx, vid); 4748 if (!vlan) { 4749 netif_err(efx, drv, efx->net_dev, 4750 "VLAN %u not found in filter state\n", vid); 4751 return; 4752 } 4753 4754 efx_ef10_filter_del_vlan_internal(efx, vlan); 4755 } 4756 4757 static int efx_ef10_set_mac_address(struct efx_nic *efx) 4758 { 4759 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 4760 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4761 bool was_enabled = efx->port_enabled; 4762 int rc; 4763 4764 efx_device_detach_sync(efx); 4765 efx_net_stop(efx->net_dev); 4766 4767 mutex_lock(&efx->mac_lock); 4768 down_write(&efx->filter_sem); 4769 efx_ef10_filter_table_remove(efx); 4770 4771 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 4772 efx->net_dev->dev_addr); 4773 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 4774 nic_data->vport_id); 4775 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 4776 sizeof(inbuf), NULL, 0, NULL); 4777 4778 efx_ef10_filter_table_probe(efx); 4779 up_write(&efx->filter_sem); 4780 mutex_unlock(&efx->mac_lock); 4781 4782 if (was_enabled) 4783 efx_net_open(efx->net_dev); 4784 netif_device_attach(efx->net_dev); 4785 4786 #ifdef CONFIG_SFC_SRIOV 4787 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 4788 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 4789 4790 if (rc == -EPERM) { 4791 struct efx_nic *efx_pf; 4792 4793 /* Switch to PF and change MAC address on vport */ 4794 efx_pf = pci_get_drvdata(pci_dev_pf); 4795 4796 rc = efx_ef10_sriov_set_vf_mac(efx_pf, 4797 nic_data->vf_index, 4798 efx->net_dev->dev_addr); 4799 } else if (!rc) { 4800 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 4801 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data; 4802 unsigned int i; 4803 4804 /* MAC address successfully changed by VF (with MAC 4805 * spoofing) so update the parent PF if possible. 4806 */ 4807 for (i = 0; i < efx_pf->vf_count; ++i) { 4808 struct ef10_vf *vf = nic_data->vf + i; 4809 4810 if (vf->efx == efx) { 4811 ether_addr_copy(vf->mac, 4812 efx->net_dev->dev_addr); 4813 return 0; 4814 } 4815 } 4816 } 4817 } else 4818 #endif 4819 if (rc == -EPERM) { 4820 netif_err(efx, drv, efx->net_dev, 4821 "Cannot change MAC address; use sfboot to enable" 4822 " mac-spoofing on this interface\n"); 4823 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 4824 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 4825 * fall-back to the method of changing the MAC address on the 4826 * vport. This only applies to PFs because such versions of 4827 * MCFW do not support VFs. 4828 */ 4829 rc = efx_ef10_vport_set_mac_address(efx); 4830 } else { 4831 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 4832 sizeof(inbuf), NULL, 0, rc); 4833 } 4834 4835 return rc; 4836 } 4837 4838 static int efx_ef10_mac_reconfigure(struct efx_nic *efx) 4839 { 4840 efx_ef10_filter_sync_rx_mode(efx); 4841 4842 return efx_mcdi_set_mac(efx); 4843 } 4844 4845 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx) 4846 { 4847 efx_ef10_filter_sync_rx_mode(efx); 4848 4849 return 0; 4850 } 4851 4852 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 4853 { 4854 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 4855 4856 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 4857 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 4858 NULL, 0, NULL); 4859 } 4860 4861 /* MC BISTs follow a different poll mechanism to phy BISTs. 4862 * The BIST is done in the poll handler on the MC, and the MCDI command 4863 * will block until the BIST is done. 4864 */ 4865 static int efx_ef10_poll_bist(struct efx_nic *efx) 4866 { 4867 int rc; 4868 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 4869 size_t outlen; 4870 u32 result; 4871 4872 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 4873 outbuf, sizeof(outbuf), &outlen); 4874 if (rc != 0) 4875 return rc; 4876 4877 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 4878 return -EIO; 4879 4880 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 4881 switch (result) { 4882 case MC_CMD_POLL_BIST_PASSED: 4883 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 4884 return 0; 4885 case MC_CMD_POLL_BIST_TIMEOUT: 4886 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 4887 return -EIO; 4888 case MC_CMD_POLL_BIST_FAILED: 4889 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 4890 return -EIO; 4891 default: 4892 netif_err(efx, hw, efx->net_dev, 4893 "BIST returned unknown result %u", result); 4894 return -EIO; 4895 } 4896 } 4897 4898 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 4899 { 4900 int rc; 4901 4902 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 4903 4904 rc = efx_ef10_start_bist(efx, bist_type); 4905 if (rc != 0) 4906 return rc; 4907 4908 return efx_ef10_poll_bist(efx); 4909 } 4910 4911 static int 4912 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 4913 { 4914 int rc, rc2; 4915 4916 efx_reset_down(efx, RESET_TYPE_WORLD); 4917 4918 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 4919 NULL, 0, NULL, 0, NULL); 4920 if (rc != 0) 4921 goto out; 4922 4923 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 4924 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 4925 4926 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 4927 4928 out: 4929 if (rc == -EPERM) 4930 rc = 0; 4931 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 4932 return rc ? rc : rc2; 4933 } 4934 4935 #ifdef CONFIG_SFC_MTD 4936 4937 struct efx_ef10_nvram_type_info { 4938 u16 type, type_mask; 4939 u8 port; 4940 const char *name; 4941 }; 4942 4943 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 4944 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 4945 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 4946 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 4947 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 4948 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 4949 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 4950 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 4951 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 4952 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 4953 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 4954 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 4955 }; 4956 4957 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 4958 struct efx_mcdi_mtd_partition *part, 4959 unsigned int type) 4960 { 4961 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 4962 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 4963 const struct efx_ef10_nvram_type_info *info; 4964 size_t size, erase_size, outlen; 4965 bool protected; 4966 int rc; 4967 4968 for (info = efx_ef10_nvram_types; ; info++) { 4969 if (info == 4970 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types)) 4971 return -ENODEV; 4972 if ((type & ~info->type_mask) == info->type) 4973 break; 4974 } 4975 if (info->port != efx_port_num(efx)) 4976 return -ENODEV; 4977 4978 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 4979 if (rc) 4980 return rc; 4981 if (protected) 4982 return -ENODEV; /* hide it */ 4983 4984 part->nvram_type = type; 4985 4986 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 4987 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 4988 outbuf, sizeof(outbuf), &outlen); 4989 if (rc) 4990 return rc; 4991 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 4992 return -EIO; 4993 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 4994 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 4995 part->fw_subtype = MCDI_DWORD(outbuf, 4996 NVRAM_METADATA_OUT_SUBTYPE); 4997 4998 part->common.dev_type_name = "EF10 NVRAM manager"; 4999 part->common.type_name = info->name; 5000 5001 part->common.mtd.type = MTD_NORFLASH; 5002 part->common.mtd.flags = MTD_CAP_NORFLASH; 5003 part->common.mtd.size = size; 5004 part->common.mtd.erasesize = erase_size; 5005 5006 return 0; 5007 } 5008 5009 static int efx_ef10_mtd_probe(struct efx_nic *efx) 5010 { 5011 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 5012 struct efx_mcdi_mtd_partition *parts; 5013 size_t outlen, n_parts_total, i, n_parts; 5014 unsigned int type; 5015 int rc; 5016 5017 ASSERT_RTNL(); 5018 5019 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 5020 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 5021 outbuf, sizeof(outbuf), &outlen); 5022 if (rc) 5023 return rc; 5024 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 5025 return -EIO; 5026 5027 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 5028 if (n_parts_total > 5029 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 5030 return -EIO; 5031 5032 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 5033 if (!parts) 5034 return -ENOMEM; 5035 5036 n_parts = 0; 5037 for (i = 0; i < n_parts_total; i++) { 5038 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 5039 i); 5040 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type); 5041 if (rc == 0) 5042 n_parts++; 5043 else if (rc != -ENODEV) 5044 goto fail; 5045 } 5046 5047 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 5048 fail: 5049 if (rc) 5050 kfree(parts); 5051 return rc; 5052 } 5053 5054 #endif /* CONFIG_SFC_MTD */ 5055 5056 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 5057 { 5058 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 5059 } 5060 5061 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 5062 u32 host_time) {} 5063 5064 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 5065 bool temp) 5066 { 5067 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 5068 int rc; 5069 5070 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 5071 channel->sync_events_state == SYNC_EVENTS_VALID || 5072 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 5073 return 0; 5074 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 5075 5076 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 5077 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 5078 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 5079 channel->channel); 5080 5081 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 5082 inbuf, sizeof(inbuf), NULL, 0, NULL); 5083 5084 if (rc != 0) 5085 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 5086 SYNC_EVENTS_DISABLED; 5087 5088 return rc; 5089 } 5090 5091 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 5092 bool temp) 5093 { 5094 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 5095 int rc; 5096 5097 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 5098 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 5099 return 0; 5100 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 5101 channel->sync_events_state = SYNC_EVENTS_DISABLED; 5102 return 0; 5103 } 5104 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 5105 SYNC_EVENTS_DISABLED; 5106 5107 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 5108 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 5109 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 5110 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 5111 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 5112 channel->channel); 5113 5114 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 5115 inbuf, sizeof(inbuf), NULL, 0, NULL); 5116 5117 return rc; 5118 } 5119 5120 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 5121 bool temp) 5122 { 5123 int (*set)(struct efx_channel *channel, bool temp); 5124 struct efx_channel *channel; 5125 5126 set = en ? 5127 efx_ef10_rx_enable_timestamping : 5128 efx_ef10_rx_disable_timestamping; 5129 5130 efx_for_each_channel(channel, efx) { 5131 int rc = set(channel, temp); 5132 if (en && rc != 0) { 5133 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 5134 return rc; 5135 } 5136 } 5137 5138 return 0; 5139 } 5140 5141 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 5142 struct hwtstamp_config *init) 5143 { 5144 return -EOPNOTSUPP; 5145 } 5146 5147 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 5148 struct hwtstamp_config *init) 5149 { 5150 int rc; 5151 5152 switch (init->rx_filter) { 5153 case HWTSTAMP_FILTER_NONE: 5154 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 5155 /* if TX timestamping is still requested then leave PTP on */ 5156 return efx_ptp_change_mode(efx, 5157 init->tx_type != HWTSTAMP_TX_OFF, 0); 5158 case HWTSTAMP_FILTER_ALL: 5159 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 5160 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 5161 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 5162 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 5163 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 5164 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 5165 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 5166 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 5167 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 5168 case HWTSTAMP_FILTER_PTP_V2_EVENT: 5169 case HWTSTAMP_FILTER_PTP_V2_SYNC: 5170 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 5171 init->rx_filter = HWTSTAMP_FILTER_ALL; 5172 rc = efx_ptp_change_mode(efx, true, 0); 5173 if (!rc) 5174 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 5175 if (rc) 5176 efx_ptp_change_mode(efx, false, 0); 5177 return rc; 5178 default: 5179 return -ERANGE; 5180 } 5181 } 5182 5183 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid) 5184 { 5185 if (proto != htons(ETH_P_8021Q)) 5186 return -EINVAL; 5187 5188 return efx_ef10_add_vlan(efx, vid); 5189 } 5190 5191 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid) 5192 { 5193 if (proto != htons(ETH_P_8021Q)) 5194 return -EINVAL; 5195 5196 return efx_ef10_del_vlan(efx, vid); 5197 } 5198 5199 #define EF10_OFFLOAD_FEATURES \ 5200 (NETIF_F_IP_CSUM | \ 5201 NETIF_F_HW_VLAN_CTAG_FILTER | \ 5202 NETIF_F_IPV6_CSUM | \ 5203 NETIF_F_RXHASH | \ 5204 NETIF_F_NTUPLE) 5205 5206 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 5207 .is_vf = true, 5208 .mem_bar = EFX_MEM_VF_BAR, 5209 .mem_map_size = efx_ef10_mem_map_size, 5210 .probe = efx_ef10_probe_vf, 5211 .remove = efx_ef10_remove, 5212 .dimension_resources = efx_ef10_dimension_resources, 5213 .init = efx_ef10_init_nic, 5214 .fini = efx_port_dummy_op_void, 5215 .map_reset_reason = efx_ef10_map_reset_reason, 5216 .map_reset_flags = efx_ef10_map_reset_flags, 5217 .reset = efx_ef10_reset, 5218 .probe_port = efx_mcdi_port_probe, 5219 .remove_port = efx_mcdi_port_remove, 5220 .fini_dmaq = efx_ef10_fini_dmaq, 5221 .prepare_flr = efx_ef10_prepare_flr, 5222 .finish_flr = efx_port_dummy_op_void, 5223 .describe_stats = efx_ef10_describe_stats, 5224 .update_stats = efx_ef10_update_stats_vf, 5225 .start_stats = efx_port_dummy_op_void, 5226 .pull_stats = efx_port_dummy_op_void, 5227 .stop_stats = efx_port_dummy_op_void, 5228 .set_id_led = efx_mcdi_set_id_led, 5229 .push_irq_moderation = efx_ef10_push_irq_moderation, 5230 .reconfigure_mac = efx_ef10_mac_reconfigure_vf, 5231 .check_mac_fault = efx_mcdi_mac_check_fault, 5232 .reconfigure_port = efx_mcdi_port_reconfigure, 5233 .get_wol = efx_ef10_get_wol_vf, 5234 .set_wol = efx_ef10_set_wol_vf, 5235 .resume_wol = efx_port_dummy_op_void, 5236 .mcdi_request = efx_ef10_mcdi_request, 5237 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 5238 .mcdi_read_response = efx_ef10_mcdi_read_response, 5239 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 5240 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 5241 .irq_enable_master = efx_port_dummy_op_void, 5242 .irq_test_generate = efx_ef10_irq_test_generate, 5243 .irq_disable_non_ev = efx_port_dummy_op_void, 5244 .irq_handle_msi = efx_ef10_msi_interrupt, 5245 .irq_handle_legacy = efx_ef10_legacy_interrupt, 5246 .tx_probe = efx_ef10_tx_probe, 5247 .tx_init = efx_ef10_tx_init, 5248 .tx_remove = efx_ef10_tx_remove, 5249 .tx_write = efx_ef10_tx_write, 5250 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config, 5251 .rx_probe = efx_ef10_rx_probe, 5252 .rx_init = efx_ef10_rx_init, 5253 .rx_remove = efx_ef10_rx_remove, 5254 .rx_write = efx_ef10_rx_write, 5255 .rx_defer_refill = efx_ef10_rx_defer_refill, 5256 .ev_probe = efx_ef10_ev_probe, 5257 .ev_init = efx_ef10_ev_init, 5258 .ev_fini = efx_ef10_ev_fini, 5259 .ev_remove = efx_ef10_ev_remove, 5260 .ev_process = efx_ef10_ev_process, 5261 .ev_read_ack = efx_ef10_ev_read_ack, 5262 .ev_test_generate = efx_ef10_ev_test_generate, 5263 .filter_table_probe = efx_ef10_filter_table_probe, 5264 .filter_table_restore = efx_ef10_filter_table_restore, 5265 .filter_table_remove = efx_ef10_filter_table_remove, 5266 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 5267 .filter_insert = efx_ef10_filter_insert, 5268 .filter_remove_safe = efx_ef10_filter_remove_safe, 5269 .filter_get_safe = efx_ef10_filter_get_safe, 5270 .filter_clear_rx = efx_ef10_filter_clear_rx, 5271 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 5272 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 5273 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 5274 #ifdef CONFIG_RFS_ACCEL 5275 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 5276 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 5277 #endif 5278 #ifdef CONFIG_SFC_MTD 5279 .mtd_probe = efx_port_dummy_op_int, 5280 #endif 5281 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 5282 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 5283 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 5284 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 5285 #ifdef CONFIG_SFC_SRIOV 5286 .vswitching_probe = efx_ef10_vswitching_probe_vf, 5287 .vswitching_restore = efx_ef10_vswitching_restore_vf, 5288 .vswitching_remove = efx_ef10_vswitching_remove_vf, 5289 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id, 5290 #endif 5291 .get_mac_address = efx_ef10_get_mac_address_vf, 5292 .set_mac_address = efx_ef10_set_mac_address, 5293 5294 .revision = EFX_REV_HUNT_A0, 5295 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 5296 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 5297 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 5298 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 5299 .can_rx_scatter = true, 5300 .always_rx_scatter = true, 5301 .max_interrupt_mode = EFX_INT_MODE_MSIX, 5302 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 5303 .offload_features = EF10_OFFLOAD_FEATURES, 5304 .mcdi_max_ver = 2, 5305 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 5306 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 5307 1 << HWTSTAMP_FILTER_ALL, 5308 }; 5309 5310 const struct efx_nic_type efx_hunt_a0_nic_type = { 5311 .is_vf = false, 5312 .mem_bar = EFX_MEM_BAR, 5313 .mem_map_size = efx_ef10_mem_map_size, 5314 .probe = efx_ef10_probe_pf, 5315 .remove = efx_ef10_remove, 5316 .dimension_resources = efx_ef10_dimension_resources, 5317 .init = efx_ef10_init_nic, 5318 .fini = efx_port_dummy_op_void, 5319 .map_reset_reason = efx_ef10_map_reset_reason, 5320 .map_reset_flags = efx_ef10_map_reset_flags, 5321 .reset = efx_ef10_reset, 5322 .probe_port = efx_mcdi_port_probe, 5323 .remove_port = efx_mcdi_port_remove, 5324 .fini_dmaq = efx_ef10_fini_dmaq, 5325 .prepare_flr = efx_ef10_prepare_flr, 5326 .finish_flr = efx_port_dummy_op_void, 5327 .describe_stats = efx_ef10_describe_stats, 5328 .update_stats = efx_ef10_update_stats_pf, 5329 .start_stats = efx_mcdi_mac_start_stats, 5330 .pull_stats = efx_mcdi_mac_pull_stats, 5331 .stop_stats = efx_mcdi_mac_stop_stats, 5332 .set_id_led = efx_mcdi_set_id_led, 5333 .push_irq_moderation = efx_ef10_push_irq_moderation, 5334 .reconfigure_mac = efx_ef10_mac_reconfigure, 5335 .check_mac_fault = efx_mcdi_mac_check_fault, 5336 .reconfigure_port = efx_mcdi_port_reconfigure, 5337 .get_wol = efx_ef10_get_wol, 5338 .set_wol = efx_ef10_set_wol, 5339 .resume_wol = efx_port_dummy_op_void, 5340 .test_chip = efx_ef10_test_chip, 5341 .test_nvram = efx_mcdi_nvram_test_all, 5342 .mcdi_request = efx_ef10_mcdi_request, 5343 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 5344 .mcdi_read_response = efx_ef10_mcdi_read_response, 5345 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 5346 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 5347 .irq_enable_master = efx_port_dummy_op_void, 5348 .irq_test_generate = efx_ef10_irq_test_generate, 5349 .irq_disable_non_ev = efx_port_dummy_op_void, 5350 .irq_handle_msi = efx_ef10_msi_interrupt, 5351 .irq_handle_legacy = efx_ef10_legacy_interrupt, 5352 .tx_probe = efx_ef10_tx_probe, 5353 .tx_init = efx_ef10_tx_init, 5354 .tx_remove = efx_ef10_tx_remove, 5355 .tx_write = efx_ef10_tx_write, 5356 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config, 5357 .rx_probe = efx_ef10_rx_probe, 5358 .rx_init = efx_ef10_rx_init, 5359 .rx_remove = efx_ef10_rx_remove, 5360 .rx_write = efx_ef10_rx_write, 5361 .rx_defer_refill = efx_ef10_rx_defer_refill, 5362 .ev_probe = efx_ef10_ev_probe, 5363 .ev_init = efx_ef10_ev_init, 5364 .ev_fini = efx_ef10_ev_fini, 5365 .ev_remove = efx_ef10_ev_remove, 5366 .ev_process = efx_ef10_ev_process, 5367 .ev_read_ack = efx_ef10_ev_read_ack, 5368 .ev_test_generate = efx_ef10_ev_test_generate, 5369 .filter_table_probe = efx_ef10_filter_table_probe, 5370 .filter_table_restore = efx_ef10_filter_table_restore, 5371 .filter_table_remove = efx_ef10_filter_table_remove, 5372 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 5373 .filter_insert = efx_ef10_filter_insert, 5374 .filter_remove_safe = efx_ef10_filter_remove_safe, 5375 .filter_get_safe = efx_ef10_filter_get_safe, 5376 .filter_clear_rx = efx_ef10_filter_clear_rx, 5377 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 5378 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 5379 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 5380 #ifdef CONFIG_RFS_ACCEL 5381 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 5382 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 5383 #endif 5384 #ifdef CONFIG_SFC_MTD 5385 .mtd_probe = efx_ef10_mtd_probe, 5386 .mtd_rename = efx_mcdi_mtd_rename, 5387 .mtd_read = efx_mcdi_mtd_read, 5388 .mtd_erase = efx_mcdi_mtd_erase, 5389 .mtd_write = efx_mcdi_mtd_write, 5390 .mtd_sync = efx_mcdi_mtd_sync, 5391 #endif 5392 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 5393 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 5394 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 5395 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 5396 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 5397 #ifdef CONFIG_SFC_SRIOV 5398 .sriov_configure = efx_ef10_sriov_configure, 5399 .sriov_init = efx_ef10_sriov_init, 5400 .sriov_fini = efx_ef10_sriov_fini, 5401 .sriov_wanted = efx_ef10_sriov_wanted, 5402 .sriov_reset = efx_ef10_sriov_reset, 5403 .sriov_flr = efx_ef10_sriov_flr, 5404 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 5405 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 5406 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 5407 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 5408 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 5409 .vswitching_probe = efx_ef10_vswitching_probe_pf, 5410 .vswitching_restore = efx_ef10_vswitching_restore_pf, 5411 .vswitching_remove = efx_ef10_vswitching_remove_pf, 5412 #endif 5413 .get_mac_address = efx_ef10_get_mac_address_pf, 5414 .set_mac_address = efx_ef10_set_mac_address, 5415 5416 .revision = EFX_REV_HUNT_A0, 5417 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 5418 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 5419 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 5420 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 5421 .can_rx_scatter = true, 5422 .always_rx_scatter = true, 5423 .max_interrupt_mode = EFX_INT_MODE_MSIX, 5424 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 5425 .offload_features = EF10_OFFLOAD_FEATURES, 5426 .mcdi_max_ver = 2, 5427 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 5428 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 5429 1 << HWTSTAMP_FILTER_ALL, 5430 }; 5431