1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2012-2013 Solarflare Communications Inc. 5 */ 6 7 #include "net_driver.h" 8 #include "rx_common.h" 9 #include "tx_common.h" 10 #include "ef10_regs.h" 11 #include "io.h" 12 #include "mcdi.h" 13 #include "mcdi_pcol.h" 14 #include "mcdi_port.h" 15 #include "mcdi_port_common.h" 16 #include "mcdi_functions.h" 17 #include "nic.h" 18 #include "mcdi_filters.h" 19 #include "workarounds.h" 20 #include "selftest.h" 21 #include "ef10_sriov.h" 22 #include <linux/in.h> 23 #include <linux/jhash.h> 24 #include <linux/wait.h> 25 #include <linux/workqueue.h> 26 #include <net/udp_tunnel.h> 27 28 /* Hardware control for EF10 architecture including 'Huntington'. */ 29 30 #define EFX_EF10_DRVGEN_EV 7 31 enum { 32 EFX_EF10_TEST = 1, 33 EFX_EF10_REFILL, 34 }; 35 36 /* VLAN list entry */ 37 struct efx_ef10_vlan { 38 struct list_head list; 39 u16 vid; 40 }; 41 42 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading); 43 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels; 44 45 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 46 { 47 efx_dword_t reg; 48 49 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 50 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 51 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 52 } 53 54 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for 55 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O 56 * bar; PFs use BAR 0/1 for memory. 57 */ 58 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx) 59 { 60 switch (efx->pci_dev->device) { 61 case 0x0b03: /* SFC9250 PF */ 62 return 0; 63 default: 64 return 2; 65 } 66 } 67 68 /* All VFs use BAR 0/1 for memory */ 69 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx) 70 { 71 return 0; 72 } 73 74 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 75 { 76 int bar; 77 78 bar = efx->type->mem_bar(efx); 79 return resource_size(&efx->pci_dev->resource[bar]); 80 } 81 82 static bool efx_ef10_is_vf(struct efx_nic *efx) 83 { 84 return efx->type->is_vf; 85 } 86 87 #ifdef CONFIG_SFC_SRIOV 88 static int efx_ef10_get_vf_index(struct efx_nic *efx) 89 { 90 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 91 struct efx_ef10_nic_data *nic_data = efx->nic_data; 92 size_t outlen; 93 int rc; 94 95 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 96 sizeof(outbuf), &outlen); 97 if (rc) 98 return rc; 99 if (outlen < sizeof(outbuf)) 100 return -EIO; 101 102 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 103 return 0; 104 } 105 #endif 106 107 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 108 { 109 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN); 110 struct efx_ef10_nic_data *nic_data = efx->nic_data; 111 size_t outlen; 112 int rc; 113 114 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 115 116 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 117 outbuf, sizeof(outbuf), &outlen); 118 if (rc) 119 return rc; 120 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 121 netif_err(efx, drv, efx->net_dev, 122 "unable to read datapath firmware capabilities\n"); 123 return -EIO; 124 } 125 126 nic_data->datapath_caps = 127 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 128 129 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) { 130 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 131 GET_CAPABILITIES_V2_OUT_FLAGS2); 132 nic_data->piobuf_size = MCDI_WORD(outbuf, 133 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF); 134 } else { 135 nic_data->datapath_caps2 = 0; 136 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE; 137 } 138 139 /* record the DPCPU firmware IDs to determine VEB vswitching support. 140 */ 141 nic_data->rx_dpcpu_fw_id = 142 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 143 nic_data->tx_dpcpu_fw_id = 144 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 145 146 if (!(nic_data->datapath_caps & 147 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 148 netif_err(efx, probe, efx->net_dev, 149 "current firmware does not support an RX prefix\n"); 150 return -ENODEV; 151 } 152 153 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { 154 u8 vi_window_mode = MCDI_BYTE(outbuf, 155 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 156 157 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 158 if (rc) 159 return rc; 160 } else { 161 /* keep default VI stride */ 162 netif_dbg(efx, probe, efx->net_dev, 163 "firmware did not report VI window mode, assuming vi_stride = %u\n", 164 efx->vi_stride); 165 } 166 167 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 168 efx->num_mac_stats = MCDI_WORD(outbuf, 169 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 170 netif_dbg(efx, probe, efx->net_dev, 171 "firmware reports num_mac_stats = %u\n", 172 efx->num_mac_stats); 173 } else { 174 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */ 175 netif_dbg(efx, probe, efx->net_dev, 176 "firmware did not report num_mac_stats, assuming %u\n", 177 efx->num_mac_stats); 178 } 179 180 return 0; 181 } 182 183 static void efx_ef10_read_licensed_features(struct efx_nic *efx) 184 { 185 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN); 186 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN); 187 struct efx_ef10_nic_data *nic_data = efx->nic_data; 188 size_t outlen; 189 int rc; 190 191 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP, 192 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE); 193 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf), 194 outbuf, sizeof(outbuf), &outlen); 195 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN)) 196 return; 197 198 nic_data->licensed_features = MCDI_QWORD(outbuf, 199 LICENSING_V3_OUT_LICENSED_FEATURES); 200 } 201 202 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 203 { 204 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 205 int rc; 206 207 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 208 outbuf, sizeof(outbuf), NULL); 209 if (rc) 210 return rc; 211 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 212 return rc > 0 ? rc : -ERANGE; 213 } 214 215 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx) 216 { 217 struct efx_ef10_nic_data *nic_data = efx->nic_data; 218 unsigned int implemented; 219 unsigned int enabled; 220 int rc; 221 222 nic_data->workaround_35388 = false; 223 nic_data->workaround_61265 = false; 224 225 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 226 227 if (rc == -ENOSYS) { 228 /* Firmware without GET_WORKAROUNDS - not a problem. */ 229 rc = 0; 230 } else if (rc == 0) { 231 /* Bug61265 workaround is always enabled if implemented. */ 232 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265) 233 nic_data->workaround_61265 = true; 234 235 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 236 nic_data->workaround_35388 = true; 237 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 238 /* Workaround is implemented but not enabled. 239 * Try to enable it. 240 */ 241 rc = efx_mcdi_set_workaround(efx, 242 MC_CMD_WORKAROUND_BUG35388, 243 true, NULL); 244 if (rc == 0) 245 nic_data->workaround_35388 = true; 246 /* If we failed to set the workaround just carry on. */ 247 rc = 0; 248 } 249 } 250 251 netif_dbg(efx, probe, efx->net_dev, 252 "workaround for bug 35388 is %sabled\n", 253 nic_data->workaround_35388 ? "en" : "dis"); 254 netif_dbg(efx, probe, efx->net_dev, 255 "workaround for bug 61265 is %sabled\n", 256 nic_data->workaround_61265 ? "en" : "dis"); 257 258 return rc; 259 } 260 261 static void efx_ef10_process_timer_config(struct efx_nic *efx, 262 const efx_dword_t *data) 263 { 264 unsigned int max_count; 265 266 if (EFX_EF10_WORKAROUND_61265(efx)) { 267 efx->timer_quantum_ns = MCDI_DWORD(data, 268 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS); 269 efx->timer_max_ns = MCDI_DWORD(data, 270 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS); 271 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 272 efx->timer_quantum_ns = MCDI_DWORD(data, 273 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT); 274 max_count = MCDI_DWORD(data, 275 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT); 276 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 277 } else { 278 efx->timer_quantum_ns = MCDI_DWORD(data, 279 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT); 280 max_count = MCDI_DWORD(data, 281 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT); 282 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 283 } 284 285 netif_dbg(efx, probe, efx->net_dev, 286 "got timer properties from MC: quantum %u ns; max %u ns\n", 287 efx->timer_quantum_ns, efx->timer_max_ns); 288 } 289 290 static int efx_ef10_get_timer_config(struct efx_nic *efx) 291 { 292 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN); 293 int rc; 294 295 rc = efx_ef10_get_timer_workarounds(efx); 296 if (rc) 297 return rc; 298 299 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0, 300 outbuf, sizeof(outbuf), NULL); 301 302 if (rc == 0) { 303 efx_ef10_process_timer_config(efx, outbuf); 304 } else if (rc == -ENOSYS || rc == -EPERM) { 305 /* Not available - fall back to Huntington defaults. */ 306 unsigned int quantum; 307 308 rc = efx_ef10_get_sysclk_freq(efx); 309 if (rc < 0) 310 return rc; 311 312 quantum = 1536000 / rc; /* 1536 cycles */ 313 efx->timer_quantum_ns = quantum; 314 efx->timer_max_ns = efx->type->timer_period_max * quantum; 315 rc = 0; 316 } else { 317 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, 318 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN, 319 NULL, 0, rc); 320 } 321 322 return rc; 323 } 324 325 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 326 { 327 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 328 size_t outlen; 329 int rc; 330 331 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 332 333 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 334 outbuf, sizeof(outbuf), &outlen); 335 if (rc) 336 return rc; 337 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 338 return -EIO; 339 340 ether_addr_copy(mac_address, 341 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 342 return 0; 343 } 344 345 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 346 { 347 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 348 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 349 size_t outlen; 350 int num_addrs, rc; 351 352 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 353 EVB_PORT_ID_ASSIGNED); 354 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 355 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 356 357 if (rc) 358 return rc; 359 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 360 return -EIO; 361 362 num_addrs = MCDI_DWORD(outbuf, 363 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 364 365 WARN_ON(num_addrs != 1); 366 367 ether_addr_copy(mac_address, 368 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 369 370 return 0; 371 } 372 373 static ssize_t efx_ef10_show_link_control_flag(struct device *dev, 374 struct device_attribute *attr, 375 char *buf) 376 { 377 struct efx_nic *efx = dev_get_drvdata(dev); 378 379 return sprintf(buf, "%d\n", 380 ((efx->mcdi->fn_flags) & 381 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 382 ? 1 : 0); 383 } 384 385 static ssize_t efx_ef10_show_primary_flag(struct device *dev, 386 struct device_attribute *attr, 387 char *buf) 388 { 389 struct efx_nic *efx = dev_get_drvdata(dev); 390 391 return sprintf(buf, "%d\n", 392 ((efx->mcdi->fn_flags) & 393 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 394 ? 1 : 0); 395 } 396 397 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid) 398 { 399 struct efx_ef10_nic_data *nic_data = efx->nic_data; 400 struct efx_ef10_vlan *vlan; 401 402 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 403 404 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 405 if (vlan->vid == vid) 406 return vlan; 407 } 408 409 return NULL; 410 } 411 412 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid) 413 { 414 struct efx_ef10_nic_data *nic_data = efx->nic_data; 415 struct efx_ef10_vlan *vlan; 416 int rc; 417 418 mutex_lock(&nic_data->vlan_lock); 419 420 vlan = efx_ef10_find_vlan(efx, vid); 421 if (vlan) { 422 /* We add VID 0 on init. 8021q adds it on module init 423 * for all interfaces with VLAN filtring feature. 424 */ 425 if (vid == 0) 426 goto done_unlock; 427 netif_warn(efx, drv, efx->net_dev, 428 "VLAN %u already added\n", vid); 429 rc = -EALREADY; 430 goto fail_exist; 431 } 432 433 rc = -ENOMEM; 434 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 435 if (!vlan) 436 goto fail_alloc; 437 438 vlan->vid = vid; 439 440 list_add_tail(&vlan->list, &nic_data->vlan_list); 441 442 if (efx->filter_state) { 443 mutex_lock(&efx->mac_lock); 444 down_write(&efx->filter_sem); 445 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 446 up_write(&efx->filter_sem); 447 mutex_unlock(&efx->mac_lock); 448 if (rc) 449 goto fail_filter_add_vlan; 450 } 451 452 done_unlock: 453 mutex_unlock(&nic_data->vlan_lock); 454 return 0; 455 456 fail_filter_add_vlan: 457 list_del(&vlan->list); 458 kfree(vlan); 459 fail_alloc: 460 fail_exist: 461 mutex_unlock(&nic_data->vlan_lock); 462 return rc; 463 } 464 465 static void efx_ef10_del_vlan_internal(struct efx_nic *efx, 466 struct efx_ef10_vlan *vlan) 467 { 468 struct efx_ef10_nic_data *nic_data = efx->nic_data; 469 470 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 471 472 if (efx->filter_state) { 473 down_write(&efx->filter_sem); 474 efx_mcdi_filter_del_vlan(efx, vlan->vid); 475 up_write(&efx->filter_sem); 476 } 477 478 list_del(&vlan->list); 479 kfree(vlan); 480 } 481 482 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid) 483 { 484 struct efx_ef10_nic_data *nic_data = efx->nic_data; 485 struct efx_ef10_vlan *vlan; 486 int rc = 0; 487 488 /* 8021q removes VID 0 on module unload for all interfaces 489 * with VLAN filtering feature. We need to keep it to receive 490 * untagged traffic. 491 */ 492 if (vid == 0) 493 return 0; 494 495 mutex_lock(&nic_data->vlan_lock); 496 497 vlan = efx_ef10_find_vlan(efx, vid); 498 if (!vlan) { 499 netif_err(efx, drv, efx->net_dev, 500 "VLAN %u to be deleted not found\n", vid); 501 rc = -ENOENT; 502 } else { 503 efx_ef10_del_vlan_internal(efx, vlan); 504 } 505 506 mutex_unlock(&nic_data->vlan_lock); 507 508 return rc; 509 } 510 511 static void efx_ef10_cleanup_vlans(struct efx_nic *efx) 512 { 513 struct efx_ef10_nic_data *nic_data = efx->nic_data; 514 struct efx_ef10_vlan *vlan, *next_vlan; 515 516 mutex_lock(&nic_data->vlan_lock); 517 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list) 518 efx_ef10_del_vlan_internal(efx, vlan); 519 mutex_unlock(&nic_data->vlan_lock); 520 } 521 522 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag, 523 NULL); 524 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL); 525 526 static int efx_ef10_probe(struct efx_nic *efx) 527 { 528 struct efx_ef10_nic_data *nic_data; 529 int i, rc; 530 531 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 532 if (!nic_data) 533 return -ENOMEM; 534 efx->nic_data = nic_data; 535 536 /* we assume later that we can copy from this buffer in dwords */ 537 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 538 539 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 540 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 541 if (rc) 542 goto fail1; 543 544 /* Get the MC's warm boot count. In case it's rebooting right 545 * now, be prepared to retry. 546 */ 547 i = 0; 548 for (;;) { 549 rc = efx_ef10_get_warm_boot_count(efx); 550 if (rc >= 0) 551 break; 552 if (++i == 5) 553 goto fail2; 554 ssleep(1); 555 } 556 nic_data->warm_boot_count = rc; 557 558 /* In case we're recovering from a crash (kexec), we want to 559 * cancel any outstanding request by the previous user of this 560 * function. We send a special message using the least 561 * significant bits of the 'high' (doorbell) register. 562 */ 563 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 564 565 rc = efx_mcdi_init(efx); 566 if (rc) 567 goto fail2; 568 569 mutex_init(&nic_data->udp_tunnels_lock); 570 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 571 nic_data->udp_tunnels[i].type = 572 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 573 574 /* Reset (most) configuration for this function */ 575 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 576 if (rc) 577 goto fail3; 578 579 /* Enable event logging */ 580 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 581 if (rc) 582 goto fail3; 583 584 rc = device_create_file(&efx->pci_dev->dev, 585 &dev_attr_link_control_flag); 586 if (rc) 587 goto fail3; 588 589 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 590 if (rc) 591 goto fail4; 592 593 rc = efx_get_pf_index(efx, &nic_data->pf_index); 594 if (rc) 595 goto fail5; 596 597 rc = efx_ef10_init_datapath_caps(efx); 598 if (rc < 0) 599 goto fail5; 600 601 efx_ef10_read_licensed_features(efx); 602 603 /* We can have one VI for each vi_stride-byte region. 604 * However, until we use TX option descriptors we need two TX queues 605 * per channel. 606 */ 607 efx->tx_queues_per_channel = 2; 608 efx->max_vis = efx_ef10_mem_map_size(efx) / efx->vi_stride; 609 if (!efx->max_vis) { 610 netif_err(efx, drv, efx->net_dev, "error determining max VIs\n"); 611 rc = -EIO; 612 goto fail5; 613 } 614 efx->max_channels = min_t(unsigned int, EFX_MAX_CHANNELS, 615 efx->max_vis / efx->tx_queues_per_channel); 616 efx->max_tx_channels = efx->max_channels; 617 if (WARN_ON(efx->max_channels == 0)) { 618 rc = -EIO; 619 goto fail5; 620 } 621 622 efx->rx_packet_len_offset = 623 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 624 625 if (nic_data->datapath_caps & 626 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN)) 627 efx->net_dev->hw_features |= NETIF_F_RXFCS; 628 629 rc = efx_mcdi_port_get_number(efx); 630 if (rc < 0) 631 goto fail5; 632 efx->port_num = rc; 633 634 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 635 if (rc) 636 goto fail5; 637 638 rc = efx_ef10_get_timer_config(efx); 639 if (rc < 0) 640 goto fail5; 641 642 rc = efx_mcdi_mon_probe(efx); 643 if (rc && rc != -EPERM) 644 goto fail5; 645 646 efx_ptp_defer_probe_with_channel(efx); 647 648 #ifdef CONFIG_SFC_SRIOV 649 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 650 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 651 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 652 653 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 654 } else 655 #endif 656 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 657 658 INIT_LIST_HEAD(&nic_data->vlan_list); 659 mutex_init(&nic_data->vlan_lock); 660 661 /* Add unspecified VID to support VLAN filtering being disabled */ 662 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 663 if (rc) 664 goto fail_add_vid_unspec; 665 666 /* If VLAN filtering is enabled, we need VID 0 to get untagged 667 * traffic. It is added automatically if 8021q module is loaded, 668 * but we can't rely on it since module may be not loaded. 669 */ 670 rc = efx_ef10_add_vlan(efx, 0); 671 if (rc) 672 goto fail_add_vid_0; 673 674 if (nic_data->datapath_caps & 675 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) && 676 efx->mcdi->fn_flags & 677 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) 678 efx->net_dev->udp_tunnel_nic_info = &efx_ef10_udp_tunnels; 679 680 return 0; 681 682 fail_add_vid_0: 683 efx_ef10_cleanup_vlans(efx); 684 fail_add_vid_unspec: 685 mutex_destroy(&nic_data->vlan_lock); 686 efx_ptp_remove(efx); 687 efx_mcdi_mon_remove(efx); 688 fail5: 689 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 690 fail4: 691 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 692 fail3: 693 efx_mcdi_detach(efx); 694 695 mutex_lock(&nic_data->udp_tunnels_lock); 696 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 697 (void)efx_ef10_set_udp_tnl_ports(efx, true); 698 mutex_unlock(&nic_data->udp_tunnels_lock); 699 mutex_destroy(&nic_data->udp_tunnels_lock); 700 701 efx_mcdi_fini(efx); 702 fail2: 703 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 704 fail1: 705 kfree(nic_data); 706 efx->nic_data = NULL; 707 return rc; 708 } 709 710 #ifdef EFX_USE_PIO 711 712 static void efx_ef10_free_piobufs(struct efx_nic *efx) 713 { 714 struct efx_ef10_nic_data *nic_data = efx->nic_data; 715 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 716 unsigned int i; 717 int rc; 718 719 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 720 721 for (i = 0; i < nic_data->n_piobufs; i++) { 722 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 723 nic_data->piobuf_handle[i]); 724 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 725 NULL, 0, NULL); 726 WARN_ON(rc); 727 } 728 729 nic_data->n_piobufs = 0; 730 } 731 732 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 733 { 734 struct efx_ef10_nic_data *nic_data = efx->nic_data; 735 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 736 unsigned int i; 737 size_t outlen; 738 int rc = 0; 739 740 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 741 742 for (i = 0; i < n; i++) { 743 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 744 outbuf, sizeof(outbuf), &outlen); 745 if (rc) { 746 /* Don't display the MC error if we didn't have space 747 * for a VF. 748 */ 749 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC)) 750 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF, 751 0, outbuf, outlen, rc); 752 break; 753 } 754 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 755 rc = -EIO; 756 break; 757 } 758 nic_data->piobuf_handle[i] = 759 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 760 netif_dbg(efx, probe, efx->net_dev, 761 "allocated PIO buffer %u handle %x\n", i, 762 nic_data->piobuf_handle[i]); 763 } 764 765 nic_data->n_piobufs = i; 766 if (rc) 767 efx_ef10_free_piobufs(efx); 768 return rc; 769 } 770 771 static int efx_ef10_link_piobufs(struct efx_nic *efx) 772 { 773 struct efx_ef10_nic_data *nic_data = efx->nic_data; 774 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN); 775 struct efx_channel *channel; 776 struct efx_tx_queue *tx_queue; 777 unsigned int offset, index; 778 int rc; 779 780 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 781 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 782 783 /* Link a buffer to each VI in the write-combining mapping */ 784 for (index = 0; index < nic_data->n_piobufs; ++index) { 785 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 786 nic_data->piobuf_handle[index]); 787 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 788 nic_data->pio_write_vi_base + index); 789 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 790 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 791 NULL, 0, NULL); 792 if (rc) { 793 netif_err(efx, drv, efx->net_dev, 794 "failed to link VI %u to PIO buffer %u (%d)\n", 795 nic_data->pio_write_vi_base + index, index, 796 rc); 797 goto fail; 798 } 799 netif_dbg(efx, probe, efx->net_dev, 800 "linked VI %u to PIO buffer %u\n", 801 nic_data->pio_write_vi_base + index, index); 802 } 803 804 /* Link a buffer to each TX queue */ 805 efx_for_each_channel(channel, efx) { 806 /* Extra channels, even those with TXQs (PTP), do not require 807 * PIO resources. 808 */ 809 if (!channel->type->want_pio || 810 channel->channel >= efx->xdp_channel_offset) 811 continue; 812 813 efx_for_each_channel_tx_queue(tx_queue, channel) { 814 /* We assign the PIO buffers to queues in 815 * reverse order to allow for the following 816 * special case. 817 */ 818 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 819 tx_queue->channel->channel - 1) * 820 efx_piobuf_size); 821 index = offset / nic_data->piobuf_size; 822 offset = offset % nic_data->piobuf_size; 823 824 /* When the host page size is 4K, the first 825 * host page in the WC mapping may be within 826 * the same VI page as the last TX queue. We 827 * can only link one buffer to each VI. 828 */ 829 if (tx_queue->queue == nic_data->pio_write_vi_base) { 830 BUG_ON(index != 0); 831 rc = 0; 832 } else { 833 MCDI_SET_DWORD(inbuf, 834 LINK_PIOBUF_IN_PIOBUF_HANDLE, 835 nic_data->piobuf_handle[index]); 836 MCDI_SET_DWORD(inbuf, 837 LINK_PIOBUF_IN_TXQ_INSTANCE, 838 tx_queue->queue); 839 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 840 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 841 NULL, 0, NULL); 842 } 843 844 if (rc) { 845 /* This is non-fatal; the TX path just 846 * won't use PIO for this queue 847 */ 848 netif_err(efx, drv, efx->net_dev, 849 "failed to link VI %u to PIO buffer %u (%d)\n", 850 tx_queue->queue, index, rc); 851 tx_queue->piobuf = NULL; 852 } else { 853 tx_queue->piobuf = 854 nic_data->pio_write_base + 855 index * efx->vi_stride + offset; 856 tx_queue->piobuf_offset = offset; 857 netif_dbg(efx, probe, efx->net_dev, 858 "linked VI %u to PIO buffer %u offset %x addr %p\n", 859 tx_queue->queue, index, 860 tx_queue->piobuf_offset, 861 tx_queue->piobuf); 862 } 863 } 864 } 865 866 return 0; 867 868 fail: 869 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same 870 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter. 871 */ 872 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN); 873 while (index--) { 874 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 875 nic_data->pio_write_vi_base + index); 876 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 877 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 878 NULL, 0, NULL); 879 } 880 return rc; 881 } 882 883 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 884 { 885 struct efx_channel *channel; 886 struct efx_tx_queue *tx_queue; 887 888 /* All our existing PIO buffers went away */ 889 efx_for_each_channel(channel, efx) 890 efx_for_each_channel_tx_queue(tx_queue, channel) 891 tx_queue->piobuf = NULL; 892 } 893 894 #else /* !EFX_USE_PIO */ 895 896 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 897 { 898 return n == 0 ? 0 : -ENOBUFS; 899 } 900 901 static int efx_ef10_link_piobufs(struct efx_nic *efx) 902 { 903 return 0; 904 } 905 906 static void efx_ef10_free_piobufs(struct efx_nic *efx) 907 { 908 } 909 910 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 911 { 912 } 913 914 #endif /* EFX_USE_PIO */ 915 916 static void efx_ef10_remove(struct efx_nic *efx) 917 { 918 struct efx_ef10_nic_data *nic_data = efx->nic_data; 919 int rc; 920 921 #ifdef CONFIG_SFC_SRIOV 922 struct efx_ef10_nic_data *nic_data_pf; 923 struct pci_dev *pci_dev_pf; 924 struct efx_nic *efx_pf; 925 struct ef10_vf *vf; 926 927 if (efx->pci_dev->is_virtfn) { 928 pci_dev_pf = efx->pci_dev->physfn; 929 if (pci_dev_pf) { 930 efx_pf = pci_get_drvdata(pci_dev_pf); 931 nic_data_pf = efx_pf->nic_data; 932 vf = nic_data_pf->vf + nic_data->vf_index; 933 vf->efx = NULL; 934 } else 935 netif_info(efx, drv, efx->net_dev, 936 "Could not get the PF id from VF\n"); 937 } 938 #endif 939 940 efx_ef10_cleanup_vlans(efx); 941 mutex_destroy(&nic_data->vlan_lock); 942 943 efx_ptp_remove(efx); 944 945 efx_mcdi_mon_remove(efx); 946 947 efx_mcdi_rx_free_indir_table(efx); 948 949 if (nic_data->wc_membase) 950 iounmap(nic_data->wc_membase); 951 952 rc = efx_mcdi_free_vis(efx); 953 WARN_ON(rc != 0); 954 955 if (!nic_data->must_restore_piobufs) 956 efx_ef10_free_piobufs(efx); 957 958 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 959 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 960 961 efx_mcdi_detach(efx); 962 963 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 964 mutex_lock(&nic_data->udp_tunnels_lock); 965 (void)efx_ef10_set_udp_tnl_ports(efx, true); 966 mutex_unlock(&nic_data->udp_tunnels_lock); 967 968 mutex_destroy(&nic_data->udp_tunnels_lock); 969 970 efx_mcdi_fini(efx); 971 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 972 kfree(nic_data); 973 } 974 975 static int efx_ef10_probe_pf(struct efx_nic *efx) 976 { 977 return efx_ef10_probe(efx); 978 } 979 980 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id, 981 u32 *port_flags, u32 *vadaptor_flags, 982 unsigned int *vlan_tags) 983 { 984 struct efx_ef10_nic_data *nic_data = efx->nic_data; 985 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN); 986 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN); 987 size_t outlen; 988 int rc; 989 990 if (nic_data->datapath_caps & 991 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) { 992 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID, 993 port_id); 994 995 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf), 996 outbuf, sizeof(outbuf), &outlen); 997 if (rc) 998 return rc; 999 1000 if (outlen < sizeof(outbuf)) { 1001 rc = -EIO; 1002 return rc; 1003 } 1004 } 1005 1006 if (port_flags) 1007 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS); 1008 if (vadaptor_flags) 1009 *vadaptor_flags = 1010 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS); 1011 if (vlan_tags) 1012 *vlan_tags = 1013 MCDI_DWORD(outbuf, 1014 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS); 1015 1016 return 0; 1017 } 1018 1019 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 1020 { 1021 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 1022 1023 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 1024 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 1025 NULL, 0, NULL); 1026 } 1027 1028 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 1029 { 1030 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 1031 1032 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 1033 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 1034 NULL, 0, NULL); 1035 } 1036 1037 int efx_ef10_vport_add_mac(struct efx_nic *efx, 1038 unsigned int port_id, u8 *mac) 1039 { 1040 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 1041 1042 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 1043 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 1044 1045 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 1046 sizeof(inbuf), NULL, 0, NULL); 1047 } 1048 1049 int efx_ef10_vport_del_mac(struct efx_nic *efx, 1050 unsigned int port_id, u8 *mac) 1051 { 1052 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 1053 1054 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 1055 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 1056 1057 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 1058 sizeof(inbuf), NULL, 0, NULL); 1059 } 1060 1061 #ifdef CONFIG_SFC_SRIOV 1062 static int efx_ef10_probe_vf(struct efx_nic *efx) 1063 { 1064 int rc; 1065 struct pci_dev *pci_dev_pf; 1066 1067 /* If the parent PF has no VF data structure, it doesn't know about this 1068 * VF so fail probe. The VF needs to be re-created. This can happen 1069 * if the PF driver is unloaded while the VF is assigned to a guest. 1070 */ 1071 pci_dev_pf = efx->pci_dev->physfn; 1072 if (pci_dev_pf) { 1073 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 1074 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 1075 1076 if (!nic_data_pf->vf) { 1077 netif_info(efx, drv, efx->net_dev, 1078 "The VF cannot link to its parent PF; " 1079 "please destroy and re-create the VF\n"); 1080 return -EBUSY; 1081 } 1082 } 1083 1084 rc = efx_ef10_probe(efx); 1085 if (rc) 1086 return rc; 1087 1088 rc = efx_ef10_get_vf_index(efx); 1089 if (rc) 1090 goto fail; 1091 1092 if (efx->pci_dev->is_virtfn) { 1093 if (efx->pci_dev->physfn) { 1094 struct efx_nic *efx_pf = 1095 pci_get_drvdata(efx->pci_dev->physfn); 1096 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 1097 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1098 1099 nic_data_p->vf[nic_data->vf_index].efx = efx; 1100 nic_data_p->vf[nic_data->vf_index].pci_dev = 1101 efx->pci_dev; 1102 } else 1103 netif_info(efx, drv, efx->net_dev, 1104 "Could not get the PF id from VF\n"); 1105 } 1106 1107 return 0; 1108 1109 fail: 1110 efx_ef10_remove(efx); 1111 return rc; 1112 } 1113 #else 1114 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 1115 { 1116 return 0; 1117 } 1118 #endif 1119 1120 static int efx_ef10_alloc_vis(struct efx_nic *efx, 1121 unsigned int min_vis, unsigned int max_vis) 1122 { 1123 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1124 1125 return efx_mcdi_alloc_vis(efx, min_vis, max_vis, &nic_data->vi_base, 1126 &nic_data->n_allocated_vis); 1127 } 1128 1129 /* Note that the failure path of this function does not free 1130 * resources, as this will be done by efx_ef10_remove(). 1131 */ 1132 static int efx_ef10_dimension_resources(struct efx_nic *efx) 1133 { 1134 unsigned int min_vis = max_t(unsigned int, efx->tx_queues_per_channel, 1135 efx_separate_tx_channels ? 2 : 1); 1136 unsigned int channel_vis, pio_write_vi_base, max_vis; 1137 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1138 unsigned int uc_mem_map_size, wc_mem_map_size; 1139 void __iomem *membase; 1140 int rc; 1141 1142 channel_vis = max(efx->n_channels, 1143 ((efx->n_tx_channels + efx->n_extra_tx_channels) * 1144 efx->tx_queues_per_channel) + 1145 efx->n_xdp_channels * efx->xdp_tx_per_channel); 1146 if (efx->max_vis && efx->max_vis < channel_vis) { 1147 netif_dbg(efx, drv, efx->net_dev, 1148 "Reducing channel VIs from %u to %u\n", 1149 channel_vis, efx->max_vis); 1150 channel_vis = efx->max_vis; 1151 } 1152 1153 #ifdef EFX_USE_PIO 1154 /* Try to allocate PIO buffers if wanted and if the full 1155 * number of PIO buffers would be sufficient to allocate one 1156 * copy-buffer per TX channel. Failure is non-fatal, as there 1157 * are only a small number of PIO buffers shared between all 1158 * functions of the controller. 1159 */ 1160 if (efx_piobuf_size != 0 && 1161 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 1162 efx->n_tx_channels) { 1163 unsigned int n_piobufs = 1164 DIV_ROUND_UP(efx->n_tx_channels, 1165 nic_data->piobuf_size / efx_piobuf_size); 1166 1167 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 1168 if (rc == -ENOSPC) 1169 netif_dbg(efx, probe, efx->net_dev, 1170 "out of PIO buffers; cannot allocate more\n"); 1171 else if (rc == -EPERM) 1172 netif_dbg(efx, probe, efx->net_dev, 1173 "not permitted to allocate PIO buffers\n"); 1174 else if (rc) 1175 netif_err(efx, probe, efx->net_dev, 1176 "failed to allocate PIO buffers (%d)\n", rc); 1177 else 1178 netif_dbg(efx, probe, efx->net_dev, 1179 "allocated %u PIO buffers\n", n_piobufs); 1180 } 1181 #else 1182 nic_data->n_piobufs = 0; 1183 #endif 1184 1185 /* PIO buffers should be mapped with write-combining enabled, 1186 * and we want to make single UC and WC mappings rather than 1187 * several of each (in fact that's the only option if host 1188 * page size is >4K). So we may allocate some extra VIs just 1189 * for writing PIO buffers through. 1190 * 1191 * The UC mapping contains (channel_vis - 1) complete VIs and the 1192 * first 4K of the next VI. Then the WC mapping begins with 1193 * the remainder of this last VI. 1194 */ 1195 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride + 1196 ER_DZ_TX_PIOBUF); 1197 if (nic_data->n_piobufs) { 1198 /* pio_write_vi_base rounds down to give the number of complete 1199 * VIs inside the UC mapping. 1200 */ 1201 pio_write_vi_base = uc_mem_map_size / efx->vi_stride; 1202 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 1203 nic_data->n_piobufs) * 1204 efx->vi_stride) - 1205 uc_mem_map_size); 1206 max_vis = pio_write_vi_base + nic_data->n_piobufs; 1207 } else { 1208 pio_write_vi_base = 0; 1209 wc_mem_map_size = 0; 1210 max_vis = channel_vis; 1211 } 1212 1213 /* In case the last attached driver failed to free VIs, do it now */ 1214 rc = efx_mcdi_free_vis(efx); 1215 if (rc != 0) 1216 return rc; 1217 1218 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 1219 if (rc != 0) 1220 return rc; 1221 1222 if (nic_data->n_allocated_vis < channel_vis) { 1223 netif_info(efx, drv, efx->net_dev, 1224 "Could not allocate enough VIs to satisfy RSS" 1225 " requirements. Performance may not be optimal.\n"); 1226 /* We didn't get the VIs to populate our channels. 1227 * We could keep what we got but then we'd have more 1228 * interrupts than we need. 1229 * Instead calculate new max_channels and restart 1230 */ 1231 efx->max_channels = nic_data->n_allocated_vis; 1232 efx->max_tx_channels = 1233 nic_data->n_allocated_vis / efx->tx_queues_per_channel; 1234 1235 efx_mcdi_free_vis(efx); 1236 return -EAGAIN; 1237 } 1238 1239 /* If we didn't get enough VIs to map all the PIO buffers, free the 1240 * PIO buffers 1241 */ 1242 if (nic_data->n_piobufs && 1243 nic_data->n_allocated_vis < 1244 pio_write_vi_base + nic_data->n_piobufs) { 1245 netif_dbg(efx, probe, efx->net_dev, 1246 "%u VIs are not sufficient to map %u PIO buffers\n", 1247 nic_data->n_allocated_vis, nic_data->n_piobufs); 1248 efx_ef10_free_piobufs(efx); 1249 } 1250 1251 /* Shrink the original UC mapping of the memory BAR */ 1252 membase = ioremap(efx->membase_phys, uc_mem_map_size); 1253 if (!membase) { 1254 netif_err(efx, probe, efx->net_dev, 1255 "could not shrink memory BAR to %x\n", 1256 uc_mem_map_size); 1257 return -ENOMEM; 1258 } 1259 iounmap(efx->membase); 1260 efx->membase = membase; 1261 1262 /* Set up the WC mapping if needed */ 1263 if (wc_mem_map_size) { 1264 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 1265 uc_mem_map_size, 1266 wc_mem_map_size); 1267 if (!nic_data->wc_membase) { 1268 netif_err(efx, probe, efx->net_dev, 1269 "could not allocate WC mapping of size %x\n", 1270 wc_mem_map_size); 1271 return -ENOMEM; 1272 } 1273 nic_data->pio_write_vi_base = pio_write_vi_base; 1274 nic_data->pio_write_base = 1275 nic_data->wc_membase + 1276 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF - 1277 uc_mem_map_size); 1278 1279 rc = efx_ef10_link_piobufs(efx); 1280 if (rc) 1281 efx_ef10_free_piobufs(efx); 1282 } 1283 1284 netif_dbg(efx, probe, efx->net_dev, 1285 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 1286 &efx->membase_phys, efx->membase, uc_mem_map_size, 1287 nic_data->wc_membase, wc_mem_map_size); 1288 1289 return 0; 1290 } 1291 1292 static void efx_ef10_fini_nic(struct efx_nic *efx) 1293 { 1294 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1295 1296 kfree(nic_data->mc_stats); 1297 nic_data->mc_stats = NULL; 1298 } 1299 1300 static int efx_ef10_init_nic(struct efx_nic *efx) 1301 { 1302 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1303 int rc; 1304 1305 if (nic_data->must_check_datapath_caps) { 1306 rc = efx_ef10_init_datapath_caps(efx); 1307 if (rc) 1308 return rc; 1309 nic_data->must_check_datapath_caps = false; 1310 } 1311 1312 if (efx->must_realloc_vis) { 1313 /* We cannot let the number of VIs change now */ 1314 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 1315 nic_data->n_allocated_vis); 1316 if (rc) 1317 return rc; 1318 efx->must_realloc_vis = false; 1319 } 1320 1321 nic_data->mc_stats = kmalloc(efx->num_mac_stats * sizeof(__le64), 1322 GFP_KERNEL); 1323 if (!nic_data->mc_stats) 1324 return -ENOMEM; 1325 1326 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 1327 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 1328 if (rc == 0) { 1329 rc = efx_ef10_link_piobufs(efx); 1330 if (rc) 1331 efx_ef10_free_piobufs(efx); 1332 } 1333 1334 /* Log an error on failure, but this is non-fatal. 1335 * Permission errors are less important - we've presumably 1336 * had the PIO buffer licence removed. 1337 */ 1338 if (rc == -EPERM) 1339 netif_dbg(efx, drv, efx->net_dev, 1340 "not permitted to restore PIO buffers\n"); 1341 else if (rc) 1342 netif_err(efx, drv, efx->net_dev, 1343 "failed to restore PIO buffers (%d)\n", rc); 1344 nic_data->must_restore_piobufs = false; 1345 } 1346 1347 /* don't fail init if RSS setup doesn't work */ 1348 rc = efx->type->rx_push_rss_config(efx, false, 1349 efx->rss_context.rx_indir_table, NULL); 1350 1351 return 0; 1352 } 1353 1354 static void efx_ef10_table_reset_mc_allocations(struct efx_nic *efx) 1355 { 1356 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1357 #ifdef CONFIG_SFC_SRIOV 1358 unsigned int i; 1359 #endif 1360 1361 /* All our allocations have been reset */ 1362 efx->must_realloc_vis = true; 1363 efx_mcdi_filter_table_reset_mc_allocations(efx); 1364 nic_data->must_restore_piobufs = true; 1365 efx_ef10_forget_old_piobufs(efx); 1366 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID; 1367 1368 /* Driver-created vswitches and vports must be re-created */ 1369 nic_data->must_probe_vswitching = true; 1370 efx->vport_id = EVB_PORT_ID_ASSIGNED; 1371 #ifdef CONFIG_SFC_SRIOV 1372 if (nic_data->vf) 1373 for (i = 0; i < efx->vf_count; i++) 1374 nic_data->vf[i].vport_id = 0; 1375 #endif 1376 } 1377 1378 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1379 { 1380 if (reason == RESET_TYPE_MC_FAILURE) 1381 return RESET_TYPE_DATAPATH; 1382 1383 return efx_mcdi_map_reset_reason(reason); 1384 } 1385 1386 static int efx_ef10_map_reset_flags(u32 *flags) 1387 { 1388 enum { 1389 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1390 ETH_RESET_SHARED_SHIFT), 1391 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1392 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1393 ETH_RESET_PHY | ETH_RESET_MGMT) << 1394 ETH_RESET_SHARED_SHIFT) 1395 }; 1396 1397 /* We assume for now that our PCI function is permitted to 1398 * reset everything. 1399 */ 1400 1401 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1402 *flags &= ~EF10_RESET_MC; 1403 return RESET_TYPE_WORLD; 1404 } 1405 1406 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1407 *flags &= ~EF10_RESET_PORT; 1408 return RESET_TYPE_ALL; 1409 } 1410 1411 /* no invisible reset implemented */ 1412 1413 return -EINVAL; 1414 } 1415 1416 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1417 { 1418 int rc = efx_mcdi_reset(efx, reset_type); 1419 1420 /* Unprivileged functions return -EPERM, but need to return success 1421 * here so that the datapath is brought back up. 1422 */ 1423 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1424 rc = 0; 1425 1426 /* If it was a port reset, trigger reallocation of MC resources. 1427 * Note that on an MC reset nothing needs to be done now because we'll 1428 * detect the MC reset later and handle it then. 1429 * For an FLR, we never get an MC reset event, but the MC has reset all 1430 * resources assigned to us, so we have to trigger reallocation now. 1431 */ 1432 if ((reset_type == RESET_TYPE_ALL || 1433 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1434 efx_ef10_table_reset_mc_allocations(efx); 1435 return rc; 1436 } 1437 1438 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1439 [EF10_STAT_ ## ext_name] = \ 1440 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1441 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1442 [EF10_STAT_ ## int_name] = \ 1443 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1444 #define EF10_OTHER_STAT(ext_name) \ 1445 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1446 1447 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1448 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1449 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1450 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1451 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1452 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1453 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1454 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1455 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1456 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1457 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1458 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1459 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1460 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1461 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1462 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1463 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1464 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1465 EF10_OTHER_STAT(port_rx_good_bytes), 1466 EF10_OTHER_STAT(port_rx_bad_bytes), 1467 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1468 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1469 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1470 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1471 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1472 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1473 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1474 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1475 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1476 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1477 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1478 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1479 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1480 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1481 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1482 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1483 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1484 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1485 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1486 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1487 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1488 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1489 EFX_GENERIC_SW_STAT(rx_nodesc_trunc), 1490 EFX_GENERIC_SW_STAT(rx_noskb_drops), 1491 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1492 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1493 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1494 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1495 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1496 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1497 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1498 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1499 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1500 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1501 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1502 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1503 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1504 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1505 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1506 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1507 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1508 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1509 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1510 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1511 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1512 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1513 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1514 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1515 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1516 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1517 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1518 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1519 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1520 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1521 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS), 1522 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS), 1523 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0), 1524 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1), 1525 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2), 1526 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3), 1527 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK), 1528 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS), 1529 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL), 1530 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL), 1531 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL), 1532 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL), 1533 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL), 1534 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL), 1535 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL), 1536 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK), 1537 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK), 1538 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK), 1539 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS), 1540 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK), 1541 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON), 1542 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE), 1543 }; 1544 1545 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1546 (1ULL << EF10_STAT_port_tx_packets) | \ 1547 (1ULL << EF10_STAT_port_tx_pause) | \ 1548 (1ULL << EF10_STAT_port_tx_unicast) | \ 1549 (1ULL << EF10_STAT_port_tx_multicast) | \ 1550 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1551 (1ULL << EF10_STAT_port_rx_bytes) | \ 1552 (1ULL << \ 1553 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1554 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1555 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1556 (1ULL << EF10_STAT_port_rx_packets) | \ 1557 (1ULL << EF10_STAT_port_rx_good) | \ 1558 (1ULL << EF10_STAT_port_rx_bad) | \ 1559 (1ULL << EF10_STAT_port_rx_pause) | \ 1560 (1ULL << EF10_STAT_port_rx_control) | \ 1561 (1ULL << EF10_STAT_port_rx_unicast) | \ 1562 (1ULL << EF10_STAT_port_rx_multicast) | \ 1563 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1564 (1ULL << EF10_STAT_port_rx_lt64) | \ 1565 (1ULL << EF10_STAT_port_rx_64) | \ 1566 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1567 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1568 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1569 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1570 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1571 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1572 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1573 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1574 (1ULL << EF10_STAT_port_rx_overflow) | \ 1575 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1576 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1577 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1578 1579 /* On 7000 series NICs, these statistics are only provided by the 10G MAC. 1580 * For a 10G/40G switchable port we do not expose these because they might 1581 * not include all the packets they should. 1582 * On 8000 series NICs these statistics are always provided. 1583 */ 1584 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1585 (1ULL << EF10_STAT_port_tx_lt64) | \ 1586 (1ULL << EF10_STAT_port_tx_64) | \ 1587 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1588 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1589 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1590 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1591 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1592 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1593 1594 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1595 * switchable port we do expose these because the errors will otherwise 1596 * be silent. 1597 */ 1598 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1599 (1ULL << EF10_STAT_port_rx_length_error)) 1600 1601 /* These statistics are only provided if the firmware supports the 1602 * capability PM_AND_RXDP_COUNTERS. 1603 */ 1604 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1605 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1606 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1607 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1608 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1609 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1610 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1611 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1612 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1613 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1614 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1615 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1616 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1617 1618 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2, 1619 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in 1620 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1621 * These bits are in the second u64 of the raw mask. 1622 */ 1623 #define EF10_FEC_STAT_MASK ( \ 1624 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \ 1625 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \ 1626 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \ 1627 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \ 1628 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \ 1629 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64))) 1630 1631 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3, 1632 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in 1633 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1634 * These bits are in the second u64 of the raw mask. 1635 */ 1636 #define EF10_CTPIO_STAT_MASK ( \ 1637 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \ 1638 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \ 1639 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \ 1640 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \ 1641 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \ 1642 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \ 1643 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \ 1644 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \ 1645 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \ 1646 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \ 1647 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \ 1648 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \ 1649 (1ULL << (EF10_STAT_ctpio_success - 64)) | \ 1650 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \ 1651 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \ 1652 (1ULL << (EF10_STAT_ctpio_erase - 64))) 1653 1654 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1655 { 1656 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1657 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1658 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1659 1660 if (!(efx->mcdi->fn_flags & 1661 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1662 return 0; 1663 1664 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) { 1665 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1666 /* 8000 series have everything even at 40G */ 1667 if (nic_data->datapath_caps2 & 1668 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN)) 1669 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1670 } else { 1671 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1672 } 1673 1674 if (nic_data->datapath_caps & 1675 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1676 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1677 1678 return raw_mask; 1679 } 1680 1681 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1682 { 1683 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1684 u64 raw_mask[2]; 1685 1686 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1687 1688 /* Only show vadaptor stats when EVB capability is present */ 1689 if (nic_data->datapath_caps & 1690 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1691 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1692 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1; 1693 } else { 1694 raw_mask[1] = 0; 1695 } 1696 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */ 1697 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2) 1698 raw_mask[1] |= EF10_FEC_STAT_MASK; 1699 1700 /* CTPIO stats appear in V3. Only show them on devices that actually 1701 * support CTPIO. Although this driver doesn't use CTPIO others might, 1702 * and we may be reporting the stats for the underlying port. 1703 */ 1704 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 && 1705 (nic_data->datapath_caps2 & 1706 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN))) 1707 raw_mask[1] |= EF10_CTPIO_STAT_MASK; 1708 1709 #if BITS_PER_LONG == 64 1710 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2); 1711 mask[0] = raw_mask[0]; 1712 mask[1] = raw_mask[1]; 1713 #else 1714 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3); 1715 mask[0] = raw_mask[0] & 0xffffffff; 1716 mask[1] = raw_mask[0] >> 32; 1717 mask[2] = raw_mask[1] & 0xffffffff; 1718 #endif 1719 } 1720 1721 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1722 { 1723 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1724 1725 efx_ef10_get_stat_mask(efx, mask); 1726 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1727 mask, names); 1728 } 1729 1730 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1731 struct rtnl_link_stats64 *core_stats) 1732 { 1733 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1734 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1735 u64 *stats = nic_data->stats; 1736 size_t stats_count = 0, index; 1737 1738 efx_ef10_get_stat_mask(efx, mask); 1739 1740 if (full_stats) { 1741 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1742 if (efx_ef10_stat_desc[index].name) { 1743 *full_stats++ = stats[index]; 1744 ++stats_count; 1745 } 1746 } 1747 } 1748 1749 if (!core_stats) 1750 return stats_count; 1751 1752 if (nic_data->datapath_caps & 1753 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1754 /* Use vadaptor stats. */ 1755 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1756 stats[EF10_STAT_rx_multicast] + 1757 stats[EF10_STAT_rx_broadcast]; 1758 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1759 stats[EF10_STAT_tx_multicast] + 1760 stats[EF10_STAT_tx_broadcast]; 1761 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1762 stats[EF10_STAT_rx_multicast_bytes] + 1763 stats[EF10_STAT_rx_broadcast_bytes]; 1764 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1765 stats[EF10_STAT_tx_multicast_bytes] + 1766 stats[EF10_STAT_tx_broadcast_bytes]; 1767 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1768 stats[GENERIC_STAT_rx_noskb_drops]; 1769 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1770 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1771 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1772 core_stats->rx_errors = core_stats->rx_crc_errors; 1773 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1774 } else { 1775 /* Use port stats. */ 1776 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1777 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1778 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1779 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1780 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1781 stats[GENERIC_STAT_rx_nodesc_trunc] + 1782 stats[GENERIC_STAT_rx_noskb_drops]; 1783 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1784 core_stats->rx_length_errors = 1785 stats[EF10_STAT_port_rx_gtjumbo] + 1786 stats[EF10_STAT_port_rx_length_error]; 1787 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1788 core_stats->rx_frame_errors = 1789 stats[EF10_STAT_port_rx_align_error]; 1790 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1791 core_stats->rx_errors = (core_stats->rx_length_errors + 1792 core_stats->rx_crc_errors + 1793 core_stats->rx_frame_errors); 1794 } 1795 1796 return stats_count; 1797 } 1798 1799 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1800 struct rtnl_link_stats64 *core_stats) 1801 { 1802 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1803 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1804 u64 *stats = nic_data->stats; 1805 1806 efx_ef10_get_stat_mask(efx, mask); 1807 1808 efx_nic_copy_stats(efx, nic_data->mc_stats); 1809 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1810 mask, stats, nic_data->mc_stats, false); 1811 1812 /* Update derived statistics */ 1813 efx_nic_fix_nodesc_drop_stat(efx, 1814 &stats[EF10_STAT_port_rx_nodesc_drops]); 1815 /* MC Firmware reads RX_BYTES and RX_GOOD_BYTES from the MAC. 1816 * It then calculates RX_BAD_BYTES and DMAs it to us with RX_BYTES. 1817 * We report these as port_rx_ stats. We are not given RX_GOOD_BYTES. 1818 * Here we calculate port_rx_good_bytes. 1819 */ 1820 stats[EF10_STAT_port_rx_good_bytes] = 1821 stats[EF10_STAT_port_rx_bytes] - 1822 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1823 1824 /* The asynchronous reads used to calculate RX_BAD_BYTES in 1825 * MC Firmware are done such that we should not see an increase in 1826 * RX_BAD_BYTES when a good packet has arrived. Unfortunately this 1827 * does mean that the stat can decrease at times. Here we do not 1828 * update the stat unless it has increased or has gone to zero 1829 * (In the case of the NIC rebooting). 1830 * Please see Bug 33781 for a discussion of why things work this way. 1831 */ 1832 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1833 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1834 efx_update_sw_stats(efx, stats); 1835 1836 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1837 } 1838 1839 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1840 __must_hold(&efx->stats_lock) 1841 { 1842 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1843 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1844 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1845 __le64 generation_start, generation_end; 1846 u64 *stats = nic_data->stats; 1847 u32 dma_len = efx->num_mac_stats * sizeof(u64); 1848 struct efx_buffer stats_buf; 1849 __le64 *dma_stats; 1850 int rc; 1851 1852 spin_unlock_bh(&efx->stats_lock); 1853 1854 if (in_interrupt()) { 1855 /* If in atomic context, cannot update stats. Just update the 1856 * software stats and return so the caller can continue. 1857 */ 1858 spin_lock_bh(&efx->stats_lock); 1859 efx_update_sw_stats(efx, stats); 1860 return 0; 1861 } 1862 1863 efx_ef10_get_stat_mask(efx, mask); 1864 1865 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC); 1866 if (rc) { 1867 spin_lock_bh(&efx->stats_lock); 1868 return rc; 1869 } 1870 1871 dma_stats = stats_buf.addr; 1872 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID; 1873 1874 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1875 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1876 MAC_STATS_IN_DMA, 1); 1877 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1878 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1879 1880 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1881 NULL, 0, NULL); 1882 spin_lock_bh(&efx->stats_lock); 1883 if (rc) { 1884 /* Expect ENOENT if DMA queues have not been set up */ 1885 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1886 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1887 sizeof(inbuf), NULL, 0, rc); 1888 goto out; 1889 } 1890 1891 generation_end = dma_stats[efx->num_mac_stats - 1]; 1892 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1893 WARN_ON_ONCE(1); 1894 goto out; 1895 } 1896 rmb(); 1897 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1898 stats, stats_buf.addr, false); 1899 rmb(); 1900 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1901 if (generation_end != generation_start) { 1902 rc = -EAGAIN; 1903 goto out; 1904 } 1905 1906 efx_update_sw_stats(efx, stats); 1907 out: 1908 efx_nic_free_buffer(efx, &stats_buf); 1909 return rc; 1910 } 1911 1912 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1913 struct rtnl_link_stats64 *core_stats) 1914 { 1915 if (efx_ef10_try_update_nic_stats_vf(efx)) 1916 return 0; 1917 1918 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1919 } 1920 1921 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1922 { 1923 struct efx_nic *efx = channel->efx; 1924 unsigned int mode, usecs; 1925 efx_dword_t timer_cmd; 1926 1927 if (channel->irq_moderation_us) { 1928 mode = 3; 1929 usecs = channel->irq_moderation_us; 1930 } else { 1931 mode = 0; 1932 usecs = 0; 1933 } 1934 1935 if (EFX_EF10_WORKAROUND_61265(efx)) { 1936 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN); 1937 unsigned int ns = usecs * 1000; 1938 1939 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE, 1940 channel->channel); 1941 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns); 1942 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns); 1943 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode); 1944 1945 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR, 1946 inbuf, sizeof(inbuf), 0, NULL, 0); 1947 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 1948 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1949 1950 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1951 EFE_DD_EVQ_IND_TIMER_FLAGS, 1952 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1953 ERF_DD_EVQ_IND_TIMER_VAL, ticks); 1954 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1955 channel->channel); 1956 } else { 1957 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1958 1959 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1960 ERF_DZ_TC_TIMER_VAL, ticks, 1961 ERF_FZ_TC_TMR_REL_VAL, ticks); 1962 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1963 channel->channel); 1964 } 1965 } 1966 1967 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 1968 struct ethtool_wolinfo *wol) {} 1969 1970 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 1971 { 1972 return -EOPNOTSUPP; 1973 } 1974 1975 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1976 { 1977 wol->supported = 0; 1978 wol->wolopts = 0; 1979 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1980 } 1981 1982 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 1983 { 1984 if (type != 0) 1985 return -EINVAL; 1986 return 0; 1987 } 1988 1989 static void efx_ef10_mcdi_request(struct efx_nic *efx, 1990 const efx_dword_t *hdr, size_t hdr_len, 1991 const efx_dword_t *sdu, size_t sdu_len) 1992 { 1993 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1994 u8 *pdu = nic_data->mcdi_buf.addr; 1995 1996 memcpy(pdu, hdr, hdr_len); 1997 memcpy(pdu + hdr_len, sdu, sdu_len); 1998 wmb(); 1999 2000 /* The hardware provides 'low' and 'high' (doorbell) registers 2001 * for passing the 64-bit address of an MCDI request to 2002 * firmware. However the dwords are swapped by firmware. The 2003 * least significant bits of the doorbell are then 0 for all 2004 * MCDI requests due to alignment. 2005 */ 2006 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 2007 ER_DZ_MC_DB_LWRD); 2008 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 2009 ER_DZ_MC_DB_HWRD); 2010 } 2011 2012 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 2013 { 2014 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2015 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 2016 2017 rmb(); 2018 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 2019 } 2020 2021 static void 2022 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 2023 size_t offset, size_t outlen) 2024 { 2025 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2026 const u8 *pdu = nic_data->mcdi_buf.addr; 2027 2028 memcpy(outbuf, pdu + offset, outlen); 2029 } 2030 2031 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 2032 { 2033 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2034 2035 /* All our allocations have been reset */ 2036 efx_ef10_table_reset_mc_allocations(efx); 2037 2038 /* The datapath firmware might have been changed */ 2039 nic_data->must_check_datapath_caps = true; 2040 2041 /* MAC statistics have been cleared on the NIC; clear the local 2042 * statistic that we update with efx_update_diff_stat(). 2043 */ 2044 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 2045 } 2046 2047 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 2048 { 2049 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2050 int rc; 2051 2052 rc = efx_ef10_get_warm_boot_count(efx); 2053 if (rc < 0) { 2054 /* The firmware is presumably in the process of 2055 * rebooting. However, we are supposed to report each 2056 * reboot just once, so we must only do that once we 2057 * can read and store the updated warm boot count. 2058 */ 2059 return 0; 2060 } 2061 2062 if (rc == nic_data->warm_boot_count) 2063 return 0; 2064 2065 nic_data->warm_boot_count = rc; 2066 efx_ef10_mcdi_reboot_detected(efx); 2067 2068 return -EIO; 2069 } 2070 2071 /* Handle an MSI interrupt 2072 * 2073 * Handle an MSI hardware interrupt. This routine schedules event 2074 * queue processing. No interrupt acknowledgement cycle is necessary. 2075 * Also, we never need to check that the interrupt is for us, since 2076 * MSI interrupts cannot be shared. 2077 */ 2078 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 2079 { 2080 struct efx_msi_context *context = dev_id; 2081 struct efx_nic *efx = context->efx; 2082 2083 netif_vdbg(efx, intr, efx->net_dev, 2084 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 2085 2086 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 2087 /* Note test interrupts */ 2088 if (context->index == efx->irq_level) 2089 efx->last_irq_cpu = raw_smp_processor_id(); 2090 2091 /* Schedule processing of the channel */ 2092 efx_schedule_channel_irq(efx->channel[context->index]); 2093 } 2094 2095 return IRQ_HANDLED; 2096 } 2097 2098 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 2099 { 2100 struct efx_nic *efx = dev_id; 2101 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled); 2102 struct efx_channel *channel; 2103 efx_dword_t reg; 2104 u32 queues; 2105 2106 /* Read the ISR which also ACKs the interrupts */ 2107 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 2108 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 2109 2110 if (queues == 0) 2111 return IRQ_NONE; 2112 2113 if (likely(soft_enabled)) { 2114 /* Note test interrupts */ 2115 if (queues & (1U << efx->irq_level)) 2116 efx->last_irq_cpu = raw_smp_processor_id(); 2117 2118 efx_for_each_channel(channel, efx) { 2119 if (queues & 1) 2120 efx_schedule_channel_irq(channel); 2121 queues >>= 1; 2122 } 2123 } 2124 2125 netif_vdbg(efx, intr, efx->net_dev, 2126 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 2127 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 2128 2129 return IRQ_HANDLED; 2130 } 2131 2132 static int efx_ef10_irq_test_generate(struct efx_nic *efx) 2133 { 2134 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 2135 2136 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true, 2137 NULL) == 0) 2138 return -ENOTSUPP; 2139 2140 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 2141 2142 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 2143 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 2144 inbuf, sizeof(inbuf), NULL, 0, NULL); 2145 } 2146 2147 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 2148 { 2149 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 2150 (tx_queue->ptr_mask + 1) * 2151 sizeof(efx_qword_t), 2152 GFP_KERNEL); 2153 } 2154 2155 /* This writes to the TX_DESC_WPTR and also pushes data */ 2156 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 2157 const efx_qword_t *txd) 2158 { 2159 unsigned int write_ptr; 2160 efx_oword_t reg; 2161 2162 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2163 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 2164 reg.qword[0] = *txd; 2165 efx_writeo_page(tx_queue->efx, ®, 2166 ER_DZ_TX_DESC_UPD, tx_queue->queue); 2167 } 2168 2169 /* Add Firmware-Assisted TSO v2 option descriptors to a queue. 2170 */ 2171 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, 2172 struct sk_buff *skb, 2173 bool *data_mapped) 2174 { 2175 struct efx_tx_buffer *buffer; 2176 struct tcphdr *tcp; 2177 struct iphdr *ip; 2178 2179 u16 ipv4_id; 2180 u32 seqnum; 2181 u32 mss; 2182 2183 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2); 2184 2185 mss = skb_shinfo(skb)->gso_size; 2186 2187 if (unlikely(mss < 4)) { 2188 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss); 2189 return -EINVAL; 2190 } 2191 2192 ip = ip_hdr(skb); 2193 if (ip->version == 4) { 2194 /* Modify IPv4 header if needed. */ 2195 ip->tot_len = 0; 2196 ip->check = 0; 2197 ipv4_id = ntohs(ip->id); 2198 } else { 2199 /* Modify IPv6 header if needed. */ 2200 struct ipv6hdr *ipv6 = ipv6_hdr(skb); 2201 2202 ipv6->payload_len = 0; 2203 ipv4_id = 0; 2204 } 2205 2206 tcp = tcp_hdr(skb); 2207 seqnum = ntohl(tcp->seq); 2208 2209 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2210 2211 buffer->flags = EFX_TX_BUF_OPTION; 2212 buffer->len = 0; 2213 buffer->unmap_len = 0; 2214 EFX_POPULATE_QWORD_5(buffer->option, 2215 ESF_DZ_TX_DESC_IS_OPT, 1, 2216 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2217 ESF_DZ_TX_TSO_OPTION_TYPE, 2218 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A, 2219 ESF_DZ_TX_TSO_IP_ID, ipv4_id, 2220 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum 2221 ); 2222 ++tx_queue->insert_count; 2223 2224 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2225 2226 buffer->flags = EFX_TX_BUF_OPTION; 2227 buffer->len = 0; 2228 buffer->unmap_len = 0; 2229 EFX_POPULATE_QWORD_4(buffer->option, 2230 ESF_DZ_TX_DESC_IS_OPT, 1, 2231 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2232 ESF_DZ_TX_TSO_OPTION_TYPE, 2233 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B, 2234 ESF_DZ_TX_TSO_TCP_MSS, mss 2235 ); 2236 ++tx_queue->insert_count; 2237 2238 return 0; 2239 } 2240 2241 static u32 efx_ef10_tso_versions(struct efx_nic *efx) 2242 { 2243 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2244 u32 tso_versions = 0; 2245 2246 if (nic_data->datapath_caps & 2247 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) 2248 tso_versions |= BIT(1); 2249 if (nic_data->datapath_caps2 & 2250 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) 2251 tso_versions |= BIT(2); 2252 return tso_versions; 2253 } 2254 2255 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 2256 { 2257 bool csum_offload = tx_queue->label & EFX_TXQ_TYPE_OFFLOAD; 2258 struct efx_channel *channel = tx_queue->channel; 2259 struct efx_nic *efx = tx_queue->efx; 2260 struct efx_ef10_nic_data *nic_data; 2261 bool tso_v2 = false; 2262 efx_qword_t *txd; 2263 int rc; 2264 2265 nic_data = efx->nic_data; 2266 2267 /* Only attempt to enable TX timestamping if we have the license for it, 2268 * otherwise TXQ init will fail 2269 */ 2270 if (!(nic_data->licensed_features & 2271 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) { 2272 tx_queue->timestamping = false; 2273 /* Disable sync events on this channel. */ 2274 if (efx->type->ptp_set_ts_sync_events) 2275 efx->type->ptp_set_ts_sync_events(efx, false, false); 2276 } 2277 2278 /* TSOv2 is a limited resource that can only be configured on a limited 2279 * number of queues. TSO without checksum offload is not really a thing, 2280 * so we only enable it for those queues. 2281 * TSOv2 cannot be used with Hardware timestamping, and is never needed 2282 * for XDP tx. 2283 */ 2284 if (csum_offload && (nic_data->datapath_caps2 & 2285 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) && 2286 !tx_queue->timestamping && !tx_queue->xdp_tx) { 2287 tso_v2 = true; 2288 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n", 2289 channel->channel); 2290 } 2291 2292 rc = efx_mcdi_tx_init(tx_queue, tso_v2); 2293 if (rc) 2294 goto fail; 2295 2296 /* A previous user of this TX queue might have set us up the 2297 * bomb by writing a descriptor to the TX push collector but 2298 * not the doorbell. (Each collector belongs to a port, not a 2299 * queue or function, so cannot easily be reset.) We must 2300 * attempt to push a no-op descriptor in its place. 2301 */ 2302 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 2303 tx_queue->insert_count = 1; 2304 txd = efx_tx_desc(tx_queue, 0); 2305 EFX_POPULATE_QWORD_5(*txd, 2306 ESF_DZ_TX_DESC_IS_OPT, true, 2307 ESF_DZ_TX_OPTION_TYPE, 2308 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 2309 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 2310 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload, 2311 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping); 2312 tx_queue->write_count = 1; 2313 2314 if (tso_v2) { 2315 tx_queue->handle_tso = efx_ef10_tx_tso_desc; 2316 tx_queue->tso_version = 2; 2317 } else if (nic_data->datapath_caps & 2318 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) { 2319 tx_queue->tso_version = 1; 2320 } 2321 2322 wmb(); 2323 efx_ef10_push_tx_desc(tx_queue, txd); 2324 2325 return; 2326 2327 fail: 2328 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 2329 tx_queue->queue); 2330 } 2331 2332 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 2333 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 2334 { 2335 unsigned int write_ptr; 2336 efx_dword_t reg; 2337 2338 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2339 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 2340 efx_writed_page(tx_queue->efx, ®, 2341 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 2342 } 2343 2344 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff 2345 2346 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue, 2347 dma_addr_t dma_addr, unsigned int len) 2348 { 2349 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) { 2350 /* If we need to break across multiple descriptors we should 2351 * stop at a page boundary. This assumes the length limit is 2352 * greater than the page size. 2353 */ 2354 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN; 2355 2356 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE); 2357 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr; 2358 } 2359 2360 return len; 2361 } 2362 2363 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 2364 { 2365 unsigned int old_write_count = tx_queue->write_count; 2366 struct efx_tx_buffer *buffer; 2367 unsigned int write_ptr; 2368 efx_qword_t *txd; 2369 2370 tx_queue->xmit_more_available = false; 2371 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 2372 return; 2373 2374 do { 2375 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2376 buffer = &tx_queue->buffer[write_ptr]; 2377 txd = efx_tx_desc(tx_queue, write_ptr); 2378 ++tx_queue->write_count; 2379 2380 /* Create TX descriptor ring entry */ 2381 if (buffer->flags & EFX_TX_BUF_OPTION) { 2382 *txd = buffer->option; 2383 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1) 2384 /* PIO descriptor */ 2385 tx_queue->packet_write_count = tx_queue->write_count; 2386 } else { 2387 tx_queue->packet_write_count = tx_queue->write_count; 2388 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 2389 EFX_POPULATE_QWORD_3( 2390 *txd, 2391 ESF_DZ_TX_KER_CONT, 2392 buffer->flags & EFX_TX_BUF_CONT, 2393 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 2394 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 2395 } 2396 } while (tx_queue->write_count != tx_queue->insert_count); 2397 2398 wmb(); /* Ensure descriptors are written before they are fetched */ 2399 2400 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 2401 txd = efx_tx_desc(tx_queue, 2402 old_write_count & tx_queue->ptr_mask); 2403 efx_ef10_push_tx_desc(tx_queue, txd); 2404 ++tx_queue->pushes; 2405 } else { 2406 efx_ef10_notify_tx_desc(tx_queue); 2407 } 2408 } 2409 2410 static int efx_ef10_probe_multicast_chaining(struct efx_nic *efx) 2411 { 2412 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2413 unsigned int enabled, implemented; 2414 bool want_workaround_26807; 2415 int rc; 2416 2417 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2418 if (rc == -ENOSYS) { 2419 /* GET_WORKAROUNDS was implemented before this workaround, 2420 * thus it must be unavailable in this firmware. 2421 */ 2422 nic_data->workaround_26807 = false; 2423 return 0; 2424 } 2425 if (rc) 2426 return rc; 2427 want_workaround_26807 = 2428 implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807; 2429 nic_data->workaround_26807 = 2430 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2431 2432 if (want_workaround_26807 && !nic_data->workaround_26807) { 2433 unsigned int flags; 2434 2435 rc = efx_mcdi_set_workaround(efx, 2436 MC_CMD_WORKAROUND_BUG26807, 2437 true, &flags); 2438 if (!rc) { 2439 if (flags & 2440 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2441 netif_info(efx, drv, efx->net_dev, 2442 "other functions on NIC have been reset\n"); 2443 2444 /* With MCFW v4.6.x and earlier, the 2445 * boot count will have incremented, 2446 * so re-read the warm_boot_count 2447 * value now to ensure this function 2448 * doesn't think it has changed next 2449 * time it checks. 2450 */ 2451 rc = efx_ef10_get_warm_boot_count(efx); 2452 if (rc >= 0) { 2453 nic_data->warm_boot_count = rc; 2454 rc = 0; 2455 } 2456 } 2457 nic_data->workaround_26807 = true; 2458 } else if (rc == -EPERM) { 2459 rc = 0; 2460 } 2461 } 2462 return rc; 2463 } 2464 2465 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 2466 { 2467 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2468 int rc = efx_ef10_probe_multicast_chaining(efx); 2469 struct efx_mcdi_filter_vlan *vlan; 2470 2471 if (rc) 2472 return rc; 2473 rc = efx_mcdi_filter_table_probe(efx, nic_data->workaround_26807); 2474 2475 if (rc) 2476 return rc; 2477 2478 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 2479 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 2480 if (rc) 2481 goto fail_add_vlan; 2482 } 2483 return 0; 2484 2485 fail_add_vlan: 2486 efx_mcdi_filter_table_remove(efx); 2487 return rc; 2488 } 2489 2490 /* This creates an entry in the RX descriptor queue */ 2491 static inline void 2492 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2493 { 2494 struct efx_rx_buffer *rx_buf; 2495 efx_qword_t *rxd; 2496 2497 rxd = efx_rx_desc(rx_queue, index); 2498 rx_buf = efx_rx_buffer(rx_queue, index); 2499 EFX_POPULATE_QWORD_2(*rxd, 2500 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2501 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2502 } 2503 2504 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2505 { 2506 struct efx_nic *efx = rx_queue->efx; 2507 unsigned int write_count; 2508 efx_dword_t reg; 2509 2510 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2511 write_count = rx_queue->added_count & ~7; 2512 if (rx_queue->notified_count == write_count) 2513 return; 2514 2515 do 2516 efx_ef10_build_rx_desc( 2517 rx_queue, 2518 rx_queue->notified_count & rx_queue->ptr_mask); 2519 while (++rx_queue->notified_count != write_count); 2520 2521 wmb(); 2522 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2523 write_count & rx_queue->ptr_mask); 2524 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2525 efx_rx_queue_index(rx_queue)); 2526 } 2527 2528 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2529 2530 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2531 { 2532 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2533 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2534 efx_qword_t event; 2535 2536 EFX_POPULATE_QWORD_2(event, 2537 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2538 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2539 2540 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2541 2542 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2543 * already swapped the data to little-endian order. 2544 */ 2545 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2546 sizeof(efx_qword_t)); 2547 2548 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2549 inbuf, sizeof(inbuf), 0, 2550 efx_ef10_rx_defer_refill_complete, 0); 2551 } 2552 2553 static void 2554 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2555 int rc, efx_dword_t *outbuf, 2556 size_t outlen_actual) 2557 { 2558 /* nothing to do */ 2559 } 2560 2561 static int efx_ef10_ev_init(struct efx_channel *channel) 2562 { 2563 struct efx_nic *efx = channel->efx; 2564 struct efx_ef10_nic_data *nic_data; 2565 bool use_v2, cut_thru; 2566 2567 nic_data = efx->nic_data; 2568 use_v2 = nic_data->datapath_caps2 & 2569 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN; 2570 cut_thru = !(nic_data->datapath_caps & 2571 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2572 return efx_mcdi_ev_init(channel, cut_thru, use_v2); 2573 } 2574 2575 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2576 unsigned int rx_queue_label) 2577 { 2578 struct efx_nic *efx = rx_queue->efx; 2579 2580 netif_info(efx, hw, efx->net_dev, 2581 "rx event arrived on queue %d labeled as queue %u\n", 2582 efx_rx_queue_index(rx_queue), rx_queue_label); 2583 2584 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2585 } 2586 2587 static void 2588 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2589 unsigned int actual, unsigned int expected) 2590 { 2591 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2592 struct efx_nic *efx = rx_queue->efx; 2593 2594 netif_info(efx, hw, efx->net_dev, 2595 "dropped %d events (index=%d expected=%d)\n", 2596 dropped, actual, expected); 2597 2598 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2599 } 2600 2601 /* partially received RX was aborted. clean up. */ 2602 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2603 { 2604 unsigned int rx_desc_ptr; 2605 2606 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2607 "scattered RX aborted (dropping %u buffers)\n", 2608 rx_queue->scatter_n); 2609 2610 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2611 2612 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2613 0, EFX_RX_PKT_DISCARD); 2614 2615 rx_queue->removed_count += rx_queue->scatter_n; 2616 rx_queue->scatter_n = 0; 2617 rx_queue->scatter_len = 0; 2618 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2619 } 2620 2621 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel, 2622 unsigned int n_packets, 2623 unsigned int rx_encap_hdr, 2624 unsigned int rx_l3_class, 2625 unsigned int rx_l4_class, 2626 const efx_qword_t *event) 2627 { 2628 struct efx_nic *efx = channel->efx; 2629 bool handled = false; 2630 2631 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) { 2632 if (!(efx->net_dev->features & NETIF_F_RXALL)) { 2633 if (!efx->loopback_selftest) 2634 channel->n_rx_eth_crc_err += n_packets; 2635 return EFX_RX_PKT_DISCARD; 2636 } 2637 handled = true; 2638 } 2639 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) { 2640 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2641 rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2642 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2643 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2644 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2645 netdev_WARN(efx->net_dev, 2646 "invalid class for RX_IPCKSUM_ERR: event=" 2647 EFX_QWORD_FMT "\n", 2648 EFX_QWORD_VAL(*event)); 2649 if (!efx->loopback_selftest) 2650 *(rx_encap_hdr ? 2651 &channel->n_rx_outer_ip_hdr_chksum_err : 2652 &channel->n_rx_ip_hdr_chksum_err) += n_packets; 2653 return 0; 2654 } 2655 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) { 2656 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2657 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2658 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2659 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2660 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))) 2661 netdev_WARN(efx->net_dev, 2662 "invalid class for RX_TCPUDP_CKSUM_ERR: event=" 2663 EFX_QWORD_FMT "\n", 2664 EFX_QWORD_VAL(*event)); 2665 if (!efx->loopback_selftest) 2666 *(rx_encap_hdr ? 2667 &channel->n_rx_outer_tcp_udp_chksum_err : 2668 &channel->n_rx_tcp_udp_chksum_err) += n_packets; 2669 return 0; 2670 } 2671 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) { 2672 if (unlikely(!rx_encap_hdr)) 2673 netdev_WARN(efx->net_dev, 2674 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event=" 2675 EFX_QWORD_FMT "\n", 2676 EFX_QWORD_VAL(*event)); 2677 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2678 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2679 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2680 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2681 netdev_WARN(efx->net_dev, 2682 "invalid class for RX_IP_INNER_CHKSUM_ERR: event=" 2683 EFX_QWORD_FMT "\n", 2684 EFX_QWORD_VAL(*event)); 2685 if (!efx->loopback_selftest) 2686 channel->n_rx_inner_ip_hdr_chksum_err += n_packets; 2687 return 0; 2688 } 2689 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) { 2690 if (unlikely(!rx_encap_hdr)) 2691 netdev_WARN(efx->net_dev, 2692 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2693 EFX_QWORD_FMT "\n", 2694 EFX_QWORD_VAL(*event)); 2695 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2696 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2697 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2698 rx_l4_class != ESE_FZ_L4_CLASS_UDP))) 2699 netdev_WARN(efx->net_dev, 2700 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2701 EFX_QWORD_FMT "\n", 2702 EFX_QWORD_VAL(*event)); 2703 if (!efx->loopback_selftest) 2704 channel->n_rx_inner_tcp_udp_chksum_err += n_packets; 2705 return 0; 2706 } 2707 2708 WARN_ON(!handled); /* No error bits were recognised */ 2709 return 0; 2710 } 2711 2712 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2713 const efx_qword_t *event) 2714 { 2715 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label; 2716 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr; 2717 unsigned int n_descs, n_packets, i; 2718 struct efx_nic *efx = channel->efx; 2719 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2720 struct efx_rx_queue *rx_queue; 2721 efx_qword_t errors; 2722 bool rx_cont; 2723 u16 flags = 0; 2724 2725 if (unlikely(READ_ONCE(efx->reset_pending))) 2726 return 0; 2727 2728 /* Basic packet information */ 2729 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2730 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2731 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2732 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS); 2733 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS); 2734 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2735 rx_encap_hdr = 2736 nic_data->datapath_caps & 2737 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ? 2738 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) : 2739 ESE_EZ_ENCAP_HDR_NONE; 2740 2741 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2742 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2743 EFX_QWORD_FMT "\n", 2744 EFX_QWORD_VAL(*event)); 2745 2746 rx_queue = efx_channel_get_rx_queue(channel); 2747 2748 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2749 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2750 2751 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2752 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2753 2754 if (n_descs != rx_queue->scatter_n + 1) { 2755 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2756 2757 /* detect rx abort */ 2758 if (unlikely(n_descs == rx_queue->scatter_n)) { 2759 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2760 netdev_WARN(efx->net_dev, 2761 "invalid RX abort: scatter_n=%u event=" 2762 EFX_QWORD_FMT "\n", 2763 rx_queue->scatter_n, 2764 EFX_QWORD_VAL(*event)); 2765 efx_ef10_handle_rx_abort(rx_queue); 2766 return 0; 2767 } 2768 2769 /* Check that RX completion merging is valid, i.e. 2770 * the current firmware supports it and this is a 2771 * non-scattered packet. 2772 */ 2773 if (!(nic_data->datapath_caps & 2774 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2775 rx_queue->scatter_n != 0 || rx_cont) { 2776 efx_ef10_handle_rx_bad_lbits( 2777 rx_queue, next_ptr_lbits, 2778 (rx_queue->removed_count + 2779 rx_queue->scatter_n + 1) & 2780 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2781 return 0; 2782 } 2783 2784 /* Merged completion for multiple non-scattered packets */ 2785 rx_queue->scatter_n = 1; 2786 rx_queue->scatter_len = 0; 2787 n_packets = n_descs; 2788 ++channel->n_rx_merge_events; 2789 channel->n_rx_merge_packets += n_packets; 2790 flags |= EFX_RX_PKT_PREFIX_LEN; 2791 } else { 2792 ++rx_queue->scatter_n; 2793 rx_queue->scatter_len += rx_bytes; 2794 if (rx_cont) 2795 return 0; 2796 n_packets = 1; 2797 } 2798 2799 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1, 2800 ESF_DZ_RX_IPCKSUM_ERR, 1, 2801 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1, 2802 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1, 2803 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1); 2804 EFX_AND_QWORD(errors, *event, errors); 2805 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) { 2806 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets, 2807 rx_encap_hdr, 2808 rx_l3_class, rx_l4_class, 2809 event); 2810 } else { 2811 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP || 2812 rx_l4_class == ESE_FZ_L4_CLASS_UDP; 2813 2814 switch (rx_encap_hdr) { 2815 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */ 2816 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */ 2817 if (tcpudp) 2818 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */ 2819 break; 2820 case ESE_EZ_ENCAP_HDR_GRE: 2821 case ESE_EZ_ENCAP_HDR_NONE: 2822 if (tcpudp) 2823 flags |= EFX_RX_PKT_CSUMMED; 2824 break; 2825 default: 2826 netdev_WARN(efx->net_dev, 2827 "unknown encapsulation type: event=" 2828 EFX_QWORD_FMT "\n", 2829 EFX_QWORD_VAL(*event)); 2830 } 2831 } 2832 2833 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP) 2834 flags |= EFX_RX_PKT_TCP; 2835 2836 channel->irq_mod_score += 2 * n_packets; 2837 2838 /* Handle received packet(s) */ 2839 for (i = 0; i < n_packets; i++) { 2840 efx_rx_packet(rx_queue, 2841 rx_queue->removed_count & rx_queue->ptr_mask, 2842 rx_queue->scatter_n, rx_queue->scatter_len, 2843 flags); 2844 rx_queue->removed_count += rx_queue->scatter_n; 2845 } 2846 2847 rx_queue->scatter_n = 0; 2848 rx_queue->scatter_len = 0; 2849 2850 return n_packets; 2851 } 2852 2853 static u32 efx_ef10_extract_event_ts(efx_qword_t *event) 2854 { 2855 u32 tstamp; 2856 2857 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI); 2858 tstamp <<= 16; 2859 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO); 2860 2861 return tstamp; 2862 } 2863 2864 static void 2865 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2866 { 2867 struct efx_nic *efx = channel->efx; 2868 struct efx_tx_queue *tx_queue; 2869 unsigned int tx_ev_desc_ptr; 2870 unsigned int tx_ev_q_label; 2871 unsigned int tx_ev_type; 2872 u64 ts_part; 2873 2874 if (unlikely(READ_ONCE(efx->reset_pending))) 2875 return; 2876 2877 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2878 return; 2879 2880 /* Get the transmit queue */ 2881 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2882 tx_queue = efx_channel_get_tx_queue(channel, 2883 tx_ev_q_label % EFX_TXQ_TYPES); 2884 2885 if (!tx_queue->timestamping) { 2886 /* Transmit completion */ 2887 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2888 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2889 return; 2890 } 2891 2892 /* Transmit timestamps are only available for 8XXX series. They result 2893 * in up to three events per packet. These occur in order, and are: 2894 * - the normal completion event (may be omitted) 2895 * - the low part of the timestamp 2896 * - the high part of the timestamp 2897 * 2898 * It's possible for multiple completion events to appear before the 2899 * corresponding timestamps. So we can for example get: 2900 * COMP N 2901 * COMP N+1 2902 * TS_LO N 2903 * TS_HI N 2904 * TS_LO N+1 2905 * TS_HI N+1 2906 * 2907 * In addition it's also possible for the adjacent completions to be 2908 * merged, so we may not see COMP N above. As such, the completion 2909 * events are not very useful here. 2910 * 2911 * Each part of the timestamp is itself split across two 16 bit 2912 * fields in the event. 2913 */ 2914 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1); 2915 2916 switch (tx_ev_type) { 2917 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION: 2918 /* Ignore this event - see above. */ 2919 break; 2920 2921 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO: 2922 ts_part = efx_ef10_extract_event_ts(event); 2923 tx_queue->completed_timestamp_minor = ts_part; 2924 break; 2925 2926 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI: 2927 ts_part = efx_ef10_extract_event_ts(event); 2928 tx_queue->completed_timestamp_major = ts_part; 2929 2930 efx_xmit_done_single(tx_queue); 2931 break; 2932 2933 default: 2934 netif_err(efx, hw, efx->net_dev, 2935 "channel %d unknown tx event type %d (data " 2936 EFX_QWORD_FMT ")\n", 2937 channel->channel, tx_ev_type, 2938 EFX_QWORD_VAL(*event)); 2939 break; 2940 } 2941 } 2942 2943 static void 2944 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 2945 { 2946 struct efx_nic *efx = channel->efx; 2947 int subcode; 2948 2949 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 2950 2951 switch (subcode) { 2952 case ESE_DZ_DRV_TIMER_EV: 2953 case ESE_DZ_DRV_WAKE_UP_EV: 2954 break; 2955 case ESE_DZ_DRV_START_UP_EV: 2956 /* event queue init complete. ok. */ 2957 break; 2958 default: 2959 netif_err(efx, hw, efx->net_dev, 2960 "channel %d unknown driver event type %d" 2961 " (data " EFX_QWORD_FMT ")\n", 2962 channel->channel, subcode, 2963 EFX_QWORD_VAL(*event)); 2964 2965 } 2966 } 2967 2968 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 2969 efx_qword_t *event) 2970 { 2971 struct efx_nic *efx = channel->efx; 2972 u32 subcode; 2973 2974 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 2975 2976 switch (subcode) { 2977 case EFX_EF10_TEST: 2978 channel->event_test_cpu = raw_smp_processor_id(); 2979 break; 2980 case EFX_EF10_REFILL: 2981 /* The queue must be empty, so we won't receive any rx 2982 * events, so efx_process_channel() won't refill the 2983 * queue. Refill it here 2984 */ 2985 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 2986 break; 2987 default: 2988 netif_err(efx, hw, efx->net_dev, 2989 "channel %d unknown driver event type %u" 2990 " (data " EFX_QWORD_FMT ")\n", 2991 channel->channel, (unsigned) subcode, 2992 EFX_QWORD_VAL(*event)); 2993 } 2994 } 2995 2996 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 2997 { 2998 struct efx_nic *efx = channel->efx; 2999 efx_qword_t event, *p_event; 3000 unsigned int read_ptr; 3001 int ev_code; 3002 int spent = 0; 3003 3004 if (quota <= 0) 3005 return spent; 3006 3007 read_ptr = channel->eventq_read_ptr; 3008 3009 for (;;) { 3010 p_event = efx_event(channel, read_ptr); 3011 event = *p_event; 3012 3013 if (!efx_event_present(&event)) 3014 break; 3015 3016 EFX_SET_QWORD(*p_event); 3017 3018 ++read_ptr; 3019 3020 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 3021 3022 netif_vdbg(efx, drv, efx->net_dev, 3023 "processing event on %d " EFX_QWORD_FMT "\n", 3024 channel->channel, EFX_QWORD_VAL(event)); 3025 3026 switch (ev_code) { 3027 case ESE_DZ_EV_CODE_MCDI_EV: 3028 efx_mcdi_process_event(channel, &event); 3029 break; 3030 case ESE_DZ_EV_CODE_RX_EV: 3031 spent += efx_ef10_handle_rx_event(channel, &event); 3032 if (spent >= quota) { 3033 /* XXX can we split a merged event to 3034 * avoid going over-quota? 3035 */ 3036 spent = quota; 3037 goto out; 3038 } 3039 break; 3040 case ESE_DZ_EV_CODE_TX_EV: 3041 efx_ef10_handle_tx_event(channel, &event); 3042 break; 3043 case ESE_DZ_EV_CODE_DRIVER_EV: 3044 efx_ef10_handle_driver_event(channel, &event); 3045 if (++spent == quota) 3046 goto out; 3047 break; 3048 case EFX_EF10_DRVGEN_EV: 3049 efx_ef10_handle_driver_generated_event(channel, &event); 3050 break; 3051 default: 3052 netif_err(efx, hw, efx->net_dev, 3053 "channel %d unknown event type %d" 3054 " (data " EFX_QWORD_FMT ")\n", 3055 channel->channel, ev_code, 3056 EFX_QWORD_VAL(event)); 3057 } 3058 } 3059 3060 out: 3061 channel->eventq_read_ptr = read_ptr; 3062 return spent; 3063 } 3064 3065 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 3066 { 3067 struct efx_nic *efx = channel->efx; 3068 efx_dword_t rptr; 3069 3070 if (EFX_EF10_WORKAROUND_35388(efx)) { 3071 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 3072 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 3073 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 3074 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 3075 3076 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3077 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 3078 ERF_DD_EVQ_IND_RPTR, 3079 (channel->eventq_read_ptr & 3080 channel->eventq_mask) >> 3081 ERF_DD_EVQ_IND_RPTR_WIDTH); 3082 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3083 channel->channel); 3084 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3085 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 3086 ERF_DD_EVQ_IND_RPTR, 3087 channel->eventq_read_ptr & 3088 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 3089 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3090 channel->channel); 3091 } else { 3092 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 3093 channel->eventq_read_ptr & 3094 channel->eventq_mask); 3095 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 3096 } 3097 } 3098 3099 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 3100 { 3101 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 3102 struct efx_nic *efx = channel->efx; 3103 efx_qword_t event; 3104 int rc; 3105 3106 EFX_POPULATE_QWORD_2(event, 3107 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 3108 ESF_DZ_EV_DATA, EFX_EF10_TEST); 3109 3110 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 3111 3112 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 3113 * already swapped the data to little-endian order. 3114 */ 3115 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 3116 sizeof(efx_qword_t)); 3117 3118 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 3119 NULL, 0, NULL); 3120 if (rc != 0) 3121 goto fail; 3122 3123 return; 3124 3125 fail: 3126 WARN_ON(true); 3127 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 3128 } 3129 3130 static void efx_ef10_prepare_flr(struct efx_nic *efx) 3131 { 3132 atomic_set(&efx->active_queues, 0); 3133 } 3134 3135 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 3136 { 3137 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3138 u8 mac_old[ETH_ALEN]; 3139 int rc, rc2; 3140 3141 /* Only reconfigure a PF-created vport */ 3142 if (is_zero_ether_addr(nic_data->vport_mac)) 3143 return 0; 3144 3145 efx_device_detach_sync(efx); 3146 efx_net_stop(efx->net_dev); 3147 down_write(&efx->filter_sem); 3148 efx_mcdi_filter_table_remove(efx); 3149 up_write(&efx->filter_sem); 3150 3151 rc = efx_ef10_vadaptor_free(efx, efx->vport_id); 3152 if (rc) 3153 goto restore_filters; 3154 3155 ether_addr_copy(mac_old, nic_data->vport_mac); 3156 rc = efx_ef10_vport_del_mac(efx, efx->vport_id, 3157 nic_data->vport_mac); 3158 if (rc) 3159 goto restore_vadaptor; 3160 3161 rc = efx_ef10_vport_add_mac(efx, efx->vport_id, 3162 efx->net_dev->dev_addr); 3163 if (!rc) { 3164 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 3165 } else { 3166 rc2 = efx_ef10_vport_add_mac(efx, efx->vport_id, mac_old); 3167 if (rc2) { 3168 /* Failed to add original MAC, so clear vport_mac */ 3169 eth_zero_addr(nic_data->vport_mac); 3170 goto reset_nic; 3171 } 3172 } 3173 3174 restore_vadaptor: 3175 rc2 = efx_ef10_vadaptor_alloc(efx, efx->vport_id); 3176 if (rc2) 3177 goto reset_nic; 3178 restore_filters: 3179 down_write(&efx->filter_sem); 3180 rc2 = efx_ef10_filter_table_probe(efx); 3181 up_write(&efx->filter_sem); 3182 if (rc2) 3183 goto reset_nic; 3184 3185 rc2 = efx_net_open(efx->net_dev); 3186 if (rc2) 3187 goto reset_nic; 3188 3189 efx_device_attach_if_not_resetting(efx); 3190 3191 return rc; 3192 3193 reset_nic: 3194 netif_err(efx, drv, efx->net_dev, 3195 "Failed to restore when changing MAC address - scheduling reset\n"); 3196 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 3197 3198 return rc ? rc : rc2; 3199 } 3200 3201 static int efx_ef10_set_mac_address(struct efx_nic *efx) 3202 { 3203 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 3204 bool was_enabled = efx->port_enabled; 3205 int rc; 3206 3207 efx_device_detach_sync(efx); 3208 efx_net_stop(efx->net_dev); 3209 3210 mutex_lock(&efx->mac_lock); 3211 down_write(&efx->filter_sem); 3212 efx_mcdi_filter_table_remove(efx); 3213 3214 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 3215 efx->net_dev->dev_addr); 3216 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 3217 efx->vport_id); 3218 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 3219 sizeof(inbuf), NULL, 0, NULL); 3220 3221 efx_ef10_filter_table_probe(efx); 3222 up_write(&efx->filter_sem); 3223 mutex_unlock(&efx->mac_lock); 3224 3225 if (was_enabled) 3226 efx_net_open(efx->net_dev); 3227 efx_device_attach_if_not_resetting(efx); 3228 3229 #ifdef CONFIG_SFC_SRIOV 3230 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 3231 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3232 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 3233 3234 if (rc == -EPERM) { 3235 struct efx_nic *efx_pf; 3236 3237 /* Switch to PF and change MAC address on vport */ 3238 efx_pf = pci_get_drvdata(pci_dev_pf); 3239 3240 rc = efx_ef10_sriov_set_vf_mac(efx_pf, 3241 nic_data->vf_index, 3242 efx->net_dev->dev_addr); 3243 } else if (!rc) { 3244 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 3245 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data; 3246 unsigned int i; 3247 3248 /* MAC address successfully changed by VF (with MAC 3249 * spoofing) so update the parent PF if possible. 3250 */ 3251 for (i = 0; i < efx_pf->vf_count; ++i) { 3252 struct ef10_vf *vf = nic_data->vf + i; 3253 3254 if (vf->efx == efx) { 3255 ether_addr_copy(vf->mac, 3256 efx->net_dev->dev_addr); 3257 return 0; 3258 } 3259 } 3260 } 3261 } else 3262 #endif 3263 if (rc == -EPERM) { 3264 netif_err(efx, drv, efx->net_dev, 3265 "Cannot change MAC address; use sfboot to enable" 3266 " mac-spoofing on this interface\n"); 3267 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 3268 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 3269 * fall-back to the method of changing the MAC address on the 3270 * vport. This only applies to PFs because such versions of 3271 * MCFW do not support VFs. 3272 */ 3273 rc = efx_ef10_vport_set_mac_address(efx); 3274 } else if (rc) { 3275 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 3276 sizeof(inbuf), NULL, 0, rc); 3277 } 3278 3279 return rc; 3280 } 3281 3282 static int efx_ef10_mac_reconfigure(struct efx_nic *efx, bool mtu_only) 3283 { 3284 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 3285 3286 efx_mcdi_filter_sync_rx_mode(efx); 3287 3288 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED)) 3289 return efx_mcdi_set_mtu(efx); 3290 return efx_mcdi_set_mac(efx); 3291 } 3292 3293 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 3294 { 3295 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 3296 3297 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 3298 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 3299 NULL, 0, NULL); 3300 } 3301 3302 /* MC BISTs follow a different poll mechanism to phy BISTs. 3303 * The BIST is done in the poll handler on the MC, and the MCDI command 3304 * will block until the BIST is done. 3305 */ 3306 static int efx_ef10_poll_bist(struct efx_nic *efx) 3307 { 3308 int rc; 3309 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 3310 size_t outlen; 3311 u32 result; 3312 3313 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 3314 outbuf, sizeof(outbuf), &outlen); 3315 if (rc != 0) 3316 return rc; 3317 3318 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 3319 return -EIO; 3320 3321 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 3322 switch (result) { 3323 case MC_CMD_POLL_BIST_PASSED: 3324 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 3325 return 0; 3326 case MC_CMD_POLL_BIST_TIMEOUT: 3327 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 3328 return -EIO; 3329 case MC_CMD_POLL_BIST_FAILED: 3330 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 3331 return -EIO; 3332 default: 3333 netif_err(efx, hw, efx->net_dev, 3334 "BIST returned unknown result %u", result); 3335 return -EIO; 3336 } 3337 } 3338 3339 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 3340 { 3341 int rc; 3342 3343 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 3344 3345 rc = efx_ef10_start_bist(efx, bist_type); 3346 if (rc != 0) 3347 return rc; 3348 3349 return efx_ef10_poll_bist(efx); 3350 } 3351 3352 static int 3353 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 3354 { 3355 int rc, rc2; 3356 3357 efx_reset_down(efx, RESET_TYPE_WORLD); 3358 3359 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 3360 NULL, 0, NULL, 0, NULL); 3361 if (rc != 0) 3362 goto out; 3363 3364 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 3365 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 3366 3367 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 3368 3369 out: 3370 if (rc == -EPERM) 3371 rc = 0; 3372 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 3373 return rc ? rc : rc2; 3374 } 3375 3376 #ifdef CONFIG_SFC_MTD 3377 3378 struct efx_ef10_nvram_type_info { 3379 u16 type, type_mask; 3380 u8 port; 3381 const char *name; 3382 }; 3383 3384 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 3385 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 3386 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 3387 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 3388 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 3389 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 3390 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 3391 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 3392 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 3393 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 3394 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 3395 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 3396 { NVRAM_PARTITION_TYPE_MUM_FIRMWARE, 0, 0, "sfc_mumfw" }, 3397 { NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 0, 0, "sfc_uefi" }, 3398 { NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS, 0, 0, "sfc_dynamic_cfg_dflt" }, 3399 { NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS, 0, 0, "sfc_exp_rom_cfg_dflt" }, 3400 { NVRAM_PARTITION_TYPE_STATUS, 0, 0, "sfc_status" }, 3401 { NVRAM_PARTITION_TYPE_BUNDLE, 0, 0, "sfc_bundle" }, 3402 { NVRAM_PARTITION_TYPE_BUNDLE_METADATA, 0, 0, "sfc_bundle_metadata" }, 3403 }; 3404 #define EF10_NVRAM_PARTITION_COUNT ARRAY_SIZE(efx_ef10_nvram_types) 3405 3406 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 3407 struct efx_mcdi_mtd_partition *part, 3408 unsigned int type, 3409 unsigned long *found) 3410 { 3411 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 3412 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 3413 const struct efx_ef10_nvram_type_info *info; 3414 size_t size, erase_size, outlen; 3415 int type_idx = 0; 3416 bool protected; 3417 int rc; 3418 3419 for (type_idx = 0; ; type_idx++) { 3420 if (type_idx == EF10_NVRAM_PARTITION_COUNT) 3421 return -ENODEV; 3422 info = efx_ef10_nvram_types + type_idx; 3423 if ((type & ~info->type_mask) == info->type) 3424 break; 3425 } 3426 if (info->port != efx_port_num(efx)) 3427 return -ENODEV; 3428 3429 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 3430 if (rc) 3431 return rc; 3432 if (protected && 3433 (type != NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS && 3434 type != NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS)) 3435 /* Hide protected partitions that don't provide defaults. */ 3436 return -ENODEV; 3437 3438 if (protected) 3439 /* Protected partitions are read only. */ 3440 erase_size = 0; 3441 3442 /* If we've already exposed a partition of this type, hide this 3443 * duplicate. All operations on MTDs are keyed by the type anyway, 3444 * so we can't act on the duplicate. 3445 */ 3446 if (__test_and_set_bit(type_idx, found)) 3447 return -EEXIST; 3448 3449 part->nvram_type = type; 3450 3451 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 3452 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 3453 outbuf, sizeof(outbuf), &outlen); 3454 if (rc) 3455 return rc; 3456 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 3457 return -EIO; 3458 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 3459 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 3460 part->fw_subtype = MCDI_DWORD(outbuf, 3461 NVRAM_METADATA_OUT_SUBTYPE); 3462 3463 part->common.dev_type_name = "EF10 NVRAM manager"; 3464 part->common.type_name = info->name; 3465 3466 part->common.mtd.type = MTD_NORFLASH; 3467 part->common.mtd.flags = MTD_CAP_NORFLASH; 3468 part->common.mtd.size = size; 3469 part->common.mtd.erasesize = erase_size; 3470 /* sfc_status is read-only */ 3471 if (!erase_size) 3472 part->common.mtd.flags |= MTD_NO_ERASE; 3473 3474 return 0; 3475 } 3476 3477 static int efx_ef10_mtd_probe(struct efx_nic *efx) 3478 { 3479 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 3480 DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 }; 3481 struct efx_mcdi_mtd_partition *parts; 3482 size_t outlen, n_parts_total, i, n_parts; 3483 unsigned int type; 3484 int rc; 3485 3486 ASSERT_RTNL(); 3487 3488 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 3489 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 3490 outbuf, sizeof(outbuf), &outlen); 3491 if (rc) 3492 return rc; 3493 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 3494 return -EIO; 3495 3496 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 3497 if (n_parts_total > 3498 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 3499 return -EIO; 3500 3501 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 3502 if (!parts) 3503 return -ENOMEM; 3504 3505 n_parts = 0; 3506 for (i = 0; i < n_parts_total; i++) { 3507 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 3508 i); 3509 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type, 3510 found); 3511 if (rc == -EEXIST || rc == -ENODEV) 3512 continue; 3513 if (rc) 3514 goto fail; 3515 n_parts++; 3516 } 3517 3518 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 3519 fail: 3520 if (rc) 3521 kfree(parts); 3522 return rc; 3523 } 3524 3525 #endif /* CONFIG_SFC_MTD */ 3526 3527 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 3528 { 3529 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 3530 } 3531 3532 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 3533 u32 host_time) {} 3534 3535 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 3536 bool temp) 3537 { 3538 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 3539 int rc; 3540 3541 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 3542 channel->sync_events_state == SYNC_EVENTS_VALID || 3543 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 3544 return 0; 3545 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 3546 3547 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 3548 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3549 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 3550 channel->channel); 3551 3552 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3553 inbuf, sizeof(inbuf), NULL, 0, NULL); 3554 3555 if (rc != 0) 3556 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3557 SYNC_EVENTS_DISABLED; 3558 3559 return rc; 3560 } 3561 3562 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 3563 bool temp) 3564 { 3565 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 3566 int rc; 3567 3568 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 3569 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 3570 return 0; 3571 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 3572 channel->sync_events_state = SYNC_EVENTS_DISABLED; 3573 return 0; 3574 } 3575 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3576 SYNC_EVENTS_DISABLED; 3577 3578 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 3579 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3580 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 3581 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 3582 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 3583 channel->channel); 3584 3585 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3586 inbuf, sizeof(inbuf), NULL, 0, NULL); 3587 3588 return rc; 3589 } 3590 3591 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 3592 bool temp) 3593 { 3594 int (*set)(struct efx_channel *channel, bool temp); 3595 struct efx_channel *channel; 3596 3597 set = en ? 3598 efx_ef10_rx_enable_timestamping : 3599 efx_ef10_rx_disable_timestamping; 3600 3601 channel = efx_ptp_channel(efx); 3602 if (channel) { 3603 int rc = set(channel, temp); 3604 if (en && rc != 0) { 3605 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 3606 return rc; 3607 } 3608 } 3609 3610 return 0; 3611 } 3612 3613 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 3614 struct hwtstamp_config *init) 3615 { 3616 return -EOPNOTSUPP; 3617 } 3618 3619 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 3620 struct hwtstamp_config *init) 3621 { 3622 int rc; 3623 3624 switch (init->rx_filter) { 3625 case HWTSTAMP_FILTER_NONE: 3626 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 3627 /* if TX timestamping is still requested then leave PTP on */ 3628 return efx_ptp_change_mode(efx, 3629 init->tx_type != HWTSTAMP_TX_OFF, 0); 3630 case HWTSTAMP_FILTER_ALL: 3631 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3632 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3633 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3634 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3635 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3636 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3637 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3638 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3639 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3640 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3641 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3642 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3643 case HWTSTAMP_FILTER_NTP_ALL: 3644 init->rx_filter = HWTSTAMP_FILTER_ALL; 3645 rc = efx_ptp_change_mode(efx, true, 0); 3646 if (!rc) 3647 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 3648 if (rc) 3649 efx_ptp_change_mode(efx, false, 0); 3650 return rc; 3651 default: 3652 return -ERANGE; 3653 } 3654 } 3655 3656 static int efx_ef10_get_phys_port_id(struct efx_nic *efx, 3657 struct netdev_phys_item_id *ppid) 3658 { 3659 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3660 3661 if (!is_valid_ether_addr(nic_data->port_id)) 3662 return -EOPNOTSUPP; 3663 3664 ppid->id_len = ETH_ALEN; 3665 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 3666 3667 return 0; 3668 } 3669 3670 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3671 { 3672 if (proto != htons(ETH_P_8021Q)) 3673 return -EINVAL; 3674 3675 return efx_ef10_add_vlan(efx, vid); 3676 } 3677 3678 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3679 { 3680 if (proto != htons(ETH_P_8021Q)) 3681 return -EINVAL; 3682 3683 return efx_ef10_del_vlan(efx, vid); 3684 } 3685 3686 /* We rely on the MCDI wiping out our TX rings if it made any changes to the 3687 * ports table, ensuring that any TSO descriptors that were made on a now- 3688 * removed tunnel port will be blown away and won't break things when we try 3689 * to transmit them using the new ports table. 3690 */ 3691 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading) 3692 { 3693 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3694 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX); 3695 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN); 3696 bool will_reset = false; 3697 size_t num_entries = 0; 3698 size_t inlen, outlen; 3699 size_t i; 3700 int rc; 3701 efx_dword_t flags_and_num_entries; 3702 3703 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock)); 3704 3705 nic_data->udp_tunnels_dirty = false; 3706 3707 if (!(nic_data->datapath_caps & 3708 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) { 3709 efx_device_attach_if_not_resetting(efx); 3710 return 0; 3711 } 3712 3713 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) > 3714 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM); 3715 3716 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) { 3717 if (nic_data->udp_tunnels[i].type != 3718 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID) { 3719 efx_dword_t entry; 3720 3721 EFX_POPULATE_DWORD_2(entry, 3722 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT, 3723 ntohs(nic_data->udp_tunnels[i].port), 3724 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL, 3725 nic_data->udp_tunnels[i].type); 3726 *_MCDI_ARRAY_DWORD(inbuf, 3727 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES, 3728 num_entries++) = entry; 3729 } 3730 } 3731 3732 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST - 3733 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 != 3734 EFX_WORD_1_LBN); 3735 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 != 3736 EFX_WORD_1_WIDTH); 3737 EFX_POPULATE_DWORD_2(flags_and_num_entries, 3738 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING, 3739 !!unloading, 3740 EFX_WORD_1, num_entries); 3741 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) = 3742 flags_and_num_entries; 3743 3744 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries); 3745 3746 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS, 3747 inbuf, inlen, outbuf, sizeof(outbuf), &outlen); 3748 if (rc == -EIO) { 3749 /* Most likely the MC rebooted due to another function also 3750 * setting its tunnel port list. Mark the tunnel port list as 3751 * dirty, so it will be pushed upon coming up from the reboot. 3752 */ 3753 nic_data->udp_tunnels_dirty = true; 3754 return 0; 3755 } 3756 3757 if (rc) { 3758 /* expected not available on unprivileged functions */ 3759 if (rc != -EPERM) 3760 netif_warn(efx, drv, efx->net_dev, 3761 "Unable to set UDP tunnel ports; rc=%d.\n", rc); 3762 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) & 3763 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) { 3764 netif_info(efx, drv, efx->net_dev, 3765 "Rebooting MC due to UDP tunnel port list change\n"); 3766 will_reset = true; 3767 if (unloading) 3768 /* Delay for the MC reset to complete. This will make 3769 * unloading other functions a bit smoother. This is a 3770 * race, but the other unload will work whichever way 3771 * it goes, this just avoids an unnecessary error 3772 * message. 3773 */ 3774 msleep(100); 3775 } 3776 if (!will_reset && !unloading) { 3777 /* The caller will have detached, relying on the MC reset to 3778 * trigger a re-attach. Since there won't be an MC reset, we 3779 * have to do the attach ourselves. 3780 */ 3781 efx_device_attach_if_not_resetting(efx); 3782 } 3783 3784 return rc; 3785 } 3786 3787 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx) 3788 { 3789 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3790 int rc = 0; 3791 3792 mutex_lock(&nic_data->udp_tunnels_lock); 3793 if (nic_data->udp_tunnels_dirty) { 3794 /* Make sure all TX are stopped while we modify the table, else 3795 * we might race against an efx_features_check(). 3796 */ 3797 efx_device_detach_sync(efx); 3798 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3799 } 3800 mutex_unlock(&nic_data->udp_tunnels_lock); 3801 return rc; 3802 } 3803 3804 static int efx_ef10_udp_tnl_set_port(struct net_device *dev, 3805 unsigned int table, unsigned int entry, 3806 struct udp_tunnel_info *ti) 3807 { 3808 struct efx_nic *efx = netdev_priv(dev); 3809 struct efx_ef10_nic_data *nic_data; 3810 int efx_tunnel_type, rc; 3811 3812 if (ti->type == UDP_TUNNEL_TYPE_VXLAN) 3813 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN; 3814 else 3815 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE; 3816 3817 nic_data = efx->nic_data; 3818 if (!(nic_data->datapath_caps & 3819 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3820 return -EOPNOTSUPP; 3821 3822 mutex_lock(&nic_data->udp_tunnels_lock); 3823 /* Make sure all TX are stopped while we add to the table, else we 3824 * might race against an efx_features_check(). 3825 */ 3826 efx_device_detach_sync(efx); 3827 nic_data->udp_tunnels[entry].type = efx_tunnel_type; 3828 nic_data->udp_tunnels[entry].port = ti->port; 3829 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3830 mutex_unlock(&nic_data->udp_tunnels_lock); 3831 3832 return rc; 3833 } 3834 3835 /* Called under the TX lock with the TX queue running, hence no-one can be 3836 * in the middle of updating the UDP tunnels table. However, they could 3837 * have tried and failed the MCDI, in which case they'll have set the dirty 3838 * flag before dropping their locks. 3839 */ 3840 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port) 3841 { 3842 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3843 size_t i; 3844 3845 if (!(nic_data->datapath_caps & 3846 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3847 return false; 3848 3849 if (nic_data->udp_tunnels_dirty) 3850 /* SW table may not match HW state, so just assume we can't 3851 * use any UDP tunnel offloads. 3852 */ 3853 return false; 3854 3855 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 3856 if (nic_data->udp_tunnels[i].type != 3857 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID && 3858 nic_data->udp_tunnels[i].port == port) 3859 return true; 3860 3861 return false; 3862 } 3863 3864 static int efx_ef10_udp_tnl_unset_port(struct net_device *dev, 3865 unsigned int table, unsigned int entry, 3866 struct udp_tunnel_info *ti) 3867 { 3868 struct efx_nic *efx = netdev_priv(dev); 3869 struct efx_ef10_nic_data *nic_data; 3870 int rc; 3871 3872 nic_data = efx->nic_data; 3873 3874 mutex_lock(&nic_data->udp_tunnels_lock); 3875 /* Make sure all TX are stopped while we remove from the table, else we 3876 * might race against an efx_features_check(). 3877 */ 3878 efx_device_detach_sync(efx); 3879 nic_data->udp_tunnels[entry].type = TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 3880 nic_data->udp_tunnels[entry].port = 0; 3881 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3882 mutex_unlock(&nic_data->udp_tunnels_lock); 3883 3884 return rc; 3885 } 3886 3887 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels = { 3888 .set_port = efx_ef10_udp_tnl_set_port, 3889 .unset_port = efx_ef10_udp_tnl_unset_port, 3890 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP, 3891 .tables = { 3892 { 3893 .n_entries = 16, 3894 .tunnel_types = UDP_TUNNEL_TYPE_VXLAN | 3895 UDP_TUNNEL_TYPE_GENEVE, 3896 }, 3897 }, 3898 }; 3899 3900 /* EF10 may have multiple datapath firmware variants within a 3901 * single version. Report which variants are running. 3902 */ 3903 static size_t efx_ef10_print_additional_fwver(struct efx_nic *efx, char *buf, 3904 size_t len) 3905 { 3906 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3907 3908 return scnprintf(buf, len, " rx%x tx%x", 3909 nic_data->rx_dpcpu_fw_id, 3910 nic_data->tx_dpcpu_fw_id); 3911 } 3912 3913 static unsigned int ef10_check_caps(const struct efx_nic *efx, 3914 u8 flag, 3915 u32 offset) 3916 { 3917 const struct efx_ef10_nic_data *nic_data = efx->nic_data; 3918 3919 switch (offset) { 3920 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST): 3921 return nic_data->datapath_caps & BIT_ULL(flag); 3922 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST): 3923 return nic_data->datapath_caps2 & BIT_ULL(flag); 3924 default: 3925 return 0; 3926 } 3927 } 3928 3929 #define EF10_OFFLOAD_FEATURES \ 3930 (NETIF_F_IP_CSUM | \ 3931 NETIF_F_HW_VLAN_CTAG_FILTER | \ 3932 NETIF_F_IPV6_CSUM | \ 3933 NETIF_F_RXHASH | \ 3934 NETIF_F_NTUPLE) 3935 3936 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 3937 .is_vf = true, 3938 .mem_bar = efx_ef10_vf_mem_bar, 3939 .mem_map_size = efx_ef10_mem_map_size, 3940 .probe = efx_ef10_probe_vf, 3941 .remove = efx_ef10_remove, 3942 .dimension_resources = efx_ef10_dimension_resources, 3943 .init = efx_ef10_init_nic, 3944 .fini = efx_ef10_fini_nic, 3945 .map_reset_reason = efx_ef10_map_reset_reason, 3946 .map_reset_flags = efx_ef10_map_reset_flags, 3947 .reset = efx_ef10_reset, 3948 .probe_port = efx_mcdi_port_probe, 3949 .remove_port = efx_mcdi_port_remove, 3950 .fini_dmaq = efx_fini_dmaq, 3951 .prepare_flr = efx_ef10_prepare_flr, 3952 .finish_flr = efx_port_dummy_op_void, 3953 .describe_stats = efx_ef10_describe_stats, 3954 .update_stats = efx_ef10_update_stats_vf, 3955 .start_stats = efx_port_dummy_op_void, 3956 .pull_stats = efx_port_dummy_op_void, 3957 .stop_stats = efx_port_dummy_op_void, 3958 .set_id_led = efx_mcdi_set_id_led, 3959 .push_irq_moderation = efx_ef10_push_irq_moderation, 3960 .reconfigure_mac = efx_ef10_mac_reconfigure, 3961 .check_mac_fault = efx_mcdi_mac_check_fault, 3962 .reconfigure_port = efx_mcdi_port_reconfigure, 3963 .get_wol = efx_ef10_get_wol_vf, 3964 .set_wol = efx_ef10_set_wol_vf, 3965 .resume_wol = efx_port_dummy_op_void, 3966 .mcdi_request = efx_ef10_mcdi_request, 3967 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 3968 .mcdi_read_response = efx_ef10_mcdi_read_response, 3969 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 3970 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 3971 .irq_enable_master = efx_port_dummy_op_void, 3972 .irq_test_generate = efx_ef10_irq_test_generate, 3973 .irq_disable_non_ev = efx_port_dummy_op_void, 3974 .irq_handle_msi = efx_ef10_msi_interrupt, 3975 .irq_handle_legacy = efx_ef10_legacy_interrupt, 3976 .tx_probe = efx_ef10_tx_probe, 3977 .tx_init = efx_ef10_tx_init, 3978 .tx_remove = efx_mcdi_tx_remove, 3979 .tx_write = efx_ef10_tx_write, 3980 .tx_limit_len = efx_ef10_tx_limit_len, 3981 .tx_enqueue = __efx_enqueue_skb, 3982 .rx_push_rss_config = efx_mcdi_vf_rx_push_rss_config, 3983 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 3984 .rx_probe = efx_mcdi_rx_probe, 3985 .rx_init = efx_mcdi_rx_init, 3986 .rx_remove = efx_mcdi_rx_remove, 3987 .rx_write = efx_ef10_rx_write, 3988 .rx_defer_refill = efx_ef10_rx_defer_refill, 3989 .rx_packet = __efx_rx_packet, 3990 .ev_probe = efx_mcdi_ev_probe, 3991 .ev_init = efx_ef10_ev_init, 3992 .ev_fini = efx_mcdi_ev_fini, 3993 .ev_remove = efx_mcdi_ev_remove, 3994 .ev_process = efx_ef10_ev_process, 3995 .ev_read_ack = efx_ef10_ev_read_ack, 3996 .ev_test_generate = efx_ef10_ev_test_generate, 3997 .filter_table_probe = efx_ef10_filter_table_probe, 3998 .filter_table_restore = efx_mcdi_filter_table_restore, 3999 .filter_table_remove = efx_mcdi_filter_table_remove, 4000 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4001 .filter_insert = efx_mcdi_filter_insert, 4002 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4003 .filter_get_safe = efx_mcdi_filter_get_safe, 4004 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4005 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4006 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4007 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4008 #ifdef CONFIG_RFS_ACCEL 4009 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4010 #endif 4011 #ifdef CONFIG_SFC_MTD 4012 .mtd_probe = efx_port_dummy_op_int, 4013 #endif 4014 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4015 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4016 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4017 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4018 #ifdef CONFIG_SFC_SRIOV 4019 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4020 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4021 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4022 #endif 4023 .get_mac_address = efx_ef10_get_mac_address_vf, 4024 .set_mac_address = efx_ef10_set_mac_address, 4025 4026 .get_phys_port_id = efx_ef10_get_phys_port_id, 4027 .revision = EFX_REV_HUNT_A0, 4028 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4029 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4030 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4031 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4032 .can_rx_scatter = true, 4033 .always_rx_scatter = true, 4034 .min_interrupt_mode = EFX_INT_MODE_MSIX, 4035 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4036 .offload_features = EF10_OFFLOAD_FEATURES, 4037 .mcdi_max_ver = 2, 4038 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4039 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4040 1 << HWTSTAMP_FILTER_ALL, 4041 .rx_hash_key_size = 40, 4042 .check_caps = ef10_check_caps, 4043 .print_additional_fwver = efx_ef10_print_additional_fwver, 4044 .sensor_event = efx_mcdi_sensor_event, 4045 }; 4046 4047 const struct efx_nic_type efx_hunt_a0_nic_type = { 4048 .is_vf = false, 4049 .mem_bar = efx_ef10_pf_mem_bar, 4050 .mem_map_size = efx_ef10_mem_map_size, 4051 .probe = efx_ef10_probe_pf, 4052 .remove = efx_ef10_remove, 4053 .dimension_resources = efx_ef10_dimension_resources, 4054 .init = efx_ef10_init_nic, 4055 .fini = efx_ef10_fini_nic, 4056 .map_reset_reason = efx_ef10_map_reset_reason, 4057 .map_reset_flags = efx_ef10_map_reset_flags, 4058 .reset = efx_ef10_reset, 4059 .probe_port = efx_mcdi_port_probe, 4060 .remove_port = efx_mcdi_port_remove, 4061 .fini_dmaq = efx_fini_dmaq, 4062 .prepare_flr = efx_ef10_prepare_flr, 4063 .finish_flr = efx_port_dummy_op_void, 4064 .describe_stats = efx_ef10_describe_stats, 4065 .update_stats = efx_ef10_update_stats_pf, 4066 .start_stats = efx_mcdi_mac_start_stats, 4067 .pull_stats = efx_mcdi_mac_pull_stats, 4068 .stop_stats = efx_mcdi_mac_stop_stats, 4069 .set_id_led = efx_mcdi_set_id_led, 4070 .push_irq_moderation = efx_ef10_push_irq_moderation, 4071 .reconfigure_mac = efx_ef10_mac_reconfigure, 4072 .check_mac_fault = efx_mcdi_mac_check_fault, 4073 .reconfigure_port = efx_mcdi_port_reconfigure, 4074 .get_wol = efx_ef10_get_wol, 4075 .set_wol = efx_ef10_set_wol, 4076 .resume_wol = efx_port_dummy_op_void, 4077 .test_chip = efx_ef10_test_chip, 4078 .test_nvram = efx_mcdi_nvram_test_all, 4079 .mcdi_request = efx_ef10_mcdi_request, 4080 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4081 .mcdi_read_response = efx_ef10_mcdi_read_response, 4082 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4083 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4084 .irq_enable_master = efx_port_dummy_op_void, 4085 .irq_test_generate = efx_ef10_irq_test_generate, 4086 .irq_disable_non_ev = efx_port_dummy_op_void, 4087 .irq_handle_msi = efx_ef10_msi_interrupt, 4088 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4089 .tx_probe = efx_ef10_tx_probe, 4090 .tx_init = efx_ef10_tx_init, 4091 .tx_remove = efx_mcdi_tx_remove, 4092 .tx_write = efx_ef10_tx_write, 4093 .tx_limit_len = efx_ef10_tx_limit_len, 4094 .tx_enqueue = __efx_enqueue_skb, 4095 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 4096 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4097 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 4098 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 4099 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 4100 .rx_probe = efx_mcdi_rx_probe, 4101 .rx_init = efx_mcdi_rx_init, 4102 .rx_remove = efx_mcdi_rx_remove, 4103 .rx_write = efx_ef10_rx_write, 4104 .rx_defer_refill = efx_ef10_rx_defer_refill, 4105 .rx_packet = __efx_rx_packet, 4106 .ev_probe = efx_mcdi_ev_probe, 4107 .ev_init = efx_ef10_ev_init, 4108 .ev_fini = efx_mcdi_ev_fini, 4109 .ev_remove = efx_mcdi_ev_remove, 4110 .ev_process = efx_ef10_ev_process, 4111 .ev_read_ack = efx_ef10_ev_read_ack, 4112 .ev_test_generate = efx_ef10_ev_test_generate, 4113 .filter_table_probe = efx_ef10_filter_table_probe, 4114 .filter_table_restore = efx_mcdi_filter_table_restore, 4115 .filter_table_remove = efx_mcdi_filter_table_remove, 4116 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4117 .filter_insert = efx_mcdi_filter_insert, 4118 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4119 .filter_get_safe = efx_mcdi_filter_get_safe, 4120 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4121 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4122 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4123 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4124 #ifdef CONFIG_RFS_ACCEL 4125 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4126 #endif 4127 #ifdef CONFIG_SFC_MTD 4128 .mtd_probe = efx_ef10_mtd_probe, 4129 .mtd_rename = efx_mcdi_mtd_rename, 4130 .mtd_read = efx_mcdi_mtd_read, 4131 .mtd_erase = efx_mcdi_mtd_erase, 4132 .mtd_write = efx_mcdi_mtd_write, 4133 .mtd_sync = efx_mcdi_mtd_sync, 4134 #endif 4135 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4136 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4137 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4138 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4139 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4140 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports, 4141 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port, 4142 #ifdef CONFIG_SFC_SRIOV 4143 .sriov_configure = efx_ef10_sriov_configure, 4144 .sriov_init = efx_ef10_sriov_init, 4145 .sriov_fini = efx_ef10_sriov_fini, 4146 .sriov_wanted = efx_ef10_sriov_wanted, 4147 .sriov_reset = efx_ef10_sriov_reset, 4148 .sriov_flr = efx_ef10_sriov_flr, 4149 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4150 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4151 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4152 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4153 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4154 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4155 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4156 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4157 #endif 4158 .get_mac_address = efx_ef10_get_mac_address_pf, 4159 .set_mac_address = efx_ef10_set_mac_address, 4160 .tso_versions = efx_ef10_tso_versions, 4161 4162 .get_phys_port_id = efx_ef10_get_phys_port_id, 4163 .revision = EFX_REV_HUNT_A0, 4164 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4165 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4166 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4167 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4168 .can_rx_scatter = true, 4169 .always_rx_scatter = true, 4170 .option_descriptors = true, 4171 .min_interrupt_mode = EFX_INT_MODE_LEGACY, 4172 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4173 .offload_features = EF10_OFFLOAD_FEATURES, 4174 .mcdi_max_ver = 2, 4175 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4176 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4177 1 << HWTSTAMP_FILTER_ALL, 4178 .rx_hash_key_size = 40, 4179 .check_caps = ef10_check_caps, 4180 .print_additional_fwver = efx_ef10_print_additional_fwver, 4181 .sensor_event = efx_mcdi_sensor_event, 4182 }; 4183