1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2012-2013 Solarflare Communications Inc. 5 */ 6 7 #include "net_driver.h" 8 #include "rx_common.h" 9 #include "tx_common.h" 10 #include "ef10_regs.h" 11 #include "io.h" 12 #include "mcdi.h" 13 #include "mcdi_pcol.h" 14 #include "mcdi_port.h" 15 #include "mcdi_port_common.h" 16 #include "mcdi_functions.h" 17 #include "nic.h" 18 #include "mcdi_filters.h" 19 #include "workarounds.h" 20 #include "selftest.h" 21 #include "ef10_sriov.h" 22 #include <linux/in.h> 23 #include <linux/jhash.h> 24 #include <linux/wait.h> 25 #include <linux/workqueue.h> 26 #include <net/udp_tunnel.h> 27 28 /* Hardware control for EF10 architecture including 'Huntington'. */ 29 30 #define EFX_EF10_DRVGEN_EV 7 31 enum { 32 EFX_EF10_TEST = 1, 33 EFX_EF10_REFILL, 34 }; 35 36 /* VLAN list entry */ 37 struct efx_ef10_vlan { 38 struct list_head list; 39 u16 vid; 40 }; 41 42 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading); 43 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels; 44 45 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 46 { 47 efx_dword_t reg; 48 49 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 50 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 51 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 52 } 53 54 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for 55 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O 56 * bar; PFs use BAR 0/1 for memory. 57 */ 58 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx) 59 { 60 switch (efx->pci_dev->device) { 61 case 0x0b03: /* SFC9250 PF */ 62 return 0; 63 default: 64 return 2; 65 } 66 } 67 68 /* All VFs use BAR 0/1 for memory */ 69 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx) 70 { 71 return 0; 72 } 73 74 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 75 { 76 int bar; 77 78 bar = efx->type->mem_bar(efx); 79 return resource_size(&efx->pci_dev->resource[bar]); 80 } 81 82 static bool efx_ef10_is_vf(struct efx_nic *efx) 83 { 84 return efx->type->is_vf; 85 } 86 87 #ifdef CONFIG_SFC_SRIOV 88 static int efx_ef10_get_vf_index(struct efx_nic *efx) 89 { 90 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 91 struct efx_ef10_nic_data *nic_data = efx->nic_data; 92 size_t outlen; 93 int rc; 94 95 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 96 sizeof(outbuf), &outlen); 97 if (rc) 98 return rc; 99 if (outlen < sizeof(outbuf)) 100 return -EIO; 101 102 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 103 return 0; 104 } 105 #endif 106 107 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 108 { 109 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN); 110 struct efx_ef10_nic_data *nic_data = efx->nic_data; 111 size_t outlen; 112 int rc; 113 114 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 115 116 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 117 outbuf, sizeof(outbuf), &outlen); 118 if (rc) 119 return rc; 120 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 121 netif_err(efx, drv, efx->net_dev, 122 "unable to read datapath firmware capabilities\n"); 123 return -EIO; 124 } 125 126 nic_data->datapath_caps = 127 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 128 129 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) { 130 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 131 GET_CAPABILITIES_V2_OUT_FLAGS2); 132 nic_data->piobuf_size = MCDI_WORD(outbuf, 133 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF); 134 } else { 135 nic_data->datapath_caps2 = 0; 136 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE; 137 } 138 139 /* record the DPCPU firmware IDs to determine VEB vswitching support. 140 */ 141 nic_data->rx_dpcpu_fw_id = 142 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 143 nic_data->tx_dpcpu_fw_id = 144 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 145 146 if (!(nic_data->datapath_caps & 147 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 148 netif_err(efx, probe, efx->net_dev, 149 "current firmware does not support an RX prefix\n"); 150 return -ENODEV; 151 } 152 153 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { 154 u8 vi_window_mode = MCDI_BYTE(outbuf, 155 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 156 157 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 158 if (rc) 159 return rc; 160 } else { 161 /* keep default VI stride */ 162 netif_dbg(efx, probe, efx->net_dev, 163 "firmware did not report VI window mode, assuming vi_stride = %u\n", 164 efx->vi_stride); 165 } 166 167 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 168 efx->num_mac_stats = MCDI_WORD(outbuf, 169 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 170 netif_dbg(efx, probe, efx->net_dev, 171 "firmware reports num_mac_stats = %u\n", 172 efx->num_mac_stats); 173 } else { 174 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */ 175 netif_dbg(efx, probe, efx->net_dev, 176 "firmware did not report num_mac_stats, assuming %u\n", 177 efx->num_mac_stats); 178 } 179 180 return 0; 181 } 182 183 static void efx_ef10_read_licensed_features(struct efx_nic *efx) 184 { 185 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN); 186 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN); 187 struct efx_ef10_nic_data *nic_data = efx->nic_data; 188 size_t outlen; 189 int rc; 190 191 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP, 192 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE); 193 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf), 194 outbuf, sizeof(outbuf), &outlen); 195 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN)) 196 return; 197 198 nic_data->licensed_features = MCDI_QWORD(outbuf, 199 LICENSING_V3_OUT_LICENSED_FEATURES); 200 } 201 202 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 203 { 204 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 205 int rc; 206 207 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 208 outbuf, sizeof(outbuf), NULL); 209 if (rc) 210 return rc; 211 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 212 return rc > 0 ? rc : -ERANGE; 213 } 214 215 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx) 216 { 217 struct efx_ef10_nic_data *nic_data = efx->nic_data; 218 unsigned int implemented; 219 unsigned int enabled; 220 int rc; 221 222 nic_data->workaround_35388 = false; 223 nic_data->workaround_61265 = false; 224 225 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 226 227 if (rc == -ENOSYS) { 228 /* Firmware without GET_WORKAROUNDS - not a problem. */ 229 rc = 0; 230 } else if (rc == 0) { 231 /* Bug61265 workaround is always enabled if implemented. */ 232 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265) 233 nic_data->workaround_61265 = true; 234 235 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 236 nic_data->workaround_35388 = true; 237 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 238 /* Workaround is implemented but not enabled. 239 * Try to enable it. 240 */ 241 rc = efx_mcdi_set_workaround(efx, 242 MC_CMD_WORKAROUND_BUG35388, 243 true, NULL); 244 if (rc == 0) 245 nic_data->workaround_35388 = true; 246 /* If we failed to set the workaround just carry on. */ 247 rc = 0; 248 } 249 } 250 251 netif_dbg(efx, probe, efx->net_dev, 252 "workaround for bug 35388 is %sabled\n", 253 nic_data->workaround_35388 ? "en" : "dis"); 254 netif_dbg(efx, probe, efx->net_dev, 255 "workaround for bug 61265 is %sabled\n", 256 nic_data->workaround_61265 ? "en" : "dis"); 257 258 return rc; 259 } 260 261 static void efx_ef10_process_timer_config(struct efx_nic *efx, 262 const efx_dword_t *data) 263 { 264 unsigned int max_count; 265 266 if (EFX_EF10_WORKAROUND_61265(efx)) { 267 efx->timer_quantum_ns = MCDI_DWORD(data, 268 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS); 269 efx->timer_max_ns = MCDI_DWORD(data, 270 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS); 271 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 272 efx->timer_quantum_ns = MCDI_DWORD(data, 273 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT); 274 max_count = MCDI_DWORD(data, 275 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT); 276 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 277 } else { 278 efx->timer_quantum_ns = MCDI_DWORD(data, 279 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT); 280 max_count = MCDI_DWORD(data, 281 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT); 282 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 283 } 284 285 netif_dbg(efx, probe, efx->net_dev, 286 "got timer properties from MC: quantum %u ns; max %u ns\n", 287 efx->timer_quantum_ns, efx->timer_max_ns); 288 } 289 290 static int efx_ef10_get_timer_config(struct efx_nic *efx) 291 { 292 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN); 293 int rc; 294 295 rc = efx_ef10_get_timer_workarounds(efx); 296 if (rc) 297 return rc; 298 299 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0, 300 outbuf, sizeof(outbuf), NULL); 301 302 if (rc == 0) { 303 efx_ef10_process_timer_config(efx, outbuf); 304 } else if (rc == -ENOSYS || rc == -EPERM) { 305 /* Not available - fall back to Huntington defaults. */ 306 unsigned int quantum; 307 308 rc = efx_ef10_get_sysclk_freq(efx); 309 if (rc < 0) 310 return rc; 311 312 quantum = 1536000 / rc; /* 1536 cycles */ 313 efx->timer_quantum_ns = quantum; 314 efx->timer_max_ns = efx->type->timer_period_max * quantum; 315 rc = 0; 316 } else { 317 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, 318 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN, 319 NULL, 0, rc); 320 } 321 322 return rc; 323 } 324 325 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 326 { 327 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 328 size_t outlen; 329 int rc; 330 331 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 332 333 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 334 outbuf, sizeof(outbuf), &outlen); 335 if (rc) 336 return rc; 337 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 338 return -EIO; 339 340 ether_addr_copy(mac_address, 341 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 342 return 0; 343 } 344 345 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 346 { 347 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 348 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 349 size_t outlen; 350 int num_addrs, rc; 351 352 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 353 EVB_PORT_ID_ASSIGNED); 354 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 355 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 356 357 if (rc) 358 return rc; 359 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 360 return -EIO; 361 362 num_addrs = MCDI_DWORD(outbuf, 363 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 364 365 WARN_ON(num_addrs != 1); 366 367 ether_addr_copy(mac_address, 368 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 369 370 return 0; 371 } 372 373 static ssize_t link_control_flag_show(struct device *dev, 374 struct device_attribute *attr, 375 char *buf) 376 { 377 struct efx_nic *efx = dev_get_drvdata(dev); 378 379 return sprintf(buf, "%d\n", 380 ((efx->mcdi->fn_flags) & 381 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 382 ? 1 : 0); 383 } 384 385 static ssize_t primary_flag_show(struct device *dev, 386 struct device_attribute *attr, 387 char *buf) 388 { 389 struct efx_nic *efx = dev_get_drvdata(dev); 390 391 return sprintf(buf, "%d\n", 392 ((efx->mcdi->fn_flags) & 393 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 394 ? 1 : 0); 395 } 396 397 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid) 398 { 399 struct efx_ef10_nic_data *nic_data = efx->nic_data; 400 struct efx_ef10_vlan *vlan; 401 402 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 403 404 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 405 if (vlan->vid == vid) 406 return vlan; 407 } 408 409 return NULL; 410 } 411 412 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid) 413 { 414 struct efx_ef10_nic_data *nic_data = efx->nic_data; 415 struct efx_ef10_vlan *vlan; 416 int rc; 417 418 mutex_lock(&nic_data->vlan_lock); 419 420 vlan = efx_ef10_find_vlan(efx, vid); 421 if (vlan) { 422 /* We add VID 0 on init. 8021q adds it on module init 423 * for all interfaces with VLAN filtring feature. 424 */ 425 if (vid == 0) 426 goto done_unlock; 427 netif_warn(efx, drv, efx->net_dev, 428 "VLAN %u already added\n", vid); 429 rc = -EALREADY; 430 goto fail_exist; 431 } 432 433 rc = -ENOMEM; 434 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 435 if (!vlan) 436 goto fail_alloc; 437 438 vlan->vid = vid; 439 440 list_add_tail(&vlan->list, &nic_data->vlan_list); 441 442 if (efx->filter_state) { 443 mutex_lock(&efx->mac_lock); 444 down_write(&efx->filter_sem); 445 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 446 up_write(&efx->filter_sem); 447 mutex_unlock(&efx->mac_lock); 448 if (rc) 449 goto fail_filter_add_vlan; 450 } 451 452 done_unlock: 453 mutex_unlock(&nic_data->vlan_lock); 454 return 0; 455 456 fail_filter_add_vlan: 457 list_del(&vlan->list); 458 kfree(vlan); 459 fail_alloc: 460 fail_exist: 461 mutex_unlock(&nic_data->vlan_lock); 462 return rc; 463 } 464 465 static void efx_ef10_del_vlan_internal(struct efx_nic *efx, 466 struct efx_ef10_vlan *vlan) 467 { 468 struct efx_ef10_nic_data *nic_data = efx->nic_data; 469 470 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 471 472 if (efx->filter_state) { 473 down_write(&efx->filter_sem); 474 efx_mcdi_filter_del_vlan(efx, vlan->vid); 475 up_write(&efx->filter_sem); 476 } 477 478 list_del(&vlan->list); 479 kfree(vlan); 480 } 481 482 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid) 483 { 484 struct efx_ef10_nic_data *nic_data = efx->nic_data; 485 struct efx_ef10_vlan *vlan; 486 int rc = 0; 487 488 /* 8021q removes VID 0 on module unload for all interfaces 489 * with VLAN filtering feature. We need to keep it to receive 490 * untagged traffic. 491 */ 492 if (vid == 0) 493 return 0; 494 495 mutex_lock(&nic_data->vlan_lock); 496 497 vlan = efx_ef10_find_vlan(efx, vid); 498 if (!vlan) { 499 netif_err(efx, drv, efx->net_dev, 500 "VLAN %u to be deleted not found\n", vid); 501 rc = -ENOENT; 502 } else { 503 efx_ef10_del_vlan_internal(efx, vlan); 504 } 505 506 mutex_unlock(&nic_data->vlan_lock); 507 508 return rc; 509 } 510 511 static void efx_ef10_cleanup_vlans(struct efx_nic *efx) 512 { 513 struct efx_ef10_nic_data *nic_data = efx->nic_data; 514 struct efx_ef10_vlan *vlan, *next_vlan; 515 516 mutex_lock(&nic_data->vlan_lock); 517 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list) 518 efx_ef10_del_vlan_internal(efx, vlan); 519 mutex_unlock(&nic_data->vlan_lock); 520 } 521 522 static DEVICE_ATTR_RO(link_control_flag); 523 static DEVICE_ATTR_RO(primary_flag); 524 525 static int efx_ef10_probe(struct efx_nic *efx) 526 { 527 struct efx_ef10_nic_data *nic_data; 528 int i, rc; 529 530 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 531 if (!nic_data) 532 return -ENOMEM; 533 efx->nic_data = nic_data; 534 535 /* we assume later that we can copy from this buffer in dwords */ 536 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 537 538 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 539 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 540 if (rc) 541 goto fail1; 542 543 /* Get the MC's warm boot count. In case it's rebooting right 544 * now, be prepared to retry. 545 */ 546 i = 0; 547 for (;;) { 548 rc = efx_ef10_get_warm_boot_count(efx); 549 if (rc >= 0) 550 break; 551 if (++i == 5) 552 goto fail2; 553 ssleep(1); 554 } 555 nic_data->warm_boot_count = rc; 556 557 /* In case we're recovering from a crash (kexec), we want to 558 * cancel any outstanding request by the previous user of this 559 * function. We send a special message using the least 560 * significant bits of the 'high' (doorbell) register. 561 */ 562 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 563 564 rc = efx_mcdi_init(efx); 565 if (rc) 566 goto fail2; 567 568 mutex_init(&nic_data->udp_tunnels_lock); 569 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 570 nic_data->udp_tunnels[i].type = 571 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 572 573 /* Reset (most) configuration for this function */ 574 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 575 if (rc) 576 goto fail3; 577 578 /* Enable event logging */ 579 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 580 if (rc) 581 goto fail3; 582 583 rc = device_create_file(&efx->pci_dev->dev, 584 &dev_attr_link_control_flag); 585 if (rc) 586 goto fail3; 587 588 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 589 if (rc) 590 goto fail4; 591 592 rc = efx_get_pf_index(efx, &nic_data->pf_index); 593 if (rc) 594 goto fail5; 595 596 rc = efx_ef10_init_datapath_caps(efx); 597 if (rc < 0) 598 goto fail5; 599 600 efx_ef10_read_licensed_features(efx); 601 602 /* We can have one VI for each vi_stride-byte region. 603 * However, until we use TX option descriptors we need up to four 604 * TX queues per channel for different checksumming combinations. 605 */ 606 if (nic_data->datapath_caps & 607 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)) 608 efx->tx_queues_per_channel = 4; 609 else 610 efx->tx_queues_per_channel = 2; 611 efx->max_vis = efx_ef10_mem_map_size(efx) / efx->vi_stride; 612 if (!efx->max_vis) { 613 netif_err(efx, drv, efx->net_dev, "error determining max VIs\n"); 614 rc = -EIO; 615 goto fail5; 616 } 617 efx->max_channels = min_t(unsigned int, EFX_MAX_CHANNELS, 618 efx->max_vis / efx->tx_queues_per_channel); 619 efx->max_tx_channels = efx->max_channels; 620 if (WARN_ON(efx->max_channels == 0)) { 621 rc = -EIO; 622 goto fail5; 623 } 624 625 efx->rx_packet_len_offset = 626 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 627 628 if (nic_data->datapath_caps & 629 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN)) 630 efx->net_dev->hw_features |= NETIF_F_RXFCS; 631 632 rc = efx_mcdi_port_get_number(efx); 633 if (rc < 0) 634 goto fail5; 635 efx->port_num = rc; 636 637 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 638 if (rc) 639 goto fail5; 640 641 rc = efx_ef10_get_timer_config(efx); 642 if (rc < 0) 643 goto fail5; 644 645 rc = efx_mcdi_mon_probe(efx); 646 if (rc && rc != -EPERM) 647 goto fail5; 648 649 efx_ptp_defer_probe_with_channel(efx); 650 651 #ifdef CONFIG_SFC_SRIOV 652 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 653 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 654 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 655 656 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 657 } else 658 #endif 659 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 660 661 INIT_LIST_HEAD(&nic_data->vlan_list); 662 mutex_init(&nic_data->vlan_lock); 663 664 /* Add unspecified VID to support VLAN filtering being disabled */ 665 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 666 if (rc) 667 goto fail_add_vid_unspec; 668 669 /* If VLAN filtering is enabled, we need VID 0 to get untagged 670 * traffic. It is added automatically if 8021q module is loaded, 671 * but we can't rely on it since module may be not loaded. 672 */ 673 rc = efx_ef10_add_vlan(efx, 0); 674 if (rc) 675 goto fail_add_vid_0; 676 677 if (nic_data->datapath_caps & 678 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) && 679 efx->mcdi->fn_flags & 680 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) 681 efx->net_dev->udp_tunnel_nic_info = &efx_ef10_udp_tunnels; 682 683 return 0; 684 685 fail_add_vid_0: 686 efx_ef10_cleanup_vlans(efx); 687 fail_add_vid_unspec: 688 mutex_destroy(&nic_data->vlan_lock); 689 efx_ptp_remove(efx); 690 efx_mcdi_mon_remove(efx); 691 fail5: 692 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 693 fail4: 694 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 695 fail3: 696 efx_mcdi_detach(efx); 697 698 mutex_lock(&nic_data->udp_tunnels_lock); 699 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 700 (void)efx_ef10_set_udp_tnl_ports(efx, true); 701 mutex_unlock(&nic_data->udp_tunnels_lock); 702 mutex_destroy(&nic_data->udp_tunnels_lock); 703 704 efx_mcdi_fini(efx); 705 fail2: 706 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 707 fail1: 708 kfree(nic_data); 709 efx->nic_data = NULL; 710 return rc; 711 } 712 713 #ifdef EFX_USE_PIO 714 715 static void efx_ef10_free_piobufs(struct efx_nic *efx) 716 { 717 struct efx_ef10_nic_data *nic_data = efx->nic_data; 718 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 719 unsigned int i; 720 int rc; 721 722 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 723 724 for (i = 0; i < nic_data->n_piobufs; i++) { 725 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 726 nic_data->piobuf_handle[i]); 727 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 728 NULL, 0, NULL); 729 WARN_ON(rc); 730 } 731 732 nic_data->n_piobufs = 0; 733 } 734 735 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 736 { 737 struct efx_ef10_nic_data *nic_data = efx->nic_data; 738 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 739 unsigned int i; 740 size_t outlen; 741 int rc = 0; 742 743 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 744 745 for (i = 0; i < n; i++) { 746 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 747 outbuf, sizeof(outbuf), &outlen); 748 if (rc) { 749 /* Don't display the MC error if we didn't have space 750 * for a VF. 751 */ 752 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC)) 753 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF, 754 0, outbuf, outlen, rc); 755 break; 756 } 757 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 758 rc = -EIO; 759 break; 760 } 761 nic_data->piobuf_handle[i] = 762 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 763 netif_dbg(efx, probe, efx->net_dev, 764 "allocated PIO buffer %u handle %x\n", i, 765 nic_data->piobuf_handle[i]); 766 } 767 768 nic_data->n_piobufs = i; 769 if (rc) 770 efx_ef10_free_piobufs(efx); 771 return rc; 772 } 773 774 static int efx_ef10_link_piobufs(struct efx_nic *efx) 775 { 776 struct efx_ef10_nic_data *nic_data = efx->nic_data; 777 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN); 778 struct efx_channel *channel; 779 struct efx_tx_queue *tx_queue; 780 unsigned int offset, index; 781 int rc; 782 783 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 784 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 785 786 /* Link a buffer to each VI in the write-combining mapping */ 787 for (index = 0; index < nic_data->n_piobufs; ++index) { 788 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 789 nic_data->piobuf_handle[index]); 790 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 791 nic_data->pio_write_vi_base + index); 792 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 793 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 794 NULL, 0, NULL); 795 if (rc) { 796 netif_err(efx, drv, efx->net_dev, 797 "failed to link VI %u to PIO buffer %u (%d)\n", 798 nic_data->pio_write_vi_base + index, index, 799 rc); 800 goto fail; 801 } 802 netif_dbg(efx, probe, efx->net_dev, 803 "linked VI %u to PIO buffer %u\n", 804 nic_data->pio_write_vi_base + index, index); 805 } 806 807 /* Link a buffer to each TX queue */ 808 efx_for_each_channel(channel, efx) { 809 /* Extra channels, even those with TXQs (PTP), do not require 810 * PIO resources. 811 */ 812 if (!channel->type->want_pio || 813 channel->channel >= efx->xdp_channel_offset) 814 continue; 815 816 efx_for_each_channel_tx_queue(tx_queue, channel) { 817 /* We assign the PIO buffers to queues in 818 * reverse order to allow for the following 819 * special case. 820 */ 821 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 822 tx_queue->channel->channel - 1) * 823 efx_piobuf_size); 824 index = offset / nic_data->piobuf_size; 825 offset = offset % nic_data->piobuf_size; 826 827 /* When the host page size is 4K, the first 828 * host page in the WC mapping may be within 829 * the same VI page as the last TX queue. We 830 * can only link one buffer to each VI. 831 */ 832 if (tx_queue->queue == nic_data->pio_write_vi_base) { 833 BUG_ON(index != 0); 834 rc = 0; 835 } else { 836 MCDI_SET_DWORD(inbuf, 837 LINK_PIOBUF_IN_PIOBUF_HANDLE, 838 nic_data->piobuf_handle[index]); 839 MCDI_SET_DWORD(inbuf, 840 LINK_PIOBUF_IN_TXQ_INSTANCE, 841 tx_queue->queue); 842 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 843 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 844 NULL, 0, NULL); 845 } 846 847 if (rc) { 848 /* This is non-fatal; the TX path just 849 * won't use PIO for this queue 850 */ 851 netif_err(efx, drv, efx->net_dev, 852 "failed to link VI %u to PIO buffer %u (%d)\n", 853 tx_queue->queue, index, rc); 854 tx_queue->piobuf = NULL; 855 } else { 856 tx_queue->piobuf = 857 nic_data->pio_write_base + 858 index * efx->vi_stride + offset; 859 tx_queue->piobuf_offset = offset; 860 netif_dbg(efx, probe, efx->net_dev, 861 "linked VI %u to PIO buffer %u offset %x addr %p\n", 862 tx_queue->queue, index, 863 tx_queue->piobuf_offset, 864 tx_queue->piobuf); 865 } 866 } 867 } 868 869 return 0; 870 871 fail: 872 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same 873 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter. 874 */ 875 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN); 876 while (index--) { 877 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 878 nic_data->pio_write_vi_base + index); 879 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 880 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 881 NULL, 0, NULL); 882 } 883 return rc; 884 } 885 886 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 887 { 888 struct efx_channel *channel; 889 struct efx_tx_queue *tx_queue; 890 891 /* All our existing PIO buffers went away */ 892 efx_for_each_channel(channel, efx) 893 efx_for_each_channel_tx_queue(tx_queue, channel) 894 tx_queue->piobuf = NULL; 895 } 896 897 #else /* !EFX_USE_PIO */ 898 899 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 900 { 901 return n == 0 ? 0 : -ENOBUFS; 902 } 903 904 static int efx_ef10_link_piobufs(struct efx_nic *efx) 905 { 906 return 0; 907 } 908 909 static void efx_ef10_free_piobufs(struct efx_nic *efx) 910 { 911 } 912 913 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 914 { 915 } 916 917 #endif /* EFX_USE_PIO */ 918 919 static void efx_ef10_remove(struct efx_nic *efx) 920 { 921 struct efx_ef10_nic_data *nic_data = efx->nic_data; 922 int rc; 923 924 #ifdef CONFIG_SFC_SRIOV 925 struct efx_ef10_nic_data *nic_data_pf; 926 struct pci_dev *pci_dev_pf; 927 struct efx_nic *efx_pf; 928 struct ef10_vf *vf; 929 930 if (efx->pci_dev->is_virtfn) { 931 pci_dev_pf = efx->pci_dev->physfn; 932 if (pci_dev_pf) { 933 efx_pf = pci_get_drvdata(pci_dev_pf); 934 nic_data_pf = efx_pf->nic_data; 935 vf = nic_data_pf->vf + nic_data->vf_index; 936 vf->efx = NULL; 937 } else 938 netif_info(efx, drv, efx->net_dev, 939 "Could not get the PF id from VF\n"); 940 } 941 #endif 942 943 efx_ef10_cleanup_vlans(efx); 944 mutex_destroy(&nic_data->vlan_lock); 945 946 efx_ptp_remove(efx); 947 948 efx_mcdi_mon_remove(efx); 949 950 efx_mcdi_rx_free_indir_table(efx); 951 952 if (nic_data->wc_membase) 953 iounmap(nic_data->wc_membase); 954 955 rc = efx_mcdi_free_vis(efx); 956 WARN_ON(rc != 0); 957 958 if (!nic_data->must_restore_piobufs) 959 efx_ef10_free_piobufs(efx); 960 961 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 962 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 963 964 efx_mcdi_detach(efx); 965 966 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 967 mutex_lock(&nic_data->udp_tunnels_lock); 968 (void)efx_ef10_set_udp_tnl_ports(efx, true); 969 mutex_unlock(&nic_data->udp_tunnels_lock); 970 971 mutex_destroy(&nic_data->udp_tunnels_lock); 972 973 efx_mcdi_fini(efx); 974 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 975 kfree(nic_data); 976 } 977 978 static int efx_ef10_probe_pf(struct efx_nic *efx) 979 { 980 return efx_ef10_probe(efx); 981 } 982 983 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id, 984 u32 *port_flags, u32 *vadaptor_flags, 985 unsigned int *vlan_tags) 986 { 987 struct efx_ef10_nic_data *nic_data = efx->nic_data; 988 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN); 989 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN); 990 size_t outlen; 991 int rc; 992 993 if (nic_data->datapath_caps & 994 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) { 995 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID, 996 port_id); 997 998 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf), 999 outbuf, sizeof(outbuf), &outlen); 1000 if (rc) 1001 return rc; 1002 1003 if (outlen < sizeof(outbuf)) { 1004 rc = -EIO; 1005 return rc; 1006 } 1007 } 1008 1009 if (port_flags) 1010 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS); 1011 if (vadaptor_flags) 1012 *vadaptor_flags = 1013 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS); 1014 if (vlan_tags) 1015 *vlan_tags = 1016 MCDI_DWORD(outbuf, 1017 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS); 1018 1019 return 0; 1020 } 1021 1022 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 1023 { 1024 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 1025 1026 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 1027 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 1028 NULL, 0, NULL); 1029 } 1030 1031 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 1032 { 1033 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 1034 1035 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 1036 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 1037 NULL, 0, NULL); 1038 } 1039 1040 int efx_ef10_vport_add_mac(struct efx_nic *efx, 1041 unsigned int port_id, u8 *mac) 1042 { 1043 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 1044 1045 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 1046 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 1047 1048 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 1049 sizeof(inbuf), NULL, 0, NULL); 1050 } 1051 1052 int efx_ef10_vport_del_mac(struct efx_nic *efx, 1053 unsigned int port_id, u8 *mac) 1054 { 1055 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 1056 1057 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 1058 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 1059 1060 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 1061 sizeof(inbuf), NULL, 0, NULL); 1062 } 1063 1064 #ifdef CONFIG_SFC_SRIOV 1065 static int efx_ef10_probe_vf(struct efx_nic *efx) 1066 { 1067 int rc; 1068 struct pci_dev *pci_dev_pf; 1069 1070 /* If the parent PF has no VF data structure, it doesn't know about this 1071 * VF so fail probe. The VF needs to be re-created. This can happen 1072 * if the PF driver is unloaded while the VF is assigned to a guest. 1073 */ 1074 pci_dev_pf = efx->pci_dev->physfn; 1075 if (pci_dev_pf) { 1076 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 1077 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 1078 1079 if (!nic_data_pf->vf) { 1080 netif_info(efx, drv, efx->net_dev, 1081 "The VF cannot link to its parent PF; " 1082 "please destroy and re-create the VF\n"); 1083 return -EBUSY; 1084 } 1085 } 1086 1087 rc = efx_ef10_probe(efx); 1088 if (rc) 1089 return rc; 1090 1091 rc = efx_ef10_get_vf_index(efx); 1092 if (rc) 1093 goto fail; 1094 1095 if (efx->pci_dev->is_virtfn) { 1096 if (efx->pci_dev->physfn) { 1097 struct efx_nic *efx_pf = 1098 pci_get_drvdata(efx->pci_dev->physfn); 1099 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 1100 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1101 1102 nic_data_p->vf[nic_data->vf_index].efx = efx; 1103 nic_data_p->vf[nic_data->vf_index].pci_dev = 1104 efx->pci_dev; 1105 } else 1106 netif_info(efx, drv, efx->net_dev, 1107 "Could not get the PF id from VF\n"); 1108 } 1109 1110 return 0; 1111 1112 fail: 1113 efx_ef10_remove(efx); 1114 return rc; 1115 } 1116 #else 1117 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 1118 { 1119 return 0; 1120 } 1121 #endif 1122 1123 static int efx_ef10_alloc_vis(struct efx_nic *efx, 1124 unsigned int min_vis, unsigned int max_vis) 1125 { 1126 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1127 1128 return efx_mcdi_alloc_vis(efx, min_vis, max_vis, &nic_data->vi_base, 1129 &nic_data->n_allocated_vis); 1130 } 1131 1132 /* Note that the failure path of this function does not free 1133 * resources, as this will be done by efx_ef10_remove(). 1134 */ 1135 static int efx_ef10_dimension_resources(struct efx_nic *efx) 1136 { 1137 unsigned int min_vis = max_t(unsigned int, efx->tx_queues_per_channel, 1138 efx_separate_tx_channels ? 2 : 1); 1139 unsigned int channel_vis, pio_write_vi_base, max_vis; 1140 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1141 unsigned int uc_mem_map_size, wc_mem_map_size; 1142 void __iomem *membase; 1143 int rc; 1144 1145 channel_vis = max(efx->n_channels, 1146 ((efx->n_tx_channels + efx->n_extra_tx_channels) * 1147 efx->tx_queues_per_channel) + 1148 efx->n_xdp_channels * efx->xdp_tx_per_channel); 1149 if (efx->max_vis && efx->max_vis < channel_vis) { 1150 netif_dbg(efx, drv, efx->net_dev, 1151 "Reducing channel VIs from %u to %u\n", 1152 channel_vis, efx->max_vis); 1153 channel_vis = efx->max_vis; 1154 } 1155 1156 #ifdef EFX_USE_PIO 1157 /* Try to allocate PIO buffers if wanted and if the full 1158 * number of PIO buffers would be sufficient to allocate one 1159 * copy-buffer per TX channel. Failure is non-fatal, as there 1160 * are only a small number of PIO buffers shared between all 1161 * functions of the controller. 1162 */ 1163 if (efx_piobuf_size != 0 && 1164 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 1165 efx->n_tx_channels) { 1166 unsigned int n_piobufs = 1167 DIV_ROUND_UP(efx->n_tx_channels, 1168 nic_data->piobuf_size / efx_piobuf_size); 1169 1170 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 1171 if (rc == -ENOSPC) 1172 netif_dbg(efx, probe, efx->net_dev, 1173 "out of PIO buffers; cannot allocate more\n"); 1174 else if (rc == -EPERM) 1175 netif_dbg(efx, probe, efx->net_dev, 1176 "not permitted to allocate PIO buffers\n"); 1177 else if (rc) 1178 netif_err(efx, probe, efx->net_dev, 1179 "failed to allocate PIO buffers (%d)\n", rc); 1180 else 1181 netif_dbg(efx, probe, efx->net_dev, 1182 "allocated %u PIO buffers\n", n_piobufs); 1183 } 1184 #else 1185 nic_data->n_piobufs = 0; 1186 #endif 1187 1188 /* PIO buffers should be mapped with write-combining enabled, 1189 * and we want to make single UC and WC mappings rather than 1190 * several of each (in fact that's the only option if host 1191 * page size is >4K). So we may allocate some extra VIs just 1192 * for writing PIO buffers through. 1193 * 1194 * The UC mapping contains (channel_vis - 1) complete VIs and the 1195 * first 4K of the next VI. Then the WC mapping begins with 1196 * the remainder of this last VI. 1197 */ 1198 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride + 1199 ER_DZ_TX_PIOBUF); 1200 if (nic_data->n_piobufs) { 1201 /* pio_write_vi_base rounds down to give the number of complete 1202 * VIs inside the UC mapping. 1203 */ 1204 pio_write_vi_base = uc_mem_map_size / efx->vi_stride; 1205 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 1206 nic_data->n_piobufs) * 1207 efx->vi_stride) - 1208 uc_mem_map_size); 1209 max_vis = pio_write_vi_base + nic_data->n_piobufs; 1210 } else { 1211 pio_write_vi_base = 0; 1212 wc_mem_map_size = 0; 1213 max_vis = channel_vis; 1214 } 1215 1216 /* In case the last attached driver failed to free VIs, do it now */ 1217 rc = efx_mcdi_free_vis(efx); 1218 if (rc != 0) 1219 return rc; 1220 1221 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 1222 if (rc != 0) 1223 return rc; 1224 1225 if (nic_data->n_allocated_vis < channel_vis) { 1226 netif_info(efx, drv, efx->net_dev, 1227 "Could not allocate enough VIs to satisfy RSS" 1228 " requirements. Performance may not be optimal.\n"); 1229 /* We didn't get the VIs to populate our channels. 1230 * We could keep what we got but then we'd have more 1231 * interrupts than we need. 1232 * Instead calculate new max_channels and restart 1233 */ 1234 efx->max_channels = nic_data->n_allocated_vis; 1235 efx->max_tx_channels = 1236 nic_data->n_allocated_vis / efx->tx_queues_per_channel; 1237 1238 efx_mcdi_free_vis(efx); 1239 return -EAGAIN; 1240 } 1241 1242 /* If we didn't get enough VIs to map all the PIO buffers, free the 1243 * PIO buffers 1244 */ 1245 if (nic_data->n_piobufs && 1246 nic_data->n_allocated_vis < 1247 pio_write_vi_base + nic_data->n_piobufs) { 1248 netif_dbg(efx, probe, efx->net_dev, 1249 "%u VIs are not sufficient to map %u PIO buffers\n", 1250 nic_data->n_allocated_vis, nic_data->n_piobufs); 1251 efx_ef10_free_piobufs(efx); 1252 } 1253 1254 /* Shrink the original UC mapping of the memory BAR */ 1255 membase = ioremap(efx->membase_phys, uc_mem_map_size); 1256 if (!membase) { 1257 netif_err(efx, probe, efx->net_dev, 1258 "could not shrink memory BAR to %x\n", 1259 uc_mem_map_size); 1260 return -ENOMEM; 1261 } 1262 iounmap(efx->membase); 1263 efx->membase = membase; 1264 1265 /* Set up the WC mapping if needed */ 1266 if (wc_mem_map_size) { 1267 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 1268 uc_mem_map_size, 1269 wc_mem_map_size); 1270 if (!nic_data->wc_membase) { 1271 netif_err(efx, probe, efx->net_dev, 1272 "could not allocate WC mapping of size %x\n", 1273 wc_mem_map_size); 1274 return -ENOMEM; 1275 } 1276 nic_data->pio_write_vi_base = pio_write_vi_base; 1277 nic_data->pio_write_base = 1278 nic_data->wc_membase + 1279 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF - 1280 uc_mem_map_size); 1281 1282 rc = efx_ef10_link_piobufs(efx); 1283 if (rc) 1284 efx_ef10_free_piobufs(efx); 1285 } 1286 1287 netif_dbg(efx, probe, efx->net_dev, 1288 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 1289 &efx->membase_phys, efx->membase, uc_mem_map_size, 1290 nic_data->wc_membase, wc_mem_map_size); 1291 1292 return 0; 1293 } 1294 1295 static void efx_ef10_fini_nic(struct efx_nic *efx) 1296 { 1297 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1298 1299 kfree(nic_data->mc_stats); 1300 nic_data->mc_stats = NULL; 1301 } 1302 1303 static int efx_ef10_init_nic(struct efx_nic *efx) 1304 { 1305 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1306 netdev_features_t hw_enc_features = 0; 1307 int rc; 1308 1309 if (nic_data->must_check_datapath_caps) { 1310 rc = efx_ef10_init_datapath_caps(efx); 1311 if (rc) 1312 return rc; 1313 nic_data->must_check_datapath_caps = false; 1314 } 1315 1316 if (efx->must_realloc_vis) { 1317 /* We cannot let the number of VIs change now */ 1318 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 1319 nic_data->n_allocated_vis); 1320 if (rc) 1321 return rc; 1322 efx->must_realloc_vis = false; 1323 } 1324 1325 nic_data->mc_stats = kmalloc(efx->num_mac_stats * sizeof(__le64), 1326 GFP_KERNEL); 1327 if (!nic_data->mc_stats) 1328 return -ENOMEM; 1329 1330 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 1331 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 1332 if (rc == 0) { 1333 rc = efx_ef10_link_piobufs(efx); 1334 if (rc) 1335 efx_ef10_free_piobufs(efx); 1336 } 1337 1338 /* Log an error on failure, but this is non-fatal. 1339 * Permission errors are less important - we've presumably 1340 * had the PIO buffer licence removed. 1341 */ 1342 if (rc == -EPERM) 1343 netif_dbg(efx, drv, efx->net_dev, 1344 "not permitted to restore PIO buffers\n"); 1345 else if (rc) 1346 netif_err(efx, drv, efx->net_dev, 1347 "failed to restore PIO buffers (%d)\n", rc); 1348 nic_data->must_restore_piobufs = false; 1349 } 1350 1351 /* add encapsulated checksum offload features */ 1352 if (efx_has_cap(efx, VXLAN_NVGRE) && !efx_ef10_is_vf(efx)) 1353 hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1354 /* add encapsulated TSO features */ 1355 if (efx_has_cap(efx, TX_TSO_V2_ENCAP)) { 1356 netdev_features_t encap_tso_features; 1357 1358 encap_tso_features = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 1359 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM; 1360 1361 hw_enc_features |= encap_tso_features | NETIF_F_TSO; 1362 efx->net_dev->features |= encap_tso_features; 1363 } 1364 efx->net_dev->hw_enc_features = hw_enc_features; 1365 1366 /* don't fail init if RSS setup doesn't work */ 1367 rc = efx->type->rx_push_rss_config(efx, false, 1368 efx->rss_context.rx_indir_table, NULL); 1369 1370 return 0; 1371 } 1372 1373 static void efx_ef10_table_reset_mc_allocations(struct efx_nic *efx) 1374 { 1375 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1376 #ifdef CONFIG_SFC_SRIOV 1377 unsigned int i; 1378 #endif 1379 1380 /* All our allocations have been reset */ 1381 efx->must_realloc_vis = true; 1382 efx_mcdi_filter_table_reset_mc_allocations(efx); 1383 nic_data->must_restore_piobufs = true; 1384 efx_ef10_forget_old_piobufs(efx); 1385 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID; 1386 1387 /* Driver-created vswitches and vports must be re-created */ 1388 nic_data->must_probe_vswitching = true; 1389 efx->vport_id = EVB_PORT_ID_ASSIGNED; 1390 #ifdef CONFIG_SFC_SRIOV 1391 if (nic_data->vf) 1392 for (i = 0; i < efx->vf_count; i++) 1393 nic_data->vf[i].vport_id = 0; 1394 #endif 1395 } 1396 1397 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1398 { 1399 if (reason == RESET_TYPE_MC_FAILURE) 1400 return RESET_TYPE_DATAPATH; 1401 1402 return efx_mcdi_map_reset_reason(reason); 1403 } 1404 1405 static int efx_ef10_map_reset_flags(u32 *flags) 1406 { 1407 enum { 1408 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1409 ETH_RESET_SHARED_SHIFT), 1410 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1411 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1412 ETH_RESET_PHY | ETH_RESET_MGMT) << 1413 ETH_RESET_SHARED_SHIFT) 1414 }; 1415 1416 /* We assume for now that our PCI function is permitted to 1417 * reset everything. 1418 */ 1419 1420 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1421 *flags &= ~EF10_RESET_MC; 1422 return RESET_TYPE_WORLD; 1423 } 1424 1425 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1426 *flags &= ~EF10_RESET_PORT; 1427 return RESET_TYPE_ALL; 1428 } 1429 1430 /* no invisible reset implemented */ 1431 1432 return -EINVAL; 1433 } 1434 1435 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1436 { 1437 int rc = efx_mcdi_reset(efx, reset_type); 1438 1439 /* Unprivileged functions return -EPERM, but need to return success 1440 * here so that the datapath is brought back up. 1441 */ 1442 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1443 rc = 0; 1444 1445 /* If it was a port reset, trigger reallocation of MC resources. 1446 * Note that on an MC reset nothing needs to be done now because we'll 1447 * detect the MC reset later and handle it then. 1448 * For an FLR, we never get an MC reset event, but the MC has reset all 1449 * resources assigned to us, so we have to trigger reallocation now. 1450 */ 1451 if ((reset_type == RESET_TYPE_ALL || 1452 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1453 efx_ef10_table_reset_mc_allocations(efx); 1454 return rc; 1455 } 1456 1457 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1458 [EF10_STAT_ ## ext_name] = \ 1459 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1460 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1461 [EF10_STAT_ ## int_name] = \ 1462 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1463 #define EF10_OTHER_STAT(ext_name) \ 1464 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1465 1466 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1467 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1468 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1469 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1470 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1471 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1472 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1473 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1474 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1475 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1476 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1477 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1478 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1479 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1480 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1481 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1482 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1483 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1484 EF10_OTHER_STAT(port_rx_good_bytes), 1485 EF10_OTHER_STAT(port_rx_bad_bytes), 1486 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1487 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1488 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1489 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1490 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1491 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1492 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1493 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1494 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1495 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1496 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1497 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1498 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1499 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1500 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1501 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1502 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1503 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1504 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1505 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1506 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1507 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1508 EFX_GENERIC_SW_STAT(rx_nodesc_trunc), 1509 EFX_GENERIC_SW_STAT(rx_noskb_drops), 1510 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1511 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1512 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1513 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1514 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1515 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1516 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1517 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1518 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1519 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1520 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1521 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1522 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1523 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1524 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1525 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1526 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1527 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1528 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1529 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1530 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1531 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1532 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1533 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1534 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1535 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1536 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1537 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1538 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1539 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1540 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS), 1541 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS), 1542 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0), 1543 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1), 1544 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2), 1545 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3), 1546 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK), 1547 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS), 1548 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL), 1549 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL), 1550 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL), 1551 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL), 1552 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL), 1553 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL), 1554 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL), 1555 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK), 1556 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK), 1557 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK), 1558 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS), 1559 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK), 1560 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON), 1561 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE), 1562 }; 1563 1564 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1565 (1ULL << EF10_STAT_port_tx_packets) | \ 1566 (1ULL << EF10_STAT_port_tx_pause) | \ 1567 (1ULL << EF10_STAT_port_tx_unicast) | \ 1568 (1ULL << EF10_STAT_port_tx_multicast) | \ 1569 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1570 (1ULL << EF10_STAT_port_rx_bytes) | \ 1571 (1ULL << \ 1572 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1573 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1574 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1575 (1ULL << EF10_STAT_port_rx_packets) | \ 1576 (1ULL << EF10_STAT_port_rx_good) | \ 1577 (1ULL << EF10_STAT_port_rx_bad) | \ 1578 (1ULL << EF10_STAT_port_rx_pause) | \ 1579 (1ULL << EF10_STAT_port_rx_control) | \ 1580 (1ULL << EF10_STAT_port_rx_unicast) | \ 1581 (1ULL << EF10_STAT_port_rx_multicast) | \ 1582 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1583 (1ULL << EF10_STAT_port_rx_lt64) | \ 1584 (1ULL << EF10_STAT_port_rx_64) | \ 1585 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1586 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1587 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1588 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1589 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1590 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1591 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1592 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1593 (1ULL << EF10_STAT_port_rx_overflow) | \ 1594 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1595 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1596 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1597 1598 /* On 7000 series NICs, these statistics are only provided by the 10G MAC. 1599 * For a 10G/40G switchable port we do not expose these because they might 1600 * not include all the packets they should. 1601 * On 8000 series NICs these statistics are always provided. 1602 */ 1603 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1604 (1ULL << EF10_STAT_port_tx_lt64) | \ 1605 (1ULL << EF10_STAT_port_tx_64) | \ 1606 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1607 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1608 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1609 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1610 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1611 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1612 1613 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1614 * switchable port we do expose these because the errors will otherwise 1615 * be silent. 1616 */ 1617 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1618 (1ULL << EF10_STAT_port_rx_length_error)) 1619 1620 /* These statistics are only provided if the firmware supports the 1621 * capability PM_AND_RXDP_COUNTERS. 1622 */ 1623 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1624 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1625 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1626 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1627 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1628 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1629 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1630 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1631 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1632 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1633 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1634 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1635 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1636 1637 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2, 1638 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in 1639 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1640 * These bits are in the second u64 of the raw mask. 1641 */ 1642 #define EF10_FEC_STAT_MASK ( \ 1643 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \ 1644 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \ 1645 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \ 1646 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \ 1647 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \ 1648 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64))) 1649 1650 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3, 1651 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in 1652 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1653 * These bits are in the second u64 of the raw mask. 1654 */ 1655 #define EF10_CTPIO_STAT_MASK ( \ 1656 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \ 1657 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \ 1658 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \ 1659 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \ 1660 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \ 1661 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \ 1662 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \ 1663 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \ 1664 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \ 1665 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \ 1666 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \ 1667 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \ 1668 (1ULL << (EF10_STAT_ctpio_success - 64)) | \ 1669 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \ 1670 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \ 1671 (1ULL << (EF10_STAT_ctpio_erase - 64))) 1672 1673 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1674 { 1675 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1676 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1677 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1678 1679 if (!(efx->mcdi->fn_flags & 1680 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1681 return 0; 1682 1683 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) { 1684 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1685 /* 8000 series have everything even at 40G */ 1686 if (nic_data->datapath_caps2 & 1687 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN)) 1688 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1689 } else { 1690 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1691 } 1692 1693 if (nic_data->datapath_caps & 1694 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1695 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1696 1697 return raw_mask; 1698 } 1699 1700 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1701 { 1702 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1703 u64 raw_mask[2]; 1704 1705 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1706 1707 /* Only show vadaptor stats when EVB capability is present */ 1708 if (nic_data->datapath_caps & 1709 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1710 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1711 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1; 1712 } else { 1713 raw_mask[1] = 0; 1714 } 1715 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */ 1716 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2) 1717 raw_mask[1] |= EF10_FEC_STAT_MASK; 1718 1719 /* CTPIO stats appear in V3. Only show them on devices that actually 1720 * support CTPIO. Although this driver doesn't use CTPIO others might, 1721 * and we may be reporting the stats for the underlying port. 1722 */ 1723 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 && 1724 (nic_data->datapath_caps2 & 1725 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN))) 1726 raw_mask[1] |= EF10_CTPIO_STAT_MASK; 1727 1728 #if BITS_PER_LONG == 64 1729 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2); 1730 mask[0] = raw_mask[0]; 1731 mask[1] = raw_mask[1]; 1732 #else 1733 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3); 1734 mask[0] = raw_mask[0] & 0xffffffff; 1735 mask[1] = raw_mask[0] >> 32; 1736 mask[2] = raw_mask[1] & 0xffffffff; 1737 #endif 1738 } 1739 1740 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1741 { 1742 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1743 1744 efx_ef10_get_stat_mask(efx, mask); 1745 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1746 mask, names); 1747 } 1748 1749 static void efx_ef10_get_fec_stats(struct efx_nic *efx, 1750 struct ethtool_fec_stats *fec_stats) 1751 { 1752 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1753 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1754 u64 *stats = nic_data->stats; 1755 1756 efx_ef10_get_stat_mask(efx, mask); 1757 if (test_bit(EF10_STAT_fec_corrected_errors, mask)) 1758 fec_stats->corrected_blocks.total = 1759 stats[EF10_STAT_fec_corrected_errors]; 1760 if (test_bit(EF10_STAT_fec_uncorrected_errors, mask)) 1761 fec_stats->uncorrectable_blocks.total = 1762 stats[EF10_STAT_fec_uncorrected_errors]; 1763 } 1764 1765 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1766 struct rtnl_link_stats64 *core_stats) 1767 { 1768 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1769 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1770 u64 *stats = nic_data->stats; 1771 size_t stats_count = 0, index; 1772 1773 efx_ef10_get_stat_mask(efx, mask); 1774 1775 if (full_stats) { 1776 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1777 if (efx_ef10_stat_desc[index].name) { 1778 *full_stats++ = stats[index]; 1779 ++stats_count; 1780 } 1781 } 1782 } 1783 1784 if (!core_stats) 1785 return stats_count; 1786 1787 if (nic_data->datapath_caps & 1788 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1789 /* Use vadaptor stats. */ 1790 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1791 stats[EF10_STAT_rx_multicast] + 1792 stats[EF10_STAT_rx_broadcast]; 1793 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1794 stats[EF10_STAT_tx_multicast] + 1795 stats[EF10_STAT_tx_broadcast]; 1796 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1797 stats[EF10_STAT_rx_multicast_bytes] + 1798 stats[EF10_STAT_rx_broadcast_bytes]; 1799 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1800 stats[EF10_STAT_tx_multicast_bytes] + 1801 stats[EF10_STAT_tx_broadcast_bytes]; 1802 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1803 stats[GENERIC_STAT_rx_noskb_drops]; 1804 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1805 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1806 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1807 core_stats->rx_errors = core_stats->rx_crc_errors; 1808 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1809 } else { 1810 /* Use port stats. */ 1811 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1812 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1813 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1814 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1815 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1816 stats[GENERIC_STAT_rx_nodesc_trunc] + 1817 stats[GENERIC_STAT_rx_noskb_drops]; 1818 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1819 core_stats->rx_length_errors = 1820 stats[EF10_STAT_port_rx_gtjumbo] + 1821 stats[EF10_STAT_port_rx_length_error]; 1822 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1823 core_stats->rx_frame_errors = 1824 stats[EF10_STAT_port_rx_align_error]; 1825 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1826 core_stats->rx_errors = (core_stats->rx_length_errors + 1827 core_stats->rx_crc_errors + 1828 core_stats->rx_frame_errors); 1829 } 1830 1831 return stats_count; 1832 } 1833 1834 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1835 struct rtnl_link_stats64 *core_stats) 1836 { 1837 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1838 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1839 u64 *stats = nic_data->stats; 1840 1841 efx_ef10_get_stat_mask(efx, mask); 1842 1843 efx_nic_copy_stats(efx, nic_data->mc_stats); 1844 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1845 mask, stats, nic_data->mc_stats, false); 1846 1847 /* Update derived statistics */ 1848 efx_nic_fix_nodesc_drop_stat(efx, 1849 &stats[EF10_STAT_port_rx_nodesc_drops]); 1850 /* MC Firmware reads RX_BYTES and RX_GOOD_BYTES from the MAC. 1851 * It then calculates RX_BAD_BYTES and DMAs it to us with RX_BYTES. 1852 * We report these as port_rx_ stats. We are not given RX_GOOD_BYTES. 1853 * Here we calculate port_rx_good_bytes. 1854 */ 1855 stats[EF10_STAT_port_rx_good_bytes] = 1856 stats[EF10_STAT_port_rx_bytes] - 1857 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1858 1859 /* The asynchronous reads used to calculate RX_BAD_BYTES in 1860 * MC Firmware are done such that we should not see an increase in 1861 * RX_BAD_BYTES when a good packet has arrived. Unfortunately this 1862 * does mean that the stat can decrease at times. Here we do not 1863 * update the stat unless it has increased or has gone to zero 1864 * (In the case of the NIC rebooting). 1865 * Please see Bug 33781 for a discussion of why things work this way. 1866 */ 1867 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1868 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1869 efx_update_sw_stats(efx, stats); 1870 1871 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1872 } 1873 1874 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1875 __must_hold(&efx->stats_lock) 1876 { 1877 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1878 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1879 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1880 __le64 generation_start, generation_end; 1881 u64 *stats = nic_data->stats; 1882 u32 dma_len = efx->num_mac_stats * sizeof(u64); 1883 struct efx_buffer stats_buf; 1884 __le64 *dma_stats; 1885 int rc; 1886 1887 spin_unlock_bh(&efx->stats_lock); 1888 1889 efx_ef10_get_stat_mask(efx, mask); 1890 1891 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_KERNEL); 1892 if (rc) { 1893 spin_lock_bh(&efx->stats_lock); 1894 return rc; 1895 } 1896 1897 dma_stats = stats_buf.addr; 1898 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID; 1899 1900 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1901 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1902 MAC_STATS_IN_DMA, 1); 1903 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1904 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1905 1906 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1907 NULL, 0, NULL); 1908 spin_lock_bh(&efx->stats_lock); 1909 if (rc) { 1910 /* Expect ENOENT if DMA queues have not been set up */ 1911 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1912 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1913 sizeof(inbuf), NULL, 0, rc); 1914 goto out; 1915 } 1916 1917 generation_end = dma_stats[efx->num_mac_stats - 1]; 1918 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1919 WARN_ON_ONCE(1); 1920 goto out; 1921 } 1922 rmb(); 1923 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1924 stats, stats_buf.addr, false); 1925 rmb(); 1926 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1927 if (generation_end != generation_start) { 1928 rc = -EAGAIN; 1929 goto out; 1930 } 1931 1932 efx_update_sw_stats(efx, stats); 1933 out: 1934 efx_nic_free_buffer(efx, &stats_buf); 1935 return rc; 1936 } 1937 1938 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1939 struct rtnl_link_stats64 *core_stats) 1940 { 1941 if (efx_ef10_try_update_nic_stats_vf(efx)) 1942 return 0; 1943 1944 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1945 } 1946 1947 static size_t efx_ef10_update_stats_atomic_vf(struct efx_nic *efx, u64 *full_stats, 1948 struct rtnl_link_stats64 *core_stats) 1949 { 1950 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1951 1952 /* In atomic context, cannot update HW stats. Just update the 1953 * software stats and return so the caller can continue. 1954 */ 1955 efx_update_sw_stats(efx, nic_data->stats); 1956 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1957 } 1958 1959 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1960 { 1961 struct efx_nic *efx = channel->efx; 1962 unsigned int mode, usecs; 1963 efx_dword_t timer_cmd; 1964 1965 if (channel->irq_moderation_us) { 1966 mode = 3; 1967 usecs = channel->irq_moderation_us; 1968 } else { 1969 mode = 0; 1970 usecs = 0; 1971 } 1972 1973 if (EFX_EF10_WORKAROUND_61265(efx)) { 1974 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN); 1975 unsigned int ns = usecs * 1000; 1976 1977 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE, 1978 channel->channel); 1979 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns); 1980 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns); 1981 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode); 1982 1983 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR, 1984 inbuf, sizeof(inbuf), 0, NULL, 0); 1985 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 1986 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1987 1988 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1989 EFE_DD_EVQ_IND_TIMER_FLAGS, 1990 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1991 ERF_DD_EVQ_IND_TIMER_VAL, ticks); 1992 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1993 channel->channel); 1994 } else { 1995 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1996 1997 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1998 ERF_DZ_TC_TIMER_VAL, ticks, 1999 ERF_FZ_TC_TMR_REL_VAL, ticks); 2000 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 2001 channel->channel); 2002 } 2003 } 2004 2005 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 2006 struct ethtool_wolinfo *wol) {} 2007 2008 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 2009 { 2010 return -EOPNOTSUPP; 2011 } 2012 2013 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 2014 { 2015 wol->supported = 0; 2016 wol->wolopts = 0; 2017 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2018 } 2019 2020 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 2021 { 2022 if (type != 0) 2023 return -EINVAL; 2024 return 0; 2025 } 2026 2027 static void efx_ef10_mcdi_request(struct efx_nic *efx, 2028 const efx_dword_t *hdr, size_t hdr_len, 2029 const efx_dword_t *sdu, size_t sdu_len) 2030 { 2031 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2032 u8 *pdu = nic_data->mcdi_buf.addr; 2033 2034 memcpy(pdu, hdr, hdr_len); 2035 memcpy(pdu + hdr_len, sdu, sdu_len); 2036 wmb(); 2037 2038 /* The hardware provides 'low' and 'high' (doorbell) registers 2039 * for passing the 64-bit address of an MCDI request to 2040 * firmware. However the dwords are swapped by firmware. The 2041 * least significant bits of the doorbell are then 0 for all 2042 * MCDI requests due to alignment. 2043 */ 2044 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 2045 ER_DZ_MC_DB_LWRD); 2046 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 2047 ER_DZ_MC_DB_HWRD); 2048 } 2049 2050 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 2051 { 2052 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2053 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 2054 2055 rmb(); 2056 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 2057 } 2058 2059 static void 2060 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 2061 size_t offset, size_t outlen) 2062 { 2063 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2064 const u8 *pdu = nic_data->mcdi_buf.addr; 2065 2066 memcpy(outbuf, pdu + offset, outlen); 2067 } 2068 2069 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 2070 { 2071 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2072 2073 /* All our allocations have been reset */ 2074 efx_ef10_table_reset_mc_allocations(efx); 2075 2076 /* The datapath firmware might have been changed */ 2077 nic_data->must_check_datapath_caps = true; 2078 2079 /* MAC statistics have been cleared on the NIC; clear the local 2080 * statistic that we update with efx_update_diff_stat(). 2081 */ 2082 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 2083 } 2084 2085 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 2086 { 2087 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2088 int rc; 2089 2090 rc = efx_ef10_get_warm_boot_count(efx); 2091 if (rc < 0) { 2092 /* The firmware is presumably in the process of 2093 * rebooting. However, we are supposed to report each 2094 * reboot just once, so we must only do that once we 2095 * can read and store the updated warm boot count. 2096 */ 2097 return 0; 2098 } 2099 2100 if (rc == nic_data->warm_boot_count) 2101 return 0; 2102 2103 nic_data->warm_boot_count = rc; 2104 efx_ef10_mcdi_reboot_detected(efx); 2105 2106 return -EIO; 2107 } 2108 2109 /* Handle an MSI interrupt 2110 * 2111 * Handle an MSI hardware interrupt. This routine schedules event 2112 * queue processing. No interrupt acknowledgement cycle is necessary. 2113 * Also, we never need to check that the interrupt is for us, since 2114 * MSI interrupts cannot be shared. 2115 */ 2116 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 2117 { 2118 struct efx_msi_context *context = dev_id; 2119 struct efx_nic *efx = context->efx; 2120 2121 netif_vdbg(efx, intr, efx->net_dev, 2122 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 2123 2124 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 2125 /* Note test interrupts */ 2126 if (context->index == efx->irq_level) 2127 efx->last_irq_cpu = raw_smp_processor_id(); 2128 2129 /* Schedule processing of the channel */ 2130 efx_schedule_channel_irq(efx->channel[context->index]); 2131 } 2132 2133 return IRQ_HANDLED; 2134 } 2135 2136 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 2137 { 2138 struct efx_nic *efx = dev_id; 2139 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled); 2140 struct efx_channel *channel; 2141 efx_dword_t reg; 2142 u32 queues; 2143 2144 /* Read the ISR which also ACKs the interrupts */ 2145 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 2146 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 2147 2148 if (queues == 0) 2149 return IRQ_NONE; 2150 2151 if (likely(soft_enabled)) { 2152 /* Note test interrupts */ 2153 if (queues & (1U << efx->irq_level)) 2154 efx->last_irq_cpu = raw_smp_processor_id(); 2155 2156 efx_for_each_channel(channel, efx) { 2157 if (queues & 1) 2158 efx_schedule_channel_irq(channel); 2159 queues >>= 1; 2160 } 2161 } 2162 2163 netif_vdbg(efx, intr, efx->net_dev, 2164 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 2165 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 2166 2167 return IRQ_HANDLED; 2168 } 2169 2170 static int efx_ef10_irq_test_generate(struct efx_nic *efx) 2171 { 2172 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 2173 2174 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true, 2175 NULL) == 0) 2176 return -ENOTSUPP; 2177 2178 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 2179 2180 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 2181 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 2182 inbuf, sizeof(inbuf), NULL, 0, NULL); 2183 } 2184 2185 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 2186 { 2187 /* low two bits of label are what we want for type */ 2188 BUILD_BUG_ON((EFX_TXQ_TYPE_OUTER_CSUM | EFX_TXQ_TYPE_INNER_CSUM) != 3); 2189 tx_queue->type = tx_queue->label & 3; 2190 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 2191 (tx_queue->ptr_mask + 1) * 2192 sizeof(efx_qword_t), 2193 GFP_KERNEL); 2194 } 2195 2196 /* This writes to the TX_DESC_WPTR and also pushes data */ 2197 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 2198 const efx_qword_t *txd) 2199 { 2200 unsigned int write_ptr; 2201 efx_oword_t reg; 2202 2203 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2204 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 2205 reg.qword[0] = *txd; 2206 efx_writeo_page(tx_queue->efx, ®, 2207 ER_DZ_TX_DESC_UPD, tx_queue->queue); 2208 } 2209 2210 /* Add Firmware-Assisted TSO v2 option descriptors to a queue. 2211 */ 2212 int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 2213 bool *data_mapped) 2214 { 2215 struct efx_tx_buffer *buffer; 2216 u16 inner_ipv4_id = 0; 2217 u16 outer_ipv4_id = 0; 2218 struct tcphdr *tcp; 2219 struct iphdr *ip; 2220 u16 ip_tot_len; 2221 u32 seqnum; 2222 u32 mss; 2223 2224 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2); 2225 2226 mss = skb_shinfo(skb)->gso_size; 2227 2228 if (unlikely(mss < 4)) { 2229 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss); 2230 return -EINVAL; 2231 } 2232 2233 if (skb->encapsulation) { 2234 if (!tx_queue->tso_encap) 2235 return -EINVAL; 2236 ip = ip_hdr(skb); 2237 if (ip->version == 4) 2238 outer_ipv4_id = ntohs(ip->id); 2239 2240 ip = inner_ip_hdr(skb); 2241 tcp = inner_tcp_hdr(skb); 2242 } else { 2243 ip = ip_hdr(skb); 2244 tcp = tcp_hdr(skb); 2245 } 2246 2247 /* 8000-series EF10 hardware requires that IP Total Length be 2248 * greater than or equal to the value it will have in each segment 2249 * (which is at most mss + 208 + TCP header length), but also less 2250 * than (0x10000 - inner_network_header). Otherwise the TCP 2251 * checksum calculation will be broken for encapsulated packets. 2252 * We fill in ip->tot_len with 0xff30, which should satisfy the 2253 * first requirement unless the MSS is ridiculously large (which 2254 * should be impossible as the driver max MTU is 9216); it is 2255 * guaranteed to satisfy the second as we only attempt TSO if 2256 * inner_network_header <= 208. 2257 */ 2258 ip_tot_len = -EFX_TSO2_MAX_HDRLEN; 2259 EFX_WARN_ON_ONCE_PARANOID(mss + EFX_TSO2_MAX_HDRLEN + 2260 (tcp->doff << 2u) > ip_tot_len); 2261 2262 if (ip->version == 4) { 2263 ip->tot_len = htons(ip_tot_len); 2264 ip->check = 0; 2265 inner_ipv4_id = ntohs(ip->id); 2266 } else { 2267 ((struct ipv6hdr *)ip)->payload_len = htons(ip_tot_len); 2268 } 2269 2270 seqnum = ntohl(tcp->seq); 2271 2272 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2273 2274 buffer->flags = EFX_TX_BUF_OPTION; 2275 buffer->len = 0; 2276 buffer->unmap_len = 0; 2277 EFX_POPULATE_QWORD_5(buffer->option, 2278 ESF_DZ_TX_DESC_IS_OPT, 1, 2279 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2280 ESF_DZ_TX_TSO_OPTION_TYPE, 2281 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A, 2282 ESF_DZ_TX_TSO_IP_ID, inner_ipv4_id, 2283 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum 2284 ); 2285 ++tx_queue->insert_count; 2286 2287 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2288 2289 buffer->flags = EFX_TX_BUF_OPTION; 2290 buffer->len = 0; 2291 buffer->unmap_len = 0; 2292 EFX_POPULATE_QWORD_5(buffer->option, 2293 ESF_DZ_TX_DESC_IS_OPT, 1, 2294 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2295 ESF_DZ_TX_TSO_OPTION_TYPE, 2296 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B, 2297 ESF_DZ_TX_TSO_OUTER_IPID, outer_ipv4_id, 2298 ESF_DZ_TX_TSO_TCP_MSS, mss 2299 ); 2300 ++tx_queue->insert_count; 2301 2302 return 0; 2303 } 2304 2305 static u32 efx_ef10_tso_versions(struct efx_nic *efx) 2306 { 2307 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2308 u32 tso_versions = 0; 2309 2310 if (nic_data->datapath_caps & 2311 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) 2312 tso_versions |= BIT(1); 2313 if (nic_data->datapath_caps2 & 2314 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) 2315 tso_versions |= BIT(2); 2316 return tso_versions; 2317 } 2318 2319 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 2320 { 2321 bool csum_offload = tx_queue->type & EFX_TXQ_TYPE_OUTER_CSUM; 2322 bool inner_csum = tx_queue->type & EFX_TXQ_TYPE_INNER_CSUM; 2323 struct efx_channel *channel = tx_queue->channel; 2324 struct efx_nic *efx = tx_queue->efx; 2325 struct efx_ef10_nic_data *nic_data; 2326 efx_qword_t *txd; 2327 int rc; 2328 2329 nic_data = efx->nic_data; 2330 2331 /* Only attempt to enable TX timestamping if we have the license for it, 2332 * otherwise TXQ init will fail 2333 */ 2334 if (!(nic_data->licensed_features & 2335 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) { 2336 tx_queue->timestamping = false; 2337 /* Disable sync events on this channel. */ 2338 if (efx->type->ptp_set_ts_sync_events) 2339 efx->type->ptp_set_ts_sync_events(efx, false, false); 2340 } 2341 2342 /* TSOv2 is a limited resource that can only be configured on a limited 2343 * number of queues. TSO without checksum offload is not really a thing, 2344 * so we only enable it for those queues. 2345 * TSOv2 cannot be used with Hardware timestamping, and is never needed 2346 * for XDP tx. 2347 */ 2348 if (efx_has_cap(efx, TX_TSO_V2)) { 2349 if ((csum_offload || inner_csum) && 2350 !tx_queue->timestamping && !tx_queue->xdp_tx) { 2351 tx_queue->tso_version = 2; 2352 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n", 2353 channel->channel); 2354 } 2355 } else if (efx_has_cap(efx, TX_TSO)) { 2356 tx_queue->tso_version = 1; 2357 } 2358 2359 rc = efx_mcdi_tx_init(tx_queue); 2360 if (rc) 2361 goto fail; 2362 2363 /* A previous user of this TX queue might have set us up the 2364 * bomb by writing a descriptor to the TX push collector but 2365 * not the doorbell. (Each collector belongs to a port, not a 2366 * queue or function, so cannot easily be reset.) We must 2367 * attempt to push a no-op descriptor in its place. 2368 */ 2369 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 2370 tx_queue->insert_count = 1; 2371 txd = efx_tx_desc(tx_queue, 0); 2372 EFX_POPULATE_QWORD_7(*txd, 2373 ESF_DZ_TX_DESC_IS_OPT, true, 2374 ESF_DZ_TX_OPTION_TYPE, 2375 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 2376 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 2377 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload && tx_queue->tso_version != 2, 2378 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM, inner_csum, 2379 ESF_DZ_TX_OPTION_INNER_IP_CSUM, inner_csum && tx_queue->tso_version != 2, 2380 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping); 2381 tx_queue->write_count = 1; 2382 2383 if (tx_queue->tso_version == 2 && efx_has_cap(efx, TX_TSO_V2_ENCAP)) 2384 tx_queue->tso_encap = true; 2385 2386 wmb(); 2387 efx_ef10_push_tx_desc(tx_queue, txd); 2388 2389 return; 2390 2391 fail: 2392 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 2393 tx_queue->queue); 2394 } 2395 2396 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 2397 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 2398 { 2399 unsigned int write_ptr; 2400 efx_dword_t reg; 2401 2402 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2403 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 2404 efx_writed_page(tx_queue->efx, ®, 2405 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 2406 } 2407 2408 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff 2409 2410 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue, 2411 dma_addr_t dma_addr, unsigned int len) 2412 { 2413 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) { 2414 /* If we need to break across multiple descriptors we should 2415 * stop at a page boundary. This assumes the length limit is 2416 * greater than the page size. 2417 */ 2418 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN; 2419 2420 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE); 2421 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr; 2422 } 2423 2424 return len; 2425 } 2426 2427 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 2428 { 2429 unsigned int old_write_count = tx_queue->write_count; 2430 struct efx_tx_buffer *buffer; 2431 unsigned int write_ptr; 2432 efx_qword_t *txd; 2433 2434 tx_queue->xmit_pending = false; 2435 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 2436 return; 2437 2438 do { 2439 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2440 buffer = &tx_queue->buffer[write_ptr]; 2441 txd = efx_tx_desc(tx_queue, write_ptr); 2442 ++tx_queue->write_count; 2443 2444 /* Create TX descriptor ring entry */ 2445 if (buffer->flags & EFX_TX_BUF_OPTION) { 2446 *txd = buffer->option; 2447 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1) 2448 /* PIO descriptor */ 2449 tx_queue->packet_write_count = tx_queue->write_count; 2450 } else { 2451 tx_queue->packet_write_count = tx_queue->write_count; 2452 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 2453 EFX_POPULATE_QWORD_3( 2454 *txd, 2455 ESF_DZ_TX_KER_CONT, 2456 buffer->flags & EFX_TX_BUF_CONT, 2457 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 2458 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 2459 } 2460 } while (tx_queue->write_count != tx_queue->insert_count); 2461 2462 wmb(); /* Ensure descriptors are written before they are fetched */ 2463 2464 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 2465 txd = efx_tx_desc(tx_queue, 2466 old_write_count & tx_queue->ptr_mask); 2467 efx_ef10_push_tx_desc(tx_queue, txd); 2468 ++tx_queue->pushes; 2469 } else { 2470 efx_ef10_notify_tx_desc(tx_queue); 2471 } 2472 } 2473 2474 static int efx_ef10_probe_multicast_chaining(struct efx_nic *efx) 2475 { 2476 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2477 unsigned int enabled, implemented; 2478 bool want_workaround_26807; 2479 int rc; 2480 2481 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2482 if (rc == -ENOSYS) { 2483 /* GET_WORKAROUNDS was implemented before this workaround, 2484 * thus it must be unavailable in this firmware. 2485 */ 2486 nic_data->workaround_26807 = false; 2487 return 0; 2488 } 2489 if (rc) 2490 return rc; 2491 want_workaround_26807 = 2492 implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807; 2493 nic_data->workaround_26807 = 2494 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2495 2496 if (want_workaround_26807 && !nic_data->workaround_26807) { 2497 unsigned int flags; 2498 2499 rc = efx_mcdi_set_workaround(efx, 2500 MC_CMD_WORKAROUND_BUG26807, 2501 true, &flags); 2502 if (!rc) { 2503 if (flags & 2504 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2505 netif_info(efx, drv, efx->net_dev, 2506 "other functions on NIC have been reset\n"); 2507 2508 /* With MCFW v4.6.x and earlier, the 2509 * boot count will have incremented, 2510 * so re-read the warm_boot_count 2511 * value now to ensure this function 2512 * doesn't think it has changed next 2513 * time it checks. 2514 */ 2515 rc = efx_ef10_get_warm_boot_count(efx); 2516 if (rc >= 0) { 2517 nic_data->warm_boot_count = rc; 2518 rc = 0; 2519 } 2520 } 2521 nic_data->workaround_26807 = true; 2522 } else if (rc == -EPERM) { 2523 rc = 0; 2524 } 2525 } 2526 return rc; 2527 } 2528 2529 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 2530 { 2531 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2532 int rc = efx_ef10_probe_multicast_chaining(efx); 2533 struct efx_mcdi_filter_vlan *vlan; 2534 2535 if (rc) 2536 return rc; 2537 rc = efx_mcdi_filter_table_probe(efx, nic_data->workaround_26807); 2538 2539 if (rc) 2540 return rc; 2541 2542 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 2543 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 2544 if (rc) 2545 goto fail_add_vlan; 2546 } 2547 return 0; 2548 2549 fail_add_vlan: 2550 efx_mcdi_filter_table_remove(efx); 2551 return rc; 2552 } 2553 2554 /* This creates an entry in the RX descriptor queue */ 2555 static inline void 2556 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2557 { 2558 struct efx_rx_buffer *rx_buf; 2559 efx_qword_t *rxd; 2560 2561 rxd = efx_rx_desc(rx_queue, index); 2562 rx_buf = efx_rx_buffer(rx_queue, index); 2563 EFX_POPULATE_QWORD_2(*rxd, 2564 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2565 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2566 } 2567 2568 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2569 { 2570 struct efx_nic *efx = rx_queue->efx; 2571 unsigned int write_count; 2572 efx_dword_t reg; 2573 2574 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2575 write_count = rx_queue->added_count & ~7; 2576 if (rx_queue->notified_count == write_count) 2577 return; 2578 2579 do 2580 efx_ef10_build_rx_desc( 2581 rx_queue, 2582 rx_queue->notified_count & rx_queue->ptr_mask); 2583 while (++rx_queue->notified_count != write_count); 2584 2585 wmb(); 2586 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2587 write_count & rx_queue->ptr_mask); 2588 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2589 efx_rx_queue_index(rx_queue)); 2590 } 2591 2592 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2593 2594 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2595 { 2596 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2597 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2598 efx_qword_t event; 2599 2600 EFX_POPULATE_QWORD_2(event, 2601 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2602 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2603 2604 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2605 2606 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2607 * already swapped the data to little-endian order. 2608 */ 2609 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2610 sizeof(efx_qword_t)); 2611 2612 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2613 inbuf, sizeof(inbuf), 0, 2614 efx_ef10_rx_defer_refill_complete, 0); 2615 } 2616 2617 static void 2618 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2619 int rc, efx_dword_t *outbuf, 2620 size_t outlen_actual) 2621 { 2622 /* nothing to do */ 2623 } 2624 2625 static int efx_ef10_ev_init(struct efx_channel *channel) 2626 { 2627 struct efx_nic *efx = channel->efx; 2628 struct efx_ef10_nic_data *nic_data; 2629 bool use_v2, cut_thru; 2630 2631 nic_data = efx->nic_data; 2632 use_v2 = nic_data->datapath_caps2 & 2633 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN; 2634 cut_thru = !(nic_data->datapath_caps & 2635 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2636 return efx_mcdi_ev_init(channel, cut_thru, use_v2); 2637 } 2638 2639 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2640 unsigned int rx_queue_label) 2641 { 2642 struct efx_nic *efx = rx_queue->efx; 2643 2644 netif_info(efx, hw, efx->net_dev, 2645 "rx event arrived on queue %d labeled as queue %u\n", 2646 efx_rx_queue_index(rx_queue), rx_queue_label); 2647 2648 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2649 } 2650 2651 static void 2652 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2653 unsigned int actual, unsigned int expected) 2654 { 2655 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2656 struct efx_nic *efx = rx_queue->efx; 2657 2658 netif_info(efx, hw, efx->net_dev, 2659 "dropped %d events (index=%d expected=%d)\n", 2660 dropped, actual, expected); 2661 2662 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2663 } 2664 2665 /* partially received RX was aborted. clean up. */ 2666 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2667 { 2668 unsigned int rx_desc_ptr; 2669 2670 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2671 "scattered RX aborted (dropping %u buffers)\n", 2672 rx_queue->scatter_n); 2673 2674 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2675 2676 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2677 0, EFX_RX_PKT_DISCARD); 2678 2679 rx_queue->removed_count += rx_queue->scatter_n; 2680 rx_queue->scatter_n = 0; 2681 rx_queue->scatter_len = 0; 2682 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2683 } 2684 2685 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel, 2686 unsigned int n_packets, 2687 unsigned int rx_encap_hdr, 2688 unsigned int rx_l3_class, 2689 unsigned int rx_l4_class, 2690 const efx_qword_t *event) 2691 { 2692 struct efx_nic *efx = channel->efx; 2693 bool handled = false; 2694 2695 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) { 2696 if (!(efx->net_dev->features & NETIF_F_RXALL)) { 2697 if (!efx->loopback_selftest) 2698 channel->n_rx_eth_crc_err += n_packets; 2699 return EFX_RX_PKT_DISCARD; 2700 } 2701 handled = true; 2702 } 2703 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) { 2704 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2705 rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2706 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2707 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2708 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2709 netdev_WARN(efx->net_dev, 2710 "invalid class for RX_IPCKSUM_ERR: event=" 2711 EFX_QWORD_FMT "\n", 2712 EFX_QWORD_VAL(*event)); 2713 if (!efx->loopback_selftest) 2714 *(rx_encap_hdr ? 2715 &channel->n_rx_outer_ip_hdr_chksum_err : 2716 &channel->n_rx_ip_hdr_chksum_err) += n_packets; 2717 return 0; 2718 } 2719 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) { 2720 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2721 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2722 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2723 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2724 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))) 2725 netdev_WARN(efx->net_dev, 2726 "invalid class for RX_TCPUDP_CKSUM_ERR: event=" 2727 EFX_QWORD_FMT "\n", 2728 EFX_QWORD_VAL(*event)); 2729 if (!efx->loopback_selftest) 2730 *(rx_encap_hdr ? 2731 &channel->n_rx_outer_tcp_udp_chksum_err : 2732 &channel->n_rx_tcp_udp_chksum_err) += n_packets; 2733 return 0; 2734 } 2735 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) { 2736 if (unlikely(!rx_encap_hdr)) 2737 netdev_WARN(efx->net_dev, 2738 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event=" 2739 EFX_QWORD_FMT "\n", 2740 EFX_QWORD_VAL(*event)); 2741 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2742 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2743 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2744 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2745 netdev_WARN(efx->net_dev, 2746 "invalid class for RX_IP_INNER_CHKSUM_ERR: event=" 2747 EFX_QWORD_FMT "\n", 2748 EFX_QWORD_VAL(*event)); 2749 if (!efx->loopback_selftest) 2750 channel->n_rx_inner_ip_hdr_chksum_err += n_packets; 2751 return 0; 2752 } 2753 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) { 2754 if (unlikely(!rx_encap_hdr)) 2755 netdev_WARN(efx->net_dev, 2756 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2757 EFX_QWORD_FMT "\n", 2758 EFX_QWORD_VAL(*event)); 2759 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2760 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2761 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2762 rx_l4_class != ESE_FZ_L4_CLASS_UDP))) 2763 netdev_WARN(efx->net_dev, 2764 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2765 EFX_QWORD_FMT "\n", 2766 EFX_QWORD_VAL(*event)); 2767 if (!efx->loopback_selftest) 2768 channel->n_rx_inner_tcp_udp_chksum_err += n_packets; 2769 return 0; 2770 } 2771 2772 WARN_ON(!handled); /* No error bits were recognised */ 2773 return 0; 2774 } 2775 2776 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2777 const efx_qword_t *event) 2778 { 2779 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label; 2780 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr; 2781 unsigned int n_descs, n_packets, i; 2782 struct efx_nic *efx = channel->efx; 2783 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2784 struct efx_rx_queue *rx_queue; 2785 efx_qword_t errors; 2786 bool rx_cont; 2787 u16 flags = 0; 2788 2789 if (unlikely(READ_ONCE(efx->reset_pending))) 2790 return 0; 2791 2792 /* Basic packet information */ 2793 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2794 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2795 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2796 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS); 2797 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS); 2798 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2799 rx_encap_hdr = 2800 nic_data->datapath_caps & 2801 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ? 2802 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) : 2803 ESE_EZ_ENCAP_HDR_NONE; 2804 2805 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2806 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2807 EFX_QWORD_FMT "\n", 2808 EFX_QWORD_VAL(*event)); 2809 2810 rx_queue = efx_channel_get_rx_queue(channel); 2811 2812 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2813 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2814 2815 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2816 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2817 2818 if (n_descs != rx_queue->scatter_n + 1) { 2819 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2820 2821 /* detect rx abort */ 2822 if (unlikely(n_descs == rx_queue->scatter_n)) { 2823 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2824 netdev_WARN(efx->net_dev, 2825 "invalid RX abort: scatter_n=%u event=" 2826 EFX_QWORD_FMT "\n", 2827 rx_queue->scatter_n, 2828 EFX_QWORD_VAL(*event)); 2829 efx_ef10_handle_rx_abort(rx_queue); 2830 return 0; 2831 } 2832 2833 /* Check that RX completion merging is valid, i.e. 2834 * the current firmware supports it and this is a 2835 * non-scattered packet. 2836 */ 2837 if (!(nic_data->datapath_caps & 2838 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2839 rx_queue->scatter_n != 0 || rx_cont) { 2840 efx_ef10_handle_rx_bad_lbits( 2841 rx_queue, next_ptr_lbits, 2842 (rx_queue->removed_count + 2843 rx_queue->scatter_n + 1) & 2844 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2845 return 0; 2846 } 2847 2848 /* Merged completion for multiple non-scattered packets */ 2849 rx_queue->scatter_n = 1; 2850 rx_queue->scatter_len = 0; 2851 n_packets = n_descs; 2852 ++channel->n_rx_merge_events; 2853 channel->n_rx_merge_packets += n_packets; 2854 flags |= EFX_RX_PKT_PREFIX_LEN; 2855 } else { 2856 ++rx_queue->scatter_n; 2857 rx_queue->scatter_len += rx_bytes; 2858 if (rx_cont) 2859 return 0; 2860 n_packets = 1; 2861 } 2862 2863 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1, 2864 ESF_DZ_RX_IPCKSUM_ERR, 1, 2865 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1, 2866 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1, 2867 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1); 2868 EFX_AND_QWORD(errors, *event, errors); 2869 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) { 2870 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets, 2871 rx_encap_hdr, 2872 rx_l3_class, rx_l4_class, 2873 event); 2874 } else { 2875 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP || 2876 rx_l4_class == ESE_FZ_L4_CLASS_UDP; 2877 2878 switch (rx_encap_hdr) { 2879 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */ 2880 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */ 2881 if (tcpudp) 2882 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */ 2883 break; 2884 case ESE_EZ_ENCAP_HDR_GRE: 2885 case ESE_EZ_ENCAP_HDR_NONE: 2886 if (tcpudp) 2887 flags |= EFX_RX_PKT_CSUMMED; 2888 break; 2889 default: 2890 netdev_WARN(efx->net_dev, 2891 "unknown encapsulation type: event=" 2892 EFX_QWORD_FMT "\n", 2893 EFX_QWORD_VAL(*event)); 2894 } 2895 } 2896 2897 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP) 2898 flags |= EFX_RX_PKT_TCP; 2899 2900 channel->irq_mod_score += 2 * n_packets; 2901 2902 /* Handle received packet(s) */ 2903 for (i = 0; i < n_packets; i++) { 2904 efx_rx_packet(rx_queue, 2905 rx_queue->removed_count & rx_queue->ptr_mask, 2906 rx_queue->scatter_n, rx_queue->scatter_len, 2907 flags); 2908 rx_queue->removed_count += rx_queue->scatter_n; 2909 } 2910 2911 rx_queue->scatter_n = 0; 2912 rx_queue->scatter_len = 0; 2913 2914 return n_packets; 2915 } 2916 2917 static u32 efx_ef10_extract_event_ts(efx_qword_t *event) 2918 { 2919 u32 tstamp; 2920 2921 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI); 2922 tstamp <<= 16; 2923 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO); 2924 2925 return tstamp; 2926 } 2927 2928 static void 2929 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2930 { 2931 struct efx_nic *efx = channel->efx; 2932 struct efx_tx_queue *tx_queue; 2933 unsigned int tx_ev_desc_ptr; 2934 unsigned int tx_ev_q_label; 2935 unsigned int tx_ev_type; 2936 u64 ts_part; 2937 2938 if (unlikely(READ_ONCE(efx->reset_pending))) 2939 return; 2940 2941 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2942 return; 2943 2944 /* Get the transmit queue */ 2945 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2946 tx_queue = channel->tx_queue + (tx_ev_q_label % EFX_MAX_TXQ_PER_CHANNEL); 2947 2948 if (!tx_queue->timestamping) { 2949 /* Transmit completion */ 2950 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2951 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2952 return; 2953 } 2954 2955 /* Transmit timestamps are only available for 8XXX series. They result 2956 * in up to three events per packet. These occur in order, and are: 2957 * - the normal completion event (may be omitted) 2958 * - the low part of the timestamp 2959 * - the high part of the timestamp 2960 * 2961 * It's possible for multiple completion events to appear before the 2962 * corresponding timestamps. So we can for example get: 2963 * COMP N 2964 * COMP N+1 2965 * TS_LO N 2966 * TS_HI N 2967 * TS_LO N+1 2968 * TS_HI N+1 2969 * 2970 * In addition it's also possible for the adjacent completions to be 2971 * merged, so we may not see COMP N above. As such, the completion 2972 * events are not very useful here. 2973 * 2974 * Each part of the timestamp is itself split across two 16 bit 2975 * fields in the event. 2976 */ 2977 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1); 2978 2979 switch (tx_ev_type) { 2980 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION: 2981 /* Ignore this event - see above. */ 2982 break; 2983 2984 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO: 2985 ts_part = efx_ef10_extract_event_ts(event); 2986 tx_queue->completed_timestamp_minor = ts_part; 2987 break; 2988 2989 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI: 2990 ts_part = efx_ef10_extract_event_ts(event); 2991 tx_queue->completed_timestamp_major = ts_part; 2992 2993 efx_xmit_done_single(tx_queue); 2994 break; 2995 2996 default: 2997 netif_err(efx, hw, efx->net_dev, 2998 "channel %d unknown tx event type %d (data " 2999 EFX_QWORD_FMT ")\n", 3000 channel->channel, tx_ev_type, 3001 EFX_QWORD_VAL(*event)); 3002 break; 3003 } 3004 } 3005 3006 static void 3007 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 3008 { 3009 struct efx_nic *efx = channel->efx; 3010 int subcode; 3011 3012 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 3013 3014 switch (subcode) { 3015 case ESE_DZ_DRV_TIMER_EV: 3016 case ESE_DZ_DRV_WAKE_UP_EV: 3017 break; 3018 case ESE_DZ_DRV_START_UP_EV: 3019 /* event queue init complete. ok. */ 3020 break; 3021 default: 3022 netif_err(efx, hw, efx->net_dev, 3023 "channel %d unknown driver event type %d" 3024 " (data " EFX_QWORD_FMT ")\n", 3025 channel->channel, subcode, 3026 EFX_QWORD_VAL(*event)); 3027 3028 } 3029 } 3030 3031 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 3032 efx_qword_t *event) 3033 { 3034 struct efx_nic *efx = channel->efx; 3035 u32 subcode; 3036 3037 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 3038 3039 switch (subcode) { 3040 case EFX_EF10_TEST: 3041 channel->event_test_cpu = raw_smp_processor_id(); 3042 break; 3043 case EFX_EF10_REFILL: 3044 /* The queue must be empty, so we won't receive any rx 3045 * events, so efx_process_channel() won't refill the 3046 * queue. Refill it here 3047 */ 3048 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 3049 break; 3050 default: 3051 netif_err(efx, hw, efx->net_dev, 3052 "channel %d unknown driver event type %u" 3053 " (data " EFX_QWORD_FMT ")\n", 3054 channel->channel, (unsigned) subcode, 3055 EFX_QWORD_VAL(*event)); 3056 } 3057 } 3058 3059 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 3060 { 3061 struct efx_nic *efx = channel->efx; 3062 efx_qword_t event, *p_event; 3063 unsigned int read_ptr; 3064 int ev_code; 3065 int spent = 0; 3066 3067 if (quota <= 0) 3068 return spent; 3069 3070 read_ptr = channel->eventq_read_ptr; 3071 3072 for (;;) { 3073 p_event = efx_event(channel, read_ptr); 3074 event = *p_event; 3075 3076 if (!efx_event_present(&event)) 3077 break; 3078 3079 EFX_SET_QWORD(*p_event); 3080 3081 ++read_ptr; 3082 3083 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 3084 3085 netif_vdbg(efx, drv, efx->net_dev, 3086 "processing event on %d " EFX_QWORD_FMT "\n", 3087 channel->channel, EFX_QWORD_VAL(event)); 3088 3089 switch (ev_code) { 3090 case ESE_DZ_EV_CODE_MCDI_EV: 3091 efx_mcdi_process_event(channel, &event); 3092 break; 3093 case ESE_DZ_EV_CODE_RX_EV: 3094 spent += efx_ef10_handle_rx_event(channel, &event); 3095 if (spent >= quota) { 3096 /* XXX can we split a merged event to 3097 * avoid going over-quota? 3098 */ 3099 spent = quota; 3100 goto out; 3101 } 3102 break; 3103 case ESE_DZ_EV_CODE_TX_EV: 3104 efx_ef10_handle_tx_event(channel, &event); 3105 break; 3106 case ESE_DZ_EV_CODE_DRIVER_EV: 3107 efx_ef10_handle_driver_event(channel, &event); 3108 if (++spent == quota) 3109 goto out; 3110 break; 3111 case EFX_EF10_DRVGEN_EV: 3112 efx_ef10_handle_driver_generated_event(channel, &event); 3113 break; 3114 default: 3115 netif_err(efx, hw, efx->net_dev, 3116 "channel %d unknown event type %d" 3117 " (data " EFX_QWORD_FMT ")\n", 3118 channel->channel, ev_code, 3119 EFX_QWORD_VAL(event)); 3120 } 3121 } 3122 3123 out: 3124 channel->eventq_read_ptr = read_ptr; 3125 return spent; 3126 } 3127 3128 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 3129 { 3130 struct efx_nic *efx = channel->efx; 3131 efx_dword_t rptr; 3132 3133 if (EFX_EF10_WORKAROUND_35388(efx)) { 3134 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 3135 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 3136 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 3137 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 3138 3139 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3140 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 3141 ERF_DD_EVQ_IND_RPTR, 3142 (channel->eventq_read_ptr & 3143 channel->eventq_mask) >> 3144 ERF_DD_EVQ_IND_RPTR_WIDTH); 3145 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3146 channel->channel); 3147 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3148 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 3149 ERF_DD_EVQ_IND_RPTR, 3150 channel->eventq_read_ptr & 3151 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 3152 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3153 channel->channel); 3154 } else { 3155 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 3156 channel->eventq_read_ptr & 3157 channel->eventq_mask); 3158 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 3159 } 3160 } 3161 3162 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 3163 { 3164 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 3165 struct efx_nic *efx = channel->efx; 3166 efx_qword_t event; 3167 int rc; 3168 3169 EFX_POPULATE_QWORD_2(event, 3170 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 3171 ESF_DZ_EV_DATA, EFX_EF10_TEST); 3172 3173 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 3174 3175 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 3176 * already swapped the data to little-endian order. 3177 */ 3178 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 3179 sizeof(efx_qword_t)); 3180 3181 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 3182 NULL, 0, NULL); 3183 if (rc != 0) 3184 goto fail; 3185 3186 return; 3187 3188 fail: 3189 WARN_ON(true); 3190 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 3191 } 3192 3193 static void efx_ef10_prepare_flr(struct efx_nic *efx) 3194 { 3195 atomic_set(&efx->active_queues, 0); 3196 } 3197 3198 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 3199 { 3200 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3201 u8 mac_old[ETH_ALEN]; 3202 int rc, rc2; 3203 3204 /* Only reconfigure a PF-created vport */ 3205 if (is_zero_ether_addr(nic_data->vport_mac)) 3206 return 0; 3207 3208 efx_device_detach_sync(efx); 3209 efx_net_stop(efx->net_dev); 3210 down_write(&efx->filter_sem); 3211 efx_mcdi_filter_table_remove(efx); 3212 up_write(&efx->filter_sem); 3213 3214 rc = efx_ef10_vadaptor_free(efx, efx->vport_id); 3215 if (rc) 3216 goto restore_filters; 3217 3218 ether_addr_copy(mac_old, nic_data->vport_mac); 3219 rc = efx_ef10_vport_del_mac(efx, efx->vport_id, 3220 nic_data->vport_mac); 3221 if (rc) 3222 goto restore_vadaptor; 3223 3224 rc = efx_ef10_vport_add_mac(efx, efx->vport_id, 3225 efx->net_dev->dev_addr); 3226 if (!rc) { 3227 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 3228 } else { 3229 rc2 = efx_ef10_vport_add_mac(efx, efx->vport_id, mac_old); 3230 if (rc2) { 3231 /* Failed to add original MAC, so clear vport_mac */ 3232 eth_zero_addr(nic_data->vport_mac); 3233 goto reset_nic; 3234 } 3235 } 3236 3237 restore_vadaptor: 3238 rc2 = efx_ef10_vadaptor_alloc(efx, efx->vport_id); 3239 if (rc2) 3240 goto reset_nic; 3241 restore_filters: 3242 down_write(&efx->filter_sem); 3243 rc2 = efx_ef10_filter_table_probe(efx); 3244 up_write(&efx->filter_sem); 3245 if (rc2) 3246 goto reset_nic; 3247 3248 rc2 = efx_net_open(efx->net_dev); 3249 if (rc2) 3250 goto reset_nic; 3251 3252 efx_device_attach_if_not_resetting(efx); 3253 3254 return rc; 3255 3256 reset_nic: 3257 netif_err(efx, drv, efx->net_dev, 3258 "Failed to restore when changing MAC address - scheduling reset\n"); 3259 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 3260 3261 return rc ? rc : rc2; 3262 } 3263 3264 static int efx_ef10_set_mac_address(struct efx_nic *efx) 3265 { 3266 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 3267 bool was_enabled = efx->port_enabled; 3268 int rc; 3269 3270 efx_device_detach_sync(efx); 3271 efx_net_stop(efx->net_dev); 3272 3273 mutex_lock(&efx->mac_lock); 3274 down_write(&efx->filter_sem); 3275 efx_mcdi_filter_table_remove(efx); 3276 3277 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 3278 efx->net_dev->dev_addr); 3279 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 3280 efx->vport_id); 3281 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 3282 sizeof(inbuf), NULL, 0, NULL); 3283 3284 efx_ef10_filter_table_probe(efx); 3285 up_write(&efx->filter_sem); 3286 mutex_unlock(&efx->mac_lock); 3287 3288 if (was_enabled) 3289 efx_net_open(efx->net_dev); 3290 efx_device_attach_if_not_resetting(efx); 3291 3292 #ifdef CONFIG_SFC_SRIOV 3293 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 3294 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3295 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 3296 3297 if (rc == -EPERM) { 3298 struct efx_nic *efx_pf; 3299 3300 /* Switch to PF and change MAC address on vport */ 3301 efx_pf = pci_get_drvdata(pci_dev_pf); 3302 3303 rc = efx_ef10_sriov_set_vf_mac(efx_pf, 3304 nic_data->vf_index, 3305 efx->net_dev->dev_addr); 3306 } else if (!rc) { 3307 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 3308 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data; 3309 unsigned int i; 3310 3311 /* MAC address successfully changed by VF (with MAC 3312 * spoofing) so update the parent PF if possible. 3313 */ 3314 for (i = 0; i < efx_pf->vf_count; ++i) { 3315 struct ef10_vf *vf = nic_data->vf + i; 3316 3317 if (vf->efx == efx) { 3318 ether_addr_copy(vf->mac, 3319 efx->net_dev->dev_addr); 3320 return 0; 3321 } 3322 } 3323 } 3324 } else 3325 #endif 3326 if (rc == -EPERM) { 3327 netif_err(efx, drv, efx->net_dev, 3328 "Cannot change MAC address; use sfboot to enable" 3329 " mac-spoofing on this interface\n"); 3330 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 3331 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 3332 * fall-back to the method of changing the MAC address on the 3333 * vport. This only applies to PFs because such versions of 3334 * MCFW do not support VFs. 3335 */ 3336 rc = efx_ef10_vport_set_mac_address(efx); 3337 } else if (rc) { 3338 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 3339 sizeof(inbuf), NULL, 0, rc); 3340 } 3341 3342 return rc; 3343 } 3344 3345 static int efx_ef10_mac_reconfigure(struct efx_nic *efx, bool mtu_only) 3346 { 3347 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 3348 3349 efx_mcdi_filter_sync_rx_mode(efx); 3350 3351 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED)) 3352 return efx_mcdi_set_mtu(efx); 3353 return efx_mcdi_set_mac(efx); 3354 } 3355 3356 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 3357 { 3358 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 3359 3360 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 3361 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 3362 NULL, 0, NULL); 3363 } 3364 3365 /* MC BISTs follow a different poll mechanism to phy BISTs. 3366 * The BIST is done in the poll handler on the MC, and the MCDI command 3367 * will block until the BIST is done. 3368 */ 3369 static int efx_ef10_poll_bist(struct efx_nic *efx) 3370 { 3371 int rc; 3372 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 3373 size_t outlen; 3374 u32 result; 3375 3376 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 3377 outbuf, sizeof(outbuf), &outlen); 3378 if (rc != 0) 3379 return rc; 3380 3381 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 3382 return -EIO; 3383 3384 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 3385 switch (result) { 3386 case MC_CMD_POLL_BIST_PASSED: 3387 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 3388 return 0; 3389 case MC_CMD_POLL_BIST_TIMEOUT: 3390 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 3391 return -EIO; 3392 case MC_CMD_POLL_BIST_FAILED: 3393 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 3394 return -EIO; 3395 default: 3396 netif_err(efx, hw, efx->net_dev, 3397 "BIST returned unknown result %u", result); 3398 return -EIO; 3399 } 3400 } 3401 3402 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 3403 { 3404 int rc; 3405 3406 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 3407 3408 rc = efx_ef10_start_bist(efx, bist_type); 3409 if (rc != 0) 3410 return rc; 3411 3412 return efx_ef10_poll_bist(efx); 3413 } 3414 3415 static int 3416 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 3417 { 3418 int rc, rc2; 3419 3420 efx_reset_down(efx, RESET_TYPE_WORLD); 3421 3422 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 3423 NULL, 0, NULL, 0, NULL); 3424 if (rc != 0) 3425 goto out; 3426 3427 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 3428 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 3429 3430 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 3431 3432 out: 3433 if (rc == -EPERM) 3434 rc = 0; 3435 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 3436 return rc ? rc : rc2; 3437 } 3438 3439 #ifdef CONFIG_SFC_MTD 3440 3441 struct efx_ef10_nvram_type_info { 3442 u16 type, type_mask; 3443 u8 port; 3444 const char *name; 3445 }; 3446 3447 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 3448 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 3449 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 3450 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 3451 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 3452 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 3453 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 3454 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 3455 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 3456 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 3457 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 3458 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 3459 { NVRAM_PARTITION_TYPE_MUM_FIRMWARE, 0, 0, "sfc_mumfw" }, 3460 { NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 0, 0, "sfc_uefi" }, 3461 { NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS, 0, 0, "sfc_dynamic_cfg_dflt" }, 3462 { NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS, 0, 0, "sfc_exp_rom_cfg_dflt" }, 3463 { NVRAM_PARTITION_TYPE_STATUS, 0, 0, "sfc_status" }, 3464 { NVRAM_PARTITION_TYPE_BUNDLE, 0, 0, "sfc_bundle" }, 3465 { NVRAM_PARTITION_TYPE_BUNDLE_METADATA, 0, 0, "sfc_bundle_metadata" }, 3466 }; 3467 #define EF10_NVRAM_PARTITION_COUNT ARRAY_SIZE(efx_ef10_nvram_types) 3468 3469 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 3470 struct efx_mcdi_mtd_partition *part, 3471 unsigned int type, 3472 unsigned long *found) 3473 { 3474 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 3475 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 3476 const struct efx_ef10_nvram_type_info *info; 3477 size_t size, erase_size, outlen; 3478 int type_idx = 0; 3479 bool protected; 3480 int rc; 3481 3482 for (type_idx = 0; ; type_idx++) { 3483 if (type_idx == EF10_NVRAM_PARTITION_COUNT) 3484 return -ENODEV; 3485 info = efx_ef10_nvram_types + type_idx; 3486 if ((type & ~info->type_mask) == info->type) 3487 break; 3488 } 3489 if (info->port != efx_port_num(efx)) 3490 return -ENODEV; 3491 3492 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 3493 if (rc) 3494 return rc; 3495 if (protected && 3496 (type != NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS && 3497 type != NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS)) 3498 /* Hide protected partitions that don't provide defaults. */ 3499 return -ENODEV; 3500 3501 if (protected) 3502 /* Protected partitions are read only. */ 3503 erase_size = 0; 3504 3505 /* If we've already exposed a partition of this type, hide this 3506 * duplicate. All operations on MTDs are keyed by the type anyway, 3507 * so we can't act on the duplicate. 3508 */ 3509 if (__test_and_set_bit(type_idx, found)) 3510 return -EEXIST; 3511 3512 part->nvram_type = type; 3513 3514 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 3515 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 3516 outbuf, sizeof(outbuf), &outlen); 3517 if (rc) 3518 return rc; 3519 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 3520 return -EIO; 3521 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 3522 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 3523 part->fw_subtype = MCDI_DWORD(outbuf, 3524 NVRAM_METADATA_OUT_SUBTYPE); 3525 3526 part->common.dev_type_name = "EF10 NVRAM manager"; 3527 part->common.type_name = info->name; 3528 3529 part->common.mtd.type = MTD_NORFLASH; 3530 part->common.mtd.flags = MTD_CAP_NORFLASH; 3531 part->common.mtd.size = size; 3532 part->common.mtd.erasesize = erase_size; 3533 /* sfc_status is read-only */ 3534 if (!erase_size) 3535 part->common.mtd.flags |= MTD_NO_ERASE; 3536 3537 return 0; 3538 } 3539 3540 static int efx_ef10_mtd_probe(struct efx_nic *efx) 3541 { 3542 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 3543 DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 }; 3544 struct efx_mcdi_mtd_partition *parts; 3545 size_t outlen, n_parts_total, i, n_parts; 3546 unsigned int type; 3547 int rc; 3548 3549 ASSERT_RTNL(); 3550 3551 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 3552 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 3553 outbuf, sizeof(outbuf), &outlen); 3554 if (rc) 3555 return rc; 3556 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 3557 return -EIO; 3558 3559 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 3560 if (n_parts_total > 3561 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 3562 return -EIO; 3563 3564 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 3565 if (!parts) 3566 return -ENOMEM; 3567 3568 n_parts = 0; 3569 for (i = 0; i < n_parts_total; i++) { 3570 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 3571 i); 3572 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type, 3573 found); 3574 if (rc == -EEXIST || rc == -ENODEV) 3575 continue; 3576 if (rc) 3577 goto fail; 3578 n_parts++; 3579 } 3580 3581 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 3582 fail: 3583 if (rc) 3584 kfree(parts); 3585 return rc; 3586 } 3587 3588 #endif /* CONFIG_SFC_MTD */ 3589 3590 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 3591 { 3592 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 3593 } 3594 3595 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 3596 u32 host_time) {} 3597 3598 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 3599 bool temp) 3600 { 3601 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 3602 int rc; 3603 3604 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 3605 channel->sync_events_state == SYNC_EVENTS_VALID || 3606 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 3607 return 0; 3608 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 3609 3610 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 3611 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3612 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 3613 channel->channel); 3614 3615 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3616 inbuf, sizeof(inbuf), NULL, 0, NULL); 3617 3618 if (rc != 0) 3619 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3620 SYNC_EVENTS_DISABLED; 3621 3622 return rc; 3623 } 3624 3625 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 3626 bool temp) 3627 { 3628 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 3629 int rc; 3630 3631 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 3632 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 3633 return 0; 3634 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 3635 channel->sync_events_state = SYNC_EVENTS_DISABLED; 3636 return 0; 3637 } 3638 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3639 SYNC_EVENTS_DISABLED; 3640 3641 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 3642 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3643 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 3644 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 3645 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 3646 channel->channel); 3647 3648 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3649 inbuf, sizeof(inbuf), NULL, 0, NULL); 3650 3651 return rc; 3652 } 3653 3654 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 3655 bool temp) 3656 { 3657 int (*set)(struct efx_channel *channel, bool temp); 3658 struct efx_channel *channel; 3659 3660 set = en ? 3661 efx_ef10_rx_enable_timestamping : 3662 efx_ef10_rx_disable_timestamping; 3663 3664 channel = efx_ptp_channel(efx); 3665 if (channel) { 3666 int rc = set(channel, temp); 3667 if (en && rc != 0) { 3668 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 3669 return rc; 3670 } 3671 } 3672 3673 return 0; 3674 } 3675 3676 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 3677 struct hwtstamp_config *init) 3678 { 3679 return -EOPNOTSUPP; 3680 } 3681 3682 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 3683 struct hwtstamp_config *init) 3684 { 3685 int rc; 3686 3687 switch (init->rx_filter) { 3688 case HWTSTAMP_FILTER_NONE: 3689 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 3690 /* if TX timestamping is still requested then leave PTP on */ 3691 return efx_ptp_change_mode(efx, 3692 init->tx_type != HWTSTAMP_TX_OFF, 0); 3693 case HWTSTAMP_FILTER_ALL: 3694 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3695 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3696 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3697 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3698 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3699 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3700 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3701 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3702 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3703 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3704 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3705 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3706 case HWTSTAMP_FILTER_NTP_ALL: 3707 init->rx_filter = HWTSTAMP_FILTER_ALL; 3708 rc = efx_ptp_change_mode(efx, true, 0); 3709 if (!rc) 3710 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 3711 if (rc) 3712 efx_ptp_change_mode(efx, false, 0); 3713 return rc; 3714 default: 3715 return -ERANGE; 3716 } 3717 } 3718 3719 static int efx_ef10_get_phys_port_id(struct efx_nic *efx, 3720 struct netdev_phys_item_id *ppid) 3721 { 3722 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3723 3724 if (!is_valid_ether_addr(nic_data->port_id)) 3725 return -EOPNOTSUPP; 3726 3727 ppid->id_len = ETH_ALEN; 3728 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 3729 3730 return 0; 3731 } 3732 3733 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3734 { 3735 if (proto != htons(ETH_P_8021Q)) 3736 return -EINVAL; 3737 3738 return efx_ef10_add_vlan(efx, vid); 3739 } 3740 3741 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3742 { 3743 if (proto != htons(ETH_P_8021Q)) 3744 return -EINVAL; 3745 3746 return efx_ef10_del_vlan(efx, vid); 3747 } 3748 3749 /* We rely on the MCDI wiping out our TX rings if it made any changes to the 3750 * ports table, ensuring that any TSO descriptors that were made on a now- 3751 * removed tunnel port will be blown away and won't break things when we try 3752 * to transmit them using the new ports table. 3753 */ 3754 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading) 3755 { 3756 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3757 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX); 3758 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN); 3759 bool will_reset = false; 3760 size_t num_entries = 0; 3761 size_t inlen, outlen; 3762 size_t i; 3763 int rc; 3764 efx_dword_t flags_and_num_entries; 3765 3766 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock)); 3767 3768 nic_data->udp_tunnels_dirty = false; 3769 3770 if (!(nic_data->datapath_caps & 3771 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) { 3772 efx_device_attach_if_not_resetting(efx); 3773 return 0; 3774 } 3775 3776 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) > 3777 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM); 3778 3779 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) { 3780 if (nic_data->udp_tunnels[i].type != 3781 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID) { 3782 efx_dword_t entry; 3783 3784 EFX_POPULATE_DWORD_2(entry, 3785 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT, 3786 ntohs(nic_data->udp_tunnels[i].port), 3787 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL, 3788 nic_data->udp_tunnels[i].type); 3789 *_MCDI_ARRAY_DWORD(inbuf, 3790 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES, 3791 num_entries++) = entry; 3792 } 3793 } 3794 3795 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST - 3796 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 != 3797 EFX_WORD_1_LBN); 3798 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 != 3799 EFX_WORD_1_WIDTH); 3800 EFX_POPULATE_DWORD_2(flags_and_num_entries, 3801 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING, 3802 !!unloading, 3803 EFX_WORD_1, num_entries); 3804 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) = 3805 flags_and_num_entries; 3806 3807 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries); 3808 3809 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS, 3810 inbuf, inlen, outbuf, sizeof(outbuf), &outlen); 3811 if (rc == -EIO) { 3812 /* Most likely the MC rebooted due to another function also 3813 * setting its tunnel port list. Mark the tunnel port list as 3814 * dirty, so it will be pushed upon coming up from the reboot. 3815 */ 3816 nic_data->udp_tunnels_dirty = true; 3817 return 0; 3818 } 3819 3820 if (rc) { 3821 /* expected not available on unprivileged functions */ 3822 if (rc != -EPERM) 3823 netif_warn(efx, drv, efx->net_dev, 3824 "Unable to set UDP tunnel ports; rc=%d.\n", rc); 3825 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) & 3826 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) { 3827 netif_info(efx, drv, efx->net_dev, 3828 "Rebooting MC due to UDP tunnel port list change\n"); 3829 will_reset = true; 3830 if (unloading) 3831 /* Delay for the MC reset to complete. This will make 3832 * unloading other functions a bit smoother. This is a 3833 * race, but the other unload will work whichever way 3834 * it goes, this just avoids an unnecessary error 3835 * message. 3836 */ 3837 msleep(100); 3838 } 3839 if (!will_reset && !unloading) { 3840 /* The caller will have detached, relying on the MC reset to 3841 * trigger a re-attach. Since there won't be an MC reset, we 3842 * have to do the attach ourselves. 3843 */ 3844 efx_device_attach_if_not_resetting(efx); 3845 } 3846 3847 return rc; 3848 } 3849 3850 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx) 3851 { 3852 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3853 int rc = 0; 3854 3855 mutex_lock(&nic_data->udp_tunnels_lock); 3856 if (nic_data->udp_tunnels_dirty) { 3857 /* Make sure all TX are stopped while we modify the table, else 3858 * we might race against an efx_features_check(). 3859 */ 3860 efx_device_detach_sync(efx); 3861 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3862 } 3863 mutex_unlock(&nic_data->udp_tunnels_lock); 3864 return rc; 3865 } 3866 3867 static int efx_ef10_udp_tnl_set_port(struct net_device *dev, 3868 unsigned int table, unsigned int entry, 3869 struct udp_tunnel_info *ti) 3870 { 3871 struct efx_nic *efx = netdev_priv(dev); 3872 struct efx_ef10_nic_data *nic_data; 3873 int efx_tunnel_type, rc; 3874 3875 if (ti->type == UDP_TUNNEL_TYPE_VXLAN) 3876 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN; 3877 else 3878 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE; 3879 3880 nic_data = efx->nic_data; 3881 if (!(nic_data->datapath_caps & 3882 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3883 return -EOPNOTSUPP; 3884 3885 mutex_lock(&nic_data->udp_tunnels_lock); 3886 /* Make sure all TX are stopped while we add to the table, else we 3887 * might race against an efx_features_check(). 3888 */ 3889 efx_device_detach_sync(efx); 3890 nic_data->udp_tunnels[entry].type = efx_tunnel_type; 3891 nic_data->udp_tunnels[entry].port = ti->port; 3892 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3893 mutex_unlock(&nic_data->udp_tunnels_lock); 3894 3895 return rc; 3896 } 3897 3898 /* Called under the TX lock with the TX queue running, hence no-one can be 3899 * in the middle of updating the UDP tunnels table. However, they could 3900 * have tried and failed the MCDI, in which case they'll have set the dirty 3901 * flag before dropping their locks. 3902 */ 3903 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port) 3904 { 3905 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3906 size_t i; 3907 3908 if (!(nic_data->datapath_caps & 3909 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3910 return false; 3911 3912 if (nic_data->udp_tunnels_dirty) 3913 /* SW table may not match HW state, so just assume we can't 3914 * use any UDP tunnel offloads. 3915 */ 3916 return false; 3917 3918 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 3919 if (nic_data->udp_tunnels[i].type != 3920 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID && 3921 nic_data->udp_tunnels[i].port == port) 3922 return true; 3923 3924 return false; 3925 } 3926 3927 static int efx_ef10_udp_tnl_unset_port(struct net_device *dev, 3928 unsigned int table, unsigned int entry, 3929 struct udp_tunnel_info *ti) 3930 { 3931 struct efx_nic *efx = netdev_priv(dev); 3932 struct efx_ef10_nic_data *nic_data; 3933 int rc; 3934 3935 nic_data = efx->nic_data; 3936 3937 mutex_lock(&nic_data->udp_tunnels_lock); 3938 /* Make sure all TX are stopped while we remove from the table, else we 3939 * might race against an efx_features_check(). 3940 */ 3941 efx_device_detach_sync(efx); 3942 nic_data->udp_tunnels[entry].type = TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 3943 nic_data->udp_tunnels[entry].port = 0; 3944 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3945 mutex_unlock(&nic_data->udp_tunnels_lock); 3946 3947 return rc; 3948 } 3949 3950 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels = { 3951 .set_port = efx_ef10_udp_tnl_set_port, 3952 .unset_port = efx_ef10_udp_tnl_unset_port, 3953 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP, 3954 .tables = { 3955 { 3956 .n_entries = 16, 3957 .tunnel_types = UDP_TUNNEL_TYPE_VXLAN | 3958 UDP_TUNNEL_TYPE_GENEVE, 3959 }, 3960 }, 3961 }; 3962 3963 /* EF10 may have multiple datapath firmware variants within a 3964 * single version. Report which variants are running. 3965 */ 3966 static size_t efx_ef10_print_additional_fwver(struct efx_nic *efx, char *buf, 3967 size_t len) 3968 { 3969 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3970 3971 return scnprintf(buf, len, " rx%x tx%x", 3972 nic_data->rx_dpcpu_fw_id, 3973 nic_data->tx_dpcpu_fw_id); 3974 } 3975 3976 static unsigned int ef10_check_caps(const struct efx_nic *efx, 3977 u8 flag, 3978 u32 offset) 3979 { 3980 const struct efx_ef10_nic_data *nic_data = efx->nic_data; 3981 3982 switch (offset) { 3983 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST): 3984 return nic_data->datapath_caps & BIT_ULL(flag); 3985 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST): 3986 return nic_data->datapath_caps2 & BIT_ULL(flag); 3987 default: 3988 return 0; 3989 } 3990 } 3991 3992 #define EF10_OFFLOAD_FEATURES \ 3993 (NETIF_F_IP_CSUM | \ 3994 NETIF_F_HW_VLAN_CTAG_FILTER | \ 3995 NETIF_F_IPV6_CSUM | \ 3996 NETIF_F_RXHASH | \ 3997 NETIF_F_NTUPLE) 3998 3999 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 4000 .is_vf = true, 4001 .mem_bar = efx_ef10_vf_mem_bar, 4002 .mem_map_size = efx_ef10_mem_map_size, 4003 .probe = efx_ef10_probe_vf, 4004 .remove = efx_ef10_remove, 4005 .dimension_resources = efx_ef10_dimension_resources, 4006 .init = efx_ef10_init_nic, 4007 .fini = efx_ef10_fini_nic, 4008 .map_reset_reason = efx_ef10_map_reset_reason, 4009 .map_reset_flags = efx_ef10_map_reset_flags, 4010 .reset = efx_ef10_reset, 4011 .probe_port = efx_mcdi_port_probe, 4012 .remove_port = efx_mcdi_port_remove, 4013 .fini_dmaq = efx_fini_dmaq, 4014 .prepare_flr = efx_ef10_prepare_flr, 4015 .finish_flr = efx_port_dummy_op_void, 4016 .describe_stats = efx_ef10_describe_stats, 4017 .update_stats = efx_ef10_update_stats_vf, 4018 .update_stats_atomic = efx_ef10_update_stats_atomic_vf, 4019 .start_stats = efx_port_dummy_op_void, 4020 .pull_stats = efx_port_dummy_op_void, 4021 .stop_stats = efx_port_dummy_op_void, 4022 .push_irq_moderation = efx_ef10_push_irq_moderation, 4023 .reconfigure_mac = efx_ef10_mac_reconfigure, 4024 .check_mac_fault = efx_mcdi_mac_check_fault, 4025 .reconfigure_port = efx_mcdi_port_reconfigure, 4026 .get_wol = efx_ef10_get_wol_vf, 4027 .set_wol = efx_ef10_set_wol_vf, 4028 .resume_wol = efx_port_dummy_op_void, 4029 .mcdi_request = efx_ef10_mcdi_request, 4030 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4031 .mcdi_read_response = efx_ef10_mcdi_read_response, 4032 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4033 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4034 .irq_enable_master = efx_port_dummy_op_void, 4035 .irq_test_generate = efx_ef10_irq_test_generate, 4036 .irq_disable_non_ev = efx_port_dummy_op_void, 4037 .irq_handle_msi = efx_ef10_msi_interrupt, 4038 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4039 .tx_probe = efx_ef10_tx_probe, 4040 .tx_init = efx_ef10_tx_init, 4041 .tx_remove = efx_mcdi_tx_remove, 4042 .tx_write = efx_ef10_tx_write, 4043 .tx_limit_len = efx_ef10_tx_limit_len, 4044 .tx_enqueue = __efx_enqueue_skb, 4045 .rx_push_rss_config = efx_mcdi_vf_rx_push_rss_config, 4046 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4047 .rx_probe = efx_mcdi_rx_probe, 4048 .rx_init = efx_mcdi_rx_init, 4049 .rx_remove = efx_mcdi_rx_remove, 4050 .rx_write = efx_ef10_rx_write, 4051 .rx_defer_refill = efx_ef10_rx_defer_refill, 4052 .rx_packet = __efx_rx_packet, 4053 .ev_probe = efx_mcdi_ev_probe, 4054 .ev_init = efx_ef10_ev_init, 4055 .ev_fini = efx_mcdi_ev_fini, 4056 .ev_remove = efx_mcdi_ev_remove, 4057 .ev_process = efx_ef10_ev_process, 4058 .ev_read_ack = efx_ef10_ev_read_ack, 4059 .ev_test_generate = efx_ef10_ev_test_generate, 4060 .filter_table_probe = efx_ef10_filter_table_probe, 4061 .filter_table_restore = efx_mcdi_filter_table_restore, 4062 .filter_table_remove = efx_mcdi_filter_table_remove, 4063 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4064 .filter_insert = efx_mcdi_filter_insert, 4065 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4066 .filter_get_safe = efx_mcdi_filter_get_safe, 4067 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4068 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4069 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4070 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4071 #ifdef CONFIG_RFS_ACCEL 4072 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4073 #endif 4074 #ifdef CONFIG_SFC_MTD 4075 .mtd_probe = efx_port_dummy_op_int, 4076 #endif 4077 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4078 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4079 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4080 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4081 #ifdef CONFIG_SFC_SRIOV 4082 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4083 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4084 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4085 #endif 4086 .get_mac_address = efx_ef10_get_mac_address_vf, 4087 .set_mac_address = efx_ef10_set_mac_address, 4088 4089 .get_phys_port_id = efx_ef10_get_phys_port_id, 4090 .revision = EFX_REV_HUNT_A0, 4091 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4092 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4093 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4094 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4095 .can_rx_scatter = true, 4096 .always_rx_scatter = true, 4097 .min_interrupt_mode = EFX_INT_MODE_MSIX, 4098 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4099 .offload_features = EF10_OFFLOAD_FEATURES, 4100 .mcdi_max_ver = 2, 4101 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4102 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4103 1 << HWTSTAMP_FILTER_ALL, 4104 .rx_hash_key_size = 40, 4105 .check_caps = ef10_check_caps, 4106 .print_additional_fwver = efx_ef10_print_additional_fwver, 4107 .sensor_event = efx_mcdi_sensor_event, 4108 }; 4109 4110 const struct efx_nic_type efx_hunt_a0_nic_type = { 4111 .is_vf = false, 4112 .mem_bar = efx_ef10_pf_mem_bar, 4113 .mem_map_size = efx_ef10_mem_map_size, 4114 .probe = efx_ef10_probe_pf, 4115 .remove = efx_ef10_remove, 4116 .dimension_resources = efx_ef10_dimension_resources, 4117 .init = efx_ef10_init_nic, 4118 .fini = efx_ef10_fini_nic, 4119 .map_reset_reason = efx_ef10_map_reset_reason, 4120 .map_reset_flags = efx_ef10_map_reset_flags, 4121 .reset = efx_ef10_reset, 4122 .probe_port = efx_mcdi_port_probe, 4123 .remove_port = efx_mcdi_port_remove, 4124 .fini_dmaq = efx_fini_dmaq, 4125 .prepare_flr = efx_ef10_prepare_flr, 4126 .finish_flr = efx_port_dummy_op_void, 4127 .describe_stats = efx_ef10_describe_stats, 4128 .update_stats = efx_ef10_update_stats_pf, 4129 .start_stats = efx_mcdi_mac_start_stats, 4130 .pull_stats = efx_mcdi_mac_pull_stats, 4131 .stop_stats = efx_mcdi_mac_stop_stats, 4132 .push_irq_moderation = efx_ef10_push_irq_moderation, 4133 .reconfigure_mac = efx_ef10_mac_reconfigure, 4134 .check_mac_fault = efx_mcdi_mac_check_fault, 4135 .reconfigure_port = efx_mcdi_port_reconfigure, 4136 .get_wol = efx_ef10_get_wol, 4137 .set_wol = efx_ef10_set_wol, 4138 .resume_wol = efx_port_dummy_op_void, 4139 .get_fec_stats = efx_ef10_get_fec_stats, 4140 .test_chip = efx_ef10_test_chip, 4141 .test_nvram = efx_mcdi_nvram_test_all, 4142 .mcdi_request = efx_ef10_mcdi_request, 4143 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4144 .mcdi_read_response = efx_ef10_mcdi_read_response, 4145 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4146 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4147 .irq_enable_master = efx_port_dummy_op_void, 4148 .irq_test_generate = efx_ef10_irq_test_generate, 4149 .irq_disable_non_ev = efx_port_dummy_op_void, 4150 .irq_handle_msi = efx_ef10_msi_interrupt, 4151 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4152 .tx_probe = efx_ef10_tx_probe, 4153 .tx_init = efx_ef10_tx_init, 4154 .tx_remove = efx_mcdi_tx_remove, 4155 .tx_write = efx_ef10_tx_write, 4156 .tx_limit_len = efx_ef10_tx_limit_len, 4157 .tx_enqueue = __efx_enqueue_skb, 4158 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 4159 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4160 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 4161 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 4162 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 4163 .rx_probe = efx_mcdi_rx_probe, 4164 .rx_init = efx_mcdi_rx_init, 4165 .rx_remove = efx_mcdi_rx_remove, 4166 .rx_write = efx_ef10_rx_write, 4167 .rx_defer_refill = efx_ef10_rx_defer_refill, 4168 .rx_packet = __efx_rx_packet, 4169 .ev_probe = efx_mcdi_ev_probe, 4170 .ev_init = efx_ef10_ev_init, 4171 .ev_fini = efx_mcdi_ev_fini, 4172 .ev_remove = efx_mcdi_ev_remove, 4173 .ev_process = efx_ef10_ev_process, 4174 .ev_read_ack = efx_ef10_ev_read_ack, 4175 .ev_test_generate = efx_ef10_ev_test_generate, 4176 .filter_table_probe = efx_ef10_filter_table_probe, 4177 .filter_table_restore = efx_mcdi_filter_table_restore, 4178 .filter_table_remove = efx_mcdi_filter_table_remove, 4179 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4180 .filter_insert = efx_mcdi_filter_insert, 4181 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4182 .filter_get_safe = efx_mcdi_filter_get_safe, 4183 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4184 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4185 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4186 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4187 #ifdef CONFIG_RFS_ACCEL 4188 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4189 #endif 4190 #ifdef CONFIG_SFC_MTD 4191 .mtd_probe = efx_ef10_mtd_probe, 4192 .mtd_rename = efx_mcdi_mtd_rename, 4193 .mtd_read = efx_mcdi_mtd_read, 4194 .mtd_erase = efx_mcdi_mtd_erase, 4195 .mtd_write = efx_mcdi_mtd_write, 4196 .mtd_sync = efx_mcdi_mtd_sync, 4197 #endif 4198 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4199 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4200 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4201 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4202 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4203 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports, 4204 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port, 4205 #ifdef CONFIG_SFC_SRIOV 4206 .sriov_configure = efx_ef10_sriov_configure, 4207 .sriov_init = efx_ef10_sriov_init, 4208 .sriov_fini = efx_ef10_sriov_fini, 4209 .sriov_wanted = efx_ef10_sriov_wanted, 4210 .sriov_reset = efx_ef10_sriov_reset, 4211 .sriov_flr = efx_ef10_sriov_flr, 4212 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4213 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4214 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4215 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4216 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4217 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4218 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4219 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4220 #endif 4221 .get_mac_address = efx_ef10_get_mac_address_pf, 4222 .set_mac_address = efx_ef10_set_mac_address, 4223 .tso_versions = efx_ef10_tso_versions, 4224 4225 .get_phys_port_id = efx_ef10_get_phys_port_id, 4226 .revision = EFX_REV_HUNT_A0, 4227 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4228 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4229 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4230 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4231 .can_rx_scatter = true, 4232 .always_rx_scatter = true, 4233 .option_descriptors = true, 4234 .min_interrupt_mode = EFX_INT_MODE_LEGACY, 4235 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4236 .offload_features = EF10_OFFLOAD_FEATURES, 4237 .mcdi_max_ver = 2, 4238 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4239 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4240 1 << HWTSTAMP_FILTER_ALL, 4241 .rx_hash_key_size = 40, 4242 .check_caps = ef10_check_caps, 4243 .print_additional_fwver = efx_ef10_print_additional_fwver, 4244 .sensor_event = efx_mcdi_sensor_event, 4245 }; 4246