1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2012-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 #include "net_driver.h" 11 #include "ef10_regs.h" 12 #include "io.h" 13 #include "mcdi.h" 14 #include "mcdi_pcol.h" 15 #include "nic.h" 16 #include "workarounds.h" 17 #include "selftest.h" 18 #include "ef10_sriov.h" 19 #include <linux/in.h> 20 #include <linux/jhash.h> 21 #include <linux/wait.h> 22 #include <linux/workqueue.h> 23 24 /* Hardware control for EF10 architecture including 'Huntington'. */ 25 26 #define EFX_EF10_DRVGEN_EV 7 27 enum { 28 EFX_EF10_TEST = 1, 29 EFX_EF10_REFILL, 30 }; 31 32 /* The reserved RSS context value */ 33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff 34 /* The maximum size of a shared RSS context */ 35 /* TODO: this should really be from the mcdi protocol export */ 36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL 37 38 /* The filter table(s) are managed by firmware and we have write-only 39 * access. When removing filters we must identify them to the 40 * firmware by a 64-bit handle, but this is too wide for Linux kernel 41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to 42 * be able to tell in advance whether a requested insertion will 43 * replace an existing filter. Therefore we maintain a software hash 44 * table, which should be at least as large as the hardware hash 45 * table. 46 * 47 * Huntington has a single 8K filter table shared between all filter 48 * types and both ports. 49 */ 50 #define HUNT_FILTER_TBL_ROWS 8192 51 52 #define EFX_EF10_FILTER_ID_INVALID 0xffff 53 struct efx_ef10_dev_addr { 54 u8 addr[ETH_ALEN]; 55 u16 id; 56 }; 57 58 struct efx_ef10_filter_table { 59 /* The RX match field masks supported by this fw & hw, in order of priority */ 60 enum efx_filter_match_flags rx_match_flags[ 61 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM]; 62 unsigned int rx_match_count; 63 64 struct { 65 unsigned long spec; /* pointer to spec plus flag bits */ 66 /* BUSY flag indicates that an update is in progress. AUTO_OLD is 67 * used to mark and sweep MAC filters for the device address lists. 68 */ 69 #define EFX_EF10_FILTER_FLAG_BUSY 1UL 70 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL 71 #define EFX_EF10_FILTER_FLAGS 3UL 72 u64 handle; /* firmware handle */ 73 } *entry; 74 wait_queue_head_t waitq; 75 /* Shadow of net_device address lists, guarded by mac_lock */ 76 #define EFX_EF10_FILTER_DEV_UC_MAX 32 77 #define EFX_EF10_FILTER_DEV_MC_MAX 256 78 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX]; 79 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX]; 80 int dev_uc_count; 81 int dev_mc_count; 82 /* Indices (like efx_ef10_dev_addr.id) for promisc/allmulti filters */ 83 u16 ucdef_id; 84 u16 bcast_id; 85 u16 mcdef_id; 86 }; 87 88 /* An arbitrary search limit for the software hash table */ 89 #define EFX_EF10_FILTER_SEARCH_LIMIT 200 90 91 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx); 92 static void efx_ef10_filter_table_remove(struct efx_nic *efx); 93 94 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 95 { 96 efx_dword_t reg; 97 98 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 99 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 100 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 101 } 102 103 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 104 { 105 int bar; 106 107 bar = efx->type->mem_bar; 108 return resource_size(&efx->pci_dev->resource[bar]); 109 } 110 111 static bool efx_ef10_is_vf(struct efx_nic *efx) 112 { 113 return efx->type->is_vf; 114 } 115 116 static int efx_ef10_get_pf_index(struct efx_nic *efx) 117 { 118 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 119 struct efx_ef10_nic_data *nic_data = efx->nic_data; 120 size_t outlen; 121 int rc; 122 123 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 124 sizeof(outbuf), &outlen); 125 if (rc) 126 return rc; 127 if (outlen < sizeof(outbuf)) 128 return -EIO; 129 130 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF); 131 return 0; 132 } 133 134 #ifdef CONFIG_SFC_SRIOV 135 static int efx_ef10_get_vf_index(struct efx_nic *efx) 136 { 137 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 138 struct efx_ef10_nic_data *nic_data = efx->nic_data; 139 size_t outlen; 140 int rc; 141 142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 143 sizeof(outbuf), &outlen); 144 if (rc) 145 return rc; 146 if (outlen < sizeof(outbuf)) 147 return -EIO; 148 149 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 150 return 0; 151 } 152 #endif 153 154 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 155 { 156 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN); 157 struct efx_ef10_nic_data *nic_data = efx->nic_data; 158 size_t outlen; 159 int rc; 160 161 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 162 163 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 164 outbuf, sizeof(outbuf), &outlen); 165 if (rc) 166 return rc; 167 if (outlen < sizeof(outbuf)) { 168 netif_err(efx, drv, efx->net_dev, 169 "unable to read datapath firmware capabilities\n"); 170 return -EIO; 171 } 172 173 nic_data->datapath_caps = 174 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 175 176 /* record the DPCPU firmware IDs to determine VEB vswitching support. 177 */ 178 nic_data->rx_dpcpu_fw_id = 179 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 180 nic_data->tx_dpcpu_fw_id = 181 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 182 183 if (!(nic_data->datapath_caps & 184 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 185 netif_err(efx, probe, efx->net_dev, 186 "current firmware does not support an RX prefix\n"); 187 return -ENODEV; 188 } 189 190 return 0; 191 } 192 193 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 194 { 195 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 196 int rc; 197 198 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 199 outbuf, sizeof(outbuf), NULL); 200 if (rc) 201 return rc; 202 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 203 return rc > 0 ? rc : -ERANGE; 204 } 205 206 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 207 { 208 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 209 size_t outlen; 210 int rc; 211 212 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 213 214 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 215 outbuf, sizeof(outbuf), &outlen); 216 if (rc) 217 return rc; 218 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 219 return -EIO; 220 221 ether_addr_copy(mac_address, 222 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 223 return 0; 224 } 225 226 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 227 { 228 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 229 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 230 size_t outlen; 231 int num_addrs, rc; 232 233 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 234 EVB_PORT_ID_ASSIGNED); 235 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 236 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 237 238 if (rc) 239 return rc; 240 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 241 return -EIO; 242 243 num_addrs = MCDI_DWORD(outbuf, 244 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 245 246 WARN_ON(num_addrs != 1); 247 248 ether_addr_copy(mac_address, 249 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 250 251 return 0; 252 } 253 254 static ssize_t efx_ef10_show_link_control_flag(struct device *dev, 255 struct device_attribute *attr, 256 char *buf) 257 { 258 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 259 260 return sprintf(buf, "%d\n", 261 ((efx->mcdi->fn_flags) & 262 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 263 ? 1 : 0); 264 } 265 266 static ssize_t efx_ef10_show_primary_flag(struct device *dev, 267 struct device_attribute *attr, 268 char *buf) 269 { 270 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 271 272 return sprintf(buf, "%d\n", 273 ((efx->mcdi->fn_flags) & 274 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 275 ? 1 : 0); 276 } 277 278 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag, 279 NULL); 280 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL); 281 282 static int efx_ef10_probe(struct efx_nic *efx) 283 { 284 struct efx_ef10_nic_data *nic_data; 285 struct net_device *net_dev = efx->net_dev; 286 int i, rc; 287 288 /* We can have one VI for each 8K region. However, until we 289 * use TX option descriptors we need two TX queues per channel. 290 */ 291 efx->max_channels = min_t(unsigned int, 292 EFX_MAX_CHANNELS, 293 efx_ef10_mem_map_size(efx) / 294 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES)); 295 efx->max_tx_channels = efx->max_channels; 296 if (WARN_ON(efx->max_channels == 0)) 297 return -EIO; 298 299 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 300 if (!nic_data) 301 return -ENOMEM; 302 efx->nic_data = nic_data; 303 304 /* we assume later that we can copy from this buffer in dwords */ 305 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 306 307 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 308 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 309 if (rc) 310 goto fail1; 311 312 /* Get the MC's warm boot count. In case it's rebooting right 313 * now, be prepared to retry. 314 */ 315 i = 0; 316 for (;;) { 317 rc = efx_ef10_get_warm_boot_count(efx); 318 if (rc >= 0) 319 break; 320 if (++i == 5) 321 goto fail2; 322 ssleep(1); 323 } 324 nic_data->warm_boot_count = rc; 325 326 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 327 328 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 329 330 /* In case we're recovering from a crash (kexec), we want to 331 * cancel any outstanding request by the previous user of this 332 * function. We send a special message using the least 333 * significant bits of the 'high' (doorbell) register. 334 */ 335 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 336 337 rc = efx_mcdi_init(efx); 338 if (rc) 339 goto fail2; 340 341 /* Reset (most) configuration for this function */ 342 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 343 if (rc) 344 goto fail3; 345 346 /* Enable event logging */ 347 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 348 if (rc) 349 goto fail3; 350 351 rc = device_create_file(&efx->pci_dev->dev, 352 &dev_attr_link_control_flag); 353 if (rc) 354 goto fail3; 355 356 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 357 if (rc) 358 goto fail4; 359 360 rc = efx_ef10_get_pf_index(efx); 361 if (rc) 362 goto fail5; 363 364 rc = efx_ef10_init_datapath_caps(efx); 365 if (rc < 0) 366 goto fail5; 367 368 efx->rx_packet_len_offset = 369 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 370 371 rc = efx_mcdi_port_get_number(efx); 372 if (rc < 0) 373 goto fail5; 374 efx->port_num = rc; 375 net_dev->dev_port = rc; 376 377 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 378 if (rc) 379 goto fail5; 380 381 rc = efx_ef10_get_sysclk_freq(efx); 382 if (rc < 0) 383 goto fail5; 384 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */ 385 386 /* Check whether firmware supports bug 35388 workaround. 387 * First try to enable it, then if we get EPERM, just 388 * ask if it's already enabled 389 */ 390 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL); 391 if (rc == 0) { 392 nic_data->workaround_35388 = true; 393 } else if (rc == -EPERM) { 394 unsigned int enabled; 395 396 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled); 397 if (rc) 398 goto fail3; 399 nic_data->workaround_35388 = enabled & 400 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388; 401 } else if (rc != -ENOSYS && rc != -ENOENT) { 402 goto fail5; 403 } 404 netif_dbg(efx, probe, efx->net_dev, 405 "workaround for bug 35388 is %sabled\n", 406 nic_data->workaround_35388 ? "en" : "dis"); 407 408 rc = efx_mcdi_mon_probe(efx); 409 if (rc && rc != -EPERM) 410 goto fail5; 411 412 efx_ptp_probe(efx, NULL); 413 414 #ifdef CONFIG_SFC_SRIOV 415 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 416 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 417 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 418 419 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 420 } else 421 #endif 422 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 423 424 return 0; 425 426 fail5: 427 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 428 fail4: 429 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 430 fail3: 431 efx_mcdi_fini(efx); 432 fail2: 433 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 434 fail1: 435 kfree(nic_data); 436 efx->nic_data = NULL; 437 return rc; 438 } 439 440 static int efx_ef10_free_vis(struct efx_nic *efx) 441 { 442 MCDI_DECLARE_BUF_ERR(outbuf); 443 size_t outlen; 444 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, 445 outbuf, sizeof(outbuf), &outlen); 446 447 /* -EALREADY means nothing to free, so ignore */ 448 if (rc == -EALREADY) 449 rc = 0; 450 if (rc) 451 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, 452 rc); 453 return rc; 454 } 455 456 #ifdef EFX_USE_PIO 457 458 static void efx_ef10_free_piobufs(struct efx_nic *efx) 459 { 460 struct efx_ef10_nic_data *nic_data = efx->nic_data; 461 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 462 unsigned int i; 463 int rc; 464 465 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 466 467 for (i = 0; i < nic_data->n_piobufs; i++) { 468 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 469 nic_data->piobuf_handle[i]); 470 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 471 NULL, 0, NULL); 472 WARN_ON(rc); 473 } 474 475 nic_data->n_piobufs = 0; 476 } 477 478 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 479 { 480 struct efx_ef10_nic_data *nic_data = efx->nic_data; 481 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 482 unsigned int i; 483 size_t outlen; 484 int rc = 0; 485 486 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 487 488 for (i = 0; i < n; i++) { 489 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 490 outbuf, sizeof(outbuf), &outlen); 491 if (rc) { 492 /* Don't display the MC error if we didn't have space 493 * for a VF. 494 */ 495 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC)) 496 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF, 497 0, outbuf, outlen, rc); 498 break; 499 } 500 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 501 rc = -EIO; 502 break; 503 } 504 nic_data->piobuf_handle[i] = 505 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 506 netif_dbg(efx, probe, efx->net_dev, 507 "allocated PIO buffer %u handle %x\n", i, 508 nic_data->piobuf_handle[i]); 509 } 510 511 nic_data->n_piobufs = i; 512 if (rc) 513 efx_ef10_free_piobufs(efx); 514 return rc; 515 } 516 517 static int efx_ef10_link_piobufs(struct efx_nic *efx) 518 { 519 struct efx_ef10_nic_data *nic_data = efx->nic_data; 520 _MCDI_DECLARE_BUF(inbuf, 521 max(MC_CMD_LINK_PIOBUF_IN_LEN, 522 MC_CMD_UNLINK_PIOBUF_IN_LEN)); 523 struct efx_channel *channel; 524 struct efx_tx_queue *tx_queue; 525 unsigned int offset, index; 526 int rc; 527 528 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 529 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 530 531 memset(inbuf, 0, sizeof(inbuf)); 532 533 /* Link a buffer to each VI in the write-combining mapping */ 534 for (index = 0; index < nic_data->n_piobufs; ++index) { 535 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 536 nic_data->piobuf_handle[index]); 537 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 538 nic_data->pio_write_vi_base + index); 539 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 540 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 541 NULL, 0, NULL); 542 if (rc) { 543 netif_err(efx, drv, efx->net_dev, 544 "failed to link VI %u to PIO buffer %u (%d)\n", 545 nic_data->pio_write_vi_base + index, index, 546 rc); 547 goto fail; 548 } 549 netif_dbg(efx, probe, efx->net_dev, 550 "linked VI %u to PIO buffer %u\n", 551 nic_data->pio_write_vi_base + index, index); 552 } 553 554 /* Link a buffer to each TX queue */ 555 efx_for_each_channel(channel, efx) { 556 efx_for_each_channel_tx_queue(tx_queue, channel) { 557 /* We assign the PIO buffers to queues in 558 * reverse order to allow for the following 559 * special case. 560 */ 561 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 562 tx_queue->channel->channel - 1) * 563 efx_piobuf_size); 564 index = offset / ER_DZ_TX_PIOBUF_SIZE; 565 offset = offset % ER_DZ_TX_PIOBUF_SIZE; 566 567 /* When the host page size is 4K, the first 568 * host page in the WC mapping may be within 569 * the same VI page as the last TX queue. We 570 * can only link one buffer to each VI. 571 */ 572 if (tx_queue->queue == nic_data->pio_write_vi_base) { 573 BUG_ON(index != 0); 574 rc = 0; 575 } else { 576 MCDI_SET_DWORD(inbuf, 577 LINK_PIOBUF_IN_PIOBUF_HANDLE, 578 nic_data->piobuf_handle[index]); 579 MCDI_SET_DWORD(inbuf, 580 LINK_PIOBUF_IN_TXQ_INSTANCE, 581 tx_queue->queue); 582 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 583 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 584 NULL, 0, NULL); 585 } 586 587 if (rc) { 588 /* This is non-fatal; the TX path just 589 * won't use PIO for this queue 590 */ 591 netif_err(efx, drv, efx->net_dev, 592 "failed to link VI %u to PIO buffer %u (%d)\n", 593 tx_queue->queue, index, rc); 594 tx_queue->piobuf = NULL; 595 } else { 596 tx_queue->piobuf = 597 nic_data->pio_write_base + 598 index * EFX_VI_PAGE_SIZE + offset; 599 tx_queue->piobuf_offset = offset; 600 netif_dbg(efx, probe, efx->net_dev, 601 "linked VI %u to PIO buffer %u offset %x addr %p\n", 602 tx_queue->queue, index, 603 tx_queue->piobuf_offset, 604 tx_queue->piobuf); 605 } 606 } 607 } 608 609 return 0; 610 611 fail: 612 while (index--) { 613 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 614 nic_data->pio_write_vi_base + index); 615 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 616 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 617 NULL, 0, NULL); 618 } 619 return rc; 620 } 621 622 #else /* !EFX_USE_PIO */ 623 624 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 625 { 626 return n == 0 ? 0 : -ENOBUFS; 627 } 628 629 static int efx_ef10_link_piobufs(struct efx_nic *efx) 630 { 631 return 0; 632 } 633 634 static void efx_ef10_free_piobufs(struct efx_nic *efx) 635 { 636 } 637 638 #endif /* EFX_USE_PIO */ 639 640 static void efx_ef10_remove(struct efx_nic *efx) 641 { 642 struct efx_ef10_nic_data *nic_data = efx->nic_data; 643 int rc; 644 645 #ifdef CONFIG_SFC_SRIOV 646 struct efx_ef10_nic_data *nic_data_pf; 647 struct pci_dev *pci_dev_pf; 648 struct efx_nic *efx_pf; 649 struct ef10_vf *vf; 650 651 if (efx->pci_dev->is_virtfn) { 652 pci_dev_pf = efx->pci_dev->physfn; 653 if (pci_dev_pf) { 654 efx_pf = pci_get_drvdata(pci_dev_pf); 655 nic_data_pf = efx_pf->nic_data; 656 vf = nic_data_pf->vf + nic_data->vf_index; 657 vf->efx = NULL; 658 } else 659 netif_info(efx, drv, efx->net_dev, 660 "Could not get the PF id from VF\n"); 661 } 662 #endif 663 664 efx_ptp_remove(efx); 665 666 efx_mcdi_mon_remove(efx); 667 668 efx_ef10_rx_free_indir_table(efx); 669 670 if (nic_data->wc_membase) 671 iounmap(nic_data->wc_membase); 672 673 rc = efx_ef10_free_vis(efx); 674 WARN_ON(rc != 0); 675 676 if (!nic_data->must_restore_piobufs) 677 efx_ef10_free_piobufs(efx); 678 679 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 680 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 681 682 efx_mcdi_fini(efx); 683 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 684 kfree(nic_data); 685 } 686 687 static int efx_ef10_probe_pf(struct efx_nic *efx) 688 { 689 return efx_ef10_probe(efx); 690 } 691 692 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 693 { 694 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 695 696 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 697 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 698 NULL, 0, NULL); 699 } 700 701 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 702 { 703 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 704 705 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 706 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 707 NULL, 0, NULL); 708 } 709 710 int efx_ef10_vport_add_mac(struct efx_nic *efx, 711 unsigned int port_id, u8 *mac) 712 { 713 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 714 715 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 716 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 717 718 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 719 sizeof(inbuf), NULL, 0, NULL); 720 } 721 722 int efx_ef10_vport_del_mac(struct efx_nic *efx, 723 unsigned int port_id, u8 *mac) 724 { 725 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 726 727 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 728 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 729 730 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 731 sizeof(inbuf), NULL, 0, NULL); 732 } 733 734 #ifdef CONFIG_SFC_SRIOV 735 static int efx_ef10_probe_vf(struct efx_nic *efx) 736 { 737 int rc; 738 struct pci_dev *pci_dev_pf; 739 740 /* If the parent PF has no VF data structure, it doesn't know about this 741 * VF so fail probe. The VF needs to be re-created. This can happen 742 * if the PF driver is unloaded while the VF is assigned to a guest. 743 */ 744 pci_dev_pf = efx->pci_dev->physfn; 745 if (pci_dev_pf) { 746 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 747 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 748 749 if (!nic_data_pf->vf) { 750 netif_info(efx, drv, efx->net_dev, 751 "The VF cannot link to its parent PF; " 752 "please destroy and re-create the VF\n"); 753 return -EBUSY; 754 } 755 } 756 757 rc = efx_ef10_probe(efx); 758 if (rc) 759 return rc; 760 761 rc = efx_ef10_get_vf_index(efx); 762 if (rc) 763 goto fail; 764 765 if (efx->pci_dev->is_virtfn) { 766 if (efx->pci_dev->physfn) { 767 struct efx_nic *efx_pf = 768 pci_get_drvdata(efx->pci_dev->physfn); 769 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 770 struct efx_ef10_nic_data *nic_data = efx->nic_data; 771 772 nic_data_p->vf[nic_data->vf_index].efx = efx; 773 nic_data_p->vf[nic_data->vf_index].pci_dev = 774 efx->pci_dev; 775 } else 776 netif_info(efx, drv, efx->net_dev, 777 "Could not get the PF id from VF\n"); 778 } 779 780 return 0; 781 782 fail: 783 efx_ef10_remove(efx); 784 return rc; 785 } 786 #else 787 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 788 { 789 return 0; 790 } 791 #endif 792 793 static int efx_ef10_alloc_vis(struct efx_nic *efx, 794 unsigned int min_vis, unsigned int max_vis) 795 { 796 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); 797 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); 798 struct efx_ef10_nic_data *nic_data = efx->nic_data; 799 size_t outlen; 800 int rc; 801 802 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); 803 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); 804 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), 805 outbuf, sizeof(outbuf), &outlen); 806 if (rc != 0) 807 return rc; 808 809 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) 810 return -EIO; 811 812 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", 813 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); 814 815 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); 816 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); 817 return 0; 818 } 819 820 /* Note that the failure path of this function does not free 821 * resources, as this will be done by efx_ef10_remove(). 822 */ 823 static int efx_ef10_dimension_resources(struct efx_nic *efx) 824 { 825 struct efx_ef10_nic_data *nic_data = efx->nic_data; 826 unsigned int uc_mem_map_size, wc_mem_map_size; 827 unsigned int min_vis = max(EFX_TXQ_TYPES, 828 efx_separate_tx_channels ? 2 : 1); 829 unsigned int channel_vis, pio_write_vi_base, max_vis; 830 void __iomem *membase; 831 int rc; 832 833 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); 834 835 #ifdef EFX_USE_PIO 836 /* Try to allocate PIO buffers if wanted and if the full 837 * number of PIO buffers would be sufficient to allocate one 838 * copy-buffer per TX channel. Failure is non-fatal, as there 839 * are only a small number of PIO buffers shared between all 840 * functions of the controller. 841 */ 842 if (efx_piobuf_size != 0 && 843 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 844 efx->n_tx_channels) { 845 unsigned int n_piobufs = 846 DIV_ROUND_UP(efx->n_tx_channels, 847 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size); 848 849 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 850 if (rc) 851 netif_err(efx, probe, efx->net_dev, 852 "failed to allocate PIO buffers (%d)\n", rc); 853 else 854 netif_dbg(efx, probe, efx->net_dev, 855 "allocated %u PIO buffers\n", n_piobufs); 856 } 857 #else 858 nic_data->n_piobufs = 0; 859 #endif 860 861 /* PIO buffers should be mapped with write-combining enabled, 862 * and we want to make single UC and WC mappings rather than 863 * several of each (in fact that's the only option if host 864 * page size is >4K). So we may allocate some extra VIs just 865 * for writing PIO buffers through. 866 * 867 * The UC mapping contains (channel_vis - 1) complete VIs and the 868 * first half of the next VI. Then the WC mapping begins with 869 * the second half of this last VI. 870 */ 871 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE + 872 ER_DZ_TX_PIOBUF); 873 if (nic_data->n_piobufs) { 874 /* pio_write_vi_base rounds down to give the number of complete 875 * VIs inside the UC mapping. 876 */ 877 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; 878 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 879 nic_data->n_piobufs) * 880 EFX_VI_PAGE_SIZE) - 881 uc_mem_map_size); 882 max_vis = pio_write_vi_base + nic_data->n_piobufs; 883 } else { 884 pio_write_vi_base = 0; 885 wc_mem_map_size = 0; 886 max_vis = channel_vis; 887 } 888 889 /* In case the last attached driver failed to free VIs, do it now */ 890 rc = efx_ef10_free_vis(efx); 891 if (rc != 0) 892 return rc; 893 894 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 895 if (rc != 0) 896 return rc; 897 898 if (nic_data->n_allocated_vis < channel_vis) { 899 netif_info(efx, drv, efx->net_dev, 900 "Could not allocate enough VIs to satisfy RSS" 901 " requirements. Performance may not be optimal.\n"); 902 /* We didn't get the VIs to populate our channels. 903 * We could keep what we got but then we'd have more 904 * interrupts than we need. 905 * Instead calculate new max_channels and restart 906 */ 907 efx->max_channels = nic_data->n_allocated_vis; 908 efx->max_tx_channels = 909 nic_data->n_allocated_vis / EFX_TXQ_TYPES; 910 911 efx_ef10_free_vis(efx); 912 return -EAGAIN; 913 } 914 915 /* If we didn't get enough VIs to map all the PIO buffers, free the 916 * PIO buffers 917 */ 918 if (nic_data->n_piobufs && 919 nic_data->n_allocated_vis < 920 pio_write_vi_base + nic_data->n_piobufs) { 921 netif_dbg(efx, probe, efx->net_dev, 922 "%u VIs are not sufficient to map %u PIO buffers\n", 923 nic_data->n_allocated_vis, nic_data->n_piobufs); 924 efx_ef10_free_piobufs(efx); 925 } 926 927 /* Shrink the original UC mapping of the memory BAR */ 928 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); 929 if (!membase) { 930 netif_err(efx, probe, efx->net_dev, 931 "could not shrink memory BAR to %x\n", 932 uc_mem_map_size); 933 return -ENOMEM; 934 } 935 iounmap(efx->membase); 936 efx->membase = membase; 937 938 /* Set up the WC mapping if needed */ 939 if (wc_mem_map_size) { 940 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 941 uc_mem_map_size, 942 wc_mem_map_size); 943 if (!nic_data->wc_membase) { 944 netif_err(efx, probe, efx->net_dev, 945 "could not allocate WC mapping of size %x\n", 946 wc_mem_map_size); 947 return -ENOMEM; 948 } 949 nic_data->pio_write_vi_base = pio_write_vi_base; 950 nic_data->pio_write_base = 951 nic_data->wc_membase + 952 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF - 953 uc_mem_map_size); 954 955 rc = efx_ef10_link_piobufs(efx); 956 if (rc) 957 efx_ef10_free_piobufs(efx); 958 } 959 960 netif_dbg(efx, probe, efx->net_dev, 961 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 962 &efx->membase_phys, efx->membase, uc_mem_map_size, 963 nic_data->wc_membase, wc_mem_map_size); 964 965 return 0; 966 } 967 968 static int efx_ef10_init_nic(struct efx_nic *efx) 969 { 970 struct efx_ef10_nic_data *nic_data = efx->nic_data; 971 int rc; 972 973 if (nic_data->must_check_datapath_caps) { 974 rc = efx_ef10_init_datapath_caps(efx); 975 if (rc) 976 return rc; 977 nic_data->must_check_datapath_caps = false; 978 } 979 980 if (nic_data->must_realloc_vis) { 981 /* We cannot let the number of VIs change now */ 982 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 983 nic_data->n_allocated_vis); 984 if (rc) 985 return rc; 986 nic_data->must_realloc_vis = false; 987 } 988 989 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 990 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 991 if (rc == 0) { 992 rc = efx_ef10_link_piobufs(efx); 993 if (rc) 994 efx_ef10_free_piobufs(efx); 995 } 996 997 /* Log an error on failure, but this is non-fatal */ 998 if (rc) 999 netif_err(efx, drv, efx->net_dev, 1000 "failed to restore PIO buffers (%d)\n", rc); 1001 nic_data->must_restore_piobufs = false; 1002 } 1003 1004 /* don't fail init if RSS setup doesn't work */ 1005 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table); 1006 1007 return 0; 1008 } 1009 1010 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx) 1011 { 1012 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1013 #ifdef CONFIG_SFC_SRIOV 1014 unsigned int i; 1015 #endif 1016 1017 /* All our allocations have been reset */ 1018 nic_data->must_realloc_vis = true; 1019 nic_data->must_restore_filters = true; 1020 nic_data->must_restore_piobufs = true; 1021 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 1022 1023 /* Driver-created vswitches and vports must be re-created */ 1024 nic_data->must_probe_vswitching = true; 1025 nic_data->vport_id = EVB_PORT_ID_ASSIGNED; 1026 #ifdef CONFIG_SFC_SRIOV 1027 if (nic_data->vf) 1028 for (i = 0; i < efx->vf_count; i++) 1029 nic_data->vf[i].vport_id = 0; 1030 #endif 1031 } 1032 1033 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1034 { 1035 if (reason == RESET_TYPE_MC_FAILURE) 1036 return RESET_TYPE_DATAPATH; 1037 1038 return efx_mcdi_map_reset_reason(reason); 1039 } 1040 1041 static int efx_ef10_map_reset_flags(u32 *flags) 1042 { 1043 enum { 1044 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1045 ETH_RESET_SHARED_SHIFT), 1046 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1047 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1048 ETH_RESET_PHY | ETH_RESET_MGMT) << 1049 ETH_RESET_SHARED_SHIFT) 1050 }; 1051 1052 /* We assume for now that our PCI function is permitted to 1053 * reset everything. 1054 */ 1055 1056 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1057 *flags &= ~EF10_RESET_MC; 1058 return RESET_TYPE_WORLD; 1059 } 1060 1061 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1062 *flags &= ~EF10_RESET_PORT; 1063 return RESET_TYPE_ALL; 1064 } 1065 1066 /* no invisible reset implemented */ 1067 1068 return -EINVAL; 1069 } 1070 1071 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1072 { 1073 int rc = efx_mcdi_reset(efx, reset_type); 1074 1075 /* Unprivileged functions return -EPERM, but need to return success 1076 * here so that the datapath is brought back up. 1077 */ 1078 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1079 rc = 0; 1080 1081 /* If it was a port reset, trigger reallocation of MC resources. 1082 * Note that on an MC reset nothing needs to be done now because we'll 1083 * detect the MC reset later and handle it then. 1084 * For an FLR, we never get an MC reset event, but the MC has reset all 1085 * resources assigned to us, so we have to trigger reallocation now. 1086 */ 1087 if ((reset_type == RESET_TYPE_ALL || 1088 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1089 efx_ef10_reset_mc_allocations(efx); 1090 return rc; 1091 } 1092 1093 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1094 [EF10_STAT_ ## ext_name] = \ 1095 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1096 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1097 [EF10_STAT_ ## int_name] = \ 1098 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1099 #define EF10_OTHER_STAT(ext_name) \ 1100 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1101 #define GENERIC_SW_STAT(ext_name) \ 1102 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1103 1104 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1105 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1106 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1107 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1108 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1109 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1110 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1111 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1112 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1113 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1114 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1115 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1116 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1117 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1118 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1119 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1120 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1121 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1122 EF10_OTHER_STAT(port_rx_good_bytes), 1123 EF10_OTHER_STAT(port_rx_bad_bytes), 1124 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1125 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1126 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1127 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1128 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1129 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1130 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1131 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1132 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1133 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1134 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1135 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1136 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1137 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1138 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1139 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1140 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1141 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1142 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1143 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1144 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1145 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1146 GENERIC_SW_STAT(rx_nodesc_trunc), 1147 GENERIC_SW_STAT(rx_noskb_drops), 1148 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1149 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1150 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1151 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1152 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1153 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1154 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1155 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1156 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1157 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1158 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1159 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1160 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1161 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1162 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1163 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1164 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1165 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1166 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1167 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1168 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1169 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1170 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1171 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1172 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1173 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1174 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1175 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1176 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1177 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1178 }; 1179 1180 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1181 (1ULL << EF10_STAT_port_tx_packets) | \ 1182 (1ULL << EF10_STAT_port_tx_pause) | \ 1183 (1ULL << EF10_STAT_port_tx_unicast) | \ 1184 (1ULL << EF10_STAT_port_tx_multicast) | \ 1185 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1186 (1ULL << EF10_STAT_port_rx_bytes) | \ 1187 (1ULL << \ 1188 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1189 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1190 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1191 (1ULL << EF10_STAT_port_rx_packets) | \ 1192 (1ULL << EF10_STAT_port_rx_good) | \ 1193 (1ULL << EF10_STAT_port_rx_bad) | \ 1194 (1ULL << EF10_STAT_port_rx_pause) | \ 1195 (1ULL << EF10_STAT_port_rx_control) | \ 1196 (1ULL << EF10_STAT_port_rx_unicast) | \ 1197 (1ULL << EF10_STAT_port_rx_multicast) | \ 1198 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1199 (1ULL << EF10_STAT_port_rx_lt64) | \ 1200 (1ULL << EF10_STAT_port_rx_64) | \ 1201 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1202 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1203 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1204 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1205 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1206 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1207 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1208 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1209 (1ULL << EF10_STAT_port_rx_overflow) | \ 1210 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1211 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1212 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1213 1214 /* These statistics are only provided by the 10G MAC. For a 10G/40G 1215 * switchable port we do not expose these because they might not 1216 * include all the packets they should. 1217 */ 1218 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1219 (1ULL << EF10_STAT_port_tx_lt64) | \ 1220 (1ULL << EF10_STAT_port_tx_64) | \ 1221 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1222 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1223 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1224 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1225 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1226 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1227 1228 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1229 * switchable port we do expose these because the errors will otherwise 1230 * be silent. 1231 */ 1232 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1233 (1ULL << EF10_STAT_port_rx_length_error)) 1234 1235 /* These statistics are only provided if the firmware supports the 1236 * capability PM_AND_RXDP_COUNTERS. 1237 */ 1238 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1239 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1240 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1241 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1242 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1243 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1244 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1245 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1246 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1247 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1248 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1249 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1250 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1251 1252 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1253 { 1254 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1255 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1256 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1257 1258 if (!(efx->mcdi->fn_flags & 1259 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1260 return 0; 1261 1262 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) 1263 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1264 else 1265 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1266 1267 if (nic_data->datapath_caps & 1268 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1269 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1270 1271 return raw_mask; 1272 } 1273 1274 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1275 { 1276 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1277 u64 raw_mask[2]; 1278 1279 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1280 1281 /* Only show vadaptor stats when EVB capability is present */ 1282 if (nic_data->datapath_caps & 1283 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1284 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1285 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1; 1286 } else { 1287 raw_mask[1] = 0; 1288 } 1289 1290 #if BITS_PER_LONG == 64 1291 mask[0] = raw_mask[0]; 1292 mask[1] = raw_mask[1]; 1293 #else 1294 mask[0] = raw_mask[0] & 0xffffffff; 1295 mask[1] = raw_mask[0] >> 32; 1296 mask[2] = raw_mask[1] & 0xffffffff; 1297 mask[3] = raw_mask[1] >> 32; 1298 #endif 1299 } 1300 1301 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1302 { 1303 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1304 1305 efx_ef10_get_stat_mask(efx, mask); 1306 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1307 mask, names); 1308 } 1309 1310 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1311 struct rtnl_link_stats64 *core_stats) 1312 { 1313 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1314 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1315 u64 *stats = nic_data->stats; 1316 size_t stats_count = 0, index; 1317 1318 efx_ef10_get_stat_mask(efx, mask); 1319 1320 if (full_stats) { 1321 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1322 if (efx_ef10_stat_desc[index].name) { 1323 *full_stats++ = stats[index]; 1324 ++stats_count; 1325 } 1326 } 1327 } 1328 1329 if (!core_stats) 1330 return stats_count; 1331 1332 if (nic_data->datapath_caps & 1333 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1334 /* Use vadaptor stats. */ 1335 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1336 stats[EF10_STAT_rx_multicast] + 1337 stats[EF10_STAT_rx_broadcast]; 1338 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1339 stats[EF10_STAT_tx_multicast] + 1340 stats[EF10_STAT_tx_broadcast]; 1341 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1342 stats[EF10_STAT_rx_multicast_bytes] + 1343 stats[EF10_STAT_rx_broadcast_bytes]; 1344 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1345 stats[EF10_STAT_tx_multicast_bytes] + 1346 stats[EF10_STAT_tx_broadcast_bytes]; 1347 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1348 stats[GENERIC_STAT_rx_noskb_drops]; 1349 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1350 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1351 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1352 core_stats->rx_errors = core_stats->rx_crc_errors; 1353 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1354 } else { 1355 /* Use port stats. */ 1356 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1357 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1358 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1359 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1360 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1361 stats[GENERIC_STAT_rx_nodesc_trunc] + 1362 stats[GENERIC_STAT_rx_noskb_drops]; 1363 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1364 core_stats->rx_length_errors = 1365 stats[EF10_STAT_port_rx_gtjumbo] + 1366 stats[EF10_STAT_port_rx_length_error]; 1367 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1368 core_stats->rx_frame_errors = 1369 stats[EF10_STAT_port_rx_align_error]; 1370 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1371 core_stats->rx_errors = (core_stats->rx_length_errors + 1372 core_stats->rx_crc_errors + 1373 core_stats->rx_frame_errors); 1374 } 1375 1376 return stats_count; 1377 } 1378 1379 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx) 1380 { 1381 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1382 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1383 __le64 generation_start, generation_end; 1384 u64 *stats = nic_data->stats; 1385 __le64 *dma_stats; 1386 1387 efx_ef10_get_stat_mask(efx, mask); 1388 1389 dma_stats = efx->stats_buffer.addr; 1390 nic_data = efx->nic_data; 1391 1392 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1393 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 1394 return 0; 1395 rmb(); 1396 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1397 stats, efx->stats_buffer.addr, false); 1398 rmb(); 1399 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1400 if (generation_end != generation_start) 1401 return -EAGAIN; 1402 1403 /* Update derived statistics */ 1404 efx_nic_fix_nodesc_drop_stat(efx, 1405 &stats[EF10_STAT_port_rx_nodesc_drops]); 1406 stats[EF10_STAT_port_rx_good_bytes] = 1407 stats[EF10_STAT_port_rx_bytes] - 1408 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1409 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1410 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1411 efx_update_sw_stats(efx, stats); 1412 return 0; 1413 } 1414 1415 1416 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1417 struct rtnl_link_stats64 *core_stats) 1418 { 1419 int retry; 1420 1421 /* If we're unlucky enough to read statistics during the DMA, wait 1422 * up to 10ms for it to finish (typically takes <500us) 1423 */ 1424 for (retry = 0; retry < 100; ++retry) { 1425 if (efx_ef10_try_update_nic_stats_pf(efx) == 0) 1426 break; 1427 udelay(100); 1428 } 1429 1430 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1431 } 1432 1433 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1434 { 1435 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1436 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1437 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1438 __le64 generation_start, generation_end; 1439 u64 *stats = nic_data->stats; 1440 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64); 1441 struct efx_buffer stats_buf; 1442 __le64 *dma_stats; 1443 int rc; 1444 1445 spin_unlock_bh(&efx->stats_lock); 1446 1447 if (in_interrupt()) { 1448 /* If in atomic context, cannot update stats. Just update the 1449 * software stats and return so the caller can continue. 1450 */ 1451 spin_lock_bh(&efx->stats_lock); 1452 efx_update_sw_stats(efx, stats); 1453 return 0; 1454 } 1455 1456 efx_ef10_get_stat_mask(efx, mask); 1457 1458 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC); 1459 if (rc) { 1460 spin_lock_bh(&efx->stats_lock); 1461 return rc; 1462 } 1463 1464 dma_stats = stats_buf.addr; 1465 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID; 1466 1467 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1468 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1469 MAC_STATS_IN_DMA, 1); 1470 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1471 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1472 1473 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1474 NULL, 0, NULL); 1475 spin_lock_bh(&efx->stats_lock); 1476 if (rc) { 1477 /* Expect ENOENT if DMA queues have not been set up */ 1478 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1479 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1480 sizeof(inbuf), NULL, 0, rc); 1481 goto out; 1482 } 1483 1484 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 1485 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1486 WARN_ON_ONCE(1); 1487 goto out; 1488 } 1489 rmb(); 1490 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1491 stats, stats_buf.addr, false); 1492 rmb(); 1493 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1494 if (generation_end != generation_start) { 1495 rc = -EAGAIN; 1496 goto out; 1497 } 1498 1499 efx_update_sw_stats(efx, stats); 1500 out: 1501 efx_nic_free_buffer(efx, &stats_buf); 1502 return rc; 1503 } 1504 1505 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1506 struct rtnl_link_stats64 *core_stats) 1507 { 1508 if (efx_ef10_try_update_nic_stats_vf(efx)) 1509 return 0; 1510 1511 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1512 } 1513 1514 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1515 { 1516 struct efx_nic *efx = channel->efx; 1517 unsigned int mode, value; 1518 efx_dword_t timer_cmd; 1519 1520 if (channel->irq_moderation) { 1521 mode = 3; 1522 value = channel->irq_moderation - 1; 1523 } else { 1524 mode = 0; 1525 value = 0; 1526 } 1527 1528 if (EFX_EF10_WORKAROUND_35388(efx)) { 1529 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1530 EFE_DD_EVQ_IND_TIMER_FLAGS, 1531 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1532 ERF_DD_EVQ_IND_TIMER_VAL, value); 1533 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1534 channel->channel); 1535 } else { 1536 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1537 ERF_DZ_TC_TIMER_VAL, value); 1538 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1539 channel->channel); 1540 } 1541 } 1542 1543 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 1544 struct ethtool_wolinfo *wol) {} 1545 1546 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 1547 { 1548 return -EOPNOTSUPP; 1549 } 1550 1551 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1552 { 1553 wol->supported = 0; 1554 wol->wolopts = 0; 1555 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1556 } 1557 1558 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 1559 { 1560 if (type != 0) 1561 return -EINVAL; 1562 return 0; 1563 } 1564 1565 static void efx_ef10_mcdi_request(struct efx_nic *efx, 1566 const efx_dword_t *hdr, size_t hdr_len, 1567 const efx_dword_t *sdu, size_t sdu_len) 1568 { 1569 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1570 u8 *pdu = nic_data->mcdi_buf.addr; 1571 1572 memcpy(pdu, hdr, hdr_len); 1573 memcpy(pdu + hdr_len, sdu, sdu_len); 1574 wmb(); 1575 1576 /* The hardware provides 'low' and 'high' (doorbell) registers 1577 * for passing the 64-bit address of an MCDI request to 1578 * firmware. However the dwords are swapped by firmware. The 1579 * least significant bits of the doorbell are then 0 for all 1580 * MCDI requests due to alignment. 1581 */ 1582 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 1583 ER_DZ_MC_DB_LWRD); 1584 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 1585 ER_DZ_MC_DB_HWRD); 1586 } 1587 1588 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 1589 { 1590 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1591 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 1592 1593 rmb(); 1594 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 1595 } 1596 1597 static void 1598 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 1599 size_t offset, size_t outlen) 1600 { 1601 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1602 const u8 *pdu = nic_data->mcdi_buf.addr; 1603 1604 memcpy(outbuf, pdu + offset, outlen); 1605 } 1606 1607 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 1608 { 1609 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1610 1611 /* All our allocations have been reset */ 1612 efx_ef10_reset_mc_allocations(efx); 1613 1614 /* The datapath firmware might have been changed */ 1615 nic_data->must_check_datapath_caps = true; 1616 1617 /* MAC statistics have been cleared on the NIC; clear the local 1618 * statistic that we update with efx_update_diff_stat(). 1619 */ 1620 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 1621 } 1622 1623 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 1624 { 1625 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1626 int rc; 1627 1628 rc = efx_ef10_get_warm_boot_count(efx); 1629 if (rc < 0) { 1630 /* The firmware is presumably in the process of 1631 * rebooting. However, we are supposed to report each 1632 * reboot just once, so we must only do that once we 1633 * can read and store the updated warm boot count. 1634 */ 1635 return 0; 1636 } 1637 1638 if (rc == nic_data->warm_boot_count) 1639 return 0; 1640 1641 nic_data->warm_boot_count = rc; 1642 efx_ef10_mcdi_reboot_detected(efx); 1643 1644 return -EIO; 1645 } 1646 1647 /* Handle an MSI interrupt 1648 * 1649 * Handle an MSI hardware interrupt. This routine schedules event 1650 * queue processing. No interrupt acknowledgement cycle is necessary. 1651 * Also, we never need to check that the interrupt is for us, since 1652 * MSI interrupts cannot be shared. 1653 */ 1654 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 1655 { 1656 struct efx_msi_context *context = dev_id; 1657 struct efx_nic *efx = context->efx; 1658 1659 netif_vdbg(efx, intr, efx->net_dev, 1660 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 1661 1662 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) { 1663 /* Note test interrupts */ 1664 if (context->index == efx->irq_level) 1665 efx->last_irq_cpu = raw_smp_processor_id(); 1666 1667 /* Schedule processing of the channel */ 1668 efx_schedule_channel_irq(efx->channel[context->index]); 1669 } 1670 1671 return IRQ_HANDLED; 1672 } 1673 1674 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 1675 { 1676 struct efx_nic *efx = dev_id; 1677 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); 1678 struct efx_channel *channel; 1679 efx_dword_t reg; 1680 u32 queues; 1681 1682 /* Read the ISR which also ACKs the interrupts */ 1683 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 1684 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 1685 1686 if (queues == 0) 1687 return IRQ_NONE; 1688 1689 if (likely(soft_enabled)) { 1690 /* Note test interrupts */ 1691 if (queues & (1U << efx->irq_level)) 1692 efx->last_irq_cpu = raw_smp_processor_id(); 1693 1694 efx_for_each_channel(channel, efx) { 1695 if (queues & 1) 1696 efx_schedule_channel_irq(channel); 1697 queues >>= 1; 1698 } 1699 } 1700 1701 netif_vdbg(efx, intr, efx->net_dev, 1702 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 1703 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 1704 1705 return IRQ_HANDLED; 1706 } 1707 1708 static void efx_ef10_irq_test_generate(struct efx_nic *efx) 1709 { 1710 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 1711 1712 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 1713 1714 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 1715 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 1716 inbuf, sizeof(inbuf), NULL, 0, NULL); 1717 } 1718 1719 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 1720 { 1721 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 1722 (tx_queue->ptr_mask + 1) * 1723 sizeof(efx_qword_t), 1724 GFP_KERNEL); 1725 } 1726 1727 /* This writes to the TX_DESC_WPTR and also pushes data */ 1728 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 1729 const efx_qword_t *txd) 1730 { 1731 unsigned int write_ptr; 1732 efx_oword_t reg; 1733 1734 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1735 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 1736 reg.qword[0] = *txd; 1737 efx_writeo_page(tx_queue->efx, ®, 1738 ER_DZ_TX_DESC_UPD, tx_queue->queue); 1739 } 1740 1741 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 1742 { 1743 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 1744 EFX_BUF_SIZE)); 1745 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 1746 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; 1747 struct efx_channel *channel = tx_queue->channel; 1748 struct efx_nic *efx = tx_queue->efx; 1749 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1750 size_t inlen; 1751 dma_addr_t dma_addr; 1752 efx_qword_t *txd; 1753 int rc; 1754 int i; 1755 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0); 1756 1757 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); 1758 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); 1759 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); 1760 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); 1761 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS, 1762 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, 1763 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload); 1764 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); 1765 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id); 1766 1767 dma_addr = tx_queue->txd.buf.dma_addr; 1768 1769 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", 1770 tx_queue->queue, entries, (u64)dma_addr); 1771 1772 for (i = 0; i < entries; ++i) { 1773 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); 1774 dma_addr += EFX_BUF_SIZE; 1775 } 1776 1777 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); 1778 1779 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen, 1780 NULL, 0, NULL); 1781 if (rc) 1782 goto fail; 1783 1784 /* A previous user of this TX queue might have set us up the 1785 * bomb by writing a descriptor to the TX push collector but 1786 * not the doorbell. (Each collector belongs to a port, not a 1787 * queue or function, so cannot easily be reset.) We must 1788 * attempt to push a no-op descriptor in its place. 1789 */ 1790 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 1791 tx_queue->insert_count = 1; 1792 txd = efx_tx_desc(tx_queue, 0); 1793 EFX_POPULATE_QWORD_4(*txd, 1794 ESF_DZ_TX_DESC_IS_OPT, true, 1795 ESF_DZ_TX_OPTION_TYPE, 1796 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 1797 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 1798 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload); 1799 tx_queue->write_count = 1; 1800 1801 if (nic_data->datapath_caps & 1802 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) { 1803 tx_queue->tso_version = 1; 1804 } 1805 1806 wmb(); 1807 efx_ef10_push_tx_desc(tx_queue, txd); 1808 1809 return; 1810 1811 fail: 1812 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 1813 tx_queue->queue); 1814 } 1815 1816 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue) 1817 { 1818 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); 1819 MCDI_DECLARE_BUF_ERR(outbuf); 1820 struct efx_nic *efx = tx_queue->efx; 1821 size_t outlen; 1822 int rc; 1823 1824 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, 1825 tx_queue->queue); 1826 1827 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), 1828 outbuf, sizeof(outbuf), &outlen); 1829 1830 if (rc && rc != -EALREADY) 1831 goto fail; 1832 1833 return; 1834 1835 fail: 1836 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, 1837 outbuf, outlen, rc); 1838 } 1839 1840 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue) 1841 { 1842 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); 1843 } 1844 1845 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 1846 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 1847 { 1848 unsigned int write_ptr; 1849 efx_dword_t reg; 1850 1851 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1852 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 1853 efx_writed_page(tx_queue->efx, ®, 1854 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 1855 } 1856 1857 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 1858 { 1859 unsigned int old_write_count = tx_queue->write_count; 1860 struct efx_tx_buffer *buffer; 1861 unsigned int write_ptr; 1862 efx_qword_t *txd; 1863 1864 tx_queue->xmit_more_available = false; 1865 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 1866 return; 1867 1868 do { 1869 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1870 buffer = &tx_queue->buffer[write_ptr]; 1871 txd = efx_tx_desc(tx_queue, write_ptr); 1872 ++tx_queue->write_count; 1873 1874 /* Create TX descriptor ring entry */ 1875 if (buffer->flags & EFX_TX_BUF_OPTION) { 1876 *txd = buffer->option; 1877 } else { 1878 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 1879 EFX_POPULATE_QWORD_3( 1880 *txd, 1881 ESF_DZ_TX_KER_CONT, 1882 buffer->flags & EFX_TX_BUF_CONT, 1883 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 1884 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 1885 } 1886 } while (tx_queue->write_count != tx_queue->insert_count); 1887 1888 wmb(); /* Ensure descriptors are written before they are fetched */ 1889 1890 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 1891 txd = efx_tx_desc(tx_queue, 1892 old_write_count & tx_queue->ptr_mask); 1893 efx_ef10_push_tx_desc(tx_queue, txd); 1894 ++tx_queue->pushes; 1895 } else { 1896 efx_ef10_notify_tx_desc(tx_queue); 1897 } 1898 } 1899 1900 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context, 1901 bool exclusive, unsigned *context_size) 1902 { 1903 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN); 1904 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN); 1905 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1906 size_t outlen; 1907 int rc; 1908 u32 alloc_type = exclusive ? 1909 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE : 1910 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED; 1911 unsigned rss_spread = exclusive ? 1912 efx->rss_spread : 1913 min(rounddown_pow_of_two(efx->rss_spread), 1914 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE); 1915 1916 if (!exclusive && rss_spread == 1) { 1917 *context = EFX_EF10_RSS_CONTEXT_INVALID; 1918 if (context_size) 1919 *context_size = 1; 1920 return 0; 1921 } 1922 1923 if (nic_data->datapath_caps & 1924 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN) 1925 return -EOPNOTSUPP; 1926 1927 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, 1928 nic_data->vport_id); 1929 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type); 1930 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread); 1931 1932 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf), 1933 outbuf, sizeof(outbuf), &outlen); 1934 if (rc != 0) 1935 return rc; 1936 1937 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) 1938 return -EIO; 1939 1940 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); 1941 1942 if (context_size) 1943 *context_size = rss_spread; 1944 1945 return 0; 1946 } 1947 1948 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context) 1949 { 1950 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN); 1951 int rc; 1952 1953 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, 1954 context); 1955 1956 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf), 1957 NULL, 0, NULL); 1958 WARN_ON(rc != 0); 1959 } 1960 1961 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context, 1962 const u32 *rx_indir_table) 1963 { 1964 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN); 1965 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN); 1966 int i, rc; 1967 1968 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, 1969 context); 1970 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != 1971 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN); 1972 1973 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i) 1974 MCDI_PTR(tablebuf, 1975 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] = 1976 (u8) rx_indir_table[i]; 1977 1978 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf, 1979 sizeof(tablebuf), NULL, 0, NULL); 1980 if (rc != 0) 1981 return rc; 1982 1983 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, 1984 context); 1985 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) != 1986 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); 1987 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i) 1988 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = 1989 efx->rx_hash_key[i]; 1990 1991 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf, 1992 sizeof(keybuf), NULL, 0, NULL); 1993 } 1994 1995 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx) 1996 { 1997 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1998 1999 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 2000 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context); 2001 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 2002 } 2003 2004 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx, 2005 unsigned *context_size) 2006 { 2007 u32 new_rx_rss_context; 2008 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2009 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 2010 false, context_size); 2011 2012 if (rc != 0) 2013 return rc; 2014 2015 nic_data->rx_rss_context = new_rx_rss_context; 2016 nic_data->rx_rss_context_exclusive = false; 2017 efx_set_default_rx_indir_table(efx); 2018 return 0; 2019 } 2020 2021 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx, 2022 const u32 *rx_indir_table) 2023 { 2024 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2025 int rc; 2026 u32 new_rx_rss_context; 2027 2028 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID || 2029 !nic_data->rx_rss_context_exclusive) { 2030 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context, 2031 true, NULL); 2032 if (rc == -EOPNOTSUPP) 2033 return rc; 2034 else if (rc != 0) 2035 goto fail1; 2036 } else { 2037 new_rx_rss_context = nic_data->rx_rss_context; 2038 } 2039 2040 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context, 2041 rx_indir_table); 2042 if (rc != 0) 2043 goto fail2; 2044 2045 if (nic_data->rx_rss_context != new_rx_rss_context) 2046 efx_ef10_rx_free_indir_table(efx); 2047 nic_data->rx_rss_context = new_rx_rss_context; 2048 nic_data->rx_rss_context_exclusive = true; 2049 if (rx_indir_table != efx->rx_indir_table) 2050 memcpy(efx->rx_indir_table, rx_indir_table, 2051 sizeof(efx->rx_indir_table)); 2052 return 0; 2053 2054 fail2: 2055 if (new_rx_rss_context != nic_data->rx_rss_context) 2056 efx_ef10_free_rss_context(efx, new_rx_rss_context); 2057 fail1: 2058 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 2059 return rc; 2060 } 2061 2062 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user, 2063 const u32 *rx_indir_table) 2064 { 2065 int rc; 2066 2067 if (efx->rss_spread == 1) 2068 return 0; 2069 2070 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table); 2071 2072 if (rc == -ENOBUFS && !user) { 2073 unsigned context_size; 2074 bool mismatch = false; 2075 size_t i; 2076 2077 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch; 2078 i++) 2079 mismatch = rx_indir_table[i] != 2080 ethtool_rxfh_indir_default(i, efx->rss_spread); 2081 2082 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size); 2083 if (rc == 0) { 2084 if (context_size != efx->rss_spread) 2085 netif_warn(efx, probe, efx->net_dev, 2086 "Could not allocate an exclusive RSS" 2087 " context; allocated a shared one of" 2088 " different size." 2089 " Wanted %u, got %u.\n", 2090 efx->rss_spread, context_size); 2091 else if (mismatch) 2092 netif_warn(efx, probe, efx->net_dev, 2093 "Could not allocate an exclusive RSS" 2094 " context; allocated a shared one but" 2095 " could not apply custom" 2096 " indirection.\n"); 2097 else 2098 netif_info(efx, probe, efx->net_dev, 2099 "Could not allocate an exclusive RSS" 2100 " context; allocated a shared one.\n"); 2101 } 2102 } 2103 return rc; 2104 } 2105 2106 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user, 2107 const u32 *rx_indir_table 2108 __attribute__ ((unused))) 2109 { 2110 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2111 2112 if (user) 2113 return -EOPNOTSUPP; 2114 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 2115 return 0; 2116 return efx_ef10_rx_push_shared_rss_config(efx, NULL); 2117 } 2118 2119 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue) 2120 { 2121 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, 2122 (rx_queue->ptr_mask + 1) * 2123 sizeof(efx_qword_t), 2124 GFP_KERNEL); 2125 } 2126 2127 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue) 2128 { 2129 MCDI_DECLARE_BUF(inbuf, 2130 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 2131 EFX_BUF_SIZE)); 2132 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2133 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; 2134 struct efx_nic *efx = rx_queue->efx; 2135 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2136 size_t inlen; 2137 dma_addr_t dma_addr; 2138 int rc; 2139 int i; 2140 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0); 2141 2142 rx_queue->scatter_n = 0; 2143 rx_queue->scatter_len = 0; 2144 2145 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); 2146 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); 2147 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); 2148 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, 2149 efx_rx_queue_index(rx_queue)); 2150 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, 2151 INIT_RXQ_IN_FLAG_PREFIX, 1, 2152 INIT_RXQ_IN_FLAG_TIMESTAMP, 1); 2153 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); 2154 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id); 2155 2156 dma_addr = rx_queue->rxd.buf.dma_addr; 2157 2158 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", 2159 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); 2160 2161 for (i = 0; i < entries; ++i) { 2162 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); 2163 dma_addr += EFX_BUF_SIZE; 2164 } 2165 2166 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); 2167 2168 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, 2169 NULL, 0, NULL); 2170 if (rc) 2171 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", 2172 efx_rx_queue_index(rx_queue)); 2173 } 2174 2175 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue) 2176 { 2177 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); 2178 MCDI_DECLARE_BUF_ERR(outbuf); 2179 struct efx_nic *efx = rx_queue->efx; 2180 size_t outlen; 2181 int rc; 2182 2183 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, 2184 efx_rx_queue_index(rx_queue)); 2185 2186 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), 2187 outbuf, sizeof(outbuf), &outlen); 2188 2189 if (rc && rc != -EALREADY) 2190 goto fail; 2191 2192 return; 2193 2194 fail: 2195 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, 2196 outbuf, outlen, rc); 2197 } 2198 2199 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue) 2200 { 2201 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); 2202 } 2203 2204 /* This creates an entry in the RX descriptor queue */ 2205 static inline void 2206 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2207 { 2208 struct efx_rx_buffer *rx_buf; 2209 efx_qword_t *rxd; 2210 2211 rxd = efx_rx_desc(rx_queue, index); 2212 rx_buf = efx_rx_buffer(rx_queue, index); 2213 EFX_POPULATE_QWORD_2(*rxd, 2214 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2215 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2216 } 2217 2218 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2219 { 2220 struct efx_nic *efx = rx_queue->efx; 2221 unsigned int write_count; 2222 efx_dword_t reg; 2223 2224 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2225 write_count = rx_queue->added_count & ~7; 2226 if (rx_queue->notified_count == write_count) 2227 return; 2228 2229 do 2230 efx_ef10_build_rx_desc( 2231 rx_queue, 2232 rx_queue->notified_count & rx_queue->ptr_mask); 2233 while (++rx_queue->notified_count != write_count); 2234 2235 wmb(); 2236 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2237 write_count & rx_queue->ptr_mask); 2238 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2239 efx_rx_queue_index(rx_queue)); 2240 } 2241 2242 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2243 2244 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2245 { 2246 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2247 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2248 efx_qword_t event; 2249 2250 EFX_POPULATE_QWORD_2(event, 2251 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2252 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2253 2254 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2255 2256 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2257 * already swapped the data to little-endian order. 2258 */ 2259 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2260 sizeof(efx_qword_t)); 2261 2262 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2263 inbuf, sizeof(inbuf), 0, 2264 efx_ef10_rx_defer_refill_complete, 0); 2265 } 2266 2267 static void 2268 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2269 int rc, efx_dword_t *outbuf, 2270 size_t outlen_actual) 2271 { 2272 /* nothing to do */ 2273 } 2274 2275 static int efx_ef10_ev_probe(struct efx_channel *channel) 2276 { 2277 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 2278 (channel->eventq_mask + 1) * 2279 sizeof(efx_qword_t), 2280 GFP_KERNEL); 2281 } 2282 2283 static void efx_ef10_ev_fini(struct efx_channel *channel) 2284 { 2285 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); 2286 MCDI_DECLARE_BUF_ERR(outbuf); 2287 struct efx_nic *efx = channel->efx; 2288 size_t outlen; 2289 int rc; 2290 2291 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); 2292 2293 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), 2294 outbuf, sizeof(outbuf), &outlen); 2295 2296 if (rc && rc != -EALREADY) 2297 goto fail; 2298 2299 return; 2300 2301 fail: 2302 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, 2303 outbuf, outlen, rc); 2304 } 2305 2306 static int efx_ef10_ev_init(struct efx_channel *channel) 2307 { 2308 MCDI_DECLARE_BUF(inbuf, 2309 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / 2310 EFX_BUF_SIZE)); 2311 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN); 2312 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; 2313 struct efx_nic *efx = channel->efx; 2314 struct efx_ef10_nic_data *nic_data; 2315 bool supports_rx_merge; 2316 size_t inlen, outlen; 2317 unsigned int enabled, implemented; 2318 dma_addr_t dma_addr; 2319 int rc; 2320 int i; 2321 2322 nic_data = efx->nic_data; 2323 supports_rx_merge = 2324 !!(nic_data->datapath_caps & 2325 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2326 2327 /* Fill event queue with all ones (i.e. empty events) */ 2328 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); 2329 2330 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); 2331 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); 2332 /* INIT_EVQ expects index in vector table, not absolute */ 2333 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); 2334 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, 2335 INIT_EVQ_IN_FLAG_INTERRUPTING, 1, 2336 INIT_EVQ_IN_FLAG_RX_MERGE, 1, 2337 INIT_EVQ_IN_FLAG_TX_MERGE, 1, 2338 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge); 2339 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, 2340 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); 2341 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); 2342 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); 2343 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, 2344 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); 2345 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); 2346 2347 dma_addr = channel->eventq.buf.dma_addr; 2348 for (i = 0; i < entries; ++i) { 2349 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); 2350 dma_addr += EFX_BUF_SIZE; 2351 } 2352 2353 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); 2354 2355 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, 2356 outbuf, sizeof(outbuf), &outlen); 2357 /* IRQ return is ignored */ 2358 if (channel->channel || rc) 2359 return rc; 2360 2361 /* Successfully created event queue on channel 0 */ 2362 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2363 if (rc == -ENOSYS) { 2364 /* GET_WORKAROUNDS was implemented before the bug26807 2365 * workaround, thus the latter must be unavailable in this fw 2366 */ 2367 nic_data->workaround_26807 = false; 2368 rc = 0; 2369 } else if (rc) { 2370 goto fail; 2371 } else { 2372 nic_data->workaround_26807 = 2373 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2374 2375 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 && 2376 !nic_data->workaround_26807) { 2377 unsigned int flags; 2378 2379 rc = efx_mcdi_set_workaround(efx, 2380 MC_CMD_WORKAROUND_BUG26807, 2381 true, &flags); 2382 2383 if (!rc) { 2384 if (flags & 2385 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2386 netif_info(efx, drv, efx->net_dev, 2387 "other functions on NIC have been reset\n"); 2388 2389 /* With MCFW v4.6.x and earlier, the 2390 * boot count will have incremented, 2391 * so re-read the warm_boot_count 2392 * value now to ensure this function 2393 * doesn't think it has changed next 2394 * time it checks. 2395 */ 2396 rc = efx_ef10_get_warm_boot_count(efx); 2397 if (rc >= 0) { 2398 nic_data->warm_boot_count = rc; 2399 rc = 0; 2400 } 2401 } 2402 nic_data->workaround_26807 = true; 2403 } else if (rc == -EPERM) { 2404 rc = 0; 2405 } 2406 } 2407 } 2408 2409 if (!rc) 2410 return 0; 2411 2412 fail: 2413 efx_ef10_ev_fini(channel); 2414 return rc; 2415 } 2416 2417 static void efx_ef10_ev_remove(struct efx_channel *channel) 2418 { 2419 efx_nic_free_buffer(channel->efx, &channel->eventq.buf); 2420 } 2421 2422 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2423 unsigned int rx_queue_label) 2424 { 2425 struct efx_nic *efx = rx_queue->efx; 2426 2427 netif_info(efx, hw, efx->net_dev, 2428 "rx event arrived on queue %d labeled as queue %u\n", 2429 efx_rx_queue_index(rx_queue), rx_queue_label); 2430 2431 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2432 } 2433 2434 static void 2435 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2436 unsigned int actual, unsigned int expected) 2437 { 2438 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2439 struct efx_nic *efx = rx_queue->efx; 2440 2441 netif_info(efx, hw, efx->net_dev, 2442 "dropped %d events (index=%d expected=%d)\n", 2443 dropped, actual, expected); 2444 2445 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2446 } 2447 2448 /* partially received RX was aborted. clean up. */ 2449 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2450 { 2451 unsigned int rx_desc_ptr; 2452 2453 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2454 "scattered RX aborted (dropping %u buffers)\n", 2455 rx_queue->scatter_n); 2456 2457 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2458 2459 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2460 0, EFX_RX_PKT_DISCARD); 2461 2462 rx_queue->removed_count += rx_queue->scatter_n; 2463 rx_queue->scatter_n = 0; 2464 rx_queue->scatter_len = 0; 2465 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2466 } 2467 2468 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2469 const efx_qword_t *event) 2470 { 2471 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class; 2472 unsigned int n_descs, n_packets, i; 2473 struct efx_nic *efx = channel->efx; 2474 struct efx_rx_queue *rx_queue; 2475 bool rx_cont; 2476 u16 flags = 0; 2477 2478 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 2479 return 0; 2480 2481 /* Basic packet information */ 2482 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2483 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2484 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2485 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); 2486 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2487 2488 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2489 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2490 EFX_QWORD_FMT "\n", 2491 EFX_QWORD_VAL(*event)); 2492 2493 rx_queue = efx_channel_get_rx_queue(channel); 2494 2495 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2496 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2497 2498 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2499 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2500 2501 if (n_descs != rx_queue->scatter_n + 1) { 2502 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2503 2504 /* detect rx abort */ 2505 if (unlikely(n_descs == rx_queue->scatter_n)) { 2506 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2507 netdev_WARN(efx->net_dev, 2508 "invalid RX abort: scatter_n=%u event=" 2509 EFX_QWORD_FMT "\n", 2510 rx_queue->scatter_n, 2511 EFX_QWORD_VAL(*event)); 2512 efx_ef10_handle_rx_abort(rx_queue); 2513 return 0; 2514 } 2515 2516 /* Check that RX completion merging is valid, i.e. 2517 * the current firmware supports it and this is a 2518 * non-scattered packet. 2519 */ 2520 if (!(nic_data->datapath_caps & 2521 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2522 rx_queue->scatter_n != 0 || rx_cont) { 2523 efx_ef10_handle_rx_bad_lbits( 2524 rx_queue, next_ptr_lbits, 2525 (rx_queue->removed_count + 2526 rx_queue->scatter_n + 1) & 2527 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2528 return 0; 2529 } 2530 2531 /* Merged completion for multiple non-scattered packets */ 2532 rx_queue->scatter_n = 1; 2533 rx_queue->scatter_len = 0; 2534 n_packets = n_descs; 2535 ++channel->n_rx_merge_events; 2536 channel->n_rx_merge_packets += n_packets; 2537 flags |= EFX_RX_PKT_PREFIX_LEN; 2538 } else { 2539 ++rx_queue->scatter_n; 2540 rx_queue->scatter_len += rx_bytes; 2541 if (rx_cont) 2542 return 0; 2543 n_packets = 1; 2544 } 2545 2546 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR))) 2547 flags |= EFX_RX_PKT_DISCARD; 2548 2549 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) { 2550 channel->n_rx_ip_hdr_chksum_err += n_packets; 2551 } else if (unlikely(EFX_QWORD_FIELD(*event, 2552 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) { 2553 channel->n_rx_tcp_udp_chksum_err += n_packets; 2554 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP || 2555 rx_l4_class == ESE_DZ_L4_CLASS_UDP) { 2556 flags |= EFX_RX_PKT_CSUMMED; 2557 } 2558 2559 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) 2560 flags |= EFX_RX_PKT_TCP; 2561 2562 channel->irq_mod_score += 2 * n_packets; 2563 2564 /* Handle received packet(s) */ 2565 for (i = 0; i < n_packets; i++) { 2566 efx_rx_packet(rx_queue, 2567 rx_queue->removed_count & rx_queue->ptr_mask, 2568 rx_queue->scatter_n, rx_queue->scatter_len, 2569 flags); 2570 rx_queue->removed_count += rx_queue->scatter_n; 2571 } 2572 2573 rx_queue->scatter_n = 0; 2574 rx_queue->scatter_len = 0; 2575 2576 return n_packets; 2577 } 2578 2579 static int 2580 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2581 { 2582 struct efx_nic *efx = channel->efx; 2583 struct efx_tx_queue *tx_queue; 2584 unsigned int tx_ev_desc_ptr; 2585 unsigned int tx_ev_q_label; 2586 int tx_descs = 0; 2587 2588 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 2589 return 0; 2590 2591 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2592 return 0; 2593 2594 /* Transmit completion */ 2595 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2596 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2597 tx_queue = efx_channel_get_tx_queue(channel, 2598 tx_ev_q_label % EFX_TXQ_TYPES); 2599 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) & 2600 tx_queue->ptr_mask); 2601 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2602 2603 return tx_descs; 2604 } 2605 2606 static void 2607 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 2608 { 2609 struct efx_nic *efx = channel->efx; 2610 int subcode; 2611 2612 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 2613 2614 switch (subcode) { 2615 case ESE_DZ_DRV_TIMER_EV: 2616 case ESE_DZ_DRV_WAKE_UP_EV: 2617 break; 2618 case ESE_DZ_DRV_START_UP_EV: 2619 /* event queue init complete. ok. */ 2620 break; 2621 default: 2622 netif_err(efx, hw, efx->net_dev, 2623 "channel %d unknown driver event type %d" 2624 " (data " EFX_QWORD_FMT ")\n", 2625 channel->channel, subcode, 2626 EFX_QWORD_VAL(*event)); 2627 2628 } 2629 } 2630 2631 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 2632 efx_qword_t *event) 2633 { 2634 struct efx_nic *efx = channel->efx; 2635 u32 subcode; 2636 2637 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 2638 2639 switch (subcode) { 2640 case EFX_EF10_TEST: 2641 channel->event_test_cpu = raw_smp_processor_id(); 2642 break; 2643 case EFX_EF10_REFILL: 2644 /* The queue must be empty, so we won't receive any rx 2645 * events, so efx_process_channel() won't refill the 2646 * queue. Refill it here 2647 */ 2648 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 2649 break; 2650 default: 2651 netif_err(efx, hw, efx->net_dev, 2652 "channel %d unknown driver event type %u" 2653 " (data " EFX_QWORD_FMT ")\n", 2654 channel->channel, (unsigned) subcode, 2655 EFX_QWORD_VAL(*event)); 2656 } 2657 } 2658 2659 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 2660 { 2661 struct efx_nic *efx = channel->efx; 2662 efx_qword_t event, *p_event; 2663 unsigned int read_ptr; 2664 int ev_code; 2665 int tx_descs = 0; 2666 int spent = 0; 2667 2668 if (quota <= 0) 2669 return spent; 2670 2671 read_ptr = channel->eventq_read_ptr; 2672 2673 for (;;) { 2674 p_event = efx_event(channel, read_ptr); 2675 event = *p_event; 2676 2677 if (!efx_event_present(&event)) 2678 break; 2679 2680 EFX_SET_QWORD(*p_event); 2681 2682 ++read_ptr; 2683 2684 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 2685 2686 netif_vdbg(efx, drv, efx->net_dev, 2687 "processing event on %d " EFX_QWORD_FMT "\n", 2688 channel->channel, EFX_QWORD_VAL(event)); 2689 2690 switch (ev_code) { 2691 case ESE_DZ_EV_CODE_MCDI_EV: 2692 efx_mcdi_process_event(channel, &event); 2693 break; 2694 case ESE_DZ_EV_CODE_RX_EV: 2695 spent += efx_ef10_handle_rx_event(channel, &event); 2696 if (spent >= quota) { 2697 /* XXX can we split a merged event to 2698 * avoid going over-quota? 2699 */ 2700 spent = quota; 2701 goto out; 2702 } 2703 break; 2704 case ESE_DZ_EV_CODE_TX_EV: 2705 tx_descs += efx_ef10_handle_tx_event(channel, &event); 2706 if (tx_descs > efx->txq_entries) { 2707 spent = quota; 2708 goto out; 2709 } else if (++spent == quota) { 2710 goto out; 2711 } 2712 break; 2713 case ESE_DZ_EV_CODE_DRIVER_EV: 2714 efx_ef10_handle_driver_event(channel, &event); 2715 if (++spent == quota) 2716 goto out; 2717 break; 2718 case EFX_EF10_DRVGEN_EV: 2719 efx_ef10_handle_driver_generated_event(channel, &event); 2720 break; 2721 default: 2722 netif_err(efx, hw, efx->net_dev, 2723 "channel %d unknown event type %d" 2724 " (data " EFX_QWORD_FMT ")\n", 2725 channel->channel, ev_code, 2726 EFX_QWORD_VAL(event)); 2727 } 2728 } 2729 2730 out: 2731 channel->eventq_read_ptr = read_ptr; 2732 return spent; 2733 } 2734 2735 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 2736 { 2737 struct efx_nic *efx = channel->efx; 2738 efx_dword_t rptr; 2739 2740 if (EFX_EF10_WORKAROUND_35388(efx)) { 2741 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 2742 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 2743 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 2744 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 2745 2746 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2747 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 2748 ERF_DD_EVQ_IND_RPTR, 2749 (channel->eventq_read_ptr & 2750 channel->eventq_mask) >> 2751 ERF_DD_EVQ_IND_RPTR_WIDTH); 2752 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2753 channel->channel); 2754 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2755 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 2756 ERF_DD_EVQ_IND_RPTR, 2757 channel->eventq_read_ptr & 2758 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 2759 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2760 channel->channel); 2761 } else { 2762 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 2763 channel->eventq_read_ptr & 2764 channel->eventq_mask); 2765 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 2766 } 2767 } 2768 2769 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 2770 { 2771 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2772 struct efx_nic *efx = channel->efx; 2773 efx_qword_t event; 2774 int rc; 2775 2776 EFX_POPULATE_QWORD_2(event, 2777 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2778 ESF_DZ_EV_DATA, EFX_EF10_TEST); 2779 2780 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2781 2782 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2783 * already swapped the data to little-endian order. 2784 */ 2785 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2786 sizeof(efx_qword_t)); 2787 2788 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 2789 NULL, 0, NULL); 2790 if (rc != 0) 2791 goto fail; 2792 2793 return; 2794 2795 fail: 2796 WARN_ON(true); 2797 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 2798 } 2799 2800 void efx_ef10_handle_drain_event(struct efx_nic *efx) 2801 { 2802 if (atomic_dec_and_test(&efx->active_queues)) 2803 wake_up(&efx->flush_wq); 2804 2805 WARN_ON(atomic_read(&efx->active_queues) < 0); 2806 } 2807 2808 static int efx_ef10_fini_dmaq(struct efx_nic *efx) 2809 { 2810 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2811 struct efx_channel *channel; 2812 struct efx_tx_queue *tx_queue; 2813 struct efx_rx_queue *rx_queue; 2814 int pending; 2815 2816 /* If the MC has just rebooted, the TX/RX queues will have already been 2817 * torn down, but efx->active_queues needs to be set to zero. 2818 */ 2819 if (nic_data->must_realloc_vis) { 2820 atomic_set(&efx->active_queues, 0); 2821 return 0; 2822 } 2823 2824 /* Do not attempt to write to the NIC during EEH recovery */ 2825 if (efx->state != STATE_RECOVERY) { 2826 efx_for_each_channel(channel, efx) { 2827 efx_for_each_channel_rx_queue(rx_queue, channel) 2828 efx_ef10_rx_fini(rx_queue); 2829 efx_for_each_channel_tx_queue(tx_queue, channel) 2830 efx_ef10_tx_fini(tx_queue); 2831 } 2832 2833 wait_event_timeout(efx->flush_wq, 2834 atomic_read(&efx->active_queues) == 0, 2835 msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); 2836 pending = atomic_read(&efx->active_queues); 2837 if (pending) { 2838 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", 2839 pending); 2840 return -ETIMEDOUT; 2841 } 2842 } 2843 2844 return 0; 2845 } 2846 2847 static void efx_ef10_prepare_flr(struct efx_nic *efx) 2848 { 2849 atomic_set(&efx->active_queues, 0); 2850 } 2851 2852 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left, 2853 const struct efx_filter_spec *right) 2854 { 2855 if ((left->match_flags ^ right->match_flags) | 2856 ((left->flags ^ right->flags) & 2857 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX))) 2858 return false; 2859 2860 return memcmp(&left->outer_vid, &right->outer_vid, 2861 sizeof(struct efx_filter_spec) - 2862 offsetof(struct efx_filter_spec, outer_vid)) == 0; 2863 } 2864 2865 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec) 2866 { 2867 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3); 2868 return jhash2((const u32 *)&spec->outer_vid, 2869 (sizeof(struct efx_filter_spec) - 2870 offsetof(struct efx_filter_spec, outer_vid)) / 4, 2871 0); 2872 /* XXX should we randomise the initval? */ 2873 } 2874 2875 /* Decide whether a filter should be exclusive or else should allow 2876 * delivery to additional recipients. Currently we decide that 2877 * filters for specific local unicast MAC and IP addresses are 2878 * exclusive. 2879 */ 2880 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec) 2881 { 2882 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC && 2883 !is_multicast_ether_addr(spec->loc_mac)) 2884 return true; 2885 2886 if ((spec->match_flags & 2887 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == 2888 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { 2889 if (spec->ether_type == htons(ETH_P_IP) && 2890 !ipv4_is_multicast(spec->loc_host[0])) 2891 return true; 2892 if (spec->ether_type == htons(ETH_P_IPV6) && 2893 ((const u8 *)spec->loc_host)[0] != 0xff) 2894 return true; 2895 } 2896 2897 return false; 2898 } 2899 2900 static struct efx_filter_spec * 2901 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table, 2902 unsigned int filter_idx) 2903 { 2904 return (struct efx_filter_spec *)(table->entry[filter_idx].spec & 2905 ~EFX_EF10_FILTER_FLAGS); 2906 } 2907 2908 static unsigned int 2909 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table, 2910 unsigned int filter_idx) 2911 { 2912 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS; 2913 } 2914 2915 static void 2916 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table, 2917 unsigned int filter_idx, 2918 const struct efx_filter_spec *spec, 2919 unsigned int flags) 2920 { 2921 table->entry[filter_idx].spec = (unsigned long)spec | flags; 2922 } 2923 2924 static void efx_ef10_filter_push_prep(struct efx_nic *efx, 2925 const struct efx_filter_spec *spec, 2926 efx_dword_t *inbuf, u64 handle, 2927 bool replacing) 2928 { 2929 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2930 u32 flags = spec->flags; 2931 2932 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN); 2933 2934 /* Remove RSS flag if we don't have an RSS context. */ 2935 if (flags & EFX_FILTER_FLAG_RX_RSS && 2936 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT && 2937 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) 2938 flags &= ~EFX_FILTER_FLAG_RX_RSS; 2939 2940 if (replacing) { 2941 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2942 MC_CMD_FILTER_OP_IN_OP_REPLACE); 2943 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle); 2944 } else { 2945 u32 match_fields = 0; 2946 2947 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2948 efx_ef10_filter_is_exclusive(spec) ? 2949 MC_CMD_FILTER_OP_IN_OP_INSERT : 2950 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE); 2951 2952 /* Convert match flags and values. Unlike almost 2953 * everything else in MCDI, these fields are in 2954 * network byte order. 2955 */ 2956 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) 2957 match_fields |= 2958 is_multicast_ether_addr(spec->loc_mac) ? 2959 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN : 2960 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; 2961 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \ 2962 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \ 2963 match_fields |= \ 2964 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 2965 mcdi_field ## _LBN; \ 2966 BUILD_BUG_ON( \ 2967 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \ 2968 sizeof(spec->gen_field)); \ 2969 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \ 2970 &spec->gen_field, sizeof(spec->gen_field)); \ 2971 } 2972 COPY_FIELD(REM_HOST, rem_host, SRC_IP); 2973 COPY_FIELD(LOC_HOST, loc_host, DST_IP); 2974 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC); 2975 COPY_FIELD(REM_PORT, rem_port, SRC_PORT); 2976 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC); 2977 COPY_FIELD(LOC_PORT, loc_port, DST_PORT); 2978 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE); 2979 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN); 2980 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN); 2981 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO); 2982 #undef COPY_FIELD 2983 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS, 2984 match_fields); 2985 } 2986 2987 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id); 2988 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST, 2989 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2990 MC_CMD_FILTER_OP_IN_RX_DEST_DROP : 2991 MC_CMD_FILTER_OP_IN_RX_DEST_HOST); 2992 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0); 2993 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST, 2994 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); 2995 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, 2996 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2997 0 : spec->dmaq_id); 2998 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE, 2999 (flags & EFX_FILTER_FLAG_RX_RSS) ? 3000 MC_CMD_FILTER_OP_IN_RX_MODE_RSS : 3001 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); 3002 if (flags & EFX_FILTER_FLAG_RX_RSS) 3003 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, 3004 spec->rss_context != 3005 EFX_FILTER_RSS_CONTEXT_DEFAULT ? 3006 spec->rss_context : nic_data->rx_rss_context); 3007 } 3008 3009 static int efx_ef10_filter_push(struct efx_nic *efx, 3010 const struct efx_filter_spec *spec, 3011 u64 *handle, bool replacing) 3012 { 3013 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3014 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN); 3015 int rc; 3016 3017 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing); 3018 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3019 outbuf, sizeof(outbuf), NULL); 3020 if (rc == 0) 3021 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 3022 if (rc == -ENOSPC) 3023 rc = -EBUSY; /* to match efx_farch_filter_insert() */ 3024 return rc; 3025 } 3026 3027 static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table, 3028 enum efx_filter_match_flags match_flags) 3029 { 3030 unsigned int match_pri; 3031 3032 for (match_pri = 0; 3033 match_pri < table->rx_match_count; 3034 match_pri++) 3035 if (table->rx_match_flags[match_pri] == match_flags) 3036 return match_pri; 3037 3038 return -EPROTONOSUPPORT; 3039 } 3040 3041 static s32 efx_ef10_filter_insert(struct efx_nic *efx, 3042 struct efx_filter_spec *spec, 3043 bool replace_equal) 3044 { 3045 struct efx_ef10_filter_table *table = efx->filter_state; 3046 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 3047 struct efx_filter_spec *saved_spec; 3048 unsigned int match_pri, hash; 3049 unsigned int priv_flags; 3050 bool replacing = false; 3051 int ins_index = -1; 3052 DEFINE_WAIT(wait); 3053 bool is_mc_recip; 3054 s32 rc; 3055 3056 /* For now, only support RX filters */ 3057 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) != 3058 EFX_FILTER_FLAG_RX) 3059 return -EINVAL; 3060 3061 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags); 3062 if (rc < 0) 3063 return rc; 3064 match_pri = rc; 3065 3066 hash = efx_ef10_filter_hash(spec); 3067 is_mc_recip = efx_filter_is_mc_recipient(spec); 3068 if (is_mc_recip) 3069 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 3070 3071 /* Find any existing filters with the same match tuple or 3072 * else a free slot to insert at. If any of them are busy, 3073 * we have to wait and retry. 3074 */ 3075 for (;;) { 3076 unsigned int depth = 1; 3077 unsigned int i; 3078 3079 spin_lock_bh(&efx->filter_lock); 3080 3081 for (;;) { 3082 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3083 saved_spec = efx_ef10_filter_entry_spec(table, i); 3084 3085 if (!saved_spec) { 3086 if (ins_index < 0) 3087 ins_index = i; 3088 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 3089 if (table->entry[i].spec & 3090 EFX_EF10_FILTER_FLAG_BUSY) 3091 break; 3092 if (spec->priority < saved_spec->priority && 3093 spec->priority != EFX_FILTER_PRI_AUTO) { 3094 rc = -EPERM; 3095 goto out_unlock; 3096 } 3097 if (!is_mc_recip) { 3098 /* This is the only one */ 3099 if (spec->priority == 3100 saved_spec->priority && 3101 !replace_equal) { 3102 rc = -EEXIST; 3103 goto out_unlock; 3104 } 3105 ins_index = i; 3106 goto found; 3107 } else if (spec->priority > 3108 saved_spec->priority || 3109 (spec->priority == 3110 saved_spec->priority && 3111 replace_equal)) { 3112 if (ins_index < 0) 3113 ins_index = i; 3114 else 3115 __set_bit(depth, mc_rem_map); 3116 } 3117 } 3118 3119 /* Once we reach the maximum search depth, use 3120 * the first suitable slot or return -EBUSY if 3121 * there was none 3122 */ 3123 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 3124 if (ins_index < 0) { 3125 rc = -EBUSY; 3126 goto out_unlock; 3127 } 3128 goto found; 3129 } 3130 3131 ++depth; 3132 } 3133 3134 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 3135 spin_unlock_bh(&efx->filter_lock); 3136 schedule(); 3137 } 3138 3139 found: 3140 /* Create a software table entry if necessary, and mark it 3141 * busy. We might yet fail to insert, but any attempt to 3142 * insert a conflicting filter while we're waiting for the 3143 * firmware must find the busy entry. 3144 */ 3145 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 3146 if (saved_spec) { 3147 if (spec->priority == EFX_FILTER_PRI_AUTO && 3148 saved_spec->priority >= EFX_FILTER_PRI_AUTO) { 3149 /* Just make sure it won't be removed */ 3150 if (saved_spec->priority > EFX_FILTER_PRI_AUTO) 3151 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; 3152 table->entry[ins_index].spec &= 3153 ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3154 rc = ins_index; 3155 goto out_unlock; 3156 } 3157 replacing = true; 3158 priv_flags = efx_ef10_filter_entry_flags(table, ins_index); 3159 } else { 3160 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 3161 if (!saved_spec) { 3162 rc = -ENOMEM; 3163 goto out_unlock; 3164 } 3165 *saved_spec = *spec; 3166 priv_flags = 0; 3167 } 3168 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 3169 priv_flags | EFX_EF10_FILTER_FLAG_BUSY); 3170 3171 /* Mark lower-priority multicast recipients busy prior to removal */ 3172 if (is_mc_recip) { 3173 unsigned int depth, i; 3174 3175 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3176 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3177 if (test_bit(depth, mc_rem_map)) 3178 table->entry[i].spec |= 3179 EFX_EF10_FILTER_FLAG_BUSY; 3180 } 3181 } 3182 3183 spin_unlock_bh(&efx->filter_lock); 3184 3185 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle, 3186 replacing); 3187 3188 /* Finalise the software table entry */ 3189 spin_lock_bh(&efx->filter_lock); 3190 if (rc == 0) { 3191 if (replacing) { 3192 /* Update the fields that may differ */ 3193 if (saved_spec->priority == EFX_FILTER_PRI_AUTO) 3194 saved_spec->flags |= 3195 EFX_FILTER_FLAG_RX_OVER_AUTO; 3196 saved_spec->priority = spec->priority; 3197 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO; 3198 saved_spec->flags |= spec->flags; 3199 saved_spec->rss_context = spec->rss_context; 3200 saved_spec->dmaq_id = spec->dmaq_id; 3201 } 3202 } else if (!replacing) { 3203 kfree(saved_spec); 3204 saved_spec = NULL; 3205 } 3206 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags); 3207 3208 /* Remove and finalise entries for lower-priority multicast 3209 * recipients 3210 */ 3211 if (is_mc_recip) { 3212 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3213 unsigned int depth, i; 3214 3215 memset(inbuf, 0, sizeof(inbuf)); 3216 3217 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 3218 if (!test_bit(depth, mc_rem_map)) 3219 continue; 3220 3221 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3222 saved_spec = efx_ef10_filter_entry_spec(table, i); 3223 priv_flags = efx_ef10_filter_entry_flags(table, i); 3224 3225 if (rc == 0) { 3226 spin_unlock_bh(&efx->filter_lock); 3227 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3228 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3229 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3230 table->entry[i].handle); 3231 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3232 inbuf, sizeof(inbuf), 3233 NULL, 0, NULL); 3234 spin_lock_bh(&efx->filter_lock); 3235 } 3236 3237 if (rc == 0) { 3238 kfree(saved_spec); 3239 saved_spec = NULL; 3240 priv_flags = 0; 3241 } else { 3242 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY; 3243 } 3244 efx_ef10_filter_set_entry(table, i, saved_spec, 3245 priv_flags); 3246 } 3247 } 3248 3249 /* If successful, return the inserted filter ID */ 3250 if (rc == 0) 3251 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index; 3252 3253 wake_up_all(&table->waitq); 3254 out_unlock: 3255 spin_unlock_bh(&efx->filter_lock); 3256 finish_wait(&table->waitq, &wait); 3257 return rc; 3258 } 3259 3260 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx) 3261 { 3262 /* no need to do anything here on EF10 */ 3263 } 3264 3265 /* Remove a filter. 3266 * If !by_index, remove by ID 3267 * If by_index, remove by index 3268 * Filter ID may come from userland and must be range-checked. 3269 */ 3270 static int efx_ef10_filter_remove_internal(struct efx_nic *efx, 3271 unsigned int priority_mask, 3272 u32 filter_id, bool by_index) 3273 { 3274 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 3275 struct efx_ef10_filter_table *table = efx->filter_state; 3276 MCDI_DECLARE_BUF(inbuf, 3277 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 3278 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 3279 struct efx_filter_spec *spec; 3280 DEFINE_WAIT(wait); 3281 int rc; 3282 3283 /* Find the software table entry and mark it busy. Don't 3284 * remove it yet; any attempt to update while we're waiting 3285 * for the firmware must find the busy entry. 3286 */ 3287 for (;;) { 3288 spin_lock_bh(&efx->filter_lock); 3289 if (!(table->entry[filter_idx].spec & 3290 EFX_EF10_FILTER_FLAG_BUSY)) 3291 break; 3292 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 3293 spin_unlock_bh(&efx->filter_lock); 3294 schedule(); 3295 } 3296 3297 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3298 if (!spec || 3299 (!by_index && 3300 efx_ef10_filter_rx_match_pri(table, spec->match_flags) != 3301 filter_id / HUNT_FILTER_TBL_ROWS)) { 3302 rc = -ENOENT; 3303 goto out_unlock; 3304 } 3305 3306 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO && 3307 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) { 3308 /* Just remove flags */ 3309 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO; 3310 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 3311 rc = 0; 3312 goto out_unlock; 3313 } 3314 3315 if (!(priority_mask & (1U << spec->priority))) { 3316 rc = -ENOENT; 3317 goto out_unlock; 3318 } 3319 3320 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3321 spin_unlock_bh(&efx->filter_lock); 3322 3323 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { 3324 /* Reset to an automatic filter */ 3325 3326 struct efx_filter_spec new_spec = *spec; 3327 3328 new_spec.priority = EFX_FILTER_PRI_AUTO; 3329 new_spec.flags = (EFX_FILTER_FLAG_RX | 3330 (efx_rss_enabled(efx) ? 3331 EFX_FILTER_FLAG_RX_RSS : 0)); 3332 new_spec.dmaq_id = 0; 3333 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT; 3334 rc = efx_ef10_filter_push(efx, &new_spec, 3335 &table->entry[filter_idx].handle, 3336 true); 3337 3338 spin_lock_bh(&efx->filter_lock); 3339 if (rc == 0) 3340 *spec = new_spec; 3341 } else { 3342 /* Really remove the filter */ 3343 3344 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3345 efx_ef10_filter_is_exclusive(spec) ? 3346 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3347 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3348 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3349 table->entry[filter_idx].handle); 3350 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 3351 inbuf, sizeof(inbuf), NULL, 0, NULL); 3352 3353 spin_lock_bh(&efx->filter_lock); 3354 if (rc == 0) { 3355 kfree(spec); 3356 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3357 } 3358 } 3359 3360 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 3361 wake_up_all(&table->waitq); 3362 out_unlock: 3363 spin_unlock_bh(&efx->filter_lock); 3364 finish_wait(&table->waitq, &wait); 3365 return rc; 3366 } 3367 3368 static int efx_ef10_filter_remove_safe(struct efx_nic *efx, 3369 enum efx_filter_priority priority, 3370 u32 filter_id) 3371 { 3372 return efx_ef10_filter_remove_internal(efx, 1U << priority, 3373 filter_id, false); 3374 } 3375 3376 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id) 3377 { 3378 return filter_id % HUNT_FILTER_TBL_ROWS; 3379 } 3380 3381 static int efx_ef10_filter_remove_unsafe(struct efx_nic *efx, 3382 enum efx_filter_priority priority, 3383 u32 filter_id) 3384 { 3385 return efx_ef10_filter_remove_internal(efx, 1U << priority, 3386 filter_id, true); 3387 } 3388 3389 static int efx_ef10_filter_get_safe(struct efx_nic *efx, 3390 enum efx_filter_priority priority, 3391 u32 filter_id, struct efx_filter_spec *spec) 3392 { 3393 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 3394 struct efx_ef10_filter_table *table = efx->filter_state; 3395 const struct efx_filter_spec *saved_spec; 3396 int rc; 3397 3398 spin_lock_bh(&efx->filter_lock); 3399 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx); 3400 if (saved_spec && saved_spec->priority == priority && 3401 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) == 3402 filter_id / HUNT_FILTER_TBL_ROWS) { 3403 *spec = *saved_spec; 3404 rc = 0; 3405 } else { 3406 rc = -ENOENT; 3407 } 3408 spin_unlock_bh(&efx->filter_lock); 3409 return rc; 3410 } 3411 3412 static int efx_ef10_filter_clear_rx(struct efx_nic *efx, 3413 enum efx_filter_priority priority) 3414 { 3415 unsigned int priority_mask; 3416 unsigned int i; 3417 int rc; 3418 3419 priority_mask = (((1U << (priority + 1)) - 1) & 3420 ~(1U << EFX_FILTER_PRI_AUTO)); 3421 3422 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 3423 rc = efx_ef10_filter_remove_internal(efx, priority_mask, 3424 i, true); 3425 if (rc && rc != -ENOENT) 3426 return rc; 3427 } 3428 3429 return 0; 3430 } 3431 3432 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx, 3433 enum efx_filter_priority priority) 3434 { 3435 struct efx_ef10_filter_table *table = efx->filter_state; 3436 unsigned int filter_idx; 3437 s32 count = 0; 3438 3439 spin_lock_bh(&efx->filter_lock); 3440 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3441 if (table->entry[filter_idx].spec && 3442 efx_ef10_filter_entry_spec(table, filter_idx)->priority == 3443 priority) 3444 ++count; 3445 } 3446 spin_unlock_bh(&efx->filter_lock); 3447 return count; 3448 } 3449 3450 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx) 3451 { 3452 struct efx_ef10_filter_table *table = efx->filter_state; 3453 3454 return table->rx_match_count * HUNT_FILTER_TBL_ROWS; 3455 } 3456 3457 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx, 3458 enum efx_filter_priority priority, 3459 u32 *buf, u32 size) 3460 { 3461 struct efx_ef10_filter_table *table = efx->filter_state; 3462 struct efx_filter_spec *spec; 3463 unsigned int filter_idx; 3464 s32 count = 0; 3465 3466 spin_lock_bh(&efx->filter_lock); 3467 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3468 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3469 if (spec && spec->priority == priority) { 3470 if (count == size) { 3471 count = -EMSGSIZE; 3472 break; 3473 } 3474 buf[count++] = (efx_ef10_filter_rx_match_pri( 3475 table, spec->match_flags) * 3476 HUNT_FILTER_TBL_ROWS + 3477 filter_idx); 3478 } 3479 } 3480 spin_unlock_bh(&efx->filter_lock); 3481 return count; 3482 } 3483 3484 #ifdef CONFIG_RFS_ACCEL 3485 3486 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete; 3487 3488 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx, 3489 struct efx_filter_spec *spec) 3490 { 3491 struct efx_ef10_filter_table *table = efx->filter_state; 3492 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3493 struct efx_filter_spec *saved_spec; 3494 unsigned int hash, i, depth = 1; 3495 bool replacing = false; 3496 int ins_index = -1; 3497 u64 cookie; 3498 s32 rc; 3499 3500 /* Must be an RX filter without RSS and not for a multicast 3501 * destination address (RFS only works for connected sockets). 3502 * These restrictions allow us to pass only a tiny amount of 3503 * data through to the completion function. 3504 */ 3505 EFX_WARN_ON_PARANOID(spec->flags != 3506 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER)); 3507 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT); 3508 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec)); 3509 3510 hash = efx_ef10_filter_hash(spec); 3511 3512 spin_lock_bh(&efx->filter_lock); 3513 3514 /* Find any existing filter with the same match tuple or else 3515 * a free slot to insert at. If an existing filter is busy, 3516 * we have to give up. 3517 */ 3518 for (;;) { 3519 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 3520 saved_spec = efx_ef10_filter_entry_spec(table, i); 3521 3522 if (!saved_spec) { 3523 if (ins_index < 0) 3524 ins_index = i; 3525 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 3526 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) { 3527 rc = -EBUSY; 3528 goto fail_unlock; 3529 } 3530 if (spec->priority < saved_spec->priority) { 3531 rc = -EPERM; 3532 goto fail_unlock; 3533 } 3534 ins_index = i; 3535 break; 3536 } 3537 3538 /* Once we reach the maximum search depth, use the 3539 * first suitable slot or return -EBUSY if there was 3540 * none 3541 */ 3542 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 3543 if (ins_index < 0) { 3544 rc = -EBUSY; 3545 goto fail_unlock; 3546 } 3547 break; 3548 } 3549 3550 ++depth; 3551 } 3552 3553 /* Create a software table entry if necessary, and mark it 3554 * busy. We might yet fail to insert, but any attempt to 3555 * insert a conflicting filter while we're waiting for the 3556 * firmware must find the busy entry. 3557 */ 3558 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 3559 if (saved_spec) { 3560 replacing = true; 3561 } else { 3562 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 3563 if (!saved_spec) { 3564 rc = -ENOMEM; 3565 goto fail_unlock; 3566 } 3567 *saved_spec = *spec; 3568 } 3569 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 3570 EFX_EF10_FILTER_FLAG_BUSY); 3571 3572 spin_unlock_bh(&efx->filter_lock); 3573 3574 /* Pack up the variables needed on completion */ 3575 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id; 3576 3577 efx_ef10_filter_push_prep(efx, spec, inbuf, 3578 table->entry[ins_index].handle, replacing); 3579 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3580 MC_CMD_FILTER_OP_OUT_LEN, 3581 efx_ef10_filter_rfs_insert_complete, cookie); 3582 3583 return ins_index; 3584 3585 fail_unlock: 3586 spin_unlock_bh(&efx->filter_lock); 3587 return rc; 3588 } 3589 3590 static void 3591 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie, 3592 int rc, efx_dword_t *outbuf, 3593 size_t outlen_actual) 3594 { 3595 struct efx_ef10_filter_table *table = efx->filter_state; 3596 unsigned int ins_index, dmaq_id; 3597 struct efx_filter_spec *spec; 3598 bool replacing; 3599 3600 /* Unpack the cookie */ 3601 replacing = cookie >> 31; 3602 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1); 3603 dmaq_id = cookie & 0xffff; 3604 3605 spin_lock_bh(&efx->filter_lock); 3606 spec = efx_ef10_filter_entry_spec(table, ins_index); 3607 if (rc == 0) { 3608 table->entry[ins_index].handle = 3609 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 3610 if (replacing) 3611 spec->dmaq_id = dmaq_id; 3612 } else if (!replacing) { 3613 kfree(spec); 3614 spec = NULL; 3615 } 3616 efx_ef10_filter_set_entry(table, ins_index, spec, 0); 3617 spin_unlock_bh(&efx->filter_lock); 3618 3619 wake_up_all(&table->waitq); 3620 } 3621 3622 static void 3623 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 3624 unsigned long filter_idx, 3625 int rc, efx_dword_t *outbuf, 3626 size_t outlen_actual); 3627 3628 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, 3629 unsigned int filter_idx) 3630 { 3631 struct efx_ef10_filter_table *table = efx->filter_state; 3632 struct efx_filter_spec *spec = 3633 efx_ef10_filter_entry_spec(table, filter_idx); 3634 MCDI_DECLARE_BUF(inbuf, 3635 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 3636 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 3637 3638 if (!spec || 3639 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) || 3640 spec->priority != EFX_FILTER_PRI_HINT || 3641 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id, 3642 flow_id, filter_idx)) 3643 return false; 3644 3645 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3646 MC_CMD_FILTER_OP_IN_OP_REMOVE); 3647 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3648 table->entry[filter_idx].handle); 3649 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0, 3650 efx_ef10_filter_rfs_expire_complete, filter_idx)) 3651 return false; 3652 3653 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3654 return true; 3655 } 3656 3657 static void 3658 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 3659 unsigned long filter_idx, 3660 int rc, efx_dword_t *outbuf, 3661 size_t outlen_actual) 3662 { 3663 struct efx_ef10_filter_table *table = efx->filter_state; 3664 struct efx_filter_spec *spec = 3665 efx_ef10_filter_entry_spec(table, filter_idx); 3666 3667 spin_lock_bh(&efx->filter_lock); 3668 if (rc == 0) { 3669 kfree(spec); 3670 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3671 } 3672 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 3673 wake_up_all(&table->waitq); 3674 spin_unlock_bh(&efx->filter_lock); 3675 } 3676 3677 #endif /* CONFIG_RFS_ACCEL */ 3678 3679 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags) 3680 { 3681 int match_flags = 0; 3682 3683 #define MAP_FLAG(gen_flag, mcdi_field) { \ 3684 u32 old_mcdi_flags = mcdi_flags; \ 3685 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 3686 mcdi_field ## _LBN); \ 3687 if (mcdi_flags != old_mcdi_flags) \ 3688 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \ 3689 } 3690 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST); 3691 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST); 3692 MAP_FLAG(REM_HOST, SRC_IP); 3693 MAP_FLAG(LOC_HOST, DST_IP); 3694 MAP_FLAG(REM_MAC, SRC_MAC); 3695 MAP_FLAG(REM_PORT, SRC_PORT); 3696 MAP_FLAG(LOC_MAC, DST_MAC); 3697 MAP_FLAG(LOC_PORT, DST_PORT); 3698 MAP_FLAG(ETHER_TYPE, ETHER_TYPE); 3699 MAP_FLAG(INNER_VID, INNER_VLAN); 3700 MAP_FLAG(OUTER_VID, OUTER_VLAN); 3701 MAP_FLAG(IP_PROTO, IP_PROTO); 3702 #undef MAP_FLAG 3703 3704 /* Did we map them all? */ 3705 if (mcdi_flags) 3706 return -EINVAL; 3707 3708 return match_flags; 3709 } 3710 3711 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 3712 { 3713 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN); 3714 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX); 3715 unsigned int pd_match_pri, pd_match_count; 3716 struct efx_ef10_filter_table *table; 3717 size_t outlen; 3718 int rc; 3719 3720 table = kzalloc(sizeof(*table), GFP_KERNEL); 3721 if (!table) 3722 return -ENOMEM; 3723 3724 /* Find out which RX filter types are supported, and their priorities */ 3725 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP, 3726 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); 3727 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO, 3728 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf), 3729 &outlen); 3730 if (rc) 3731 goto fail; 3732 pd_match_count = MCDI_VAR_ARRAY_LEN( 3733 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES); 3734 table->rx_match_count = 0; 3735 3736 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) { 3737 u32 mcdi_flags = 3738 MCDI_ARRAY_DWORD( 3739 outbuf, 3740 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES, 3741 pd_match_pri); 3742 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags); 3743 if (rc < 0) { 3744 netif_dbg(efx, probe, efx->net_dev, 3745 "%s: fw flags %#x pri %u not supported in driver\n", 3746 __func__, mcdi_flags, pd_match_pri); 3747 } else { 3748 netif_dbg(efx, probe, efx->net_dev, 3749 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n", 3750 __func__, mcdi_flags, pd_match_pri, 3751 rc, table->rx_match_count); 3752 table->rx_match_flags[table->rx_match_count++] = rc; 3753 } 3754 } 3755 3756 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry)); 3757 if (!table->entry) { 3758 rc = -ENOMEM; 3759 goto fail; 3760 } 3761 3762 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID; 3763 table->bcast_id = EFX_EF10_FILTER_ID_INVALID; 3764 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID; 3765 3766 efx->filter_state = table; 3767 init_waitqueue_head(&table->waitq); 3768 return 0; 3769 3770 fail: 3771 kfree(table); 3772 return rc; 3773 } 3774 3775 /* Caller must hold efx->filter_sem for read if race against 3776 * efx_ef10_filter_table_remove() is possible 3777 */ 3778 static void efx_ef10_filter_table_restore(struct efx_nic *efx) 3779 { 3780 struct efx_ef10_filter_table *table = efx->filter_state; 3781 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3782 struct efx_filter_spec *spec; 3783 unsigned int filter_idx; 3784 bool failed = false; 3785 int rc; 3786 3787 WARN_ON(!rwsem_is_locked(&efx->filter_sem)); 3788 3789 if (!nic_data->must_restore_filters) 3790 return; 3791 3792 if (!table) 3793 return; 3794 3795 spin_lock_bh(&efx->filter_lock); 3796 3797 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3798 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3799 if (!spec) 3800 continue; 3801 3802 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3803 spin_unlock_bh(&efx->filter_lock); 3804 3805 rc = efx_ef10_filter_push(efx, spec, 3806 &table->entry[filter_idx].handle, 3807 false); 3808 if (rc) 3809 failed = true; 3810 3811 spin_lock_bh(&efx->filter_lock); 3812 if (rc) { 3813 kfree(spec); 3814 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3815 } else { 3816 table->entry[filter_idx].spec &= 3817 ~EFX_EF10_FILTER_FLAG_BUSY; 3818 } 3819 } 3820 3821 spin_unlock_bh(&efx->filter_lock); 3822 3823 if (failed) 3824 netif_err(efx, hw, efx->net_dev, 3825 "unable to restore all filters\n"); 3826 else 3827 nic_data->must_restore_filters = false; 3828 } 3829 3830 /* Caller must hold efx->filter_sem for write */ 3831 static void efx_ef10_filter_table_remove(struct efx_nic *efx) 3832 { 3833 struct efx_ef10_filter_table *table = efx->filter_state; 3834 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3835 struct efx_filter_spec *spec; 3836 unsigned int filter_idx; 3837 int rc; 3838 3839 efx->filter_state = NULL; 3840 if (!table) 3841 return; 3842 3843 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3844 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3845 if (!spec) 3846 continue; 3847 3848 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3849 efx_ef10_filter_is_exclusive(spec) ? 3850 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3851 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3852 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3853 table->entry[filter_idx].handle); 3854 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf, 3855 sizeof(inbuf), NULL, 0, NULL); 3856 if (rc) 3857 netif_info(efx, drv, efx->net_dev, 3858 "%s: filter %04x remove failed\n", 3859 __func__, filter_idx); 3860 kfree(spec); 3861 } 3862 3863 vfree(table->entry); 3864 kfree(table); 3865 } 3866 3867 #define EFX_EF10_FILTER_DO_MARK_OLD(id) \ 3868 if (id != EFX_EF10_FILTER_ID_INVALID) { \ 3869 filter_idx = efx_ef10_filter_get_unsafe_id(efx, id); \ 3870 if (!table->entry[filter_idx].spec) \ 3871 netif_dbg(efx, drv, efx->net_dev, \ 3872 "%s: marked null spec old %04x:%04x\n", \ 3873 __func__, id, filter_idx); \ 3874 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;\ 3875 } 3876 static void efx_ef10_filter_mark_old(struct efx_nic *efx) 3877 { 3878 struct efx_ef10_filter_table *table = efx->filter_state; 3879 unsigned int filter_idx, i; 3880 3881 if (!table) 3882 return; 3883 3884 /* Mark old filters that may need to be removed */ 3885 spin_lock_bh(&efx->filter_lock); 3886 for (i = 0; i < table->dev_uc_count; i++) 3887 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_uc_list[i].id); 3888 for (i = 0; i < table->dev_mc_count; i++) 3889 EFX_EF10_FILTER_DO_MARK_OLD(table->dev_mc_list[i].id); 3890 EFX_EF10_FILTER_DO_MARK_OLD(table->ucdef_id); 3891 EFX_EF10_FILTER_DO_MARK_OLD(table->bcast_id); 3892 EFX_EF10_FILTER_DO_MARK_OLD(table->mcdef_id); 3893 spin_unlock_bh(&efx->filter_lock); 3894 } 3895 #undef EFX_EF10_FILTER_DO_MARK_OLD 3896 3897 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx, bool *promisc) 3898 { 3899 struct efx_ef10_filter_table *table = efx->filter_state; 3900 struct net_device *net_dev = efx->net_dev; 3901 struct netdev_hw_addr *uc; 3902 int addr_count; 3903 unsigned int i; 3904 3905 table->ucdef_id = EFX_EF10_FILTER_ID_INVALID; 3906 addr_count = netdev_uc_count(net_dev); 3907 if (net_dev->flags & IFF_PROMISC) 3908 *promisc = true; 3909 table->dev_uc_count = 1 + addr_count; 3910 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr); 3911 i = 1; 3912 netdev_for_each_uc_addr(uc, net_dev) { 3913 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) { 3914 *promisc = true; 3915 break; 3916 } 3917 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr); 3918 table->dev_uc_list[i].id = EFX_EF10_FILTER_ID_INVALID; 3919 i++; 3920 } 3921 } 3922 3923 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx, bool *promisc) 3924 { 3925 struct efx_ef10_filter_table *table = efx->filter_state; 3926 struct net_device *net_dev = efx->net_dev; 3927 struct netdev_hw_addr *mc; 3928 unsigned int i, addr_count; 3929 3930 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID; 3931 table->bcast_id = EFX_EF10_FILTER_ID_INVALID; 3932 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) 3933 *promisc = true; 3934 3935 addr_count = netdev_mc_count(net_dev); 3936 i = 0; 3937 netdev_for_each_mc_addr(mc, net_dev) { 3938 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) { 3939 *promisc = true; 3940 break; 3941 } 3942 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr); 3943 table->dev_mc_list[i].id = EFX_EF10_FILTER_ID_INVALID; 3944 i++; 3945 } 3946 3947 table->dev_mc_count = i; 3948 } 3949 3950 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx, 3951 bool multicast, bool rollback) 3952 { 3953 struct efx_ef10_filter_table *table = efx->filter_state; 3954 struct efx_ef10_dev_addr *addr_list; 3955 enum efx_filter_flags filter_flags; 3956 struct efx_filter_spec spec; 3957 u8 baddr[ETH_ALEN]; 3958 unsigned int i, j; 3959 int addr_count; 3960 int rc; 3961 3962 if (multicast) { 3963 addr_list = table->dev_mc_list; 3964 addr_count = table->dev_mc_count; 3965 } else { 3966 addr_list = table->dev_uc_list; 3967 addr_count = table->dev_uc_count; 3968 } 3969 3970 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0; 3971 3972 /* Insert/renew filters */ 3973 for (i = 0; i < addr_count; i++) { 3974 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 3975 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 3976 addr_list[i].addr); 3977 rc = efx_ef10_filter_insert(efx, &spec, true); 3978 if (rc < 0) { 3979 if (rollback) { 3980 netif_info(efx, drv, efx->net_dev, 3981 "efx_ef10_filter_insert failed rc=%d\n", 3982 rc); 3983 /* Fall back to promiscuous */ 3984 for (j = 0; j < i; j++) { 3985 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID) 3986 continue; 3987 efx_ef10_filter_remove_unsafe( 3988 efx, EFX_FILTER_PRI_AUTO, 3989 addr_list[j].id); 3990 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID; 3991 } 3992 return rc; 3993 } else { 3994 /* mark as not inserted, and carry on */ 3995 rc = EFX_EF10_FILTER_ID_INVALID; 3996 } 3997 } 3998 addr_list[i].id = efx_ef10_filter_get_unsafe_id(efx, rc); 3999 } 4000 4001 if (multicast && rollback) { 4002 /* Also need an Ethernet broadcast filter */ 4003 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 4004 eth_broadcast_addr(baddr); 4005 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, baddr); 4006 rc = efx_ef10_filter_insert(efx, &spec, true); 4007 if (rc < 0) { 4008 netif_warn(efx, drv, efx->net_dev, 4009 "Broadcast filter insert failed rc=%d\n", rc); 4010 /* Fall back to promiscuous */ 4011 for (j = 0; j < i; j++) { 4012 if (addr_list[j].id == EFX_EF10_FILTER_ID_INVALID) 4013 continue; 4014 efx_ef10_filter_remove_unsafe( 4015 efx, EFX_FILTER_PRI_AUTO, 4016 addr_list[j].id); 4017 addr_list[j].id = EFX_EF10_FILTER_ID_INVALID; 4018 } 4019 return rc; 4020 } else { 4021 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc); 4022 } 4023 } 4024 4025 return 0; 4026 } 4027 4028 static int efx_ef10_filter_insert_def(struct efx_nic *efx, bool multicast, 4029 bool rollback) 4030 { 4031 struct efx_ef10_filter_table *table = efx->filter_state; 4032 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4033 enum efx_filter_flags filter_flags; 4034 struct efx_filter_spec spec; 4035 u8 baddr[ETH_ALEN]; 4036 int rc; 4037 4038 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0; 4039 4040 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0); 4041 4042 if (multicast) 4043 efx_filter_set_mc_def(&spec); 4044 else 4045 efx_filter_set_uc_def(&spec); 4046 4047 rc = efx_ef10_filter_insert(efx, &spec, true); 4048 if (rc < 0) { 4049 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING, 4050 efx->net_dev, 4051 "%scast mismatch filter insert failed rc=%d\n", 4052 multicast ? "Multi" : "Uni", rc); 4053 } else if (multicast) { 4054 table->mcdef_id = efx_ef10_filter_get_unsafe_id(efx, rc); 4055 if (!nic_data->workaround_26807) { 4056 /* Also need an Ethernet broadcast filter */ 4057 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 4058 filter_flags, 0); 4059 eth_broadcast_addr(baddr); 4060 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 4061 baddr); 4062 rc = efx_ef10_filter_insert(efx, &spec, true); 4063 if (rc < 0) { 4064 netif_warn(efx, drv, efx->net_dev, 4065 "Broadcast filter insert failed rc=%d\n", 4066 rc); 4067 if (rollback) { 4068 /* Roll back the mc_def filter */ 4069 efx_ef10_filter_remove_unsafe( 4070 efx, EFX_FILTER_PRI_AUTO, 4071 table->mcdef_id); 4072 table->mcdef_id = EFX_EF10_FILTER_ID_INVALID; 4073 return rc; 4074 } 4075 } else { 4076 table->bcast_id = efx_ef10_filter_get_unsafe_id(efx, rc); 4077 } 4078 } 4079 rc = 0; 4080 } else { 4081 table->ucdef_id = rc; 4082 rc = 0; 4083 } 4084 return rc; 4085 } 4086 4087 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD 4088 * flag or removes these filters, we don't need to hold the filter_lock while 4089 * scanning for these filters. 4090 */ 4091 static void efx_ef10_filter_remove_old(struct efx_nic *efx) 4092 { 4093 struct efx_ef10_filter_table *table = efx->filter_state; 4094 int remove_failed = 0; 4095 int remove_noent = 0; 4096 int rc; 4097 int i; 4098 4099 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 4100 if (ACCESS_ONCE(table->entry[i].spec) & 4101 EFX_EF10_FILTER_FLAG_AUTO_OLD) { 4102 rc = efx_ef10_filter_remove_internal(efx, 4103 1U << EFX_FILTER_PRI_AUTO, i, true); 4104 if (rc == -ENOENT) 4105 remove_noent++; 4106 else if (rc) 4107 remove_failed++; 4108 } 4109 } 4110 4111 if (remove_failed) 4112 netif_info(efx, drv, efx->net_dev, 4113 "%s: failed to remove %d filters\n", 4114 __func__, remove_failed); 4115 if (remove_noent) 4116 netif_info(efx, drv, efx->net_dev, 4117 "%s: failed to remove %d non-existent filters\n", 4118 __func__, remove_noent); 4119 } 4120 4121 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 4122 { 4123 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4124 u8 mac_old[ETH_ALEN]; 4125 int rc, rc2; 4126 4127 /* Only reconfigure a PF-created vport */ 4128 if (is_zero_ether_addr(nic_data->vport_mac)) 4129 return 0; 4130 4131 efx_device_detach_sync(efx); 4132 efx_net_stop(efx->net_dev); 4133 down_write(&efx->filter_sem); 4134 efx_ef10_filter_table_remove(efx); 4135 up_write(&efx->filter_sem); 4136 4137 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id); 4138 if (rc) 4139 goto restore_filters; 4140 4141 ether_addr_copy(mac_old, nic_data->vport_mac); 4142 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id, 4143 nic_data->vport_mac); 4144 if (rc) 4145 goto restore_vadaptor; 4146 4147 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id, 4148 efx->net_dev->dev_addr); 4149 if (!rc) { 4150 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 4151 } else { 4152 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old); 4153 if (rc2) { 4154 /* Failed to add original MAC, so clear vport_mac */ 4155 eth_zero_addr(nic_data->vport_mac); 4156 goto reset_nic; 4157 } 4158 } 4159 4160 restore_vadaptor: 4161 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id); 4162 if (rc2) 4163 goto reset_nic; 4164 restore_filters: 4165 down_write(&efx->filter_sem); 4166 rc2 = efx_ef10_filter_table_probe(efx); 4167 up_write(&efx->filter_sem); 4168 if (rc2) 4169 goto reset_nic; 4170 4171 rc2 = efx_net_open(efx->net_dev); 4172 if (rc2) 4173 goto reset_nic; 4174 4175 netif_device_attach(efx->net_dev); 4176 4177 return rc; 4178 4179 reset_nic: 4180 netif_err(efx, drv, efx->net_dev, 4181 "Failed to restore when changing MAC address - scheduling reset\n"); 4182 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 4183 4184 return rc ? rc : rc2; 4185 } 4186 4187 /* Caller must hold efx->filter_sem for read if race against 4188 * efx_ef10_filter_table_remove() is possible 4189 */ 4190 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx) 4191 { 4192 struct efx_ef10_filter_table *table = efx->filter_state; 4193 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4194 struct net_device *net_dev = efx->net_dev; 4195 bool uc_promisc = false, mc_promisc = false; 4196 4197 if (!efx_dev_registered(efx)) 4198 return; 4199 4200 if (!table) 4201 return; 4202 4203 efx_ef10_filter_mark_old(efx); 4204 4205 /* Copy/convert the address lists; add the primary station 4206 * address and broadcast address 4207 */ 4208 netif_addr_lock_bh(net_dev); 4209 efx_ef10_filter_uc_addr_list(efx, &uc_promisc); 4210 efx_ef10_filter_mc_addr_list(efx, &mc_promisc); 4211 netif_addr_unlock_bh(net_dev); 4212 4213 /* Insert/renew unicast filters */ 4214 if (uc_promisc) { 4215 efx_ef10_filter_insert_def(efx, false, false); 4216 efx_ef10_filter_insert_addr_list(efx, false, false); 4217 } else { 4218 /* If any of the filters failed to insert, fall back to 4219 * promiscuous mode - add in the uc_def filter. But keep 4220 * our individual unicast filters. 4221 */ 4222 if (efx_ef10_filter_insert_addr_list(efx, false, false)) 4223 efx_ef10_filter_insert_def(efx, false, false); 4224 } 4225 4226 /* Insert/renew multicast filters */ 4227 /* If changing promiscuous state with cascaded multicast filters, remove 4228 * old filters first, so that packets are dropped rather than duplicated 4229 */ 4230 if (nic_data->workaround_26807 && efx->mc_promisc != mc_promisc) 4231 efx_ef10_filter_remove_old(efx); 4232 if (mc_promisc) { 4233 if (nic_data->workaround_26807) { 4234 /* If we failed to insert promiscuous filters, rollback 4235 * and fall back to individual multicast filters 4236 */ 4237 if (efx_ef10_filter_insert_def(efx, true, true)) { 4238 /* Changing promisc state, so remove old filters */ 4239 efx_ef10_filter_remove_old(efx); 4240 efx_ef10_filter_insert_addr_list(efx, true, false); 4241 } 4242 } else { 4243 /* If we failed to insert promiscuous filters, don't 4244 * rollback. Regardless, also insert the mc_list 4245 */ 4246 efx_ef10_filter_insert_def(efx, true, false); 4247 efx_ef10_filter_insert_addr_list(efx, true, false); 4248 } 4249 } else { 4250 /* If any filters failed to insert, rollback and fall back to 4251 * promiscuous mode - mc_def filter and maybe broadcast. If 4252 * that fails, roll back again and insert as many of our 4253 * individual multicast filters as we can. 4254 */ 4255 if (efx_ef10_filter_insert_addr_list(efx, true, true)) { 4256 /* Changing promisc state, so remove old filters */ 4257 if (nic_data->workaround_26807) 4258 efx_ef10_filter_remove_old(efx); 4259 if (efx_ef10_filter_insert_def(efx, true, true)) 4260 efx_ef10_filter_insert_addr_list(efx, true, false); 4261 } 4262 } 4263 4264 efx_ef10_filter_remove_old(efx); 4265 efx->mc_promisc = mc_promisc; 4266 } 4267 4268 static int efx_ef10_set_mac_address(struct efx_nic *efx) 4269 { 4270 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 4271 struct efx_ef10_nic_data *nic_data = efx->nic_data; 4272 bool was_enabled = efx->port_enabled; 4273 int rc; 4274 4275 efx_device_detach_sync(efx); 4276 efx_net_stop(efx->net_dev); 4277 down_write(&efx->filter_sem); 4278 efx_ef10_filter_table_remove(efx); 4279 4280 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 4281 efx->net_dev->dev_addr); 4282 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 4283 nic_data->vport_id); 4284 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 4285 sizeof(inbuf), NULL, 0, NULL); 4286 4287 efx_ef10_filter_table_probe(efx); 4288 up_write(&efx->filter_sem); 4289 if (was_enabled) 4290 efx_net_open(efx->net_dev); 4291 netif_device_attach(efx->net_dev); 4292 4293 #ifdef CONFIG_SFC_SRIOV 4294 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 4295 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 4296 4297 if (rc == -EPERM) { 4298 struct efx_nic *efx_pf; 4299 4300 /* Switch to PF and change MAC address on vport */ 4301 efx_pf = pci_get_drvdata(pci_dev_pf); 4302 4303 rc = efx_ef10_sriov_set_vf_mac(efx_pf, 4304 nic_data->vf_index, 4305 efx->net_dev->dev_addr); 4306 } else if (!rc) { 4307 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 4308 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data; 4309 unsigned int i; 4310 4311 /* MAC address successfully changed by VF (with MAC 4312 * spoofing) so update the parent PF if possible. 4313 */ 4314 for (i = 0; i < efx_pf->vf_count; ++i) { 4315 struct ef10_vf *vf = nic_data->vf + i; 4316 4317 if (vf->efx == efx) { 4318 ether_addr_copy(vf->mac, 4319 efx->net_dev->dev_addr); 4320 return 0; 4321 } 4322 } 4323 } 4324 } else 4325 #endif 4326 if (rc == -EPERM) { 4327 netif_err(efx, drv, efx->net_dev, 4328 "Cannot change MAC address; use sfboot to enable" 4329 " mac-spoofing on this interface\n"); 4330 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 4331 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 4332 * fall-back to the method of changing the MAC address on the 4333 * vport. This only applies to PFs because such versions of 4334 * MCFW do not support VFs. 4335 */ 4336 rc = efx_ef10_vport_set_mac_address(efx); 4337 } else { 4338 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 4339 sizeof(inbuf), NULL, 0, rc); 4340 } 4341 4342 return rc; 4343 } 4344 4345 static int efx_ef10_mac_reconfigure(struct efx_nic *efx) 4346 { 4347 efx_ef10_filter_sync_rx_mode(efx); 4348 4349 return efx_mcdi_set_mac(efx); 4350 } 4351 4352 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx) 4353 { 4354 efx_ef10_filter_sync_rx_mode(efx); 4355 4356 return 0; 4357 } 4358 4359 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 4360 { 4361 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 4362 4363 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 4364 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 4365 NULL, 0, NULL); 4366 } 4367 4368 /* MC BISTs follow a different poll mechanism to phy BISTs. 4369 * The BIST is done in the poll handler on the MC, and the MCDI command 4370 * will block until the BIST is done. 4371 */ 4372 static int efx_ef10_poll_bist(struct efx_nic *efx) 4373 { 4374 int rc; 4375 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 4376 size_t outlen; 4377 u32 result; 4378 4379 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 4380 outbuf, sizeof(outbuf), &outlen); 4381 if (rc != 0) 4382 return rc; 4383 4384 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 4385 return -EIO; 4386 4387 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 4388 switch (result) { 4389 case MC_CMD_POLL_BIST_PASSED: 4390 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 4391 return 0; 4392 case MC_CMD_POLL_BIST_TIMEOUT: 4393 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 4394 return -EIO; 4395 case MC_CMD_POLL_BIST_FAILED: 4396 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 4397 return -EIO; 4398 default: 4399 netif_err(efx, hw, efx->net_dev, 4400 "BIST returned unknown result %u", result); 4401 return -EIO; 4402 } 4403 } 4404 4405 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 4406 { 4407 int rc; 4408 4409 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 4410 4411 rc = efx_ef10_start_bist(efx, bist_type); 4412 if (rc != 0) 4413 return rc; 4414 4415 return efx_ef10_poll_bist(efx); 4416 } 4417 4418 static int 4419 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 4420 { 4421 int rc, rc2; 4422 4423 efx_reset_down(efx, RESET_TYPE_WORLD); 4424 4425 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 4426 NULL, 0, NULL, 0, NULL); 4427 if (rc != 0) 4428 goto out; 4429 4430 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 4431 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 4432 4433 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 4434 4435 out: 4436 if (rc == -EPERM) 4437 rc = 0; 4438 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 4439 return rc ? rc : rc2; 4440 } 4441 4442 #ifdef CONFIG_SFC_MTD 4443 4444 struct efx_ef10_nvram_type_info { 4445 u16 type, type_mask; 4446 u8 port; 4447 const char *name; 4448 }; 4449 4450 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 4451 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 4452 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 4453 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 4454 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 4455 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 4456 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 4457 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 4458 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 4459 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 4460 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 4461 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 4462 }; 4463 4464 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 4465 struct efx_mcdi_mtd_partition *part, 4466 unsigned int type) 4467 { 4468 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 4469 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 4470 const struct efx_ef10_nvram_type_info *info; 4471 size_t size, erase_size, outlen; 4472 bool protected; 4473 int rc; 4474 4475 for (info = efx_ef10_nvram_types; ; info++) { 4476 if (info == 4477 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types)) 4478 return -ENODEV; 4479 if ((type & ~info->type_mask) == info->type) 4480 break; 4481 } 4482 if (info->port != efx_port_num(efx)) 4483 return -ENODEV; 4484 4485 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 4486 if (rc) 4487 return rc; 4488 if (protected) 4489 return -ENODEV; /* hide it */ 4490 4491 part->nvram_type = type; 4492 4493 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 4494 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 4495 outbuf, sizeof(outbuf), &outlen); 4496 if (rc) 4497 return rc; 4498 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 4499 return -EIO; 4500 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 4501 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 4502 part->fw_subtype = MCDI_DWORD(outbuf, 4503 NVRAM_METADATA_OUT_SUBTYPE); 4504 4505 part->common.dev_type_name = "EF10 NVRAM manager"; 4506 part->common.type_name = info->name; 4507 4508 part->common.mtd.type = MTD_NORFLASH; 4509 part->common.mtd.flags = MTD_CAP_NORFLASH; 4510 part->common.mtd.size = size; 4511 part->common.mtd.erasesize = erase_size; 4512 4513 return 0; 4514 } 4515 4516 static int efx_ef10_mtd_probe(struct efx_nic *efx) 4517 { 4518 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 4519 struct efx_mcdi_mtd_partition *parts; 4520 size_t outlen, n_parts_total, i, n_parts; 4521 unsigned int type; 4522 int rc; 4523 4524 ASSERT_RTNL(); 4525 4526 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 4527 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 4528 outbuf, sizeof(outbuf), &outlen); 4529 if (rc) 4530 return rc; 4531 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 4532 return -EIO; 4533 4534 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 4535 if (n_parts_total > 4536 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 4537 return -EIO; 4538 4539 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 4540 if (!parts) 4541 return -ENOMEM; 4542 4543 n_parts = 0; 4544 for (i = 0; i < n_parts_total; i++) { 4545 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 4546 i); 4547 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type); 4548 if (rc == 0) 4549 n_parts++; 4550 else if (rc != -ENODEV) 4551 goto fail; 4552 } 4553 4554 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 4555 fail: 4556 if (rc) 4557 kfree(parts); 4558 return rc; 4559 } 4560 4561 #endif /* CONFIG_SFC_MTD */ 4562 4563 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 4564 { 4565 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 4566 } 4567 4568 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 4569 u32 host_time) {} 4570 4571 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 4572 bool temp) 4573 { 4574 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 4575 int rc; 4576 4577 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 4578 channel->sync_events_state == SYNC_EVENTS_VALID || 4579 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 4580 return 0; 4581 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 4582 4583 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 4584 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 4585 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 4586 channel->channel); 4587 4588 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 4589 inbuf, sizeof(inbuf), NULL, 0, NULL); 4590 4591 if (rc != 0) 4592 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 4593 SYNC_EVENTS_DISABLED; 4594 4595 return rc; 4596 } 4597 4598 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 4599 bool temp) 4600 { 4601 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 4602 int rc; 4603 4604 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 4605 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 4606 return 0; 4607 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 4608 channel->sync_events_state = SYNC_EVENTS_DISABLED; 4609 return 0; 4610 } 4611 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 4612 SYNC_EVENTS_DISABLED; 4613 4614 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 4615 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 4616 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 4617 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 4618 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 4619 channel->channel); 4620 4621 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 4622 inbuf, sizeof(inbuf), NULL, 0, NULL); 4623 4624 return rc; 4625 } 4626 4627 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 4628 bool temp) 4629 { 4630 int (*set)(struct efx_channel *channel, bool temp); 4631 struct efx_channel *channel; 4632 4633 set = en ? 4634 efx_ef10_rx_enable_timestamping : 4635 efx_ef10_rx_disable_timestamping; 4636 4637 efx_for_each_channel(channel, efx) { 4638 int rc = set(channel, temp); 4639 if (en && rc != 0) { 4640 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 4641 return rc; 4642 } 4643 } 4644 4645 return 0; 4646 } 4647 4648 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 4649 struct hwtstamp_config *init) 4650 { 4651 return -EOPNOTSUPP; 4652 } 4653 4654 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 4655 struct hwtstamp_config *init) 4656 { 4657 int rc; 4658 4659 switch (init->rx_filter) { 4660 case HWTSTAMP_FILTER_NONE: 4661 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 4662 /* if TX timestamping is still requested then leave PTP on */ 4663 return efx_ptp_change_mode(efx, 4664 init->tx_type != HWTSTAMP_TX_OFF, 0); 4665 case HWTSTAMP_FILTER_ALL: 4666 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 4667 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 4668 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 4669 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 4670 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 4671 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 4672 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 4673 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 4674 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 4675 case HWTSTAMP_FILTER_PTP_V2_EVENT: 4676 case HWTSTAMP_FILTER_PTP_V2_SYNC: 4677 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 4678 init->rx_filter = HWTSTAMP_FILTER_ALL; 4679 rc = efx_ptp_change_mode(efx, true, 0); 4680 if (!rc) 4681 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 4682 if (rc) 4683 efx_ptp_change_mode(efx, false, 0); 4684 return rc; 4685 default: 4686 return -ERANGE; 4687 } 4688 } 4689 4690 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 4691 .is_vf = true, 4692 .mem_bar = EFX_MEM_VF_BAR, 4693 .mem_map_size = efx_ef10_mem_map_size, 4694 .probe = efx_ef10_probe_vf, 4695 .remove = efx_ef10_remove, 4696 .dimension_resources = efx_ef10_dimension_resources, 4697 .init = efx_ef10_init_nic, 4698 .fini = efx_port_dummy_op_void, 4699 .map_reset_reason = efx_ef10_map_reset_reason, 4700 .map_reset_flags = efx_ef10_map_reset_flags, 4701 .reset = efx_ef10_reset, 4702 .probe_port = efx_mcdi_port_probe, 4703 .remove_port = efx_mcdi_port_remove, 4704 .fini_dmaq = efx_ef10_fini_dmaq, 4705 .prepare_flr = efx_ef10_prepare_flr, 4706 .finish_flr = efx_port_dummy_op_void, 4707 .describe_stats = efx_ef10_describe_stats, 4708 .update_stats = efx_ef10_update_stats_vf, 4709 .start_stats = efx_port_dummy_op_void, 4710 .pull_stats = efx_port_dummy_op_void, 4711 .stop_stats = efx_port_dummy_op_void, 4712 .set_id_led = efx_mcdi_set_id_led, 4713 .push_irq_moderation = efx_ef10_push_irq_moderation, 4714 .reconfigure_mac = efx_ef10_mac_reconfigure_vf, 4715 .check_mac_fault = efx_mcdi_mac_check_fault, 4716 .reconfigure_port = efx_mcdi_port_reconfigure, 4717 .get_wol = efx_ef10_get_wol_vf, 4718 .set_wol = efx_ef10_set_wol_vf, 4719 .resume_wol = efx_port_dummy_op_void, 4720 .mcdi_request = efx_ef10_mcdi_request, 4721 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4722 .mcdi_read_response = efx_ef10_mcdi_read_response, 4723 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4724 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4725 .irq_enable_master = efx_port_dummy_op_void, 4726 .irq_test_generate = efx_ef10_irq_test_generate, 4727 .irq_disable_non_ev = efx_port_dummy_op_void, 4728 .irq_handle_msi = efx_ef10_msi_interrupt, 4729 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4730 .tx_probe = efx_ef10_tx_probe, 4731 .tx_init = efx_ef10_tx_init, 4732 .tx_remove = efx_ef10_tx_remove, 4733 .tx_write = efx_ef10_tx_write, 4734 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config, 4735 .rx_probe = efx_ef10_rx_probe, 4736 .rx_init = efx_ef10_rx_init, 4737 .rx_remove = efx_ef10_rx_remove, 4738 .rx_write = efx_ef10_rx_write, 4739 .rx_defer_refill = efx_ef10_rx_defer_refill, 4740 .ev_probe = efx_ef10_ev_probe, 4741 .ev_init = efx_ef10_ev_init, 4742 .ev_fini = efx_ef10_ev_fini, 4743 .ev_remove = efx_ef10_ev_remove, 4744 .ev_process = efx_ef10_ev_process, 4745 .ev_read_ack = efx_ef10_ev_read_ack, 4746 .ev_test_generate = efx_ef10_ev_test_generate, 4747 .filter_table_probe = efx_ef10_filter_table_probe, 4748 .filter_table_restore = efx_ef10_filter_table_restore, 4749 .filter_table_remove = efx_ef10_filter_table_remove, 4750 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 4751 .filter_insert = efx_ef10_filter_insert, 4752 .filter_remove_safe = efx_ef10_filter_remove_safe, 4753 .filter_get_safe = efx_ef10_filter_get_safe, 4754 .filter_clear_rx = efx_ef10_filter_clear_rx, 4755 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 4756 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 4757 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 4758 #ifdef CONFIG_RFS_ACCEL 4759 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 4760 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 4761 #endif 4762 #ifdef CONFIG_SFC_MTD 4763 .mtd_probe = efx_port_dummy_op_int, 4764 #endif 4765 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4766 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4767 #ifdef CONFIG_SFC_SRIOV 4768 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4769 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4770 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4771 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id, 4772 #endif 4773 .get_mac_address = efx_ef10_get_mac_address_vf, 4774 .set_mac_address = efx_ef10_set_mac_address, 4775 4776 .revision = EFX_REV_HUNT_A0, 4777 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4778 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4779 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4780 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4781 .can_rx_scatter = true, 4782 .always_rx_scatter = true, 4783 .max_interrupt_mode = EFX_INT_MODE_MSIX, 4784 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4785 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4786 NETIF_F_RXHASH | NETIF_F_NTUPLE), 4787 .mcdi_max_ver = 2, 4788 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 4789 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4790 1 << HWTSTAMP_FILTER_ALL, 4791 }; 4792 4793 const struct efx_nic_type efx_hunt_a0_nic_type = { 4794 .is_vf = false, 4795 .mem_bar = EFX_MEM_BAR, 4796 .mem_map_size = efx_ef10_mem_map_size, 4797 .probe = efx_ef10_probe_pf, 4798 .remove = efx_ef10_remove, 4799 .dimension_resources = efx_ef10_dimension_resources, 4800 .init = efx_ef10_init_nic, 4801 .fini = efx_port_dummy_op_void, 4802 .map_reset_reason = efx_ef10_map_reset_reason, 4803 .map_reset_flags = efx_ef10_map_reset_flags, 4804 .reset = efx_ef10_reset, 4805 .probe_port = efx_mcdi_port_probe, 4806 .remove_port = efx_mcdi_port_remove, 4807 .fini_dmaq = efx_ef10_fini_dmaq, 4808 .prepare_flr = efx_ef10_prepare_flr, 4809 .finish_flr = efx_port_dummy_op_void, 4810 .describe_stats = efx_ef10_describe_stats, 4811 .update_stats = efx_ef10_update_stats_pf, 4812 .start_stats = efx_mcdi_mac_start_stats, 4813 .pull_stats = efx_mcdi_mac_pull_stats, 4814 .stop_stats = efx_mcdi_mac_stop_stats, 4815 .set_id_led = efx_mcdi_set_id_led, 4816 .push_irq_moderation = efx_ef10_push_irq_moderation, 4817 .reconfigure_mac = efx_ef10_mac_reconfigure, 4818 .check_mac_fault = efx_mcdi_mac_check_fault, 4819 .reconfigure_port = efx_mcdi_port_reconfigure, 4820 .get_wol = efx_ef10_get_wol, 4821 .set_wol = efx_ef10_set_wol, 4822 .resume_wol = efx_port_dummy_op_void, 4823 .test_chip = efx_ef10_test_chip, 4824 .test_nvram = efx_mcdi_nvram_test_all, 4825 .mcdi_request = efx_ef10_mcdi_request, 4826 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4827 .mcdi_read_response = efx_ef10_mcdi_read_response, 4828 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4829 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4830 .irq_enable_master = efx_port_dummy_op_void, 4831 .irq_test_generate = efx_ef10_irq_test_generate, 4832 .irq_disable_non_ev = efx_port_dummy_op_void, 4833 .irq_handle_msi = efx_ef10_msi_interrupt, 4834 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4835 .tx_probe = efx_ef10_tx_probe, 4836 .tx_init = efx_ef10_tx_init, 4837 .tx_remove = efx_ef10_tx_remove, 4838 .tx_write = efx_ef10_tx_write, 4839 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config, 4840 .rx_probe = efx_ef10_rx_probe, 4841 .rx_init = efx_ef10_rx_init, 4842 .rx_remove = efx_ef10_rx_remove, 4843 .rx_write = efx_ef10_rx_write, 4844 .rx_defer_refill = efx_ef10_rx_defer_refill, 4845 .ev_probe = efx_ef10_ev_probe, 4846 .ev_init = efx_ef10_ev_init, 4847 .ev_fini = efx_ef10_ev_fini, 4848 .ev_remove = efx_ef10_ev_remove, 4849 .ev_process = efx_ef10_ev_process, 4850 .ev_read_ack = efx_ef10_ev_read_ack, 4851 .ev_test_generate = efx_ef10_ev_test_generate, 4852 .filter_table_probe = efx_ef10_filter_table_probe, 4853 .filter_table_restore = efx_ef10_filter_table_restore, 4854 .filter_table_remove = efx_ef10_filter_table_remove, 4855 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 4856 .filter_insert = efx_ef10_filter_insert, 4857 .filter_remove_safe = efx_ef10_filter_remove_safe, 4858 .filter_get_safe = efx_ef10_filter_get_safe, 4859 .filter_clear_rx = efx_ef10_filter_clear_rx, 4860 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 4861 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 4862 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 4863 #ifdef CONFIG_RFS_ACCEL 4864 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 4865 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 4866 #endif 4867 #ifdef CONFIG_SFC_MTD 4868 .mtd_probe = efx_ef10_mtd_probe, 4869 .mtd_rename = efx_mcdi_mtd_rename, 4870 .mtd_read = efx_mcdi_mtd_read, 4871 .mtd_erase = efx_mcdi_mtd_erase, 4872 .mtd_write = efx_mcdi_mtd_write, 4873 .mtd_sync = efx_mcdi_mtd_sync, 4874 #endif 4875 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4876 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4877 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4878 #ifdef CONFIG_SFC_SRIOV 4879 .sriov_configure = efx_ef10_sriov_configure, 4880 .sriov_init = efx_ef10_sriov_init, 4881 .sriov_fini = efx_ef10_sriov_fini, 4882 .sriov_wanted = efx_ef10_sriov_wanted, 4883 .sriov_reset = efx_ef10_sriov_reset, 4884 .sriov_flr = efx_ef10_sriov_flr, 4885 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4886 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4887 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4888 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4889 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4890 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4891 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4892 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4893 #endif 4894 .get_mac_address = efx_ef10_get_mac_address_pf, 4895 .set_mac_address = efx_ef10_set_mac_address, 4896 4897 .revision = EFX_REV_HUNT_A0, 4898 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4899 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4900 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4901 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4902 .can_rx_scatter = true, 4903 .always_rx_scatter = true, 4904 .max_interrupt_mode = EFX_INT_MODE_MSIX, 4905 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4906 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4907 NETIF_F_RXHASH | NETIF_F_NTUPLE), 4908 .mcdi_max_ver = 2, 4909 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 4910 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4911 1 << HWTSTAMP_FILTER_ALL, 4912 }; 4913