1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2012-2013 Solarflare Communications Inc. 5 */ 6 7 #include "net_driver.h" 8 #include "rx_common.h" 9 #include "ef10_regs.h" 10 #include "io.h" 11 #include "mcdi.h" 12 #include "mcdi_pcol.h" 13 #include "mcdi_port_common.h" 14 #include "mcdi_functions.h" 15 #include "nic.h" 16 #include "mcdi_filters.h" 17 #include "workarounds.h" 18 #include "selftest.h" 19 #include "ef10_sriov.h" 20 #include <linux/in.h> 21 #include <linux/jhash.h> 22 #include <linux/wait.h> 23 #include <linux/workqueue.h> 24 25 /* Hardware control for EF10 architecture including 'Huntington'. */ 26 27 #define EFX_EF10_DRVGEN_EV 7 28 enum { 29 EFX_EF10_TEST = 1, 30 EFX_EF10_REFILL, 31 }; 32 33 /* VLAN list entry */ 34 struct efx_ef10_vlan { 35 struct list_head list; 36 u16 vid; 37 }; 38 39 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading); 40 41 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 42 { 43 efx_dword_t reg; 44 45 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 46 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 47 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 48 } 49 50 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for 51 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O 52 * bar; PFs use BAR 0/1 for memory. 53 */ 54 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx) 55 { 56 switch (efx->pci_dev->device) { 57 case 0x0b03: /* SFC9250 PF */ 58 return 0; 59 default: 60 return 2; 61 } 62 } 63 64 /* All VFs use BAR 0/1 for memory */ 65 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx) 66 { 67 return 0; 68 } 69 70 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 71 { 72 int bar; 73 74 bar = efx->type->mem_bar(efx); 75 return resource_size(&efx->pci_dev->resource[bar]); 76 } 77 78 static bool efx_ef10_is_vf(struct efx_nic *efx) 79 { 80 return efx->type->is_vf; 81 } 82 83 #ifdef CONFIG_SFC_SRIOV 84 static int efx_ef10_get_vf_index(struct efx_nic *efx) 85 { 86 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 87 struct efx_ef10_nic_data *nic_data = efx->nic_data; 88 size_t outlen; 89 int rc; 90 91 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 92 sizeof(outbuf), &outlen); 93 if (rc) 94 return rc; 95 if (outlen < sizeof(outbuf)) 96 return -EIO; 97 98 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 99 return 0; 100 } 101 #endif 102 103 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 104 { 105 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN); 106 struct efx_ef10_nic_data *nic_data = efx->nic_data; 107 size_t outlen; 108 int rc; 109 110 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 111 112 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 113 outbuf, sizeof(outbuf), &outlen); 114 if (rc) 115 return rc; 116 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 117 netif_err(efx, drv, efx->net_dev, 118 "unable to read datapath firmware capabilities\n"); 119 return -EIO; 120 } 121 122 nic_data->datapath_caps = 123 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 124 125 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) { 126 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 127 GET_CAPABILITIES_V2_OUT_FLAGS2); 128 nic_data->piobuf_size = MCDI_WORD(outbuf, 129 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF); 130 } else { 131 nic_data->datapath_caps2 = 0; 132 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE; 133 } 134 135 /* record the DPCPU firmware IDs to determine VEB vswitching support. 136 */ 137 nic_data->rx_dpcpu_fw_id = 138 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 139 nic_data->tx_dpcpu_fw_id = 140 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 141 142 if (!(nic_data->datapath_caps & 143 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 144 netif_err(efx, probe, efx->net_dev, 145 "current firmware does not support an RX prefix\n"); 146 return -ENODEV; 147 } 148 149 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { 150 u8 vi_window_mode = MCDI_BYTE(outbuf, 151 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 152 153 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 154 if (rc) 155 return rc; 156 } else { 157 /* keep default VI stride */ 158 netif_dbg(efx, probe, efx->net_dev, 159 "firmware did not report VI window mode, assuming vi_stride = %u\n", 160 efx->vi_stride); 161 } 162 163 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 164 efx->num_mac_stats = MCDI_WORD(outbuf, 165 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 166 netif_dbg(efx, probe, efx->net_dev, 167 "firmware reports num_mac_stats = %u\n", 168 efx->num_mac_stats); 169 } else { 170 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */ 171 netif_dbg(efx, probe, efx->net_dev, 172 "firmware did not report num_mac_stats, assuming %u\n", 173 efx->num_mac_stats); 174 } 175 176 return 0; 177 } 178 179 static void efx_ef10_read_licensed_features(struct efx_nic *efx) 180 { 181 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN); 182 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN); 183 struct efx_ef10_nic_data *nic_data = efx->nic_data; 184 size_t outlen; 185 int rc; 186 187 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP, 188 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE); 189 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf), 190 outbuf, sizeof(outbuf), &outlen); 191 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN)) 192 return; 193 194 nic_data->licensed_features = MCDI_QWORD(outbuf, 195 LICENSING_V3_OUT_LICENSED_FEATURES); 196 } 197 198 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 199 { 200 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 201 int rc; 202 203 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 204 outbuf, sizeof(outbuf), NULL); 205 if (rc) 206 return rc; 207 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 208 return rc > 0 ? rc : -ERANGE; 209 } 210 211 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx) 212 { 213 struct efx_ef10_nic_data *nic_data = efx->nic_data; 214 unsigned int implemented; 215 unsigned int enabled; 216 int rc; 217 218 nic_data->workaround_35388 = false; 219 nic_data->workaround_61265 = false; 220 221 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 222 223 if (rc == -ENOSYS) { 224 /* Firmware without GET_WORKAROUNDS - not a problem. */ 225 rc = 0; 226 } else if (rc == 0) { 227 /* Bug61265 workaround is always enabled if implemented. */ 228 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265) 229 nic_data->workaround_61265 = true; 230 231 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 232 nic_data->workaround_35388 = true; 233 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 234 /* Workaround is implemented but not enabled. 235 * Try to enable it. 236 */ 237 rc = efx_mcdi_set_workaround(efx, 238 MC_CMD_WORKAROUND_BUG35388, 239 true, NULL); 240 if (rc == 0) 241 nic_data->workaround_35388 = true; 242 /* If we failed to set the workaround just carry on. */ 243 rc = 0; 244 } 245 } 246 247 netif_dbg(efx, probe, efx->net_dev, 248 "workaround for bug 35388 is %sabled\n", 249 nic_data->workaround_35388 ? "en" : "dis"); 250 netif_dbg(efx, probe, efx->net_dev, 251 "workaround for bug 61265 is %sabled\n", 252 nic_data->workaround_61265 ? "en" : "dis"); 253 254 return rc; 255 } 256 257 static void efx_ef10_process_timer_config(struct efx_nic *efx, 258 const efx_dword_t *data) 259 { 260 unsigned int max_count; 261 262 if (EFX_EF10_WORKAROUND_61265(efx)) { 263 efx->timer_quantum_ns = MCDI_DWORD(data, 264 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS); 265 efx->timer_max_ns = MCDI_DWORD(data, 266 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS); 267 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 268 efx->timer_quantum_ns = MCDI_DWORD(data, 269 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT); 270 max_count = MCDI_DWORD(data, 271 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT); 272 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 273 } else { 274 efx->timer_quantum_ns = MCDI_DWORD(data, 275 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT); 276 max_count = MCDI_DWORD(data, 277 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT); 278 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 279 } 280 281 netif_dbg(efx, probe, efx->net_dev, 282 "got timer properties from MC: quantum %u ns; max %u ns\n", 283 efx->timer_quantum_ns, efx->timer_max_ns); 284 } 285 286 static int efx_ef10_get_timer_config(struct efx_nic *efx) 287 { 288 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN); 289 int rc; 290 291 rc = efx_ef10_get_timer_workarounds(efx); 292 if (rc) 293 return rc; 294 295 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0, 296 outbuf, sizeof(outbuf), NULL); 297 298 if (rc == 0) { 299 efx_ef10_process_timer_config(efx, outbuf); 300 } else if (rc == -ENOSYS || rc == -EPERM) { 301 /* Not available - fall back to Huntington defaults. */ 302 unsigned int quantum; 303 304 rc = efx_ef10_get_sysclk_freq(efx); 305 if (rc < 0) 306 return rc; 307 308 quantum = 1536000 / rc; /* 1536 cycles */ 309 efx->timer_quantum_ns = quantum; 310 efx->timer_max_ns = efx->type->timer_period_max * quantum; 311 rc = 0; 312 } else { 313 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, 314 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN, 315 NULL, 0, rc); 316 } 317 318 return rc; 319 } 320 321 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 322 { 323 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 324 size_t outlen; 325 int rc; 326 327 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 328 329 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 330 outbuf, sizeof(outbuf), &outlen); 331 if (rc) 332 return rc; 333 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 334 return -EIO; 335 336 ether_addr_copy(mac_address, 337 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 338 return 0; 339 } 340 341 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 342 { 343 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 344 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 345 size_t outlen; 346 int num_addrs, rc; 347 348 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 349 EVB_PORT_ID_ASSIGNED); 350 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 351 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 352 353 if (rc) 354 return rc; 355 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 356 return -EIO; 357 358 num_addrs = MCDI_DWORD(outbuf, 359 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 360 361 WARN_ON(num_addrs != 1); 362 363 ether_addr_copy(mac_address, 364 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 365 366 return 0; 367 } 368 369 static ssize_t efx_ef10_show_link_control_flag(struct device *dev, 370 struct device_attribute *attr, 371 char *buf) 372 { 373 struct efx_nic *efx = dev_get_drvdata(dev); 374 375 return sprintf(buf, "%d\n", 376 ((efx->mcdi->fn_flags) & 377 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 378 ? 1 : 0); 379 } 380 381 static ssize_t efx_ef10_show_primary_flag(struct device *dev, 382 struct device_attribute *attr, 383 char *buf) 384 { 385 struct efx_nic *efx = dev_get_drvdata(dev); 386 387 return sprintf(buf, "%d\n", 388 ((efx->mcdi->fn_flags) & 389 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 390 ? 1 : 0); 391 } 392 393 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid) 394 { 395 struct efx_ef10_nic_data *nic_data = efx->nic_data; 396 struct efx_ef10_vlan *vlan; 397 398 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 399 400 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 401 if (vlan->vid == vid) 402 return vlan; 403 } 404 405 return NULL; 406 } 407 408 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid) 409 { 410 struct efx_ef10_nic_data *nic_data = efx->nic_data; 411 struct efx_ef10_vlan *vlan; 412 int rc; 413 414 mutex_lock(&nic_data->vlan_lock); 415 416 vlan = efx_ef10_find_vlan(efx, vid); 417 if (vlan) { 418 /* We add VID 0 on init. 8021q adds it on module init 419 * for all interfaces with VLAN filtring feature. 420 */ 421 if (vid == 0) 422 goto done_unlock; 423 netif_warn(efx, drv, efx->net_dev, 424 "VLAN %u already added\n", vid); 425 rc = -EALREADY; 426 goto fail_exist; 427 } 428 429 rc = -ENOMEM; 430 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 431 if (!vlan) 432 goto fail_alloc; 433 434 vlan->vid = vid; 435 436 list_add_tail(&vlan->list, &nic_data->vlan_list); 437 438 if (efx->filter_state) { 439 mutex_lock(&efx->mac_lock); 440 down_write(&efx->filter_sem); 441 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 442 up_write(&efx->filter_sem); 443 mutex_unlock(&efx->mac_lock); 444 if (rc) 445 goto fail_filter_add_vlan; 446 } 447 448 done_unlock: 449 mutex_unlock(&nic_data->vlan_lock); 450 return 0; 451 452 fail_filter_add_vlan: 453 list_del(&vlan->list); 454 kfree(vlan); 455 fail_alloc: 456 fail_exist: 457 mutex_unlock(&nic_data->vlan_lock); 458 return rc; 459 } 460 461 static void efx_ef10_del_vlan_internal(struct efx_nic *efx, 462 struct efx_ef10_vlan *vlan) 463 { 464 struct efx_ef10_nic_data *nic_data = efx->nic_data; 465 466 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 467 468 if (efx->filter_state) { 469 down_write(&efx->filter_sem); 470 efx_mcdi_filter_del_vlan(efx, vlan->vid); 471 up_write(&efx->filter_sem); 472 } 473 474 list_del(&vlan->list); 475 kfree(vlan); 476 } 477 478 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid) 479 { 480 struct efx_ef10_nic_data *nic_data = efx->nic_data; 481 struct efx_ef10_vlan *vlan; 482 int rc = 0; 483 484 /* 8021q removes VID 0 on module unload for all interfaces 485 * with VLAN filtering feature. We need to keep it to receive 486 * untagged traffic. 487 */ 488 if (vid == 0) 489 return 0; 490 491 mutex_lock(&nic_data->vlan_lock); 492 493 vlan = efx_ef10_find_vlan(efx, vid); 494 if (!vlan) { 495 netif_err(efx, drv, efx->net_dev, 496 "VLAN %u to be deleted not found\n", vid); 497 rc = -ENOENT; 498 } else { 499 efx_ef10_del_vlan_internal(efx, vlan); 500 } 501 502 mutex_unlock(&nic_data->vlan_lock); 503 504 return rc; 505 } 506 507 static void efx_ef10_cleanup_vlans(struct efx_nic *efx) 508 { 509 struct efx_ef10_nic_data *nic_data = efx->nic_data; 510 struct efx_ef10_vlan *vlan, *next_vlan; 511 512 mutex_lock(&nic_data->vlan_lock); 513 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list) 514 efx_ef10_del_vlan_internal(efx, vlan); 515 mutex_unlock(&nic_data->vlan_lock); 516 } 517 518 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag, 519 NULL); 520 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL); 521 522 static int efx_ef10_probe(struct efx_nic *efx) 523 { 524 struct efx_ef10_nic_data *nic_data; 525 int i, rc; 526 527 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 528 if (!nic_data) 529 return -ENOMEM; 530 efx->nic_data = nic_data; 531 532 /* we assume later that we can copy from this buffer in dwords */ 533 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 534 535 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 536 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 537 if (rc) 538 goto fail1; 539 540 /* Get the MC's warm boot count. In case it's rebooting right 541 * now, be prepared to retry. 542 */ 543 i = 0; 544 for (;;) { 545 rc = efx_ef10_get_warm_boot_count(efx); 546 if (rc >= 0) 547 break; 548 if (++i == 5) 549 goto fail2; 550 ssleep(1); 551 } 552 nic_data->warm_boot_count = rc; 553 554 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID; 555 556 efx->vport_id = EVB_PORT_ID_ASSIGNED; 557 558 /* In case we're recovering from a crash (kexec), we want to 559 * cancel any outstanding request by the previous user of this 560 * function. We send a special message using the least 561 * significant bits of the 'high' (doorbell) register. 562 */ 563 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 564 565 rc = efx_mcdi_init(efx); 566 if (rc) 567 goto fail2; 568 569 mutex_init(&nic_data->udp_tunnels_lock); 570 571 /* Reset (most) configuration for this function */ 572 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 573 if (rc) 574 goto fail3; 575 576 /* Enable event logging */ 577 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 578 if (rc) 579 goto fail3; 580 581 rc = device_create_file(&efx->pci_dev->dev, 582 &dev_attr_link_control_flag); 583 if (rc) 584 goto fail3; 585 586 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 587 if (rc) 588 goto fail4; 589 590 rc = efx_get_pf_index(efx, &nic_data->pf_index); 591 if (rc) 592 goto fail5; 593 594 rc = efx_ef10_init_datapath_caps(efx); 595 if (rc < 0) 596 goto fail5; 597 598 efx_ef10_read_licensed_features(efx); 599 600 /* We can have one VI for each vi_stride-byte region. 601 * However, until we use TX option descriptors we need two TX queues 602 * per channel. 603 */ 604 efx->max_channels = min_t(unsigned int, 605 EFX_MAX_CHANNELS, 606 efx_ef10_mem_map_size(efx) / 607 (efx->vi_stride * EFX_TXQ_TYPES)); 608 efx->max_tx_channels = efx->max_channels; 609 if (WARN_ON(efx->max_channels == 0)) { 610 rc = -EIO; 611 goto fail5; 612 } 613 614 efx->rx_packet_len_offset = 615 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 616 617 if (nic_data->datapath_caps & 618 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN)) 619 efx->net_dev->hw_features |= NETIF_F_RXFCS; 620 621 rc = efx_mcdi_port_get_number(efx); 622 if (rc < 0) 623 goto fail5; 624 efx->port_num = rc; 625 626 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 627 if (rc) 628 goto fail5; 629 630 rc = efx_ef10_get_timer_config(efx); 631 if (rc < 0) 632 goto fail5; 633 634 rc = efx_mcdi_mon_probe(efx); 635 if (rc && rc != -EPERM) 636 goto fail5; 637 638 efx_ptp_defer_probe_with_channel(efx); 639 640 #ifdef CONFIG_SFC_SRIOV 641 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 642 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 643 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 644 645 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 646 } else 647 #endif 648 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 649 650 INIT_LIST_HEAD(&nic_data->vlan_list); 651 mutex_init(&nic_data->vlan_lock); 652 653 /* Add unspecified VID to support VLAN filtering being disabled */ 654 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 655 if (rc) 656 goto fail_add_vid_unspec; 657 658 /* If VLAN filtering is enabled, we need VID 0 to get untagged 659 * traffic. It is added automatically if 8021q module is loaded, 660 * but we can't rely on it since module may be not loaded. 661 */ 662 rc = efx_ef10_add_vlan(efx, 0); 663 if (rc) 664 goto fail_add_vid_0; 665 666 return 0; 667 668 fail_add_vid_0: 669 efx_ef10_cleanup_vlans(efx); 670 fail_add_vid_unspec: 671 mutex_destroy(&nic_data->vlan_lock); 672 efx_ptp_remove(efx); 673 efx_mcdi_mon_remove(efx); 674 fail5: 675 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 676 fail4: 677 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 678 fail3: 679 efx_mcdi_detach(efx); 680 681 mutex_lock(&nic_data->udp_tunnels_lock); 682 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 683 (void)efx_ef10_set_udp_tnl_ports(efx, true); 684 mutex_unlock(&nic_data->udp_tunnels_lock); 685 mutex_destroy(&nic_data->udp_tunnels_lock); 686 687 efx_mcdi_fini(efx); 688 fail2: 689 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 690 fail1: 691 kfree(nic_data); 692 efx->nic_data = NULL; 693 return rc; 694 } 695 696 #ifdef EFX_USE_PIO 697 698 static void efx_ef10_free_piobufs(struct efx_nic *efx) 699 { 700 struct efx_ef10_nic_data *nic_data = efx->nic_data; 701 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 702 unsigned int i; 703 int rc; 704 705 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 706 707 for (i = 0; i < nic_data->n_piobufs; i++) { 708 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 709 nic_data->piobuf_handle[i]); 710 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 711 NULL, 0, NULL); 712 WARN_ON(rc); 713 } 714 715 nic_data->n_piobufs = 0; 716 } 717 718 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 719 { 720 struct efx_ef10_nic_data *nic_data = efx->nic_data; 721 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 722 unsigned int i; 723 size_t outlen; 724 int rc = 0; 725 726 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 727 728 for (i = 0; i < n; i++) { 729 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 730 outbuf, sizeof(outbuf), &outlen); 731 if (rc) { 732 /* Don't display the MC error if we didn't have space 733 * for a VF. 734 */ 735 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC)) 736 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF, 737 0, outbuf, outlen, rc); 738 break; 739 } 740 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 741 rc = -EIO; 742 break; 743 } 744 nic_data->piobuf_handle[i] = 745 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 746 netif_dbg(efx, probe, efx->net_dev, 747 "allocated PIO buffer %u handle %x\n", i, 748 nic_data->piobuf_handle[i]); 749 } 750 751 nic_data->n_piobufs = i; 752 if (rc) 753 efx_ef10_free_piobufs(efx); 754 return rc; 755 } 756 757 static int efx_ef10_link_piobufs(struct efx_nic *efx) 758 { 759 struct efx_ef10_nic_data *nic_data = efx->nic_data; 760 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN); 761 struct efx_channel *channel; 762 struct efx_tx_queue *tx_queue; 763 unsigned int offset, index; 764 int rc; 765 766 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 767 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 768 769 /* Link a buffer to each VI in the write-combining mapping */ 770 for (index = 0; index < nic_data->n_piobufs; ++index) { 771 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 772 nic_data->piobuf_handle[index]); 773 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 774 nic_data->pio_write_vi_base + index); 775 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 776 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 777 NULL, 0, NULL); 778 if (rc) { 779 netif_err(efx, drv, efx->net_dev, 780 "failed to link VI %u to PIO buffer %u (%d)\n", 781 nic_data->pio_write_vi_base + index, index, 782 rc); 783 goto fail; 784 } 785 netif_dbg(efx, probe, efx->net_dev, 786 "linked VI %u to PIO buffer %u\n", 787 nic_data->pio_write_vi_base + index, index); 788 } 789 790 /* Link a buffer to each TX queue */ 791 efx_for_each_channel(channel, efx) { 792 /* Extra channels, even those with TXQs (PTP), do not require 793 * PIO resources. 794 */ 795 if (!channel->type->want_pio || 796 channel->channel >= efx->xdp_channel_offset) 797 continue; 798 799 efx_for_each_channel_tx_queue(tx_queue, channel) { 800 /* We assign the PIO buffers to queues in 801 * reverse order to allow for the following 802 * special case. 803 */ 804 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 805 tx_queue->channel->channel - 1) * 806 efx_piobuf_size); 807 index = offset / nic_data->piobuf_size; 808 offset = offset % nic_data->piobuf_size; 809 810 /* When the host page size is 4K, the first 811 * host page in the WC mapping may be within 812 * the same VI page as the last TX queue. We 813 * can only link one buffer to each VI. 814 */ 815 if (tx_queue->queue == nic_data->pio_write_vi_base) { 816 BUG_ON(index != 0); 817 rc = 0; 818 } else { 819 MCDI_SET_DWORD(inbuf, 820 LINK_PIOBUF_IN_PIOBUF_HANDLE, 821 nic_data->piobuf_handle[index]); 822 MCDI_SET_DWORD(inbuf, 823 LINK_PIOBUF_IN_TXQ_INSTANCE, 824 tx_queue->queue); 825 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 826 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 827 NULL, 0, NULL); 828 } 829 830 if (rc) { 831 /* This is non-fatal; the TX path just 832 * won't use PIO for this queue 833 */ 834 netif_err(efx, drv, efx->net_dev, 835 "failed to link VI %u to PIO buffer %u (%d)\n", 836 tx_queue->queue, index, rc); 837 tx_queue->piobuf = NULL; 838 } else { 839 tx_queue->piobuf = 840 nic_data->pio_write_base + 841 index * efx->vi_stride + offset; 842 tx_queue->piobuf_offset = offset; 843 netif_dbg(efx, probe, efx->net_dev, 844 "linked VI %u to PIO buffer %u offset %x addr %p\n", 845 tx_queue->queue, index, 846 tx_queue->piobuf_offset, 847 tx_queue->piobuf); 848 } 849 } 850 } 851 852 return 0; 853 854 fail: 855 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same 856 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter. 857 */ 858 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN); 859 while (index--) { 860 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 861 nic_data->pio_write_vi_base + index); 862 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 863 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 864 NULL, 0, NULL); 865 } 866 return rc; 867 } 868 869 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 870 { 871 struct efx_channel *channel; 872 struct efx_tx_queue *tx_queue; 873 874 /* All our existing PIO buffers went away */ 875 efx_for_each_channel(channel, efx) 876 efx_for_each_channel_tx_queue(tx_queue, channel) 877 tx_queue->piobuf = NULL; 878 } 879 880 #else /* !EFX_USE_PIO */ 881 882 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 883 { 884 return n == 0 ? 0 : -ENOBUFS; 885 } 886 887 static int efx_ef10_link_piobufs(struct efx_nic *efx) 888 { 889 return 0; 890 } 891 892 static void efx_ef10_free_piobufs(struct efx_nic *efx) 893 { 894 } 895 896 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 897 { 898 } 899 900 #endif /* EFX_USE_PIO */ 901 902 static void efx_ef10_remove(struct efx_nic *efx) 903 { 904 struct efx_ef10_nic_data *nic_data = efx->nic_data; 905 int rc; 906 907 #ifdef CONFIG_SFC_SRIOV 908 struct efx_ef10_nic_data *nic_data_pf; 909 struct pci_dev *pci_dev_pf; 910 struct efx_nic *efx_pf; 911 struct ef10_vf *vf; 912 913 if (efx->pci_dev->is_virtfn) { 914 pci_dev_pf = efx->pci_dev->physfn; 915 if (pci_dev_pf) { 916 efx_pf = pci_get_drvdata(pci_dev_pf); 917 nic_data_pf = efx_pf->nic_data; 918 vf = nic_data_pf->vf + nic_data->vf_index; 919 vf->efx = NULL; 920 } else 921 netif_info(efx, drv, efx->net_dev, 922 "Could not get the PF id from VF\n"); 923 } 924 #endif 925 926 efx_ef10_cleanup_vlans(efx); 927 mutex_destroy(&nic_data->vlan_lock); 928 929 efx_ptp_remove(efx); 930 931 efx_mcdi_mon_remove(efx); 932 933 efx_mcdi_rx_free_indir_table(efx); 934 935 if (nic_data->wc_membase) 936 iounmap(nic_data->wc_membase); 937 938 rc = efx_mcdi_free_vis(efx); 939 WARN_ON(rc != 0); 940 941 if (!nic_data->must_restore_piobufs) 942 efx_ef10_free_piobufs(efx); 943 944 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 945 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 946 947 efx_mcdi_detach(efx); 948 949 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 950 mutex_lock(&nic_data->udp_tunnels_lock); 951 (void)efx_ef10_set_udp_tnl_ports(efx, true); 952 mutex_unlock(&nic_data->udp_tunnels_lock); 953 954 mutex_destroy(&nic_data->udp_tunnels_lock); 955 956 efx_mcdi_fini(efx); 957 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 958 kfree(nic_data); 959 } 960 961 static int efx_ef10_probe_pf(struct efx_nic *efx) 962 { 963 return efx_ef10_probe(efx); 964 } 965 966 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id, 967 u32 *port_flags, u32 *vadaptor_flags, 968 unsigned int *vlan_tags) 969 { 970 struct efx_ef10_nic_data *nic_data = efx->nic_data; 971 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN); 972 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN); 973 size_t outlen; 974 int rc; 975 976 if (nic_data->datapath_caps & 977 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) { 978 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID, 979 port_id); 980 981 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf), 982 outbuf, sizeof(outbuf), &outlen); 983 if (rc) 984 return rc; 985 986 if (outlen < sizeof(outbuf)) { 987 rc = -EIO; 988 return rc; 989 } 990 } 991 992 if (port_flags) 993 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS); 994 if (vadaptor_flags) 995 *vadaptor_flags = 996 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS); 997 if (vlan_tags) 998 *vlan_tags = 999 MCDI_DWORD(outbuf, 1000 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS); 1001 1002 return 0; 1003 } 1004 1005 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 1006 { 1007 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 1008 1009 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 1010 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 1011 NULL, 0, NULL); 1012 } 1013 1014 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 1015 { 1016 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 1017 1018 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 1019 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 1020 NULL, 0, NULL); 1021 } 1022 1023 int efx_ef10_vport_add_mac(struct efx_nic *efx, 1024 unsigned int port_id, u8 *mac) 1025 { 1026 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 1027 1028 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 1029 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 1030 1031 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 1032 sizeof(inbuf), NULL, 0, NULL); 1033 } 1034 1035 int efx_ef10_vport_del_mac(struct efx_nic *efx, 1036 unsigned int port_id, u8 *mac) 1037 { 1038 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 1039 1040 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 1041 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 1042 1043 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 1044 sizeof(inbuf), NULL, 0, NULL); 1045 } 1046 1047 #ifdef CONFIG_SFC_SRIOV 1048 static int efx_ef10_probe_vf(struct efx_nic *efx) 1049 { 1050 int rc; 1051 struct pci_dev *pci_dev_pf; 1052 1053 /* If the parent PF has no VF data structure, it doesn't know about this 1054 * VF so fail probe. The VF needs to be re-created. This can happen 1055 * if the PF driver is unloaded while the VF is assigned to a guest. 1056 */ 1057 pci_dev_pf = efx->pci_dev->physfn; 1058 if (pci_dev_pf) { 1059 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 1060 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 1061 1062 if (!nic_data_pf->vf) { 1063 netif_info(efx, drv, efx->net_dev, 1064 "The VF cannot link to its parent PF; " 1065 "please destroy and re-create the VF\n"); 1066 return -EBUSY; 1067 } 1068 } 1069 1070 rc = efx_ef10_probe(efx); 1071 if (rc) 1072 return rc; 1073 1074 rc = efx_ef10_get_vf_index(efx); 1075 if (rc) 1076 goto fail; 1077 1078 if (efx->pci_dev->is_virtfn) { 1079 if (efx->pci_dev->physfn) { 1080 struct efx_nic *efx_pf = 1081 pci_get_drvdata(efx->pci_dev->physfn); 1082 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 1083 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1084 1085 nic_data_p->vf[nic_data->vf_index].efx = efx; 1086 nic_data_p->vf[nic_data->vf_index].pci_dev = 1087 efx->pci_dev; 1088 } else 1089 netif_info(efx, drv, efx->net_dev, 1090 "Could not get the PF id from VF\n"); 1091 } 1092 1093 return 0; 1094 1095 fail: 1096 efx_ef10_remove(efx); 1097 return rc; 1098 } 1099 #else 1100 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 1101 { 1102 return 0; 1103 } 1104 #endif 1105 1106 static int efx_ef10_alloc_vis(struct efx_nic *efx, 1107 unsigned int min_vis, unsigned int max_vis) 1108 { 1109 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1110 1111 return efx_mcdi_alloc_vis(efx, min_vis, max_vis, &nic_data->vi_base, 1112 &nic_data->n_allocated_vis); 1113 } 1114 1115 /* Note that the failure path of this function does not free 1116 * resources, as this will be done by efx_ef10_remove(). 1117 */ 1118 static int efx_ef10_dimension_resources(struct efx_nic *efx) 1119 { 1120 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1121 unsigned int uc_mem_map_size, wc_mem_map_size; 1122 unsigned int min_vis = max(EFX_TXQ_TYPES, 1123 efx_separate_tx_channels ? 2 : 1); 1124 unsigned int channel_vis, pio_write_vi_base, max_vis; 1125 void __iomem *membase; 1126 int rc; 1127 1128 channel_vis = max(efx->n_channels, 1129 ((efx->n_tx_channels + efx->n_extra_tx_channels) * 1130 EFX_TXQ_TYPES) + 1131 efx->n_xdp_channels * efx->xdp_tx_per_channel); 1132 1133 #ifdef EFX_USE_PIO 1134 /* Try to allocate PIO buffers if wanted and if the full 1135 * number of PIO buffers would be sufficient to allocate one 1136 * copy-buffer per TX channel. Failure is non-fatal, as there 1137 * are only a small number of PIO buffers shared between all 1138 * functions of the controller. 1139 */ 1140 if (efx_piobuf_size != 0 && 1141 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 1142 efx->n_tx_channels) { 1143 unsigned int n_piobufs = 1144 DIV_ROUND_UP(efx->n_tx_channels, 1145 nic_data->piobuf_size / efx_piobuf_size); 1146 1147 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 1148 if (rc == -ENOSPC) 1149 netif_dbg(efx, probe, efx->net_dev, 1150 "out of PIO buffers; cannot allocate more\n"); 1151 else if (rc == -EPERM) 1152 netif_dbg(efx, probe, efx->net_dev, 1153 "not permitted to allocate PIO buffers\n"); 1154 else if (rc) 1155 netif_err(efx, probe, efx->net_dev, 1156 "failed to allocate PIO buffers (%d)\n", rc); 1157 else 1158 netif_dbg(efx, probe, efx->net_dev, 1159 "allocated %u PIO buffers\n", n_piobufs); 1160 } 1161 #else 1162 nic_data->n_piobufs = 0; 1163 #endif 1164 1165 /* PIO buffers should be mapped with write-combining enabled, 1166 * and we want to make single UC and WC mappings rather than 1167 * several of each (in fact that's the only option if host 1168 * page size is >4K). So we may allocate some extra VIs just 1169 * for writing PIO buffers through. 1170 * 1171 * The UC mapping contains (channel_vis - 1) complete VIs and the 1172 * first 4K of the next VI. Then the WC mapping begins with 1173 * the remainder of this last VI. 1174 */ 1175 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride + 1176 ER_DZ_TX_PIOBUF); 1177 if (nic_data->n_piobufs) { 1178 /* pio_write_vi_base rounds down to give the number of complete 1179 * VIs inside the UC mapping. 1180 */ 1181 pio_write_vi_base = uc_mem_map_size / efx->vi_stride; 1182 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 1183 nic_data->n_piobufs) * 1184 efx->vi_stride) - 1185 uc_mem_map_size); 1186 max_vis = pio_write_vi_base + nic_data->n_piobufs; 1187 } else { 1188 pio_write_vi_base = 0; 1189 wc_mem_map_size = 0; 1190 max_vis = channel_vis; 1191 } 1192 1193 /* In case the last attached driver failed to free VIs, do it now */ 1194 rc = efx_mcdi_free_vis(efx); 1195 if (rc != 0) 1196 return rc; 1197 1198 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 1199 if (rc != 0) 1200 return rc; 1201 1202 if (nic_data->n_allocated_vis < channel_vis) { 1203 netif_info(efx, drv, efx->net_dev, 1204 "Could not allocate enough VIs to satisfy RSS" 1205 " requirements. Performance may not be optimal.\n"); 1206 /* We didn't get the VIs to populate our channels. 1207 * We could keep what we got but then we'd have more 1208 * interrupts than we need. 1209 * Instead calculate new max_channels and restart 1210 */ 1211 efx->max_channels = nic_data->n_allocated_vis; 1212 efx->max_tx_channels = 1213 nic_data->n_allocated_vis / EFX_TXQ_TYPES; 1214 1215 efx_mcdi_free_vis(efx); 1216 return -EAGAIN; 1217 } 1218 1219 /* If we didn't get enough VIs to map all the PIO buffers, free the 1220 * PIO buffers 1221 */ 1222 if (nic_data->n_piobufs && 1223 nic_data->n_allocated_vis < 1224 pio_write_vi_base + nic_data->n_piobufs) { 1225 netif_dbg(efx, probe, efx->net_dev, 1226 "%u VIs are not sufficient to map %u PIO buffers\n", 1227 nic_data->n_allocated_vis, nic_data->n_piobufs); 1228 efx_ef10_free_piobufs(efx); 1229 } 1230 1231 /* Shrink the original UC mapping of the memory BAR */ 1232 membase = ioremap(efx->membase_phys, uc_mem_map_size); 1233 if (!membase) { 1234 netif_err(efx, probe, efx->net_dev, 1235 "could not shrink memory BAR to %x\n", 1236 uc_mem_map_size); 1237 return -ENOMEM; 1238 } 1239 iounmap(efx->membase); 1240 efx->membase = membase; 1241 1242 /* Set up the WC mapping if needed */ 1243 if (wc_mem_map_size) { 1244 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 1245 uc_mem_map_size, 1246 wc_mem_map_size); 1247 if (!nic_data->wc_membase) { 1248 netif_err(efx, probe, efx->net_dev, 1249 "could not allocate WC mapping of size %x\n", 1250 wc_mem_map_size); 1251 return -ENOMEM; 1252 } 1253 nic_data->pio_write_vi_base = pio_write_vi_base; 1254 nic_data->pio_write_base = 1255 nic_data->wc_membase + 1256 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF - 1257 uc_mem_map_size); 1258 1259 rc = efx_ef10_link_piobufs(efx); 1260 if (rc) 1261 efx_ef10_free_piobufs(efx); 1262 } 1263 1264 netif_dbg(efx, probe, efx->net_dev, 1265 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 1266 &efx->membase_phys, efx->membase, uc_mem_map_size, 1267 nic_data->wc_membase, wc_mem_map_size); 1268 1269 return 0; 1270 } 1271 1272 static int efx_ef10_init_nic(struct efx_nic *efx) 1273 { 1274 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1275 int rc; 1276 1277 if (nic_data->must_check_datapath_caps) { 1278 rc = efx_ef10_init_datapath_caps(efx); 1279 if (rc) 1280 return rc; 1281 nic_data->must_check_datapath_caps = false; 1282 } 1283 1284 if (efx->must_realloc_vis) { 1285 /* We cannot let the number of VIs change now */ 1286 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 1287 nic_data->n_allocated_vis); 1288 if (rc) 1289 return rc; 1290 efx->must_realloc_vis = false; 1291 } 1292 1293 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 1294 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 1295 if (rc == 0) { 1296 rc = efx_ef10_link_piobufs(efx); 1297 if (rc) 1298 efx_ef10_free_piobufs(efx); 1299 } 1300 1301 /* Log an error on failure, but this is non-fatal. 1302 * Permission errors are less important - we've presumably 1303 * had the PIO buffer licence removed. 1304 */ 1305 if (rc == -EPERM) 1306 netif_dbg(efx, drv, efx->net_dev, 1307 "not permitted to restore PIO buffers\n"); 1308 else if (rc) 1309 netif_err(efx, drv, efx->net_dev, 1310 "failed to restore PIO buffers (%d)\n", rc); 1311 nic_data->must_restore_piobufs = false; 1312 } 1313 1314 /* don't fail init if RSS setup doesn't work */ 1315 rc = efx->type->rx_push_rss_config(efx, false, 1316 efx->rss_context.rx_indir_table, NULL); 1317 1318 return 0; 1319 } 1320 1321 static void efx_ef10_table_reset_mc_allocations(struct efx_nic *efx) 1322 { 1323 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1324 #ifdef CONFIG_SFC_SRIOV 1325 unsigned int i; 1326 #endif 1327 1328 /* All our allocations have been reset */ 1329 efx->must_realloc_vis = true; 1330 efx_mcdi_filter_table_reset_mc_allocations(efx); 1331 nic_data->must_restore_piobufs = true; 1332 efx_ef10_forget_old_piobufs(efx); 1333 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID; 1334 1335 /* Driver-created vswitches and vports must be re-created */ 1336 nic_data->must_probe_vswitching = true; 1337 efx->vport_id = EVB_PORT_ID_ASSIGNED; 1338 #ifdef CONFIG_SFC_SRIOV 1339 if (nic_data->vf) 1340 for (i = 0; i < efx->vf_count; i++) 1341 nic_data->vf[i].vport_id = 0; 1342 #endif 1343 } 1344 1345 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1346 { 1347 if (reason == RESET_TYPE_MC_FAILURE) 1348 return RESET_TYPE_DATAPATH; 1349 1350 return efx_mcdi_map_reset_reason(reason); 1351 } 1352 1353 static int efx_ef10_map_reset_flags(u32 *flags) 1354 { 1355 enum { 1356 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1357 ETH_RESET_SHARED_SHIFT), 1358 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1359 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1360 ETH_RESET_PHY | ETH_RESET_MGMT) << 1361 ETH_RESET_SHARED_SHIFT) 1362 }; 1363 1364 /* We assume for now that our PCI function is permitted to 1365 * reset everything. 1366 */ 1367 1368 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1369 *flags &= ~EF10_RESET_MC; 1370 return RESET_TYPE_WORLD; 1371 } 1372 1373 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1374 *flags &= ~EF10_RESET_PORT; 1375 return RESET_TYPE_ALL; 1376 } 1377 1378 /* no invisible reset implemented */ 1379 1380 return -EINVAL; 1381 } 1382 1383 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1384 { 1385 int rc = efx_mcdi_reset(efx, reset_type); 1386 1387 /* Unprivileged functions return -EPERM, but need to return success 1388 * here so that the datapath is brought back up. 1389 */ 1390 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1391 rc = 0; 1392 1393 /* If it was a port reset, trigger reallocation of MC resources. 1394 * Note that on an MC reset nothing needs to be done now because we'll 1395 * detect the MC reset later and handle it then. 1396 * For an FLR, we never get an MC reset event, but the MC has reset all 1397 * resources assigned to us, so we have to trigger reallocation now. 1398 */ 1399 if ((reset_type == RESET_TYPE_ALL || 1400 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1401 efx_ef10_table_reset_mc_allocations(efx); 1402 return rc; 1403 } 1404 1405 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1406 [EF10_STAT_ ## ext_name] = \ 1407 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1408 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1409 [EF10_STAT_ ## int_name] = \ 1410 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1411 #define EF10_OTHER_STAT(ext_name) \ 1412 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1413 #define GENERIC_SW_STAT(ext_name) \ 1414 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1415 1416 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1417 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1418 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1419 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1420 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1421 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1422 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1423 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1424 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1425 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1426 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1427 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1428 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1429 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1430 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1431 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1432 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1433 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1434 EF10_OTHER_STAT(port_rx_good_bytes), 1435 EF10_OTHER_STAT(port_rx_bad_bytes), 1436 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1437 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1438 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1439 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1440 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1441 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1442 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1443 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1444 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1445 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1446 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1447 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1448 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1449 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1450 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1451 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1452 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1453 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1454 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1455 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1456 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1457 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1458 GENERIC_SW_STAT(rx_nodesc_trunc), 1459 GENERIC_SW_STAT(rx_noskb_drops), 1460 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1461 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1462 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1463 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1464 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1465 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1466 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1467 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1468 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1469 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1470 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1471 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1472 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1473 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1474 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1475 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1476 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1477 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1478 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1479 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1480 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1481 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1482 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1483 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1484 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1485 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1486 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1487 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1488 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1489 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1490 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS), 1491 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS), 1492 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0), 1493 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1), 1494 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2), 1495 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3), 1496 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK), 1497 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS), 1498 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL), 1499 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL), 1500 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL), 1501 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL), 1502 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL), 1503 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL), 1504 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL), 1505 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK), 1506 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK), 1507 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK), 1508 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS), 1509 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK), 1510 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON), 1511 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE), 1512 }; 1513 1514 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1515 (1ULL << EF10_STAT_port_tx_packets) | \ 1516 (1ULL << EF10_STAT_port_tx_pause) | \ 1517 (1ULL << EF10_STAT_port_tx_unicast) | \ 1518 (1ULL << EF10_STAT_port_tx_multicast) | \ 1519 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1520 (1ULL << EF10_STAT_port_rx_bytes) | \ 1521 (1ULL << \ 1522 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1523 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1524 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1525 (1ULL << EF10_STAT_port_rx_packets) | \ 1526 (1ULL << EF10_STAT_port_rx_good) | \ 1527 (1ULL << EF10_STAT_port_rx_bad) | \ 1528 (1ULL << EF10_STAT_port_rx_pause) | \ 1529 (1ULL << EF10_STAT_port_rx_control) | \ 1530 (1ULL << EF10_STAT_port_rx_unicast) | \ 1531 (1ULL << EF10_STAT_port_rx_multicast) | \ 1532 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1533 (1ULL << EF10_STAT_port_rx_lt64) | \ 1534 (1ULL << EF10_STAT_port_rx_64) | \ 1535 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1536 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1537 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1538 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1539 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1540 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1541 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1542 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1543 (1ULL << EF10_STAT_port_rx_overflow) | \ 1544 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1545 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1546 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1547 1548 /* On 7000 series NICs, these statistics are only provided by the 10G MAC. 1549 * For a 10G/40G switchable port we do not expose these because they might 1550 * not include all the packets they should. 1551 * On 8000 series NICs these statistics are always provided. 1552 */ 1553 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1554 (1ULL << EF10_STAT_port_tx_lt64) | \ 1555 (1ULL << EF10_STAT_port_tx_64) | \ 1556 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1557 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1558 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1559 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1560 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1561 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1562 1563 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1564 * switchable port we do expose these because the errors will otherwise 1565 * be silent. 1566 */ 1567 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1568 (1ULL << EF10_STAT_port_rx_length_error)) 1569 1570 /* These statistics are only provided if the firmware supports the 1571 * capability PM_AND_RXDP_COUNTERS. 1572 */ 1573 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1574 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1575 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1576 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1577 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1578 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1579 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1580 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1581 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1582 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1583 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1584 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1585 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1586 1587 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2, 1588 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in 1589 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1590 * These bits are in the second u64 of the raw mask. 1591 */ 1592 #define EF10_FEC_STAT_MASK ( \ 1593 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \ 1594 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \ 1595 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \ 1596 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \ 1597 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \ 1598 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64))) 1599 1600 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3, 1601 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in 1602 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1603 * These bits are in the second u64 of the raw mask. 1604 */ 1605 #define EF10_CTPIO_STAT_MASK ( \ 1606 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \ 1607 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \ 1608 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \ 1609 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \ 1610 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \ 1611 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \ 1612 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \ 1613 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \ 1614 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \ 1615 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \ 1616 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \ 1617 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \ 1618 (1ULL << (EF10_STAT_ctpio_success - 64)) | \ 1619 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \ 1620 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \ 1621 (1ULL << (EF10_STAT_ctpio_erase - 64))) 1622 1623 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1624 { 1625 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1626 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1627 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1628 1629 if (!(efx->mcdi->fn_flags & 1630 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1631 return 0; 1632 1633 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) { 1634 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1635 /* 8000 series have everything even at 40G */ 1636 if (nic_data->datapath_caps2 & 1637 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN)) 1638 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1639 } else { 1640 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1641 } 1642 1643 if (nic_data->datapath_caps & 1644 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1645 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1646 1647 return raw_mask; 1648 } 1649 1650 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1651 { 1652 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1653 u64 raw_mask[2]; 1654 1655 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1656 1657 /* Only show vadaptor stats when EVB capability is present */ 1658 if (nic_data->datapath_caps & 1659 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1660 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1661 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1; 1662 } else { 1663 raw_mask[1] = 0; 1664 } 1665 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */ 1666 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2) 1667 raw_mask[1] |= EF10_FEC_STAT_MASK; 1668 1669 /* CTPIO stats appear in V3. Only show them on devices that actually 1670 * support CTPIO. Although this driver doesn't use CTPIO others might, 1671 * and we may be reporting the stats for the underlying port. 1672 */ 1673 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 && 1674 (nic_data->datapath_caps2 & 1675 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN))) 1676 raw_mask[1] |= EF10_CTPIO_STAT_MASK; 1677 1678 #if BITS_PER_LONG == 64 1679 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2); 1680 mask[0] = raw_mask[0]; 1681 mask[1] = raw_mask[1]; 1682 #else 1683 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3); 1684 mask[0] = raw_mask[0] & 0xffffffff; 1685 mask[1] = raw_mask[0] >> 32; 1686 mask[2] = raw_mask[1] & 0xffffffff; 1687 #endif 1688 } 1689 1690 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1691 { 1692 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1693 1694 efx_ef10_get_stat_mask(efx, mask); 1695 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1696 mask, names); 1697 } 1698 1699 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1700 struct rtnl_link_stats64 *core_stats) 1701 { 1702 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1703 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1704 u64 *stats = nic_data->stats; 1705 size_t stats_count = 0, index; 1706 1707 efx_ef10_get_stat_mask(efx, mask); 1708 1709 if (full_stats) { 1710 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1711 if (efx_ef10_stat_desc[index].name) { 1712 *full_stats++ = stats[index]; 1713 ++stats_count; 1714 } 1715 } 1716 } 1717 1718 if (!core_stats) 1719 return stats_count; 1720 1721 if (nic_data->datapath_caps & 1722 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1723 /* Use vadaptor stats. */ 1724 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1725 stats[EF10_STAT_rx_multicast] + 1726 stats[EF10_STAT_rx_broadcast]; 1727 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1728 stats[EF10_STAT_tx_multicast] + 1729 stats[EF10_STAT_tx_broadcast]; 1730 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1731 stats[EF10_STAT_rx_multicast_bytes] + 1732 stats[EF10_STAT_rx_broadcast_bytes]; 1733 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1734 stats[EF10_STAT_tx_multicast_bytes] + 1735 stats[EF10_STAT_tx_broadcast_bytes]; 1736 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1737 stats[GENERIC_STAT_rx_noskb_drops]; 1738 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1739 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1740 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1741 core_stats->rx_errors = core_stats->rx_crc_errors; 1742 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1743 } else { 1744 /* Use port stats. */ 1745 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1746 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1747 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1748 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1749 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1750 stats[GENERIC_STAT_rx_nodesc_trunc] + 1751 stats[GENERIC_STAT_rx_noskb_drops]; 1752 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1753 core_stats->rx_length_errors = 1754 stats[EF10_STAT_port_rx_gtjumbo] + 1755 stats[EF10_STAT_port_rx_length_error]; 1756 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1757 core_stats->rx_frame_errors = 1758 stats[EF10_STAT_port_rx_align_error]; 1759 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1760 core_stats->rx_errors = (core_stats->rx_length_errors + 1761 core_stats->rx_crc_errors + 1762 core_stats->rx_frame_errors); 1763 } 1764 1765 return stats_count; 1766 } 1767 1768 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx) 1769 { 1770 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1771 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1772 __le64 generation_start, generation_end; 1773 u64 *stats = nic_data->stats; 1774 __le64 *dma_stats; 1775 1776 efx_ef10_get_stat_mask(efx, mask); 1777 1778 dma_stats = efx->stats_buffer.addr; 1779 1780 generation_end = dma_stats[efx->num_mac_stats - 1]; 1781 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 1782 return 0; 1783 rmb(); 1784 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1785 stats, efx->stats_buffer.addr, false); 1786 rmb(); 1787 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1788 if (generation_end != generation_start) 1789 return -EAGAIN; 1790 1791 /* Update derived statistics */ 1792 efx_nic_fix_nodesc_drop_stat(efx, 1793 &stats[EF10_STAT_port_rx_nodesc_drops]); 1794 stats[EF10_STAT_port_rx_good_bytes] = 1795 stats[EF10_STAT_port_rx_bytes] - 1796 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1797 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1798 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1799 efx_update_sw_stats(efx, stats); 1800 return 0; 1801 } 1802 1803 1804 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1805 struct rtnl_link_stats64 *core_stats) 1806 { 1807 int retry; 1808 1809 /* If we're unlucky enough to read statistics during the DMA, wait 1810 * up to 10ms for it to finish (typically takes <500us) 1811 */ 1812 for (retry = 0; retry < 100; ++retry) { 1813 if (efx_ef10_try_update_nic_stats_pf(efx) == 0) 1814 break; 1815 udelay(100); 1816 } 1817 1818 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1819 } 1820 1821 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1822 __must_hold(&efx->stats_lock) 1823 { 1824 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1825 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1826 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1827 __le64 generation_start, generation_end; 1828 u64 *stats = nic_data->stats; 1829 u32 dma_len = efx->num_mac_stats * sizeof(u64); 1830 struct efx_buffer stats_buf; 1831 __le64 *dma_stats; 1832 int rc; 1833 1834 spin_unlock_bh(&efx->stats_lock); 1835 1836 if (in_interrupt()) { 1837 /* If in atomic context, cannot update stats. Just update the 1838 * software stats and return so the caller can continue. 1839 */ 1840 spin_lock_bh(&efx->stats_lock); 1841 efx_update_sw_stats(efx, stats); 1842 return 0; 1843 } 1844 1845 efx_ef10_get_stat_mask(efx, mask); 1846 1847 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC); 1848 if (rc) { 1849 spin_lock_bh(&efx->stats_lock); 1850 return rc; 1851 } 1852 1853 dma_stats = stats_buf.addr; 1854 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID; 1855 1856 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1857 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1858 MAC_STATS_IN_DMA, 1); 1859 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1860 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1861 1862 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1863 NULL, 0, NULL); 1864 spin_lock_bh(&efx->stats_lock); 1865 if (rc) { 1866 /* Expect ENOENT if DMA queues have not been set up */ 1867 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1868 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1869 sizeof(inbuf), NULL, 0, rc); 1870 goto out; 1871 } 1872 1873 generation_end = dma_stats[efx->num_mac_stats - 1]; 1874 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1875 WARN_ON_ONCE(1); 1876 goto out; 1877 } 1878 rmb(); 1879 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1880 stats, stats_buf.addr, false); 1881 rmb(); 1882 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1883 if (generation_end != generation_start) { 1884 rc = -EAGAIN; 1885 goto out; 1886 } 1887 1888 efx_update_sw_stats(efx, stats); 1889 out: 1890 efx_nic_free_buffer(efx, &stats_buf); 1891 return rc; 1892 } 1893 1894 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1895 struct rtnl_link_stats64 *core_stats) 1896 { 1897 if (efx_ef10_try_update_nic_stats_vf(efx)) 1898 return 0; 1899 1900 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1901 } 1902 1903 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1904 { 1905 struct efx_nic *efx = channel->efx; 1906 unsigned int mode, usecs; 1907 efx_dword_t timer_cmd; 1908 1909 if (channel->irq_moderation_us) { 1910 mode = 3; 1911 usecs = channel->irq_moderation_us; 1912 } else { 1913 mode = 0; 1914 usecs = 0; 1915 } 1916 1917 if (EFX_EF10_WORKAROUND_61265(efx)) { 1918 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN); 1919 unsigned int ns = usecs * 1000; 1920 1921 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE, 1922 channel->channel); 1923 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns); 1924 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns); 1925 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode); 1926 1927 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR, 1928 inbuf, sizeof(inbuf), 0, NULL, 0); 1929 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 1930 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1931 1932 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1933 EFE_DD_EVQ_IND_TIMER_FLAGS, 1934 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1935 ERF_DD_EVQ_IND_TIMER_VAL, ticks); 1936 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1937 channel->channel); 1938 } else { 1939 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1940 1941 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1942 ERF_DZ_TC_TIMER_VAL, ticks, 1943 ERF_FZ_TC_TMR_REL_VAL, ticks); 1944 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1945 channel->channel); 1946 } 1947 } 1948 1949 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 1950 struct ethtool_wolinfo *wol) {} 1951 1952 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 1953 { 1954 return -EOPNOTSUPP; 1955 } 1956 1957 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1958 { 1959 wol->supported = 0; 1960 wol->wolopts = 0; 1961 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1962 } 1963 1964 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 1965 { 1966 if (type != 0) 1967 return -EINVAL; 1968 return 0; 1969 } 1970 1971 static void efx_ef10_mcdi_request(struct efx_nic *efx, 1972 const efx_dword_t *hdr, size_t hdr_len, 1973 const efx_dword_t *sdu, size_t sdu_len) 1974 { 1975 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1976 u8 *pdu = nic_data->mcdi_buf.addr; 1977 1978 memcpy(pdu, hdr, hdr_len); 1979 memcpy(pdu + hdr_len, sdu, sdu_len); 1980 wmb(); 1981 1982 /* The hardware provides 'low' and 'high' (doorbell) registers 1983 * for passing the 64-bit address of an MCDI request to 1984 * firmware. However the dwords are swapped by firmware. The 1985 * least significant bits of the doorbell are then 0 for all 1986 * MCDI requests due to alignment. 1987 */ 1988 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 1989 ER_DZ_MC_DB_LWRD); 1990 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 1991 ER_DZ_MC_DB_HWRD); 1992 } 1993 1994 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 1995 { 1996 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1997 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 1998 1999 rmb(); 2000 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 2001 } 2002 2003 static void 2004 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 2005 size_t offset, size_t outlen) 2006 { 2007 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2008 const u8 *pdu = nic_data->mcdi_buf.addr; 2009 2010 memcpy(outbuf, pdu + offset, outlen); 2011 } 2012 2013 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 2014 { 2015 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2016 2017 /* All our allocations have been reset */ 2018 efx_ef10_table_reset_mc_allocations(efx); 2019 2020 /* The datapath firmware might have been changed */ 2021 nic_data->must_check_datapath_caps = true; 2022 2023 /* MAC statistics have been cleared on the NIC; clear the local 2024 * statistic that we update with efx_update_diff_stat(). 2025 */ 2026 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 2027 } 2028 2029 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 2030 { 2031 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2032 int rc; 2033 2034 rc = efx_ef10_get_warm_boot_count(efx); 2035 if (rc < 0) { 2036 /* The firmware is presumably in the process of 2037 * rebooting. However, we are supposed to report each 2038 * reboot just once, so we must only do that once we 2039 * can read and store the updated warm boot count. 2040 */ 2041 return 0; 2042 } 2043 2044 if (rc == nic_data->warm_boot_count) 2045 return 0; 2046 2047 nic_data->warm_boot_count = rc; 2048 efx_ef10_mcdi_reboot_detected(efx); 2049 2050 return -EIO; 2051 } 2052 2053 /* Handle an MSI interrupt 2054 * 2055 * Handle an MSI hardware interrupt. This routine schedules event 2056 * queue processing. No interrupt acknowledgement cycle is necessary. 2057 * Also, we never need to check that the interrupt is for us, since 2058 * MSI interrupts cannot be shared. 2059 */ 2060 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 2061 { 2062 struct efx_msi_context *context = dev_id; 2063 struct efx_nic *efx = context->efx; 2064 2065 netif_vdbg(efx, intr, efx->net_dev, 2066 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 2067 2068 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 2069 /* Note test interrupts */ 2070 if (context->index == efx->irq_level) 2071 efx->last_irq_cpu = raw_smp_processor_id(); 2072 2073 /* Schedule processing of the channel */ 2074 efx_schedule_channel_irq(efx->channel[context->index]); 2075 } 2076 2077 return IRQ_HANDLED; 2078 } 2079 2080 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 2081 { 2082 struct efx_nic *efx = dev_id; 2083 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled); 2084 struct efx_channel *channel; 2085 efx_dword_t reg; 2086 u32 queues; 2087 2088 /* Read the ISR which also ACKs the interrupts */ 2089 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 2090 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 2091 2092 if (queues == 0) 2093 return IRQ_NONE; 2094 2095 if (likely(soft_enabled)) { 2096 /* Note test interrupts */ 2097 if (queues & (1U << efx->irq_level)) 2098 efx->last_irq_cpu = raw_smp_processor_id(); 2099 2100 efx_for_each_channel(channel, efx) { 2101 if (queues & 1) 2102 efx_schedule_channel_irq(channel); 2103 queues >>= 1; 2104 } 2105 } 2106 2107 netif_vdbg(efx, intr, efx->net_dev, 2108 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 2109 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 2110 2111 return IRQ_HANDLED; 2112 } 2113 2114 static int efx_ef10_irq_test_generate(struct efx_nic *efx) 2115 { 2116 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 2117 2118 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true, 2119 NULL) == 0) 2120 return -ENOTSUPP; 2121 2122 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 2123 2124 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 2125 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 2126 inbuf, sizeof(inbuf), NULL, 0, NULL); 2127 } 2128 2129 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 2130 { 2131 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 2132 (tx_queue->ptr_mask + 1) * 2133 sizeof(efx_qword_t), 2134 GFP_KERNEL); 2135 } 2136 2137 /* This writes to the TX_DESC_WPTR and also pushes data */ 2138 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 2139 const efx_qword_t *txd) 2140 { 2141 unsigned int write_ptr; 2142 efx_oword_t reg; 2143 2144 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2145 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 2146 reg.qword[0] = *txd; 2147 efx_writeo_page(tx_queue->efx, ®, 2148 ER_DZ_TX_DESC_UPD, tx_queue->queue); 2149 } 2150 2151 /* Add Firmware-Assisted TSO v2 option descriptors to a queue. 2152 */ 2153 static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, 2154 struct sk_buff *skb, 2155 bool *data_mapped) 2156 { 2157 struct efx_tx_buffer *buffer; 2158 struct tcphdr *tcp; 2159 struct iphdr *ip; 2160 2161 u16 ipv4_id; 2162 u32 seqnum; 2163 u32 mss; 2164 2165 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2); 2166 2167 mss = skb_shinfo(skb)->gso_size; 2168 2169 if (unlikely(mss < 4)) { 2170 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss); 2171 return -EINVAL; 2172 } 2173 2174 ip = ip_hdr(skb); 2175 if (ip->version == 4) { 2176 /* Modify IPv4 header if needed. */ 2177 ip->tot_len = 0; 2178 ip->check = 0; 2179 ipv4_id = ntohs(ip->id); 2180 } else { 2181 /* Modify IPv6 header if needed. */ 2182 struct ipv6hdr *ipv6 = ipv6_hdr(skb); 2183 2184 ipv6->payload_len = 0; 2185 ipv4_id = 0; 2186 } 2187 2188 tcp = tcp_hdr(skb); 2189 seqnum = ntohl(tcp->seq); 2190 2191 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2192 2193 buffer->flags = EFX_TX_BUF_OPTION; 2194 buffer->len = 0; 2195 buffer->unmap_len = 0; 2196 EFX_POPULATE_QWORD_5(buffer->option, 2197 ESF_DZ_TX_DESC_IS_OPT, 1, 2198 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2199 ESF_DZ_TX_TSO_OPTION_TYPE, 2200 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A, 2201 ESF_DZ_TX_TSO_IP_ID, ipv4_id, 2202 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum 2203 ); 2204 ++tx_queue->insert_count; 2205 2206 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2207 2208 buffer->flags = EFX_TX_BUF_OPTION; 2209 buffer->len = 0; 2210 buffer->unmap_len = 0; 2211 EFX_POPULATE_QWORD_4(buffer->option, 2212 ESF_DZ_TX_DESC_IS_OPT, 1, 2213 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2214 ESF_DZ_TX_TSO_OPTION_TYPE, 2215 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B, 2216 ESF_DZ_TX_TSO_TCP_MSS, mss 2217 ); 2218 ++tx_queue->insert_count; 2219 2220 return 0; 2221 } 2222 2223 static u32 efx_ef10_tso_versions(struct efx_nic *efx) 2224 { 2225 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2226 u32 tso_versions = 0; 2227 2228 if (nic_data->datapath_caps & 2229 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) 2230 tso_versions |= BIT(1); 2231 if (nic_data->datapath_caps2 & 2232 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) 2233 tso_versions |= BIT(2); 2234 return tso_versions; 2235 } 2236 2237 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 2238 { 2239 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 2240 struct efx_channel *channel = tx_queue->channel; 2241 struct efx_nic *efx = tx_queue->efx; 2242 struct efx_ef10_nic_data *nic_data; 2243 bool tso_v2 = false; 2244 efx_qword_t *txd; 2245 int rc; 2246 2247 nic_data = efx->nic_data; 2248 2249 /* Only attempt to enable TX timestamping if we have the license for it, 2250 * otherwise TXQ init will fail 2251 */ 2252 if (!(nic_data->licensed_features & 2253 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) { 2254 tx_queue->timestamping = false; 2255 /* Disable sync events on this channel. */ 2256 if (efx->type->ptp_set_ts_sync_events) 2257 efx->type->ptp_set_ts_sync_events(efx, false, false); 2258 } 2259 2260 /* TSOv2 is a limited resource that can only be configured on a limited 2261 * number of queues. TSO without checksum offload is not really a thing, 2262 * so we only enable it for those queues. 2263 * TSOv2 cannot be used with Hardware timestamping, and is never needed 2264 * for XDP tx. 2265 */ 2266 if (csum_offload && (nic_data->datapath_caps2 & 2267 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) && 2268 !tx_queue->timestamping && !tx_queue->xdp_tx) { 2269 tso_v2 = true; 2270 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n", 2271 channel->channel); 2272 } 2273 2274 rc = efx_mcdi_tx_init(tx_queue, tso_v2); 2275 if (rc) 2276 goto fail; 2277 2278 /* A previous user of this TX queue might have set us up the 2279 * bomb by writing a descriptor to the TX push collector but 2280 * not the doorbell. (Each collector belongs to a port, not a 2281 * queue or function, so cannot easily be reset.) We must 2282 * attempt to push a no-op descriptor in its place. 2283 */ 2284 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 2285 tx_queue->insert_count = 1; 2286 txd = efx_tx_desc(tx_queue, 0); 2287 EFX_POPULATE_QWORD_5(*txd, 2288 ESF_DZ_TX_DESC_IS_OPT, true, 2289 ESF_DZ_TX_OPTION_TYPE, 2290 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 2291 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 2292 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload, 2293 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping); 2294 tx_queue->write_count = 1; 2295 2296 if (tso_v2) { 2297 tx_queue->handle_tso = efx_ef10_tx_tso_desc; 2298 tx_queue->tso_version = 2; 2299 } else if (nic_data->datapath_caps & 2300 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) { 2301 tx_queue->tso_version = 1; 2302 } 2303 2304 wmb(); 2305 efx_ef10_push_tx_desc(tx_queue, txd); 2306 2307 return; 2308 2309 fail: 2310 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 2311 tx_queue->queue); 2312 } 2313 2314 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 2315 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 2316 { 2317 unsigned int write_ptr; 2318 efx_dword_t reg; 2319 2320 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2321 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 2322 efx_writed_page(tx_queue->efx, ®, 2323 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 2324 } 2325 2326 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff 2327 2328 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue, 2329 dma_addr_t dma_addr, unsigned int len) 2330 { 2331 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) { 2332 /* If we need to break across multiple descriptors we should 2333 * stop at a page boundary. This assumes the length limit is 2334 * greater than the page size. 2335 */ 2336 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN; 2337 2338 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE); 2339 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr; 2340 } 2341 2342 return len; 2343 } 2344 2345 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 2346 { 2347 unsigned int old_write_count = tx_queue->write_count; 2348 struct efx_tx_buffer *buffer; 2349 unsigned int write_ptr; 2350 efx_qword_t *txd; 2351 2352 tx_queue->xmit_more_available = false; 2353 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 2354 return; 2355 2356 do { 2357 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2358 buffer = &tx_queue->buffer[write_ptr]; 2359 txd = efx_tx_desc(tx_queue, write_ptr); 2360 ++tx_queue->write_count; 2361 2362 /* Create TX descriptor ring entry */ 2363 if (buffer->flags & EFX_TX_BUF_OPTION) { 2364 *txd = buffer->option; 2365 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1) 2366 /* PIO descriptor */ 2367 tx_queue->packet_write_count = tx_queue->write_count; 2368 } else { 2369 tx_queue->packet_write_count = tx_queue->write_count; 2370 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 2371 EFX_POPULATE_QWORD_3( 2372 *txd, 2373 ESF_DZ_TX_KER_CONT, 2374 buffer->flags & EFX_TX_BUF_CONT, 2375 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 2376 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 2377 } 2378 } while (tx_queue->write_count != tx_queue->insert_count); 2379 2380 wmb(); /* Ensure descriptors are written before they are fetched */ 2381 2382 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 2383 txd = efx_tx_desc(tx_queue, 2384 old_write_count & tx_queue->ptr_mask); 2385 efx_ef10_push_tx_desc(tx_queue, txd); 2386 ++tx_queue->pushes; 2387 } else { 2388 efx_ef10_notify_tx_desc(tx_queue); 2389 } 2390 } 2391 2392 static int efx_ef10_probe_multicast_chaining(struct efx_nic *efx) 2393 { 2394 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2395 unsigned int enabled, implemented; 2396 bool want_workaround_26807; 2397 int rc; 2398 2399 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2400 if (rc == -ENOSYS) { 2401 /* GET_WORKAROUNDS was implemented before this workaround, 2402 * thus it must be unavailable in this firmware. 2403 */ 2404 nic_data->workaround_26807 = false; 2405 return 0; 2406 } 2407 if (rc) 2408 return rc; 2409 want_workaround_26807 = 2410 implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807; 2411 nic_data->workaround_26807 = 2412 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2413 2414 if (want_workaround_26807 && !nic_data->workaround_26807) { 2415 unsigned int flags; 2416 2417 rc = efx_mcdi_set_workaround(efx, 2418 MC_CMD_WORKAROUND_BUG26807, 2419 true, &flags); 2420 if (!rc) { 2421 if (flags & 2422 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2423 netif_info(efx, drv, efx->net_dev, 2424 "other functions on NIC have been reset\n"); 2425 2426 /* With MCFW v4.6.x and earlier, the 2427 * boot count will have incremented, 2428 * so re-read the warm_boot_count 2429 * value now to ensure this function 2430 * doesn't think it has changed next 2431 * time it checks. 2432 */ 2433 rc = efx_ef10_get_warm_boot_count(efx); 2434 if (rc >= 0) { 2435 nic_data->warm_boot_count = rc; 2436 rc = 0; 2437 } 2438 } 2439 nic_data->workaround_26807 = true; 2440 } else if (rc == -EPERM) { 2441 rc = 0; 2442 } 2443 } 2444 return rc; 2445 } 2446 2447 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 2448 { 2449 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2450 int rc = efx_ef10_probe_multicast_chaining(efx); 2451 struct efx_mcdi_filter_vlan *vlan; 2452 2453 if (rc) 2454 return rc; 2455 rc = efx_mcdi_filter_table_probe(efx, nic_data->workaround_26807); 2456 2457 if (rc) 2458 return rc; 2459 2460 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 2461 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 2462 if (rc) 2463 goto fail_add_vlan; 2464 } 2465 return 0; 2466 2467 fail_add_vlan: 2468 efx_mcdi_filter_table_remove(efx); 2469 return rc; 2470 } 2471 2472 /* This creates an entry in the RX descriptor queue */ 2473 static inline void 2474 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2475 { 2476 struct efx_rx_buffer *rx_buf; 2477 efx_qword_t *rxd; 2478 2479 rxd = efx_rx_desc(rx_queue, index); 2480 rx_buf = efx_rx_buffer(rx_queue, index); 2481 EFX_POPULATE_QWORD_2(*rxd, 2482 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2483 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2484 } 2485 2486 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2487 { 2488 struct efx_nic *efx = rx_queue->efx; 2489 unsigned int write_count; 2490 efx_dword_t reg; 2491 2492 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2493 write_count = rx_queue->added_count & ~7; 2494 if (rx_queue->notified_count == write_count) 2495 return; 2496 2497 do 2498 efx_ef10_build_rx_desc( 2499 rx_queue, 2500 rx_queue->notified_count & rx_queue->ptr_mask); 2501 while (++rx_queue->notified_count != write_count); 2502 2503 wmb(); 2504 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2505 write_count & rx_queue->ptr_mask); 2506 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2507 efx_rx_queue_index(rx_queue)); 2508 } 2509 2510 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2511 2512 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2513 { 2514 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2515 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2516 efx_qword_t event; 2517 2518 EFX_POPULATE_QWORD_2(event, 2519 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2520 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2521 2522 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2523 2524 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2525 * already swapped the data to little-endian order. 2526 */ 2527 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2528 sizeof(efx_qword_t)); 2529 2530 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2531 inbuf, sizeof(inbuf), 0, 2532 efx_ef10_rx_defer_refill_complete, 0); 2533 } 2534 2535 static void 2536 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2537 int rc, efx_dword_t *outbuf, 2538 size_t outlen_actual) 2539 { 2540 /* nothing to do */ 2541 } 2542 2543 static int efx_ef10_ev_init(struct efx_channel *channel) 2544 { 2545 struct efx_nic *efx = channel->efx; 2546 struct efx_ef10_nic_data *nic_data; 2547 bool use_v2, cut_thru; 2548 2549 nic_data = efx->nic_data; 2550 use_v2 = nic_data->datapath_caps2 & 2551 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN; 2552 cut_thru = !(nic_data->datapath_caps & 2553 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2554 return efx_mcdi_ev_init(channel, cut_thru, use_v2); 2555 } 2556 2557 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2558 unsigned int rx_queue_label) 2559 { 2560 struct efx_nic *efx = rx_queue->efx; 2561 2562 netif_info(efx, hw, efx->net_dev, 2563 "rx event arrived on queue %d labeled as queue %u\n", 2564 efx_rx_queue_index(rx_queue), rx_queue_label); 2565 2566 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2567 } 2568 2569 static void 2570 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2571 unsigned int actual, unsigned int expected) 2572 { 2573 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2574 struct efx_nic *efx = rx_queue->efx; 2575 2576 netif_info(efx, hw, efx->net_dev, 2577 "dropped %d events (index=%d expected=%d)\n", 2578 dropped, actual, expected); 2579 2580 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2581 } 2582 2583 /* partially received RX was aborted. clean up. */ 2584 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2585 { 2586 unsigned int rx_desc_ptr; 2587 2588 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2589 "scattered RX aborted (dropping %u buffers)\n", 2590 rx_queue->scatter_n); 2591 2592 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2593 2594 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2595 0, EFX_RX_PKT_DISCARD); 2596 2597 rx_queue->removed_count += rx_queue->scatter_n; 2598 rx_queue->scatter_n = 0; 2599 rx_queue->scatter_len = 0; 2600 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2601 } 2602 2603 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel, 2604 unsigned int n_packets, 2605 unsigned int rx_encap_hdr, 2606 unsigned int rx_l3_class, 2607 unsigned int rx_l4_class, 2608 const efx_qword_t *event) 2609 { 2610 struct efx_nic *efx = channel->efx; 2611 bool handled = false; 2612 2613 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) { 2614 if (!(efx->net_dev->features & NETIF_F_RXALL)) { 2615 if (!efx->loopback_selftest) 2616 channel->n_rx_eth_crc_err += n_packets; 2617 return EFX_RX_PKT_DISCARD; 2618 } 2619 handled = true; 2620 } 2621 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) { 2622 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2623 rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2624 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2625 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2626 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2627 netdev_WARN(efx->net_dev, 2628 "invalid class for RX_IPCKSUM_ERR: event=" 2629 EFX_QWORD_FMT "\n", 2630 EFX_QWORD_VAL(*event)); 2631 if (!efx->loopback_selftest) 2632 *(rx_encap_hdr ? 2633 &channel->n_rx_outer_ip_hdr_chksum_err : 2634 &channel->n_rx_ip_hdr_chksum_err) += n_packets; 2635 return 0; 2636 } 2637 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) { 2638 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2639 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2640 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2641 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2642 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))) 2643 netdev_WARN(efx->net_dev, 2644 "invalid class for RX_TCPUDP_CKSUM_ERR: event=" 2645 EFX_QWORD_FMT "\n", 2646 EFX_QWORD_VAL(*event)); 2647 if (!efx->loopback_selftest) 2648 *(rx_encap_hdr ? 2649 &channel->n_rx_outer_tcp_udp_chksum_err : 2650 &channel->n_rx_tcp_udp_chksum_err) += n_packets; 2651 return 0; 2652 } 2653 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) { 2654 if (unlikely(!rx_encap_hdr)) 2655 netdev_WARN(efx->net_dev, 2656 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event=" 2657 EFX_QWORD_FMT "\n", 2658 EFX_QWORD_VAL(*event)); 2659 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2660 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2661 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2662 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2663 netdev_WARN(efx->net_dev, 2664 "invalid class for RX_IP_INNER_CHKSUM_ERR: event=" 2665 EFX_QWORD_FMT "\n", 2666 EFX_QWORD_VAL(*event)); 2667 if (!efx->loopback_selftest) 2668 channel->n_rx_inner_ip_hdr_chksum_err += n_packets; 2669 return 0; 2670 } 2671 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) { 2672 if (unlikely(!rx_encap_hdr)) 2673 netdev_WARN(efx->net_dev, 2674 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2675 EFX_QWORD_FMT "\n", 2676 EFX_QWORD_VAL(*event)); 2677 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2678 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2679 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2680 rx_l4_class != ESE_FZ_L4_CLASS_UDP))) 2681 netdev_WARN(efx->net_dev, 2682 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2683 EFX_QWORD_FMT "\n", 2684 EFX_QWORD_VAL(*event)); 2685 if (!efx->loopback_selftest) 2686 channel->n_rx_inner_tcp_udp_chksum_err += n_packets; 2687 return 0; 2688 } 2689 2690 WARN_ON(!handled); /* No error bits were recognised */ 2691 return 0; 2692 } 2693 2694 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2695 const efx_qword_t *event) 2696 { 2697 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label; 2698 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr; 2699 unsigned int n_descs, n_packets, i; 2700 struct efx_nic *efx = channel->efx; 2701 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2702 struct efx_rx_queue *rx_queue; 2703 efx_qword_t errors; 2704 bool rx_cont; 2705 u16 flags = 0; 2706 2707 if (unlikely(READ_ONCE(efx->reset_pending))) 2708 return 0; 2709 2710 /* Basic packet information */ 2711 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2712 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2713 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2714 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS); 2715 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS); 2716 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2717 rx_encap_hdr = 2718 nic_data->datapath_caps & 2719 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ? 2720 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) : 2721 ESE_EZ_ENCAP_HDR_NONE; 2722 2723 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2724 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2725 EFX_QWORD_FMT "\n", 2726 EFX_QWORD_VAL(*event)); 2727 2728 rx_queue = efx_channel_get_rx_queue(channel); 2729 2730 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2731 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2732 2733 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2734 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2735 2736 if (n_descs != rx_queue->scatter_n + 1) { 2737 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2738 2739 /* detect rx abort */ 2740 if (unlikely(n_descs == rx_queue->scatter_n)) { 2741 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2742 netdev_WARN(efx->net_dev, 2743 "invalid RX abort: scatter_n=%u event=" 2744 EFX_QWORD_FMT "\n", 2745 rx_queue->scatter_n, 2746 EFX_QWORD_VAL(*event)); 2747 efx_ef10_handle_rx_abort(rx_queue); 2748 return 0; 2749 } 2750 2751 /* Check that RX completion merging is valid, i.e. 2752 * the current firmware supports it and this is a 2753 * non-scattered packet. 2754 */ 2755 if (!(nic_data->datapath_caps & 2756 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2757 rx_queue->scatter_n != 0 || rx_cont) { 2758 efx_ef10_handle_rx_bad_lbits( 2759 rx_queue, next_ptr_lbits, 2760 (rx_queue->removed_count + 2761 rx_queue->scatter_n + 1) & 2762 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2763 return 0; 2764 } 2765 2766 /* Merged completion for multiple non-scattered packets */ 2767 rx_queue->scatter_n = 1; 2768 rx_queue->scatter_len = 0; 2769 n_packets = n_descs; 2770 ++channel->n_rx_merge_events; 2771 channel->n_rx_merge_packets += n_packets; 2772 flags |= EFX_RX_PKT_PREFIX_LEN; 2773 } else { 2774 ++rx_queue->scatter_n; 2775 rx_queue->scatter_len += rx_bytes; 2776 if (rx_cont) 2777 return 0; 2778 n_packets = 1; 2779 } 2780 2781 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1, 2782 ESF_DZ_RX_IPCKSUM_ERR, 1, 2783 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1, 2784 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1, 2785 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1); 2786 EFX_AND_QWORD(errors, *event, errors); 2787 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) { 2788 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets, 2789 rx_encap_hdr, 2790 rx_l3_class, rx_l4_class, 2791 event); 2792 } else { 2793 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP || 2794 rx_l4_class == ESE_FZ_L4_CLASS_UDP; 2795 2796 switch (rx_encap_hdr) { 2797 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */ 2798 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */ 2799 if (tcpudp) 2800 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */ 2801 break; 2802 case ESE_EZ_ENCAP_HDR_GRE: 2803 case ESE_EZ_ENCAP_HDR_NONE: 2804 if (tcpudp) 2805 flags |= EFX_RX_PKT_CSUMMED; 2806 break; 2807 default: 2808 netdev_WARN(efx->net_dev, 2809 "unknown encapsulation type: event=" 2810 EFX_QWORD_FMT "\n", 2811 EFX_QWORD_VAL(*event)); 2812 } 2813 } 2814 2815 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP) 2816 flags |= EFX_RX_PKT_TCP; 2817 2818 channel->irq_mod_score += 2 * n_packets; 2819 2820 /* Handle received packet(s) */ 2821 for (i = 0; i < n_packets; i++) { 2822 efx_rx_packet(rx_queue, 2823 rx_queue->removed_count & rx_queue->ptr_mask, 2824 rx_queue->scatter_n, rx_queue->scatter_len, 2825 flags); 2826 rx_queue->removed_count += rx_queue->scatter_n; 2827 } 2828 2829 rx_queue->scatter_n = 0; 2830 rx_queue->scatter_len = 0; 2831 2832 return n_packets; 2833 } 2834 2835 static u32 efx_ef10_extract_event_ts(efx_qword_t *event) 2836 { 2837 u32 tstamp; 2838 2839 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI); 2840 tstamp <<= 16; 2841 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO); 2842 2843 return tstamp; 2844 } 2845 2846 static void 2847 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2848 { 2849 struct efx_nic *efx = channel->efx; 2850 struct efx_tx_queue *tx_queue; 2851 unsigned int tx_ev_desc_ptr; 2852 unsigned int tx_ev_q_label; 2853 unsigned int tx_ev_type; 2854 u64 ts_part; 2855 2856 if (unlikely(READ_ONCE(efx->reset_pending))) 2857 return; 2858 2859 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2860 return; 2861 2862 /* Get the transmit queue */ 2863 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2864 tx_queue = efx_channel_get_tx_queue(channel, 2865 tx_ev_q_label % EFX_TXQ_TYPES); 2866 2867 if (!tx_queue->timestamping) { 2868 /* Transmit completion */ 2869 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2870 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2871 return; 2872 } 2873 2874 /* Transmit timestamps are only available for 8XXX series. They result 2875 * in up to three events per packet. These occur in order, and are: 2876 * - the normal completion event (may be omitted) 2877 * - the low part of the timestamp 2878 * - the high part of the timestamp 2879 * 2880 * It's possible for multiple completion events to appear before the 2881 * corresponding timestamps. So we can for example get: 2882 * COMP N 2883 * COMP N+1 2884 * TS_LO N 2885 * TS_HI N 2886 * TS_LO N+1 2887 * TS_HI N+1 2888 * 2889 * In addition it's also possible for the adjacent completions to be 2890 * merged, so we may not see COMP N above. As such, the completion 2891 * events are not very useful here. 2892 * 2893 * Each part of the timestamp is itself split across two 16 bit 2894 * fields in the event. 2895 */ 2896 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1); 2897 2898 switch (tx_ev_type) { 2899 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION: 2900 /* Ignore this event - see above. */ 2901 break; 2902 2903 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO: 2904 ts_part = efx_ef10_extract_event_ts(event); 2905 tx_queue->completed_timestamp_minor = ts_part; 2906 break; 2907 2908 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI: 2909 ts_part = efx_ef10_extract_event_ts(event); 2910 tx_queue->completed_timestamp_major = ts_part; 2911 2912 efx_xmit_done_single(tx_queue); 2913 break; 2914 2915 default: 2916 netif_err(efx, hw, efx->net_dev, 2917 "channel %d unknown tx event type %d (data " 2918 EFX_QWORD_FMT ")\n", 2919 channel->channel, tx_ev_type, 2920 EFX_QWORD_VAL(*event)); 2921 break; 2922 } 2923 } 2924 2925 static void 2926 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 2927 { 2928 struct efx_nic *efx = channel->efx; 2929 int subcode; 2930 2931 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 2932 2933 switch (subcode) { 2934 case ESE_DZ_DRV_TIMER_EV: 2935 case ESE_DZ_DRV_WAKE_UP_EV: 2936 break; 2937 case ESE_DZ_DRV_START_UP_EV: 2938 /* event queue init complete. ok. */ 2939 break; 2940 default: 2941 netif_err(efx, hw, efx->net_dev, 2942 "channel %d unknown driver event type %d" 2943 " (data " EFX_QWORD_FMT ")\n", 2944 channel->channel, subcode, 2945 EFX_QWORD_VAL(*event)); 2946 2947 } 2948 } 2949 2950 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 2951 efx_qword_t *event) 2952 { 2953 struct efx_nic *efx = channel->efx; 2954 u32 subcode; 2955 2956 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 2957 2958 switch (subcode) { 2959 case EFX_EF10_TEST: 2960 channel->event_test_cpu = raw_smp_processor_id(); 2961 break; 2962 case EFX_EF10_REFILL: 2963 /* The queue must be empty, so we won't receive any rx 2964 * events, so efx_process_channel() won't refill the 2965 * queue. Refill it here 2966 */ 2967 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 2968 break; 2969 default: 2970 netif_err(efx, hw, efx->net_dev, 2971 "channel %d unknown driver event type %u" 2972 " (data " EFX_QWORD_FMT ")\n", 2973 channel->channel, (unsigned) subcode, 2974 EFX_QWORD_VAL(*event)); 2975 } 2976 } 2977 2978 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 2979 { 2980 struct efx_nic *efx = channel->efx; 2981 efx_qword_t event, *p_event; 2982 unsigned int read_ptr; 2983 int ev_code; 2984 int spent = 0; 2985 2986 if (quota <= 0) 2987 return spent; 2988 2989 read_ptr = channel->eventq_read_ptr; 2990 2991 for (;;) { 2992 p_event = efx_event(channel, read_ptr); 2993 event = *p_event; 2994 2995 if (!efx_event_present(&event)) 2996 break; 2997 2998 EFX_SET_QWORD(*p_event); 2999 3000 ++read_ptr; 3001 3002 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 3003 3004 netif_vdbg(efx, drv, efx->net_dev, 3005 "processing event on %d " EFX_QWORD_FMT "\n", 3006 channel->channel, EFX_QWORD_VAL(event)); 3007 3008 switch (ev_code) { 3009 case ESE_DZ_EV_CODE_MCDI_EV: 3010 efx_mcdi_process_event(channel, &event); 3011 break; 3012 case ESE_DZ_EV_CODE_RX_EV: 3013 spent += efx_ef10_handle_rx_event(channel, &event); 3014 if (spent >= quota) { 3015 /* XXX can we split a merged event to 3016 * avoid going over-quota? 3017 */ 3018 spent = quota; 3019 goto out; 3020 } 3021 break; 3022 case ESE_DZ_EV_CODE_TX_EV: 3023 efx_ef10_handle_tx_event(channel, &event); 3024 break; 3025 case ESE_DZ_EV_CODE_DRIVER_EV: 3026 efx_ef10_handle_driver_event(channel, &event); 3027 if (++spent == quota) 3028 goto out; 3029 break; 3030 case EFX_EF10_DRVGEN_EV: 3031 efx_ef10_handle_driver_generated_event(channel, &event); 3032 break; 3033 default: 3034 netif_err(efx, hw, efx->net_dev, 3035 "channel %d unknown event type %d" 3036 " (data " EFX_QWORD_FMT ")\n", 3037 channel->channel, ev_code, 3038 EFX_QWORD_VAL(event)); 3039 } 3040 } 3041 3042 out: 3043 channel->eventq_read_ptr = read_ptr; 3044 return spent; 3045 } 3046 3047 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 3048 { 3049 struct efx_nic *efx = channel->efx; 3050 efx_dword_t rptr; 3051 3052 if (EFX_EF10_WORKAROUND_35388(efx)) { 3053 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 3054 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 3055 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 3056 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 3057 3058 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3059 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 3060 ERF_DD_EVQ_IND_RPTR, 3061 (channel->eventq_read_ptr & 3062 channel->eventq_mask) >> 3063 ERF_DD_EVQ_IND_RPTR_WIDTH); 3064 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3065 channel->channel); 3066 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3067 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 3068 ERF_DD_EVQ_IND_RPTR, 3069 channel->eventq_read_ptr & 3070 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 3071 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3072 channel->channel); 3073 } else { 3074 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 3075 channel->eventq_read_ptr & 3076 channel->eventq_mask); 3077 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 3078 } 3079 } 3080 3081 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 3082 { 3083 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 3084 struct efx_nic *efx = channel->efx; 3085 efx_qword_t event; 3086 int rc; 3087 3088 EFX_POPULATE_QWORD_2(event, 3089 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 3090 ESF_DZ_EV_DATA, EFX_EF10_TEST); 3091 3092 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 3093 3094 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 3095 * already swapped the data to little-endian order. 3096 */ 3097 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 3098 sizeof(efx_qword_t)); 3099 3100 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 3101 NULL, 0, NULL); 3102 if (rc != 0) 3103 goto fail; 3104 3105 return; 3106 3107 fail: 3108 WARN_ON(true); 3109 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 3110 } 3111 3112 void efx_ef10_handle_drain_event(struct efx_nic *efx) 3113 { 3114 if (atomic_dec_and_test(&efx->active_queues)) 3115 wake_up(&efx->flush_wq); 3116 3117 WARN_ON(atomic_read(&efx->active_queues) < 0); 3118 } 3119 3120 static int efx_ef10_fini_dmaq(struct efx_nic *efx) 3121 { 3122 struct efx_tx_queue *tx_queue; 3123 struct efx_rx_queue *rx_queue; 3124 struct efx_channel *channel; 3125 int pending; 3126 3127 /* If the MC has just rebooted, the TX/RX queues will have already been 3128 * torn down, but efx->active_queues needs to be set to zero. 3129 */ 3130 if (efx->must_realloc_vis) { 3131 atomic_set(&efx->active_queues, 0); 3132 return 0; 3133 } 3134 3135 /* Do not attempt to write to the NIC during EEH recovery */ 3136 if (efx->state != STATE_RECOVERY) { 3137 efx_for_each_channel(channel, efx) { 3138 efx_for_each_channel_rx_queue(rx_queue, channel) 3139 efx_mcdi_rx_fini(rx_queue); 3140 efx_for_each_channel_tx_queue(tx_queue, channel) 3141 efx_mcdi_tx_fini(tx_queue); 3142 } 3143 3144 wait_event_timeout(efx->flush_wq, 3145 atomic_read(&efx->active_queues) == 0, 3146 msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); 3147 pending = atomic_read(&efx->active_queues); 3148 if (pending) { 3149 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", 3150 pending); 3151 return -ETIMEDOUT; 3152 } 3153 } 3154 3155 return 0; 3156 } 3157 3158 static void efx_ef10_prepare_flr(struct efx_nic *efx) 3159 { 3160 atomic_set(&efx->active_queues, 0); 3161 } 3162 3163 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 3164 { 3165 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3166 u8 mac_old[ETH_ALEN]; 3167 int rc, rc2; 3168 3169 /* Only reconfigure a PF-created vport */ 3170 if (is_zero_ether_addr(nic_data->vport_mac)) 3171 return 0; 3172 3173 efx_device_detach_sync(efx); 3174 efx_net_stop(efx->net_dev); 3175 down_write(&efx->filter_sem); 3176 efx_mcdi_filter_table_remove(efx); 3177 up_write(&efx->filter_sem); 3178 3179 rc = efx_ef10_vadaptor_free(efx, efx->vport_id); 3180 if (rc) 3181 goto restore_filters; 3182 3183 ether_addr_copy(mac_old, nic_data->vport_mac); 3184 rc = efx_ef10_vport_del_mac(efx, efx->vport_id, 3185 nic_data->vport_mac); 3186 if (rc) 3187 goto restore_vadaptor; 3188 3189 rc = efx_ef10_vport_add_mac(efx, efx->vport_id, 3190 efx->net_dev->dev_addr); 3191 if (!rc) { 3192 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 3193 } else { 3194 rc2 = efx_ef10_vport_add_mac(efx, efx->vport_id, mac_old); 3195 if (rc2) { 3196 /* Failed to add original MAC, so clear vport_mac */ 3197 eth_zero_addr(nic_data->vport_mac); 3198 goto reset_nic; 3199 } 3200 } 3201 3202 restore_vadaptor: 3203 rc2 = efx_ef10_vadaptor_alloc(efx, efx->vport_id); 3204 if (rc2) 3205 goto reset_nic; 3206 restore_filters: 3207 down_write(&efx->filter_sem); 3208 rc2 = efx_ef10_filter_table_probe(efx); 3209 up_write(&efx->filter_sem); 3210 if (rc2) 3211 goto reset_nic; 3212 3213 rc2 = efx_net_open(efx->net_dev); 3214 if (rc2) 3215 goto reset_nic; 3216 3217 efx_device_attach_if_not_resetting(efx); 3218 3219 return rc; 3220 3221 reset_nic: 3222 netif_err(efx, drv, efx->net_dev, 3223 "Failed to restore when changing MAC address - scheduling reset\n"); 3224 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 3225 3226 return rc ? rc : rc2; 3227 } 3228 3229 static int efx_ef10_set_mac_address(struct efx_nic *efx) 3230 { 3231 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 3232 bool was_enabled = efx->port_enabled; 3233 int rc; 3234 3235 efx_device_detach_sync(efx); 3236 efx_net_stop(efx->net_dev); 3237 3238 mutex_lock(&efx->mac_lock); 3239 down_write(&efx->filter_sem); 3240 efx_mcdi_filter_table_remove(efx); 3241 3242 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 3243 efx->net_dev->dev_addr); 3244 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 3245 efx->vport_id); 3246 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 3247 sizeof(inbuf), NULL, 0, NULL); 3248 3249 efx_ef10_filter_table_probe(efx); 3250 up_write(&efx->filter_sem); 3251 mutex_unlock(&efx->mac_lock); 3252 3253 if (was_enabled) 3254 efx_net_open(efx->net_dev); 3255 efx_device_attach_if_not_resetting(efx); 3256 3257 #ifdef CONFIG_SFC_SRIOV 3258 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 3259 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3260 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 3261 3262 if (rc == -EPERM) { 3263 struct efx_nic *efx_pf; 3264 3265 /* Switch to PF and change MAC address on vport */ 3266 efx_pf = pci_get_drvdata(pci_dev_pf); 3267 3268 rc = efx_ef10_sriov_set_vf_mac(efx_pf, 3269 nic_data->vf_index, 3270 efx->net_dev->dev_addr); 3271 } else if (!rc) { 3272 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 3273 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data; 3274 unsigned int i; 3275 3276 /* MAC address successfully changed by VF (with MAC 3277 * spoofing) so update the parent PF if possible. 3278 */ 3279 for (i = 0; i < efx_pf->vf_count; ++i) { 3280 struct ef10_vf *vf = nic_data->vf + i; 3281 3282 if (vf->efx == efx) { 3283 ether_addr_copy(vf->mac, 3284 efx->net_dev->dev_addr); 3285 return 0; 3286 } 3287 } 3288 } 3289 } else 3290 #endif 3291 if (rc == -EPERM) { 3292 netif_err(efx, drv, efx->net_dev, 3293 "Cannot change MAC address; use sfboot to enable" 3294 " mac-spoofing on this interface\n"); 3295 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 3296 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 3297 * fall-back to the method of changing the MAC address on the 3298 * vport. This only applies to PFs because such versions of 3299 * MCFW do not support VFs. 3300 */ 3301 rc = efx_ef10_vport_set_mac_address(efx); 3302 } else if (rc) { 3303 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 3304 sizeof(inbuf), NULL, 0, rc); 3305 } 3306 3307 return rc; 3308 } 3309 3310 static int efx_ef10_mac_reconfigure(struct efx_nic *efx) 3311 { 3312 efx_mcdi_filter_sync_rx_mode(efx); 3313 3314 return efx_mcdi_set_mac(efx); 3315 } 3316 3317 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx) 3318 { 3319 efx_mcdi_filter_sync_rx_mode(efx); 3320 3321 return 0; 3322 } 3323 3324 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 3325 { 3326 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 3327 3328 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 3329 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 3330 NULL, 0, NULL); 3331 } 3332 3333 /* MC BISTs follow a different poll mechanism to phy BISTs. 3334 * The BIST is done in the poll handler on the MC, and the MCDI command 3335 * will block until the BIST is done. 3336 */ 3337 static int efx_ef10_poll_bist(struct efx_nic *efx) 3338 { 3339 int rc; 3340 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 3341 size_t outlen; 3342 u32 result; 3343 3344 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 3345 outbuf, sizeof(outbuf), &outlen); 3346 if (rc != 0) 3347 return rc; 3348 3349 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 3350 return -EIO; 3351 3352 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 3353 switch (result) { 3354 case MC_CMD_POLL_BIST_PASSED: 3355 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 3356 return 0; 3357 case MC_CMD_POLL_BIST_TIMEOUT: 3358 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 3359 return -EIO; 3360 case MC_CMD_POLL_BIST_FAILED: 3361 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 3362 return -EIO; 3363 default: 3364 netif_err(efx, hw, efx->net_dev, 3365 "BIST returned unknown result %u", result); 3366 return -EIO; 3367 } 3368 } 3369 3370 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 3371 { 3372 int rc; 3373 3374 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 3375 3376 rc = efx_ef10_start_bist(efx, bist_type); 3377 if (rc != 0) 3378 return rc; 3379 3380 return efx_ef10_poll_bist(efx); 3381 } 3382 3383 static int 3384 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 3385 { 3386 int rc, rc2; 3387 3388 efx_reset_down(efx, RESET_TYPE_WORLD); 3389 3390 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 3391 NULL, 0, NULL, 0, NULL); 3392 if (rc != 0) 3393 goto out; 3394 3395 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 3396 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 3397 3398 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 3399 3400 out: 3401 if (rc == -EPERM) 3402 rc = 0; 3403 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 3404 return rc ? rc : rc2; 3405 } 3406 3407 #ifdef CONFIG_SFC_MTD 3408 3409 struct efx_ef10_nvram_type_info { 3410 u16 type, type_mask; 3411 u8 port; 3412 const char *name; 3413 }; 3414 3415 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 3416 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 3417 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 3418 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 3419 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 3420 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 3421 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 3422 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 3423 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 3424 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 3425 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 3426 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 3427 { NVRAM_PARTITION_TYPE_MUM_FIRMWARE, 0, 0, "sfc_mumfw" }, 3428 { NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 0, 0, "sfc_uefi" }, 3429 { NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS, 0, 0, "sfc_dynamic_cfg_dflt" }, 3430 { NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS, 0, 0, "sfc_exp_rom_cfg_dflt" }, 3431 { NVRAM_PARTITION_TYPE_STATUS, 0, 0, "sfc_status" }, 3432 { NVRAM_PARTITION_TYPE_BUNDLE, 0, 0, "sfc_bundle" }, 3433 { NVRAM_PARTITION_TYPE_BUNDLE_METADATA, 0, 0, "sfc_bundle_metadata" }, 3434 }; 3435 #define EF10_NVRAM_PARTITION_COUNT ARRAY_SIZE(efx_ef10_nvram_types) 3436 3437 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 3438 struct efx_mcdi_mtd_partition *part, 3439 unsigned int type, 3440 unsigned long *found) 3441 { 3442 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 3443 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 3444 const struct efx_ef10_nvram_type_info *info; 3445 size_t size, erase_size, outlen; 3446 int type_idx = 0; 3447 bool protected; 3448 int rc; 3449 3450 for (type_idx = 0; ; type_idx++) { 3451 if (type_idx == EF10_NVRAM_PARTITION_COUNT) 3452 return -ENODEV; 3453 info = efx_ef10_nvram_types + type_idx; 3454 if ((type & ~info->type_mask) == info->type) 3455 break; 3456 } 3457 if (info->port != efx_port_num(efx)) 3458 return -ENODEV; 3459 3460 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 3461 if (rc) 3462 return rc; 3463 if (protected && 3464 (type != NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS && 3465 type != NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS)) 3466 /* Hide protected partitions that don't provide defaults. */ 3467 return -ENODEV; 3468 3469 if (protected) 3470 /* Protected partitions are read only. */ 3471 erase_size = 0; 3472 3473 /* If we've already exposed a partition of this type, hide this 3474 * duplicate. All operations on MTDs are keyed by the type anyway, 3475 * so we can't act on the duplicate. 3476 */ 3477 if (__test_and_set_bit(type_idx, found)) 3478 return -EEXIST; 3479 3480 part->nvram_type = type; 3481 3482 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 3483 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 3484 outbuf, sizeof(outbuf), &outlen); 3485 if (rc) 3486 return rc; 3487 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 3488 return -EIO; 3489 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 3490 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 3491 part->fw_subtype = MCDI_DWORD(outbuf, 3492 NVRAM_METADATA_OUT_SUBTYPE); 3493 3494 part->common.dev_type_name = "EF10 NVRAM manager"; 3495 part->common.type_name = info->name; 3496 3497 part->common.mtd.type = MTD_NORFLASH; 3498 part->common.mtd.flags = MTD_CAP_NORFLASH; 3499 part->common.mtd.size = size; 3500 part->common.mtd.erasesize = erase_size; 3501 /* sfc_status is read-only */ 3502 if (!erase_size) 3503 part->common.mtd.flags |= MTD_NO_ERASE; 3504 3505 return 0; 3506 } 3507 3508 static int efx_ef10_mtd_probe(struct efx_nic *efx) 3509 { 3510 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 3511 DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 }; 3512 struct efx_mcdi_mtd_partition *parts; 3513 size_t outlen, n_parts_total, i, n_parts; 3514 unsigned int type; 3515 int rc; 3516 3517 ASSERT_RTNL(); 3518 3519 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 3520 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 3521 outbuf, sizeof(outbuf), &outlen); 3522 if (rc) 3523 return rc; 3524 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 3525 return -EIO; 3526 3527 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 3528 if (n_parts_total > 3529 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 3530 return -EIO; 3531 3532 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 3533 if (!parts) 3534 return -ENOMEM; 3535 3536 n_parts = 0; 3537 for (i = 0; i < n_parts_total; i++) { 3538 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 3539 i); 3540 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type, 3541 found); 3542 if (rc == -EEXIST || rc == -ENODEV) 3543 continue; 3544 if (rc) 3545 goto fail; 3546 n_parts++; 3547 } 3548 3549 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 3550 fail: 3551 if (rc) 3552 kfree(parts); 3553 return rc; 3554 } 3555 3556 #endif /* CONFIG_SFC_MTD */ 3557 3558 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 3559 { 3560 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 3561 } 3562 3563 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 3564 u32 host_time) {} 3565 3566 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 3567 bool temp) 3568 { 3569 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 3570 int rc; 3571 3572 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 3573 channel->sync_events_state == SYNC_EVENTS_VALID || 3574 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 3575 return 0; 3576 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 3577 3578 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 3579 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3580 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 3581 channel->channel); 3582 3583 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3584 inbuf, sizeof(inbuf), NULL, 0, NULL); 3585 3586 if (rc != 0) 3587 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3588 SYNC_EVENTS_DISABLED; 3589 3590 return rc; 3591 } 3592 3593 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 3594 bool temp) 3595 { 3596 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 3597 int rc; 3598 3599 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 3600 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 3601 return 0; 3602 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 3603 channel->sync_events_state = SYNC_EVENTS_DISABLED; 3604 return 0; 3605 } 3606 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3607 SYNC_EVENTS_DISABLED; 3608 3609 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 3610 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3611 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 3612 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 3613 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 3614 channel->channel); 3615 3616 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3617 inbuf, sizeof(inbuf), NULL, 0, NULL); 3618 3619 return rc; 3620 } 3621 3622 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 3623 bool temp) 3624 { 3625 int (*set)(struct efx_channel *channel, bool temp); 3626 struct efx_channel *channel; 3627 3628 set = en ? 3629 efx_ef10_rx_enable_timestamping : 3630 efx_ef10_rx_disable_timestamping; 3631 3632 channel = efx_ptp_channel(efx); 3633 if (channel) { 3634 int rc = set(channel, temp); 3635 if (en && rc != 0) { 3636 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 3637 return rc; 3638 } 3639 } 3640 3641 return 0; 3642 } 3643 3644 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 3645 struct hwtstamp_config *init) 3646 { 3647 return -EOPNOTSUPP; 3648 } 3649 3650 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 3651 struct hwtstamp_config *init) 3652 { 3653 int rc; 3654 3655 switch (init->rx_filter) { 3656 case HWTSTAMP_FILTER_NONE: 3657 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 3658 /* if TX timestamping is still requested then leave PTP on */ 3659 return efx_ptp_change_mode(efx, 3660 init->tx_type != HWTSTAMP_TX_OFF, 0); 3661 case HWTSTAMP_FILTER_ALL: 3662 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3663 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3664 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3665 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3666 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3667 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3668 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3669 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3670 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3671 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3672 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3673 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3674 case HWTSTAMP_FILTER_NTP_ALL: 3675 init->rx_filter = HWTSTAMP_FILTER_ALL; 3676 rc = efx_ptp_change_mode(efx, true, 0); 3677 if (!rc) 3678 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 3679 if (rc) 3680 efx_ptp_change_mode(efx, false, 0); 3681 return rc; 3682 default: 3683 return -ERANGE; 3684 } 3685 } 3686 3687 static int efx_ef10_get_phys_port_id(struct efx_nic *efx, 3688 struct netdev_phys_item_id *ppid) 3689 { 3690 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3691 3692 if (!is_valid_ether_addr(nic_data->port_id)) 3693 return -EOPNOTSUPP; 3694 3695 ppid->id_len = ETH_ALEN; 3696 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 3697 3698 return 0; 3699 } 3700 3701 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3702 { 3703 if (proto != htons(ETH_P_8021Q)) 3704 return -EINVAL; 3705 3706 return efx_ef10_add_vlan(efx, vid); 3707 } 3708 3709 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3710 { 3711 if (proto != htons(ETH_P_8021Q)) 3712 return -EINVAL; 3713 3714 return efx_ef10_del_vlan(efx, vid); 3715 } 3716 3717 /* We rely on the MCDI wiping out our TX rings if it made any changes to the 3718 * ports table, ensuring that any TSO descriptors that were made on a now- 3719 * removed tunnel port will be blown away and won't break things when we try 3720 * to transmit them using the new ports table. 3721 */ 3722 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading) 3723 { 3724 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3725 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX); 3726 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN); 3727 bool will_reset = false; 3728 size_t num_entries = 0; 3729 size_t inlen, outlen; 3730 size_t i; 3731 int rc; 3732 efx_dword_t flags_and_num_entries; 3733 3734 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock)); 3735 3736 nic_data->udp_tunnels_dirty = false; 3737 3738 if (!(nic_data->datapath_caps & 3739 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) { 3740 efx_device_attach_if_not_resetting(efx); 3741 return 0; 3742 } 3743 3744 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) > 3745 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM); 3746 3747 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) { 3748 if (nic_data->udp_tunnels[i].count && 3749 nic_data->udp_tunnels[i].port) { 3750 efx_dword_t entry; 3751 3752 EFX_POPULATE_DWORD_2(entry, 3753 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT, 3754 ntohs(nic_data->udp_tunnels[i].port), 3755 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL, 3756 nic_data->udp_tunnels[i].type); 3757 *_MCDI_ARRAY_DWORD(inbuf, 3758 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES, 3759 num_entries++) = entry; 3760 } 3761 } 3762 3763 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST - 3764 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 != 3765 EFX_WORD_1_LBN); 3766 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 != 3767 EFX_WORD_1_WIDTH); 3768 EFX_POPULATE_DWORD_2(flags_and_num_entries, 3769 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING, 3770 !!unloading, 3771 EFX_WORD_1, num_entries); 3772 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) = 3773 flags_and_num_entries; 3774 3775 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries); 3776 3777 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS, 3778 inbuf, inlen, outbuf, sizeof(outbuf), &outlen); 3779 if (rc == -EIO) { 3780 /* Most likely the MC rebooted due to another function also 3781 * setting its tunnel port list. Mark the tunnel port list as 3782 * dirty, so it will be pushed upon coming up from the reboot. 3783 */ 3784 nic_data->udp_tunnels_dirty = true; 3785 return 0; 3786 } 3787 3788 if (rc) { 3789 /* expected not available on unprivileged functions */ 3790 if (rc != -EPERM) 3791 netif_warn(efx, drv, efx->net_dev, 3792 "Unable to set UDP tunnel ports; rc=%d.\n", rc); 3793 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) & 3794 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) { 3795 netif_info(efx, drv, efx->net_dev, 3796 "Rebooting MC due to UDP tunnel port list change\n"); 3797 will_reset = true; 3798 if (unloading) 3799 /* Delay for the MC reset to complete. This will make 3800 * unloading other functions a bit smoother. This is a 3801 * race, but the other unload will work whichever way 3802 * it goes, this just avoids an unnecessary error 3803 * message. 3804 */ 3805 msleep(100); 3806 } 3807 if (!will_reset && !unloading) { 3808 /* The caller will have detached, relying on the MC reset to 3809 * trigger a re-attach. Since there won't be an MC reset, we 3810 * have to do the attach ourselves. 3811 */ 3812 efx_device_attach_if_not_resetting(efx); 3813 } 3814 3815 return rc; 3816 } 3817 3818 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx) 3819 { 3820 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3821 int rc = 0; 3822 3823 mutex_lock(&nic_data->udp_tunnels_lock); 3824 if (nic_data->udp_tunnels_dirty) { 3825 /* Make sure all TX are stopped while we modify the table, else 3826 * we might race against an efx_features_check(). 3827 */ 3828 efx_device_detach_sync(efx); 3829 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3830 } 3831 mutex_unlock(&nic_data->udp_tunnels_lock); 3832 return rc; 3833 } 3834 3835 static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx, 3836 __be16 port) 3837 { 3838 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3839 size_t i; 3840 3841 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) { 3842 if (!nic_data->udp_tunnels[i].count) 3843 continue; 3844 if (nic_data->udp_tunnels[i].port == port) 3845 return &nic_data->udp_tunnels[i]; 3846 } 3847 return NULL; 3848 } 3849 3850 static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx, 3851 struct efx_udp_tunnel tnl) 3852 { 3853 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3854 struct efx_udp_tunnel *match; 3855 char typebuf[8]; 3856 size_t i; 3857 int rc; 3858 3859 if (!(nic_data->datapath_caps & 3860 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3861 return 0; 3862 3863 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf)); 3864 netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n", 3865 typebuf, ntohs(tnl.port)); 3866 3867 mutex_lock(&nic_data->udp_tunnels_lock); 3868 /* Make sure all TX are stopped while we add to the table, else we 3869 * might race against an efx_features_check(). 3870 */ 3871 efx_device_detach_sync(efx); 3872 3873 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port); 3874 if (match != NULL) { 3875 if (match->type == tnl.type) { 3876 netif_dbg(efx, drv, efx->net_dev, 3877 "Referencing existing tunnel entry\n"); 3878 match->count++; 3879 /* No need to cause an MCDI update */ 3880 rc = 0; 3881 goto unlock_out; 3882 } 3883 efx_get_udp_tunnel_type_name(match->type, 3884 typebuf, sizeof(typebuf)); 3885 netif_dbg(efx, drv, efx->net_dev, 3886 "UDP port %d is already in use by %s\n", 3887 ntohs(tnl.port), typebuf); 3888 rc = -EEXIST; 3889 goto unlock_out; 3890 } 3891 3892 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 3893 if (!nic_data->udp_tunnels[i].count) { 3894 nic_data->udp_tunnels[i] = tnl; 3895 nic_data->udp_tunnels[i].count = 1; 3896 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3897 goto unlock_out; 3898 } 3899 3900 netif_dbg(efx, drv, efx->net_dev, 3901 "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n", 3902 typebuf, ntohs(tnl.port)); 3903 3904 rc = -ENOMEM; 3905 3906 unlock_out: 3907 mutex_unlock(&nic_data->udp_tunnels_lock); 3908 return rc; 3909 } 3910 3911 /* Called under the TX lock with the TX queue running, hence no-one can be 3912 * in the middle of updating the UDP tunnels table. However, they could 3913 * have tried and failed the MCDI, in which case they'll have set the dirty 3914 * flag before dropping their locks. 3915 */ 3916 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port) 3917 { 3918 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3919 3920 if (!(nic_data->datapath_caps & 3921 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3922 return false; 3923 3924 if (nic_data->udp_tunnels_dirty) 3925 /* SW table may not match HW state, so just assume we can't 3926 * use any UDP tunnel offloads. 3927 */ 3928 return false; 3929 3930 return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL; 3931 } 3932 3933 static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx, 3934 struct efx_udp_tunnel tnl) 3935 { 3936 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3937 struct efx_udp_tunnel *match; 3938 char typebuf[8]; 3939 int rc; 3940 3941 if (!(nic_data->datapath_caps & 3942 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3943 return 0; 3944 3945 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf)); 3946 netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n", 3947 typebuf, ntohs(tnl.port)); 3948 3949 mutex_lock(&nic_data->udp_tunnels_lock); 3950 /* Make sure all TX are stopped while we remove from the table, else we 3951 * might race against an efx_features_check(). 3952 */ 3953 efx_device_detach_sync(efx); 3954 3955 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port); 3956 if (match != NULL) { 3957 if (match->type == tnl.type) { 3958 if (--match->count) { 3959 /* Port is still in use, so nothing to do */ 3960 netif_dbg(efx, drv, efx->net_dev, 3961 "UDP tunnel port %d remains active\n", 3962 ntohs(tnl.port)); 3963 rc = 0; 3964 goto out_unlock; 3965 } 3966 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3967 goto out_unlock; 3968 } 3969 efx_get_udp_tunnel_type_name(match->type, 3970 typebuf, sizeof(typebuf)); 3971 netif_warn(efx, drv, efx->net_dev, 3972 "UDP port %d is actually in use by %s, not removing\n", 3973 ntohs(tnl.port), typebuf); 3974 } 3975 rc = -ENOENT; 3976 3977 out_unlock: 3978 mutex_unlock(&nic_data->udp_tunnels_lock); 3979 return rc; 3980 } 3981 3982 /* EF10 may have multiple datapath firmware variants within a 3983 * single version. Report which variants are running. 3984 */ 3985 static size_t efx_ef10_print_additional_fwver(struct efx_nic *efx, char *buf, 3986 size_t len) 3987 { 3988 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3989 3990 return scnprintf(buf, len, " rx%x tx%x", 3991 nic_data->rx_dpcpu_fw_id, 3992 nic_data->tx_dpcpu_fw_id); 3993 } 3994 3995 static unsigned int ef10_check_caps(const struct efx_nic *efx, 3996 u8 flag, 3997 u32 offset) 3998 { 3999 const struct efx_ef10_nic_data *nic_data = efx->nic_data; 4000 4001 switch (offset) { 4002 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST): 4003 return nic_data->datapath_caps & BIT_ULL(flag); 4004 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST): 4005 return nic_data->datapath_caps2 & BIT_ULL(flag); 4006 default: 4007 return 0; 4008 } 4009 } 4010 4011 #define EF10_OFFLOAD_FEATURES \ 4012 (NETIF_F_IP_CSUM | \ 4013 NETIF_F_HW_VLAN_CTAG_FILTER | \ 4014 NETIF_F_IPV6_CSUM | \ 4015 NETIF_F_RXHASH | \ 4016 NETIF_F_NTUPLE) 4017 4018 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 4019 .is_vf = true, 4020 .mem_bar = efx_ef10_vf_mem_bar, 4021 .mem_map_size = efx_ef10_mem_map_size, 4022 .probe = efx_ef10_probe_vf, 4023 .remove = efx_ef10_remove, 4024 .dimension_resources = efx_ef10_dimension_resources, 4025 .init = efx_ef10_init_nic, 4026 .fini = efx_port_dummy_op_void, 4027 .map_reset_reason = efx_ef10_map_reset_reason, 4028 .map_reset_flags = efx_ef10_map_reset_flags, 4029 .reset = efx_ef10_reset, 4030 .probe_port = efx_mcdi_port_probe, 4031 .remove_port = efx_mcdi_port_remove, 4032 .fini_dmaq = efx_ef10_fini_dmaq, 4033 .prepare_flr = efx_ef10_prepare_flr, 4034 .finish_flr = efx_port_dummy_op_void, 4035 .describe_stats = efx_ef10_describe_stats, 4036 .update_stats = efx_ef10_update_stats_vf, 4037 .start_stats = efx_port_dummy_op_void, 4038 .pull_stats = efx_port_dummy_op_void, 4039 .stop_stats = efx_port_dummy_op_void, 4040 .set_id_led = efx_mcdi_set_id_led, 4041 .push_irq_moderation = efx_ef10_push_irq_moderation, 4042 .reconfigure_mac = efx_ef10_mac_reconfigure_vf, 4043 .check_mac_fault = efx_mcdi_mac_check_fault, 4044 .reconfigure_port = efx_mcdi_port_reconfigure, 4045 .get_wol = efx_ef10_get_wol_vf, 4046 .set_wol = efx_ef10_set_wol_vf, 4047 .resume_wol = efx_port_dummy_op_void, 4048 .mcdi_request = efx_ef10_mcdi_request, 4049 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4050 .mcdi_read_response = efx_ef10_mcdi_read_response, 4051 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4052 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4053 .irq_enable_master = efx_port_dummy_op_void, 4054 .irq_test_generate = efx_ef10_irq_test_generate, 4055 .irq_disable_non_ev = efx_port_dummy_op_void, 4056 .irq_handle_msi = efx_ef10_msi_interrupt, 4057 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4058 .tx_probe = efx_ef10_tx_probe, 4059 .tx_init = efx_ef10_tx_init, 4060 .tx_remove = efx_mcdi_tx_remove, 4061 .tx_write = efx_ef10_tx_write, 4062 .tx_limit_len = efx_ef10_tx_limit_len, 4063 .rx_push_rss_config = efx_mcdi_vf_rx_push_rss_config, 4064 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4065 .rx_probe = efx_mcdi_rx_probe, 4066 .rx_init = efx_mcdi_rx_init, 4067 .rx_remove = efx_mcdi_rx_remove, 4068 .rx_write = efx_ef10_rx_write, 4069 .rx_defer_refill = efx_ef10_rx_defer_refill, 4070 .ev_probe = efx_mcdi_ev_probe, 4071 .ev_init = efx_ef10_ev_init, 4072 .ev_fini = efx_mcdi_ev_fini, 4073 .ev_remove = efx_mcdi_ev_remove, 4074 .ev_process = efx_ef10_ev_process, 4075 .ev_read_ack = efx_ef10_ev_read_ack, 4076 .ev_test_generate = efx_ef10_ev_test_generate, 4077 .filter_table_probe = efx_ef10_filter_table_probe, 4078 .filter_table_restore = efx_mcdi_filter_table_restore, 4079 .filter_table_remove = efx_mcdi_filter_table_remove, 4080 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4081 .filter_insert = efx_mcdi_filter_insert, 4082 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4083 .filter_get_safe = efx_mcdi_filter_get_safe, 4084 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4085 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4086 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4087 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4088 #ifdef CONFIG_RFS_ACCEL 4089 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4090 #endif 4091 #ifdef CONFIG_SFC_MTD 4092 .mtd_probe = efx_port_dummy_op_int, 4093 #endif 4094 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4095 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4096 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4097 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4098 #ifdef CONFIG_SFC_SRIOV 4099 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4100 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4101 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4102 #endif 4103 .get_mac_address = efx_ef10_get_mac_address_vf, 4104 .set_mac_address = efx_ef10_set_mac_address, 4105 4106 .get_phys_port_id = efx_ef10_get_phys_port_id, 4107 .revision = EFX_REV_HUNT_A0, 4108 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4109 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4110 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4111 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4112 .can_rx_scatter = true, 4113 .always_rx_scatter = true, 4114 .min_interrupt_mode = EFX_INT_MODE_MSIX, 4115 .max_interrupt_mode = EFX_INT_MODE_MSIX, 4116 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4117 .offload_features = EF10_OFFLOAD_FEATURES, 4118 .mcdi_max_ver = 2, 4119 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4120 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4121 1 << HWTSTAMP_FILTER_ALL, 4122 .rx_hash_key_size = 40, 4123 .check_caps = ef10_check_caps, 4124 .print_additional_fwver = efx_ef10_print_additional_fwver, 4125 }; 4126 4127 const struct efx_nic_type efx_hunt_a0_nic_type = { 4128 .is_vf = false, 4129 .mem_bar = efx_ef10_pf_mem_bar, 4130 .mem_map_size = efx_ef10_mem_map_size, 4131 .probe = efx_ef10_probe_pf, 4132 .remove = efx_ef10_remove, 4133 .dimension_resources = efx_ef10_dimension_resources, 4134 .init = efx_ef10_init_nic, 4135 .fini = efx_port_dummy_op_void, 4136 .map_reset_reason = efx_ef10_map_reset_reason, 4137 .map_reset_flags = efx_ef10_map_reset_flags, 4138 .reset = efx_ef10_reset, 4139 .probe_port = efx_mcdi_port_probe, 4140 .remove_port = efx_mcdi_port_remove, 4141 .fini_dmaq = efx_ef10_fini_dmaq, 4142 .prepare_flr = efx_ef10_prepare_flr, 4143 .finish_flr = efx_port_dummy_op_void, 4144 .describe_stats = efx_ef10_describe_stats, 4145 .update_stats = efx_ef10_update_stats_pf, 4146 .start_stats = efx_mcdi_mac_start_stats, 4147 .pull_stats = efx_mcdi_mac_pull_stats, 4148 .stop_stats = efx_mcdi_mac_stop_stats, 4149 .set_id_led = efx_mcdi_set_id_led, 4150 .push_irq_moderation = efx_ef10_push_irq_moderation, 4151 .reconfigure_mac = efx_ef10_mac_reconfigure, 4152 .check_mac_fault = efx_mcdi_mac_check_fault, 4153 .reconfigure_port = efx_mcdi_port_reconfigure, 4154 .get_wol = efx_ef10_get_wol, 4155 .set_wol = efx_ef10_set_wol, 4156 .resume_wol = efx_port_dummy_op_void, 4157 .test_chip = efx_ef10_test_chip, 4158 .test_nvram = efx_mcdi_nvram_test_all, 4159 .mcdi_request = efx_ef10_mcdi_request, 4160 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4161 .mcdi_read_response = efx_ef10_mcdi_read_response, 4162 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4163 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4164 .irq_enable_master = efx_port_dummy_op_void, 4165 .irq_test_generate = efx_ef10_irq_test_generate, 4166 .irq_disable_non_ev = efx_port_dummy_op_void, 4167 .irq_handle_msi = efx_ef10_msi_interrupt, 4168 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4169 .tx_probe = efx_ef10_tx_probe, 4170 .tx_init = efx_ef10_tx_init, 4171 .tx_remove = efx_mcdi_tx_remove, 4172 .tx_write = efx_ef10_tx_write, 4173 .tx_limit_len = efx_ef10_tx_limit_len, 4174 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 4175 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4176 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 4177 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 4178 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 4179 .rx_probe = efx_mcdi_rx_probe, 4180 .rx_init = efx_mcdi_rx_init, 4181 .rx_remove = efx_mcdi_rx_remove, 4182 .rx_write = efx_ef10_rx_write, 4183 .rx_defer_refill = efx_ef10_rx_defer_refill, 4184 .ev_probe = efx_mcdi_ev_probe, 4185 .ev_init = efx_ef10_ev_init, 4186 .ev_fini = efx_mcdi_ev_fini, 4187 .ev_remove = efx_mcdi_ev_remove, 4188 .ev_process = efx_ef10_ev_process, 4189 .ev_read_ack = efx_ef10_ev_read_ack, 4190 .ev_test_generate = efx_ef10_ev_test_generate, 4191 .filter_table_probe = efx_ef10_filter_table_probe, 4192 .filter_table_restore = efx_mcdi_filter_table_restore, 4193 .filter_table_remove = efx_mcdi_filter_table_remove, 4194 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4195 .filter_insert = efx_mcdi_filter_insert, 4196 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4197 .filter_get_safe = efx_mcdi_filter_get_safe, 4198 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4199 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4200 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4201 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4202 #ifdef CONFIG_RFS_ACCEL 4203 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4204 #endif 4205 #ifdef CONFIG_SFC_MTD 4206 .mtd_probe = efx_ef10_mtd_probe, 4207 .mtd_rename = efx_mcdi_mtd_rename, 4208 .mtd_read = efx_mcdi_mtd_read, 4209 .mtd_erase = efx_mcdi_mtd_erase, 4210 .mtd_write = efx_mcdi_mtd_write, 4211 .mtd_sync = efx_mcdi_mtd_sync, 4212 #endif 4213 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4214 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4215 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4216 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4217 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4218 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports, 4219 .udp_tnl_add_port = efx_ef10_udp_tnl_add_port, 4220 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port, 4221 .udp_tnl_del_port = efx_ef10_udp_tnl_del_port, 4222 #ifdef CONFIG_SFC_SRIOV 4223 .sriov_configure = efx_ef10_sriov_configure, 4224 .sriov_init = efx_ef10_sriov_init, 4225 .sriov_fini = efx_ef10_sriov_fini, 4226 .sriov_wanted = efx_ef10_sriov_wanted, 4227 .sriov_reset = efx_ef10_sriov_reset, 4228 .sriov_flr = efx_ef10_sriov_flr, 4229 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4230 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4231 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4232 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4233 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4234 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4235 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4236 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4237 #endif 4238 .get_mac_address = efx_ef10_get_mac_address_pf, 4239 .set_mac_address = efx_ef10_set_mac_address, 4240 .tso_versions = efx_ef10_tso_versions, 4241 4242 .get_phys_port_id = efx_ef10_get_phys_port_id, 4243 .revision = EFX_REV_HUNT_A0, 4244 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4245 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4246 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4247 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4248 .can_rx_scatter = true, 4249 .always_rx_scatter = true, 4250 .option_descriptors = true, 4251 .min_interrupt_mode = EFX_INT_MODE_LEGACY, 4252 .max_interrupt_mode = EFX_INT_MODE_MSIX, 4253 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4254 .offload_features = EF10_OFFLOAD_FEATURES, 4255 .mcdi_max_ver = 2, 4256 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4257 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4258 1 << HWTSTAMP_FILTER_ALL, 4259 .rx_hash_key_size = 40, 4260 .check_caps = ef10_check_caps, 4261 .print_additional_fwver = efx_ef10_print_additional_fwver, 4262 }; 4263