1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2012-2013 Solarflare Communications Inc. 5 */ 6 7 #include "net_driver.h" 8 #include "rx_common.h" 9 #include "tx_common.h" 10 #include "ef10_regs.h" 11 #include "io.h" 12 #include "mcdi.h" 13 #include "mcdi_pcol.h" 14 #include "mcdi_port.h" 15 #include "mcdi_port_common.h" 16 #include "mcdi_functions.h" 17 #include "nic.h" 18 #include "mcdi_filters.h" 19 #include "workarounds.h" 20 #include "selftest.h" 21 #include "ef10_sriov.h" 22 #include <linux/in.h> 23 #include <linux/jhash.h> 24 #include <linux/wait.h> 25 #include <linux/workqueue.h> 26 #include <net/udp_tunnel.h> 27 28 /* Hardware control for EF10 architecture including 'Huntington'. */ 29 30 #define EFX_EF10_DRVGEN_EV 7 31 enum { 32 EFX_EF10_TEST = 1, 33 EFX_EF10_REFILL, 34 }; 35 36 /* VLAN list entry */ 37 struct efx_ef10_vlan { 38 struct list_head list; 39 u16 vid; 40 }; 41 42 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading); 43 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels; 44 45 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 46 { 47 efx_dword_t reg; 48 49 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 50 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 51 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 52 } 53 54 /* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for 55 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O 56 * bar; PFs use BAR 0/1 for memory. 57 */ 58 static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx) 59 { 60 switch (efx->pci_dev->device) { 61 case 0x0b03: /* SFC9250 PF */ 62 return 0; 63 default: 64 return 2; 65 } 66 } 67 68 /* All VFs use BAR 0/1 for memory */ 69 static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx) 70 { 71 return 0; 72 } 73 74 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 75 { 76 int bar; 77 78 bar = efx->type->mem_bar(efx); 79 return resource_size(&efx->pci_dev->resource[bar]); 80 } 81 82 static bool efx_ef10_is_vf(struct efx_nic *efx) 83 { 84 return efx->type->is_vf; 85 } 86 87 #ifdef CONFIG_SFC_SRIOV 88 static int efx_ef10_get_vf_index(struct efx_nic *efx) 89 { 90 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 91 struct efx_ef10_nic_data *nic_data = efx->nic_data; 92 size_t outlen; 93 int rc; 94 95 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 96 sizeof(outbuf), &outlen); 97 if (rc) 98 return rc; 99 if (outlen < sizeof(outbuf)) 100 return -EIO; 101 102 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 103 return 0; 104 } 105 #endif 106 107 static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 108 { 109 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN); 110 struct efx_ef10_nic_data *nic_data = efx->nic_data; 111 size_t outlen; 112 int rc; 113 114 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 115 116 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 117 outbuf, sizeof(outbuf), &outlen); 118 if (rc) 119 return rc; 120 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 121 netif_err(efx, drv, efx->net_dev, 122 "unable to read datapath firmware capabilities\n"); 123 return -EIO; 124 } 125 126 nic_data->datapath_caps = 127 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 128 129 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) { 130 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 131 GET_CAPABILITIES_V2_OUT_FLAGS2); 132 nic_data->piobuf_size = MCDI_WORD(outbuf, 133 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF); 134 } else { 135 nic_data->datapath_caps2 = 0; 136 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE; 137 } 138 139 /* record the DPCPU firmware IDs to determine VEB vswitching support. 140 */ 141 nic_data->rx_dpcpu_fw_id = 142 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 143 nic_data->tx_dpcpu_fw_id = 144 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 145 146 if (!(nic_data->datapath_caps & 147 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 148 netif_err(efx, probe, efx->net_dev, 149 "current firmware does not support an RX prefix\n"); 150 return -ENODEV; 151 } 152 153 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { 154 u8 vi_window_mode = MCDI_BYTE(outbuf, 155 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 156 157 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 158 if (rc) 159 return rc; 160 } else { 161 /* keep default VI stride */ 162 netif_dbg(efx, probe, efx->net_dev, 163 "firmware did not report VI window mode, assuming vi_stride = %u\n", 164 efx->vi_stride); 165 } 166 167 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 168 efx->num_mac_stats = MCDI_WORD(outbuf, 169 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 170 netif_dbg(efx, probe, efx->net_dev, 171 "firmware reports num_mac_stats = %u\n", 172 efx->num_mac_stats); 173 } else { 174 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */ 175 netif_dbg(efx, probe, efx->net_dev, 176 "firmware did not report num_mac_stats, assuming %u\n", 177 efx->num_mac_stats); 178 } 179 180 return 0; 181 } 182 183 static void efx_ef10_read_licensed_features(struct efx_nic *efx) 184 { 185 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN); 186 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN); 187 struct efx_ef10_nic_data *nic_data = efx->nic_data; 188 size_t outlen; 189 int rc; 190 191 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP, 192 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE); 193 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf), 194 outbuf, sizeof(outbuf), &outlen); 195 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN)) 196 return; 197 198 nic_data->licensed_features = MCDI_QWORD(outbuf, 199 LICENSING_V3_OUT_LICENSED_FEATURES); 200 } 201 202 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 203 { 204 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 205 int rc; 206 207 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 208 outbuf, sizeof(outbuf), NULL); 209 if (rc) 210 return rc; 211 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 212 return rc > 0 ? rc : -ERANGE; 213 } 214 215 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx) 216 { 217 struct efx_ef10_nic_data *nic_data = efx->nic_data; 218 unsigned int implemented; 219 unsigned int enabled; 220 int rc; 221 222 nic_data->workaround_35388 = false; 223 nic_data->workaround_61265 = false; 224 225 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 226 227 if (rc == -ENOSYS) { 228 /* Firmware without GET_WORKAROUNDS - not a problem. */ 229 rc = 0; 230 } else if (rc == 0) { 231 /* Bug61265 workaround is always enabled if implemented. */ 232 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265) 233 nic_data->workaround_61265 = true; 234 235 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 236 nic_data->workaround_35388 = true; 237 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 238 /* Workaround is implemented but not enabled. 239 * Try to enable it. 240 */ 241 rc = efx_mcdi_set_workaround(efx, 242 MC_CMD_WORKAROUND_BUG35388, 243 true, NULL); 244 if (rc == 0) 245 nic_data->workaround_35388 = true; 246 /* If we failed to set the workaround just carry on. */ 247 rc = 0; 248 } 249 } 250 251 netif_dbg(efx, probe, efx->net_dev, 252 "workaround for bug 35388 is %sabled\n", 253 nic_data->workaround_35388 ? "en" : "dis"); 254 netif_dbg(efx, probe, efx->net_dev, 255 "workaround for bug 61265 is %sabled\n", 256 nic_data->workaround_61265 ? "en" : "dis"); 257 258 return rc; 259 } 260 261 static void efx_ef10_process_timer_config(struct efx_nic *efx, 262 const efx_dword_t *data) 263 { 264 unsigned int max_count; 265 266 if (EFX_EF10_WORKAROUND_61265(efx)) { 267 efx->timer_quantum_ns = MCDI_DWORD(data, 268 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS); 269 efx->timer_max_ns = MCDI_DWORD(data, 270 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS); 271 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 272 efx->timer_quantum_ns = MCDI_DWORD(data, 273 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT); 274 max_count = MCDI_DWORD(data, 275 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT); 276 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 277 } else { 278 efx->timer_quantum_ns = MCDI_DWORD(data, 279 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT); 280 max_count = MCDI_DWORD(data, 281 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT); 282 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 283 } 284 285 netif_dbg(efx, probe, efx->net_dev, 286 "got timer properties from MC: quantum %u ns; max %u ns\n", 287 efx->timer_quantum_ns, efx->timer_max_ns); 288 } 289 290 static int efx_ef10_get_timer_config(struct efx_nic *efx) 291 { 292 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN); 293 int rc; 294 295 rc = efx_ef10_get_timer_workarounds(efx); 296 if (rc) 297 return rc; 298 299 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0, 300 outbuf, sizeof(outbuf), NULL); 301 302 if (rc == 0) { 303 efx_ef10_process_timer_config(efx, outbuf); 304 } else if (rc == -ENOSYS || rc == -EPERM) { 305 /* Not available - fall back to Huntington defaults. */ 306 unsigned int quantum; 307 308 rc = efx_ef10_get_sysclk_freq(efx); 309 if (rc < 0) 310 return rc; 311 312 quantum = 1536000 / rc; /* 1536 cycles */ 313 efx->timer_quantum_ns = quantum; 314 efx->timer_max_ns = efx->type->timer_period_max * quantum; 315 rc = 0; 316 } else { 317 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, 318 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN, 319 NULL, 0, rc); 320 } 321 322 return rc; 323 } 324 325 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 326 { 327 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 328 size_t outlen; 329 int rc; 330 331 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 332 333 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 334 outbuf, sizeof(outbuf), &outlen); 335 if (rc) 336 return rc; 337 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 338 return -EIO; 339 340 ether_addr_copy(mac_address, 341 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 342 return 0; 343 } 344 345 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 346 { 347 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 348 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 349 size_t outlen; 350 int num_addrs, rc; 351 352 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 353 EVB_PORT_ID_ASSIGNED); 354 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 355 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 356 357 if (rc) 358 return rc; 359 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 360 return -EIO; 361 362 num_addrs = MCDI_DWORD(outbuf, 363 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 364 365 WARN_ON(num_addrs != 1); 366 367 ether_addr_copy(mac_address, 368 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 369 370 return 0; 371 } 372 373 static ssize_t link_control_flag_show(struct device *dev, 374 struct device_attribute *attr, 375 char *buf) 376 { 377 struct efx_nic *efx = dev_get_drvdata(dev); 378 379 return sprintf(buf, "%d\n", 380 ((efx->mcdi->fn_flags) & 381 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 382 ? 1 : 0); 383 } 384 385 static ssize_t primary_flag_show(struct device *dev, 386 struct device_attribute *attr, 387 char *buf) 388 { 389 struct efx_nic *efx = dev_get_drvdata(dev); 390 391 return sprintf(buf, "%d\n", 392 ((efx->mcdi->fn_flags) & 393 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 394 ? 1 : 0); 395 } 396 397 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid) 398 { 399 struct efx_ef10_nic_data *nic_data = efx->nic_data; 400 struct efx_ef10_vlan *vlan; 401 402 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 403 404 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 405 if (vlan->vid == vid) 406 return vlan; 407 } 408 409 return NULL; 410 } 411 412 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid) 413 { 414 struct efx_ef10_nic_data *nic_data = efx->nic_data; 415 struct efx_ef10_vlan *vlan; 416 int rc; 417 418 mutex_lock(&nic_data->vlan_lock); 419 420 vlan = efx_ef10_find_vlan(efx, vid); 421 if (vlan) { 422 /* We add VID 0 on init. 8021q adds it on module init 423 * for all interfaces with VLAN filtring feature. 424 */ 425 if (vid == 0) 426 goto done_unlock; 427 netif_warn(efx, drv, efx->net_dev, 428 "VLAN %u already added\n", vid); 429 rc = -EALREADY; 430 goto fail_exist; 431 } 432 433 rc = -ENOMEM; 434 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 435 if (!vlan) 436 goto fail_alloc; 437 438 vlan->vid = vid; 439 440 list_add_tail(&vlan->list, &nic_data->vlan_list); 441 442 if (efx->filter_state) { 443 mutex_lock(&efx->mac_lock); 444 down_write(&efx->filter_sem); 445 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 446 up_write(&efx->filter_sem); 447 mutex_unlock(&efx->mac_lock); 448 if (rc) 449 goto fail_filter_add_vlan; 450 } 451 452 done_unlock: 453 mutex_unlock(&nic_data->vlan_lock); 454 return 0; 455 456 fail_filter_add_vlan: 457 list_del(&vlan->list); 458 kfree(vlan); 459 fail_alloc: 460 fail_exist: 461 mutex_unlock(&nic_data->vlan_lock); 462 return rc; 463 } 464 465 static void efx_ef10_del_vlan_internal(struct efx_nic *efx, 466 struct efx_ef10_vlan *vlan) 467 { 468 struct efx_ef10_nic_data *nic_data = efx->nic_data; 469 470 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 471 472 if (efx->filter_state) { 473 down_write(&efx->filter_sem); 474 efx_mcdi_filter_del_vlan(efx, vlan->vid); 475 up_write(&efx->filter_sem); 476 } 477 478 list_del(&vlan->list); 479 kfree(vlan); 480 } 481 482 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid) 483 { 484 struct efx_ef10_nic_data *nic_data = efx->nic_data; 485 struct efx_ef10_vlan *vlan; 486 int rc = 0; 487 488 /* 8021q removes VID 0 on module unload for all interfaces 489 * with VLAN filtering feature. We need to keep it to receive 490 * untagged traffic. 491 */ 492 if (vid == 0) 493 return 0; 494 495 mutex_lock(&nic_data->vlan_lock); 496 497 vlan = efx_ef10_find_vlan(efx, vid); 498 if (!vlan) { 499 netif_err(efx, drv, efx->net_dev, 500 "VLAN %u to be deleted not found\n", vid); 501 rc = -ENOENT; 502 } else { 503 efx_ef10_del_vlan_internal(efx, vlan); 504 } 505 506 mutex_unlock(&nic_data->vlan_lock); 507 508 return rc; 509 } 510 511 static void efx_ef10_cleanup_vlans(struct efx_nic *efx) 512 { 513 struct efx_ef10_nic_data *nic_data = efx->nic_data; 514 struct efx_ef10_vlan *vlan, *next_vlan; 515 516 mutex_lock(&nic_data->vlan_lock); 517 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list) 518 efx_ef10_del_vlan_internal(efx, vlan); 519 mutex_unlock(&nic_data->vlan_lock); 520 } 521 522 static DEVICE_ATTR_RO(link_control_flag); 523 static DEVICE_ATTR_RO(primary_flag); 524 525 static int efx_ef10_probe(struct efx_nic *efx) 526 { 527 struct efx_ef10_nic_data *nic_data; 528 int i, rc; 529 530 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 531 if (!nic_data) 532 return -ENOMEM; 533 efx->nic_data = nic_data; 534 535 /* we assume later that we can copy from this buffer in dwords */ 536 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 537 538 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 539 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 540 if (rc) 541 goto fail1; 542 543 /* Get the MC's warm boot count. In case it's rebooting right 544 * now, be prepared to retry. 545 */ 546 i = 0; 547 for (;;) { 548 rc = efx_ef10_get_warm_boot_count(efx); 549 if (rc >= 0) 550 break; 551 if (++i == 5) 552 goto fail2; 553 ssleep(1); 554 } 555 nic_data->warm_boot_count = rc; 556 557 /* In case we're recovering from a crash (kexec), we want to 558 * cancel any outstanding request by the previous user of this 559 * function. We send a special message using the least 560 * significant bits of the 'high' (doorbell) register. 561 */ 562 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 563 564 rc = efx_mcdi_init(efx); 565 if (rc) 566 goto fail2; 567 568 mutex_init(&nic_data->udp_tunnels_lock); 569 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 570 nic_data->udp_tunnels[i].type = 571 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 572 573 /* Reset (most) configuration for this function */ 574 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 575 if (rc) 576 goto fail3; 577 578 /* Enable event logging */ 579 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 580 if (rc) 581 goto fail3; 582 583 rc = device_create_file(&efx->pci_dev->dev, 584 &dev_attr_link_control_flag); 585 if (rc) 586 goto fail3; 587 588 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 589 if (rc) 590 goto fail4; 591 592 rc = efx_get_pf_index(efx, &nic_data->pf_index); 593 if (rc) 594 goto fail5; 595 596 rc = efx_ef10_init_datapath_caps(efx); 597 if (rc < 0) 598 goto fail5; 599 600 efx_ef10_read_licensed_features(efx); 601 602 /* We can have one VI for each vi_stride-byte region. 603 * However, until we use TX option descriptors we need up to four 604 * TX queues per channel for different checksumming combinations. 605 */ 606 if (nic_data->datapath_caps & 607 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)) 608 efx->tx_queues_per_channel = 4; 609 else 610 efx->tx_queues_per_channel = 2; 611 efx->max_vis = efx_ef10_mem_map_size(efx) / efx->vi_stride; 612 if (!efx->max_vis) { 613 netif_err(efx, drv, efx->net_dev, "error determining max VIs\n"); 614 rc = -EIO; 615 goto fail5; 616 } 617 efx->max_channels = min_t(unsigned int, EFX_MAX_CHANNELS, 618 efx->max_vis / efx->tx_queues_per_channel); 619 efx->max_tx_channels = efx->max_channels; 620 if (WARN_ON(efx->max_channels == 0)) { 621 rc = -EIO; 622 goto fail5; 623 } 624 625 efx->rx_packet_len_offset = 626 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 627 628 if (nic_data->datapath_caps & 629 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN)) 630 efx->net_dev->hw_features |= NETIF_F_RXFCS; 631 632 rc = efx_mcdi_port_get_number(efx); 633 if (rc < 0) 634 goto fail5; 635 efx->port_num = rc; 636 637 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 638 if (rc) 639 goto fail5; 640 641 rc = efx_ef10_get_timer_config(efx); 642 if (rc < 0) 643 goto fail5; 644 645 rc = efx_mcdi_mon_probe(efx); 646 if (rc && rc != -EPERM) 647 goto fail5; 648 649 efx_ptp_defer_probe_with_channel(efx); 650 651 #ifdef CONFIG_SFC_SRIOV 652 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 653 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 654 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 655 656 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 657 } else 658 #endif 659 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 660 661 INIT_LIST_HEAD(&nic_data->vlan_list); 662 mutex_init(&nic_data->vlan_lock); 663 664 /* Add unspecified VID to support VLAN filtering being disabled */ 665 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 666 if (rc) 667 goto fail_add_vid_unspec; 668 669 /* If VLAN filtering is enabled, we need VID 0 to get untagged 670 * traffic. It is added automatically if 8021q module is loaded, 671 * but we can't rely on it since module may be not loaded. 672 */ 673 rc = efx_ef10_add_vlan(efx, 0); 674 if (rc) 675 goto fail_add_vid_0; 676 677 if (nic_data->datapath_caps & 678 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) && 679 efx->mcdi->fn_flags & 680 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) 681 efx->net_dev->udp_tunnel_nic_info = &efx_ef10_udp_tunnels; 682 683 return 0; 684 685 fail_add_vid_0: 686 efx_ef10_cleanup_vlans(efx); 687 fail_add_vid_unspec: 688 mutex_destroy(&nic_data->vlan_lock); 689 efx_ptp_remove(efx); 690 efx_mcdi_mon_remove(efx); 691 fail5: 692 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 693 fail4: 694 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 695 fail3: 696 efx_mcdi_detach(efx); 697 698 mutex_lock(&nic_data->udp_tunnels_lock); 699 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 700 (void)efx_ef10_set_udp_tnl_ports(efx, true); 701 mutex_unlock(&nic_data->udp_tunnels_lock); 702 mutex_destroy(&nic_data->udp_tunnels_lock); 703 704 efx_mcdi_fini(efx); 705 fail2: 706 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 707 fail1: 708 kfree(nic_data); 709 efx->nic_data = NULL; 710 return rc; 711 } 712 713 #ifdef EFX_USE_PIO 714 715 static void efx_ef10_free_piobufs(struct efx_nic *efx) 716 { 717 struct efx_ef10_nic_data *nic_data = efx->nic_data; 718 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 719 unsigned int i; 720 int rc; 721 722 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 723 724 for (i = 0; i < nic_data->n_piobufs; i++) { 725 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 726 nic_data->piobuf_handle[i]); 727 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 728 NULL, 0, NULL); 729 WARN_ON(rc); 730 } 731 732 nic_data->n_piobufs = 0; 733 } 734 735 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 736 { 737 struct efx_ef10_nic_data *nic_data = efx->nic_data; 738 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 739 unsigned int i; 740 size_t outlen; 741 int rc = 0; 742 743 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 744 745 for (i = 0; i < n; i++) { 746 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 747 outbuf, sizeof(outbuf), &outlen); 748 if (rc) { 749 /* Don't display the MC error if we didn't have space 750 * for a VF. 751 */ 752 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC)) 753 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF, 754 0, outbuf, outlen, rc); 755 break; 756 } 757 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 758 rc = -EIO; 759 break; 760 } 761 nic_data->piobuf_handle[i] = 762 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 763 netif_dbg(efx, probe, efx->net_dev, 764 "allocated PIO buffer %u handle %x\n", i, 765 nic_data->piobuf_handle[i]); 766 } 767 768 nic_data->n_piobufs = i; 769 if (rc) 770 efx_ef10_free_piobufs(efx); 771 return rc; 772 } 773 774 static int efx_ef10_link_piobufs(struct efx_nic *efx) 775 { 776 struct efx_ef10_nic_data *nic_data = efx->nic_data; 777 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN); 778 struct efx_channel *channel; 779 struct efx_tx_queue *tx_queue; 780 unsigned int offset, index; 781 int rc; 782 783 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 784 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 785 786 /* Link a buffer to each VI in the write-combining mapping */ 787 for (index = 0; index < nic_data->n_piobufs; ++index) { 788 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 789 nic_data->piobuf_handle[index]); 790 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 791 nic_data->pio_write_vi_base + index); 792 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 793 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 794 NULL, 0, NULL); 795 if (rc) { 796 netif_err(efx, drv, efx->net_dev, 797 "failed to link VI %u to PIO buffer %u (%d)\n", 798 nic_data->pio_write_vi_base + index, index, 799 rc); 800 goto fail; 801 } 802 netif_dbg(efx, probe, efx->net_dev, 803 "linked VI %u to PIO buffer %u\n", 804 nic_data->pio_write_vi_base + index, index); 805 } 806 807 /* Link a buffer to each TX queue */ 808 efx_for_each_channel(channel, efx) { 809 /* Extra channels, even those with TXQs (PTP), do not require 810 * PIO resources. 811 */ 812 if (!channel->type->want_pio || 813 channel->channel >= efx->xdp_channel_offset) 814 continue; 815 816 efx_for_each_channel_tx_queue(tx_queue, channel) { 817 /* We assign the PIO buffers to queues in 818 * reverse order to allow for the following 819 * special case. 820 */ 821 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 822 tx_queue->channel->channel - 1) * 823 efx_piobuf_size); 824 index = offset / nic_data->piobuf_size; 825 offset = offset % nic_data->piobuf_size; 826 827 /* When the host page size is 4K, the first 828 * host page in the WC mapping may be within 829 * the same VI page as the last TX queue. We 830 * can only link one buffer to each VI. 831 */ 832 if (tx_queue->queue == nic_data->pio_write_vi_base) { 833 BUG_ON(index != 0); 834 rc = 0; 835 } else { 836 MCDI_SET_DWORD(inbuf, 837 LINK_PIOBUF_IN_PIOBUF_HANDLE, 838 nic_data->piobuf_handle[index]); 839 MCDI_SET_DWORD(inbuf, 840 LINK_PIOBUF_IN_TXQ_INSTANCE, 841 tx_queue->queue); 842 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 843 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 844 NULL, 0, NULL); 845 } 846 847 if (rc) { 848 /* This is non-fatal; the TX path just 849 * won't use PIO for this queue 850 */ 851 netif_err(efx, drv, efx->net_dev, 852 "failed to link VI %u to PIO buffer %u (%d)\n", 853 tx_queue->queue, index, rc); 854 tx_queue->piobuf = NULL; 855 } else { 856 tx_queue->piobuf = 857 nic_data->pio_write_base + 858 index * efx->vi_stride + offset; 859 tx_queue->piobuf_offset = offset; 860 netif_dbg(efx, probe, efx->net_dev, 861 "linked VI %u to PIO buffer %u offset %x addr %p\n", 862 tx_queue->queue, index, 863 tx_queue->piobuf_offset, 864 tx_queue->piobuf); 865 } 866 } 867 } 868 869 return 0; 870 871 fail: 872 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same 873 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter. 874 */ 875 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN); 876 while (index--) { 877 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 878 nic_data->pio_write_vi_base + index); 879 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 880 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 881 NULL, 0, NULL); 882 } 883 return rc; 884 } 885 886 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 887 { 888 struct efx_channel *channel; 889 struct efx_tx_queue *tx_queue; 890 891 /* All our existing PIO buffers went away */ 892 efx_for_each_channel(channel, efx) 893 efx_for_each_channel_tx_queue(tx_queue, channel) 894 tx_queue->piobuf = NULL; 895 } 896 897 #else /* !EFX_USE_PIO */ 898 899 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 900 { 901 return n == 0 ? 0 : -ENOBUFS; 902 } 903 904 static int efx_ef10_link_piobufs(struct efx_nic *efx) 905 { 906 return 0; 907 } 908 909 static void efx_ef10_free_piobufs(struct efx_nic *efx) 910 { 911 } 912 913 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 914 { 915 } 916 917 #endif /* EFX_USE_PIO */ 918 919 static void efx_ef10_remove(struct efx_nic *efx) 920 { 921 struct efx_ef10_nic_data *nic_data = efx->nic_data; 922 int rc; 923 924 #ifdef CONFIG_SFC_SRIOV 925 struct efx_ef10_nic_data *nic_data_pf; 926 struct pci_dev *pci_dev_pf; 927 struct efx_nic *efx_pf; 928 struct ef10_vf *vf; 929 930 if (efx->pci_dev->is_virtfn) { 931 pci_dev_pf = efx->pci_dev->physfn; 932 if (pci_dev_pf) { 933 efx_pf = pci_get_drvdata(pci_dev_pf); 934 nic_data_pf = efx_pf->nic_data; 935 vf = nic_data_pf->vf + nic_data->vf_index; 936 vf->efx = NULL; 937 } else 938 netif_info(efx, drv, efx->net_dev, 939 "Could not get the PF id from VF\n"); 940 } 941 #endif 942 943 efx_ef10_cleanup_vlans(efx); 944 mutex_destroy(&nic_data->vlan_lock); 945 946 efx_ptp_remove(efx); 947 948 efx_mcdi_mon_remove(efx); 949 950 efx_mcdi_rx_free_indir_table(efx); 951 952 if (nic_data->wc_membase) 953 iounmap(nic_data->wc_membase); 954 955 rc = efx_mcdi_free_vis(efx); 956 WARN_ON(rc != 0); 957 958 if (!nic_data->must_restore_piobufs) 959 efx_ef10_free_piobufs(efx); 960 961 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 962 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 963 964 efx_mcdi_detach(efx); 965 966 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 967 mutex_lock(&nic_data->udp_tunnels_lock); 968 (void)efx_ef10_set_udp_tnl_ports(efx, true); 969 mutex_unlock(&nic_data->udp_tunnels_lock); 970 971 mutex_destroy(&nic_data->udp_tunnels_lock); 972 973 efx_mcdi_fini(efx); 974 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 975 kfree(nic_data); 976 } 977 978 static int efx_ef10_probe_pf(struct efx_nic *efx) 979 { 980 return efx_ef10_probe(efx); 981 } 982 983 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id, 984 u32 *port_flags, u32 *vadaptor_flags, 985 unsigned int *vlan_tags) 986 { 987 struct efx_ef10_nic_data *nic_data = efx->nic_data; 988 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN); 989 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN); 990 size_t outlen; 991 int rc; 992 993 if (nic_data->datapath_caps & 994 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) { 995 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID, 996 port_id); 997 998 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf), 999 outbuf, sizeof(outbuf), &outlen); 1000 if (rc) 1001 return rc; 1002 1003 if (outlen < sizeof(outbuf)) { 1004 rc = -EIO; 1005 return rc; 1006 } 1007 } 1008 1009 if (port_flags) 1010 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS); 1011 if (vadaptor_flags) 1012 *vadaptor_flags = 1013 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS); 1014 if (vlan_tags) 1015 *vlan_tags = 1016 MCDI_DWORD(outbuf, 1017 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS); 1018 1019 return 0; 1020 } 1021 1022 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 1023 { 1024 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 1025 1026 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 1027 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 1028 NULL, 0, NULL); 1029 } 1030 1031 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 1032 { 1033 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 1034 1035 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 1036 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 1037 NULL, 0, NULL); 1038 } 1039 1040 int efx_ef10_vport_add_mac(struct efx_nic *efx, 1041 unsigned int port_id, const u8 *mac) 1042 { 1043 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 1044 1045 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 1046 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 1047 1048 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 1049 sizeof(inbuf), NULL, 0, NULL); 1050 } 1051 1052 int efx_ef10_vport_del_mac(struct efx_nic *efx, 1053 unsigned int port_id, const u8 *mac) 1054 { 1055 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 1056 1057 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 1058 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 1059 1060 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 1061 sizeof(inbuf), NULL, 0, NULL); 1062 } 1063 1064 #ifdef CONFIG_SFC_SRIOV 1065 static int efx_ef10_probe_vf(struct efx_nic *efx) 1066 { 1067 int rc; 1068 struct pci_dev *pci_dev_pf; 1069 1070 /* If the parent PF has no VF data structure, it doesn't know about this 1071 * VF so fail probe. The VF needs to be re-created. This can happen 1072 * if the PF driver was unloaded while any VF was assigned to a guest 1073 * (using Xen, only). 1074 */ 1075 pci_dev_pf = efx->pci_dev->physfn; 1076 if (pci_dev_pf) { 1077 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 1078 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 1079 1080 if (!nic_data_pf->vf) { 1081 netif_info(efx, drv, efx->net_dev, 1082 "The VF cannot link to its parent PF; " 1083 "please destroy and re-create the VF\n"); 1084 return -EBUSY; 1085 } 1086 } 1087 1088 rc = efx_ef10_probe(efx); 1089 if (rc) 1090 return rc; 1091 1092 rc = efx_ef10_get_vf_index(efx); 1093 if (rc) 1094 goto fail; 1095 1096 if (efx->pci_dev->is_virtfn) { 1097 if (efx->pci_dev->physfn) { 1098 struct efx_nic *efx_pf = 1099 pci_get_drvdata(efx->pci_dev->physfn); 1100 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 1101 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1102 1103 nic_data_p->vf[nic_data->vf_index].efx = efx; 1104 nic_data_p->vf[nic_data->vf_index].pci_dev = 1105 efx->pci_dev; 1106 } else 1107 netif_info(efx, drv, efx->net_dev, 1108 "Could not get the PF id from VF\n"); 1109 } 1110 1111 return 0; 1112 1113 fail: 1114 efx_ef10_remove(efx); 1115 return rc; 1116 } 1117 #else 1118 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 1119 { 1120 return 0; 1121 } 1122 #endif 1123 1124 static int efx_ef10_alloc_vis(struct efx_nic *efx, 1125 unsigned int min_vis, unsigned int max_vis) 1126 { 1127 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1128 1129 return efx_mcdi_alloc_vis(efx, min_vis, max_vis, &nic_data->vi_base, 1130 &nic_data->n_allocated_vis); 1131 } 1132 1133 /* Note that the failure path of this function does not free 1134 * resources, as this will be done by efx_ef10_remove(). 1135 */ 1136 static int efx_ef10_dimension_resources(struct efx_nic *efx) 1137 { 1138 unsigned int min_vis = max_t(unsigned int, efx->tx_queues_per_channel, 1139 efx_separate_tx_channels ? 2 : 1); 1140 unsigned int channel_vis, pio_write_vi_base, max_vis; 1141 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1142 unsigned int uc_mem_map_size, wc_mem_map_size; 1143 void __iomem *membase; 1144 int rc; 1145 1146 channel_vis = max(efx->n_channels, 1147 ((efx->n_tx_channels + efx->n_extra_tx_channels) * 1148 efx->tx_queues_per_channel) + 1149 efx->n_xdp_channels * efx->xdp_tx_per_channel); 1150 if (efx->max_vis && efx->max_vis < channel_vis) { 1151 netif_dbg(efx, drv, efx->net_dev, 1152 "Reducing channel VIs from %u to %u\n", 1153 channel_vis, efx->max_vis); 1154 channel_vis = efx->max_vis; 1155 } 1156 1157 #ifdef EFX_USE_PIO 1158 /* Try to allocate PIO buffers if wanted and if the full 1159 * number of PIO buffers would be sufficient to allocate one 1160 * copy-buffer per TX channel. Failure is non-fatal, as there 1161 * are only a small number of PIO buffers shared between all 1162 * functions of the controller. 1163 */ 1164 if (efx_piobuf_size != 0 && 1165 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 1166 efx->n_tx_channels) { 1167 unsigned int n_piobufs = 1168 DIV_ROUND_UP(efx->n_tx_channels, 1169 nic_data->piobuf_size / efx_piobuf_size); 1170 1171 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 1172 if (rc == -ENOSPC) 1173 netif_dbg(efx, probe, efx->net_dev, 1174 "out of PIO buffers; cannot allocate more\n"); 1175 else if (rc == -EPERM) 1176 netif_dbg(efx, probe, efx->net_dev, 1177 "not permitted to allocate PIO buffers\n"); 1178 else if (rc) 1179 netif_err(efx, probe, efx->net_dev, 1180 "failed to allocate PIO buffers (%d)\n", rc); 1181 else 1182 netif_dbg(efx, probe, efx->net_dev, 1183 "allocated %u PIO buffers\n", n_piobufs); 1184 } 1185 #else 1186 nic_data->n_piobufs = 0; 1187 #endif 1188 1189 /* PIO buffers should be mapped with write-combining enabled, 1190 * and we want to make single UC and WC mappings rather than 1191 * several of each (in fact that's the only option if host 1192 * page size is >4K). So we may allocate some extra VIs just 1193 * for writing PIO buffers through. 1194 * 1195 * The UC mapping contains (channel_vis - 1) complete VIs and the 1196 * first 4K of the next VI. Then the WC mapping begins with 1197 * the remainder of this last VI. 1198 */ 1199 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride + 1200 ER_DZ_TX_PIOBUF); 1201 if (nic_data->n_piobufs) { 1202 /* pio_write_vi_base rounds down to give the number of complete 1203 * VIs inside the UC mapping. 1204 */ 1205 pio_write_vi_base = uc_mem_map_size / efx->vi_stride; 1206 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 1207 nic_data->n_piobufs) * 1208 efx->vi_stride) - 1209 uc_mem_map_size); 1210 max_vis = pio_write_vi_base + nic_data->n_piobufs; 1211 } else { 1212 pio_write_vi_base = 0; 1213 wc_mem_map_size = 0; 1214 max_vis = channel_vis; 1215 } 1216 1217 /* In case the last attached driver failed to free VIs, do it now */ 1218 rc = efx_mcdi_free_vis(efx); 1219 if (rc != 0) 1220 return rc; 1221 1222 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 1223 if (rc != 0) 1224 return rc; 1225 1226 if (nic_data->n_allocated_vis < channel_vis) { 1227 netif_info(efx, drv, efx->net_dev, 1228 "Could not allocate enough VIs to satisfy RSS" 1229 " requirements. Performance may not be optimal.\n"); 1230 /* We didn't get the VIs to populate our channels. 1231 * We could keep what we got but then we'd have more 1232 * interrupts than we need. 1233 * Instead calculate new max_channels and restart 1234 */ 1235 efx->max_channels = nic_data->n_allocated_vis; 1236 efx->max_tx_channels = 1237 nic_data->n_allocated_vis / efx->tx_queues_per_channel; 1238 1239 efx_mcdi_free_vis(efx); 1240 return -EAGAIN; 1241 } 1242 1243 /* If we didn't get enough VIs to map all the PIO buffers, free the 1244 * PIO buffers 1245 */ 1246 if (nic_data->n_piobufs && 1247 nic_data->n_allocated_vis < 1248 pio_write_vi_base + nic_data->n_piobufs) { 1249 netif_dbg(efx, probe, efx->net_dev, 1250 "%u VIs are not sufficient to map %u PIO buffers\n", 1251 nic_data->n_allocated_vis, nic_data->n_piobufs); 1252 efx_ef10_free_piobufs(efx); 1253 } 1254 1255 /* Shrink the original UC mapping of the memory BAR */ 1256 membase = ioremap(efx->membase_phys, uc_mem_map_size); 1257 if (!membase) { 1258 netif_err(efx, probe, efx->net_dev, 1259 "could not shrink memory BAR to %x\n", 1260 uc_mem_map_size); 1261 return -ENOMEM; 1262 } 1263 iounmap(efx->membase); 1264 efx->membase = membase; 1265 1266 /* Set up the WC mapping if needed */ 1267 if (wc_mem_map_size) { 1268 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 1269 uc_mem_map_size, 1270 wc_mem_map_size); 1271 if (!nic_data->wc_membase) { 1272 netif_err(efx, probe, efx->net_dev, 1273 "could not allocate WC mapping of size %x\n", 1274 wc_mem_map_size); 1275 return -ENOMEM; 1276 } 1277 nic_data->pio_write_vi_base = pio_write_vi_base; 1278 nic_data->pio_write_base = 1279 nic_data->wc_membase + 1280 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF - 1281 uc_mem_map_size); 1282 1283 rc = efx_ef10_link_piobufs(efx); 1284 if (rc) 1285 efx_ef10_free_piobufs(efx); 1286 } 1287 1288 netif_dbg(efx, probe, efx->net_dev, 1289 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 1290 &efx->membase_phys, efx->membase, uc_mem_map_size, 1291 nic_data->wc_membase, wc_mem_map_size); 1292 1293 return 0; 1294 } 1295 1296 static void efx_ef10_fini_nic(struct efx_nic *efx) 1297 { 1298 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1299 1300 kfree(nic_data->mc_stats); 1301 nic_data->mc_stats = NULL; 1302 } 1303 1304 static int efx_ef10_init_nic(struct efx_nic *efx) 1305 { 1306 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1307 netdev_features_t hw_enc_features = 0; 1308 int rc; 1309 1310 if (nic_data->must_check_datapath_caps) { 1311 rc = efx_ef10_init_datapath_caps(efx); 1312 if (rc) 1313 return rc; 1314 nic_data->must_check_datapath_caps = false; 1315 } 1316 1317 if (efx->must_realloc_vis) { 1318 /* We cannot let the number of VIs change now */ 1319 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 1320 nic_data->n_allocated_vis); 1321 if (rc) 1322 return rc; 1323 efx->must_realloc_vis = false; 1324 } 1325 1326 nic_data->mc_stats = kmalloc(efx->num_mac_stats * sizeof(__le64), 1327 GFP_KERNEL); 1328 if (!nic_data->mc_stats) 1329 return -ENOMEM; 1330 1331 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 1332 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 1333 if (rc == 0) { 1334 rc = efx_ef10_link_piobufs(efx); 1335 if (rc) 1336 efx_ef10_free_piobufs(efx); 1337 } 1338 1339 /* Log an error on failure, but this is non-fatal. 1340 * Permission errors are less important - we've presumably 1341 * had the PIO buffer licence removed. 1342 */ 1343 if (rc == -EPERM) 1344 netif_dbg(efx, drv, efx->net_dev, 1345 "not permitted to restore PIO buffers\n"); 1346 else if (rc) 1347 netif_err(efx, drv, efx->net_dev, 1348 "failed to restore PIO buffers (%d)\n", rc); 1349 nic_data->must_restore_piobufs = false; 1350 } 1351 1352 /* add encapsulated checksum offload features */ 1353 if (efx_has_cap(efx, VXLAN_NVGRE) && !efx_ef10_is_vf(efx)) 1354 hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1355 /* add encapsulated TSO features */ 1356 if (efx_has_cap(efx, TX_TSO_V2_ENCAP)) { 1357 netdev_features_t encap_tso_features; 1358 1359 encap_tso_features = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 1360 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM; 1361 1362 hw_enc_features |= encap_tso_features | NETIF_F_TSO; 1363 efx->net_dev->features |= encap_tso_features; 1364 } 1365 efx->net_dev->hw_enc_features = hw_enc_features; 1366 1367 /* don't fail init if RSS setup doesn't work */ 1368 rc = efx->type->rx_push_rss_config(efx, false, 1369 efx->rss_context.rx_indir_table, NULL); 1370 1371 return 0; 1372 } 1373 1374 static void efx_ef10_table_reset_mc_allocations(struct efx_nic *efx) 1375 { 1376 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1377 #ifdef CONFIG_SFC_SRIOV 1378 unsigned int i; 1379 #endif 1380 1381 /* All our allocations have been reset */ 1382 efx->must_realloc_vis = true; 1383 efx_mcdi_filter_table_reset_mc_allocations(efx); 1384 nic_data->must_restore_piobufs = true; 1385 efx_ef10_forget_old_piobufs(efx); 1386 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID; 1387 1388 /* Driver-created vswitches and vports must be re-created */ 1389 nic_data->must_probe_vswitching = true; 1390 efx->vport_id = EVB_PORT_ID_ASSIGNED; 1391 #ifdef CONFIG_SFC_SRIOV 1392 if (nic_data->vf) 1393 for (i = 0; i < efx->vf_count; i++) 1394 nic_data->vf[i].vport_id = 0; 1395 #endif 1396 } 1397 1398 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1399 { 1400 if (reason == RESET_TYPE_MC_FAILURE) 1401 return RESET_TYPE_DATAPATH; 1402 1403 return efx_mcdi_map_reset_reason(reason); 1404 } 1405 1406 static int efx_ef10_map_reset_flags(u32 *flags) 1407 { 1408 enum { 1409 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1410 ETH_RESET_SHARED_SHIFT), 1411 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1412 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1413 ETH_RESET_PHY | ETH_RESET_MGMT) << 1414 ETH_RESET_SHARED_SHIFT) 1415 }; 1416 1417 /* We assume for now that our PCI function is permitted to 1418 * reset everything. 1419 */ 1420 1421 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1422 *flags &= ~EF10_RESET_MC; 1423 return RESET_TYPE_WORLD; 1424 } 1425 1426 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1427 *flags &= ~EF10_RESET_PORT; 1428 return RESET_TYPE_ALL; 1429 } 1430 1431 /* no invisible reset implemented */ 1432 1433 return -EINVAL; 1434 } 1435 1436 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1437 { 1438 int rc = efx_mcdi_reset(efx, reset_type); 1439 1440 /* Unprivileged functions return -EPERM, but need to return success 1441 * here so that the datapath is brought back up. 1442 */ 1443 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1444 rc = 0; 1445 1446 /* If it was a port reset, trigger reallocation of MC resources. 1447 * Note that on an MC reset nothing needs to be done now because we'll 1448 * detect the MC reset later and handle it then. 1449 * For an FLR, we never get an MC reset event, but the MC has reset all 1450 * resources assigned to us, so we have to trigger reallocation now. 1451 */ 1452 if ((reset_type == RESET_TYPE_ALL || 1453 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1454 efx_ef10_table_reset_mc_allocations(efx); 1455 return rc; 1456 } 1457 1458 #define EF10_DMA_STAT(ext_name, mcdi_name) \ 1459 [EF10_STAT_ ## ext_name] = \ 1460 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1461 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1462 [EF10_STAT_ ## int_name] = \ 1463 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1464 #define EF10_OTHER_STAT(ext_name) \ 1465 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1466 1467 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1468 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1469 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1470 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1471 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1472 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1473 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1474 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1475 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1476 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1477 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1478 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1479 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1480 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1481 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1482 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1483 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1484 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1485 EF10_OTHER_STAT(port_rx_good_bytes), 1486 EF10_OTHER_STAT(port_rx_bad_bytes), 1487 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1488 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1489 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1490 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1491 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1492 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1493 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1494 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1495 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1496 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1497 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1498 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1499 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1500 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1501 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1502 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1503 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1504 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1505 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1506 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1507 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1508 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1509 EFX_GENERIC_SW_STAT(rx_nodesc_trunc), 1510 EFX_GENERIC_SW_STAT(rx_noskb_drops), 1511 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1512 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1513 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1514 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1515 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1516 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1517 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1518 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1519 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1520 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1521 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1522 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1523 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1524 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1525 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1526 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1527 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1528 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1529 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1530 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1531 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1532 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1533 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1534 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1535 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1536 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1537 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1538 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1539 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1540 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1541 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS), 1542 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS), 1543 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0), 1544 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1), 1545 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2), 1546 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3), 1547 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK), 1548 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS), 1549 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL), 1550 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL), 1551 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL), 1552 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL), 1553 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL), 1554 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL), 1555 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL), 1556 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK), 1557 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK), 1558 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK), 1559 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS), 1560 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK), 1561 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON), 1562 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE), 1563 }; 1564 1565 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1566 (1ULL << EF10_STAT_port_tx_packets) | \ 1567 (1ULL << EF10_STAT_port_tx_pause) | \ 1568 (1ULL << EF10_STAT_port_tx_unicast) | \ 1569 (1ULL << EF10_STAT_port_tx_multicast) | \ 1570 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1571 (1ULL << EF10_STAT_port_rx_bytes) | \ 1572 (1ULL << \ 1573 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1574 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1575 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1576 (1ULL << EF10_STAT_port_rx_packets) | \ 1577 (1ULL << EF10_STAT_port_rx_good) | \ 1578 (1ULL << EF10_STAT_port_rx_bad) | \ 1579 (1ULL << EF10_STAT_port_rx_pause) | \ 1580 (1ULL << EF10_STAT_port_rx_control) | \ 1581 (1ULL << EF10_STAT_port_rx_unicast) | \ 1582 (1ULL << EF10_STAT_port_rx_multicast) | \ 1583 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1584 (1ULL << EF10_STAT_port_rx_lt64) | \ 1585 (1ULL << EF10_STAT_port_rx_64) | \ 1586 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1587 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1588 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1589 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1590 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1591 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1592 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1593 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1594 (1ULL << EF10_STAT_port_rx_overflow) | \ 1595 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1596 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1597 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1598 1599 /* On 7000 series NICs, these statistics are only provided by the 10G MAC. 1600 * For a 10G/40G switchable port we do not expose these because they might 1601 * not include all the packets they should. 1602 * On 8000 series NICs these statistics are always provided. 1603 */ 1604 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1605 (1ULL << EF10_STAT_port_tx_lt64) | \ 1606 (1ULL << EF10_STAT_port_tx_64) | \ 1607 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1608 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1609 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1610 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1611 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1612 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1613 1614 /* These statistics are only provided by the 40G MAC. For a 10G/40G 1615 * switchable port we do expose these because the errors will otherwise 1616 * be silent. 1617 */ 1618 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1619 (1ULL << EF10_STAT_port_rx_length_error)) 1620 1621 /* These statistics are only provided if the firmware supports the 1622 * capability PM_AND_RXDP_COUNTERS. 1623 */ 1624 #define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1625 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1626 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1627 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1628 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1629 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1630 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1631 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1632 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1633 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1634 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1635 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1636 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1637 1638 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2, 1639 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in 1640 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1641 * These bits are in the second u64 of the raw mask. 1642 */ 1643 #define EF10_FEC_STAT_MASK ( \ 1644 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \ 1645 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \ 1646 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \ 1647 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \ 1648 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \ 1649 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64))) 1650 1651 /* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3, 1652 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in 1653 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1654 * These bits are in the second u64 of the raw mask. 1655 */ 1656 #define EF10_CTPIO_STAT_MASK ( \ 1657 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \ 1658 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \ 1659 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \ 1660 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \ 1661 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \ 1662 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \ 1663 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \ 1664 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \ 1665 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \ 1666 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \ 1667 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \ 1668 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \ 1669 (1ULL << (EF10_STAT_ctpio_success - 64)) | \ 1670 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \ 1671 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \ 1672 (1ULL << (EF10_STAT_ctpio_erase - 64))) 1673 1674 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1675 { 1676 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1677 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1678 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1679 1680 if (!(efx->mcdi->fn_flags & 1681 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1682 return 0; 1683 1684 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) { 1685 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1686 /* 8000 series have everything even at 40G */ 1687 if (nic_data->datapath_caps2 & 1688 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN)) 1689 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1690 } else { 1691 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1692 } 1693 1694 if (nic_data->datapath_caps & 1695 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1696 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1697 1698 return raw_mask; 1699 } 1700 1701 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1702 { 1703 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1704 u64 raw_mask[2]; 1705 1706 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1707 1708 /* Only show vadaptor stats when EVB capability is present */ 1709 if (nic_data->datapath_caps & 1710 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1711 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1712 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1; 1713 } else { 1714 raw_mask[1] = 0; 1715 } 1716 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */ 1717 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2) 1718 raw_mask[1] |= EF10_FEC_STAT_MASK; 1719 1720 /* CTPIO stats appear in V3. Only show them on devices that actually 1721 * support CTPIO. Although this driver doesn't use CTPIO others might, 1722 * and we may be reporting the stats for the underlying port. 1723 */ 1724 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 && 1725 (nic_data->datapath_caps2 & 1726 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN))) 1727 raw_mask[1] |= EF10_CTPIO_STAT_MASK; 1728 1729 #if BITS_PER_LONG == 64 1730 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2); 1731 mask[0] = raw_mask[0]; 1732 mask[1] = raw_mask[1]; 1733 #else 1734 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3); 1735 mask[0] = raw_mask[0] & 0xffffffff; 1736 mask[1] = raw_mask[0] >> 32; 1737 mask[2] = raw_mask[1] & 0xffffffff; 1738 #endif 1739 } 1740 1741 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1742 { 1743 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1744 1745 efx_ef10_get_stat_mask(efx, mask); 1746 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1747 mask, names); 1748 } 1749 1750 static void efx_ef10_get_fec_stats(struct efx_nic *efx, 1751 struct ethtool_fec_stats *fec_stats) 1752 { 1753 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1754 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1755 u64 *stats = nic_data->stats; 1756 1757 efx_ef10_get_stat_mask(efx, mask); 1758 if (test_bit(EF10_STAT_fec_corrected_errors, mask)) 1759 fec_stats->corrected_blocks.total = 1760 stats[EF10_STAT_fec_corrected_errors]; 1761 if (test_bit(EF10_STAT_fec_uncorrected_errors, mask)) 1762 fec_stats->uncorrectable_blocks.total = 1763 stats[EF10_STAT_fec_uncorrected_errors]; 1764 } 1765 1766 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1767 struct rtnl_link_stats64 *core_stats) 1768 { 1769 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1770 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1771 u64 *stats = nic_data->stats; 1772 size_t stats_count = 0, index; 1773 1774 efx_ef10_get_stat_mask(efx, mask); 1775 1776 if (full_stats) { 1777 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1778 if (efx_ef10_stat_desc[index].name) { 1779 *full_stats++ = stats[index]; 1780 ++stats_count; 1781 } 1782 } 1783 } 1784 1785 if (!core_stats) 1786 return stats_count; 1787 1788 if (nic_data->datapath_caps & 1789 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1790 /* Use vadaptor stats. */ 1791 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1792 stats[EF10_STAT_rx_multicast] + 1793 stats[EF10_STAT_rx_broadcast]; 1794 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1795 stats[EF10_STAT_tx_multicast] + 1796 stats[EF10_STAT_tx_broadcast]; 1797 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1798 stats[EF10_STAT_rx_multicast_bytes] + 1799 stats[EF10_STAT_rx_broadcast_bytes]; 1800 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1801 stats[EF10_STAT_tx_multicast_bytes] + 1802 stats[EF10_STAT_tx_broadcast_bytes]; 1803 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1804 stats[GENERIC_STAT_rx_noskb_drops]; 1805 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1806 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1807 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1808 core_stats->rx_errors = core_stats->rx_crc_errors; 1809 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1810 } else { 1811 /* Use port stats. */ 1812 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1813 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1814 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1815 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1816 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1817 stats[GENERIC_STAT_rx_nodesc_trunc] + 1818 stats[GENERIC_STAT_rx_noskb_drops]; 1819 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1820 core_stats->rx_length_errors = 1821 stats[EF10_STAT_port_rx_gtjumbo] + 1822 stats[EF10_STAT_port_rx_length_error]; 1823 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1824 core_stats->rx_frame_errors = 1825 stats[EF10_STAT_port_rx_align_error]; 1826 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1827 core_stats->rx_errors = (core_stats->rx_length_errors + 1828 core_stats->rx_crc_errors + 1829 core_stats->rx_frame_errors); 1830 } 1831 1832 return stats_count; 1833 } 1834 1835 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1836 struct rtnl_link_stats64 *core_stats) 1837 { 1838 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1839 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1840 u64 *stats = nic_data->stats; 1841 1842 efx_ef10_get_stat_mask(efx, mask); 1843 1844 efx_nic_copy_stats(efx, nic_data->mc_stats); 1845 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1846 mask, stats, nic_data->mc_stats, false); 1847 1848 /* Update derived statistics */ 1849 efx_nic_fix_nodesc_drop_stat(efx, 1850 &stats[EF10_STAT_port_rx_nodesc_drops]); 1851 /* MC Firmware reads RX_BYTES and RX_GOOD_BYTES from the MAC. 1852 * It then calculates RX_BAD_BYTES and DMAs it to us with RX_BYTES. 1853 * We report these as port_rx_ stats. We are not given RX_GOOD_BYTES. 1854 * Here we calculate port_rx_good_bytes. 1855 */ 1856 stats[EF10_STAT_port_rx_good_bytes] = 1857 stats[EF10_STAT_port_rx_bytes] - 1858 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1859 1860 /* The asynchronous reads used to calculate RX_BAD_BYTES in 1861 * MC Firmware are done such that we should not see an increase in 1862 * RX_BAD_BYTES when a good packet has arrived. Unfortunately this 1863 * does mean that the stat can decrease at times. Here we do not 1864 * update the stat unless it has increased or has gone to zero 1865 * (In the case of the NIC rebooting). 1866 * Please see Bug 33781 for a discussion of why things work this way. 1867 */ 1868 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1869 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1870 efx_update_sw_stats(efx, stats); 1871 1872 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1873 } 1874 1875 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1876 __must_hold(&efx->stats_lock) 1877 { 1878 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1879 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1880 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1881 __le64 generation_start, generation_end; 1882 u64 *stats = nic_data->stats; 1883 u32 dma_len = efx->num_mac_stats * sizeof(u64); 1884 struct efx_buffer stats_buf; 1885 __le64 *dma_stats; 1886 int rc; 1887 1888 spin_unlock_bh(&efx->stats_lock); 1889 1890 efx_ef10_get_stat_mask(efx, mask); 1891 1892 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_KERNEL); 1893 if (rc) { 1894 spin_lock_bh(&efx->stats_lock); 1895 return rc; 1896 } 1897 1898 dma_stats = stats_buf.addr; 1899 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID; 1900 1901 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1902 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1903 MAC_STATS_IN_DMA, 1); 1904 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1905 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1906 1907 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1908 NULL, 0, NULL); 1909 spin_lock_bh(&efx->stats_lock); 1910 if (rc) { 1911 /* Expect ENOENT if DMA queues have not been set up */ 1912 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1913 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1914 sizeof(inbuf), NULL, 0, rc); 1915 goto out; 1916 } 1917 1918 generation_end = dma_stats[efx->num_mac_stats - 1]; 1919 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1920 WARN_ON_ONCE(1); 1921 goto out; 1922 } 1923 rmb(); 1924 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1925 stats, stats_buf.addr, false); 1926 rmb(); 1927 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1928 if (generation_end != generation_start) { 1929 rc = -EAGAIN; 1930 goto out; 1931 } 1932 1933 efx_update_sw_stats(efx, stats); 1934 out: 1935 /* releasing a DMA coherent buffer with BH disabled can panic */ 1936 spin_unlock_bh(&efx->stats_lock); 1937 efx_nic_free_buffer(efx, &stats_buf); 1938 spin_lock_bh(&efx->stats_lock); 1939 return rc; 1940 } 1941 1942 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1943 struct rtnl_link_stats64 *core_stats) 1944 { 1945 if (efx_ef10_try_update_nic_stats_vf(efx)) 1946 return 0; 1947 1948 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1949 } 1950 1951 static size_t efx_ef10_update_stats_atomic_vf(struct efx_nic *efx, u64 *full_stats, 1952 struct rtnl_link_stats64 *core_stats) 1953 { 1954 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1955 1956 /* In atomic context, cannot update HW stats. Just update the 1957 * software stats and return so the caller can continue. 1958 */ 1959 efx_update_sw_stats(efx, nic_data->stats); 1960 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1961 } 1962 1963 static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1964 { 1965 struct efx_nic *efx = channel->efx; 1966 unsigned int mode, usecs; 1967 efx_dword_t timer_cmd; 1968 1969 if (channel->irq_moderation_us) { 1970 mode = 3; 1971 usecs = channel->irq_moderation_us; 1972 } else { 1973 mode = 0; 1974 usecs = 0; 1975 } 1976 1977 if (EFX_EF10_WORKAROUND_61265(efx)) { 1978 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN); 1979 unsigned int ns = usecs * 1000; 1980 1981 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE, 1982 channel->channel); 1983 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns); 1984 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns); 1985 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode); 1986 1987 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR, 1988 inbuf, sizeof(inbuf), 0, NULL, 0); 1989 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 1990 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1991 1992 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1993 EFE_DD_EVQ_IND_TIMER_FLAGS, 1994 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1995 ERF_DD_EVQ_IND_TIMER_VAL, ticks); 1996 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1997 channel->channel); 1998 } else { 1999 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 2000 2001 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 2002 ERF_DZ_TC_TIMER_VAL, ticks, 2003 ERF_FZ_TC_TMR_REL_VAL, ticks); 2004 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 2005 channel->channel); 2006 } 2007 } 2008 2009 static void efx_ef10_get_wol_vf(struct efx_nic *efx, 2010 struct ethtool_wolinfo *wol) {} 2011 2012 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 2013 { 2014 return -EOPNOTSUPP; 2015 } 2016 2017 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 2018 { 2019 wol->supported = 0; 2020 wol->wolopts = 0; 2021 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2022 } 2023 2024 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 2025 { 2026 if (type != 0) 2027 return -EINVAL; 2028 return 0; 2029 } 2030 2031 static void efx_ef10_mcdi_request(struct efx_nic *efx, 2032 const efx_dword_t *hdr, size_t hdr_len, 2033 const efx_dword_t *sdu, size_t sdu_len) 2034 { 2035 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2036 u8 *pdu = nic_data->mcdi_buf.addr; 2037 2038 memcpy(pdu, hdr, hdr_len); 2039 memcpy(pdu + hdr_len, sdu, sdu_len); 2040 wmb(); 2041 2042 /* The hardware provides 'low' and 'high' (doorbell) registers 2043 * for passing the 64-bit address of an MCDI request to 2044 * firmware. However the dwords are swapped by firmware. The 2045 * least significant bits of the doorbell are then 0 for all 2046 * MCDI requests due to alignment. 2047 */ 2048 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 2049 ER_DZ_MC_DB_LWRD); 2050 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 2051 ER_DZ_MC_DB_HWRD); 2052 } 2053 2054 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 2055 { 2056 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2057 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 2058 2059 rmb(); 2060 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 2061 } 2062 2063 static void 2064 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 2065 size_t offset, size_t outlen) 2066 { 2067 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2068 const u8 *pdu = nic_data->mcdi_buf.addr; 2069 2070 memcpy(outbuf, pdu + offset, outlen); 2071 } 2072 2073 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 2074 { 2075 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2076 2077 /* All our allocations have been reset */ 2078 efx_ef10_table_reset_mc_allocations(efx); 2079 2080 /* The datapath firmware might have been changed */ 2081 nic_data->must_check_datapath_caps = true; 2082 2083 /* MAC statistics have been cleared on the NIC; clear the local 2084 * statistic that we update with efx_update_diff_stat(). 2085 */ 2086 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 2087 } 2088 2089 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 2090 { 2091 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2092 int rc; 2093 2094 rc = efx_ef10_get_warm_boot_count(efx); 2095 if (rc < 0) { 2096 /* The firmware is presumably in the process of 2097 * rebooting. However, we are supposed to report each 2098 * reboot just once, so we must only do that once we 2099 * can read and store the updated warm boot count. 2100 */ 2101 return 0; 2102 } 2103 2104 if (rc == nic_data->warm_boot_count) 2105 return 0; 2106 2107 nic_data->warm_boot_count = rc; 2108 efx_ef10_mcdi_reboot_detected(efx); 2109 2110 return -EIO; 2111 } 2112 2113 /* Handle an MSI interrupt 2114 * 2115 * Handle an MSI hardware interrupt. This routine schedules event 2116 * queue processing. No interrupt acknowledgement cycle is necessary. 2117 * Also, we never need to check that the interrupt is for us, since 2118 * MSI interrupts cannot be shared. 2119 */ 2120 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 2121 { 2122 struct efx_msi_context *context = dev_id; 2123 struct efx_nic *efx = context->efx; 2124 2125 netif_vdbg(efx, intr, efx->net_dev, 2126 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 2127 2128 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 2129 /* Note test interrupts */ 2130 if (context->index == efx->irq_level) 2131 efx->last_irq_cpu = raw_smp_processor_id(); 2132 2133 /* Schedule processing of the channel */ 2134 efx_schedule_channel_irq(efx->channel[context->index]); 2135 } 2136 2137 return IRQ_HANDLED; 2138 } 2139 2140 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 2141 { 2142 struct efx_nic *efx = dev_id; 2143 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled); 2144 struct efx_channel *channel; 2145 efx_dword_t reg; 2146 u32 queues; 2147 2148 /* Read the ISR which also ACKs the interrupts */ 2149 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 2150 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 2151 2152 if (queues == 0) 2153 return IRQ_NONE; 2154 2155 if (likely(soft_enabled)) { 2156 /* Note test interrupts */ 2157 if (queues & (1U << efx->irq_level)) 2158 efx->last_irq_cpu = raw_smp_processor_id(); 2159 2160 efx_for_each_channel(channel, efx) { 2161 if (queues & 1) 2162 efx_schedule_channel_irq(channel); 2163 queues >>= 1; 2164 } 2165 } 2166 2167 netif_vdbg(efx, intr, efx->net_dev, 2168 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 2169 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 2170 2171 return IRQ_HANDLED; 2172 } 2173 2174 static int efx_ef10_irq_test_generate(struct efx_nic *efx) 2175 { 2176 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 2177 2178 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true, 2179 NULL) == 0) 2180 return -ENOTSUPP; 2181 2182 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 2183 2184 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 2185 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 2186 inbuf, sizeof(inbuf), NULL, 0, NULL); 2187 } 2188 2189 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 2190 { 2191 /* low two bits of label are what we want for type */ 2192 BUILD_BUG_ON((EFX_TXQ_TYPE_OUTER_CSUM | EFX_TXQ_TYPE_INNER_CSUM) != 3); 2193 tx_queue->type = tx_queue->label & 3; 2194 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 2195 (tx_queue->ptr_mask + 1) * 2196 sizeof(efx_qword_t), 2197 GFP_KERNEL); 2198 } 2199 2200 /* This writes to the TX_DESC_WPTR and also pushes data */ 2201 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 2202 const efx_qword_t *txd) 2203 { 2204 unsigned int write_ptr; 2205 efx_oword_t reg; 2206 2207 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2208 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 2209 reg.qword[0] = *txd; 2210 efx_writeo_page(tx_queue->efx, ®, 2211 ER_DZ_TX_DESC_UPD, tx_queue->queue); 2212 } 2213 2214 /* Add Firmware-Assisted TSO v2 option descriptors to a queue. 2215 */ 2216 int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 2217 bool *data_mapped) 2218 { 2219 struct efx_tx_buffer *buffer; 2220 u16 inner_ipv4_id = 0; 2221 u16 outer_ipv4_id = 0; 2222 struct tcphdr *tcp; 2223 struct iphdr *ip; 2224 u16 ip_tot_len; 2225 u32 seqnum; 2226 u32 mss; 2227 2228 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2); 2229 2230 mss = skb_shinfo(skb)->gso_size; 2231 2232 if (unlikely(mss < 4)) { 2233 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss); 2234 return -EINVAL; 2235 } 2236 2237 if (skb->encapsulation) { 2238 if (!tx_queue->tso_encap) 2239 return -EINVAL; 2240 ip = ip_hdr(skb); 2241 if (ip->version == 4) 2242 outer_ipv4_id = ntohs(ip->id); 2243 2244 ip = inner_ip_hdr(skb); 2245 tcp = inner_tcp_hdr(skb); 2246 } else { 2247 ip = ip_hdr(skb); 2248 tcp = tcp_hdr(skb); 2249 } 2250 2251 /* 8000-series EF10 hardware requires that IP Total Length be 2252 * greater than or equal to the value it will have in each segment 2253 * (which is at most mss + 208 + TCP header length), but also less 2254 * than (0x10000 - inner_network_header). Otherwise the TCP 2255 * checksum calculation will be broken for encapsulated packets. 2256 * We fill in ip->tot_len with 0xff30, which should satisfy the 2257 * first requirement unless the MSS is ridiculously large (which 2258 * should be impossible as the driver max MTU is 9216); it is 2259 * guaranteed to satisfy the second as we only attempt TSO if 2260 * inner_network_header <= 208. 2261 */ 2262 ip_tot_len = 0x10000 - EFX_TSO2_MAX_HDRLEN; 2263 EFX_WARN_ON_ONCE_PARANOID(mss + EFX_TSO2_MAX_HDRLEN + 2264 (tcp->doff << 2u) > ip_tot_len); 2265 2266 if (ip->version == 4) { 2267 ip->tot_len = htons(ip_tot_len); 2268 ip->check = 0; 2269 inner_ipv4_id = ntohs(ip->id); 2270 } else { 2271 ((struct ipv6hdr *)ip)->payload_len = htons(ip_tot_len); 2272 } 2273 2274 seqnum = ntohl(tcp->seq); 2275 2276 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2277 2278 buffer->flags = EFX_TX_BUF_OPTION; 2279 buffer->len = 0; 2280 buffer->unmap_len = 0; 2281 EFX_POPULATE_QWORD_5(buffer->option, 2282 ESF_DZ_TX_DESC_IS_OPT, 1, 2283 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2284 ESF_DZ_TX_TSO_OPTION_TYPE, 2285 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A, 2286 ESF_DZ_TX_TSO_IP_ID, inner_ipv4_id, 2287 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum 2288 ); 2289 ++tx_queue->insert_count; 2290 2291 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2292 2293 buffer->flags = EFX_TX_BUF_OPTION; 2294 buffer->len = 0; 2295 buffer->unmap_len = 0; 2296 EFX_POPULATE_QWORD_5(buffer->option, 2297 ESF_DZ_TX_DESC_IS_OPT, 1, 2298 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2299 ESF_DZ_TX_TSO_OPTION_TYPE, 2300 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B, 2301 ESF_DZ_TX_TSO_OUTER_IPID, outer_ipv4_id, 2302 ESF_DZ_TX_TSO_TCP_MSS, mss 2303 ); 2304 ++tx_queue->insert_count; 2305 2306 return 0; 2307 } 2308 2309 static u32 efx_ef10_tso_versions(struct efx_nic *efx) 2310 { 2311 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2312 u32 tso_versions = 0; 2313 2314 if (nic_data->datapath_caps & 2315 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) 2316 tso_versions |= BIT(1); 2317 if (nic_data->datapath_caps2 & 2318 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) 2319 tso_versions |= BIT(2); 2320 return tso_versions; 2321 } 2322 2323 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 2324 { 2325 bool csum_offload = tx_queue->type & EFX_TXQ_TYPE_OUTER_CSUM; 2326 bool inner_csum = tx_queue->type & EFX_TXQ_TYPE_INNER_CSUM; 2327 struct efx_channel *channel = tx_queue->channel; 2328 struct efx_nic *efx = tx_queue->efx; 2329 struct efx_ef10_nic_data *nic_data; 2330 efx_qword_t *txd; 2331 int rc; 2332 2333 nic_data = efx->nic_data; 2334 2335 /* Only attempt to enable TX timestamping if we have the license for it, 2336 * otherwise TXQ init will fail 2337 */ 2338 if (!(nic_data->licensed_features & 2339 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) { 2340 tx_queue->timestamping = false; 2341 /* Disable sync events on this channel. */ 2342 if (efx->type->ptp_set_ts_sync_events) 2343 efx->type->ptp_set_ts_sync_events(efx, false, false); 2344 } 2345 2346 /* TSOv2 is a limited resource that can only be configured on a limited 2347 * number of queues. TSO without checksum offload is not really a thing, 2348 * so we only enable it for those queues. 2349 * TSOv2 cannot be used with Hardware timestamping, and is never needed 2350 * for XDP tx. 2351 */ 2352 if (efx_has_cap(efx, TX_TSO_V2)) { 2353 if ((csum_offload || inner_csum) && 2354 !tx_queue->timestamping && !tx_queue->xdp_tx) { 2355 tx_queue->tso_version = 2; 2356 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n", 2357 channel->channel); 2358 } 2359 } else if (efx_has_cap(efx, TX_TSO)) { 2360 tx_queue->tso_version = 1; 2361 } 2362 2363 rc = efx_mcdi_tx_init(tx_queue); 2364 if (rc) 2365 goto fail; 2366 2367 /* A previous user of this TX queue might have set us up the 2368 * bomb by writing a descriptor to the TX push collector but 2369 * not the doorbell. (Each collector belongs to a port, not a 2370 * queue or function, so cannot easily be reset.) We must 2371 * attempt to push a no-op descriptor in its place. 2372 */ 2373 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 2374 tx_queue->insert_count = 1; 2375 txd = efx_tx_desc(tx_queue, 0); 2376 EFX_POPULATE_QWORD_7(*txd, 2377 ESF_DZ_TX_DESC_IS_OPT, true, 2378 ESF_DZ_TX_OPTION_TYPE, 2379 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 2380 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 2381 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload && tx_queue->tso_version != 2, 2382 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM, inner_csum, 2383 ESF_DZ_TX_OPTION_INNER_IP_CSUM, inner_csum && tx_queue->tso_version != 2, 2384 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping); 2385 tx_queue->write_count = 1; 2386 2387 if (tx_queue->tso_version == 2 && efx_has_cap(efx, TX_TSO_V2_ENCAP)) 2388 tx_queue->tso_encap = true; 2389 2390 wmb(); 2391 efx_ef10_push_tx_desc(tx_queue, txd); 2392 2393 return; 2394 2395 fail: 2396 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 2397 tx_queue->queue); 2398 } 2399 2400 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 2401 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 2402 { 2403 unsigned int write_ptr; 2404 efx_dword_t reg; 2405 2406 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2407 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 2408 efx_writed_page(tx_queue->efx, ®, 2409 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 2410 } 2411 2412 #define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff 2413 2414 static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue, 2415 dma_addr_t dma_addr, unsigned int len) 2416 { 2417 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) { 2418 /* If we need to break across multiple descriptors we should 2419 * stop at a page boundary. This assumes the length limit is 2420 * greater than the page size. 2421 */ 2422 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN; 2423 2424 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE); 2425 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr; 2426 } 2427 2428 return len; 2429 } 2430 2431 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 2432 { 2433 unsigned int old_write_count = tx_queue->write_count; 2434 struct efx_tx_buffer *buffer; 2435 unsigned int write_ptr; 2436 efx_qword_t *txd; 2437 2438 tx_queue->xmit_pending = false; 2439 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 2440 return; 2441 2442 do { 2443 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2444 buffer = &tx_queue->buffer[write_ptr]; 2445 txd = efx_tx_desc(tx_queue, write_ptr); 2446 ++tx_queue->write_count; 2447 2448 /* Create TX descriptor ring entry */ 2449 if (buffer->flags & EFX_TX_BUF_OPTION) { 2450 *txd = buffer->option; 2451 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1) 2452 /* PIO descriptor */ 2453 tx_queue->packet_write_count = tx_queue->write_count; 2454 } else { 2455 tx_queue->packet_write_count = tx_queue->write_count; 2456 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 2457 EFX_POPULATE_QWORD_3( 2458 *txd, 2459 ESF_DZ_TX_KER_CONT, 2460 buffer->flags & EFX_TX_BUF_CONT, 2461 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 2462 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 2463 } 2464 } while (tx_queue->write_count != tx_queue->insert_count); 2465 2466 wmb(); /* Ensure descriptors are written before they are fetched */ 2467 2468 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 2469 txd = efx_tx_desc(tx_queue, 2470 old_write_count & tx_queue->ptr_mask); 2471 efx_ef10_push_tx_desc(tx_queue, txd); 2472 ++tx_queue->pushes; 2473 } else { 2474 efx_ef10_notify_tx_desc(tx_queue); 2475 } 2476 } 2477 2478 static int efx_ef10_probe_multicast_chaining(struct efx_nic *efx) 2479 { 2480 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2481 unsigned int enabled, implemented; 2482 bool want_workaround_26807; 2483 int rc; 2484 2485 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2486 if (rc == -ENOSYS) { 2487 /* GET_WORKAROUNDS was implemented before this workaround, 2488 * thus it must be unavailable in this firmware. 2489 */ 2490 nic_data->workaround_26807 = false; 2491 return 0; 2492 } 2493 if (rc) 2494 return rc; 2495 want_workaround_26807 = 2496 implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807; 2497 nic_data->workaround_26807 = 2498 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2499 2500 if (want_workaround_26807 && !nic_data->workaround_26807) { 2501 unsigned int flags; 2502 2503 rc = efx_mcdi_set_workaround(efx, 2504 MC_CMD_WORKAROUND_BUG26807, 2505 true, &flags); 2506 if (!rc) { 2507 if (flags & 2508 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2509 netif_info(efx, drv, efx->net_dev, 2510 "other functions on NIC have been reset\n"); 2511 2512 /* With MCFW v4.6.x and earlier, the 2513 * boot count will have incremented, 2514 * so re-read the warm_boot_count 2515 * value now to ensure this function 2516 * doesn't think it has changed next 2517 * time it checks. 2518 */ 2519 rc = efx_ef10_get_warm_boot_count(efx); 2520 if (rc >= 0) { 2521 nic_data->warm_boot_count = rc; 2522 rc = 0; 2523 } 2524 } 2525 nic_data->workaround_26807 = true; 2526 } else if (rc == -EPERM) { 2527 rc = 0; 2528 } 2529 } 2530 return rc; 2531 } 2532 2533 static int efx_ef10_filter_table_probe(struct efx_nic *efx) 2534 { 2535 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2536 int rc = efx_ef10_probe_multicast_chaining(efx); 2537 struct efx_mcdi_filter_vlan *vlan; 2538 2539 if (rc) 2540 return rc; 2541 down_write(&efx->filter_sem); 2542 rc = efx_mcdi_filter_table_probe(efx, nic_data->workaround_26807); 2543 2544 if (rc) 2545 goto out_unlock; 2546 2547 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 2548 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 2549 if (rc) 2550 goto fail_add_vlan; 2551 } 2552 goto out_unlock; 2553 2554 fail_add_vlan: 2555 efx_mcdi_filter_table_remove(efx); 2556 out_unlock: 2557 up_write(&efx->filter_sem); 2558 return rc; 2559 } 2560 2561 static void efx_ef10_filter_table_remove(struct efx_nic *efx) 2562 { 2563 down_write(&efx->filter_sem); 2564 efx_mcdi_filter_table_remove(efx); 2565 up_write(&efx->filter_sem); 2566 } 2567 2568 /* This creates an entry in the RX descriptor queue */ 2569 static inline void 2570 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2571 { 2572 struct efx_rx_buffer *rx_buf; 2573 efx_qword_t *rxd; 2574 2575 rxd = efx_rx_desc(rx_queue, index); 2576 rx_buf = efx_rx_buffer(rx_queue, index); 2577 EFX_POPULATE_QWORD_2(*rxd, 2578 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2579 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2580 } 2581 2582 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2583 { 2584 struct efx_nic *efx = rx_queue->efx; 2585 unsigned int write_count; 2586 efx_dword_t reg; 2587 2588 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2589 write_count = rx_queue->added_count & ~7; 2590 if (rx_queue->notified_count == write_count) 2591 return; 2592 2593 do 2594 efx_ef10_build_rx_desc( 2595 rx_queue, 2596 rx_queue->notified_count & rx_queue->ptr_mask); 2597 while (++rx_queue->notified_count != write_count); 2598 2599 wmb(); 2600 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2601 write_count & rx_queue->ptr_mask); 2602 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2603 efx_rx_queue_index(rx_queue)); 2604 } 2605 2606 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2607 2608 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2609 { 2610 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2611 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2612 efx_qword_t event; 2613 2614 EFX_POPULATE_QWORD_2(event, 2615 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2616 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2617 2618 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2619 2620 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2621 * already swapped the data to little-endian order. 2622 */ 2623 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2624 sizeof(efx_qword_t)); 2625 2626 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2627 inbuf, sizeof(inbuf), 0, 2628 efx_ef10_rx_defer_refill_complete, 0); 2629 } 2630 2631 static void 2632 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2633 int rc, efx_dword_t *outbuf, 2634 size_t outlen_actual) 2635 { 2636 /* nothing to do */ 2637 } 2638 2639 static int efx_ef10_ev_init(struct efx_channel *channel) 2640 { 2641 struct efx_nic *efx = channel->efx; 2642 struct efx_ef10_nic_data *nic_data; 2643 bool use_v2, cut_thru; 2644 2645 nic_data = efx->nic_data; 2646 use_v2 = nic_data->datapath_caps2 & 2647 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN; 2648 cut_thru = !(nic_data->datapath_caps & 2649 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2650 return efx_mcdi_ev_init(channel, cut_thru, use_v2); 2651 } 2652 2653 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2654 unsigned int rx_queue_label) 2655 { 2656 struct efx_nic *efx = rx_queue->efx; 2657 2658 netif_info(efx, hw, efx->net_dev, 2659 "rx event arrived on queue %d labeled as queue %u\n", 2660 efx_rx_queue_index(rx_queue), rx_queue_label); 2661 2662 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2663 } 2664 2665 static void 2666 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2667 unsigned int actual, unsigned int expected) 2668 { 2669 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2670 struct efx_nic *efx = rx_queue->efx; 2671 2672 netif_info(efx, hw, efx->net_dev, 2673 "dropped %d events (index=%d expected=%d)\n", 2674 dropped, actual, expected); 2675 2676 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2677 } 2678 2679 /* partially received RX was aborted. clean up. */ 2680 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2681 { 2682 unsigned int rx_desc_ptr; 2683 2684 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2685 "scattered RX aborted (dropping %u buffers)\n", 2686 rx_queue->scatter_n); 2687 2688 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2689 2690 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2691 0, EFX_RX_PKT_DISCARD); 2692 2693 rx_queue->removed_count += rx_queue->scatter_n; 2694 rx_queue->scatter_n = 0; 2695 rx_queue->scatter_len = 0; 2696 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2697 } 2698 2699 static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel, 2700 unsigned int n_packets, 2701 unsigned int rx_encap_hdr, 2702 unsigned int rx_l3_class, 2703 unsigned int rx_l4_class, 2704 const efx_qword_t *event) 2705 { 2706 struct efx_nic *efx = channel->efx; 2707 bool handled = false; 2708 2709 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) { 2710 if (!(efx->net_dev->features & NETIF_F_RXALL)) { 2711 if (!efx->loopback_selftest) 2712 channel->n_rx_eth_crc_err += n_packets; 2713 return EFX_RX_PKT_DISCARD; 2714 } 2715 handled = true; 2716 } 2717 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) { 2718 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2719 rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2720 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2721 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2722 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2723 netdev_WARN(efx->net_dev, 2724 "invalid class for RX_IPCKSUM_ERR: event=" 2725 EFX_QWORD_FMT "\n", 2726 EFX_QWORD_VAL(*event)); 2727 if (!efx->loopback_selftest) 2728 *(rx_encap_hdr ? 2729 &channel->n_rx_outer_ip_hdr_chksum_err : 2730 &channel->n_rx_ip_hdr_chksum_err) += n_packets; 2731 return 0; 2732 } 2733 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) { 2734 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2735 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2736 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2737 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2738 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))) 2739 netdev_WARN(efx->net_dev, 2740 "invalid class for RX_TCPUDP_CKSUM_ERR: event=" 2741 EFX_QWORD_FMT "\n", 2742 EFX_QWORD_VAL(*event)); 2743 if (!efx->loopback_selftest) 2744 *(rx_encap_hdr ? 2745 &channel->n_rx_outer_tcp_udp_chksum_err : 2746 &channel->n_rx_tcp_udp_chksum_err) += n_packets; 2747 return 0; 2748 } 2749 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) { 2750 if (unlikely(!rx_encap_hdr)) 2751 netdev_WARN(efx->net_dev, 2752 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event=" 2753 EFX_QWORD_FMT "\n", 2754 EFX_QWORD_VAL(*event)); 2755 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2756 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2757 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2758 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2759 netdev_WARN(efx->net_dev, 2760 "invalid class for RX_IP_INNER_CHKSUM_ERR: event=" 2761 EFX_QWORD_FMT "\n", 2762 EFX_QWORD_VAL(*event)); 2763 if (!efx->loopback_selftest) 2764 channel->n_rx_inner_ip_hdr_chksum_err += n_packets; 2765 return 0; 2766 } 2767 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) { 2768 if (unlikely(!rx_encap_hdr)) 2769 netdev_WARN(efx->net_dev, 2770 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2771 EFX_QWORD_FMT "\n", 2772 EFX_QWORD_VAL(*event)); 2773 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2774 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2775 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2776 rx_l4_class != ESE_FZ_L4_CLASS_UDP))) 2777 netdev_WARN(efx->net_dev, 2778 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2779 EFX_QWORD_FMT "\n", 2780 EFX_QWORD_VAL(*event)); 2781 if (!efx->loopback_selftest) 2782 channel->n_rx_inner_tcp_udp_chksum_err += n_packets; 2783 return 0; 2784 } 2785 2786 WARN_ON(!handled); /* No error bits were recognised */ 2787 return 0; 2788 } 2789 2790 static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2791 const efx_qword_t *event) 2792 { 2793 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label; 2794 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr; 2795 unsigned int n_descs, n_packets, i; 2796 struct efx_nic *efx = channel->efx; 2797 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2798 struct efx_rx_queue *rx_queue; 2799 efx_qword_t errors; 2800 bool rx_cont; 2801 u16 flags = 0; 2802 2803 if (unlikely(READ_ONCE(efx->reset_pending))) 2804 return 0; 2805 2806 /* Basic packet information */ 2807 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2808 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2809 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2810 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS); 2811 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS); 2812 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2813 rx_encap_hdr = 2814 nic_data->datapath_caps & 2815 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ? 2816 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) : 2817 ESE_EZ_ENCAP_HDR_NONE; 2818 2819 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2820 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2821 EFX_QWORD_FMT "\n", 2822 EFX_QWORD_VAL(*event)); 2823 2824 rx_queue = efx_channel_get_rx_queue(channel); 2825 2826 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2827 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2828 2829 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2830 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2831 2832 if (n_descs != rx_queue->scatter_n + 1) { 2833 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2834 2835 /* detect rx abort */ 2836 if (unlikely(n_descs == rx_queue->scatter_n)) { 2837 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2838 netdev_WARN(efx->net_dev, 2839 "invalid RX abort: scatter_n=%u event=" 2840 EFX_QWORD_FMT "\n", 2841 rx_queue->scatter_n, 2842 EFX_QWORD_VAL(*event)); 2843 efx_ef10_handle_rx_abort(rx_queue); 2844 return 0; 2845 } 2846 2847 /* Check that RX completion merging is valid, i.e. 2848 * the current firmware supports it and this is a 2849 * non-scattered packet. 2850 */ 2851 if (!(nic_data->datapath_caps & 2852 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2853 rx_queue->scatter_n != 0 || rx_cont) { 2854 efx_ef10_handle_rx_bad_lbits( 2855 rx_queue, next_ptr_lbits, 2856 (rx_queue->removed_count + 2857 rx_queue->scatter_n + 1) & 2858 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2859 return 0; 2860 } 2861 2862 /* Merged completion for multiple non-scattered packets */ 2863 rx_queue->scatter_n = 1; 2864 rx_queue->scatter_len = 0; 2865 n_packets = n_descs; 2866 ++channel->n_rx_merge_events; 2867 channel->n_rx_merge_packets += n_packets; 2868 flags |= EFX_RX_PKT_PREFIX_LEN; 2869 } else { 2870 ++rx_queue->scatter_n; 2871 rx_queue->scatter_len += rx_bytes; 2872 if (rx_cont) 2873 return 0; 2874 n_packets = 1; 2875 } 2876 2877 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1, 2878 ESF_DZ_RX_IPCKSUM_ERR, 1, 2879 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1, 2880 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1, 2881 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1); 2882 EFX_AND_QWORD(errors, *event, errors); 2883 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) { 2884 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets, 2885 rx_encap_hdr, 2886 rx_l3_class, rx_l4_class, 2887 event); 2888 } else { 2889 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP || 2890 rx_l4_class == ESE_FZ_L4_CLASS_UDP; 2891 2892 switch (rx_encap_hdr) { 2893 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */ 2894 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */ 2895 if (tcpudp) 2896 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */ 2897 break; 2898 case ESE_EZ_ENCAP_HDR_GRE: 2899 case ESE_EZ_ENCAP_HDR_NONE: 2900 if (tcpudp) 2901 flags |= EFX_RX_PKT_CSUMMED; 2902 break; 2903 default: 2904 netdev_WARN(efx->net_dev, 2905 "unknown encapsulation type: event=" 2906 EFX_QWORD_FMT "\n", 2907 EFX_QWORD_VAL(*event)); 2908 } 2909 } 2910 2911 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP) 2912 flags |= EFX_RX_PKT_TCP; 2913 2914 channel->irq_mod_score += 2 * n_packets; 2915 2916 /* Handle received packet(s) */ 2917 for (i = 0; i < n_packets; i++) { 2918 efx_rx_packet(rx_queue, 2919 rx_queue->removed_count & rx_queue->ptr_mask, 2920 rx_queue->scatter_n, rx_queue->scatter_len, 2921 flags); 2922 rx_queue->removed_count += rx_queue->scatter_n; 2923 } 2924 2925 rx_queue->scatter_n = 0; 2926 rx_queue->scatter_len = 0; 2927 2928 return n_packets; 2929 } 2930 2931 static u32 efx_ef10_extract_event_ts(efx_qword_t *event) 2932 { 2933 u32 tstamp; 2934 2935 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI); 2936 tstamp <<= 16; 2937 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO); 2938 2939 return tstamp; 2940 } 2941 2942 static void 2943 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2944 { 2945 struct efx_nic *efx = channel->efx; 2946 struct efx_tx_queue *tx_queue; 2947 unsigned int tx_ev_desc_ptr; 2948 unsigned int tx_ev_q_label; 2949 unsigned int tx_ev_type; 2950 u64 ts_part; 2951 2952 if (unlikely(READ_ONCE(efx->reset_pending))) 2953 return; 2954 2955 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2956 return; 2957 2958 /* Get the transmit queue */ 2959 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2960 tx_queue = channel->tx_queue + (tx_ev_q_label % EFX_MAX_TXQ_PER_CHANNEL); 2961 2962 if (!tx_queue->timestamping) { 2963 /* Transmit completion */ 2964 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2965 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2966 return; 2967 } 2968 2969 /* Transmit timestamps are only available for 8XXX series. They result 2970 * in up to three events per packet. These occur in order, and are: 2971 * - the normal completion event (may be omitted) 2972 * - the low part of the timestamp 2973 * - the high part of the timestamp 2974 * 2975 * It's possible for multiple completion events to appear before the 2976 * corresponding timestamps. So we can for example get: 2977 * COMP N 2978 * COMP N+1 2979 * TS_LO N 2980 * TS_HI N 2981 * TS_LO N+1 2982 * TS_HI N+1 2983 * 2984 * In addition it's also possible for the adjacent completions to be 2985 * merged, so we may not see COMP N above. As such, the completion 2986 * events are not very useful here. 2987 * 2988 * Each part of the timestamp is itself split across two 16 bit 2989 * fields in the event. 2990 */ 2991 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1); 2992 2993 switch (tx_ev_type) { 2994 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION: 2995 /* Ignore this event - see above. */ 2996 break; 2997 2998 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO: 2999 ts_part = efx_ef10_extract_event_ts(event); 3000 tx_queue->completed_timestamp_minor = ts_part; 3001 break; 3002 3003 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI: 3004 ts_part = efx_ef10_extract_event_ts(event); 3005 tx_queue->completed_timestamp_major = ts_part; 3006 3007 efx_xmit_done_single(tx_queue); 3008 break; 3009 3010 default: 3011 netif_err(efx, hw, efx->net_dev, 3012 "channel %d unknown tx event type %d (data " 3013 EFX_QWORD_FMT ")\n", 3014 channel->channel, tx_ev_type, 3015 EFX_QWORD_VAL(*event)); 3016 break; 3017 } 3018 } 3019 3020 static void 3021 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 3022 { 3023 struct efx_nic *efx = channel->efx; 3024 int subcode; 3025 3026 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 3027 3028 switch (subcode) { 3029 case ESE_DZ_DRV_TIMER_EV: 3030 case ESE_DZ_DRV_WAKE_UP_EV: 3031 break; 3032 case ESE_DZ_DRV_START_UP_EV: 3033 /* event queue init complete. ok. */ 3034 break; 3035 default: 3036 netif_err(efx, hw, efx->net_dev, 3037 "channel %d unknown driver event type %d" 3038 " (data " EFX_QWORD_FMT ")\n", 3039 channel->channel, subcode, 3040 EFX_QWORD_VAL(*event)); 3041 3042 } 3043 } 3044 3045 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 3046 efx_qword_t *event) 3047 { 3048 struct efx_nic *efx = channel->efx; 3049 u32 subcode; 3050 3051 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 3052 3053 switch (subcode) { 3054 case EFX_EF10_TEST: 3055 channel->event_test_cpu = raw_smp_processor_id(); 3056 break; 3057 case EFX_EF10_REFILL: 3058 /* The queue must be empty, so we won't receive any rx 3059 * events, so efx_process_channel() won't refill the 3060 * queue. Refill it here 3061 */ 3062 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 3063 break; 3064 default: 3065 netif_err(efx, hw, efx->net_dev, 3066 "channel %d unknown driver event type %u" 3067 " (data " EFX_QWORD_FMT ")\n", 3068 channel->channel, (unsigned) subcode, 3069 EFX_QWORD_VAL(*event)); 3070 } 3071 } 3072 3073 static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 3074 { 3075 struct efx_nic *efx = channel->efx; 3076 efx_qword_t event, *p_event; 3077 unsigned int read_ptr; 3078 int ev_code; 3079 int spent = 0; 3080 3081 if (quota <= 0) 3082 return spent; 3083 3084 read_ptr = channel->eventq_read_ptr; 3085 3086 for (;;) { 3087 p_event = efx_event(channel, read_ptr); 3088 event = *p_event; 3089 3090 if (!efx_event_present(&event)) 3091 break; 3092 3093 EFX_SET_QWORD(*p_event); 3094 3095 ++read_ptr; 3096 3097 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 3098 3099 netif_vdbg(efx, drv, efx->net_dev, 3100 "processing event on %d " EFX_QWORD_FMT "\n", 3101 channel->channel, EFX_QWORD_VAL(event)); 3102 3103 switch (ev_code) { 3104 case ESE_DZ_EV_CODE_MCDI_EV: 3105 efx_mcdi_process_event(channel, &event); 3106 break; 3107 case ESE_DZ_EV_CODE_RX_EV: 3108 spent += efx_ef10_handle_rx_event(channel, &event); 3109 if (spent >= quota) { 3110 /* XXX can we split a merged event to 3111 * avoid going over-quota? 3112 */ 3113 spent = quota; 3114 goto out; 3115 } 3116 break; 3117 case ESE_DZ_EV_CODE_TX_EV: 3118 efx_ef10_handle_tx_event(channel, &event); 3119 break; 3120 case ESE_DZ_EV_CODE_DRIVER_EV: 3121 efx_ef10_handle_driver_event(channel, &event); 3122 if (++spent == quota) 3123 goto out; 3124 break; 3125 case EFX_EF10_DRVGEN_EV: 3126 efx_ef10_handle_driver_generated_event(channel, &event); 3127 break; 3128 default: 3129 netif_err(efx, hw, efx->net_dev, 3130 "channel %d unknown event type %d" 3131 " (data " EFX_QWORD_FMT ")\n", 3132 channel->channel, ev_code, 3133 EFX_QWORD_VAL(event)); 3134 } 3135 } 3136 3137 out: 3138 channel->eventq_read_ptr = read_ptr; 3139 return spent; 3140 } 3141 3142 static void efx_ef10_ev_read_ack(struct efx_channel *channel) 3143 { 3144 struct efx_nic *efx = channel->efx; 3145 efx_dword_t rptr; 3146 3147 if (EFX_EF10_WORKAROUND_35388(efx)) { 3148 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 3149 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 3150 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 3151 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 3152 3153 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3154 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 3155 ERF_DD_EVQ_IND_RPTR, 3156 (channel->eventq_read_ptr & 3157 channel->eventq_mask) >> 3158 ERF_DD_EVQ_IND_RPTR_WIDTH); 3159 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3160 channel->channel); 3161 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3162 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 3163 ERF_DD_EVQ_IND_RPTR, 3164 channel->eventq_read_ptr & 3165 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 3166 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3167 channel->channel); 3168 } else { 3169 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 3170 channel->eventq_read_ptr & 3171 channel->eventq_mask); 3172 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 3173 } 3174 } 3175 3176 static void efx_ef10_ev_test_generate(struct efx_channel *channel) 3177 { 3178 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 3179 struct efx_nic *efx = channel->efx; 3180 efx_qword_t event; 3181 int rc; 3182 3183 EFX_POPULATE_QWORD_2(event, 3184 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 3185 ESF_DZ_EV_DATA, EFX_EF10_TEST); 3186 3187 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 3188 3189 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 3190 * already swapped the data to little-endian order. 3191 */ 3192 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 3193 sizeof(efx_qword_t)); 3194 3195 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 3196 NULL, 0, NULL); 3197 if (rc != 0) 3198 goto fail; 3199 3200 return; 3201 3202 fail: 3203 WARN_ON(true); 3204 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 3205 } 3206 3207 static void efx_ef10_prepare_flr(struct efx_nic *efx) 3208 { 3209 atomic_set(&efx->active_queues, 0); 3210 } 3211 3212 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 3213 { 3214 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3215 u8 mac_old[ETH_ALEN]; 3216 int rc, rc2; 3217 3218 /* Only reconfigure a PF-created vport */ 3219 if (is_zero_ether_addr(nic_data->vport_mac)) 3220 return 0; 3221 3222 efx_device_detach_sync(efx); 3223 efx_net_stop(efx->net_dev); 3224 efx_ef10_filter_table_remove(efx); 3225 3226 rc = efx_ef10_vadaptor_free(efx, efx->vport_id); 3227 if (rc) 3228 goto restore_filters; 3229 3230 ether_addr_copy(mac_old, nic_data->vport_mac); 3231 rc = efx_ef10_vport_del_mac(efx, efx->vport_id, 3232 nic_data->vport_mac); 3233 if (rc) 3234 goto restore_vadaptor; 3235 3236 rc = efx_ef10_vport_add_mac(efx, efx->vport_id, 3237 efx->net_dev->dev_addr); 3238 if (!rc) { 3239 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 3240 } else { 3241 rc2 = efx_ef10_vport_add_mac(efx, efx->vport_id, mac_old); 3242 if (rc2) { 3243 /* Failed to add original MAC, so clear vport_mac */ 3244 eth_zero_addr(nic_data->vport_mac); 3245 goto reset_nic; 3246 } 3247 } 3248 3249 restore_vadaptor: 3250 rc2 = efx_ef10_vadaptor_alloc(efx, efx->vport_id); 3251 if (rc2) 3252 goto reset_nic; 3253 restore_filters: 3254 rc2 = efx_ef10_filter_table_probe(efx); 3255 if (rc2) 3256 goto reset_nic; 3257 3258 rc2 = efx_net_open(efx->net_dev); 3259 if (rc2) 3260 goto reset_nic; 3261 3262 efx_device_attach_if_not_resetting(efx); 3263 3264 return rc; 3265 3266 reset_nic: 3267 netif_err(efx, drv, efx->net_dev, 3268 "Failed to restore when changing MAC address - scheduling reset\n"); 3269 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 3270 3271 return rc ? rc : rc2; 3272 } 3273 3274 static int efx_ef10_set_mac_address(struct efx_nic *efx) 3275 { 3276 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 3277 bool was_enabled = efx->port_enabled; 3278 int rc; 3279 3280 #ifdef CONFIG_SFC_SRIOV 3281 /* If this function is a VF and we have access to the parent PF, 3282 * then use the PF control path to attempt to change the VF MAC address. 3283 */ 3284 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 3285 struct efx_nic *efx_pf = pci_get_drvdata(efx->pci_dev->physfn); 3286 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3287 u8 mac[ETH_ALEN]; 3288 3289 /* net_dev->dev_addr can be zeroed by efx_net_stop in 3290 * efx_ef10_sriov_set_vf_mac, so pass in a copy. 3291 */ 3292 ether_addr_copy(mac, efx->net_dev->dev_addr); 3293 3294 rc = efx_ef10_sriov_set_vf_mac(efx_pf, nic_data->vf_index, mac); 3295 if (!rc) 3296 return 0; 3297 3298 netif_dbg(efx, drv, efx->net_dev, 3299 "Updating VF mac via PF failed (%d), setting directly\n", 3300 rc); 3301 } 3302 #endif 3303 3304 efx_device_detach_sync(efx); 3305 efx_net_stop(efx->net_dev); 3306 3307 mutex_lock(&efx->mac_lock); 3308 efx_ef10_filter_table_remove(efx); 3309 3310 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 3311 efx->net_dev->dev_addr); 3312 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 3313 efx->vport_id); 3314 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 3315 sizeof(inbuf), NULL, 0, NULL); 3316 3317 efx_ef10_filter_table_probe(efx); 3318 mutex_unlock(&efx->mac_lock); 3319 3320 if (was_enabled) 3321 efx_net_open(efx->net_dev); 3322 efx_device_attach_if_not_resetting(efx); 3323 3324 if (rc == -EPERM) { 3325 netif_err(efx, drv, efx->net_dev, 3326 "Cannot change MAC address; use sfboot to enable" 3327 " mac-spoofing on this interface\n"); 3328 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 3329 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 3330 * fall-back to the method of changing the MAC address on the 3331 * vport. This only applies to PFs because such versions of 3332 * MCFW do not support VFs. 3333 */ 3334 rc = efx_ef10_vport_set_mac_address(efx); 3335 } else if (rc) { 3336 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 3337 sizeof(inbuf), NULL, 0, rc); 3338 } 3339 3340 return rc; 3341 } 3342 3343 static int efx_ef10_mac_reconfigure(struct efx_nic *efx, bool mtu_only) 3344 { 3345 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 3346 3347 efx_mcdi_filter_sync_rx_mode(efx); 3348 3349 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED)) 3350 return efx_mcdi_set_mtu(efx); 3351 return efx_mcdi_set_mac(efx); 3352 } 3353 3354 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 3355 { 3356 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 3357 3358 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 3359 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 3360 NULL, 0, NULL); 3361 } 3362 3363 /* MC BISTs follow a different poll mechanism to phy BISTs. 3364 * The BIST is done in the poll handler on the MC, and the MCDI command 3365 * will block until the BIST is done. 3366 */ 3367 static int efx_ef10_poll_bist(struct efx_nic *efx) 3368 { 3369 int rc; 3370 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 3371 size_t outlen; 3372 u32 result; 3373 3374 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 3375 outbuf, sizeof(outbuf), &outlen); 3376 if (rc != 0) 3377 return rc; 3378 3379 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 3380 return -EIO; 3381 3382 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 3383 switch (result) { 3384 case MC_CMD_POLL_BIST_PASSED: 3385 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 3386 return 0; 3387 case MC_CMD_POLL_BIST_TIMEOUT: 3388 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 3389 return -EIO; 3390 case MC_CMD_POLL_BIST_FAILED: 3391 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 3392 return -EIO; 3393 default: 3394 netif_err(efx, hw, efx->net_dev, 3395 "BIST returned unknown result %u", result); 3396 return -EIO; 3397 } 3398 } 3399 3400 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 3401 { 3402 int rc; 3403 3404 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 3405 3406 rc = efx_ef10_start_bist(efx, bist_type); 3407 if (rc != 0) 3408 return rc; 3409 3410 return efx_ef10_poll_bist(efx); 3411 } 3412 3413 static int 3414 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 3415 { 3416 int rc, rc2; 3417 3418 efx_reset_down(efx, RESET_TYPE_WORLD); 3419 3420 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 3421 NULL, 0, NULL, 0, NULL); 3422 if (rc != 0) 3423 goto out; 3424 3425 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 3426 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 3427 3428 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 3429 3430 out: 3431 if (rc == -EPERM) 3432 rc = 0; 3433 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 3434 return rc ? rc : rc2; 3435 } 3436 3437 #ifdef CONFIG_SFC_MTD 3438 3439 struct efx_ef10_nvram_type_info { 3440 u16 type, type_mask; 3441 u8 port; 3442 const char *name; 3443 }; 3444 3445 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 3446 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 3447 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 3448 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 3449 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 3450 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 3451 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 3452 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 3453 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 3454 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 3455 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 3456 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 3457 { NVRAM_PARTITION_TYPE_MUM_FIRMWARE, 0, 0, "sfc_mumfw" }, 3458 { NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 0, 0, "sfc_uefi" }, 3459 { NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS, 0, 0, "sfc_dynamic_cfg_dflt" }, 3460 { NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS, 0, 0, "sfc_exp_rom_cfg_dflt" }, 3461 { NVRAM_PARTITION_TYPE_STATUS, 0, 0, "sfc_status" }, 3462 { NVRAM_PARTITION_TYPE_BUNDLE, 0, 0, "sfc_bundle" }, 3463 { NVRAM_PARTITION_TYPE_BUNDLE_METADATA, 0, 0, "sfc_bundle_metadata" }, 3464 }; 3465 #define EF10_NVRAM_PARTITION_COUNT ARRAY_SIZE(efx_ef10_nvram_types) 3466 3467 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 3468 struct efx_mcdi_mtd_partition *part, 3469 unsigned int type, 3470 unsigned long *found) 3471 { 3472 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 3473 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 3474 const struct efx_ef10_nvram_type_info *info; 3475 size_t size, erase_size, outlen; 3476 int type_idx = 0; 3477 bool protected; 3478 int rc; 3479 3480 for (type_idx = 0; ; type_idx++) { 3481 if (type_idx == EF10_NVRAM_PARTITION_COUNT) 3482 return -ENODEV; 3483 info = efx_ef10_nvram_types + type_idx; 3484 if ((type & ~info->type_mask) == info->type) 3485 break; 3486 } 3487 if (info->port != efx_port_num(efx)) 3488 return -ENODEV; 3489 3490 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 3491 if (rc) 3492 return rc; 3493 if (protected && 3494 (type != NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS && 3495 type != NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS)) 3496 /* Hide protected partitions that don't provide defaults. */ 3497 return -ENODEV; 3498 3499 if (protected) 3500 /* Protected partitions are read only. */ 3501 erase_size = 0; 3502 3503 /* If we've already exposed a partition of this type, hide this 3504 * duplicate. All operations on MTDs are keyed by the type anyway, 3505 * so we can't act on the duplicate. 3506 */ 3507 if (__test_and_set_bit(type_idx, found)) 3508 return -EEXIST; 3509 3510 part->nvram_type = type; 3511 3512 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 3513 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 3514 outbuf, sizeof(outbuf), &outlen); 3515 if (rc) 3516 return rc; 3517 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 3518 return -EIO; 3519 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 3520 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 3521 part->fw_subtype = MCDI_DWORD(outbuf, 3522 NVRAM_METADATA_OUT_SUBTYPE); 3523 3524 part->common.dev_type_name = "EF10 NVRAM manager"; 3525 part->common.type_name = info->name; 3526 3527 part->common.mtd.type = MTD_NORFLASH; 3528 part->common.mtd.flags = MTD_CAP_NORFLASH; 3529 part->common.mtd.size = size; 3530 part->common.mtd.erasesize = erase_size; 3531 /* sfc_status is read-only */ 3532 if (!erase_size) 3533 part->common.mtd.flags |= MTD_NO_ERASE; 3534 3535 return 0; 3536 } 3537 3538 static int efx_ef10_mtd_probe(struct efx_nic *efx) 3539 { 3540 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 3541 DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 }; 3542 struct efx_mcdi_mtd_partition *parts; 3543 size_t outlen, n_parts_total, i, n_parts; 3544 unsigned int type; 3545 int rc; 3546 3547 ASSERT_RTNL(); 3548 3549 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 3550 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 3551 outbuf, sizeof(outbuf), &outlen); 3552 if (rc) 3553 return rc; 3554 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 3555 return -EIO; 3556 3557 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 3558 if (n_parts_total > 3559 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 3560 return -EIO; 3561 3562 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 3563 if (!parts) 3564 return -ENOMEM; 3565 3566 n_parts = 0; 3567 for (i = 0; i < n_parts_total; i++) { 3568 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 3569 i); 3570 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type, 3571 found); 3572 if (rc == -EEXIST || rc == -ENODEV) 3573 continue; 3574 if (rc) 3575 goto fail; 3576 n_parts++; 3577 } 3578 3579 if (!n_parts) { 3580 kfree(parts); 3581 return 0; 3582 } 3583 3584 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 3585 fail: 3586 if (rc) 3587 kfree(parts); 3588 return rc; 3589 } 3590 3591 #endif /* CONFIG_SFC_MTD */ 3592 3593 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 3594 { 3595 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 3596 } 3597 3598 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 3599 u32 host_time) {} 3600 3601 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 3602 bool temp) 3603 { 3604 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 3605 int rc; 3606 3607 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 3608 channel->sync_events_state == SYNC_EVENTS_VALID || 3609 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 3610 return 0; 3611 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 3612 3613 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 3614 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3615 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 3616 channel->channel); 3617 3618 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3619 inbuf, sizeof(inbuf), NULL, 0, NULL); 3620 3621 if (rc != 0) 3622 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3623 SYNC_EVENTS_DISABLED; 3624 3625 return rc; 3626 } 3627 3628 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 3629 bool temp) 3630 { 3631 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 3632 int rc; 3633 3634 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 3635 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 3636 return 0; 3637 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 3638 channel->sync_events_state = SYNC_EVENTS_DISABLED; 3639 return 0; 3640 } 3641 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3642 SYNC_EVENTS_DISABLED; 3643 3644 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 3645 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3646 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 3647 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 3648 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 3649 channel->channel); 3650 3651 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3652 inbuf, sizeof(inbuf), NULL, 0, NULL); 3653 3654 return rc; 3655 } 3656 3657 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 3658 bool temp) 3659 { 3660 int (*set)(struct efx_channel *channel, bool temp); 3661 struct efx_channel *channel; 3662 3663 set = en ? 3664 efx_ef10_rx_enable_timestamping : 3665 efx_ef10_rx_disable_timestamping; 3666 3667 channel = efx_ptp_channel(efx); 3668 if (channel) { 3669 int rc = set(channel, temp); 3670 if (en && rc != 0) { 3671 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 3672 return rc; 3673 } 3674 } 3675 3676 return 0; 3677 } 3678 3679 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 3680 struct hwtstamp_config *init) 3681 { 3682 return -EOPNOTSUPP; 3683 } 3684 3685 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 3686 struct hwtstamp_config *init) 3687 { 3688 int rc; 3689 3690 switch (init->rx_filter) { 3691 case HWTSTAMP_FILTER_NONE: 3692 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 3693 /* if TX timestamping is still requested then leave PTP on */ 3694 return efx_ptp_change_mode(efx, 3695 init->tx_type != HWTSTAMP_TX_OFF, 0); 3696 case HWTSTAMP_FILTER_ALL: 3697 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3698 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3699 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3700 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3701 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3702 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3703 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3704 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3705 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3706 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3707 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3708 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3709 case HWTSTAMP_FILTER_NTP_ALL: 3710 init->rx_filter = HWTSTAMP_FILTER_ALL; 3711 rc = efx_ptp_change_mode(efx, true, 0); 3712 if (!rc) 3713 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 3714 if (rc) 3715 efx_ptp_change_mode(efx, false, 0); 3716 return rc; 3717 default: 3718 return -ERANGE; 3719 } 3720 } 3721 3722 static int efx_ef10_get_phys_port_id(struct efx_nic *efx, 3723 struct netdev_phys_item_id *ppid) 3724 { 3725 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3726 3727 if (!is_valid_ether_addr(nic_data->port_id)) 3728 return -EOPNOTSUPP; 3729 3730 ppid->id_len = ETH_ALEN; 3731 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 3732 3733 return 0; 3734 } 3735 3736 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3737 { 3738 if (proto != htons(ETH_P_8021Q)) 3739 return -EINVAL; 3740 3741 return efx_ef10_add_vlan(efx, vid); 3742 } 3743 3744 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3745 { 3746 if (proto != htons(ETH_P_8021Q)) 3747 return -EINVAL; 3748 3749 return efx_ef10_del_vlan(efx, vid); 3750 } 3751 3752 /* We rely on the MCDI wiping out our TX rings if it made any changes to the 3753 * ports table, ensuring that any TSO descriptors that were made on a now- 3754 * removed tunnel port will be blown away and won't break things when we try 3755 * to transmit them using the new ports table. 3756 */ 3757 static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading) 3758 { 3759 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3760 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX); 3761 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN); 3762 bool will_reset = false; 3763 size_t num_entries = 0; 3764 size_t inlen, outlen; 3765 size_t i; 3766 int rc; 3767 efx_dword_t flags_and_num_entries; 3768 3769 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock)); 3770 3771 nic_data->udp_tunnels_dirty = false; 3772 3773 if (!(nic_data->datapath_caps & 3774 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) { 3775 efx_device_attach_if_not_resetting(efx); 3776 return 0; 3777 } 3778 3779 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) > 3780 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM); 3781 3782 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) { 3783 if (nic_data->udp_tunnels[i].type != 3784 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID) { 3785 efx_dword_t entry; 3786 3787 EFX_POPULATE_DWORD_2(entry, 3788 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT, 3789 ntohs(nic_data->udp_tunnels[i].port), 3790 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL, 3791 nic_data->udp_tunnels[i].type); 3792 *_MCDI_ARRAY_DWORD(inbuf, 3793 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES, 3794 num_entries++) = entry; 3795 } 3796 } 3797 3798 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST - 3799 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 != 3800 EFX_WORD_1_LBN); 3801 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 != 3802 EFX_WORD_1_WIDTH); 3803 EFX_POPULATE_DWORD_2(flags_and_num_entries, 3804 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING, 3805 !!unloading, 3806 EFX_WORD_1, num_entries); 3807 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) = 3808 flags_and_num_entries; 3809 3810 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries); 3811 3812 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS, 3813 inbuf, inlen, outbuf, sizeof(outbuf), &outlen); 3814 if (rc == -EIO) { 3815 /* Most likely the MC rebooted due to another function also 3816 * setting its tunnel port list. Mark the tunnel port list as 3817 * dirty, so it will be pushed upon coming up from the reboot. 3818 */ 3819 nic_data->udp_tunnels_dirty = true; 3820 return 0; 3821 } 3822 3823 if (rc) { 3824 /* expected not available on unprivileged functions */ 3825 if (rc != -EPERM) 3826 netif_warn(efx, drv, efx->net_dev, 3827 "Unable to set UDP tunnel ports; rc=%d.\n", rc); 3828 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) & 3829 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) { 3830 netif_info(efx, drv, efx->net_dev, 3831 "Rebooting MC due to UDP tunnel port list change\n"); 3832 will_reset = true; 3833 if (unloading) 3834 /* Delay for the MC reset to complete. This will make 3835 * unloading other functions a bit smoother. This is a 3836 * race, but the other unload will work whichever way 3837 * it goes, this just avoids an unnecessary error 3838 * message. 3839 */ 3840 msleep(100); 3841 } 3842 if (!will_reset && !unloading) { 3843 /* The caller will have detached, relying on the MC reset to 3844 * trigger a re-attach. Since there won't be an MC reset, we 3845 * have to do the attach ourselves. 3846 */ 3847 efx_device_attach_if_not_resetting(efx); 3848 } 3849 3850 return rc; 3851 } 3852 3853 static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx) 3854 { 3855 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3856 int rc = 0; 3857 3858 mutex_lock(&nic_data->udp_tunnels_lock); 3859 if (nic_data->udp_tunnels_dirty) { 3860 /* Make sure all TX are stopped while we modify the table, else 3861 * we might race against an efx_features_check(). 3862 */ 3863 efx_device_detach_sync(efx); 3864 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3865 } 3866 mutex_unlock(&nic_data->udp_tunnels_lock); 3867 return rc; 3868 } 3869 3870 static int efx_ef10_udp_tnl_set_port(struct net_device *dev, 3871 unsigned int table, unsigned int entry, 3872 struct udp_tunnel_info *ti) 3873 { 3874 struct efx_nic *efx = efx_netdev_priv(dev); 3875 struct efx_ef10_nic_data *nic_data; 3876 int efx_tunnel_type, rc; 3877 3878 if (ti->type == UDP_TUNNEL_TYPE_VXLAN) 3879 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN; 3880 else 3881 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE; 3882 3883 nic_data = efx->nic_data; 3884 if (!(nic_data->datapath_caps & 3885 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3886 return -EOPNOTSUPP; 3887 3888 mutex_lock(&nic_data->udp_tunnels_lock); 3889 /* Make sure all TX are stopped while we add to the table, else we 3890 * might race against an efx_features_check(). 3891 */ 3892 efx_device_detach_sync(efx); 3893 nic_data->udp_tunnels[entry].type = efx_tunnel_type; 3894 nic_data->udp_tunnels[entry].port = ti->port; 3895 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3896 mutex_unlock(&nic_data->udp_tunnels_lock); 3897 3898 return rc; 3899 } 3900 3901 /* Called under the TX lock with the TX queue running, hence no-one can be 3902 * in the middle of updating the UDP tunnels table. However, they could 3903 * have tried and failed the MCDI, in which case they'll have set the dirty 3904 * flag before dropping their locks. 3905 */ 3906 static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port) 3907 { 3908 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3909 size_t i; 3910 3911 if (!(nic_data->datapath_caps & 3912 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3913 return false; 3914 3915 if (nic_data->udp_tunnels_dirty) 3916 /* SW table may not match HW state, so just assume we can't 3917 * use any UDP tunnel offloads. 3918 */ 3919 return false; 3920 3921 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 3922 if (nic_data->udp_tunnels[i].type != 3923 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID && 3924 nic_data->udp_tunnels[i].port == port) 3925 return true; 3926 3927 return false; 3928 } 3929 3930 static int efx_ef10_udp_tnl_unset_port(struct net_device *dev, 3931 unsigned int table, unsigned int entry, 3932 struct udp_tunnel_info *ti) 3933 { 3934 struct efx_nic *efx = efx_netdev_priv(dev); 3935 struct efx_ef10_nic_data *nic_data; 3936 int rc; 3937 3938 nic_data = efx->nic_data; 3939 3940 mutex_lock(&nic_data->udp_tunnels_lock); 3941 /* Make sure all TX are stopped while we remove from the table, else we 3942 * might race against an efx_features_check(). 3943 */ 3944 efx_device_detach_sync(efx); 3945 nic_data->udp_tunnels[entry].type = TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 3946 nic_data->udp_tunnels[entry].port = 0; 3947 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3948 mutex_unlock(&nic_data->udp_tunnels_lock); 3949 3950 return rc; 3951 } 3952 3953 static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels = { 3954 .set_port = efx_ef10_udp_tnl_set_port, 3955 .unset_port = efx_ef10_udp_tnl_unset_port, 3956 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP, 3957 .tables = { 3958 { 3959 .n_entries = 16, 3960 .tunnel_types = UDP_TUNNEL_TYPE_VXLAN | 3961 UDP_TUNNEL_TYPE_GENEVE, 3962 }, 3963 }, 3964 }; 3965 3966 /* EF10 may have multiple datapath firmware variants within a 3967 * single version. Report which variants are running. 3968 */ 3969 static size_t efx_ef10_print_additional_fwver(struct efx_nic *efx, char *buf, 3970 size_t len) 3971 { 3972 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3973 3974 return scnprintf(buf, len, " rx%x tx%x", 3975 nic_data->rx_dpcpu_fw_id, 3976 nic_data->tx_dpcpu_fw_id); 3977 } 3978 3979 static unsigned int ef10_check_caps(const struct efx_nic *efx, 3980 u8 flag, 3981 u32 offset) 3982 { 3983 const struct efx_ef10_nic_data *nic_data = efx->nic_data; 3984 3985 switch (offset) { 3986 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST): 3987 return nic_data->datapath_caps & BIT_ULL(flag); 3988 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST): 3989 return nic_data->datapath_caps2 & BIT_ULL(flag); 3990 default: 3991 return 0; 3992 } 3993 } 3994 3995 static unsigned int efx_ef10_recycle_ring_size(const struct efx_nic *efx) 3996 { 3997 unsigned int ret = EFX_RECYCLE_RING_SIZE_10G; 3998 3999 /* There is no difference between PFs and VFs. The side is based on 4000 * the maximum link speed of a given NIC. 4001 */ 4002 switch (efx->pci_dev->device & 0xfff) { 4003 case 0x0903: /* Farmingdale can do up to 10G */ 4004 break; 4005 case 0x0923: /* Greenport can do up to 40G */ 4006 case 0x0a03: /* Medford can do up to 40G */ 4007 ret *= 4; 4008 break; 4009 default: /* Medford2 can do up to 100G */ 4010 ret *= 10; 4011 } 4012 4013 if (IS_ENABLED(CONFIG_PPC64)) 4014 ret *= 4; 4015 4016 return ret; 4017 } 4018 4019 #define EF10_OFFLOAD_FEATURES \ 4020 (NETIF_F_IP_CSUM | \ 4021 NETIF_F_HW_VLAN_CTAG_FILTER | \ 4022 NETIF_F_IPV6_CSUM | \ 4023 NETIF_F_RXHASH | \ 4024 NETIF_F_NTUPLE) 4025 4026 const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 4027 .is_vf = true, 4028 .mem_bar = efx_ef10_vf_mem_bar, 4029 .mem_map_size = efx_ef10_mem_map_size, 4030 .probe = efx_ef10_probe_vf, 4031 .remove = efx_ef10_remove, 4032 .dimension_resources = efx_ef10_dimension_resources, 4033 .init = efx_ef10_init_nic, 4034 .fini = efx_ef10_fini_nic, 4035 .map_reset_reason = efx_ef10_map_reset_reason, 4036 .map_reset_flags = efx_ef10_map_reset_flags, 4037 .reset = efx_ef10_reset, 4038 .probe_port = efx_mcdi_port_probe, 4039 .remove_port = efx_mcdi_port_remove, 4040 .fini_dmaq = efx_fini_dmaq, 4041 .prepare_flr = efx_ef10_prepare_flr, 4042 .finish_flr = efx_port_dummy_op_void, 4043 .describe_stats = efx_ef10_describe_stats, 4044 .update_stats = efx_ef10_update_stats_vf, 4045 .update_stats_atomic = efx_ef10_update_stats_atomic_vf, 4046 .start_stats = efx_port_dummy_op_void, 4047 .pull_stats = efx_port_dummy_op_void, 4048 .stop_stats = efx_port_dummy_op_void, 4049 .push_irq_moderation = efx_ef10_push_irq_moderation, 4050 .reconfigure_mac = efx_ef10_mac_reconfigure, 4051 .check_mac_fault = efx_mcdi_mac_check_fault, 4052 .reconfigure_port = efx_mcdi_port_reconfigure, 4053 .get_wol = efx_ef10_get_wol_vf, 4054 .set_wol = efx_ef10_set_wol_vf, 4055 .resume_wol = efx_port_dummy_op_void, 4056 .mcdi_request = efx_ef10_mcdi_request, 4057 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4058 .mcdi_read_response = efx_ef10_mcdi_read_response, 4059 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4060 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4061 .irq_enable_master = efx_port_dummy_op_void, 4062 .irq_test_generate = efx_ef10_irq_test_generate, 4063 .irq_disable_non_ev = efx_port_dummy_op_void, 4064 .irq_handle_msi = efx_ef10_msi_interrupt, 4065 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4066 .tx_probe = efx_ef10_tx_probe, 4067 .tx_init = efx_ef10_tx_init, 4068 .tx_remove = efx_mcdi_tx_remove, 4069 .tx_write = efx_ef10_tx_write, 4070 .tx_limit_len = efx_ef10_tx_limit_len, 4071 .tx_enqueue = __efx_enqueue_skb, 4072 .rx_push_rss_config = efx_mcdi_vf_rx_push_rss_config, 4073 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4074 .rx_probe = efx_mcdi_rx_probe, 4075 .rx_init = efx_mcdi_rx_init, 4076 .rx_remove = efx_mcdi_rx_remove, 4077 .rx_write = efx_ef10_rx_write, 4078 .rx_defer_refill = efx_ef10_rx_defer_refill, 4079 .rx_packet = __efx_rx_packet, 4080 .ev_probe = efx_mcdi_ev_probe, 4081 .ev_init = efx_ef10_ev_init, 4082 .ev_fini = efx_mcdi_ev_fini, 4083 .ev_remove = efx_mcdi_ev_remove, 4084 .ev_process = efx_ef10_ev_process, 4085 .ev_read_ack = efx_ef10_ev_read_ack, 4086 .ev_test_generate = efx_ef10_ev_test_generate, 4087 .filter_table_probe = efx_ef10_filter_table_probe, 4088 .filter_table_restore = efx_mcdi_filter_table_restore, 4089 .filter_table_remove = efx_ef10_filter_table_remove, 4090 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4091 .filter_insert = efx_mcdi_filter_insert, 4092 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4093 .filter_get_safe = efx_mcdi_filter_get_safe, 4094 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4095 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4096 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4097 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4098 #ifdef CONFIG_RFS_ACCEL 4099 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4100 #endif 4101 #ifdef CONFIG_SFC_MTD 4102 .mtd_probe = efx_port_dummy_op_int, 4103 #endif 4104 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4105 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4106 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4107 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4108 #ifdef CONFIG_SFC_SRIOV 4109 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4110 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4111 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4112 #endif 4113 .get_mac_address = efx_ef10_get_mac_address_vf, 4114 .set_mac_address = efx_ef10_set_mac_address, 4115 4116 .get_phys_port_id = efx_ef10_get_phys_port_id, 4117 .revision = EFX_REV_HUNT_A0, 4118 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4119 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4120 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4121 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4122 .can_rx_scatter = true, 4123 .always_rx_scatter = true, 4124 .min_interrupt_mode = EFX_INT_MODE_MSIX, 4125 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4126 .offload_features = EF10_OFFLOAD_FEATURES, 4127 .mcdi_max_ver = 2, 4128 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4129 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4130 1 << HWTSTAMP_FILTER_ALL, 4131 .rx_hash_key_size = 40, 4132 .check_caps = ef10_check_caps, 4133 .print_additional_fwver = efx_ef10_print_additional_fwver, 4134 .sensor_event = efx_mcdi_sensor_event, 4135 .rx_recycle_ring_size = efx_ef10_recycle_ring_size, 4136 }; 4137 4138 const struct efx_nic_type efx_hunt_a0_nic_type = { 4139 .is_vf = false, 4140 .mem_bar = efx_ef10_pf_mem_bar, 4141 .mem_map_size = efx_ef10_mem_map_size, 4142 .probe = efx_ef10_probe_pf, 4143 .remove = efx_ef10_remove, 4144 .dimension_resources = efx_ef10_dimension_resources, 4145 .init = efx_ef10_init_nic, 4146 .fini = efx_ef10_fini_nic, 4147 .map_reset_reason = efx_ef10_map_reset_reason, 4148 .map_reset_flags = efx_ef10_map_reset_flags, 4149 .reset = efx_ef10_reset, 4150 .probe_port = efx_mcdi_port_probe, 4151 .remove_port = efx_mcdi_port_remove, 4152 .fini_dmaq = efx_fini_dmaq, 4153 .prepare_flr = efx_ef10_prepare_flr, 4154 .finish_flr = efx_port_dummy_op_void, 4155 .describe_stats = efx_ef10_describe_stats, 4156 .update_stats = efx_ef10_update_stats_pf, 4157 .start_stats = efx_mcdi_mac_start_stats, 4158 .pull_stats = efx_mcdi_mac_pull_stats, 4159 .stop_stats = efx_mcdi_mac_stop_stats, 4160 .push_irq_moderation = efx_ef10_push_irq_moderation, 4161 .reconfigure_mac = efx_ef10_mac_reconfigure, 4162 .check_mac_fault = efx_mcdi_mac_check_fault, 4163 .reconfigure_port = efx_mcdi_port_reconfigure, 4164 .get_wol = efx_ef10_get_wol, 4165 .set_wol = efx_ef10_set_wol, 4166 .resume_wol = efx_port_dummy_op_void, 4167 .get_fec_stats = efx_ef10_get_fec_stats, 4168 .test_chip = efx_ef10_test_chip, 4169 .test_nvram = efx_mcdi_nvram_test_all, 4170 .mcdi_request = efx_ef10_mcdi_request, 4171 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4172 .mcdi_read_response = efx_ef10_mcdi_read_response, 4173 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4174 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4175 .irq_enable_master = efx_port_dummy_op_void, 4176 .irq_test_generate = efx_ef10_irq_test_generate, 4177 .irq_disable_non_ev = efx_port_dummy_op_void, 4178 .irq_handle_msi = efx_ef10_msi_interrupt, 4179 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4180 .tx_probe = efx_ef10_tx_probe, 4181 .tx_init = efx_ef10_tx_init, 4182 .tx_remove = efx_mcdi_tx_remove, 4183 .tx_write = efx_ef10_tx_write, 4184 .tx_limit_len = efx_ef10_tx_limit_len, 4185 .tx_enqueue = __efx_enqueue_skb, 4186 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 4187 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4188 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 4189 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 4190 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 4191 .rx_probe = efx_mcdi_rx_probe, 4192 .rx_init = efx_mcdi_rx_init, 4193 .rx_remove = efx_mcdi_rx_remove, 4194 .rx_write = efx_ef10_rx_write, 4195 .rx_defer_refill = efx_ef10_rx_defer_refill, 4196 .rx_packet = __efx_rx_packet, 4197 .ev_probe = efx_mcdi_ev_probe, 4198 .ev_init = efx_ef10_ev_init, 4199 .ev_fini = efx_mcdi_ev_fini, 4200 .ev_remove = efx_mcdi_ev_remove, 4201 .ev_process = efx_ef10_ev_process, 4202 .ev_read_ack = efx_ef10_ev_read_ack, 4203 .ev_test_generate = efx_ef10_ev_test_generate, 4204 .filter_table_probe = efx_ef10_filter_table_probe, 4205 .filter_table_restore = efx_mcdi_filter_table_restore, 4206 .filter_table_remove = efx_ef10_filter_table_remove, 4207 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4208 .filter_insert = efx_mcdi_filter_insert, 4209 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4210 .filter_get_safe = efx_mcdi_filter_get_safe, 4211 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4212 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4213 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4214 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4215 #ifdef CONFIG_RFS_ACCEL 4216 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4217 #endif 4218 #ifdef CONFIG_SFC_MTD 4219 .mtd_probe = efx_ef10_mtd_probe, 4220 .mtd_rename = efx_mcdi_mtd_rename, 4221 .mtd_read = efx_mcdi_mtd_read, 4222 .mtd_erase = efx_mcdi_mtd_erase, 4223 .mtd_write = efx_mcdi_mtd_write, 4224 .mtd_sync = efx_mcdi_mtd_sync, 4225 #endif 4226 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4227 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4228 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4229 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4230 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4231 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports, 4232 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port, 4233 #ifdef CONFIG_SFC_SRIOV 4234 .sriov_configure = efx_ef10_sriov_configure, 4235 .sriov_init = efx_ef10_sriov_init, 4236 .sriov_fini = efx_ef10_sriov_fini, 4237 .sriov_wanted = efx_ef10_sriov_wanted, 4238 .sriov_reset = efx_ef10_sriov_reset, 4239 .sriov_flr = efx_ef10_sriov_flr, 4240 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4241 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4242 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4243 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4244 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4245 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4246 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4247 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4248 #endif 4249 .get_mac_address = efx_ef10_get_mac_address_pf, 4250 .set_mac_address = efx_ef10_set_mac_address, 4251 .tso_versions = efx_ef10_tso_versions, 4252 4253 .get_phys_port_id = efx_ef10_get_phys_port_id, 4254 .revision = EFX_REV_HUNT_A0, 4255 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4256 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4257 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4258 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4259 .can_rx_scatter = true, 4260 .always_rx_scatter = true, 4261 .option_descriptors = true, 4262 .min_interrupt_mode = EFX_INT_MODE_LEGACY, 4263 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4264 .offload_features = EF10_OFFLOAD_FEATURES, 4265 .mcdi_max_ver = 2, 4266 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4267 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4268 1 << HWTSTAMP_FILTER_ALL, 4269 .rx_hash_key_size = 40, 4270 .check_caps = ef10_check_caps, 4271 .print_additional_fwver = efx_ef10_print_additional_fwver, 4272 .sensor_event = efx_mcdi_sensor_event, 4273 .rx_recycle_ring_size = efx_ef10_recycle_ring_size, 4274 }; 4275