1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * sgiseeq.h: Defines for the Seeq8003 ethernet controller. 4 * 5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 6 */ 7 #ifndef _SGISEEQ_H 8 #define _SGISEEQ_H 9 10 struct sgiseeq_wregs { 11 volatile unsigned int multicase_high[2]; 12 volatile unsigned int frame_gap; 13 volatile unsigned int control; 14 }; 15 16 struct sgiseeq_rregs { 17 volatile unsigned int collision_tx[2]; 18 volatile unsigned int collision_all[2]; 19 volatile unsigned int _unused0; 20 volatile unsigned int rflags; 21 }; 22 23 struct sgiseeq_regs { 24 union { 25 volatile unsigned int eth_addr[6]; 26 volatile unsigned int multicast_low[6]; 27 struct sgiseeq_wregs wregs; 28 struct sgiseeq_rregs rregs; 29 } rw; 30 volatile unsigned int rstat; 31 volatile unsigned int tstat; 32 }; 33 34 /* Seeq8003 receive status register */ 35 #define SEEQ_RSTAT_OVERF 0x001 /* Overflow */ 36 #define SEEQ_RSTAT_CERROR 0x002 /* CRC error */ 37 #define SEEQ_RSTAT_DERROR 0x004 /* Dribble error */ 38 #define SEEQ_RSTAT_SFRAME 0x008 /* Short frame */ 39 #define SEEQ_RSTAT_REOF 0x010 /* Received end of frame */ 40 #define SEEQ_RSTAT_FIG 0x020 /* Frame is good */ 41 #define SEEQ_RSTAT_TIMEO 0x040 /* Timeout, or late receive */ 42 #define SEEQ_RSTAT_WHICH 0x080 /* Which status, 1=old 0=new */ 43 #define SEEQ_RSTAT_LITTLE 0x100 /* DMA is done in little endian format */ 44 #define SEEQ_RSTAT_SDMA 0x200 /* DMA has started */ 45 #define SEEQ_RSTAT_ADMA 0x400 /* DMA is active */ 46 #define SEEQ_RSTAT_ROVERF 0x800 /* Receive buffer overflow */ 47 48 /* Seeq8003 receive command register */ 49 #define SEEQ_RCMD_RDISAB 0x000 /* Disable receiver on the Seeq8003 */ 50 #define SEEQ_RCMD_IOVERF 0x001 /* IRQ on buffer overflows */ 51 #define SEEQ_RCMD_ICRC 0x002 /* IRQ on CRC errors */ 52 #define SEEQ_RCMD_IDRIB 0x004 /* IRQ on dribble errors */ 53 #define SEEQ_RCMD_ISHORT 0x008 /* IRQ on short frames */ 54 #define SEEQ_RCMD_IEOF 0x010 /* IRQ on end of frame */ 55 #define SEEQ_RCMD_IGOOD 0x020 /* IRQ on good frames */ 56 #define SEEQ_RCMD_RANY 0x040 /* Receive any frame */ 57 #define SEEQ_RCMD_RBCAST 0x080 /* Receive broadcasts */ 58 #define SEEQ_RCMD_RBMCAST 0x0c0 /* Receive broadcasts/multicasts */ 59 60 /* Seeq8003 transmit status register */ 61 #define SEEQ_TSTAT_UFLOW 0x001 /* Transmit buffer underflow */ 62 #define SEEQ_TSTAT_CLS 0x002 /* Collision detected */ 63 #define SEEQ_TSTAT_R16 0x004 /* Did 16 retries to tx a frame */ 64 #define SEEQ_TSTAT_PTRANS 0x008 /* Packet was transmitted ok */ 65 #define SEEQ_TSTAT_LCLS 0x010 /* Late collision occurred */ 66 #define SEEQ_TSTAT_WHICH 0x080 /* Which status, 1=old 0=new */ 67 #define SEEQ_TSTAT_TLE 0x100 /* DMA is done in little endian format */ 68 #define SEEQ_TSTAT_SDMA 0x200 /* DMA has started */ 69 #define SEEQ_TSTAT_ADMA 0x400 /* DMA is active */ 70 71 /* Seeq8003 transmit command register */ 72 #define SEEQ_TCMD_RB0 0x00 /* Register bank zero w/station addr */ 73 #define SEEQ_TCMD_IUF 0x01 /* IRQ on tx underflow */ 74 #define SEEQ_TCMD_IC 0x02 /* IRQ on collisions */ 75 #define SEEQ_TCMD_I16 0x04 /* IRQ after 16 failed attempts to tx frame */ 76 #define SEEQ_TCMD_IPT 0x08 /* IRQ when packet successfully transmitted */ 77 #define SEEQ_TCMD_RB1 0x20 /* Register bank one w/multi-cast low byte */ 78 #define SEEQ_TCMD_RB2 0x40 /* Register bank two w/multi-cast high byte */ 79 80 /* Seeq8003 control register */ 81 #define SEEQ_CTRL_XCNT 0x01 82 #define SEEQ_CTRL_ACCNT 0x02 83 #define SEEQ_CTRL_SFLAG 0x04 84 #define SEEQ_CTRL_EMULTI 0x08 85 #define SEEQ_CTRL_ESHORT 0x10 86 #define SEEQ_CTRL_ENCARR 0x20 87 88 /* Seeq8003 control registers on the SGI Hollywood HPC. */ 89 #define SEEQ_HPIO_P1BITS 0x00000001 /* cycles to stay in P1 phase for PIO */ 90 #define SEEQ_HPIO_P2BITS 0x00000060 /* cycles to stay in P2 phase for PIO */ 91 #define SEEQ_HPIO_P3BITS 0x00000100 /* cycles to stay in P3 phase for PIO */ 92 #define SEEQ_HDMA_D1BITS 0x00000006 /* cycles to stay in D1 phase for DMA */ 93 #define SEEQ_HDMA_D2BITS 0x00000020 /* cycles to stay in D2 phase for DMA */ 94 #define SEEQ_HDMA_D3BITS 0x00000000 /* cycles to stay in D3 phase for DMA */ 95 #define SEEQ_HDMA_TIMEO 0x00030000 /* cycles for DMA timeout */ 96 #define SEEQ_HCTL_NORM 0x00000000 /* Normal operation mode */ 97 #define SEEQ_HCTL_RESET 0x00000001 /* Reset Seeq8003 and HPC interface */ 98 #define SEEQ_HCTL_IPEND 0x00000002 /* IRQ is pending for the chip */ 99 #define SEEQ_HCTL_IPG 0x00001000 /* Inter-packet gap */ 100 #define SEEQ_HCTL_RFIX 0x00002000 /* At rxdc, clear end-of-packet */ 101 #define SEEQ_HCTL_EFIX 0x00004000 /* fixes intr status bit settings */ 102 #define SEEQ_HCTL_IFIX 0x00008000 /* enable startup timeouts */ 103 104 #endif /* !(_SGISEEQ_H) */ 105