11edb9ca6SSiva Reddy /* 10G controller driver for Samsung SoCs 21edb9ca6SSiva Reddy * 31edb9ca6SSiva Reddy * Copyright (C) 2013 Samsung Electronics Co., Ltd. 41edb9ca6SSiva Reddy * http://www.samsung.com 51edb9ca6SSiva Reddy * 61edb9ca6SSiva Reddy * Author: Siva Reddy Kallam <siva.kallam@samsung.com> 71edb9ca6SSiva Reddy * 81edb9ca6SSiva Reddy * This program is free software; you can redistribute it and/or modify 91edb9ca6SSiva Reddy * it under the terms of the GNU General Public License version 2 as 101edb9ca6SSiva Reddy * published by the Free Software Foundation. 111edb9ca6SSiva Reddy */ 121edb9ca6SSiva Reddy #ifndef __SXGBE_REGMAP_H__ 131edb9ca6SSiva Reddy #define __SXGBE_REGMAP_H__ 141edb9ca6SSiva Reddy 151edb9ca6SSiva Reddy /* SXGBE MAC Registers */ 161edb9ca6SSiva Reddy #define SXGBE_CORE_TX_CONFIG_REG 0x0000 171edb9ca6SSiva Reddy #define SXGBE_CORE_RX_CONFIG_REG 0x0004 181edb9ca6SSiva Reddy #define SXGBE_CORE_PKT_FILTER_REG 0x0008 191edb9ca6SSiva Reddy #define SXGBE_CORE_WATCHDOG_TIMEOUT_REG 0x000C 201edb9ca6SSiva Reddy #define SXGBE_CORE_HASH_TABLE_REG0 0x0010 211edb9ca6SSiva Reddy #define SXGBE_CORE_HASH_TABLE_REG1 0x0014 221edb9ca6SSiva Reddy #define SXGBE_CORE_HASH_TABLE_REG2 0x0018 231edb9ca6SSiva Reddy #define SXGBE_CORE_HASH_TABLE_REG3 0x001C 241edb9ca6SSiva Reddy #define SXGBE_CORE_HASH_TABLE_REG4 0x0020 251edb9ca6SSiva Reddy #define SXGBE_CORE_HASH_TABLE_REG5 0x0024 261edb9ca6SSiva Reddy #define SXGBE_CORE_HASH_TABLE_REG6 0x0028 271edb9ca6SSiva Reddy #define SXGBE_CORE_HASH_TABLE_REG7 0x002C 28acc18c14SGirish K S 29acc18c14SGirish K S /* EEE-LPI Registers */ 30acc18c14SGirish K S #define SXGBE_CORE_LPI_CTRL_STATUS 0x00D0 31acc18c14SGirish K S #define SXGBE_CORE_LPI_TIMER_CTRL 0x00D4 32acc18c14SGirish K S 331edb9ca6SSiva Reddy /* VLAN Specific Registers */ 341edb9ca6SSiva Reddy #define SXGBE_CORE_VLAN_TAG_REG 0x0050 351edb9ca6SSiva Reddy #define SXGBE_CORE_VLAN_HASHTAB_REG 0x0058 361edb9ca6SSiva Reddy #define SXGBE_CORE_VLAN_INSCTL_REG 0x0060 371edb9ca6SSiva Reddy #define SXGBE_CORE_VLAN_INNERCTL_REG 0x0064 381edb9ca6SSiva Reddy #define SXGBE_CORE_RX_ETHTYPE_MATCH_REG 0x006C 391edb9ca6SSiva Reddy 401edb9ca6SSiva Reddy /* Flow Contol Registers */ 411edb9ca6SSiva Reddy #define SXGBE_CORE_TX_Q0_FLOWCTL_REG 0x0070 421edb9ca6SSiva Reddy #define SXGBE_CORE_TX_Q1_FLOWCTL_REG 0x0074 431edb9ca6SSiva Reddy #define SXGBE_CORE_TX_Q2_FLOWCTL_REG 0x0078 441edb9ca6SSiva Reddy #define SXGBE_CORE_TX_Q3_FLOWCTL_REG 0x007C 451edb9ca6SSiva Reddy #define SXGBE_CORE_TX_Q4_FLOWCTL_REG 0x0080 461edb9ca6SSiva Reddy #define SXGBE_CORE_TX_Q5_FLOWCTL_REG 0x0084 471edb9ca6SSiva Reddy #define SXGBE_CORE_TX_Q6_FLOWCTL_REG 0x0088 481edb9ca6SSiva Reddy #define SXGBE_CORE_TX_Q7_FLOWCTL_REG 0x008C 491edb9ca6SSiva Reddy #define SXGBE_CORE_RX_FLOWCTL_REG 0x0090 501edb9ca6SSiva Reddy #define SXGBE_CORE_RX_CTL0_REG 0x00A0 511edb9ca6SSiva Reddy #define SXGBE_CORE_RX_CTL1_REG 0x00A4 521edb9ca6SSiva Reddy #define SXGBE_CORE_RX_CTL2_REG 0x00A8 531edb9ca6SSiva Reddy #define SXGBE_CORE_RX_CTL3_REG 0x00AC 541edb9ca6SSiva Reddy 55325b94f7SByungho An #define SXGBE_CORE_RXQ_ENABLE_MASK 0x0003 56325b94f7SByungho An #define SXGBE_CORE_RXQ_ENABLE 0x0002 57325b94f7SByungho An #define SXGBE_CORE_RXQ_DISABLE 0x0000 58325b94f7SByungho An 591edb9ca6SSiva Reddy /* Interrupt Registers */ 601edb9ca6SSiva Reddy #define SXGBE_CORE_INT_STATUS_REG 0x00B0 611edb9ca6SSiva Reddy #define SXGBE_CORE_INT_ENABLE_REG 0x00B4 621edb9ca6SSiva Reddy #define SXGBE_CORE_RXTX_ERR_STATUS_REG 0x00B8 631edb9ca6SSiva Reddy #define SXGBE_CORE_PMT_CTL_STATUS_REG 0x00C0 641edb9ca6SSiva Reddy #define SXGBE_CORE_RWK_PKT_FILTER_REG 0x00C4 651edb9ca6SSiva Reddy #define SXGBE_CORE_VERSION_REG 0x0110 661edb9ca6SSiva Reddy #define SXGBE_CORE_DEBUG_REG 0x0114 671edb9ca6SSiva Reddy #define SXGBE_CORE_HW_FEA_REG(index) (0x011C + index * 4) 681edb9ca6SSiva Reddy 691edb9ca6SSiva Reddy /* SMA(MDIO) module registers */ 701edb9ca6SSiva Reddy #define SXGBE_MDIO_SCMD_ADD_REG 0x0200 711edb9ca6SSiva Reddy #define SXGBE_MDIO_SCMD_DATA_REG 0x0204 721edb9ca6SSiva Reddy #define SXGBE_MDIO_CCMD_WADD_REG 0x0208 731edb9ca6SSiva Reddy #define SXGBE_MDIO_CCMD_WDATA_REG 0x020C 741edb9ca6SSiva Reddy #define SXGBE_MDIO_CSCAN_PORT_REG 0x0210 751edb9ca6SSiva Reddy #define SXGBE_MDIO_INT_STATUS_REG 0x0214 761edb9ca6SSiva Reddy #define SXGBE_MDIO_INT_ENABLE_REG 0x0218 771edb9ca6SSiva Reddy #define SXGBE_MDIO_PORT_CONDCON_REG 0x021C 781edb9ca6SSiva Reddy #define SXGBE_MDIO_CLAUSE22_PORT_REG 0x0220 791edb9ca6SSiva Reddy 801edb9ca6SSiva Reddy /* port specific, addr = 0-3 */ 811edb9ca6SSiva Reddy #define SXGBE_MDIO_DEV_BASE_REG 0x0230 821edb9ca6SSiva Reddy #define SXGBE_MDIO_PORT_DEV_REG(addr) \ 831edb9ca6SSiva Reddy (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x0) 841edb9ca6SSiva Reddy #define SXGBE_MDIO_PORT_LSTATUS_REG(addr) \ 851edb9ca6SSiva Reddy (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x4) 861edb9ca6SSiva Reddy #define SXGBE_MDIO_PORT_ALIVE_REG(addr) \ 871edb9ca6SSiva Reddy (SXGBE_MDIO_DEV_BASE_REG + (0x10 * addr) + 0x8) 881edb9ca6SSiva Reddy 891edb9ca6SSiva Reddy #define SXGBE_CORE_GPIO_CTL_REG 0x0278 901edb9ca6SSiva Reddy #define SXGBE_CORE_GPIO_STATUS_REG 0x027C 911edb9ca6SSiva Reddy 921edb9ca6SSiva Reddy /* Address registers for filtering */ 931edb9ca6SSiva Reddy #define SXGBE_CORE_ADD_BASE_REG 0x0300 941edb9ca6SSiva Reddy 951edb9ca6SSiva Reddy /* addr = 0-31 */ 961edb9ca6SSiva Reddy #define SXGBE_CORE_ADD_HIGHOFFSET(addr) \ 971edb9ca6SSiva Reddy (SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x0) 981edb9ca6SSiva Reddy #define SXGBE_CORE_ADD_LOWOFFSET(addr) \ 991edb9ca6SSiva Reddy (SXGBE_CORE_ADD_BASE_REG + (0x8 * addr) + 0x4) 1001edb9ca6SSiva Reddy 1011edb9ca6SSiva Reddy /* SXGBE MMC registers */ 1021edb9ca6SSiva Reddy #define SXGBE_MMC_CTL_REG 0x0800 1031edb9ca6SSiva Reddy #define SXGBE_MMC_RXINT_STATUS_REG 0x0804 1041edb9ca6SSiva Reddy #define SXGBE_MMC_TXINT_STATUS_REG 0x0808 1051edb9ca6SSiva Reddy #define SXGBE_MMC_RXINT_ENABLE_REG 0x080C 1061edb9ca6SSiva Reddy #define SXGBE_MMC_TXINT_ENABLE_REG 0x0810 1071edb9ca6SSiva Reddy 1081edb9ca6SSiva Reddy /* TX specific counters */ 1091edb9ca6SSiva Reddy #define SXGBE_MMC_TXOCTETHI_GBCNT_REG 0x0814 1101edb9ca6SSiva Reddy #define SXGBE_MMC_TXOCTETLO_GBCNT_REG 0x0818 1111edb9ca6SSiva Reddy #define SXGBE_MMC_TXFRAMELO_GBCNT_REG 0x081C 1121edb9ca6SSiva Reddy #define SXGBE_MMC_TXFRAMEHI_GBCNT_REG 0x0820 1131edb9ca6SSiva Reddy #define SXGBE_MMC_TXBROADLO_GCNT_REG 0x0824 1141edb9ca6SSiva Reddy #define SXGBE_MMC_TXBROADHI_GCNT_REG 0x0828 1151edb9ca6SSiva Reddy #define SXGBE_MMC_TXMULTILO_GCNT_REG 0x082C 1161edb9ca6SSiva Reddy #define SXGBE_MMC_TXMULTIHI_GCNT_REG 0x0830 1171edb9ca6SSiva Reddy #define SXGBE_MMC_TX64LO_GBCNT_REG 0x0834 1181edb9ca6SSiva Reddy #define SXGBE_MMC_TX64HI_GBCNT_REG 0x0838 1191edb9ca6SSiva Reddy #define SXGBE_MMC_TX65TO127LO_GBCNT_REG 0x083C 1201edb9ca6SSiva Reddy #define SXGBE_MMC_TX65TO127HI_GBCNT_REG 0x0840 1211edb9ca6SSiva Reddy #define SXGBE_MMC_TX128TO255LO_GBCNT_REG 0x0844 1221edb9ca6SSiva Reddy #define SXGBE_MMC_TX128TO255HI_GBCNT_REG 0x0848 1231edb9ca6SSiva Reddy #define SXGBE_MMC_TX256TO511LO_GBCNT_REG 0x084C 1241edb9ca6SSiva Reddy #define SXGBE_MMC_TX256TO511HI_GBCNT_REG 0x0850 1251edb9ca6SSiva Reddy #define SXGBE_MMC_TX512TO1023LO_GBCNT_REG 0x0854 1261edb9ca6SSiva Reddy #define SXGBE_MMC_TX512TO1023HI_GBCNT_REG 0x0858 1271edb9ca6SSiva Reddy #define SXGBE_MMC_TX1023TOMAXLO_GBCNT_REG 0x085C 1281edb9ca6SSiva Reddy #define SXGBE_MMC_TX1023TOMAXHI_GBCNT_REG 0x0860 1291edb9ca6SSiva Reddy #define SXGBE_MMC_TXUNICASTLO_GBCNT_REG 0x0864 1301edb9ca6SSiva Reddy #define SXGBE_MMC_TXUNICASTHI_GBCNT_REG 0x0868 1311edb9ca6SSiva Reddy #define SXGBE_MMC_TXMULTILO_GBCNT_REG 0x086C 1321edb9ca6SSiva Reddy #define SXGBE_MMC_TXMULTIHI_GBCNT_REG 0x0870 1331edb9ca6SSiva Reddy #define SXGBE_MMC_TXBROADLO_GBCNT_REG 0x0874 1341edb9ca6SSiva Reddy #define SXGBE_MMC_TXBROADHI_GBCNT_REG 0x0878 1351edb9ca6SSiva Reddy #define SXGBE_MMC_TXUFLWLO_GBCNT_REG 0x087C 1361edb9ca6SSiva Reddy #define SXGBE_MMC_TXUFLWHI_GBCNT_REG 0x0880 1371edb9ca6SSiva Reddy #define SXGBE_MMC_TXOCTETLO_GCNT_REG 0x0884 1381edb9ca6SSiva Reddy #define SXGBE_MMC_TXOCTETHI_GCNT_REG 0x0888 1391edb9ca6SSiva Reddy #define SXGBE_MMC_TXFRAMELO_GCNT_REG 0x088C 1401edb9ca6SSiva Reddy #define SXGBE_MMC_TXFRAMEHI_GCNT_REG 0x0890 1411edb9ca6SSiva Reddy #define SXGBE_MMC_TXPAUSELO_CNT_REG 0x0894 1421edb9ca6SSiva Reddy #define SXGBE_MMC_TXPAUSEHI_CNT_REG 0x0898 1431edb9ca6SSiva Reddy #define SXGBE_MMC_TXVLANLO_GCNT_REG 0x089C 1441edb9ca6SSiva Reddy #define SXGBE_MMC_TXVLANHI_GCNT_REG 0x08A0 1451edb9ca6SSiva Reddy 1461edb9ca6SSiva Reddy /* RX specific counters */ 1471edb9ca6SSiva Reddy #define SXGBE_MMC_RXFRAMELO_GBCNT_REG 0x0900 1481edb9ca6SSiva Reddy #define SXGBE_MMC_RXFRAMEHI_GBCNT_REG 0x0904 1491edb9ca6SSiva Reddy #define SXGBE_MMC_RXOCTETLO_GBCNT_REG 0x0908 1501edb9ca6SSiva Reddy #define SXGBE_MMC_RXOCTETHI_GBCNT_REG 0x090C 1511edb9ca6SSiva Reddy #define SXGBE_MMC_RXOCTETLO_GCNT_REG 0x0910 1521edb9ca6SSiva Reddy #define SXGBE_MMC_RXOCTETHI_GCNT_REG 0x0914 1531edb9ca6SSiva Reddy #define SXGBE_MMC_RXBROADLO_GCNT_REG 0x0918 1541edb9ca6SSiva Reddy #define SXGBE_MMC_RXBROADHI_GCNT_REG 0x091C 1551edb9ca6SSiva Reddy #define SXGBE_MMC_RXMULTILO_GCNT_REG 0x0920 1561edb9ca6SSiva Reddy #define SXGBE_MMC_RXMULTIHI_GCNT_REG 0x0924 1571edb9ca6SSiva Reddy #define SXGBE_MMC_RXCRCERRLO_REG 0x0928 1581edb9ca6SSiva Reddy #define SXGBE_MMC_RXCRCERRHI_REG 0x092C 1591edb9ca6SSiva Reddy #define SXGBE_MMC_RXSHORT64BFRAME_ERR_REG 0x0930 1601edb9ca6SSiva Reddy #define SXGBE_MMC_RXJABBERERR_REG 0x0934 1611edb9ca6SSiva Reddy #define SXGBE_MMC_RXSHORT64BFRAME_COR_REG 0x0938 1621edb9ca6SSiva Reddy #define SXGBE_MMC_RXOVERMAXFRAME_COR_REG 0x093C 1631edb9ca6SSiva Reddy #define SXGBE_MMC_RX64LO_GBCNT_REG 0x0940 1641edb9ca6SSiva Reddy #define SXGBE_MMC_RX64HI_GBCNT_REG 0x0944 1651edb9ca6SSiva Reddy #define SXGBE_MMC_RX65TO127LO_GBCNT_REG 0x0948 1661edb9ca6SSiva Reddy #define SXGBE_MMC_RX65TO127HI_GBCNT_REG 0x094C 1671edb9ca6SSiva Reddy #define SXGBE_MMC_RX128TO255LO_GBCNT_REG 0x0950 1681edb9ca6SSiva Reddy #define SXGBE_MMC_RX128TO255HI_GBCNT_REG 0x0954 1691edb9ca6SSiva Reddy #define SXGBE_MMC_RX256TO511LO_GBCNT_REG 0x0958 1701edb9ca6SSiva Reddy #define SXGBE_MMC_RX256TO511HI_GBCNT_REG 0x095C 1711edb9ca6SSiva Reddy #define SXGBE_MMC_RX512TO1023LO_GBCNT_REG 0x0960 1721edb9ca6SSiva Reddy #define SXGBE_MMC_RX512TO1023HI_GBCNT_REG 0x0964 1731edb9ca6SSiva Reddy #define SXGBE_MMC_RX1023TOMAXLO_GBCNT_REG 0x0968 1741edb9ca6SSiva Reddy #define SXGBE_MMC_RX1023TOMAXHI_GBCNT_REG 0x096C 1751edb9ca6SSiva Reddy #define SXGBE_MMC_RXUNICASTLO_GCNT_REG 0x0970 1761edb9ca6SSiva Reddy #define SXGBE_MMC_RXUNICASTHI_GCNT_REG 0x0974 1771edb9ca6SSiva Reddy #define SXGBE_MMC_RXLENERRLO_REG 0x0978 1781edb9ca6SSiva Reddy #define SXGBE_MMC_RXLENERRHI_REG 0x097C 1791edb9ca6SSiva Reddy #define SXGBE_MMC_RXOUTOFRANGETYPELO_REG 0x0980 1801edb9ca6SSiva Reddy #define SXGBE_MMC_RXOUTOFRANGETYPEHI_REG 0x0984 1811edb9ca6SSiva Reddy #define SXGBE_MMC_RXPAUSELO_CNT_REG 0x0988 1821edb9ca6SSiva Reddy #define SXGBE_MMC_RXPAUSEHI_CNT_REG 0x098C 1831edb9ca6SSiva Reddy #define SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG 0x0990 1841edb9ca6SSiva Reddy #define SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG 0x0994 1851edb9ca6SSiva Reddy #define SXGBE_MMC_RXVLANLO_GBCNT_REG 0x0998 1861edb9ca6SSiva Reddy #define SXGBE_MMC_RXVLANHI_GBCNT_REG 0x099C 1871edb9ca6SSiva Reddy #define SXGBE_MMC_RXWATCHDOG_ERR_REG 0x09A0 1881edb9ca6SSiva Reddy 1891edb9ca6SSiva Reddy /* L3/L4 function registers */ 1901edb9ca6SSiva Reddy #define SXGBE_CORE_L34_ADDCTL_REG 0x0C00 1911edb9ca6SSiva Reddy #define SXGBE_CORE_L34_ADDCTL_REG 0x0C00 1921edb9ca6SSiva Reddy #define SXGBE_CORE_L34_DATA_REG 0x0C04 1931edb9ca6SSiva Reddy 1941edb9ca6SSiva Reddy /* ARP registers */ 1951edb9ca6SSiva Reddy #define SXGBE_CORE_ARP_ADD_REG 0x0C10 1961edb9ca6SSiva Reddy 1971edb9ca6SSiva Reddy /* RSS registers */ 1981edb9ca6SSiva Reddy #define SXGBE_CORE_RSS_CTL_REG 0x0C80 1991edb9ca6SSiva Reddy #define SXGBE_CORE_RSS_ADD_REG 0x0C88 2001edb9ca6SSiva Reddy #define SXGBE_CORE_RSS_DATA_REG 0x0C8C 2011edb9ca6SSiva Reddy 20225f72a74SVipul Pandya /* RSS control register bits */ 20325f72a74SVipul Pandya #define SXGBE_CORE_RSS_CTL_UDP4TE BIT(3) 20425f72a74SVipul Pandya #define SXGBE_CORE_RSS_CTL_TCP4TE BIT(2) 20525f72a74SVipul Pandya #define SXGBE_CORE_RSS_CTL_IP2TE BIT(1) 20625f72a74SVipul Pandya #define SXGBE_CORE_RSS_CTL_RSSE BIT(0) 20725f72a74SVipul Pandya 2081edb9ca6SSiva Reddy /* IEEE 1588 registers */ 2091edb9ca6SSiva Reddy #define SXGBE_CORE_TSTAMP_CTL_REG 0x0D00 2101edb9ca6SSiva Reddy #define SXGBE_CORE_SUBSEC_INC_REG 0x0D04 2111edb9ca6SSiva Reddy #define SXGBE_CORE_SYSTIME_SEC_REG 0x0D0C 2121edb9ca6SSiva Reddy #define SXGBE_CORE_SYSTIME_NSEC_REG 0x0D10 2131edb9ca6SSiva Reddy #define SXGBE_CORE_SYSTIME_SECUP_REG 0x0D14 2141edb9ca6SSiva Reddy #define SXGBE_CORE_TSTAMP_ADD_REG 0x0D18 2151edb9ca6SSiva Reddy #define SXGBE_CORE_SYSTIME_HWORD_REG 0x0D1C 2161edb9ca6SSiva Reddy #define SXGBE_CORE_TSTAMP_STATUS_REG 0x0D20 2171edb9ca6SSiva Reddy #define SXGBE_CORE_TXTIME_STATUSNSEC_REG 0x0D30 2181edb9ca6SSiva Reddy #define SXGBE_CORE_TXTIME_STATUSSEC_REG 0x0D34 2191edb9ca6SSiva Reddy 2201edb9ca6SSiva Reddy /* Auxiliary registers */ 2211edb9ca6SSiva Reddy #define SXGBE_CORE_AUX_CTL_REG 0x0D40 2221edb9ca6SSiva Reddy #define SXGBE_CORE_AUX_TSTAMP_NSEC_REG 0x0D48 2231edb9ca6SSiva Reddy #define SXGBE_CORE_AUX_TSTAMP_SEC_REG 0x0D4C 2241edb9ca6SSiva Reddy #define SXGBE_CORE_AUX_TSTAMP_INGCOR_REG 0x0D50 2251edb9ca6SSiva Reddy #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_REG 0x0D54 2261edb9ca6SSiva Reddy #define SXGBE_CORE_AUX_TSTAMP_INGCOR_NSEC_REG 0x0D58 2271edb9ca6SSiva Reddy #define SXGBE_CORE_AUX_TSTAMP_INGCOR_SUBNSEC_REG 0x0D5C 2281edb9ca6SSiva Reddy #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_NSEC_REG 0x0D60 2291edb9ca6SSiva Reddy #define SXGBE_CORE_AUX_TSTAMP_ENGCOR_SUBNSEC_REG 0x0D64 2301edb9ca6SSiva Reddy 2311edb9ca6SSiva Reddy /* PPS registers */ 2321edb9ca6SSiva Reddy #define SXGBE_CORE_PPS_CTL_REG 0x0D70 2331edb9ca6SSiva Reddy #define SXGBE_CORE_PPS_BASE 0x0D80 2341edb9ca6SSiva Reddy 2351edb9ca6SSiva Reddy /* addr = 0 - 3 */ 2361edb9ca6SSiva Reddy #define SXGBE_CORE_PPS_TTIME_SEC_REG(addr) \ 2371edb9ca6SSiva Reddy (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x0) 2381edb9ca6SSiva Reddy #define SXGBE_CORE_PPS_TTIME_NSEC_REG(addr) \ 2391edb9ca6SSiva Reddy (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x4) 2401edb9ca6SSiva Reddy #define SXGBE_CORE_PPS_INTERVAL_REG(addr) \ 2411edb9ca6SSiva Reddy (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0x8) 2421edb9ca6SSiva Reddy #define SXGBE_CORE_PPS_WIDTH_REG(addr) \ 2431edb9ca6SSiva Reddy (SXGBE_CORE_PPS_BASE + (0x10 * addr) + 0xC) 2441edb9ca6SSiva Reddy #define SXGBE_CORE_PTO_CTL_REG 0x0DC0 2451edb9ca6SSiva Reddy #define SXGBE_CORE_SRCPORT_ITY0_REG 0x0DC4 2461edb9ca6SSiva Reddy #define SXGBE_CORE_SRCPORT_ITY1_REG 0x0DC8 2471edb9ca6SSiva Reddy #define SXGBE_CORE_SRCPORT_ITY2_REG 0x0DCC 2481edb9ca6SSiva Reddy #define SXGBE_CORE_LOGMSG_LEVEL_REG 0x0DD0 2491edb9ca6SSiva Reddy 2501edb9ca6SSiva Reddy /* SXGBE MTL Registers */ 2511edb9ca6SSiva Reddy #define SXGBE_MTL_BASE_REG 0x1000 2521edb9ca6SSiva Reddy #define SXGBE_MTL_OP_MODE_REG (SXGBE_MTL_BASE_REG + 0x0000) 2531edb9ca6SSiva Reddy #define SXGBE_MTL_DEBUG_CTL_REG (SXGBE_MTL_BASE_REG + 0x0008) 2541edb9ca6SSiva Reddy #define SXGBE_MTL_DEBUG_STATUS_REG (SXGBE_MTL_BASE_REG + 0x000C) 2551edb9ca6SSiva Reddy #define SXGBE_MTL_FIFO_DEBUGDATA_REG (SXGBE_MTL_BASE_REG + 0x0010) 2561edb9ca6SSiva Reddy #define SXGBE_MTL_INT_STATUS_REG (SXGBE_MTL_BASE_REG + 0x0020) 2571edb9ca6SSiva Reddy #define SXGBE_MTL_RXQ_DMAMAP0_REG (SXGBE_MTL_BASE_REG + 0x0030) 2581edb9ca6SSiva Reddy #define SXGBE_MTL_RXQ_DMAMAP1_REG (SXGBE_MTL_BASE_REG + 0x0034) 2591edb9ca6SSiva Reddy #define SXGBE_MTL_RXQ_DMAMAP2_REG (SXGBE_MTL_BASE_REG + 0x0038) 2601edb9ca6SSiva Reddy #define SXGBE_MTL_TX_PRTYMAP0_REG (SXGBE_MTL_BASE_REG + 0x0040) 2611edb9ca6SSiva Reddy #define SXGBE_MTL_TX_PRTYMAP1_REG (SXGBE_MTL_BASE_REG + 0x0044) 2621edb9ca6SSiva Reddy 2631edb9ca6SSiva Reddy /* TC/Queue registers, qnum=0-15 */ 2641edb9ca6SSiva Reddy #define SXGBE_MTL_TC_TXBASE_REG (SXGBE_MTL_BASE_REG + 0x0100) 2651edb9ca6SSiva Reddy #define SXGBE_MTL_TXQ_OPMODE_REG(qnum) \ 2661edb9ca6SSiva Reddy (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x00) 2671edb9ca6SSiva Reddy #define SXGBE_MTL_SFMODE BIT(1) 2681edb9ca6SSiva Reddy #define SXGBE_MTL_FIFO_LSHIFT 16 2691edb9ca6SSiva Reddy #define SXGBE_MTL_ENABLE_QUEUE 0x00000008 2701edb9ca6SSiva Reddy #define SXGBE_MTL_TXQ_UNDERFLOW_REG(qnum) \ 2711edb9ca6SSiva Reddy (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x04) 2721edb9ca6SSiva Reddy #define SXGBE_MTL_TXQ_DEBUG_REG(qnum) \ 2731edb9ca6SSiva Reddy (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x08) 2741edb9ca6SSiva Reddy #define SXGBE_MTL_TXQ_ETSCTL_REG(qnum) \ 2751edb9ca6SSiva Reddy (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x10) 2761edb9ca6SSiva Reddy #define SXGBE_MTL_TXQ_ETSSTATUS_REG(qnum) \ 2771edb9ca6SSiva Reddy (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x14) 2781edb9ca6SSiva Reddy #define SXGBE_MTL_TXQ_QUANTWEIGHT_REG(qnum) \ 2791edb9ca6SSiva Reddy (SXGBE_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x18) 2801edb9ca6SSiva Reddy 2811edb9ca6SSiva Reddy #define SXGBE_MTL_TC_RXBASE_REG 0x1140 2821edb9ca6SSiva Reddy #define SXGBE_RX_MTL_SFMODE BIT(5) 2831edb9ca6SSiva Reddy #define SXGBE_MTL_RXQ_OPMODE_REG(qnum) \ 2841edb9ca6SSiva Reddy (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x00) 2851edb9ca6SSiva Reddy #define SXGBE_MTL_RXQ_MISPKTOVERFLOW_REG(qnum) \ 2861edb9ca6SSiva Reddy (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x04) 2871edb9ca6SSiva Reddy #define SXGBE_MTL_RXQ_DEBUG_REG(qnum) \ 2881edb9ca6SSiva Reddy (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x08) 2891edb9ca6SSiva Reddy #define SXGBE_MTL_RXQ_CTL_REG(qnum) \ 2901edb9ca6SSiva Reddy (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x0C) 2911edb9ca6SSiva Reddy #define SXGBE_MTL_RXQ_INTENABLE_REG(qnum) \ 2921edb9ca6SSiva Reddy (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x30) 2931edb9ca6SSiva Reddy #define SXGBE_MTL_RXQ_INTSTATUS_REG(qnum) \ 2941edb9ca6SSiva Reddy (SXGBE_MTL_TC_RXBASE_REG + (qnum * 0x80) + 0x34) 2951edb9ca6SSiva Reddy 2961edb9ca6SSiva Reddy /* SXGBE DMA Registers */ 2971edb9ca6SSiva Reddy #define SXGBE_DMA_BASE_REG 0x3000 2981edb9ca6SSiva Reddy #define SXGBE_DMA_MODE_REG (SXGBE_DMA_BASE_REG + 0x0000) 2991edb9ca6SSiva Reddy #define SXGBE_DMA_SOFT_RESET BIT(0) 3001edb9ca6SSiva Reddy #define SXGBE_DMA_SYSBUS_MODE_REG (SXGBE_DMA_BASE_REG + 0x0004) 3011edb9ca6SSiva Reddy #define SXGBE_DMA_AXI_UNDEF_BURST BIT(0) 3021edb9ca6SSiva Reddy #define SXGBE_DMA_ENHACE_ADDR_MODE BIT(11) 3031edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_REG (SXGBE_DMA_BASE_REG + 0x0008) 3041edb9ca6SSiva Reddy #define SXGBE_DMA_AXI_ARCACHECTL_REG (SXGBE_DMA_BASE_REG + 0x0010) 3051edb9ca6SSiva Reddy #define SXGBE_DMA_AXI_AWCACHECTL_REG (SXGBE_DMA_BASE_REG + 0x0018) 3061edb9ca6SSiva Reddy #define SXGBE_DMA_DEBUG_STATUS0_REG (SXGBE_DMA_BASE_REG + 0x0020) 3071edb9ca6SSiva Reddy #define SXGBE_DMA_DEBUG_STATUS1_REG (SXGBE_DMA_BASE_REG + 0x0024) 3081edb9ca6SSiva Reddy #define SXGBE_DMA_DEBUG_STATUS2_REG (SXGBE_DMA_BASE_REG + 0x0028) 3091edb9ca6SSiva Reddy #define SXGBE_DMA_DEBUG_STATUS3_REG (SXGBE_DMA_BASE_REG + 0x002C) 3101edb9ca6SSiva Reddy #define SXGBE_DMA_DEBUG_STATUS4_REG (SXGBE_DMA_BASE_REG + 0x0030) 3111edb9ca6SSiva Reddy #define SXGBE_DMA_DEBUG_STATUS5_REG (SXGBE_DMA_BASE_REG + 0x0034) 3121edb9ca6SSiva Reddy 3131edb9ca6SSiva Reddy /* Channel Registers, cha_num = 0-15 */ 3141edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_BASE_REG \ 3151edb9ca6SSiva Reddy (SXGBE_DMA_BASE_REG + 0x0100) 3161edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_CTL_REG(cha_num) \ 3171edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x00) 3181edb9ca6SSiva Reddy #define SXGBE_DMA_PBL_X8MODE BIT(16) 3191edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_TXCTL_TSE_ENABLE BIT(12) 3201edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_TXCTL_REG(cha_num) \ 3211edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x04) 3221edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_RXCTL_REG(cha_num) \ 3231edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x08) 3241edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num) \ 3251edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x10) 3261edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num) \ 3271edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x14) 3281edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num) \ 3291edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x18) 3301edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num) \ 3311edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x1C) 3321edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_TXDESC_TAILPTR_REG(cha_num) \ 3331edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x24) 3341edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_RXDESC_TAILPTR_REG(cha_num) \ 3351edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x2C) 3361edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num) \ 3371edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x30) 3381edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num) \ 3391edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x34) 3401edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_INT_ENABLE_REG(cha_num) \ 3411edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x38) 3421edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_INT_RXWATCHTMR_REG(cha_num) \ 3431edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x3C) 3441edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_TXDESC_CURADDLO_REG(cha_num) \ 3451edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x44) 3461edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_RXDESC_CURADDLO_REG(cha_num) \ 3471edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x4C) 3481edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_CURTXBUF_ADDHI_REG(cha_num) \ 3491edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x50) 3501edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_CURTXBUF_ADDLO_REG(cha_num) \ 3511edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x54) 3521edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_CURRXBUF_ADDHI_REG(cha_num) \ 3531edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x58) 3541edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_CURRXBUF_ADDLO_REG(cha_num) \ 3551edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x5C) 3561edb9ca6SSiva Reddy #define SXGBE_DMA_CHA_STATUS_REG(cha_num) \ 3571edb9ca6SSiva Reddy (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x60) 3581edb9ca6SSiva Reddy 3591edb9ca6SSiva Reddy /* TX DMA control register specific */ 3601edb9ca6SSiva Reddy #define SXGBE_TX_START_DMA BIT(0) 3611edb9ca6SSiva Reddy 3621edb9ca6SSiva Reddy /* sxgbe tx configuration register bitfields */ 3631edb9ca6SSiva Reddy #define SXGBE_SPEED_10G 0x0 3641edb9ca6SSiva Reddy #define SXGBE_SPEED_2_5G 0x1 3651edb9ca6SSiva Reddy #define SXGBE_SPEED_1G 0x2 3661edb9ca6SSiva Reddy #define SXGBE_SPEED_LSHIFT 29 3671edb9ca6SSiva Reddy 3681edb9ca6SSiva Reddy #define SXGBE_TX_ENABLE BIT(0) 3691edb9ca6SSiva Reddy #define SXGBE_TX_DISDIC_ALGO BIT(1) 3701edb9ca6SSiva Reddy #define SXGBE_TX_JABBER_DISABLE BIT(16) 3711edb9ca6SSiva Reddy 3721edb9ca6SSiva Reddy /* sxgbe rx configuration register bitfields */ 3731edb9ca6SSiva Reddy #define SXGBE_RX_ENABLE BIT(0) 3741edb9ca6SSiva Reddy #define SXGBE_RX_ACS_ENABLE BIT(1) 3751edb9ca6SSiva Reddy #define SXGBE_RX_WATCHDOG_DISABLE BIT(7) 3761edb9ca6SSiva Reddy #define SXGBE_RX_JUMBPKT_ENABLE BIT(8) 3771edb9ca6SSiva Reddy #define SXGBE_RX_CSUMOFFLOAD_ENABLE BIT(9) 3781edb9ca6SSiva Reddy #define SXGBE_RX_LOOPBACK_ENABLE BIT(10) 3791edb9ca6SSiva Reddy #define SXGBE_RX_ARPOFFLOAD_ENABLE BIT(31) 3801edb9ca6SSiva Reddy 3811edb9ca6SSiva Reddy /* sxgbe vlan Tag Register bitfields */ 3821edb9ca6SSiva Reddy #define SXGBE_VLAN_SVLAN_ENABLE BIT(18) 3831edb9ca6SSiva Reddy #define SXGBE_VLAN_DOUBLEVLAN_ENABLE BIT(26) 3841edb9ca6SSiva Reddy #define SXGBE_VLAN_INNERVLAN_ENABLE BIT(27) 3851edb9ca6SSiva Reddy 3861edb9ca6SSiva Reddy /* XMAC VLAN Tag Inclusion Register(0x0060) bitfields 3871edb9ca6SSiva Reddy * Below fields same for Inner VLAN Tag Inclusion 3881edb9ca6SSiva Reddy * Register(0x0064) register 3891edb9ca6SSiva Reddy */ 3901edb9ca6SSiva Reddy enum vlan_tag_ctl_tx { 3911edb9ca6SSiva Reddy VLAN_TAG_TX_NOP, 3921edb9ca6SSiva Reddy VLAN_TAG_TX_DEL, 3931edb9ca6SSiva Reddy VLAN_TAG_TX_INSERT, 3941edb9ca6SSiva Reddy VLAN_TAG_TX_REPLACE 3951edb9ca6SSiva Reddy }; 3961edb9ca6SSiva Reddy #define SXGBE_VLAN_PRTY_CTL BIT(18) 3971edb9ca6SSiva Reddy #define SXGBE_VLAN_CSVL_CTL BIT(19) 3981edb9ca6SSiva Reddy 3991edb9ca6SSiva Reddy /* SXGBE TX Q Flow Control Register bitfields */ 4001edb9ca6SSiva Reddy #define SXGBE_TX_FLOW_CTL_FCB BIT(0) 4011edb9ca6SSiva Reddy #define SXGBE_TX_FLOW_CTL_TFB BIT(1) 4021edb9ca6SSiva Reddy 4031edb9ca6SSiva Reddy /* SXGBE RX Q Flow Control Register bitfields */ 4041edb9ca6SSiva Reddy #define SXGBE_RX_FLOW_CTL_ENABLE BIT(0) 4051edb9ca6SSiva Reddy #define SXGBE_RX_UNICAST_DETECT BIT(1) 4061edb9ca6SSiva Reddy #define SXGBE_RX_PRTYFLOW_CTL_ENABLE BIT(8) 4071edb9ca6SSiva Reddy 4081edb9ca6SSiva Reddy /* sxgbe rx Q control0 register bitfields */ 4091edb9ca6SSiva Reddy #define SXGBE_RX_Q_ENABLE 0x2 4101edb9ca6SSiva Reddy 4111edb9ca6SSiva Reddy /* SXGBE hardware features bitfield specific */ 4121edb9ca6SSiva Reddy /* Capability Register 0 */ 4131edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_GMII(cap) ((cap & 0x00000002) >> 1) 4141edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_VLAN_HASH_FILTER(cap) ((cap & 0x00000010) >> 4) 4151edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_SMA(cap) ((cap & 0x00000020) >> 5) 4161edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_PMT_TEMOTE_WOP(cap) ((cap & 0x00000040) >> 6) 4171edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_PMT_MAGIC_PKT(cap) ((cap & 0x00000080) >> 7) 4181edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_RMON(cap) ((cap & 0x00000100) >> 8) 4191edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_ARP_OFFLOAD(cap) ((cap & 0x00000200) >> 9) 4201edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_IEEE1500_2008(cap) ((cap & 0x00001000) >> 12) 4211edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_EEE(cap) ((cap & 0x00002000) >> 13) 4221edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(cap) ((cap & 0x00004000) >> 14) 4231edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(cap) ((cap & 0x00010000) >> 16) 4241edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_MACADDR_COUNT(cap) ((cap & 0x007C0000) >> 18) 4251edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_TSTMAP_SRC(cap) ((cap & 0x06000000) >> 25) 4261edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_SRCADDR_VLAN(cap) ((cap & 0x08000000) >> 27) 4271edb9ca6SSiva Reddy 4281edb9ca6SSiva Reddy /* Capability Register 1 */ 4291edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_RX_FIFO_SIZE(cap) ((cap & 0x0000001F)) 4301edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_TX_FIFO_SIZE(cap) ((cap & 0x000007C0) >> 6) 4311edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_IEEE1588_HWORD(cap) ((cap & 0x00002000) >> 13) 4321edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_DCB(cap) ((cap & 0x00010000) >> 16) 4331edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_SPLIT_HDR(cap) ((cap & 0x00020000) >> 17) 4341edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_TSO(cap) ((cap & 0x00040000) >> 18) 4351edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_DEBUG_MEM_IFACE(cap) ((cap & 0x00080000) >> 19) 4361edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_RSS(cap) ((cap & 0x00100000) >> 20) 4371edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_HASH_TABLE_SIZE(cap) ((cap & 0x03000000) >> 24) 4381edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_L3L4_FILTER_NUM(cap) ((cap & 0x78000000) >> 27) 4391edb9ca6SSiva Reddy 4401edb9ca6SSiva Reddy /* Capability Register 2 */ 4411edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_RX_MTL_QUEUES(cap) ((cap & 0x0000000F)) 4421edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_TX_MTL_QUEUES(cap) ((cap & 0x000003C0) >> 6) 4431edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_RX_DMA_CHANNELS(cap) ((cap & 0x0000F000) >> 12) 4441edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_TX_DMA_CHANNELS(cap) ((cap & 0x003C0000) >> 18) 4451edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_PPS_OUTPUTS(cap) ((cap & 0x07000000) >> 24) 4461edb9ca6SSiva Reddy #define SXGBE_HW_FEAT_AUX_SNAPSHOTS(cap) ((cap & 0x70000000) >> 28) 4471edb9ca6SSiva Reddy 4481edb9ca6SSiva Reddy /* DMAchannel interrupt enable specific */ 4491edb9ca6SSiva Reddy /* DMA Normal interrupt */ 4501edb9ca6SSiva Reddy #define SXGBE_DMA_INT_ENA_NIE BIT(16) /* Normal Summary */ 4511edb9ca6SSiva Reddy #define SXGBE_DMA_INT_ENA_TIE BIT(0) /* Transmit Interrupt */ 4521edb9ca6SSiva Reddy #define SXGBE_DMA_INT_ENA_TUE BIT(2) /* Transmit Buffer Unavailable */ 4531edb9ca6SSiva Reddy #define SXGBE_DMA_INT_ENA_RIE BIT(6) /* Receive Interrupt */ 4541edb9ca6SSiva Reddy 4551edb9ca6SSiva Reddy #define SXGBE_DMA_INT_NORMAL \ 4561edb9ca6SSiva Reddy (SXGBE_DMA_INT_ENA_NIE | SXGBE_DMA_INT_ENA_RIE | \ 4571edb9ca6SSiva Reddy SXGBE_DMA_INT_ENA_TIE | SXGBE_DMA_INT_ENA_TUE) 4581edb9ca6SSiva Reddy 4591edb9ca6SSiva Reddy /* DMA Abnormal interrupt */ 4601edb9ca6SSiva Reddy #define SXGBE_DMA_INT_ENA_AIE BIT(15) /* Abnormal Summary */ 4611edb9ca6SSiva Reddy #define SXGBE_DMA_INT_ENA_TSE BIT(1) /* Transmit Stopped */ 4621edb9ca6SSiva Reddy #define SXGBE_DMA_INT_ENA_RUE BIT(7) /* Receive Buffer Unavailable */ 4631edb9ca6SSiva Reddy #define SXGBE_DMA_INT_ENA_RSE BIT(8) /* Receive Stopped */ 4641edb9ca6SSiva Reddy #define SXGBE_DMA_INT_ENA_FBE BIT(12) /* Fatal Bus Error */ 4651edb9ca6SSiva Reddy #define SXGBE_DMA_INT_ENA_CDEE BIT(13) /* Context Descriptor Error */ 4661edb9ca6SSiva Reddy 4671edb9ca6SSiva Reddy #define SXGBE_DMA_INT_ABNORMAL \ 4681edb9ca6SSiva Reddy (SXGBE_DMA_INT_ENA_AIE | SXGBE_DMA_INT_ENA_TSE | \ 4691edb9ca6SSiva Reddy SXGBE_DMA_INT_ENA_RUE | SXGBE_DMA_INT_ENA_RSE | \ 4701edb9ca6SSiva Reddy SXGBE_DMA_INT_ENA_FBE | SXGBE_DMA_INT_ENA_CDEE) 4711edb9ca6SSiva Reddy 4721edb9ca6SSiva Reddy #define SXGBE_DMA_ENA_INT (SXGBE_DMA_INT_NORMAL | SXGBE_DMA_INT_ABNORMAL) 4731edb9ca6SSiva Reddy 4741edb9ca6SSiva Reddy /* DMA channel interrupt status specific */ 4751edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_REB2 BIT(21) 4761edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_REB1 BIT(20) 4771edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_REB0 BIT(19) 4781edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_TEB2 BIT(18) 4791edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_TEB1 BIT(17) 4801edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_TEB0 BIT(16) 4811edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_NIS BIT(15) 4821edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_AIS BIT(14) 4831edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_CTXTERR BIT(13) 4841edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_FBE BIT(12) 4851edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_RPS BIT(8) 4861edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_RBU BIT(7) 4871edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_RI BIT(6) 4881edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_TBU BIT(2) 4891edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_TPS BIT(1) 4901edb9ca6SSiva Reddy #define SXGBE_DMA_INT_STATUS_TI BIT(0) 4911edb9ca6SSiva Reddy 4921edb9ca6SSiva Reddy #endif /* __SXGBE_REGMAP_H__ */ 493