1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 21edb9ca6SSiva Reddy /* 10G controller driver for Samsung SoCs 31edb9ca6SSiva Reddy * 41edb9ca6SSiva Reddy * Copyright (C) 2013 Samsung Electronics Co., Ltd. 51edb9ca6SSiva Reddy * http://www.samsung.com 61edb9ca6SSiva Reddy * 71edb9ca6SSiva Reddy * Author: Siva Reddy Kallam <siva.kallam@samsung.com> 81edb9ca6SSiva Reddy */ 91edb9ca6SSiva Reddy #ifndef __SXGBE_MTL_H__ 101edb9ca6SSiva Reddy #define __SXGBE_MTL_H__ 111edb9ca6SSiva Reddy 121edb9ca6SSiva Reddy #define SXGBE_MTL_OPMODE_ESTMASK 0x3 131edb9ca6SSiva Reddy #define SXGBE_MTL_OPMODE_RAAMASK 0x1 141edb9ca6SSiva Reddy #define SXGBE_MTL_FCMASK 0x7 151edb9ca6SSiva Reddy #define SXGBE_MTL_TX_FIFO_DIV 256 161edb9ca6SSiva Reddy #define SXGBE_MTL_RX_FIFO_DIV 256 171edb9ca6SSiva Reddy 181edb9ca6SSiva Reddy #define SXGBE_MTL_RXQ_OP_FEP BIT(4) 191edb9ca6SSiva Reddy #define SXGBE_MTL_RXQ_OP_FUP BIT(3) 201edb9ca6SSiva Reddy #define SXGBE_MTL_ENABLE_FC 0x80 211edb9ca6SSiva Reddy 221edb9ca6SSiva Reddy #define ETS_WRR 0xFFFFFF9F 231edb9ca6SSiva Reddy #define ETS_RST 0xFFFFFF9F 241edb9ca6SSiva Reddy #define ETS_WFQ 0x00000020 251edb9ca6SSiva Reddy #define ETS_DWRR 0x00000040 261edb9ca6SSiva Reddy #define RAA_SP 0xFFFFFFFB 271edb9ca6SSiva Reddy #define RAA_WSP 0x00000004 281edb9ca6SSiva Reddy 291edb9ca6SSiva Reddy #define RX_QUEUE_DYNAMIC 0x80808080 301edb9ca6SSiva Reddy #define RX_FC_ACTIVE 8 311edb9ca6SSiva Reddy #define RX_FC_DEACTIVE 13 321edb9ca6SSiva Reddy 331edb9ca6SSiva Reddy enum ttc_control { 341edb9ca6SSiva Reddy MTL_CONTROL_TTC_64 = 0x00000000, 351edb9ca6SSiva Reddy MTL_CONTROL_TTC_96 = 0x00000020, 361edb9ca6SSiva Reddy MTL_CONTROL_TTC_128 = 0x00000030, 371edb9ca6SSiva Reddy MTL_CONTROL_TTC_192 = 0x00000040, 381edb9ca6SSiva Reddy MTL_CONTROL_TTC_256 = 0x00000050, 391edb9ca6SSiva Reddy MTL_CONTROL_TTC_384 = 0x00000060, 401edb9ca6SSiva Reddy MTL_CONTROL_TTC_512 = 0x00000070, 411edb9ca6SSiva Reddy }; 421edb9ca6SSiva Reddy 431edb9ca6SSiva Reddy enum rtc_control { 441edb9ca6SSiva Reddy MTL_CONTROL_RTC_64 = 0x00000000, 451edb9ca6SSiva Reddy MTL_CONTROL_RTC_96 = 0x00000002, 461edb9ca6SSiva Reddy MTL_CONTROL_RTC_128 = 0x00000003, 471edb9ca6SSiva Reddy }; 481edb9ca6SSiva Reddy 491edb9ca6SSiva Reddy enum flow_control_th { 501edb9ca6SSiva Reddy MTL_FC_FULL_1K = 0x00000000, 511edb9ca6SSiva Reddy MTL_FC_FULL_2K = 0x00000001, 521edb9ca6SSiva Reddy MTL_FC_FULL_4K = 0x00000002, 531edb9ca6SSiva Reddy MTL_FC_FULL_5K = 0x00000003, 541edb9ca6SSiva Reddy MTL_FC_FULL_6K = 0x00000004, 551edb9ca6SSiva Reddy MTL_FC_FULL_8K = 0x00000005, 561edb9ca6SSiva Reddy MTL_FC_FULL_16K = 0x00000006, 571edb9ca6SSiva Reddy MTL_FC_FULL_24K = 0x00000007, 581edb9ca6SSiva Reddy }; 591edb9ca6SSiva Reddy 601edb9ca6SSiva Reddy struct sxgbe_mtl_ops { 611edb9ca6SSiva Reddy void (*mtl_init)(void __iomem *ioaddr, unsigned int etsalg, 621edb9ca6SSiva Reddy unsigned int raa); 631edb9ca6SSiva Reddy 641edb9ca6SSiva Reddy void (*mtl_set_txfifosize)(void __iomem *ioaddr, int queue_num, 651edb9ca6SSiva Reddy int mtl_fifo); 661edb9ca6SSiva Reddy 671edb9ca6SSiva Reddy void (*mtl_set_rxfifosize)(void __iomem *ioaddr, int queue_num, 681edb9ca6SSiva Reddy int queue_fifo); 691edb9ca6SSiva Reddy 701edb9ca6SSiva Reddy void (*mtl_enable_txqueue)(void __iomem *ioaddr, int queue_num); 711edb9ca6SSiva Reddy 721edb9ca6SSiva Reddy void (*mtl_disable_txqueue)(void __iomem *ioaddr, int queue_num); 731edb9ca6SSiva Reddy 741edb9ca6SSiva Reddy void (*set_tx_mtl_mode)(void __iomem *ioaddr, int queue_num, 751edb9ca6SSiva Reddy int tx_mode); 761edb9ca6SSiva Reddy 771edb9ca6SSiva Reddy void (*set_rx_mtl_mode)(void __iomem *ioaddr, int queue_num, 781edb9ca6SSiva Reddy int rx_mode); 791edb9ca6SSiva Reddy 801edb9ca6SSiva Reddy void (*mtl_dynamic_dma_rxqueue)(void __iomem *ioaddr); 811edb9ca6SSiva Reddy 821edb9ca6SSiva Reddy void (*mtl_fc_active)(void __iomem *ioaddr, int queue_num, 831edb9ca6SSiva Reddy int threshold); 841edb9ca6SSiva Reddy 851edb9ca6SSiva Reddy void (*mtl_fc_deactive)(void __iomem *ioaddr, int queue_num, 861edb9ca6SSiva Reddy int threshold); 871edb9ca6SSiva Reddy 881edb9ca6SSiva Reddy void (*mtl_fc_enable)(void __iomem *ioaddr, int queue_num); 891edb9ca6SSiva Reddy 901edb9ca6SSiva Reddy void (*mtl_fep_enable)(void __iomem *ioaddr, int queue_num); 911edb9ca6SSiva Reddy 921edb9ca6SSiva Reddy void (*mtl_fep_disable)(void __iomem *ioaddr, int queue_num); 931edb9ca6SSiva Reddy 941edb9ca6SSiva Reddy void (*mtl_fup_enable)(void __iomem *ioaddr, int queue_num); 951edb9ca6SSiva Reddy 961edb9ca6SSiva Reddy void (*mtl_fup_disable)(void __iomem *ioaddr, int queue_num); 971edb9ca6SSiva Reddy }; 981edb9ca6SSiva Reddy 991edb9ca6SSiva Reddy const struct sxgbe_mtl_ops *sxgbe_get_mtl_ops(void); 1001edb9ca6SSiva Reddy 1011edb9ca6SSiva Reddy #endif /* __SXGBE_MTL_H__ */ 102