1 /* 10G controller driver for Samsung SoCs
2  *
3  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
4  *		http://www.samsung.com
5  *
6  * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 
15 #include <linux/clk.h>
16 #include <linux/crc32.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if.h>
21 #include <linux/if_ether.h>
22 #include <linux/if_vlan.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/ip.h>
26 #include <linux/kernel.h>
27 #include <linux/mii.h>
28 #include <linux/module.h>
29 #include <linux/net_tstamp.h>
30 #include <linux/netdevice.h>
31 #include <linux/phy.h>
32 #include <linux/platform_device.h>
33 #include <linux/prefetch.h>
34 #include <linux/skbuff.h>
35 #include <linux/slab.h>
36 #include <linux/tcp.h>
37 #include <linux/sxgbe_platform.h>
38 
39 #include "sxgbe_common.h"
40 #include "sxgbe_desc.h"
41 #include "sxgbe_dma.h"
42 #include "sxgbe_mtl.h"
43 #include "sxgbe_reg.h"
44 
45 #define SXGBE_ALIGN(x)	L1_CACHE_ALIGN(x)
46 #define JUMBO_LEN	9000
47 
48 /* Module parameters */
49 #define TX_TIMEO	5000
50 #define DMA_TX_SIZE	512
51 #define DMA_RX_SIZE	1024
52 #define TC_DEFAULT	64
53 #define DMA_BUFFER_SIZE	BUF_SIZE_2KiB
54 /* The default timer value as per the sxgbe specification 1 sec(1000 ms) */
55 #define SXGBE_DEFAULT_LPI_TIMER	1000
56 
57 static int debug = -1;
58 static int eee_timer = SXGBE_DEFAULT_LPI_TIMER;
59 
60 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
61 
62 module_param(debug, int, S_IRUGO | S_IWUSR);
63 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
64 				      NETIF_MSG_LINK | NETIF_MSG_IFUP |
65 				      NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
66 
67 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id);
68 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id);
69 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id);
70 
71 #define SXGBE_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
72 
73 #define SXGBE_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
74 
75 /**
76  * sxgbe_verify_args - verify the driver parameters.
77  * Description: it verifies if some wrong parameter is passed to the driver.
78  * Note that wrong parameters are replaced with the default values.
79  */
80 static void sxgbe_verify_args(void)
81 {
82 	if (unlikely(eee_timer < 0))
83 		eee_timer = SXGBE_DEFAULT_LPI_TIMER;
84 }
85 
86 static void sxgbe_enable_eee_mode(const struct sxgbe_priv_data *priv)
87 {
88 	/* Check and enter in LPI mode */
89 	if (!priv->tx_path_in_lpi_mode)
90 		priv->hw->mac->set_eee_mode(priv->ioaddr);
91 }
92 
93 void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv)
94 {
95 	/* Exit and disable EEE in case of we are are in LPI state. */
96 	priv->hw->mac->reset_eee_mode(priv->ioaddr);
97 	del_timer_sync(&priv->eee_ctrl_timer);
98 	priv->tx_path_in_lpi_mode = false;
99 }
100 
101 /**
102  * sxgbe_eee_ctrl_timer
103  * @arg : data hook
104  * Description:
105  *  If there is no data transfer and if we are not in LPI state,
106  *  then MAC Transmitter can be moved to LPI state.
107  */
108 static void sxgbe_eee_ctrl_timer(unsigned long arg)
109 {
110 	struct sxgbe_priv_data *priv = (struct sxgbe_priv_data *)arg;
111 
112 	sxgbe_enable_eee_mode(priv);
113 	mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
114 }
115 
116 /**
117  * sxgbe_eee_init
118  * @priv: private device pointer
119  * Description:
120  *  If the EEE support has been enabled while configuring the driver,
121  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
122  *  phy can also manage EEE, so enable the LPI state and start the timer
123  *  to verify if the tx path can enter in LPI state.
124  */
125 bool sxgbe_eee_init(struct sxgbe_priv_data * const priv)
126 {
127 	bool ret = false;
128 
129 	/* MAC core supports the EEE feature. */
130 	if (priv->hw_cap.eee) {
131 		/* Check if the PHY supports EEE */
132 		if (phy_init_eee(priv->phydev, 1))
133 			return false;
134 
135 		priv->eee_active = 1;
136 		init_timer(&priv->eee_ctrl_timer);
137 		priv->eee_ctrl_timer.function = sxgbe_eee_ctrl_timer;
138 		priv->eee_ctrl_timer.data = (unsigned long)priv;
139 		priv->eee_ctrl_timer.expires = SXGBE_LPI_TIMER(eee_timer);
140 		add_timer(&priv->eee_ctrl_timer);
141 
142 		priv->hw->mac->set_eee_timer(priv->ioaddr,
143 					     SXGBE_DEFAULT_LPI_TIMER,
144 					     priv->tx_lpi_timer);
145 
146 		pr_info("Energy-Efficient Ethernet initialized\n");
147 
148 		ret = true;
149 	}
150 
151 	return ret;
152 }
153 
154 static void sxgbe_eee_adjust(const struct sxgbe_priv_data *priv)
155 {
156 	/* When the EEE has been already initialised we have to
157 	 * modify the PLS bit in the LPI ctrl & status reg according
158 	 * to the PHY link status. For this reason.
159 	 */
160 	if (priv->eee_enabled)
161 		priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
162 }
163 
164 /**
165  * sxgbe_clk_csr_set - dynamically set the MDC clock
166  * @priv: driver private structure
167  * Description: this is to dynamically set the MDC clock according to the csr
168  * clock input.
169  */
170 static void sxgbe_clk_csr_set(struct sxgbe_priv_data *priv)
171 {
172 	u32 clk_rate = clk_get_rate(priv->sxgbe_clk);
173 
174 	/* assign the proper divider, this will be used during
175 	 * mdio communication
176 	 */
177 	if (clk_rate < SXGBE_CSR_F_150M)
178 		priv->clk_csr = SXGBE_CSR_100_150M;
179 	else if (clk_rate <= SXGBE_CSR_F_250M)
180 		priv->clk_csr = SXGBE_CSR_150_250M;
181 	else if (clk_rate <= SXGBE_CSR_F_300M)
182 		priv->clk_csr = SXGBE_CSR_250_300M;
183 	else if (clk_rate <= SXGBE_CSR_F_350M)
184 		priv->clk_csr = SXGBE_CSR_300_350M;
185 	else if (clk_rate <= SXGBE_CSR_F_400M)
186 		priv->clk_csr = SXGBE_CSR_350_400M;
187 	else if (clk_rate <= SXGBE_CSR_F_500M)
188 		priv->clk_csr = SXGBE_CSR_400_500M;
189 }
190 
191 /* minimum number of free TX descriptors required to wake up TX process */
192 #define SXGBE_TX_THRESH(x)	(x->dma_tx_size/4)
193 
194 static inline u32 sxgbe_tx_avail(struct sxgbe_tx_queue *queue, int tx_qsize)
195 {
196 	return queue->dirty_tx + tx_qsize - queue->cur_tx - 1;
197 }
198 
199 /**
200  * sxgbe_adjust_link
201  * @dev: net device structure
202  * Description: it adjusts the link parameters.
203  */
204 static void sxgbe_adjust_link(struct net_device *dev)
205 {
206 	struct sxgbe_priv_data *priv = netdev_priv(dev);
207 	struct phy_device *phydev = priv->phydev;
208 	u8 new_state = 0;
209 	u8 speed = 0xff;
210 
211 	if (!phydev)
212 		return;
213 
214 	/* SXGBE is not supporting auto-negotiation and
215 	 * half duplex mode. so, not handling duplex change
216 	 * in this function. only handling speed and link status
217 	 */
218 	if (phydev->link) {
219 		if (phydev->speed != priv->speed) {
220 			new_state = 1;
221 			switch (phydev->speed) {
222 			case SPEED_10000:
223 				speed = SXGBE_SPEED_10G;
224 				break;
225 			case SPEED_2500:
226 				speed = SXGBE_SPEED_2_5G;
227 				break;
228 			case SPEED_1000:
229 				speed = SXGBE_SPEED_1G;
230 				break;
231 			default:
232 				netif_err(priv, link, dev,
233 					  "Speed (%d) not supported\n",
234 					  phydev->speed);
235 			}
236 
237 			priv->speed = phydev->speed;
238 			priv->hw->mac->set_speed(priv->ioaddr, speed);
239 		}
240 
241 		if (!priv->oldlink) {
242 			new_state = 1;
243 			priv->oldlink = 1;
244 		}
245 	} else if (priv->oldlink) {
246 		new_state = 1;
247 		priv->oldlink = 0;
248 		priv->speed = SPEED_UNKNOWN;
249 	}
250 
251 	if (new_state & netif_msg_link(priv))
252 		phy_print_status(phydev);
253 
254 	/* Alter the MAC settings for EEE */
255 	sxgbe_eee_adjust(priv);
256 }
257 
258 /**
259  * sxgbe_init_phy - PHY initialization
260  * @dev: net device structure
261  * Description: it initializes the driver's PHY state, and attaches the PHY
262  * to the mac driver.
263  *  Return value:
264  *  0 on success
265  */
266 static int sxgbe_init_phy(struct net_device *ndev)
267 {
268 	char phy_id_fmt[MII_BUS_ID_SIZE + 3];
269 	char bus_id[MII_BUS_ID_SIZE];
270 	struct phy_device *phydev;
271 	struct sxgbe_priv_data *priv = netdev_priv(ndev);
272 	int phy_iface = priv->plat->interface;
273 
274 	/* assign default link status */
275 	priv->oldlink = 0;
276 	priv->speed = SPEED_UNKNOWN;
277 	priv->oldduplex = DUPLEX_UNKNOWN;
278 
279 	if (priv->plat->phy_bus_name)
280 		snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
281 			 priv->plat->phy_bus_name, priv->plat->bus_id);
282 	else
283 		snprintf(bus_id, MII_BUS_ID_SIZE, "sxgbe-%x",
284 			 priv->plat->bus_id);
285 
286 	snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
287 		 priv->plat->phy_addr);
288 	netdev_dbg(ndev, "%s: trying to attach to %s\n", __func__, phy_id_fmt);
289 
290 	phydev = phy_connect(ndev, phy_id_fmt, &sxgbe_adjust_link, phy_iface);
291 
292 	if (IS_ERR(phydev)) {
293 		netdev_err(ndev, "Could not attach to PHY\n");
294 		return PTR_ERR(phydev);
295 	}
296 
297 	/* Stop Advertising 1000BASE Capability if interface is not GMII */
298 	if ((phy_iface == PHY_INTERFACE_MODE_MII) ||
299 	    (phy_iface == PHY_INTERFACE_MODE_RMII))
300 		phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
301 					 SUPPORTED_1000baseT_Full);
302 	if (phydev->phy_id == 0) {
303 		phy_disconnect(phydev);
304 		return -ENODEV;
305 	}
306 
307 	netdev_dbg(ndev, "%s: attached to PHY (UID 0x%x) Link = %d\n",
308 		   __func__, phydev->phy_id, phydev->link);
309 
310 	/* save phy device in private structure */
311 	priv->phydev = phydev;
312 
313 	return 0;
314 }
315 
316 /**
317  * sxgbe_clear_descriptors: clear descriptors
318  * @priv: driver private structure
319  * Description: this function is called to clear the tx and rx descriptors
320  * in case of both basic and extended descriptors are used.
321  */
322 static void sxgbe_clear_descriptors(struct sxgbe_priv_data *priv)
323 {
324 	int i, j;
325 	unsigned int txsize = priv->dma_tx_size;
326 	unsigned int rxsize = priv->dma_rx_size;
327 
328 	/* Clear the Rx/Tx descriptors */
329 	for (j = 0; j < SXGBE_RX_QUEUES; j++) {
330 		for (i = 0; i < rxsize; i++)
331 			priv->hw->desc->init_rx_desc(&priv->rxq[j]->dma_rx[i],
332 						     priv->use_riwt, priv->mode,
333 						     (i == rxsize - 1));
334 	}
335 
336 	for (j = 0; j < SXGBE_TX_QUEUES; j++) {
337 		for (i = 0; i < txsize; i++)
338 			priv->hw->desc->init_tx_desc(&priv->txq[j]->dma_tx[i]);
339 	}
340 }
341 
342 static int sxgbe_init_rx_buffers(struct net_device *dev,
343 				 struct sxgbe_rx_norm_desc *p, int i,
344 				 unsigned int dma_buf_sz,
345 				 struct sxgbe_rx_queue *rx_ring)
346 {
347 	struct sxgbe_priv_data *priv = netdev_priv(dev);
348 	struct sk_buff *skb;
349 
350 	skb = __netdev_alloc_skb_ip_align(dev, dma_buf_sz, GFP_KERNEL);
351 	if (!skb)
352 		return -ENOMEM;
353 
354 	rx_ring->rx_skbuff[i] = skb;
355 	rx_ring->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
356 						   dma_buf_sz, DMA_FROM_DEVICE);
357 
358 	if (dma_mapping_error(priv->device, rx_ring->rx_skbuff_dma[i])) {
359 		netdev_err(dev, "%s: DMA mapping error\n", __func__);
360 		dev_kfree_skb_any(skb);
361 		return -EINVAL;
362 	}
363 
364 	p->rdes23.rx_rd_des23.buf2_addr = rx_ring->rx_skbuff_dma[i];
365 
366 	return 0;
367 }
368 /**
369  * init_tx_ring - init the TX descriptor ring
370  * @dev: net device structure
371  * @tx_ring: ring to be intialised
372  * @tx_rsize: ring size
373  * Description:  this function initializes the DMA TX descriptor
374  */
375 static int init_tx_ring(struct device *dev, u8 queue_no,
376 			struct sxgbe_tx_queue *tx_ring,	int tx_rsize)
377 {
378 	/* TX ring is not allcoated */
379 	if (!tx_ring) {
380 		dev_err(dev, "No memory for TX queue of SXGBE\n");
381 		return -ENOMEM;
382 	}
383 
384 	/* allocate memory for TX descriptors */
385 	tx_ring->dma_tx = dma_zalloc_coherent(dev,
386 					      tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
387 					      &tx_ring->dma_tx_phy, GFP_KERNEL);
388 	if (!tx_ring->dma_tx)
389 		return -ENOMEM;
390 
391 	/* allocate memory for TX skbuff array */
392 	tx_ring->tx_skbuff_dma = devm_kcalloc(dev, tx_rsize,
393 					      sizeof(dma_addr_t), GFP_KERNEL);
394 	if (!tx_ring->tx_skbuff_dma)
395 		goto dmamem_err;
396 
397 	tx_ring->tx_skbuff = devm_kcalloc(dev, tx_rsize,
398 					  sizeof(struct sk_buff *), GFP_KERNEL);
399 
400 	if (!tx_ring->tx_skbuff)
401 		goto dmamem_err;
402 
403 	/* assign queue number */
404 	tx_ring->queue_no = queue_no;
405 
406 	/* initalise counters */
407 	tx_ring->dirty_tx = 0;
408 	tx_ring->cur_tx = 0;
409 
410 	/* initalise TX queue lock */
411 	spin_lock_init(&tx_ring->tx_lock);
412 
413 	return 0;
414 
415 dmamem_err:
416 	dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
417 			  tx_ring->dma_tx, tx_ring->dma_tx_phy);
418 	return -ENOMEM;
419 }
420 
421 /**
422  * free_rx_ring - free the RX descriptor ring
423  * @dev: net device structure
424  * @rx_ring: ring to be intialised
425  * @rx_rsize: ring size
426  * Description:  this function initializes the DMA RX descriptor
427  */
428 static void free_rx_ring(struct device *dev, struct sxgbe_rx_queue *rx_ring,
429 			 int rx_rsize)
430 {
431 	dma_free_coherent(dev, rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
432 			  rx_ring->dma_rx, rx_ring->dma_rx_phy);
433 	kfree(rx_ring->rx_skbuff_dma);
434 	kfree(rx_ring->rx_skbuff);
435 }
436 
437 /**
438  * init_rx_ring - init the RX descriptor ring
439  * @dev: net device structure
440  * @rx_ring: ring to be intialised
441  * @rx_rsize: ring size
442  * Description:  this function initializes the DMA RX descriptor
443  */
444 static int init_rx_ring(struct net_device *dev, u8 queue_no,
445 			struct sxgbe_rx_queue *rx_ring,	int rx_rsize)
446 {
447 	struct sxgbe_priv_data *priv = netdev_priv(dev);
448 	int desc_index;
449 	unsigned int bfsize = 0;
450 	unsigned int ret = 0;
451 
452 	/* Set the max buffer size according to the MTU. */
453 	bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN, 8);
454 
455 	netif_dbg(priv, probe, dev, "%s: bfsize %d\n", __func__, bfsize);
456 
457 	/* RX ring is not allcoated */
458 	if (rx_ring == NULL) {
459 		netdev_err(dev, "No memory for RX queue\n");
460 		goto error;
461 	}
462 
463 	/* assign queue number */
464 	rx_ring->queue_no = queue_no;
465 
466 	/* allocate memory for RX descriptors */
467 	rx_ring->dma_rx = dma_zalloc_coherent(priv->device,
468 					      rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
469 					      &rx_ring->dma_rx_phy, GFP_KERNEL);
470 
471 	if (rx_ring->dma_rx == NULL)
472 		goto error;
473 
474 	/* allocate memory for RX skbuff array */
475 	rx_ring->rx_skbuff_dma = kmalloc_array(rx_rsize,
476 					       sizeof(dma_addr_t), GFP_KERNEL);
477 	if (!rx_ring->rx_skbuff_dma) {
478 		dma_free_coherent(priv->device,
479 				  rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
480 				  rx_ring->dma_rx, rx_ring->dma_rx_phy);
481 		goto error;
482 	}
483 
484 	rx_ring->rx_skbuff = kmalloc_array(rx_rsize,
485 					   sizeof(struct sk_buff *), GFP_KERNEL);
486 	if (!rx_ring->rx_skbuff) {
487 		kfree(rx_ring->rx_skbuff_dma);
488 		goto error;
489 	}
490 
491 	/* initialise the buffers */
492 	for (desc_index = 0; desc_index < rx_rsize; desc_index++) {
493 		struct sxgbe_rx_norm_desc *p;
494 		p = rx_ring->dma_rx + desc_index;
495 		ret = sxgbe_init_rx_buffers(dev, p, desc_index,
496 					    bfsize, rx_ring);
497 		if (ret)
498 			goto err_init_rx_buffers;
499 	}
500 
501 	/* initalise counters */
502 	rx_ring->cur_rx = 0;
503 	rx_ring->dirty_rx = (unsigned int)(desc_index - rx_rsize);
504 	priv->dma_buf_sz = bfsize;
505 
506 	return 0;
507 
508 err_init_rx_buffers:
509 	while (--desc_index >= 0)
510 		free_rx_ring(priv->device, rx_ring, desc_index);
511 error:
512 	return -ENOMEM;
513 }
514 /**
515  * free_tx_ring - free the TX descriptor ring
516  * @dev: net device structure
517  * @tx_ring: ring to be intialised
518  * @tx_rsize: ring size
519  * Description:  this function initializes the DMA TX descriptor
520  */
521 static void free_tx_ring(struct device *dev, struct sxgbe_tx_queue *tx_ring,
522 			 int tx_rsize)
523 {
524 	dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
525 			  tx_ring->dma_tx, tx_ring->dma_tx_phy);
526 }
527 
528 /**
529  * init_dma_desc_rings - init the RX/TX descriptor rings
530  * @dev: net device structure
531  * Description:  this function initializes the DMA RX/TX descriptors
532  * and allocates the socket buffers. It suppors the chained and ring
533  * modes.
534  */
535 static int init_dma_desc_rings(struct net_device *netd)
536 {
537 	int queue_num, ret;
538 	struct sxgbe_priv_data *priv = netdev_priv(netd);
539 	int tx_rsize = priv->dma_tx_size;
540 	int rx_rsize = priv->dma_rx_size;
541 
542 	/* Allocate memory for queue structures and TX descs */
543 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
544 		ret = init_tx_ring(priv->device, queue_num,
545 				   priv->txq[queue_num], tx_rsize);
546 		if (ret) {
547 			dev_err(&netd->dev, "TX DMA ring allocation failed!\n");
548 			goto txalloc_err;
549 		}
550 
551 		/* save private pointer in each ring this
552 		 * pointer is needed during cleaing TX queue
553 		 */
554 		priv->txq[queue_num]->priv_ptr = priv;
555 	}
556 
557 	/* Allocate memory for queue structures and RX descs */
558 	SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
559 		ret = init_rx_ring(netd, queue_num,
560 				   priv->rxq[queue_num], rx_rsize);
561 		if (ret) {
562 			netdev_err(netd, "RX DMA ring allocation failed!!\n");
563 			goto rxalloc_err;
564 		}
565 
566 		/* save private pointer in each ring this
567 		 * pointer is needed during cleaing TX queue
568 		 */
569 		priv->rxq[queue_num]->priv_ptr = priv;
570 	}
571 
572 	sxgbe_clear_descriptors(priv);
573 
574 	return 0;
575 
576 txalloc_err:
577 	while (queue_num--)
578 		free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
579 	return ret;
580 
581 rxalloc_err:
582 	while (queue_num--)
583 		free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
584 	return ret;
585 }
586 
587 static void tx_free_ring_skbufs(struct sxgbe_tx_queue *txqueue)
588 {
589 	int dma_desc;
590 	struct sxgbe_priv_data *priv = txqueue->priv_ptr;
591 	int tx_rsize = priv->dma_tx_size;
592 
593 	for (dma_desc = 0; dma_desc < tx_rsize; dma_desc++) {
594 		struct sxgbe_tx_norm_desc *tdesc = txqueue->dma_tx + dma_desc;
595 
596 		if (txqueue->tx_skbuff_dma[dma_desc])
597 			dma_unmap_single(priv->device,
598 					 txqueue->tx_skbuff_dma[dma_desc],
599 					 priv->hw->desc->get_tx_len(tdesc),
600 					 DMA_TO_DEVICE);
601 
602 		dev_kfree_skb_any(txqueue->tx_skbuff[dma_desc]);
603 		txqueue->tx_skbuff[dma_desc] = NULL;
604 		txqueue->tx_skbuff_dma[dma_desc] = 0;
605 	}
606 }
607 
608 
609 static void dma_free_tx_skbufs(struct sxgbe_priv_data *priv)
610 {
611 	int queue_num;
612 
613 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
614 		struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
615 		tx_free_ring_skbufs(tqueue);
616 	}
617 }
618 
619 static void free_dma_desc_resources(struct sxgbe_priv_data *priv)
620 {
621 	int queue_num;
622 	int tx_rsize = priv->dma_tx_size;
623 	int rx_rsize = priv->dma_rx_size;
624 
625 	/* Release the DMA TX buffers */
626 	dma_free_tx_skbufs(priv);
627 
628 	/* Release the TX ring memory also */
629 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
630 		free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
631 	}
632 
633 	/* Release the RX ring memory also */
634 	SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
635 		free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
636 	}
637 }
638 
639 static int txring_mem_alloc(struct sxgbe_priv_data *priv)
640 {
641 	int queue_num;
642 
643 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
644 		priv->txq[queue_num] = devm_kmalloc(priv->device,
645 						    sizeof(struct sxgbe_tx_queue), GFP_KERNEL);
646 		if (!priv->txq[queue_num])
647 			return -ENOMEM;
648 	}
649 
650 	return 0;
651 }
652 
653 static int rxring_mem_alloc(struct sxgbe_priv_data *priv)
654 {
655 	int queue_num;
656 
657 	SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
658 		priv->rxq[queue_num] = devm_kmalloc(priv->device,
659 						    sizeof(struct sxgbe_rx_queue), GFP_KERNEL);
660 		if (!priv->rxq[queue_num])
661 			return -ENOMEM;
662 	}
663 
664 	return 0;
665 }
666 
667 /**
668  *  sxgbe_mtl_operation_mode - HW MTL operation mode
669  *  @priv: driver private structure
670  *  Description: it sets the MTL operation mode: tx/rx MTL thresholds
671  *  or Store-And-Forward capability.
672  */
673 static void sxgbe_mtl_operation_mode(struct sxgbe_priv_data *priv)
674 {
675 	int queue_num;
676 
677 	/* TX/RX threshold control */
678 	if (likely(priv->plat->force_sf_dma_mode)) {
679 		/* set TC mode for TX QUEUES */
680 		SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
681 			priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
682 						       SXGBE_MTL_SFMODE);
683 		priv->tx_tc = SXGBE_MTL_SFMODE;
684 
685 		/* set TC mode for RX QUEUES */
686 		SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
687 			priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
688 						       SXGBE_MTL_SFMODE);
689 		priv->rx_tc = SXGBE_MTL_SFMODE;
690 	} else if (unlikely(priv->plat->force_thresh_dma_mode)) {
691 		/* set TC mode for TX QUEUES */
692 		SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
693 			priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
694 						       priv->tx_tc);
695 		/* set TC mode for RX QUEUES */
696 		SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
697 			priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
698 						       priv->rx_tc);
699 	} else {
700 		pr_err("ERROR: %s: Invalid TX threshold mode\n", __func__);
701 	}
702 }
703 
704 /**
705  * sxgbe_tx_queue_clean:
706  * @priv: driver private structure
707  * Description: it reclaims resources after transmission completes.
708  */
709 static void sxgbe_tx_queue_clean(struct sxgbe_tx_queue *tqueue)
710 {
711 	struct sxgbe_priv_data *priv = tqueue->priv_ptr;
712 	unsigned int tx_rsize = priv->dma_tx_size;
713 	struct netdev_queue *dev_txq;
714 	u8 queue_no = tqueue->queue_no;
715 
716 	dev_txq = netdev_get_tx_queue(priv->dev, queue_no);
717 
718 	spin_lock(&tqueue->tx_lock);
719 
720 	priv->xstats.tx_clean++;
721 	while (tqueue->dirty_tx != tqueue->cur_tx) {
722 		unsigned int entry = tqueue->dirty_tx % tx_rsize;
723 		struct sk_buff *skb = tqueue->tx_skbuff[entry];
724 		struct sxgbe_tx_norm_desc *p;
725 
726 		p = tqueue->dma_tx + entry;
727 
728 		/* Check if the descriptor is owned by the DMA. */
729 		if (priv->hw->desc->get_tx_owner(p))
730 			break;
731 
732 		if (netif_msg_tx_done(priv))
733 			pr_debug("%s: curr %d, dirty %d\n",
734 				 __func__, tqueue->cur_tx, tqueue->dirty_tx);
735 
736 		if (likely(tqueue->tx_skbuff_dma[entry])) {
737 			dma_unmap_single(priv->device,
738 					 tqueue->tx_skbuff_dma[entry],
739 					 priv->hw->desc->get_tx_len(p),
740 					 DMA_TO_DEVICE);
741 			tqueue->tx_skbuff_dma[entry] = 0;
742 		}
743 
744 		if (likely(skb)) {
745 			dev_kfree_skb(skb);
746 			tqueue->tx_skbuff[entry] = NULL;
747 		}
748 
749 		priv->hw->desc->release_tx_desc(p);
750 
751 		tqueue->dirty_tx++;
752 	}
753 
754 	/* wake up queue */
755 	if (unlikely(netif_tx_queue_stopped(dev_txq) &&
756 		     sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv))) {
757 		netif_tx_lock(priv->dev);
758 		if (netif_tx_queue_stopped(dev_txq) &&
759 		    sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv)) {
760 			if (netif_msg_tx_done(priv))
761 				pr_debug("%s: restart transmit\n", __func__);
762 			netif_tx_wake_queue(dev_txq);
763 		}
764 		netif_tx_unlock(priv->dev);
765 	}
766 
767 	spin_unlock(&tqueue->tx_lock);
768 }
769 
770 /**
771  * sxgbe_tx_clean:
772  * @priv: driver private structure
773  * Description: it reclaims resources after transmission completes.
774  */
775 static void sxgbe_tx_all_clean(struct sxgbe_priv_data * const priv)
776 {
777 	u8 queue_num;
778 
779 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
780 		struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
781 
782 		sxgbe_tx_queue_clean(tqueue);
783 	}
784 
785 	if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
786 		sxgbe_enable_eee_mode(priv);
787 		mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
788 	}
789 }
790 
791 /**
792  * sxgbe_restart_tx_queue: irq tx error mng function
793  * @priv: driver private structure
794  * Description: it cleans the descriptors and restarts the transmission
795  * in case of errors.
796  */
797 static void sxgbe_restart_tx_queue(struct sxgbe_priv_data *priv, int queue_num)
798 {
799 	struct sxgbe_tx_queue *tx_ring = priv->txq[queue_num];
800 	struct netdev_queue *dev_txq = netdev_get_tx_queue(priv->dev,
801 							   queue_num);
802 
803 	/* stop the queue */
804 	netif_tx_stop_queue(dev_txq);
805 
806 	/* stop the tx dma */
807 	priv->hw->dma->stop_tx_queue(priv->ioaddr, queue_num);
808 
809 	/* free the skbuffs of the ring */
810 	tx_free_ring_skbufs(tx_ring);
811 
812 	/* initalise counters */
813 	tx_ring->cur_tx = 0;
814 	tx_ring->dirty_tx = 0;
815 
816 	/* start the tx dma */
817 	priv->hw->dma->start_tx_queue(priv->ioaddr, queue_num);
818 
819 	priv->dev->stats.tx_errors++;
820 
821 	/* wakeup the queue */
822 	netif_tx_wake_queue(dev_txq);
823 }
824 
825 /**
826  * sxgbe_reset_all_tx_queues: irq tx error mng function
827  * @priv: driver private structure
828  * Description: it cleans all the descriptors and
829  * restarts the transmission on all queues in case of errors.
830  */
831 static void sxgbe_reset_all_tx_queues(struct sxgbe_priv_data *priv)
832 {
833 	int queue_num;
834 
835 	/* On TX timeout of net device, resetting of all queues
836 	 * may not be proper way, revisit this later if needed
837 	 */
838 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
839 		sxgbe_restart_tx_queue(priv, queue_num);
840 }
841 
842 /**
843  * sxgbe_get_hw_features: get XMAC capabilities from the HW cap. register.
844  * @priv: driver private structure
845  * Description:
846  *  new GMAC chip generations have a new register to indicate the
847  *  presence of the optional feature/functions.
848  *  This can be also used to override the value passed through the
849  *  platform and necessary for old MAC10/100 and GMAC chips.
850  */
851 static int sxgbe_get_hw_features(struct sxgbe_priv_data * const priv)
852 {
853 	int rval = 0;
854 	struct sxgbe_hw_features *features = &priv->hw_cap;
855 
856 	/* Read First Capability Register CAP[0] */
857 	rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 0);
858 	if (rval) {
859 		features->pmt_remote_wake_up =
860 			SXGBE_HW_FEAT_PMT_TEMOTE_WOP(rval);
861 		features->pmt_magic_frame = SXGBE_HW_FEAT_PMT_MAGIC_PKT(rval);
862 		features->atime_stamp = SXGBE_HW_FEAT_IEEE1500_2008(rval);
863 		features->tx_csum_offload =
864 			SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(rval);
865 		features->rx_csum_offload =
866 			SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(rval);
867 		features->multi_macaddr = SXGBE_HW_FEAT_MACADDR_COUNT(rval);
868 		features->tstamp_srcselect = SXGBE_HW_FEAT_TSTMAP_SRC(rval);
869 		features->sa_vlan_insert = SXGBE_HW_FEAT_SRCADDR_VLAN(rval);
870 		features->eee = SXGBE_HW_FEAT_EEE(rval);
871 	}
872 
873 	/* Read First Capability Register CAP[1] */
874 	rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 1);
875 	if (rval) {
876 		features->rxfifo_size = SXGBE_HW_FEAT_RX_FIFO_SIZE(rval);
877 		features->txfifo_size = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
878 		features->atstmap_hword = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
879 		features->dcb_enable = SXGBE_HW_FEAT_DCB(rval);
880 		features->splithead_enable = SXGBE_HW_FEAT_SPLIT_HDR(rval);
881 		features->tcpseg_offload = SXGBE_HW_FEAT_TSO(rval);
882 		features->debug_mem = SXGBE_HW_FEAT_DEBUG_MEM_IFACE(rval);
883 		features->rss_enable = SXGBE_HW_FEAT_RSS(rval);
884 		features->hash_tsize = SXGBE_HW_FEAT_HASH_TABLE_SIZE(rval);
885 		features->l3l4_filer_size = SXGBE_HW_FEAT_L3L4_FILTER_NUM(rval);
886 	}
887 
888 	/* Read First Capability Register CAP[2] */
889 	rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 2);
890 	if (rval) {
891 		features->rx_mtl_queues = SXGBE_HW_FEAT_RX_MTL_QUEUES(rval);
892 		features->tx_mtl_queues = SXGBE_HW_FEAT_TX_MTL_QUEUES(rval);
893 		features->rx_dma_channels = SXGBE_HW_FEAT_RX_DMA_CHANNELS(rval);
894 		features->tx_dma_channels = SXGBE_HW_FEAT_TX_DMA_CHANNELS(rval);
895 		features->pps_output_count = SXGBE_HW_FEAT_PPS_OUTPUTS(rval);
896 		features->aux_input_count = SXGBE_HW_FEAT_AUX_SNAPSHOTS(rval);
897 	}
898 
899 	return rval;
900 }
901 
902 /**
903  * sxgbe_check_ether_addr: check if the MAC addr is valid
904  * @priv: driver private structure
905  * Description:
906  * it is to verify if the MAC address is valid, in case of failures it
907  * generates a random MAC address
908  */
909 static void sxgbe_check_ether_addr(struct sxgbe_priv_data *priv)
910 {
911 	if (!is_valid_ether_addr(priv->dev->dev_addr)) {
912 		priv->hw->mac->get_umac_addr((void __iomem *)
913 					     priv->ioaddr,
914 					     priv->dev->dev_addr, 0);
915 		if (!is_valid_ether_addr(priv->dev->dev_addr))
916 			eth_hw_addr_random(priv->dev);
917 	}
918 	dev_info(priv->device, "device MAC address %pM\n",
919 		 priv->dev->dev_addr);
920 }
921 
922 /**
923  * sxgbe_init_dma_engine: DMA init.
924  * @priv: driver private structure
925  * Description:
926  * It inits the DMA invoking the specific SXGBE callback.
927  * Some DMA parameters can be passed from the platform;
928  * in case of these are not passed a default is kept for the MAC or GMAC.
929  */
930 static int sxgbe_init_dma_engine(struct sxgbe_priv_data *priv)
931 {
932 	int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_map = 0;
933 	int queue_num;
934 
935 	if (priv->plat->dma_cfg) {
936 		pbl = priv->plat->dma_cfg->pbl;
937 		fixed_burst = priv->plat->dma_cfg->fixed_burst;
938 		burst_map = priv->plat->dma_cfg->burst_map;
939 	}
940 
941 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
942 		priv->hw->dma->cha_init(priv->ioaddr, queue_num,
943 					fixed_burst, pbl,
944 					(priv->txq[queue_num])->dma_tx_phy,
945 					(priv->rxq[queue_num])->dma_rx_phy,
946 					priv->dma_tx_size, priv->dma_rx_size);
947 
948 	return priv->hw->dma->init(priv->ioaddr, fixed_burst, burst_map);
949 }
950 
951 /**
952  * sxgbe_init_mtl_engine: MTL init.
953  * @priv: driver private structure
954  * Description:
955  * It inits the MTL invoking the specific SXGBE callback.
956  */
957 static void sxgbe_init_mtl_engine(struct sxgbe_priv_data *priv)
958 {
959 	int queue_num;
960 
961 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
962 		priv->hw->mtl->mtl_set_txfifosize(priv->ioaddr, queue_num,
963 						  priv->hw_cap.tx_mtl_qsize);
964 		priv->hw->mtl->mtl_enable_txqueue(priv->ioaddr, queue_num);
965 	}
966 }
967 
968 /**
969  * sxgbe_disable_mtl_engine: MTL disable.
970  * @priv: driver private structure
971  * Description:
972  * It disables the MTL queues by invoking the specific SXGBE callback.
973  */
974 static void sxgbe_disable_mtl_engine(struct sxgbe_priv_data *priv)
975 {
976 	int queue_num;
977 
978 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
979 		priv->hw->mtl->mtl_disable_txqueue(priv->ioaddr, queue_num);
980 }
981 
982 
983 /**
984  * sxgbe_tx_timer: mitigation sw timer for tx.
985  * @data: data pointer
986  * Description:
987  * This is the timer handler to directly invoke the sxgbe_tx_clean.
988  */
989 static void sxgbe_tx_timer(unsigned long data)
990 {
991 	struct sxgbe_tx_queue *p = (struct sxgbe_tx_queue *)data;
992 	sxgbe_tx_queue_clean(p);
993 }
994 
995 /**
996  * sxgbe_init_tx_coalesce: init tx mitigation options.
997  * @priv: driver private structure
998  * Description:
999  * This inits the transmit coalesce parameters: i.e. timer rate,
1000  * timer handler and default threshold used for enabling the
1001  * interrupt on completion bit.
1002  */
1003 static void sxgbe_tx_init_coalesce(struct sxgbe_priv_data *priv)
1004 {
1005 	u8 queue_num;
1006 
1007 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1008 		struct sxgbe_tx_queue *p = priv->txq[queue_num];
1009 		p->tx_coal_frames =  SXGBE_TX_FRAMES;
1010 		p->tx_coal_timer = SXGBE_COAL_TX_TIMER;
1011 		init_timer(&p->txtimer);
1012 		p->txtimer.expires = SXGBE_COAL_TIMER(p->tx_coal_timer);
1013 		p->txtimer.data = (unsigned long)&priv->txq[queue_num];
1014 		p->txtimer.function = sxgbe_tx_timer;
1015 		add_timer(&p->txtimer);
1016 	}
1017 }
1018 
1019 static void sxgbe_tx_del_timer(struct sxgbe_priv_data *priv)
1020 {
1021 	u8 queue_num;
1022 
1023 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1024 		struct sxgbe_tx_queue *p = priv->txq[queue_num];
1025 		del_timer_sync(&p->txtimer);
1026 	}
1027 }
1028 
1029 /**
1030  *  sxgbe_open - open entry point of the driver
1031  *  @dev : pointer to the device structure.
1032  *  Description:
1033  *  This function is the open entry point of the driver.
1034  *  Return value:
1035  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1036  *  file on failure.
1037  */
1038 static int sxgbe_open(struct net_device *dev)
1039 {
1040 	struct sxgbe_priv_data *priv = netdev_priv(dev);
1041 	int ret, queue_num;
1042 
1043 	clk_prepare_enable(priv->sxgbe_clk);
1044 
1045 	sxgbe_check_ether_addr(priv);
1046 
1047 	/* Init the phy */
1048 	ret = sxgbe_init_phy(dev);
1049 	if (ret) {
1050 		netdev_err(dev, "%s: Cannot attach to PHY (error: %d)\n",
1051 			   __func__, ret);
1052 		goto phy_error;
1053 	}
1054 
1055 	/* Create and initialize the TX/RX descriptors chains. */
1056 	priv->dma_tx_size = SXGBE_ALIGN(DMA_TX_SIZE);
1057 	priv->dma_rx_size = SXGBE_ALIGN(DMA_RX_SIZE);
1058 	priv->dma_buf_sz = SXGBE_ALIGN(DMA_BUFFER_SIZE);
1059 	priv->tx_tc = TC_DEFAULT;
1060 	priv->rx_tc = TC_DEFAULT;
1061 	init_dma_desc_rings(dev);
1062 
1063 	/* DMA initialization and SW reset */
1064 	ret = sxgbe_init_dma_engine(priv);
1065 	if (ret < 0) {
1066 		netdev_err(dev, "%s: DMA initialization failed\n", __func__);
1067 		goto init_error;
1068 	}
1069 
1070 	/*  MTL initialization */
1071 	sxgbe_init_mtl_engine(priv);
1072 
1073 	/* Copy the MAC addr into the HW  */
1074 	priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1075 
1076 	/* Initialize the MAC Core */
1077 	priv->hw->mac->core_init(priv->ioaddr);
1078 	SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1079 		priv->hw->mac->enable_rxqueue(priv->ioaddr, queue_num);
1080 	}
1081 
1082 	/* Request the IRQ lines */
1083 	ret = devm_request_irq(priv->device, priv->irq, sxgbe_common_interrupt,
1084 			       IRQF_SHARED, dev->name, dev);
1085 	if (unlikely(ret < 0)) {
1086 		netdev_err(dev, "%s: ERROR: allocating the IRQ %d (error: %d)\n",
1087 			   __func__, priv->irq, ret);
1088 		goto init_error;
1089 	}
1090 
1091 	/* If the LPI irq is different from the mac irq
1092 	 * register a dedicated handler
1093 	 */
1094 	if (priv->lpi_irq != dev->irq) {
1095 		ret = devm_request_irq(priv->device, priv->lpi_irq,
1096 				       sxgbe_common_interrupt,
1097 				       IRQF_SHARED, dev->name, dev);
1098 		if (unlikely(ret < 0)) {
1099 			netdev_err(dev, "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1100 				   __func__, priv->lpi_irq, ret);
1101 			goto init_error;
1102 		}
1103 	}
1104 
1105 	/* Request TX DMA irq lines */
1106 	SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1107 		ret = devm_request_irq(priv->device,
1108 				       (priv->txq[queue_num])->irq_no,
1109 				       sxgbe_tx_interrupt, 0,
1110 				       dev->name, priv->txq[queue_num]);
1111 		if (unlikely(ret < 0)) {
1112 			netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1113 				   __func__, priv->irq, ret);
1114 			goto init_error;
1115 		}
1116 	}
1117 
1118 	/* Request RX DMA irq lines */
1119 	SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1120 		ret = devm_request_irq(priv->device,
1121 				       (priv->rxq[queue_num])->irq_no,
1122 				       sxgbe_rx_interrupt, 0,
1123 				       dev->name, priv->rxq[queue_num]);
1124 		if (unlikely(ret < 0)) {
1125 			netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1126 				   __func__, priv->irq, ret);
1127 			goto init_error;
1128 		}
1129 	}
1130 
1131 	/* Enable the MAC Rx/Tx */
1132 	priv->hw->mac->enable_tx(priv->ioaddr, true);
1133 	priv->hw->mac->enable_rx(priv->ioaddr, true);
1134 
1135 	/* Set the HW DMA mode and the COE */
1136 	sxgbe_mtl_operation_mode(priv);
1137 
1138 	/* Extra statistics */
1139 	memset(&priv->xstats, 0, sizeof(struct sxgbe_extra_stats));
1140 
1141 	priv->xstats.tx_threshold = priv->tx_tc;
1142 	priv->xstats.rx_threshold = priv->rx_tc;
1143 
1144 	/* Start the ball rolling... */
1145 	netdev_dbg(dev, "DMA RX/TX processes started...\n");
1146 	priv->hw->dma->start_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1147 	priv->hw->dma->start_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1148 
1149 	if (priv->phydev)
1150 		phy_start(priv->phydev);
1151 
1152 	/* initalise TX coalesce parameters */
1153 	sxgbe_tx_init_coalesce(priv);
1154 
1155 	if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1156 		priv->rx_riwt = SXGBE_MAX_DMA_RIWT;
1157 		priv->hw->dma->rx_watchdog(priv->ioaddr, SXGBE_MAX_DMA_RIWT);
1158 	}
1159 
1160 	priv->tx_lpi_timer = SXGBE_DEFAULT_LPI_TIMER;
1161 	priv->eee_enabled = sxgbe_eee_init(priv);
1162 
1163 	napi_enable(&priv->napi);
1164 	netif_start_queue(dev);
1165 
1166 	return 0;
1167 
1168 init_error:
1169 	free_dma_desc_resources(priv);
1170 	if (priv->phydev)
1171 		phy_disconnect(priv->phydev);
1172 phy_error:
1173 	clk_disable_unprepare(priv->sxgbe_clk);
1174 
1175 	return ret;
1176 }
1177 
1178 /**
1179  *  sxgbe_release - close entry point of the driver
1180  *  @dev : device pointer.
1181  *  Description:
1182  *  This is the stop entry point of the driver.
1183  */
1184 static int sxgbe_release(struct net_device *dev)
1185 {
1186 	struct sxgbe_priv_data *priv = netdev_priv(dev);
1187 
1188 	if (priv->eee_enabled)
1189 		del_timer_sync(&priv->eee_ctrl_timer);
1190 
1191 	/* Stop and disconnect the PHY */
1192 	if (priv->phydev) {
1193 		phy_stop(priv->phydev);
1194 		phy_disconnect(priv->phydev);
1195 		priv->phydev = NULL;
1196 	}
1197 
1198 	netif_tx_stop_all_queues(dev);
1199 
1200 	napi_disable(&priv->napi);
1201 
1202 	/* delete TX timers */
1203 	sxgbe_tx_del_timer(priv);
1204 
1205 	/* Stop TX/RX DMA and clear the descriptors */
1206 	priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1207 	priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1208 
1209 	/* disable MTL queue */
1210 	sxgbe_disable_mtl_engine(priv);
1211 
1212 	/* Release and free the Rx/Tx resources */
1213 	free_dma_desc_resources(priv);
1214 
1215 	/* Disable the MAC Rx/Tx */
1216 	priv->hw->mac->enable_tx(priv->ioaddr, false);
1217 	priv->hw->mac->enable_rx(priv->ioaddr, false);
1218 
1219 	clk_disable_unprepare(priv->sxgbe_clk);
1220 
1221 	return 0;
1222 }
1223 /* Prepare first Tx descriptor for doing TSO operation */
1224 static void sxgbe_tso_prepare(struct sxgbe_priv_data *priv,
1225 			      struct sxgbe_tx_norm_desc *first_desc,
1226 			      struct sk_buff *skb)
1227 {
1228 	unsigned int total_hdr_len, tcp_hdr_len;
1229 
1230 	/* Write first Tx descriptor with appropriate value */
1231 	tcp_hdr_len = tcp_hdrlen(skb);
1232 	total_hdr_len = skb_transport_offset(skb) + tcp_hdr_len;
1233 
1234 	first_desc->tdes01 = dma_map_single(priv->device, skb->data,
1235 					    total_hdr_len, DMA_TO_DEVICE);
1236 	if (dma_mapping_error(priv->device, first_desc->tdes01))
1237 		pr_err("%s: TX dma mapping failed!!\n", __func__);
1238 
1239 	first_desc->tdes23.tx_rd_des23.first_desc = 1;
1240 	priv->hw->desc->tx_desc_enable_tse(first_desc, 1, total_hdr_len,
1241 					   tcp_hdr_len,
1242 					   skb->len - total_hdr_len);
1243 }
1244 
1245 /**
1246  *  sxgbe_xmit: Tx entry point of the driver
1247  *  @skb : the socket buffer
1248  *  @dev : device pointer
1249  *  Description : this is the tx entry point of the driver.
1250  *  It programs the chain or the ring and supports oversized frames
1251  *  and SG feature.
1252  */
1253 static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev)
1254 {
1255 	unsigned int entry, frag_num;
1256 	int cksum_flag = 0;
1257 	struct netdev_queue *dev_txq;
1258 	unsigned txq_index = skb_get_queue_mapping(skb);
1259 	struct sxgbe_priv_data *priv = netdev_priv(dev);
1260 	unsigned int tx_rsize = priv->dma_tx_size;
1261 	struct sxgbe_tx_queue *tqueue = priv->txq[txq_index];
1262 	struct sxgbe_tx_norm_desc *tx_desc, *first_desc;
1263 	struct sxgbe_tx_ctxt_desc *ctxt_desc = NULL;
1264 	int nr_frags = skb_shinfo(skb)->nr_frags;
1265 	int no_pagedlen = skb_headlen(skb);
1266 	int is_jumbo = 0;
1267 	u16 cur_mss = skb_shinfo(skb)->gso_size;
1268 	u32 ctxt_desc_req = 0;
1269 
1270 	/* get the TX queue handle */
1271 	dev_txq = netdev_get_tx_queue(dev, txq_index);
1272 
1273 	if (unlikely(skb_is_gso(skb) && tqueue->prev_mss != cur_mss))
1274 		ctxt_desc_req = 1;
1275 
1276 	if (unlikely(vlan_tx_tag_present(skb) ||
1277 		     ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1278 		      tqueue->hwts_tx_en)))
1279 		ctxt_desc_req = 1;
1280 
1281 	/* get the spinlock */
1282 	spin_lock(&tqueue->tx_lock);
1283 
1284 	if (priv->tx_path_in_lpi_mode)
1285 		sxgbe_disable_eee_mode(priv);
1286 
1287 	if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) < nr_frags + 1)) {
1288 		if (!netif_tx_queue_stopped(dev_txq)) {
1289 			netif_tx_stop_queue(dev_txq);
1290 			netdev_err(dev, "%s: Tx Ring is full when %d queue is awake\n",
1291 				   __func__, txq_index);
1292 		}
1293 		/* release the spin lock in case of BUSY */
1294 		spin_unlock(&tqueue->tx_lock);
1295 		return NETDEV_TX_BUSY;
1296 	}
1297 
1298 	entry = tqueue->cur_tx % tx_rsize;
1299 	tx_desc = tqueue->dma_tx + entry;
1300 
1301 	first_desc = tx_desc;
1302 	if (ctxt_desc_req)
1303 		ctxt_desc = (struct sxgbe_tx_ctxt_desc *)first_desc;
1304 
1305 	/* save the skb address */
1306 	tqueue->tx_skbuff[entry] = skb;
1307 
1308 	if (!is_jumbo) {
1309 		if (likely(skb_is_gso(skb))) {
1310 			/* TSO support */
1311 			if (unlikely(tqueue->prev_mss != cur_mss)) {
1312 				priv->hw->desc->tx_ctxt_desc_set_mss(
1313 						ctxt_desc, cur_mss);
1314 				priv->hw->desc->tx_ctxt_desc_set_tcmssv(
1315 						ctxt_desc);
1316 				priv->hw->desc->tx_ctxt_desc_reset_ostc(
1317 						ctxt_desc);
1318 				priv->hw->desc->tx_ctxt_desc_set_ctxt(
1319 						ctxt_desc);
1320 				priv->hw->desc->tx_ctxt_desc_set_owner(
1321 						ctxt_desc);
1322 
1323 				entry = (++tqueue->cur_tx) % tx_rsize;
1324 				first_desc = tqueue->dma_tx + entry;
1325 
1326 				tqueue->prev_mss = cur_mss;
1327 			}
1328 			sxgbe_tso_prepare(priv, first_desc, skb);
1329 		} else {
1330 			tx_desc->tdes01 = dma_map_single(priv->device,
1331 							 skb->data, no_pagedlen, DMA_TO_DEVICE);
1332 			if (dma_mapping_error(priv->device, tx_desc->tdes01))
1333 				netdev_err(dev, "%s: TX dma mapping failed!!\n",
1334 					   __func__);
1335 
1336 			priv->hw->desc->prepare_tx_desc(tx_desc, 1, no_pagedlen,
1337 							no_pagedlen, cksum_flag);
1338 		}
1339 	}
1340 
1341 	for (frag_num = 0; frag_num < nr_frags; frag_num++) {
1342 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_num];
1343 		int len = skb_frag_size(frag);
1344 
1345 		entry = (++tqueue->cur_tx) % tx_rsize;
1346 		tx_desc = tqueue->dma_tx + entry;
1347 		tx_desc->tdes01 = skb_frag_dma_map(priv->device, frag, 0, len,
1348 						   DMA_TO_DEVICE);
1349 
1350 		tqueue->tx_skbuff_dma[entry] = tx_desc->tdes01;
1351 		tqueue->tx_skbuff[entry] = NULL;
1352 
1353 		/* prepare the descriptor */
1354 		priv->hw->desc->prepare_tx_desc(tx_desc, 0, len,
1355 						len, cksum_flag);
1356 		/* memory barrier to flush descriptor */
1357 		wmb();
1358 
1359 		/* set the owner */
1360 		priv->hw->desc->set_tx_owner(tx_desc);
1361 	}
1362 
1363 	/* close the descriptors */
1364 	priv->hw->desc->close_tx_desc(tx_desc);
1365 
1366 	/* memory barrier to flush descriptor */
1367 	wmb();
1368 
1369 	tqueue->tx_count_frames += nr_frags + 1;
1370 	if (tqueue->tx_count_frames > tqueue->tx_coal_frames) {
1371 		priv->hw->desc->clear_tx_ic(tx_desc);
1372 		priv->xstats.tx_reset_ic_bit++;
1373 		mod_timer(&tqueue->txtimer,
1374 			  SXGBE_COAL_TIMER(tqueue->tx_coal_timer));
1375 	} else {
1376 		tqueue->tx_count_frames = 0;
1377 	}
1378 
1379 	/* set owner for first desc */
1380 	priv->hw->desc->set_tx_owner(first_desc);
1381 
1382 	/* memory barrier to flush descriptor */
1383 	wmb();
1384 
1385 	tqueue->cur_tx++;
1386 
1387 	/* display current ring */
1388 	netif_dbg(priv, pktdata, dev, "%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d\n",
1389 		  __func__, tqueue->cur_tx % tx_rsize,
1390 		  tqueue->dirty_tx % tx_rsize, entry,
1391 		  first_desc, nr_frags);
1392 
1393 	if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) <= (MAX_SKB_FRAGS + 1))) {
1394 		netif_dbg(priv, hw, dev, "%s: stop transmitted packets\n",
1395 			  __func__);
1396 		netif_tx_stop_queue(dev_txq);
1397 	}
1398 
1399 	dev->stats.tx_bytes += skb->len;
1400 
1401 	if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1402 		     tqueue->hwts_tx_en)) {
1403 		/* declare that device is doing timestamping */
1404 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1405 		priv->hw->desc->tx_enable_tstamp(first_desc);
1406 	}
1407 
1408 	if (!tqueue->hwts_tx_en)
1409 		skb_tx_timestamp(skb);
1410 
1411 	priv->hw->dma->enable_dma_transmission(priv->ioaddr, txq_index);
1412 
1413 	spin_unlock(&tqueue->tx_lock);
1414 
1415 	return NETDEV_TX_OK;
1416 }
1417 
1418 /**
1419  * sxgbe_rx_refill: refill used skb preallocated buffers
1420  * @priv: driver private structure
1421  * Description : this is to reallocate the skb for the reception process
1422  * that is based on zero-copy.
1423  */
1424 static void sxgbe_rx_refill(struct sxgbe_priv_data *priv)
1425 {
1426 	unsigned int rxsize = priv->dma_rx_size;
1427 	int bfsize = priv->dma_buf_sz;
1428 	u8 qnum = priv->cur_rx_qnum;
1429 
1430 	for (; priv->rxq[qnum]->cur_rx - priv->rxq[qnum]->dirty_rx > 0;
1431 	     priv->rxq[qnum]->dirty_rx++) {
1432 		unsigned int entry = priv->rxq[qnum]->dirty_rx % rxsize;
1433 		struct sxgbe_rx_norm_desc *p;
1434 
1435 		p = priv->rxq[qnum]->dma_rx + entry;
1436 
1437 		if (likely(priv->rxq[qnum]->rx_skbuff[entry] == NULL)) {
1438 			struct sk_buff *skb;
1439 
1440 			skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1441 
1442 			if (unlikely(skb == NULL))
1443 				break;
1444 
1445 			priv->rxq[qnum]->rx_skbuff[entry] = skb;
1446 			priv->rxq[qnum]->rx_skbuff_dma[entry] =
1447 				dma_map_single(priv->device, skb->data, bfsize,
1448 					       DMA_FROM_DEVICE);
1449 
1450 			p->rdes23.rx_rd_des23.buf2_addr =
1451 				priv->rxq[qnum]->rx_skbuff_dma[entry];
1452 		}
1453 
1454 		/* Added memory barrier for RX descriptor modification */
1455 		wmb();
1456 		priv->hw->desc->set_rx_owner(p);
1457 		priv->hw->desc->set_rx_int_on_com(p);
1458 		/* Added memory barrier for RX descriptor modification */
1459 		wmb();
1460 	}
1461 }
1462 
1463 /**
1464  * sxgbe_rx: receive the frames from the remote host
1465  * @priv: driver private structure
1466  * @limit: napi bugget.
1467  * Description :  this the function called by the napi poll method.
1468  * It gets all the frames inside the ring.
1469  */
1470 static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit)
1471 {
1472 	u8 qnum = priv->cur_rx_qnum;
1473 	unsigned int rxsize = priv->dma_rx_size;
1474 	unsigned int entry = priv->rxq[qnum]->cur_rx;
1475 	unsigned int next_entry = 0;
1476 	unsigned int count = 0;
1477 	int checksum;
1478 	int status;
1479 
1480 	while (count < limit) {
1481 		struct sxgbe_rx_norm_desc *p;
1482 		struct sk_buff *skb;
1483 		int frame_len;
1484 
1485 		p = priv->rxq[qnum]->dma_rx + entry;
1486 
1487 		if (priv->hw->desc->get_rx_owner(p))
1488 			break;
1489 
1490 		count++;
1491 
1492 		next_entry = (++priv->rxq[qnum]->cur_rx) % rxsize;
1493 		prefetch(priv->rxq[qnum]->dma_rx + next_entry);
1494 
1495 		/* Read the status of the incoming frame and also get checksum
1496 		 * value based on whether it is enabled in SXGBE hardware or
1497 		 * not.
1498 		 */
1499 		status = priv->hw->desc->rx_wbstatus(p, &priv->xstats,
1500 						     &checksum);
1501 		if (unlikely(status < 0)) {
1502 			entry = next_entry;
1503 			continue;
1504 		}
1505 		if (unlikely(!priv->rxcsum_insertion))
1506 			checksum = CHECKSUM_NONE;
1507 
1508 		skb = priv->rxq[qnum]->rx_skbuff[entry];
1509 
1510 		if (unlikely(!skb))
1511 			netdev_err(priv->dev, "rx descriptor is not consistent\n");
1512 
1513 		prefetch(skb->data - NET_IP_ALIGN);
1514 		priv->rxq[qnum]->rx_skbuff[entry] = NULL;
1515 
1516 		frame_len = priv->hw->desc->get_rx_frame_len(p);
1517 
1518 		skb_put(skb, frame_len);
1519 
1520 		skb->ip_summed = checksum;
1521 		if (checksum == CHECKSUM_NONE)
1522 			netif_receive_skb(skb);
1523 		else
1524 			napi_gro_receive(&priv->napi, skb);
1525 
1526 		entry = next_entry;
1527 	}
1528 
1529 	sxgbe_rx_refill(priv);
1530 
1531 	return count;
1532 }
1533 
1534 /**
1535  *  sxgbe_poll - sxgbe poll method (NAPI)
1536  *  @napi : pointer to the napi structure.
1537  *  @budget : maximum number of packets that the current CPU can receive from
1538  *	      all interfaces.
1539  *  Description :
1540  *  To look at the incoming frames and clear the tx resources.
1541  */
1542 static int sxgbe_poll(struct napi_struct *napi, int budget)
1543 {
1544 	struct sxgbe_priv_data *priv = container_of(napi,
1545 						    struct sxgbe_priv_data, napi);
1546 	int work_done = 0;
1547 	u8 qnum = priv->cur_rx_qnum;
1548 
1549 	priv->xstats.napi_poll++;
1550 	/* first, clean the tx queues */
1551 	sxgbe_tx_all_clean(priv);
1552 
1553 	work_done = sxgbe_rx(priv, budget);
1554 	if (work_done < budget) {
1555 		napi_complete(napi);
1556 		priv->hw->dma->enable_dma_irq(priv->ioaddr, qnum);
1557 	}
1558 
1559 	return work_done;
1560 }
1561 
1562 /**
1563  *  sxgbe_tx_timeout
1564  *  @dev : Pointer to net device structure
1565  *  Description: this function is called when a packet transmission fails to
1566  *   complete within a reasonable time. The driver will mark the error in the
1567  *   netdev structure and arrange for the device to be reset to a sane state
1568  *   in order to transmit a new packet.
1569  */
1570 static void sxgbe_tx_timeout(struct net_device *dev)
1571 {
1572 	struct sxgbe_priv_data *priv = netdev_priv(dev);
1573 
1574 	sxgbe_reset_all_tx_queues(priv);
1575 }
1576 
1577 /**
1578  *  sxgbe_common_interrupt - main ISR
1579  *  @irq: interrupt number.
1580  *  @dev_id: to pass the net device pointer.
1581  *  Description: this is the main driver interrupt service routine.
1582  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
1583  *  interrupts.
1584  */
1585 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id)
1586 {
1587 	struct net_device *netdev = (struct net_device *)dev_id;
1588 	struct sxgbe_priv_data *priv = netdev_priv(netdev);
1589 	int status;
1590 
1591 	status = priv->hw->mac->host_irq_status(priv->ioaddr, &priv->xstats);
1592 	/* For LPI we need to save the tx status */
1593 	if (status & TX_ENTRY_LPI_MODE) {
1594 		priv->xstats.tx_lpi_entry_n++;
1595 		priv->tx_path_in_lpi_mode = true;
1596 	}
1597 	if (status & TX_EXIT_LPI_MODE) {
1598 		priv->xstats.tx_lpi_exit_n++;
1599 		priv->tx_path_in_lpi_mode = false;
1600 	}
1601 	if (status & RX_ENTRY_LPI_MODE)
1602 		priv->xstats.rx_lpi_entry_n++;
1603 	if (status & RX_EXIT_LPI_MODE)
1604 		priv->xstats.rx_lpi_exit_n++;
1605 
1606 	return IRQ_HANDLED;
1607 }
1608 
1609 /**
1610  *  sxgbe_tx_interrupt - TX DMA ISR
1611  *  @irq: interrupt number.
1612  *  @dev_id: to pass the net device pointer.
1613  *  Description: this is the tx dma interrupt service routine.
1614  */
1615 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id)
1616 {
1617 	int status;
1618 	struct sxgbe_tx_queue *txq = (struct sxgbe_tx_queue *)dev_id;
1619 	struct sxgbe_priv_data *priv = txq->priv_ptr;
1620 
1621 	/* get the channel status */
1622 	status = priv->hw->dma->tx_dma_int_status(priv->ioaddr, txq->queue_no,
1623 						  &priv->xstats);
1624 	/* check for normal path */
1625 	if (likely((status & handle_tx)))
1626 		napi_schedule(&priv->napi);
1627 
1628 	/* check for unrecoverable error */
1629 	if (unlikely((status & tx_hard_error)))
1630 		sxgbe_restart_tx_queue(priv, txq->queue_no);
1631 
1632 	/* check for TC configuration change */
1633 	if (unlikely((status & tx_bump_tc) &&
1634 		     (priv->tx_tc != SXGBE_MTL_SFMODE) &&
1635 		     (priv->tx_tc < 512))) {
1636 		/* step of TX TC is 32 till 128, otherwise 64 */
1637 		priv->tx_tc += (priv->tx_tc < 128) ? 32 : 64;
1638 		priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr,
1639 					       txq->queue_no, priv->tx_tc);
1640 		priv->xstats.tx_threshold = priv->tx_tc;
1641 	}
1642 
1643 	return IRQ_HANDLED;
1644 }
1645 
1646 /**
1647  *  sxgbe_rx_interrupt - RX DMA ISR
1648  *  @irq: interrupt number.
1649  *  @dev_id: to pass the net device pointer.
1650  *  Description: this is the rx dma interrupt service routine.
1651  */
1652 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id)
1653 {
1654 	int status;
1655 	struct sxgbe_rx_queue *rxq = (struct sxgbe_rx_queue *)dev_id;
1656 	struct sxgbe_priv_data *priv = rxq->priv_ptr;
1657 
1658 	/* get the channel status */
1659 	status = priv->hw->dma->rx_dma_int_status(priv->ioaddr, rxq->queue_no,
1660 						  &priv->xstats);
1661 
1662 	if (likely((status & handle_rx) && (napi_schedule_prep(&priv->napi)))) {
1663 		priv->hw->dma->disable_dma_irq(priv->ioaddr, rxq->queue_no);
1664 		__napi_schedule(&priv->napi);
1665 	}
1666 
1667 	/* check for TC configuration change */
1668 	if (unlikely((status & rx_bump_tc) &&
1669 		     (priv->rx_tc != SXGBE_MTL_SFMODE) &&
1670 		     (priv->rx_tc < 128))) {
1671 		/* step of TC is 32 */
1672 		priv->rx_tc += 32;
1673 		priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr,
1674 					       rxq->queue_no, priv->rx_tc);
1675 		priv->xstats.rx_threshold = priv->rx_tc;
1676 	}
1677 
1678 	return IRQ_HANDLED;
1679 }
1680 
1681 static inline u64 sxgbe_get_stat64(void __iomem *ioaddr, int reg_lo, int reg_hi)
1682 {
1683 	u64 val = readl(ioaddr + reg_lo);
1684 
1685 	val |= ((u64)readl(ioaddr + reg_hi)) << 32;
1686 
1687 	return val;
1688 }
1689 
1690 
1691 /*  sxgbe_get_stats64 - entry point to see statistical information of device
1692  *  @dev : device pointer.
1693  *  @stats : pointer to hold all the statistical information of device.
1694  *  Description:
1695  *  This function is a driver entry point whenever ifconfig command gets
1696  *  executed to see device statistics. Statistics are number of
1697  *  bytes sent or received, errors occured etc.
1698  *  Return value:
1699  *  This function returns various statistical information of device.
1700  */
1701 static struct rtnl_link_stats64 *sxgbe_get_stats64(struct net_device *dev,
1702 						   struct rtnl_link_stats64 *stats)
1703 {
1704 	struct sxgbe_priv_data *priv = netdev_priv(dev);
1705 	void __iomem *ioaddr = priv->ioaddr;
1706 	u64 count;
1707 
1708 	spin_lock(&priv->stats_lock);
1709 	/* Freeze the counter registers before reading value otherwise it may
1710 	 * get updated by hardware while we are reading them
1711 	 */
1712 	writel(SXGBE_MMC_CTRL_CNT_FRZ, ioaddr + SXGBE_MMC_CTL_REG);
1713 
1714 	stats->rx_bytes = sxgbe_get_stat64(ioaddr,
1715 					   SXGBE_MMC_RXOCTETLO_GCNT_REG,
1716 					   SXGBE_MMC_RXOCTETHI_GCNT_REG);
1717 
1718 	stats->rx_packets = sxgbe_get_stat64(ioaddr,
1719 					     SXGBE_MMC_RXFRAMELO_GBCNT_REG,
1720 					     SXGBE_MMC_RXFRAMEHI_GBCNT_REG);
1721 
1722 	stats->multicast = sxgbe_get_stat64(ioaddr,
1723 					    SXGBE_MMC_RXMULTILO_GCNT_REG,
1724 					    SXGBE_MMC_RXMULTIHI_GCNT_REG);
1725 
1726 	stats->rx_crc_errors = sxgbe_get_stat64(ioaddr,
1727 						SXGBE_MMC_RXCRCERRLO_REG,
1728 						SXGBE_MMC_RXCRCERRHI_REG);
1729 
1730 	stats->rx_length_errors = sxgbe_get_stat64(ioaddr,
1731 						  SXGBE_MMC_RXLENERRLO_REG,
1732 						  SXGBE_MMC_RXLENERRHI_REG);
1733 
1734 	stats->rx_missed_errors = sxgbe_get_stat64(ioaddr,
1735 						   SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG,
1736 						   SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG);
1737 
1738 	stats->tx_bytes = sxgbe_get_stat64(ioaddr,
1739 					   SXGBE_MMC_TXOCTETLO_GCNT_REG,
1740 					   SXGBE_MMC_TXOCTETHI_GCNT_REG);
1741 
1742 	count = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GBCNT_REG,
1743 				 SXGBE_MMC_TXFRAMEHI_GBCNT_REG);
1744 
1745 	stats->tx_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GCNT_REG,
1746 					    SXGBE_MMC_TXFRAMEHI_GCNT_REG);
1747 	stats->tx_errors = count - stats->tx_errors;
1748 	stats->tx_packets = count;
1749 	stats->tx_fifo_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXUFLWLO_GBCNT_REG,
1750 						 SXGBE_MMC_TXUFLWHI_GBCNT_REG);
1751 	writel(0, ioaddr + SXGBE_MMC_CTL_REG);
1752 	spin_unlock(&priv->stats_lock);
1753 
1754 	return stats;
1755 }
1756 
1757 /*  sxgbe_set_features - entry point to set offload features of the device.
1758  *  @dev : device pointer.
1759  *  @features : features which are required to be set.
1760  *  Description:
1761  *  This function is a driver entry point and called by Linux kernel whenever
1762  *  any device features are set or reset by user.
1763  *  Return value:
1764  *  This function returns 0 after setting or resetting device features.
1765  */
1766 static int sxgbe_set_features(struct net_device *dev,
1767 			      netdev_features_t features)
1768 {
1769 	struct sxgbe_priv_data *priv = netdev_priv(dev);
1770 	netdev_features_t changed = dev->features ^ features;
1771 
1772 	if (changed & NETIF_F_RXCSUM) {
1773 		if (features & NETIF_F_RXCSUM) {
1774 			priv->hw->mac->enable_rx_csum(priv->ioaddr);
1775 			priv->rxcsum_insertion = true;
1776 		} else {
1777 			priv->hw->mac->disable_rx_csum(priv->ioaddr);
1778 			priv->rxcsum_insertion = false;
1779 		}
1780 	}
1781 
1782 	return 0;
1783 }
1784 
1785 /*  sxgbe_change_mtu - entry point to change MTU size for the device.
1786  *  @dev : device pointer.
1787  *  @new_mtu : the new MTU size for the device.
1788  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1789  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1790  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1791  *  Return value:
1792  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1793  *  file on failure.
1794  */
1795 static int sxgbe_change_mtu(struct net_device *dev, int new_mtu)
1796 {
1797 	/* RFC 791, page 25, "Every internet module must be able to forward
1798 	 * a datagram of 68 octets without further fragmentation."
1799 	 */
1800 	if (new_mtu < MIN_MTU || (new_mtu > MAX_MTU)) {
1801 		netdev_err(dev, "invalid MTU, MTU should be in between %d and %d\n",
1802 			   MIN_MTU, MAX_MTU);
1803 		return -EINVAL;
1804 	}
1805 
1806 	/* Return if the buffer sizes will not change */
1807 	if (dev->mtu == new_mtu)
1808 		return 0;
1809 
1810 	dev->mtu = new_mtu;
1811 
1812 	if (!netif_running(dev))
1813 		return 0;
1814 
1815 	/* Recevice ring buffer size is needed to be set based on MTU. If MTU is
1816 	 * changed then reinitilisation of the receive ring buffers need to be
1817 	 * done. Hence bring interface down and bring interface back up
1818 	 */
1819 	sxgbe_release(dev);
1820 	return sxgbe_open(dev);
1821 }
1822 
1823 static void sxgbe_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
1824 				unsigned int reg_n)
1825 {
1826 	unsigned long data;
1827 
1828 	data = (addr[5] << 8) | addr[4];
1829 	/* For MAC Addr registers se have to set the Address Enable (AE)
1830 	 * bit that has no effect on the High Reg 0 where the bit 31 (MO)
1831 	 * is RO.
1832 	 */
1833 	writel(data | SXGBE_HI_REG_AE, ioaddr + SXGBE_ADDR_HIGH(reg_n));
1834 	data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
1835 	writel(data, ioaddr + SXGBE_ADDR_LOW(reg_n));
1836 }
1837 
1838 /**
1839  * sxgbe_set_rx_mode - entry point for setting different receive mode of
1840  * a device. unicast, multicast addressing
1841  * @dev : pointer to the device structure
1842  * Description:
1843  * This function is a driver entry point which gets called by the kernel
1844  * whenever different receive mode like unicast, multicast and promiscuous
1845  * must be enabled/disabled.
1846  * Return value:
1847  * void.
1848  */
1849 static void sxgbe_set_rx_mode(struct net_device *dev)
1850 {
1851 	struct sxgbe_priv_data *priv = netdev_priv(dev);
1852 	void __iomem *ioaddr = (void __iomem *)priv->ioaddr;
1853 	unsigned int value = 0;
1854 	u32 mc_filter[2];
1855 	struct netdev_hw_addr *ha;
1856 	int reg = 1;
1857 
1858 	netdev_dbg(dev, "%s: # mcasts %d, # unicast %d\n",
1859 		   __func__, netdev_mc_count(dev), netdev_uc_count(dev));
1860 
1861 	if (dev->flags & IFF_PROMISC) {
1862 		value = SXGBE_FRAME_FILTER_PR;
1863 
1864 	} else if ((netdev_mc_count(dev) > SXGBE_HASH_TABLE_SIZE) ||
1865 		   (dev->flags & IFF_ALLMULTI)) {
1866 		value = SXGBE_FRAME_FILTER_PM;	/* pass all multi */
1867 		writel(0xffffffff, ioaddr + SXGBE_HASH_HIGH);
1868 		writel(0xffffffff, ioaddr + SXGBE_HASH_LOW);
1869 
1870 	} else if (!netdev_mc_empty(dev)) {
1871 		/* Hash filter for multicast */
1872 		value = SXGBE_FRAME_FILTER_HMC;
1873 
1874 		memset(mc_filter, 0, sizeof(mc_filter));
1875 		netdev_for_each_mc_addr(ha, dev) {
1876 			/* The upper 6 bits of the calculated CRC are used to
1877 			 * index the contens of the hash table
1878 			 */
1879 			int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
1880 
1881 			/* The most significant bit determines the register to
1882 			 * use (H/L) while the other 5 bits determine the bit
1883 			 * within the register.
1884 			 */
1885 			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1886 		}
1887 		writel(mc_filter[0], ioaddr + SXGBE_HASH_LOW);
1888 		writel(mc_filter[1], ioaddr + SXGBE_HASH_HIGH);
1889 	}
1890 
1891 	/* Handle multiple unicast addresses (perfect filtering) */
1892 	if (netdev_uc_count(dev) > SXGBE_MAX_PERFECT_ADDRESSES)
1893 		/* Switch to promiscuous mode if more than 16 addrs
1894 		 * are required
1895 		 */
1896 		value |= SXGBE_FRAME_FILTER_PR;
1897 	else {
1898 		netdev_for_each_uc_addr(ha, dev) {
1899 			sxgbe_set_umac_addr(ioaddr, ha->addr, reg);
1900 			reg++;
1901 		}
1902 	}
1903 #ifdef FRAME_FILTER_DEBUG
1904 	/* Enable Receive all mode (to debug filtering_fail errors) */
1905 	value |= SXGBE_FRAME_FILTER_RA;
1906 #endif
1907 	writel(value, ioaddr + SXGBE_FRAME_FILTER);
1908 
1909 	netdev_dbg(dev, "Filter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n",
1910 		   readl(ioaddr + SXGBE_FRAME_FILTER),
1911 		   readl(ioaddr + SXGBE_HASH_HIGH),
1912 		   readl(ioaddr + SXGBE_HASH_LOW));
1913 }
1914 
1915 #ifdef CONFIG_NET_POLL_CONTROLLER
1916 /**
1917  * sxgbe_poll_controller - entry point for polling receive by device
1918  * @dev : pointer to the device structure
1919  * Description:
1920  * This function is used by NETCONSOLE and other diagnostic tools
1921  * to allow network I/O with interrupts disabled.
1922  * Return value:
1923  * Void.
1924  */
1925 static void sxgbe_poll_controller(struct net_device *dev)
1926 {
1927 	struct sxgbe_priv_data *priv = netdev_priv(dev);
1928 
1929 	disable_irq(priv->irq);
1930 	sxgbe_rx_interrupt(priv->irq, dev);
1931 	enable_irq(priv->irq);
1932 }
1933 #endif
1934 
1935 /*  sxgbe_ioctl - Entry point for the Ioctl
1936  *  @dev: Device pointer.
1937  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1938  *  a proprietary structure used to pass information to the driver.
1939  *  @cmd: IOCTL command
1940  *  Description:
1941  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
1942  */
1943 static int sxgbe_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1944 {
1945 	struct sxgbe_priv_data *priv = netdev_priv(dev);
1946 	int ret = -EOPNOTSUPP;
1947 
1948 	if (!netif_running(dev))
1949 		return -EINVAL;
1950 
1951 	switch (cmd) {
1952 	case SIOCGMIIPHY:
1953 	case SIOCGMIIREG:
1954 	case SIOCSMIIREG:
1955 		if (!priv->phydev)
1956 			return -EINVAL;
1957 		ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1958 		break;
1959 	default:
1960 		break;
1961 	}
1962 
1963 	return ret;
1964 }
1965 
1966 static const struct net_device_ops sxgbe_netdev_ops = {
1967 	.ndo_open		= sxgbe_open,
1968 	.ndo_start_xmit		= sxgbe_xmit,
1969 	.ndo_stop		= sxgbe_release,
1970 	.ndo_get_stats64	= sxgbe_get_stats64,
1971 	.ndo_change_mtu		= sxgbe_change_mtu,
1972 	.ndo_set_features	= sxgbe_set_features,
1973 	.ndo_set_rx_mode	= sxgbe_set_rx_mode,
1974 	.ndo_tx_timeout		= sxgbe_tx_timeout,
1975 	.ndo_do_ioctl		= sxgbe_ioctl,
1976 #ifdef CONFIG_NET_POLL_CONTROLLER
1977 	.ndo_poll_controller	= sxgbe_poll_controller,
1978 #endif
1979 	.ndo_set_mac_address	= eth_mac_addr,
1980 };
1981 
1982 /* Get the hardware ops */
1983 static void sxgbe_get_ops(struct sxgbe_ops * const ops_ptr)
1984 {
1985 	ops_ptr->mac		= sxgbe_get_core_ops();
1986 	ops_ptr->desc		= sxgbe_get_desc_ops();
1987 	ops_ptr->dma		= sxgbe_get_dma_ops();
1988 	ops_ptr->mtl		= sxgbe_get_mtl_ops();
1989 
1990 	/* set the MDIO communication Address/Data regisers */
1991 	ops_ptr->mii.addr	= SXGBE_MDIO_SCMD_ADD_REG;
1992 	ops_ptr->mii.data	= SXGBE_MDIO_SCMD_DATA_REG;
1993 
1994 	/* Assigning the default link settings
1995 	 * no SXGBE defined default values to be set in registers,
1996 	 * so assigning as 0 for port and duplex
1997 	 */
1998 	ops_ptr->link.port	= 0;
1999 	ops_ptr->link.duplex	= 0;
2000 	ops_ptr->link.speed	= SXGBE_SPEED_10G;
2001 }
2002 
2003 /**
2004  *  sxgbe_hw_init - Init the GMAC device
2005  *  @priv: driver private structure
2006  *  Description: this function checks the HW capability
2007  *  (if supported) and sets the driver's features.
2008  */
2009 static int sxgbe_hw_init(struct sxgbe_priv_data * const priv)
2010 {
2011 	u32 ctrl_ids;
2012 
2013 	priv->hw = kmalloc(sizeof(*priv->hw), GFP_KERNEL);
2014 	if(!priv->hw)
2015 		return -ENOMEM;
2016 
2017 	/* get the hardware ops */
2018 	sxgbe_get_ops(priv->hw);
2019 
2020 	/* get the controller id */
2021 	ctrl_ids = priv->hw->mac->get_controller_version(priv->ioaddr);
2022 	priv->hw->ctrl_uid = (ctrl_ids & 0x00ff0000) >> 16;
2023 	priv->hw->ctrl_id = (ctrl_ids & 0x000000ff);
2024 	pr_info("user ID: 0x%x, Controller ID: 0x%x\n",
2025 		priv->hw->ctrl_uid, priv->hw->ctrl_id);
2026 
2027 	/* get the H/W features */
2028 	if (!sxgbe_get_hw_features(priv))
2029 		pr_info("Hardware features not found\n");
2030 
2031 	if (priv->hw_cap.tx_csum_offload)
2032 		pr_info("TX Checksum offload supported\n");
2033 
2034 	if (priv->hw_cap.rx_csum_offload)
2035 		pr_info("RX Checksum offload supported\n");
2036 
2037 	return 0;
2038 }
2039 
2040 static int sxgbe_sw_reset(void __iomem *addr)
2041 {
2042 	int retry_count = 10;
2043 
2044 	writel(SXGBE_DMA_SOFT_RESET, addr + SXGBE_DMA_MODE_REG);
2045 	while (retry_count--) {
2046 		if (!(readl(addr + SXGBE_DMA_MODE_REG) &
2047 		      SXGBE_DMA_SOFT_RESET))
2048 			break;
2049 		mdelay(10);
2050 	}
2051 
2052 	if (retry_count < 0)
2053 		return -EBUSY;
2054 
2055 	return 0;
2056 }
2057 
2058 /**
2059  * sxgbe_drv_probe
2060  * @device: device pointer
2061  * @plat_dat: platform data pointer
2062  * @addr: iobase memory address
2063  * Description: this is the main probe function used to
2064  * call the alloc_etherdev, allocate the priv structure.
2065  */
2066 struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
2067 					struct sxgbe_plat_data *plat_dat,
2068 					void __iomem *addr)
2069 {
2070 	struct sxgbe_priv_data *priv;
2071 	struct net_device *ndev;
2072 	int ret;
2073 	u8 queue_num;
2074 
2075 	ndev = alloc_etherdev_mqs(sizeof(struct sxgbe_priv_data),
2076 				  SXGBE_TX_QUEUES, SXGBE_RX_QUEUES);
2077 	if (!ndev)
2078 		return NULL;
2079 
2080 	SET_NETDEV_DEV(ndev, device);
2081 
2082 	priv = netdev_priv(ndev);
2083 	priv->device = device;
2084 	priv->dev = ndev;
2085 
2086 	sxgbe_set_ethtool_ops(ndev);
2087 	priv->plat = plat_dat;
2088 	priv->ioaddr = addr;
2089 
2090 	ret = sxgbe_sw_reset(priv->ioaddr);
2091 	if (ret)
2092 		goto error_free_netdev;
2093 
2094 	/* Verify driver arguments */
2095 	sxgbe_verify_args();
2096 
2097 	/* Init MAC and get the capabilities */
2098 	ret = sxgbe_hw_init(priv);
2099 	if (ret)
2100 		goto error_free_netdev;
2101 
2102 	/* allocate memory resources for Descriptor rings */
2103 	ret = txring_mem_alloc(priv);
2104 	if (ret)
2105 		goto error_free_hw;
2106 
2107 	ret = rxring_mem_alloc(priv);
2108 	if (ret)
2109 		goto error_free_hw;
2110 
2111 	ndev->netdev_ops = &sxgbe_netdev_ops;
2112 
2113 	ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2114 		NETIF_F_RXCSUM | NETIF_F_TSO | NETIF_F_TSO6 |
2115 		NETIF_F_GRO;
2116 	ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2117 	ndev->watchdog_timeo = msecs_to_jiffies(TX_TIMEO);
2118 
2119 	/* assign filtering support */
2120 	ndev->priv_flags |= IFF_UNICAST_FLT;
2121 
2122 	priv->msg_enable = netif_msg_init(debug, default_msg_level);
2123 
2124 	/* Enable TCP segmentation offload for all DMA channels */
2125 	if (priv->hw_cap.tcpseg_offload) {
2126 		SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
2127 			priv->hw->dma->enable_tso(priv->ioaddr, queue_num);
2128 		}
2129 	}
2130 
2131 	/* Enable Rx checksum offload */
2132 	if (priv->hw_cap.rx_csum_offload) {
2133 		priv->hw->mac->enable_rx_csum(priv->ioaddr);
2134 		priv->rxcsum_insertion = true;
2135 	}
2136 
2137 	/* Initialise pause frame settings */
2138 	priv->rx_pause = 1;
2139 	priv->tx_pause = 1;
2140 
2141 	/* Rx Watchdog is available, enable depend on platform data */
2142 	if (!priv->plat->riwt_off) {
2143 		priv->use_riwt = 1;
2144 		pr_info("Enable RX Mitigation via HW Watchdog Timer\n");
2145 	}
2146 
2147 	netif_napi_add(ndev, &priv->napi, sxgbe_poll, 64);
2148 
2149 	spin_lock_init(&priv->stats_lock);
2150 
2151 	priv->sxgbe_clk = clk_get(priv->device, SXGBE_RESOURCE_NAME);
2152 	if (IS_ERR(priv->sxgbe_clk)) {
2153 		netdev_warn(ndev, "%s: warning: cannot get CSR clock\n",
2154 			    __func__);
2155 		goto error_napi_del;
2156 	}
2157 
2158 	/* If a specific clk_csr value is passed from the platform
2159 	 * this means that the CSR Clock Range selection cannot be
2160 	 * changed at run-time and it is fixed. Viceversa the driver'll try to
2161 	 * set the MDC clock dynamically according to the csr actual
2162 	 * clock input.
2163 	 */
2164 	if (!priv->plat->clk_csr)
2165 		sxgbe_clk_csr_set(priv);
2166 	else
2167 		priv->clk_csr = priv->plat->clk_csr;
2168 
2169 	/* MDIO bus Registration */
2170 	ret = sxgbe_mdio_register(ndev);
2171 	if (ret < 0) {
2172 		netdev_dbg(ndev, "%s: MDIO bus (id: %d) registration failed\n",
2173 			   __func__, priv->plat->bus_id);
2174 		goto error_clk_put;
2175 	}
2176 
2177 	ret = register_netdev(ndev);
2178 	if (ret) {
2179 		pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2180 		goto error_mdio_unregister;
2181 	}
2182 
2183 	sxgbe_check_ether_addr(priv);
2184 
2185 	return priv;
2186 
2187 error_mdio_unregister:
2188 	sxgbe_mdio_unregister(ndev);
2189 error_clk_put:
2190 	clk_put(priv->sxgbe_clk);
2191 error_napi_del:
2192 	netif_napi_del(&priv->napi);
2193 error_free_hw:
2194 	kfree(priv->hw);
2195 error_free_netdev:
2196 	free_netdev(ndev);
2197 
2198 	return NULL;
2199 }
2200 
2201 /**
2202  * sxgbe_drv_remove
2203  * @ndev: net device pointer
2204  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2205  * changes the link status, releases the DMA descriptor rings.
2206  */
2207 int sxgbe_drv_remove(struct net_device *ndev)
2208 {
2209 	struct sxgbe_priv_data *priv = netdev_priv(ndev);
2210 	u8 queue_num;
2211 
2212 	netdev_info(ndev, "%s: removing driver\n", __func__);
2213 
2214 	SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
2215 		priv->hw->mac->disable_rxqueue(priv->ioaddr, queue_num);
2216 	}
2217 
2218 	priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
2219 	priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
2220 
2221 	priv->hw->mac->enable_tx(priv->ioaddr, false);
2222 	priv->hw->mac->enable_rx(priv->ioaddr, false);
2223 
2224 	unregister_netdev(ndev);
2225 
2226 	sxgbe_mdio_unregister(ndev);
2227 
2228 	clk_put(priv->sxgbe_clk);
2229 
2230 	netif_napi_del(&priv->napi);
2231 
2232 	kfree(priv->hw);
2233 
2234 	free_netdev(ndev);
2235 
2236 	return 0;
2237 }
2238 
2239 #ifdef CONFIG_PM
2240 int sxgbe_suspend(struct net_device *ndev)
2241 {
2242 	return 0;
2243 }
2244 
2245 int sxgbe_resume(struct net_device *ndev)
2246 {
2247 	return 0;
2248 }
2249 
2250 int sxgbe_freeze(struct net_device *ndev)
2251 {
2252 	return -ENOSYS;
2253 }
2254 
2255 int sxgbe_restore(struct net_device *ndev)
2256 {
2257 	return -ENOSYS;
2258 }
2259 #endif /* CONFIG_PM */
2260 
2261 /* Driver is configured as Platform driver */
2262 static int __init sxgbe_init(void)
2263 {
2264 	int ret;
2265 
2266 	ret = sxgbe_register_platform();
2267 	if (ret)
2268 		goto err;
2269 	return 0;
2270 err:
2271 	pr_err("driver registration failed\n");
2272 	return ret;
2273 }
2274 
2275 static void __exit sxgbe_exit(void)
2276 {
2277 	sxgbe_unregister_platform();
2278 }
2279 
2280 module_init(sxgbe_init);
2281 module_exit(sxgbe_exit);
2282 
2283 #ifndef MODULE
2284 static int __init sxgbe_cmdline_opt(char *str)
2285 {
2286 	char *opt;
2287 
2288 	if (!str || !*str)
2289 		return -EINVAL;
2290 	while ((opt = strsep(&str, ",")) != NULL) {
2291 		if (!strncmp(opt, "eee_timer:", 6)) {
2292 			if (kstrtoint(opt + 10, 0, &eee_timer))
2293 				goto err;
2294 		}
2295 	}
2296 	return 0;
2297 
2298 err:
2299 	pr_err("%s: ERROR broken module parameter conversion\n", __func__);
2300 	return -EINVAL;
2301 }
2302 
2303 __setup("sxgbeeth=", sxgbe_cmdline_opt);
2304 #endif /* MODULE */
2305 
2306 
2307 
2308 MODULE_DESCRIPTION("SAMSUNG 10G/2.5G/1G Ethernet PLATFORM driver");
2309 
2310 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
2311 MODULE_PARM_DESC(eee_timer, "EEE-LPI Default LS timer value");
2312 
2313 MODULE_AUTHOR("Siva Reddy Kallam <siva.kallam@samsung.com>");
2314 MODULE_AUTHOR("ByungHo An <bh74.an@samsung.com>");
2315 MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>");
2316 MODULE_AUTHOR("Vipul Pandya <vipul.pandya@samsung.com>");
2317 
2318 MODULE_LICENSE("GPL");
2319