1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 10G controller driver for Samsung SoCs 3 * 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Author: Siva Reddy Kallam <siva.kallam@samsung.com> 8 */ 9 #ifndef __SXGBE_DESC_H__ 10 #define __SXGBE_DESC_H__ 11 12 #define SXGBE_DESC_SIZE_BYTES 16 13 14 /* forward declaration */ 15 struct sxgbe_extra_stats; 16 17 /* Transmit checksum insertion control */ 18 enum tdes_csum_insertion { 19 cic_disabled = 0, /* Checksum Insertion Control */ 20 cic_only_ip = 1, /* Only IP header */ 21 /* IP header but pseudoheader is not calculated */ 22 cic_no_pseudoheader = 2, 23 cic_full = 3, /* IP header and pseudoheader */ 24 }; 25 26 struct sxgbe_tx_norm_desc { 27 u64 tdes01; /* buf1 address */ 28 union { 29 /* TX Read-Format Desc 2,3 */ 30 struct { 31 /* TDES2 */ 32 u32 buf1_size:14; 33 u32 vlan_tag_ctl:2; 34 u32 buf2_size:14; 35 u32 timestmp_enable:1; 36 u32 int_on_com:1; 37 /* TDES3 */ 38 union { 39 u16 tcp_payload_len; 40 struct { 41 u32 total_pkt_len:15; 42 u32 reserved1:1; 43 } pkt_len; 44 } tx_pkt_len; 45 46 u16 cksum_ctl:2; 47 u16 tse_bit:1; 48 u16 tcp_hdr_len:4; 49 u16 sa_insert_ctl:3; 50 u16 crc_pad_ctl:2; 51 u16 last_desc:1; 52 u16 first_desc:1; 53 u16 ctxt_bit:1; 54 u16 own_bit:1; 55 } tx_rd_des23; 56 57 /* tx write back Desc 2,3 */ 58 struct { 59 /* WB TES2 */ 60 u32 reserved1; 61 /* WB TES3 */ 62 u32 reserved2:31; 63 u32 own_bit:1; 64 } tx_wb_des23; 65 } tdes23; 66 }; 67 68 struct sxgbe_rx_norm_desc { 69 union { 70 u64 rdes01; /* buf1 address */ 71 union { 72 u32 out_vlan_tag:16; 73 u32 in_vlan_tag:16; 74 u32 rss_hash; 75 } rx_wb_des01; 76 } rdes01; 77 78 union { 79 /* RX Read format Desc 2,3 */ 80 struct{ 81 /* RDES2 */ 82 u64 buf2_addr:62; 83 /* RDES3 */ 84 u32 int_on_com:1; 85 u32 own_bit:1; 86 } rx_rd_des23; 87 88 /* RX write back */ 89 struct{ 90 /* WB RDES2 */ 91 u32 hdr_len:10; 92 u32 rdes2_reserved:2; 93 u32 elrd_val:1; 94 u32 iovt_sel:1; 95 u32 res_pkt:1; 96 u32 vlan_filter_match:1; 97 u32 sa_filter_fail:1; 98 u32 da_filter_fail:1; 99 u32 hash_filter_pass:1; 100 u32 macaddr_filter_match:8; 101 u32 l3_filter_match:1; 102 u32 l4_filter_match:1; 103 u32 l34_filter_num:3; 104 105 /* WB RDES3 */ 106 u32 pkt_len:14; 107 u32 rdes3_reserved:1; 108 u32 err_summary:1; 109 u32 err_l2_type:4; 110 u32 layer34_pkt_type:4; 111 u32 no_coagulation_pkt:1; 112 u32 in_seq_pkt:1; 113 u32 rss_valid:1; 114 u32 context_des_avail:1; 115 u32 last_desc:1; 116 u32 first_desc:1; 117 u32 recv_context_desc:1; 118 u32 own_bit:1; 119 } rx_wb_des23; 120 } rdes23; 121 }; 122 123 /* Context descriptor structure */ 124 struct sxgbe_tx_ctxt_desc { 125 u32 tstamp_lo; 126 u32 tstamp_hi; 127 u32 maxseg_size:15; 128 u32 reserved1:1; 129 u32 ivlan_tag:16; 130 u32 vlan_tag:16; 131 u32 vltag_valid:1; 132 u32 ivlan_tag_valid:1; 133 u32 ivlan_tag_ctl:2; 134 u32 reserved2:3; 135 u32 ctxt_desc_err:1; 136 u32 reserved3:2; 137 u32 ostc:1; 138 u32 tcmssv:1; 139 u32 reserved4:2; 140 u32 ctxt_bit:1; 141 u32 own_bit:1; 142 }; 143 144 struct sxgbe_rx_ctxt_desc { 145 u32 tstamp_lo; 146 u32 tstamp_hi; 147 u32 reserved1; 148 u32 ptp_msgtype:4; 149 u32 tstamp_available:1; 150 u32 ptp_rsp_err:1; 151 u32 tstamp_dropped:1; 152 u32 reserved2:23; 153 u32 rx_ctxt_desc:1; 154 u32 own_bit:1; 155 }; 156 157 struct sxgbe_desc_ops { 158 /* DMA TX descriptor ring initialization */ 159 void (*init_tx_desc)(struct sxgbe_tx_norm_desc *p); 160 161 /* Invoked by the xmit function to prepare the tx descriptor */ 162 void (*tx_desc_enable_tse)(struct sxgbe_tx_norm_desc *p, u8 is_tse, 163 u32 total_hdr_len, u32 tcp_hdr_len, 164 u32 tcp_payload_len); 165 166 /* Assign buffer lengths for descriptor */ 167 void (*prepare_tx_desc)(struct sxgbe_tx_norm_desc *p, u8 is_fd, 168 int buf1_len, int pkt_len, int cksum); 169 170 /* Set VLAN control information */ 171 void (*tx_vlanctl_desc)(struct sxgbe_tx_norm_desc *p, int vlan_ctl); 172 173 /* Set the owner of the descriptor */ 174 void (*set_tx_owner)(struct sxgbe_tx_norm_desc *p); 175 176 /* Get the owner of the descriptor */ 177 int (*get_tx_owner)(struct sxgbe_tx_norm_desc *p); 178 179 /* Invoked by the xmit function to close the tx descriptor */ 180 void (*close_tx_desc)(struct sxgbe_tx_norm_desc *p); 181 182 /* Clean the tx descriptor as soon as the tx irq is received */ 183 void (*release_tx_desc)(struct sxgbe_tx_norm_desc *p); 184 185 /* Clear interrupt on tx frame completion. When this bit is 186 * set an interrupt happens as soon as the frame is transmitted 187 */ 188 void (*clear_tx_ic)(struct sxgbe_tx_norm_desc *p); 189 190 /* Last tx segment reports the transmit status */ 191 int (*get_tx_ls)(struct sxgbe_tx_norm_desc *p); 192 193 /* Get the buffer size from the descriptor */ 194 int (*get_tx_len)(struct sxgbe_tx_norm_desc *p); 195 196 /* Set tx timestamp enable bit */ 197 void (*tx_enable_tstamp)(struct sxgbe_tx_norm_desc *p); 198 199 /* get tx timestamp status */ 200 int (*get_tx_timestamp_status)(struct sxgbe_tx_norm_desc *p); 201 202 /* TX Context Descripto Specific */ 203 void (*tx_ctxt_desc_set_ctxt)(struct sxgbe_tx_ctxt_desc *p); 204 205 /* Set the owner of the TX context descriptor */ 206 void (*tx_ctxt_desc_set_owner)(struct sxgbe_tx_ctxt_desc *p); 207 208 /* Get the owner of the TX context descriptor */ 209 int (*get_tx_ctxt_owner)(struct sxgbe_tx_ctxt_desc *p); 210 211 /* Set TX mss */ 212 void (*tx_ctxt_desc_set_mss)(struct sxgbe_tx_ctxt_desc *p, u16 mss); 213 214 /* Set TX mss */ 215 int (*tx_ctxt_desc_get_mss)(struct sxgbe_tx_ctxt_desc *p); 216 217 /* Set TX tcmssv */ 218 void (*tx_ctxt_desc_set_tcmssv)(struct sxgbe_tx_ctxt_desc *p); 219 220 /* Reset TX ostc */ 221 void (*tx_ctxt_desc_reset_ostc)(struct sxgbe_tx_ctxt_desc *p); 222 223 /* Set IVLAN information */ 224 void (*tx_ctxt_desc_set_ivlantag)(struct sxgbe_tx_ctxt_desc *p, 225 int is_ivlanvalid, int ivlan_tag, 226 int ivlan_ctl); 227 228 /* Return IVLAN Tag */ 229 int (*tx_ctxt_desc_get_ivlantag)(struct sxgbe_tx_ctxt_desc *p); 230 231 /* Set VLAN Tag */ 232 void (*tx_ctxt_desc_set_vlantag)(struct sxgbe_tx_ctxt_desc *p, 233 int is_vlanvalid, int vlan_tag); 234 235 /* Return VLAN Tag */ 236 int (*tx_ctxt_desc_get_vlantag)(struct sxgbe_tx_ctxt_desc *p); 237 238 /* Set Time stamp */ 239 void (*tx_ctxt_set_tstamp)(struct sxgbe_tx_ctxt_desc *p, 240 u8 ostc_enable, u64 tstamp); 241 242 /* Close TX context descriptor */ 243 void (*close_tx_ctxt_desc)(struct sxgbe_tx_ctxt_desc *p); 244 245 /* WB status of context descriptor */ 246 int (*get_tx_ctxt_cde)(struct sxgbe_tx_ctxt_desc *p); 247 248 /* DMA RX descriptor ring initialization */ 249 void (*init_rx_desc)(struct sxgbe_rx_norm_desc *p, int disable_rx_ic, 250 int mode, int end); 251 252 /* Get own bit */ 253 int (*get_rx_owner)(struct sxgbe_rx_norm_desc *p); 254 255 /* Set own bit */ 256 void (*set_rx_owner)(struct sxgbe_rx_norm_desc *p); 257 258 /* Set Interrupt on completion bit */ 259 void (*set_rx_int_on_com)(struct sxgbe_rx_norm_desc *p); 260 261 /* Get the receive frame size */ 262 int (*get_rx_frame_len)(struct sxgbe_rx_norm_desc *p); 263 264 /* Return first Descriptor status */ 265 int (*get_rx_fd_status)(struct sxgbe_rx_norm_desc *p); 266 267 /* Return first Descriptor status */ 268 int (*get_rx_ld_status)(struct sxgbe_rx_norm_desc *p); 269 270 /* Return the reception status looking at the RDES1 */ 271 int (*rx_wbstatus)(struct sxgbe_rx_norm_desc *p, 272 struct sxgbe_extra_stats *x, int *checksum); 273 274 /* Get own bit */ 275 int (*get_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p); 276 277 /* Set own bit */ 278 void (*set_rx_ctxt_owner)(struct sxgbe_rx_ctxt_desc *p); 279 280 /* Return the reception status looking at Context control information */ 281 void (*rx_ctxt_wbstatus)(struct sxgbe_rx_ctxt_desc *p, 282 struct sxgbe_extra_stats *x); 283 284 /* Get rx timestamp status */ 285 int (*get_rx_ctxt_tstamp_status)(struct sxgbe_rx_ctxt_desc *p); 286 287 /* Get timestamp value for rx, need to check this */ 288 u64 (*get_timestamp)(struct sxgbe_rx_ctxt_desc *p); 289 }; 290 291 const struct sxgbe_desc_ops *sxgbe_get_desc_ops(void); 292 293 #endif /* __SXGBE_DESC_H__ */ 294