1 /* 2 * drivers/net/ethernet/rocker/rocker.h - Rocker switch device driver 3 * Copyright (c) 2014 Jiri Pirko <jiri@resnulli.us> 4 * Copyright (c) 2014 Scott Feldman <sfeldma@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef _ROCKER_H 13 #define _ROCKER_H 14 15 #include <linux/types.h> 16 17 /* Return codes */ 18 enum { 19 ROCKER_OK = 0, 20 ROCKER_ENOENT = 2, 21 ROCKER_ENXIO = 6, 22 ROCKER_ENOMEM = 12, 23 ROCKER_EEXIST = 17, 24 ROCKER_EINVAL = 22, 25 ROCKER_EMSGSIZE = 90, 26 ROCKER_ENOTSUP = 95, 27 ROCKER_ENOBUFS = 105, 28 }; 29 30 #define ROCKER_FP_PORTS_MAX 62 31 32 #define PCI_VENDOR_ID_REDHAT 0x1b36 33 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 34 35 #define ROCKER_PCI_BAR0_SIZE 0x2000 36 37 /* MSI-X vectors */ 38 enum { 39 ROCKER_MSIX_VEC_CMD, 40 ROCKER_MSIX_VEC_EVENT, 41 ROCKER_MSIX_VEC_TEST, 42 ROCKER_MSIX_VEC_RESERVED0, 43 __ROCKER_MSIX_VEC_TX, 44 __ROCKER_MSIX_VEC_RX, 45 #define ROCKER_MSIX_VEC_TX(port) \ 46 (__ROCKER_MSIX_VEC_TX + ((port) * 2)) 47 #define ROCKER_MSIX_VEC_RX(port) \ 48 (__ROCKER_MSIX_VEC_RX + ((port) * 2)) 49 #define ROCKER_MSIX_VEC_COUNT(portcnt) \ 50 (ROCKER_MSIX_VEC_RX((portcnt - 1)) + 1) 51 }; 52 53 /* Rocker bogus registers */ 54 #define ROCKER_BOGUS_REG0 0x0000 55 #define ROCKER_BOGUS_REG1 0x0004 56 #define ROCKER_BOGUS_REG2 0x0008 57 #define ROCKER_BOGUS_REG3 0x000c 58 59 /* Rocker test registers */ 60 #define ROCKER_TEST_REG 0x0010 61 #define ROCKER_TEST_REG64 0x0018 /* 8-byte */ 62 #define ROCKER_TEST_IRQ 0x0020 63 #define ROCKER_TEST_DMA_ADDR 0x0028 /* 8-byte */ 64 #define ROCKER_TEST_DMA_SIZE 0x0030 65 #define ROCKER_TEST_DMA_CTRL 0x0034 66 67 /* Rocker test register ctrl */ 68 #define ROCKER_TEST_DMA_CTRL_CLEAR (1 << 0) 69 #define ROCKER_TEST_DMA_CTRL_FILL (1 << 1) 70 #define ROCKER_TEST_DMA_CTRL_INVERT (1 << 2) 71 72 /* Rocker DMA ring register offsets */ 73 #define ROCKER_DMA_DESC_ADDR(x) (0x1000 + (x) * 32) /* 8-byte */ 74 #define ROCKER_DMA_DESC_SIZE(x) (0x1008 + (x) * 32) 75 #define ROCKER_DMA_DESC_HEAD(x) (0x100c + (x) * 32) 76 #define ROCKER_DMA_DESC_TAIL(x) (0x1010 + (x) * 32) 77 #define ROCKER_DMA_DESC_CTRL(x) (0x1014 + (x) * 32) 78 #define ROCKER_DMA_DESC_CREDITS(x) (0x1018 + (x) * 32) 79 #define ROCKER_DMA_DESC_RES1(x) (0x101c + (x) * 32) 80 81 /* Rocker dma ctrl register bits */ 82 #define ROCKER_DMA_DESC_CTRL_RESET (1 << 0) 83 84 /* Rocker DMA ring types */ 85 enum rocker_dma_type { 86 ROCKER_DMA_CMD, 87 ROCKER_DMA_EVENT, 88 __ROCKER_DMA_TX, 89 __ROCKER_DMA_RX, 90 #define ROCKER_DMA_TX(port) (__ROCKER_DMA_TX + (port) * 2) 91 #define ROCKER_DMA_RX(port) (__ROCKER_DMA_RX + (port) * 2) 92 }; 93 94 /* Rocker DMA ring size limits and default sizes */ 95 #define ROCKER_DMA_SIZE_MIN 2ul 96 #define ROCKER_DMA_SIZE_MAX 65536ul 97 #define ROCKER_DMA_CMD_DEFAULT_SIZE 32ul 98 #define ROCKER_DMA_EVENT_DEFAULT_SIZE 32ul 99 #define ROCKER_DMA_TX_DEFAULT_SIZE 64ul 100 #define ROCKER_DMA_TX_DESC_SIZE 256 101 #define ROCKER_DMA_RX_DEFAULT_SIZE 64ul 102 #define ROCKER_DMA_RX_DESC_SIZE 256 103 104 /* Rocker DMA descriptor struct */ 105 struct rocker_desc { 106 u64 buf_addr; 107 u64 cookie; 108 u16 buf_size; 109 u16 tlv_size; 110 u16 resv[5]; 111 u16 comp_err; 112 }; 113 114 #define ROCKER_DMA_DESC_COMP_ERR_GEN (1 << 15) 115 116 /* Rocker DMA TLV struct */ 117 struct rocker_tlv { 118 u32 type; 119 u16 len; 120 }; 121 122 /* TLVs */ 123 enum { 124 ROCKER_TLV_CMD_UNSPEC, 125 ROCKER_TLV_CMD_TYPE, /* u16 */ 126 ROCKER_TLV_CMD_INFO, /* nest */ 127 128 __ROCKER_TLV_CMD_MAX, 129 ROCKER_TLV_CMD_MAX = __ROCKER_TLV_CMD_MAX - 1, 130 }; 131 132 enum { 133 ROCKER_TLV_CMD_TYPE_UNSPEC, 134 ROCKER_TLV_CMD_TYPE_GET_PORT_SETTINGS, 135 ROCKER_TLV_CMD_TYPE_SET_PORT_SETTINGS, 136 ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_ADD, 137 ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_MOD, 138 ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_DEL, 139 ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_GET_STATS, 140 ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_ADD, 141 ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_MOD, 142 ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_DEL, 143 ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_GET_STATS, 144 145 ROCKER_TLV_CMD_TYPE_CLEAR_PORT_STATS, 146 ROCKER_TLV_CMD_TYPE_GET_PORT_STATS, 147 148 __ROCKER_TLV_CMD_TYPE_MAX, 149 ROCKER_TLV_CMD_TYPE_MAX = __ROCKER_TLV_CMD_TYPE_MAX - 1, 150 }; 151 152 enum { 153 ROCKER_TLV_CMD_PORT_SETTINGS_UNSPEC, 154 ROCKER_TLV_CMD_PORT_SETTINGS_PPORT, /* u32 */ 155 ROCKER_TLV_CMD_PORT_SETTINGS_SPEED, /* u32 */ 156 ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX, /* u8 */ 157 ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG, /* u8 */ 158 ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR, /* binary */ 159 ROCKER_TLV_CMD_PORT_SETTINGS_MODE, /* u8 */ 160 ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING, /* u8 */ 161 162 __ROCKER_TLV_CMD_PORT_SETTINGS_MAX, 163 ROCKER_TLV_CMD_PORT_SETTINGS_MAX = 164 __ROCKER_TLV_CMD_PORT_SETTINGS_MAX - 1, 165 }; 166 167 enum { 168 ROCKER_TLV_CMD_PORT_STATS_UNSPEC, 169 ROCKER_TLV_CMD_PORT_STATS_PPORT, /* u32 */ 170 171 ROCKER_TLV_CMD_PORT_STATS_RX_PKTS, /* u64 */ 172 ROCKER_TLV_CMD_PORT_STATS_RX_BYTES, /* u64 */ 173 ROCKER_TLV_CMD_PORT_STATS_RX_DROPPED, /* u64 */ 174 ROCKER_TLV_CMD_PORT_STATS_RX_ERRORS, /* u64 */ 175 176 ROCKER_TLV_CMD_PORT_STATS_TX_PKTS, /* u64 */ 177 ROCKER_TLV_CMD_PORT_STATS_TX_BYTES, /* u64 */ 178 ROCKER_TLV_CMD_PORT_STATS_TX_DROPPED, /* u64 */ 179 ROCKER_TLV_CMD_PORT_STATS_TX_ERRORS, /* u64 */ 180 181 __ROCKER_TLV_CMD_PORT_STATS_MAX, 182 ROCKER_TLV_CMD_PORT_STATS_MAX = __ROCKER_TLV_CMD_PORT_STATS_MAX - 1, 183 }; 184 185 enum rocker_port_mode { 186 ROCKER_PORT_MODE_OF_DPA, 187 }; 188 189 enum { 190 ROCKER_TLV_EVENT_UNSPEC, 191 ROCKER_TLV_EVENT_TYPE, /* u16 */ 192 ROCKER_TLV_EVENT_INFO, /* nest */ 193 194 __ROCKER_TLV_EVENT_MAX, 195 ROCKER_TLV_EVENT_MAX = __ROCKER_TLV_EVENT_MAX - 1, 196 }; 197 198 enum { 199 ROCKER_TLV_EVENT_TYPE_UNSPEC, 200 ROCKER_TLV_EVENT_TYPE_LINK_CHANGED, 201 ROCKER_TLV_EVENT_TYPE_MAC_VLAN_SEEN, 202 203 __ROCKER_TLV_EVENT_TYPE_MAX, 204 ROCKER_TLV_EVENT_TYPE_MAX = __ROCKER_TLV_EVENT_TYPE_MAX - 1, 205 }; 206 207 enum { 208 ROCKER_TLV_EVENT_LINK_CHANGED_UNSPEC, 209 ROCKER_TLV_EVENT_LINK_CHANGED_PPORT, /* u32 */ 210 ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP, /* u8 */ 211 212 __ROCKER_TLV_EVENT_LINK_CHANGED_MAX, 213 ROCKER_TLV_EVENT_LINK_CHANGED_MAX = 214 __ROCKER_TLV_EVENT_LINK_CHANGED_MAX - 1, 215 }; 216 217 enum { 218 ROCKER_TLV_EVENT_MAC_VLAN_UNSPEC, 219 ROCKER_TLV_EVENT_MAC_VLAN_PPORT, /* u32 */ 220 ROCKER_TLV_EVENT_MAC_VLAN_MAC, /* binary */ 221 ROCKER_TLV_EVENT_MAC_VLAN_VLAN_ID, /* __be16 */ 222 223 __ROCKER_TLV_EVENT_MAC_VLAN_MAX, 224 ROCKER_TLV_EVENT_MAC_VLAN_MAX = __ROCKER_TLV_EVENT_MAC_VLAN_MAX - 1, 225 }; 226 227 enum { 228 ROCKER_TLV_RX_UNSPEC, 229 ROCKER_TLV_RX_FLAGS, /* u16, see ROCKER_RX_FLAGS_ */ 230 ROCKER_TLV_RX_CSUM, /* u16 */ 231 ROCKER_TLV_RX_FRAG_ADDR, /* u64 */ 232 ROCKER_TLV_RX_FRAG_MAX_LEN, /* u16 */ 233 ROCKER_TLV_RX_FRAG_LEN, /* u16 */ 234 235 __ROCKER_TLV_RX_MAX, 236 ROCKER_TLV_RX_MAX = __ROCKER_TLV_RX_MAX - 1, 237 }; 238 239 #define ROCKER_RX_FLAGS_IPV4 (1 << 0) 240 #define ROCKER_RX_FLAGS_IPV6 (1 << 1) 241 #define ROCKER_RX_FLAGS_CSUM_CALC (1 << 2) 242 #define ROCKER_RX_FLAGS_IPV4_CSUM_GOOD (1 << 3) 243 #define ROCKER_RX_FLAGS_IP_FRAG (1 << 4) 244 #define ROCKER_RX_FLAGS_TCP (1 << 5) 245 #define ROCKER_RX_FLAGS_UDP (1 << 6) 246 #define ROCKER_RX_FLAGS_TCP_UDP_CSUM_GOOD (1 << 7) 247 248 enum { 249 ROCKER_TLV_TX_UNSPEC, 250 ROCKER_TLV_TX_OFFLOAD, /* u8, see ROCKER_TX_OFFLOAD_ */ 251 ROCKER_TLV_TX_L3_CSUM_OFF, /* u16 */ 252 ROCKER_TLV_TX_TSO_MSS, /* u16 */ 253 ROCKER_TLV_TX_TSO_HDR_LEN, /* u16 */ 254 ROCKER_TLV_TX_FRAGS, /* array */ 255 256 __ROCKER_TLV_TX_MAX, 257 ROCKER_TLV_TX_MAX = __ROCKER_TLV_TX_MAX - 1, 258 }; 259 260 #define ROCKER_TX_OFFLOAD_NONE 0 261 #define ROCKER_TX_OFFLOAD_IP_CSUM 1 262 #define ROCKER_TX_OFFLOAD_TCP_UDP_CSUM 2 263 #define ROCKER_TX_OFFLOAD_L3_CSUM 3 264 #define ROCKER_TX_OFFLOAD_TSO 4 265 266 #define ROCKER_TX_FRAGS_MAX 16 267 268 enum { 269 ROCKER_TLV_TX_FRAG_UNSPEC, 270 ROCKER_TLV_TX_FRAG, /* nest */ 271 272 __ROCKER_TLV_TX_FRAG_MAX, 273 ROCKER_TLV_TX_FRAG_MAX = __ROCKER_TLV_TX_FRAG_MAX - 1, 274 }; 275 276 enum { 277 ROCKER_TLV_TX_FRAG_ATTR_UNSPEC, 278 ROCKER_TLV_TX_FRAG_ATTR_ADDR, /* u64 */ 279 ROCKER_TLV_TX_FRAG_ATTR_LEN, /* u16 */ 280 281 __ROCKER_TLV_TX_FRAG_ATTR_MAX, 282 ROCKER_TLV_TX_FRAG_ATTR_MAX = __ROCKER_TLV_TX_FRAG_ATTR_MAX - 1, 283 }; 284 285 /* cmd info nested for OF-DPA msgs */ 286 enum { 287 ROCKER_TLV_OF_DPA_UNSPEC, 288 ROCKER_TLV_OF_DPA_TABLE_ID, /* u16 */ 289 ROCKER_TLV_OF_DPA_PRIORITY, /* u32 */ 290 ROCKER_TLV_OF_DPA_HARDTIME, /* u32 */ 291 ROCKER_TLV_OF_DPA_IDLETIME, /* u32 */ 292 ROCKER_TLV_OF_DPA_COOKIE, /* u64 */ 293 ROCKER_TLV_OF_DPA_IN_PPORT, /* u32 */ 294 ROCKER_TLV_OF_DPA_IN_PPORT_MASK, /* u32 */ 295 ROCKER_TLV_OF_DPA_OUT_PPORT, /* u32 */ 296 ROCKER_TLV_OF_DPA_GOTO_TABLE_ID, /* u16 */ 297 ROCKER_TLV_OF_DPA_GROUP_ID, /* u32 */ 298 ROCKER_TLV_OF_DPA_GROUP_ID_LOWER, /* u32 */ 299 ROCKER_TLV_OF_DPA_GROUP_COUNT, /* u16 */ 300 ROCKER_TLV_OF_DPA_GROUP_IDS, /* u32 array */ 301 ROCKER_TLV_OF_DPA_VLAN_ID, /* __be16 */ 302 ROCKER_TLV_OF_DPA_VLAN_ID_MASK, /* __be16 */ 303 ROCKER_TLV_OF_DPA_VLAN_PCP, /* __be16 */ 304 ROCKER_TLV_OF_DPA_VLAN_PCP_MASK, /* __be16 */ 305 ROCKER_TLV_OF_DPA_VLAN_PCP_ACTION, /* u8 */ 306 ROCKER_TLV_OF_DPA_NEW_VLAN_ID, /* __be16 */ 307 ROCKER_TLV_OF_DPA_NEW_VLAN_PCP, /* u8 */ 308 ROCKER_TLV_OF_DPA_TUNNEL_ID, /* u32 */ 309 ROCKER_TLV_OF_DPA_TUNNEL_LPORT, /* u32 */ 310 ROCKER_TLV_OF_DPA_ETHERTYPE, /* __be16 */ 311 ROCKER_TLV_OF_DPA_DST_MAC, /* binary */ 312 ROCKER_TLV_OF_DPA_DST_MAC_MASK, /* binary */ 313 ROCKER_TLV_OF_DPA_SRC_MAC, /* binary */ 314 ROCKER_TLV_OF_DPA_SRC_MAC_MASK, /* binary */ 315 ROCKER_TLV_OF_DPA_IP_PROTO, /* u8 */ 316 ROCKER_TLV_OF_DPA_IP_PROTO_MASK, /* u8 */ 317 ROCKER_TLV_OF_DPA_IP_DSCP, /* u8 */ 318 ROCKER_TLV_OF_DPA_IP_DSCP_MASK, /* u8 */ 319 ROCKER_TLV_OF_DPA_IP_DSCP_ACTION, /* u8 */ 320 ROCKER_TLV_OF_DPA_NEW_IP_DSCP, /* u8 */ 321 ROCKER_TLV_OF_DPA_IP_ECN, /* u8 */ 322 ROCKER_TLV_OF_DPA_IP_ECN_MASK, /* u8 */ 323 ROCKER_TLV_OF_DPA_DST_IP, /* __be32 */ 324 ROCKER_TLV_OF_DPA_DST_IP_MASK, /* __be32 */ 325 ROCKER_TLV_OF_DPA_SRC_IP, /* __be32 */ 326 ROCKER_TLV_OF_DPA_SRC_IP_MASK, /* __be32 */ 327 ROCKER_TLV_OF_DPA_DST_IPV6, /* binary */ 328 ROCKER_TLV_OF_DPA_DST_IPV6_MASK, /* binary */ 329 ROCKER_TLV_OF_DPA_SRC_IPV6, /* binary */ 330 ROCKER_TLV_OF_DPA_SRC_IPV6_MASK, /* binary */ 331 ROCKER_TLV_OF_DPA_SRC_ARP_IP, /* __be32 */ 332 ROCKER_TLV_OF_DPA_SRC_ARP_IP_MASK, /* __be32 */ 333 ROCKER_TLV_OF_DPA_L4_DST_PORT, /* __be16 */ 334 ROCKER_TLV_OF_DPA_L4_DST_PORT_MASK, /* __be16 */ 335 ROCKER_TLV_OF_DPA_L4_SRC_PORT, /* __be16 */ 336 ROCKER_TLV_OF_DPA_L4_SRC_PORT_MASK, /* __be16 */ 337 ROCKER_TLV_OF_DPA_ICMP_TYPE, /* u8 */ 338 ROCKER_TLV_OF_DPA_ICMP_TYPE_MASK, /* u8 */ 339 ROCKER_TLV_OF_DPA_ICMP_CODE, /* u8 */ 340 ROCKER_TLV_OF_DPA_ICMP_CODE_MASK, /* u8 */ 341 ROCKER_TLV_OF_DPA_IPV6_LABEL, /* __be32 */ 342 ROCKER_TLV_OF_DPA_IPV6_LABEL_MASK, /* __be32 */ 343 ROCKER_TLV_OF_DPA_QUEUE_ID_ACTION, /* u8 */ 344 ROCKER_TLV_OF_DPA_NEW_QUEUE_ID, /* u8 */ 345 ROCKER_TLV_OF_DPA_CLEAR_ACTIONS, /* u32 */ 346 ROCKER_TLV_OF_DPA_POP_VLAN, /* u8 */ 347 ROCKER_TLV_OF_DPA_TTL_CHECK, /* u8 */ 348 ROCKER_TLV_OF_DPA_COPY_CPU_ACTION, /* u8 */ 349 350 __ROCKER_TLV_OF_DPA_MAX, 351 ROCKER_TLV_OF_DPA_MAX = __ROCKER_TLV_OF_DPA_MAX - 1, 352 }; 353 354 /* OF-DPA table IDs */ 355 356 enum rocker_of_dpa_table_id { 357 ROCKER_OF_DPA_TABLE_ID_INGRESS_PORT = 0, 358 ROCKER_OF_DPA_TABLE_ID_VLAN = 10, 359 ROCKER_OF_DPA_TABLE_ID_TERMINATION_MAC = 20, 360 ROCKER_OF_DPA_TABLE_ID_UNICAST_ROUTING = 30, 361 ROCKER_OF_DPA_TABLE_ID_MULTICAST_ROUTING = 40, 362 ROCKER_OF_DPA_TABLE_ID_BRIDGING = 50, 363 ROCKER_OF_DPA_TABLE_ID_ACL_POLICY = 60, 364 }; 365 366 /* OF-DPA flow stats */ 367 enum { 368 ROCKER_TLV_OF_DPA_FLOW_STAT_UNSPEC, 369 ROCKER_TLV_OF_DPA_FLOW_STAT_DURATION, /* u32 */ 370 ROCKER_TLV_OF_DPA_FLOW_STAT_RX_PKTS, /* u64 */ 371 ROCKER_TLV_OF_DPA_FLOW_STAT_TX_PKTS, /* u64 */ 372 373 __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX, 374 ROCKER_TLV_OF_DPA_FLOW_STAT_MAX = __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX - 1, 375 }; 376 377 /* OF-DPA group types */ 378 enum rocker_of_dpa_group_type { 379 ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE = 0, 380 ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE, 381 ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST, 382 ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST, 383 ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD, 384 ROCKER_OF_DPA_GROUP_TYPE_L3_INTERFACE, 385 ROCKER_OF_DPA_GROUP_TYPE_L3_MCAST, 386 ROCKER_OF_DPA_GROUP_TYPE_L3_ECMP, 387 ROCKER_OF_DPA_GROUP_TYPE_L2_OVERLAY, 388 }; 389 390 /* OF-DPA group L2 overlay types */ 391 enum rocker_of_dpa_overlay_type { 392 ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_UCAST = 0, 393 ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_MCAST, 394 ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_UCAST, 395 ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_MCAST, 396 }; 397 398 /* OF-DPA group ID encoding */ 399 #define ROCKER_GROUP_TYPE_SHIFT 28 400 #define ROCKER_GROUP_TYPE_MASK 0xf0000000 401 #define ROCKER_GROUP_VLAN_SHIFT 16 402 #define ROCKER_GROUP_VLAN_MASK 0x0fff0000 403 #define ROCKER_GROUP_PORT_SHIFT 0 404 #define ROCKER_GROUP_PORT_MASK 0x0000ffff 405 #define ROCKER_GROUP_TUNNEL_ID_SHIFT 12 406 #define ROCKER_GROUP_TUNNEL_ID_MASK 0x0ffff000 407 #define ROCKER_GROUP_SUBTYPE_SHIFT 10 408 #define ROCKER_GROUP_SUBTYPE_MASK 0x00000c00 409 #define ROCKER_GROUP_INDEX_SHIFT 0 410 #define ROCKER_GROUP_INDEX_MASK 0x0000ffff 411 #define ROCKER_GROUP_INDEX_LONG_SHIFT 0 412 #define ROCKER_GROUP_INDEX_LONG_MASK 0x0fffffff 413 414 #define ROCKER_GROUP_TYPE_GET(group_id) \ 415 (((group_id) & ROCKER_GROUP_TYPE_MASK) >> ROCKER_GROUP_TYPE_SHIFT) 416 #define ROCKER_GROUP_TYPE_SET(type) \ 417 (((type) << ROCKER_GROUP_TYPE_SHIFT) & ROCKER_GROUP_TYPE_MASK) 418 #define ROCKER_GROUP_VLAN_GET(group_id) \ 419 (((group_id) & ROCKER_GROUP_VLAN_ID_MASK) >> ROCKER_GROUP_VLAN_ID_SHIFT) 420 #define ROCKER_GROUP_VLAN_SET(vlan_id) \ 421 (((vlan_id) << ROCKER_GROUP_VLAN_SHIFT) & ROCKER_GROUP_VLAN_MASK) 422 #define ROCKER_GROUP_PORT_GET(group_id) \ 423 (((group_id) & ROCKER_GROUP_PORT_MASK) >> ROCKER_GROUP_PORT_SHIFT) 424 #define ROCKER_GROUP_PORT_SET(port) \ 425 (((port) << ROCKER_GROUP_PORT_SHIFT) & ROCKER_GROUP_PORT_MASK) 426 #define ROCKER_GROUP_INDEX_GET(group_id) \ 427 (((group_id) & ROCKER_GROUP_INDEX_MASK) >> ROCKER_GROUP_INDEX_SHIFT) 428 #define ROCKER_GROUP_INDEX_SET(index) \ 429 (((index) << ROCKER_GROUP_INDEX_SHIFT) & ROCKER_GROUP_INDEX_MASK) 430 #define ROCKER_GROUP_INDEX_LONG_GET(group_id) \ 431 (((group_id) & ROCKER_GROUP_INDEX_LONG_MASK) >> \ 432 ROCKER_GROUP_INDEX_LONG_SHIFT) 433 #define ROCKER_GROUP_INDEX_LONG_SET(index) \ 434 (((index) << ROCKER_GROUP_INDEX_LONG_SHIFT) & \ 435 ROCKER_GROUP_INDEX_LONG_MASK) 436 437 #define ROCKER_GROUP_NONE 0 438 #define ROCKER_GROUP_L2_INTERFACE(vlan_id, port) \ 439 (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE) |\ 440 ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_PORT_SET(port)) 441 #define ROCKER_GROUP_L2_REWRITE(index) \ 442 (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE) |\ 443 ROCKER_GROUP_INDEX_LONG_SET(index)) 444 #define ROCKER_GROUP_L2_MCAST(vlan_id, index) \ 445 (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST) |\ 446 ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index)) 447 #define ROCKER_GROUP_L2_FLOOD(vlan_id, index) \ 448 (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD) |\ 449 ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index)) 450 #define ROCKER_GROUP_L3_UNICAST(index) \ 451 (ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST) |\ 452 ROCKER_GROUP_INDEX_LONG_SET(index)) 453 454 /* Rocker general purpose registers */ 455 #define ROCKER_CONTROL 0x0300 456 #define ROCKER_PORT_PHYS_COUNT 0x0304 457 #define ROCKER_PORT_PHYS_LINK_STATUS 0x0310 /* 8-byte */ 458 #define ROCKER_PORT_PHYS_ENABLE 0x0318 /* 8-byte */ 459 #define ROCKER_SWITCH_ID 0x0320 /* 8-byte */ 460 461 /* Rocker control bits */ 462 #define ROCKER_CONTROL_RESET (1 << 0) 463 464 #endif 465