1 /* 2 * SuperH Ethernet device driver 3 * 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2012 Renesas Solutions Corp. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * The full GNU General Public License is included in this distribution in 20 * the file called "COPYING". 21 */ 22 23 #ifndef __SH_ETH_H__ 24 #define __SH_ETH_H__ 25 26 #define CARDNAME "sh-eth" 27 #define TX_TIMEOUT (5*HZ) 28 #define TX_RING_SIZE 64 /* Tx ring size */ 29 #define RX_RING_SIZE 64 /* Rx ring size */ 30 #define TX_RING_MIN 64 31 #define RX_RING_MIN 64 32 #define TX_RING_MAX 1024 33 #define RX_RING_MAX 1024 34 #define ETHERSMALL 60 35 #define PKT_BUF_SZ 1538 36 #define SH_ETH_TSU_TIMEOUT_MS 500 37 #define SH_ETH_TSU_CAM_ENTRIES 32 38 39 enum { 40 /* E-DMAC registers */ 41 EDSR = 0, 42 EDMR, 43 EDTRR, 44 EDRRR, 45 EESR, 46 EESIPR, 47 TDLAR, 48 TDFAR, 49 TDFXR, 50 TDFFR, 51 RDLAR, 52 RDFAR, 53 RDFXR, 54 RDFFR, 55 TRSCER, 56 RMFCR, 57 TFTR, 58 FDR, 59 RMCR, 60 EDOCR, 61 TFUCR, 62 RFOCR, 63 FCFTR, 64 RPADIR, 65 TRIMD, 66 RBWAR, 67 TBRAR, 68 69 /* Ether registers */ 70 ECMR, 71 ECSR, 72 ECSIPR, 73 PIR, 74 PSR, 75 RDMLR, 76 PIPR, 77 RFLR, 78 IPGR, 79 APR, 80 MPR, 81 PFTCR, 82 PFRCR, 83 RFCR, 84 RFCF, 85 TPAUSER, 86 TPAUSECR, 87 BCFR, 88 BCFRR, 89 GECMR, 90 BCULR, 91 MAHR, 92 MALR, 93 TROCR, 94 CDCR, 95 LCCR, 96 CNDCR, 97 CEFCR, 98 FRECR, 99 TSFRCR, 100 TLFRCR, 101 CERCR, 102 CEECR, 103 MAFCR, 104 RTRATE, 105 CSMR, 106 RMII_MII, 107 108 /* TSU Absolute address */ 109 ARSTR, 110 TSU_CTRST, 111 TSU_FWEN0, 112 TSU_FWEN1, 113 TSU_FCM, 114 TSU_BSYSL0, 115 TSU_BSYSL1, 116 TSU_PRISL0, 117 TSU_PRISL1, 118 TSU_FWSL0, 119 TSU_FWSL1, 120 TSU_FWSLC, 121 TSU_QTAG0, 122 TSU_QTAG1, 123 TSU_QTAGM0, 124 TSU_QTAGM1, 125 TSU_FWSR, 126 TSU_FWINMK, 127 TSU_ADQT0, 128 TSU_ADQT1, 129 TSU_VTAG0, 130 TSU_VTAG1, 131 TSU_ADSBSY, 132 TSU_TEN, 133 TSU_POST1, 134 TSU_POST2, 135 TSU_POST3, 136 TSU_POST4, 137 TSU_ADRH0, 138 TSU_ADRL0, 139 TSU_ADRH31, 140 TSU_ADRL31, 141 142 TXNLCR0, 143 TXALCR0, 144 RXNLCR0, 145 RXALCR0, 146 FWNLCR0, 147 FWALCR0, 148 TXNLCR1, 149 TXALCR1, 150 RXNLCR1, 151 RXALCR1, 152 FWNLCR1, 153 FWALCR1, 154 155 /* This value must be written at last. */ 156 SH_ETH_MAX_REGISTER_OFFSET, 157 }; 158 159 /* Driver's parameters */ 160 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 161 #define SH4_SKB_RX_ALIGN 32 162 #else 163 #define SH2_SH3_SKB_RX_ALIGN 2 164 #endif 165 166 /* 167 * Register's bits 168 */ 169 #if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ||\ 170 defined(CONFIG_ARCH_R8A7740) 171 /* EDSR */ 172 enum EDSR_BIT { 173 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 174 }; 175 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 176 177 /* GECMR */ 178 enum GECMR_BIT { 179 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01, 180 }; 181 #endif 182 183 /* EDMR */ 184 enum DMAC_M_BIT { 185 EDMR_EL = 0x40, /* Litte endian */ 186 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 187 EDMR_SRST_GETHER = 0x03, 188 EDMR_SRST_ETHER = 0x01, 189 }; 190 191 /* EDTRR */ 192 enum DMAC_T_BIT { 193 EDTRR_TRNS_GETHER = 0x03, 194 EDTRR_TRNS_ETHER = 0x01, 195 }; 196 197 /* EDRRR*/ 198 enum EDRRR_R_BIT { 199 EDRRR_R = 0x01, 200 }; 201 202 /* TPAUSER */ 203 enum TPAUSER_BIT { 204 TPAUSER_TPAUSE = 0x0000ffff, 205 TPAUSER_UNLIMITED = 0, 206 }; 207 208 /* BCFR */ 209 enum BCFR_BIT { 210 BCFR_RPAUSE = 0x0000ffff, 211 BCFR_UNLIMITED = 0, 212 }; 213 214 /* PIR */ 215 enum PIR_BIT { 216 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 217 }; 218 219 /* PSR */ 220 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 221 222 /* EESR */ 223 enum EESR_BIT { 224 EESR_TWB1 = 0x80000000, 225 EESR_TWB = 0x40000000, /* same as TWB0 */ 226 EESR_TC1 = 0x20000000, 227 EESR_TUC = 0x10000000, 228 EESR_ROC = 0x08000000, 229 EESR_TABT = 0x04000000, 230 EESR_RABT = 0x02000000, 231 EESR_RFRMER = 0x01000000, /* same as RFCOF */ 232 EESR_ADE = 0x00800000, 233 EESR_ECI = 0x00400000, 234 EESR_FTC = 0x00200000, /* same as TC or TC0 */ 235 EESR_TDE = 0x00100000, 236 EESR_TFE = 0x00080000, /* same as TFUF */ 237 EESR_FRC = 0x00040000, /* same as FR */ 238 EESR_RDE = 0x00020000, 239 EESR_RFE = 0x00010000, 240 EESR_CND = 0x00000800, 241 EESR_DLC = 0x00000400, 242 EESR_CD = 0x00000200, 243 EESR_RTO = 0x00000100, 244 EESR_RMAF = 0x00000080, 245 EESR_CEEF = 0x00000040, 246 EESR_CELF = 0x00000020, 247 EESR_RRF = 0x00000010, 248 EESR_RTLF = 0x00000008, 249 EESR_RTSF = 0x00000004, 250 EESR_PRE = 0x00000002, 251 EESR_CERF = 0x00000001, 252 }; 253 254 #define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \ 255 EESR_RTO) 256 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \ 257 EESR_RDE | EESR_RFRMER | EESR_ADE | \ 258 EESR_TFE | EESR_TDE | EESR_ECI) 259 #define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \ 260 EESR_TFE) 261 262 /* EESIPR */ 263 enum DMAC_IM_BIT { 264 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 265 DMAC_M_RABT = 0x02000000, 266 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 267 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 268 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 269 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 270 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 271 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 272 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 273 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 274 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 275 DMAC_M_RINT1 = 0x00000001, 276 }; 277 278 /* Receive descriptor bit */ 279 enum RD_STS_BIT { 280 RD_RACT = 0x80000000, RD_RDEL = 0x40000000, 281 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 282 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 283 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 284 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 285 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 286 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 287 RD_RFS1 = 0x00000001, 288 }; 289 #define RDF1ST RD_RFP1 290 #define RDFEND RD_RFP0 291 #define RD_RFP (RD_RFP1|RD_RFP0) 292 293 /* FCFTR */ 294 enum FCFTR_BIT { 295 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 296 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 297 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 298 }; 299 #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0) 300 #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0) 301 302 /* Transfer descriptor bit */ 303 enum TD_STS_BIT { 304 TD_TACT = 0x80000000, 305 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 306 TD_TFP0 = 0x10000000, 307 }; 308 #define TDF1ST TD_TFP1 309 #define TDFEND TD_TFP0 310 #define TD_TFP (TD_TFP1|TD_TFP0) 311 312 /* RMCR */ 313 #define DEFAULT_RMCR_VALUE 0x00000000 314 315 /* ECMR */ 316 enum FELIC_MODE_BIT { 317 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, 318 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, 319 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 320 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 321 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 322 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, 323 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001, 324 }; 325 326 /* ECSR */ 327 enum ECSR_STATUS_BIT { 328 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 329 ECSR_LCHNG = 0x04, 330 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 331 }; 332 333 #define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \ 334 ECSR_ICD | ECSIPR_MPDIP) 335 336 /* ECSIPR */ 337 enum ECSIPR_STATUS_MASK_BIT { 338 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, 339 ECSIPR_LCHNGIP = 0x04, 340 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, 341 }; 342 343 #define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \ 344 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 345 346 /* APR */ 347 enum APR_BIT { 348 APR_AP = 0x00000001, 349 }; 350 351 /* MPR */ 352 enum MPR_BIT { 353 MPR_MP = 0x00000001, 354 }; 355 356 /* TRSCER */ 357 enum DESC_I_BIT { 358 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 359 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 360 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 361 DESC_I_RINT1 = 0x0001, 362 }; 363 364 /* RPADIR */ 365 enum RPADIR_BIT { 366 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 367 RPADIR_PADR = 0x0003f, 368 }; 369 370 /* FDR */ 371 #define DEFAULT_FDR_INIT 0x00000707 372 373 /* ARSTR */ 374 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, }; 375 376 /* TSU_FWEN0 */ 377 enum TSU_FWEN0_BIT { 378 TSU_FWEN0_0 = 0x00000001, 379 }; 380 381 /* TSU_ADSBSY */ 382 enum TSU_ADSBSY_BIT { 383 TSU_ADSBSY_0 = 0x00000001, 384 }; 385 386 /* TSU_TEN */ 387 enum TSU_TEN_BIT { 388 TSU_TEN_0 = 0x80000000, 389 }; 390 391 /* TSU_FWSL0 */ 392 enum TSU_FWSL0_BIT { 393 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800, 394 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200, 395 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010, 396 }; 397 398 /* TSU_FWSLC */ 399 enum TSU_FWSLC_BIT { 400 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000, 401 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040, 402 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010, 403 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004, 404 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001, 405 }; 406 407 /* TSU_VTAGn */ 408 #define TSU_VTAG_ENABLE 0x80000000 409 #define TSU_VTAG_VID_MASK 0x00000fff 410 411 /* 412 * The sh ether Tx buffer descriptors. 413 * This structure should be 20 bytes. 414 */ 415 struct sh_eth_txdesc { 416 u32 status; /* TD0 */ 417 #if defined(__LITTLE_ENDIAN) 418 u16 pad0; /* TD1 */ 419 u16 buffer_length; /* TD1 */ 420 #else 421 u16 buffer_length; /* TD1 */ 422 u16 pad0; /* TD1 */ 423 #endif 424 u32 addr; /* TD2 */ 425 u32 pad1; /* padding data */ 426 } __attribute__((aligned(2), packed)); 427 428 /* 429 * The sh ether Rx buffer descriptors. 430 * This structure should be 20 bytes. 431 */ 432 struct sh_eth_rxdesc { 433 u32 status; /* RD0 */ 434 #if defined(__LITTLE_ENDIAN) 435 u16 frame_length; /* RD1 */ 436 u16 buffer_length; /* RD1 */ 437 #else 438 u16 buffer_length; /* RD1 */ 439 u16 frame_length; /* RD1 */ 440 #endif 441 u32 addr; /* RD2 */ 442 u32 pad0; /* padding data */ 443 } __attribute__((aligned(2), packed)); 444 445 /* This structure is used by each CPU dependency handling. */ 446 struct sh_eth_cpu_data { 447 /* optional functions */ 448 void (*chip_reset)(struct net_device *ndev); 449 void (*set_duplex)(struct net_device *ndev); 450 void (*set_rate)(struct net_device *ndev); 451 452 /* mandatory initialize value */ 453 unsigned long eesipr_value; 454 455 /* optional initialize value */ 456 unsigned long ecsr_value; 457 unsigned long ecsipr_value; 458 unsigned long fdr_value; 459 unsigned long fcftr_value; 460 unsigned long rpadir_value; 461 unsigned long rmcr_value; 462 463 /* interrupt checking mask */ 464 unsigned long tx_check; 465 unsigned long eesr_err_check; 466 unsigned long tx_error_check; 467 468 /* hardware features */ 469 unsigned no_psr:1; /* EtherC DO NOT have PSR */ 470 unsigned apr:1; /* EtherC have APR */ 471 unsigned mpr:1; /* EtherC have MPR */ 472 unsigned tpauser:1; /* EtherC have TPAUSER */ 473 unsigned bculr:1; /* EtherC have BCULR */ 474 unsigned tsu:1; /* EtherC have TSU */ 475 unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */ 476 unsigned rpadir:1; /* E-DMAC have RPADIR */ 477 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */ 478 unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */ 479 unsigned hw_crc:1; /* E-DMAC have CSMR */ 480 unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */ 481 }; 482 483 struct sh_eth_private { 484 struct platform_device *pdev; 485 struct sh_eth_cpu_data *cd; 486 const u16 *reg_offset; 487 void __iomem *addr; 488 void __iomem *tsu_addr; 489 u32 num_rx_ring; 490 u32 num_tx_ring; 491 dma_addr_t rx_desc_dma; 492 dma_addr_t tx_desc_dma; 493 struct sh_eth_rxdesc *rx_ring; 494 struct sh_eth_txdesc *tx_ring; 495 struct sk_buff **rx_skbuff; 496 struct sk_buff **tx_skbuff; 497 spinlock_t lock; 498 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */ 499 u32 cur_tx, dirty_tx; 500 u32 rx_buf_sz; /* Based on MTU+slack. */ 501 int edmac_endian; 502 /* MII transceiver section. */ 503 u32 phy_id; /* PHY ID */ 504 struct mii_bus *mii_bus; /* MDIO bus control */ 505 struct phy_device *phydev; /* PHY device control */ 506 int link; 507 phy_interface_t phy_interface; 508 int msg_enable; 509 int speed; 510 int duplex; 511 int port; /* for TSU */ 512 int vlan_num_ids; /* for VLAN tag filter */ 513 514 unsigned no_ether_link:1; 515 unsigned ether_link_active_low:1; 516 }; 517 518 static inline void sh_eth_soft_swap(char *src, int len) 519 { 520 #ifdef __LITTLE_ENDIAN__ 521 u32 *p = (u32 *)src; 522 u32 *maxp; 523 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32)); 524 525 for (; p < maxp; p++) 526 *p = swab32(*p); 527 #endif 528 } 529 530 static inline void sh_eth_write(struct net_device *ndev, unsigned long data, 531 int enum_index) 532 { 533 struct sh_eth_private *mdp = netdev_priv(ndev); 534 535 iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]); 536 } 537 538 static inline unsigned long sh_eth_read(struct net_device *ndev, 539 int enum_index) 540 { 541 struct sh_eth_private *mdp = netdev_priv(ndev); 542 543 return ioread32(mdp->addr + mdp->reg_offset[enum_index]); 544 } 545 546 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp, 547 int enum_index) 548 { 549 return mdp->tsu_addr + mdp->reg_offset[enum_index]; 550 } 551 552 static inline void sh_eth_tsu_write(struct sh_eth_private *mdp, 553 unsigned long data, int enum_index) 554 { 555 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]); 556 } 557 558 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp, 559 int enum_index) 560 { 561 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]); 562 } 563 564 #endif /* #ifndef __SH_ETH_H__ */ 565