1 /*
2  *  SuperH Ethernet device driver
3  *
4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5  *  Copyright (C) 2008-2012 Renesas Solutions Corp.
6  *
7  *  This program is free software; you can redistribute it and/or modify it
8  *  under the terms and conditions of the GNU General Public License,
9  *  version 2, as published by the Free Software Foundation.
10  *
11  *  This program is distributed in the hope it will be useful, but WITHOUT
12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  *  more details.
15  *  You should have received a copy of the GNU General Public License along with
16  *  this program; if not, write to the Free Software Foundation, Inc.,
17  *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18  *
19  *  The full GNU General Public License is included in this distribution in
20  *  the file called "COPYING".
21  */
22 
23 #ifndef __SH_ETH_H__
24 #define __SH_ETH_H__
25 
26 #define CARDNAME	"sh-eth"
27 #define TX_TIMEOUT	(5*HZ)
28 #define TX_RING_SIZE	64	/* Tx ring size */
29 #define RX_RING_SIZE	64	/* Rx ring size */
30 #define TX_RING_MIN	64
31 #define RX_RING_MIN	64
32 #define TX_RING_MAX	1024
33 #define RX_RING_MAX	1024
34 #define ETHERSMALL		60
35 #define PKT_BUF_SZ		1538
36 #define SH_ETH_TSU_TIMEOUT_MS	500
37 #define SH_ETH_TSU_CAM_ENTRIES	32
38 
39 enum {
40 	/* E-DMAC registers */
41 	EDSR = 0,
42 	EDMR,
43 	EDTRR,
44 	EDRRR,
45 	EESR,
46 	EESIPR,
47 	TDLAR,
48 	TDFAR,
49 	TDFXR,
50 	TDFFR,
51 	RDLAR,
52 	RDFAR,
53 	RDFXR,
54 	RDFFR,
55 	TRSCER,
56 	RMFCR,
57 	TFTR,
58 	FDR,
59 	RMCR,
60 	EDOCR,
61 	TFUCR,
62 	RFOCR,
63 	RMIIMODE,
64 	FCFTR,
65 	RPADIR,
66 	TRIMD,
67 	RBWAR,
68 	TBRAR,
69 
70 	/* Ether registers */
71 	ECMR,
72 	ECSR,
73 	ECSIPR,
74 	PIR,
75 	PSR,
76 	RDMLR,
77 	PIPR,
78 	RFLR,
79 	IPGR,
80 	APR,
81 	MPR,
82 	PFTCR,
83 	PFRCR,
84 	RFCR,
85 	RFCF,
86 	TPAUSER,
87 	TPAUSECR,
88 	BCFR,
89 	BCFRR,
90 	GECMR,
91 	BCULR,
92 	MAHR,
93 	MALR,
94 	TROCR,
95 	CDCR,
96 	LCCR,
97 	CNDCR,
98 	CEFCR,
99 	FRECR,
100 	TSFRCR,
101 	TLFRCR,
102 	CERCR,
103 	CEECR,
104 	MAFCR,
105 	RTRATE,
106 	CSMR,
107 	RMII_MII,
108 
109 	/* TSU Absolute address */
110 	ARSTR,
111 	TSU_CTRST,
112 	TSU_FWEN0,
113 	TSU_FWEN1,
114 	TSU_FCM,
115 	TSU_BSYSL0,
116 	TSU_BSYSL1,
117 	TSU_PRISL0,
118 	TSU_PRISL1,
119 	TSU_FWSL0,
120 	TSU_FWSL1,
121 	TSU_FWSLC,
122 	TSU_QTAG0,
123 	TSU_QTAG1,
124 	TSU_QTAGM0,
125 	TSU_QTAGM1,
126 	TSU_FWSR,
127 	TSU_FWINMK,
128 	TSU_ADQT0,
129 	TSU_ADQT1,
130 	TSU_VTAG0,
131 	TSU_VTAG1,
132 	TSU_ADSBSY,
133 	TSU_TEN,
134 	TSU_POST1,
135 	TSU_POST2,
136 	TSU_POST3,
137 	TSU_POST4,
138 	TSU_ADRH0,
139 	TSU_ADRL0,
140 	TSU_ADRH31,
141 	TSU_ADRL31,
142 
143 	TXNLCR0,
144 	TXALCR0,
145 	RXNLCR0,
146 	RXALCR0,
147 	FWNLCR0,
148 	FWALCR0,
149 	TXNLCR1,
150 	TXALCR1,
151 	RXNLCR1,
152 	RXALCR1,
153 	FWNLCR1,
154 	FWALCR1,
155 
156 	/* This value must be written at last. */
157 	SH_ETH_MAX_REGISTER_OFFSET,
158 };
159 
160 enum {
161 	SH_ETH_REG_GIGABIT,
162 	SH_ETH_REG_FAST_RCAR,
163 	SH_ETH_REG_FAST_SH4,
164 	SH_ETH_REG_FAST_SH3_SH2
165 };
166 
167 /* Driver's parameters */
168 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
169 #define SH4_SKB_RX_ALIGN	32
170 #else
171 #define SH2_SH3_SKB_RX_ALIGN	2
172 #endif
173 
174 /*
175  * Register's bits
176  */
177 /* EDSR : sh7734, sh7757, sh7763, and r8a7740 only */
178 enum EDSR_BIT {
179 	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
180 };
181 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
182 
183 /* GECMR : sh7734, sh7763 and r8a7740 only */
184 enum GECMR_BIT {
185 	GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
186 };
187 
188 /* EDMR */
189 enum DMAC_M_BIT {
190 	EDMR_EL = 0x40, /* Litte endian */
191 	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
192 	EDMR_SRST_GETHER = 0x03,
193 	EDMR_SRST_ETHER = 0x01,
194 };
195 
196 /* EDTRR */
197 enum DMAC_T_BIT {
198 	EDTRR_TRNS_GETHER = 0x03,
199 	EDTRR_TRNS_ETHER = 0x01,
200 };
201 
202 /* EDRRR*/
203 enum EDRRR_R_BIT {
204 	EDRRR_R = 0x01,
205 };
206 
207 /* TPAUSER */
208 enum TPAUSER_BIT {
209 	TPAUSER_TPAUSE = 0x0000ffff,
210 	TPAUSER_UNLIMITED = 0,
211 };
212 
213 /* BCFR */
214 enum BCFR_BIT {
215 	BCFR_RPAUSE = 0x0000ffff,
216 	BCFR_UNLIMITED = 0,
217 };
218 
219 /* PIR */
220 enum PIR_BIT {
221 	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
222 };
223 
224 /* PSR */
225 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
226 
227 /* EESR */
228 enum EESR_BIT {
229 	EESR_TWB1	= 0x80000000,
230 	EESR_TWB	= 0x40000000,	/* same as TWB0 */
231 	EESR_TC1	= 0x20000000,
232 	EESR_TUC	= 0x10000000,
233 	EESR_ROC	= 0x08000000,
234 	EESR_TABT	= 0x04000000,
235 	EESR_RABT	= 0x02000000,
236 	EESR_RFRMER	= 0x01000000,	/* same as RFCOF */
237 	EESR_ADE	= 0x00800000,
238 	EESR_ECI	= 0x00400000,
239 	EESR_FTC	= 0x00200000,	/* same as TC or TC0 */
240 	EESR_TDE	= 0x00100000,
241 	EESR_TFE	= 0x00080000,	/* same as TFUF */
242 	EESR_FRC	= 0x00040000,	/* same as FR */
243 	EESR_RDE	= 0x00020000,
244 	EESR_RFE	= 0x00010000,
245 	EESR_CND	= 0x00000800,
246 	EESR_DLC	= 0x00000400,
247 	EESR_CD		= 0x00000200,
248 	EESR_RTO	= 0x00000100,
249 	EESR_RMAF	= 0x00000080,
250 	EESR_CEEF	= 0x00000040,
251 	EESR_CELF	= 0x00000020,
252 	EESR_RRF	= 0x00000010,
253 	EESR_RTLF	= 0x00000008,
254 	EESR_RTSF	= 0x00000004,
255 	EESR_PRE	= 0x00000002,
256 	EESR_CERF	= 0x00000001,
257 };
258 
259 #define EESR_RX_CHECK		(EESR_FRC  | /* Frame recv */		\
260 				 EESR_RMAF | /* Multicast address recv */ \
261 				 EESR_RRF  | /* Bit frame recv */	\
262 				 EESR_RTLF | /* Long frame recv */	\
263 				 EESR_RTSF | /* Short frame recv */	\
264 				 EESR_PRE  | /* PHY-LSI recv error */	\
265 				 EESR_CERF)  /* Recv frame CRC error */
266 
267 #define DEFAULT_TX_CHECK	(EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
268 				 EESR_RTO)
269 #define DEFAULT_EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
270 				 EESR_RDE | EESR_RFRMER | EESR_ADE | \
271 				 EESR_TFE | EESR_TDE | EESR_ECI)
272 
273 /* EESIPR */
274 enum DMAC_IM_BIT {
275 	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
276 	DMAC_M_RABT = 0x02000000,
277 	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
278 	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
279 	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
280 	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
281 	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
282 	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
283 	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
284 	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
285 	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
286 	DMAC_M_RINT1 = 0x00000001,
287 };
288 
289 /* Receive descriptor bit */
290 enum RD_STS_BIT {
291 	RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
292 	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
293 	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
294 	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
295 	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
296 	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
297 	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
298 	RD_RFS1 = 0x00000001,
299 };
300 #define RDF1ST	RD_RFP1
301 #define RDFEND	RD_RFP0
302 #define RD_RFP	(RD_RFP1|RD_RFP0)
303 
304 /* FCFTR */
305 enum FCFTR_BIT {
306 	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
307 	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
308 	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
309 };
310 #define DEFAULT_FIFO_F_D_RFF	(FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
311 #define DEFAULT_FIFO_F_D_RFD	(FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
312 
313 /* Transmit descriptor bit */
314 enum TD_STS_BIT {
315 	TD_TACT = 0x80000000, TD_TDLE = 0x40000000,
316 	TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000,
317 	TD_TFE  = 0x08000000, TD_TWBI = 0x04000000,
318 };
319 #define TDF1ST	TD_TFP1
320 #define TDFEND	TD_TFP0
321 #define TD_TFP	(TD_TFP1|TD_TFP0)
322 
323 /* RMCR */
324 #define DEFAULT_RMCR_VALUE	0x00000000
325 
326 /* ECMR */
327 enum FELIC_MODE_BIT {
328 	ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
329 	ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
330 	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
331 	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
332 	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
333 	ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
334 	ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
335 };
336 
337 /* ECSR */
338 enum ECSR_STATUS_BIT {
339 	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
340 	ECSR_LCHNG = 0x04,
341 	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
342 };
343 
344 #define DEFAULT_ECSR_INIT	(ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
345 				 ECSR_ICD | ECSIPR_MPDIP)
346 
347 /* ECSIPR */
348 enum ECSIPR_STATUS_MASK_BIT {
349 	ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
350 	ECSIPR_LCHNGIP = 0x04,
351 	ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
352 };
353 
354 #define DEFAULT_ECSIPR_INIT	(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
355 				 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
356 
357 /* APR */
358 enum APR_BIT {
359 	APR_AP = 0x00000001,
360 };
361 
362 /* MPR */
363 enum MPR_BIT {
364 	MPR_MP = 0x00000001,
365 };
366 
367 /* TRSCER */
368 enum DESC_I_BIT {
369 	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
370 	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
371 	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
372 	DESC_I_RINT1 = 0x0001,
373 };
374 
375 /* RPADIR */
376 enum RPADIR_BIT {
377 	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
378 	RPADIR_PADR = 0x0003f,
379 };
380 
381 /* FDR */
382 #define DEFAULT_FDR_INIT	0x00000707
383 
384 /* ARSTR */
385 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
386 
387 /* TSU_FWEN0 */
388 enum TSU_FWEN0_BIT {
389 	TSU_FWEN0_0 = 0x00000001,
390 };
391 
392 /* TSU_ADSBSY */
393 enum TSU_ADSBSY_BIT {
394 	TSU_ADSBSY_0 = 0x00000001,
395 };
396 
397 /* TSU_TEN */
398 enum TSU_TEN_BIT {
399 	TSU_TEN_0 = 0x80000000,
400 };
401 
402 /* TSU_FWSL0 */
403 enum TSU_FWSL0_BIT {
404 	TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
405 	TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
406 	TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
407 };
408 
409 /* TSU_FWSLC */
410 enum TSU_FWSLC_BIT {
411 	TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
412 	TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
413 	TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
414 	TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
415 	TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
416 };
417 
418 /* TSU_VTAGn */
419 #define TSU_VTAG_ENABLE		0x80000000
420 #define TSU_VTAG_VID_MASK	0x00000fff
421 
422 /*
423  * The sh ether Tx buffer descriptors.
424  * This structure should be 20 bytes.
425  */
426 struct sh_eth_txdesc {
427 	u32 status;		/* TD0 */
428 #if defined(__LITTLE_ENDIAN)
429 	u16 pad0;		/* TD1 */
430 	u16 buffer_length;	/* TD1 */
431 #else
432 	u16 buffer_length;	/* TD1 */
433 	u16 pad0;		/* TD1 */
434 #endif
435 	u32 addr;		/* TD2 */
436 	u32 pad1;		/* padding data */
437 } __attribute__((aligned(2), packed));
438 
439 /*
440  * The sh ether Rx buffer descriptors.
441  * This structure should be 20 bytes.
442  */
443 struct sh_eth_rxdesc {
444 	u32 status;		/* RD0 */
445 #if defined(__LITTLE_ENDIAN)
446 	u16 frame_length;	/* RD1 */
447 	u16 buffer_length;	/* RD1 */
448 #else
449 	u16 buffer_length;	/* RD1 */
450 	u16 frame_length;	/* RD1 */
451 #endif
452 	u32 addr;		/* RD2 */
453 	u32 pad0;		/* padding data */
454 } __attribute__((aligned(2), packed));
455 
456 /* This structure is used by each CPU dependency handling. */
457 struct sh_eth_cpu_data {
458 	/* optional functions */
459 	void (*chip_reset)(struct net_device *ndev);
460 	void (*set_duplex)(struct net_device *ndev);
461 	void (*set_rate)(struct net_device *ndev);
462 
463 	/* mandatory initialize value */
464 	int register_type;
465 	unsigned long eesipr_value;
466 
467 	/* optional initialize value */
468 	unsigned long ecsr_value;
469 	unsigned long ecsipr_value;
470 	unsigned long fdr_value;
471 	unsigned long fcftr_value;
472 	unsigned long rpadir_value;
473 	unsigned long rmcr_value;
474 
475 	/* interrupt checking mask */
476 	unsigned long tx_check;
477 	unsigned long eesr_err_check;
478 
479 	/* hardware features */
480 	unsigned long irq_flags;	/* IRQ configuration flags */
481 	unsigned no_psr:1;		/* EtherC DO NOT have PSR */
482 	unsigned apr:1;			/* EtherC have APR */
483 	unsigned mpr:1;			/* EtherC have MPR */
484 	unsigned tpauser:1;		/* EtherC have TPAUSER */
485 	unsigned bculr:1;		/* EtherC have BCULR */
486 	unsigned tsu:1;			/* EtherC have TSU */
487 	unsigned hw_swap:1;		/* E-DMAC have DE bit in EDMR */
488 	unsigned rpadir:1;		/* E-DMAC have RPADIR */
489 	unsigned no_trimd:1;		/* E-DMAC DO NOT have TRIMD */
490 	unsigned no_ade:1;	/* E-DMAC DO NOT have ADE bit in EESR */
491 	unsigned hw_crc:1;	/* E-DMAC have CSMR */
492 	unsigned select_mii:1;	/* EtherC have RMII_MII (MII select register) */
493 	unsigned shift_rd0:1;	/* shift Rx descriptor word 0 right by 16 */
494 	unsigned rmiimode:1;	/* EtherC has RMIIMODE register */
495 };
496 
497 struct sh_eth_private {
498 	struct platform_device *pdev;
499 	struct sh_eth_cpu_data *cd;
500 	const u16 *reg_offset;
501 	void __iomem *addr;
502 	void __iomem *tsu_addr;
503 	u32 num_rx_ring;
504 	u32 num_tx_ring;
505 	dma_addr_t rx_desc_dma;
506 	dma_addr_t tx_desc_dma;
507 	struct sh_eth_rxdesc *rx_ring;
508 	struct sh_eth_txdesc *tx_ring;
509 	struct sk_buff **rx_skbuff;
510 	struct sk_buff **tx_skbuff;
511 	spinlock_t lock;
512 	u32 cur_rx, dirty_rx;	/* Producer/consumer ring indices */
513 	u32 cur_tx, dirty_tx;
514 	u32 rx_buf_sz;		/* Based on MTU+slack. */
515 	int edmac_endian;
516 	struct napi_struct napi;
517 	/* MII transceiver section. */
518 	u32 phy_id;					/* PHY ID */
519 	struct mii_bus *mii_bus;	/* MDIO bus control */
520 	struct phy_device *phydev;	/* PHY device control */
521 	int link;
522 	phy_interface_t phy_interface;
523 	int msg_enable;
524 	int speed;
525 	int duplex;
526 	int port;		/* for TSU */
527 	int vlan_num_ids;	/* for VLAN tag filter */
528 
529 	unsigned no_ether_link:1;
530 	unsigned ether_link_active_low:1;
531 };
532 
533 static inline void sh_eth_soft_swap(char *src, int len)
534 {
535 #ifdef __LITTLE_ENDIAN__
536 	u32 *p = (u32 *)src;
537 	u32 *maxp;
538 	maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
539 
540 	for (; p < maxp; p++)
541 		*p = swab32(*p);
542 #endif
543 }
544 
545 static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
546 				int enum_index)
547 {
548 	struct sh_eth_private *mdp = netdev_priv(ndev);
549 
550 	iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
551 }
552 
553 static inline unsigned long sh_eth_read(struct net_device *ndev,
554 					int enum_index)
555 {
556 	struct sh_eth_private *mdp = netdev_priv(ndev);
557 
558 	return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
559 }
560 
561 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
562 					  int enum_index)
563 {
564 	return mdp->tsu_addr + mdp->reg_offset[enum_index];
565 }
566 
567 static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
568 				unsigned long data, int enum_index)
569 {
570 	iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
571 }
572 
573 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
574 					int enum_index)
575 {
576 	return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
577 }
578 
579 #endif	/* #ifndef __SH_ETH_H__ */
580