1 /* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 4 * Copyright (C) 2008-2012 Renesas Solutions Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in 16 * the file called "COPYING". 17 */ 18 19 #ifndef __SH_ETH_H__ 20 #define __SH_ETH_H__ 21 22 #define CARDNAME "sh-eth" 23 #define TX_TIMEOUT (5*HZ) 24 #define TX_RING_SIZE 64 /* Tx ring size */ 25 #define RX_RING_SIZE 64 /* Rx ring size */ 26 #define TX_RING_MIN 64 27 #define RX_RING_MIN 64 28 #define TX_RING_MAX 1024 29 #define RX_RING_MAX 1024 30 #define PKT_BUF_SZ 1538 31 #define SH_ETH_TSU_TIMEOUT_MS 500 32 #define SH_ETH_TSU_CAM_ENTRIES 32 33 34 enum { 35 /* E-DMAC registers */ 36 EDSR = 0, 37 EDMR, 38 EDTRR, 39 EDRRR, 40 EESR, 41 EESIPR, 42 TDLAR, 43 TDFAR, 44 TDFXR, 45 TDFFR, 46 RDLAR, 47 RDFAR, 48 RDFXR, 49 RDFFR, 50 TRSCER, 51 RMFCR, 52 TFTR, 53 FDR, 54 RMCR, 55 EDOCR, 56 TFUCR, 57 RFOCR, 58 RMIIMODE, 59 FCFTR, 60 RPADIR, 61 TRIMD, 62 RBWAR, 63 TBRAR, 64 65 /* Ether registers */ 66 ECMR, 67 ECSR, 68 ECSIPR, 69 PIR, 70 PSR, 71 RDMLR, 72 PIPR, 73 RFLR, 74 IPGR, 75 APR, 76 MPR, 77 PFTCR, 78 PFRCR, 79 RFCR, 80 RFCF, 81 TPAUSER, 82 TPAUSECR, 83 BCFR, 84 BCFRR, 85 GECMR, 86 BCULR, 87 MAHR, 88 MALR, 89 TROCR, 90 CDCR, 91 LCCR, 92 CNDCR, 93 CEFCR, 94 FRECR, 95 TSFRCR, 96 TLFRCR, 97 CERCR, 98 CEECR, 99 MAFCR, 100 RTRATE, 101 CSMR, 102 RMII_MII, 103 104 /* TSU Absolute address */ 105 ARSTR, 106 TSU_CTRST, 107 TSU_FWEN0, 108 TSU_FWEN1, 109 TSU_FCM, 110 TSU_BSYSL0, 111 TSU_BSYSL1, 112 TSU_PRISL0, 113 TSU_PRISL1, 114 TSU_FWSL0, 115 TSU_FWSL1, 116 TSU_FWSLC, 117 TSU_QTAG0, 118 TSU_QTAG1, 119 TSU_QTAGM0, 120 TSU_QTAGM1, 121 TSU_FWSR, 122 TSU_FWINMK, 123 TSU_ADQT0, 124 TSU_ADQT1, 125 TSU_VTAG0, 126 TSU_VTAG1, 127 TSU_ADSBSY, 128 TSU_TEN, 129 TSU_POST1, 130 TSU_POST2, 131 TSU_POST3, 132 TSU_POST4, 133 TSU_ADRH0, 134 TSU_ADRL0, 135 TSU_ADRH31, 136 TSU_ADRL31, 137 138 TXNLCR0, 139 TXALCR0, 140 RXNLCR0, 141 RXALCR0, 142 FWNLCR0, 143 FWALCR0, 144 TXNLCR1, 145 TXALCR1, 146 RXNLCR1, 147 RXALCR1, 148 FWNLCR1, 149 FWALCR1, 150 151 /* This value must be written at last. */ 152 SH_ETH_MAX_REGISTER_OFFSET, 153 }; 154 155 enum { 156 SH_ETH_REG_GIGABIT, 157 SH_ETH_REG_FAST_RZ, 158 SH_ETH_REG_FAST_RCAR, 159 SH_ETH_REG_FAST_SH4, 160 SH_ETH_REG_FAST_SH3_SH2 161 }; 162 163 /* Driver's parameters */ 164 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 165 #define SH_ETH_RX_ALIGN 32 166 #else 167 #define SH_ETH_RX_ALIGN 2 168 #endif 169 170 /* Register's bits 171 */ 172 /* EDSR : sh7734, sh7757, sh7763, r8a7740, and r7s72100 only */ 173 enum EDSR_BIT { 174 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 175 }; 176 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 177 178 /* GECMR : sh7734, sh7763 and r8a7740 only */ 179 enum GECMR_BIT { 180 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01, 181 }; 182 183 /* EDMR */ 184 enum DMAC_M_BIT { 185 EDMR_EL = 0x40, /* Litte endian */ 186 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 187 EDMR_SRST_GETHER = 0x03, 188 EDMR_SRST_ETHER = 0x01, 189 }; 190 191 /* EDTRR */ 192 enum DMAC_T_BIT { 193 EDTRR_TRNS_GETHER = 0x03, 194 EDTRR_TRNS_ETHER = 0x01, 195 }; 196 197 /* EDRRR */ 198 enum EDRRR_R_BIT { 199 EDRRR_R = 0x01, 200 }; 201 202 /* TPAUSER */ 203 enum TPAUSER_BIT { 204 TPAUSER_TPAUSE = 0x0000ffff, 205 TPAUSER_UNLIMITED = 0, 206 }; 207 208 /* BCFR */ 209 enum BCFR_BIT { 210 BCFR_RPAUSE = 0x0000ffff, 211 BCFR_UNLIMITED = 0, 212 }; 213 214 /* PIR */ 215 enum PIR_BIT { 216 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 217 }; 218 219 /* PSR */ 220 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 221 222 /* EESR */ 223 enum EESR_BIT { 224 EESR_TWB1 = 0x80000000, 225 EESR_TWB = 0x40000000, /* same as TWB0 */ 226 EESR_TC1 = 0x20000000, 227 EESR_TUC = 0x10000000, 228 EESR_ROC = 0x08000000, 229 EESR_TABT = 0x04000000, 230 EESR_RABT = 0x02000000, 231 EESR_RFRMER = 0x01000000, /* same as RFCOF */ 232 EESR_ADE = 0x00800000, 233 EESR_ECI = 0x00400000, 234 EESR_FTC = 0x00200000, /* same as TC or TC0 */ 235 EESR_TDE = 0x00100000, 236 EESR_TFE = 0x00080000, /* same as TFUF */ 237 EESR_FRC = 0x00040000, /* same as FR */ 238 EESR_RDE = 0x00020000, 239 EESR_RFE = 0x00010000, 240 EESR_CND = 0x00000800, 241 EESR_DLC = 0x00000400, 242 EESR_CD = 0x00000200, 243 EESR_RTO = 0x00000100, 244 EESR_RMAF = 0x00000080, 245 EESR_CEEF = 0x00000040, 246 EESR_CELF = 0x00000020, 247 EESR_RRF = 0x00000010, 248 EESR_RTLF = 0x00000008, 249 EESR_RTSF = 0x00000004, 250 EESR_PRE = 0x00000002, 251 EESR_CERF = 0x00000001, 252 }; 253 254 #define EESR_RX_CHECK (EESR_FRC | /* Frame recv */ \ 255 EESR_RMAF | /* Multicast address recv */ \ 256 EESR_RRF | /* Bit frame recv */ \ 257 EESR_RTLF | /* Long frame recv */ \ 258 EESR_RTSF | /* Short frame recv */ \ 259 EESR_PRE | /* PHY-LSI recv error */ \ 260 EESR_CERF) /* Recv frame CRC error */ 261 262 #define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \ 263 EESR_RTO) 264 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \ 265 EESR_RDE | EESR_RFRMER | EESR_ADE | \ 266 EESR_TFE | EESR_TDE | EESR_ECI) 267 268 /* EESIPR */ 269 enum DMAC_IM_BIT { 270 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 271 DMAC_M_RABT = 0x02000000, 272 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 273 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 274 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 275 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 276 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 277 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 278 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 279 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 280 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 281 DMAC_M_RINT1 = 0x00000001, 282 }; 283 284 /* Receive descriptor bit */ 285 enum RD_STS_BIT { 286 RD_RACT = 0x80000000, RD_RDEL = 0x40000000, 287 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 288 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 289 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 290 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 291 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 292 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 293 RD_RFS1 = 0x00000001, 294 }; 295 #define RDF1ST RD_RFP1 296 #define RDFEND RD_RFP0 297 #define RD_RFP (RD_RFP1|RD_RFP0) 298 299 /* FCFTR */ 300 enum FCFTR_BIT { 301 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 302 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 303 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 304 }; 305 #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0) 306 #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0) 307 308 /* Transmit descriptor bit */ 309 enum TD_STS_BIT { 310 TD_TACT = 0x80000000, TD_TDLE = 0x40000000, 311 TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000, 312 TD_TFE = 0x08000000, TD_TWBI = 0x04000000, 313 }; 314 #define TDF1ST TD_TFP1 315 #define TDFEND TD_TFP0 316 #define TD_TFP (TD_TFP1|TD_TFP0) 317 318 /* RMCR */ 319 enum RMCR_BIT { 320 RMCR_RNC = 0x00000001, 321 }; 322 323 /* ECMR */ 324 enum FELIC_MODE_BIT { 325 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, 326 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, 327 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 328 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 329 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 330 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, 331 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001, 332 }; 333 334 /* ECSR */ 335 enum ECSR_STATUS_BIT { 336 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 337 ECSR_LCHNG = 0x04, 338 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 339 }; 340 341 #define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \ 342 ECSR_ICD | ECSIPR_MPDIP) 343 344 /* ECSIPR */ 345 enum ECSIPR_STATUS_MASK_BIT { 346 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, 347 ECSIPR_LCHNGIP = 0x04, 348 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, 349 }; 350 351 #define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \ 352 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 353 354 /* APR */ 355 enum APR_BIT { 356 APR_AP = 0x00000001, 357 }; 358 359 /* MPR */ 360 enum MPR_BIT { 361 MPR_MP = 0x00000001, 362 }; 363 364 /* TRSCER */ 365 enum DESC_I_BIT { 366 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 367 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 368 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 369 DESC_I_RINT1 = 0x0001, 370 }; 371 372 #define DEFAULT_TRSCER_ERR_MASK (DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2) 373 374 /* RPADIR */ 375 enum RPADIR_BIT { 376 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 377 RPADIR_PADR = 0x0003f, 378 }; 379 380 /* FDR */ 381 #define DEFAULT_FDR_INIT 0x00000707 382 383 /* ARSTR */ 384 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, }; 385 386 /* TSU_FWEN0 */ 387 enum TSU_FWEN0_BIT { 388 TSU_FWEN0_0 = 0x00000001, 389 }; 390 391 /* TSU_ADSBSY */ 392 enum TSU_ADSBSY_BIT { 393 TSU_ADSBSY_0 = 0x00000001, 394 }; 395 396 /* TSU_TEN */ 397 enum TSU_TEN_BIT { 398 TSU_TEN_0 = 0x80000000, 399 }; 400 401 /* TSU_FWSL0 */ 402 enum TSU_FWSL0_BIT { 403 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800, 404 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200, 405 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010, 406 }; 407 408 /* TSU_FWSLC */ 409 enum TSU_FWSLC_BIT { 410 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000, 411 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040, 412 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010, 413 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004, 414 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001, 415 }; 416 417 /* TSU_VTAGn */ 418 #define TSU_VTAG_ENABLE 0x80000000 419 #define TSU_VTAG_VID_MASK 0x00000fff 420 421 /* The sh ether Tx buffer descriptors. 422 * This structure should be 20 bytes. 423 */ 424 struct sh_eth_txdesc { 425 u32 status; /* TD0 */ 426 #if defined(__LITTLE_ENDIAN) 427 u16 pad0; /* TD1 */ 428 u16 buffer_length; /* TD1 */ 429 #else 430 u16 buffer_length; /* TD1 */ 431 u16 pad0; /* TD1 */ 432 #endif 433 u32 addr; /* TD2 */ 434 u32 pad1; /* padding data */ 435 } __aligned(2) __packed; 436 437 /* The sh ether Rx buffer descriptors. 438 * This structure should be 20 bytes. 439 */ 440 struct sh_eth_rxdesc { 441 u32 status; /* RD0 */ 442 #if defined(__LITTLE_ENDIAN) 443 u16 frame_length; /* RD1 */ 444 u16 buffer_length; /* RD1 */ 445 #else 446 u16 buffer_length; /* RD1 */ 447 u16 frame_length; /* RD1 */ 448 #endif 449 u32 addr; /* RD2 */ 450 u32 pad0; /* padding data */ 451 } __aligned(2) __packed; 452 453 /* This structure is used by each CPU dependency handling. */ 454 struct sh_eth_cpu_data { 455 /* optional functions */ 456 void (*chip_reset)(struct net_device *ndev); 457 void (*set_duplex)(struct net_device *ndev); 458 void (*set_rate)(struct net_device *ndev); 459 460 /* mandatory initialize value */ 461 int register_type; 462 unsigned long eesipr_value; 463 464 /* optional initialize value */ 465 unsigned long ecsr_value; 466 unsigned long ecsipr_value; 467 unsigned long fdr_value; 468 unsigned long fcftr_value; 469 unsigned long rpadir_value; 470 471 /* interrupt checking mask */ 472 unsigned long tx_check; 473 unsigned long eesr_err_check; 474 475 /* Error mask */ 476 unsigned long trscer_err_mask; 477 478 /* hardware features */ 479 unsigned long irq_flags; /* IRQ configuration flags */ 480 unsigned no_psr:1; /* EtherC DO NOT have PSR */ 481 unsigned apr:1; /* EtherC have APR */ 482 unsigned mpr:1; /* EtherC have MPR */ 483 unsigned tpauser:1; /* EtherC have TPAUSER */ 484 unsigned bculr:1; /* EtherC have BCULR */ 485 unsigned tsu:1; /* EtherC have TSU */ 486 unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */ 487 unsigned rpadir:1; /* E-DMAC have RPADIR */ 488 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */ 489 unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */ 490 unsigned hw_crc:1; /* E-DMAC have CSMR */ 491 unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */ 492 unsigned shift_rd0:1; /* shift Rx descriptor word 0 right by 16 */ 493 unsigned rmiimode:1; /* EtherC has RMIIMODE register */ 494 }; 495 496 struct sh_eth_private { 497 struct platform_device *pdev; 498 struct sh_eth_cpu_data *cd; 499 const u16 *reg_offset; 500 void __iomem *addr; 501 void __iomem *tsu_addr; 502 u32 num_rx_ring; 503 u32 num_tx_ring; 504 dma_addr_t rx_desc_dma; 505 dma_addr_t tx_desc_dma; 506 struct sh_eth_rxdesc *rx_ring; 507 struct sh_eth_txdesc *tx_ring; 508 struct sk_buff **rx_skbuff; 509 struct sk_buff **tx_skbuff; 510 spinlock_t lock; /* Register access lock */ 511 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */ 512 u32 cur_tx, dirty_tx; 513 u32 rx_buf_sz; /* Based on MTU+slack. */ 514 int edmac_endian; 515 struct napi_struct napi; 516 bool irq_enabled; 517 /* MII transceiver section. */ 518 u32 phy_id; /* PHY ID */ 519 struct mii_bus *mii_bus; /* MDIO bus control */ 520 struct phy_device *phydev; /* PHY device control */ 521 int link; 522 phy_interface_t phy_interface; 523 int msg_enable; 524 int speed; 525 int duplex; 526 int port; /* for TSU */ 527 int vlan_num_ids; /* for VLAN tag filter */ 528 529 unsigned no_ether_link:1; 530 unsigned ether_link_active_low:1; 531 unsigned is_opened:1; 532 }; 533 534 static inline void sh_eth_soft_swap(char *src, int len) 535 { 536 #ifdef __LITTLE_ENDIAN__ 537 u32 *p = (u32 *)src; 538 u32 *maxp; 539 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32)); 540 541 for (; p < maxp; p++) 542 *p = swab32(*p); 543 #endif 544 } 545 546 static inline void sh_eth_write(struct net_device *ndev, unsigned long data, 547 int enum_index) 548 { 549 struct sh_eth_private *mdp = netdev_priv(ndev); 550 551 iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]); 552 } 553 554 static inline unsigned long sh_eth_read(struct net_device *ndev, 555 int enum_index) 556 { 557 struct sh_eth_private *mdp = netdev_priv(ndev); 558 559 return ioread32(mdp->addr + mdp->reg_offset[enum_index]); 560 } 561 562 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp, 563 int enum_index) 564 { 565 return mdp->tsu_addr + mdp->reg_offset[enum_index]; 566 } 567 568 static inline void sh_eth_tsu_write(struct sh_eth_private *mdp, 569 unsigned long data, int enum_index) 570 { 571 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]); 572 } 573 574 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp, 575 int enum_index) 576 { 577 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]); 578 } 579 580 #endif /* #ifndef __SH_ETH_H__ */ 581