1 /* 2 * SuperH Ethernet device driver 3 * 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2012 Renesas Solutions Corp. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * The full GNU General Public License is included in this distribution in 20 * the file called "COPYING". 21 */ 22 23 #ifndef __SH_ETH_H__ 24 #define __SH_ETH_H__ 25 26 #define CARDNAME "sh-eth" 27 #define TX_TIMEOUT (5*HZ) 28 #define TX_RING_SIZE 64 /* Tx ring size */ 29 #define RX_RING_SIZE 64 /* Rx ring size */ 30 #define TX_RING_MIN 64 31 #define RX_RING_MIN 64 32 #define TX_RING_MAX 1024 33 #define RX_RING_MAX 1024 34 #define ETHERSMALL 60 35 #define PKT_BUF_SZ 1538 36 #define SH_ETH_TSU_TIMEOUT_MS 500 37 #define SH_ETH_TSU_CAM_ENTRIES 32 38 39 enum { 40 /* E-DMAC registers */ 41 EDSR = 0, 42 EDMR, 43 EDTRR, 44 EDRRR, 45 EESR, 46 EESIPR, 47 TDLAR, 48 TDFAR, 49 TDFXR, 50 TDFFR, 51 RDLAR, 52 RDFAR, 53 RDFXR, 54 RDFFR, 55 TRSCER, 56 RMFCR, 57 TFTR, 58 FDR, 59 RMCR, 60 EDOCR, 61 TFUCR, 62 RFOCR, 63 FCFTR, 64 RPADIR, 65 TRIMD, 66 RBWAR, 67 TBRAR, 68 69 /* Ether registers */ 70 ECMR, 71 ECSR, 72 ECSIPR, 73 PIR, 74 PSR, 75 RDMLR, 76 PIPR, 77 RFLR, 78 IPGR, 79 APR, 80 MPR, 81 PFTCR, 82 PFRCR, 83 RFCR, 84 RFCF, 85 TPAUSER, 86 TPAUSECR, 87 BCFR, 88 BCFRR, 89 GECMR, 90 BCULR, 91 MAHR, 92 MALR, 93 TROCR, 94 CDCR, 95 LCCR, 96 CNDCR, 97 CEFCR, 98 FRECR, 99 TSFRCR, 100 TLFRCR, 101 CERCR, 102 CEECR, 103 MAFCR, 104 RTRATE, 105 CSMR, 106 RMII_MII, 107 108 /* TSU Absolute address */ 109 ARSTR, 110 TSU_CTRST, 111 TSU_FWEN0, 112 TSU_FWEN1, 113 TSU_FCM, 114 TSU_BSYSL0, 115 TSU_BSYSL1, 116 TSU_PRISL0, 117 TSU_PRISL1, 118 TSU_FWSL0, 119 TSU_FWSL1, 120 TSU_FWSLC, 121 TSU_QTAG0, 122 TSU_QTAG1, 123 TSU_QTAGM0, 124 TSU_QTAGM1, 125 TSU_FWSR, 126 TSU_FWINMK, 127 TSU_ADQT0, 128 TSU_ADQT1, 129 TSU_VTAG0, 130 TSU_VTAG1, 131 TSU_ADSBSY, 132 TSU_TEN, 133 TSU_POST1, 134 TSU_POST2, 135 TSU_POST3, 136 TSU_POST4, 137 TSU_ADRH0, 138 TSU_ADRL0, 139 TSU_ADRH31, 140 TSU_ADRL31, 141 142 TXNLCR0, 143 TXALCR0, 144 RXNLCR0, 145 RXALCR0, 146 FWNLCR0, 147 FWALCR0, 148 TXNLCR1, 149 TXALCR1, 150 RXNLCR1, 151 RXALCR1, 152 FWNLCR1, 153 FWALCR1, 154 155 /* This value must be written at last. */ 156 SH_ETH_MAX_REGISTER_OFFSET, 157 }; 158 159 /* Driver's parameters */ 160 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 161 #define SH4_SKB_RX_ALIGN 32 162 #else 163 #define SH2_SH3_SKB_RX_ALIGN 2 164 #endif 165 166 /* 167 * Register's bits 168 */ 169 /* EDSR : sh7734, sh7757, sh7763, and r8a7740 only */ 170 enum EDSR_BIT { 171 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 172 }; 173 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 174 175 /* GECMR : sh7734, sh7763 and r8a7740 only */ 176 enum GECMR_BIT { 177 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01, 178 }; 179 180 /* EDMR */ 181 enum DMAC_M_BIT { 182 EDMR_EL = 0x40, /* Litte endian */ 183 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 184 EDMR_SRST_GETHER = 0x03, 185 EDMR_SRST_ETHER = 0x01, 186 }; 187 188 /* EDTRR */ 189 enum DMAC_T_BIT { 190 EDTRR_TRNS_GETHER = 0x03, 191 EDTRR_TRNS_ETHER = 0x01, 192 }; 193 194 /* EDRRR*/ 195 enum EDRRR_R_BIT { 196 EDRRR_R = 0x01, 197 }; 198 199 /* TPAUSER */ 200 enum TPAUSER_BIT { 201 TPAUSER_TPAUSE = 0x0000ffff, 202 TPAUSER_UNLIMITED = 0, 203 }; 204 205 /* BCFR */ 206 enum BCFR_BIT { 207 BCFR_RPAUSE = 0x0000ffff, 208 BCFR_UNLIMITED = 0, 209 }; 210 211 /* PIR */ 212 enum PIR_BIT { 213 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 214 }; 215 216 /* PSR */ 217 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 218 219 /* EESR */ 220 enum EESR_BIT { 221 EESR_TWB1 = 0x80000000, 222 EESR_TWB = 0x40000000, /* same as TWB0 */ 223 EESR_TC1 = 0x20000000, 224 EESR_TUC = 0x10000000, 225 EESR_ROC = 0x08000000, 226 EESR_TABT = 0x04000000, 227 EESR_RABT = 0x02000000, 228 EESR_RFRMER = 0x01000000, /* same as RFCOF */ 229 EESR_ADE = 0x00800000, 230 EESR_ECI = 0x00400000, 231 EESR_FTC = 0x00200000, /* same as TC or TC0 */ 232 EESR_TDE = 0x00100000, 233 EESR_TFE = 0x00080000, /* same as TFUF */ 234 EESR_FRC = 0x00040000, /* same as FR */ 235 EESR_RDE = 0x00020000, 236 EESR_RFE = 0x00010000, 237 EESR_CND = 0x00000800, 238 EESR_DLC = 0x00000400, 239 EESR_CD = 0x00000200, 240 EESR_RTO = 0x00000100, 241 EESR_RMAF = 0x00000080, 242 EESR_CEEF = 0x00000040, 243 EESR_CELF = 0x00000020, 244 EESR_RRF = 0x00000010, 245 EESR_RTLF = 0x00000008, 246 EESR_RTSF = 0x00000004, 247 EESR_PRE = 0x00000002, 248 EESR_CERF = 0x00000001, 249 }; 250 251 #define EESR_RX_CHECK (EESR_FRC | /* Frame recv */ \ 252 EESR_RMAF | /* Multicast address recv */ \ 253 EESR_RRF | /* Bit frame recv */ \ 254 EESR_RTLF | /* Long frame recv */ \ 255 EESR_RTSF | /* Short frame recv */ \ 256 EESR_PRE | /* PHY-LSI recv error */ \ 257 EESR_CERF) /* Recv frame CRC error */ 258 259 #define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \ 260 EESR_RTO) 261 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \ 262 EESR_RDE | EESR_RFRMER | EESR_ADE | \ 263 EESR_TFE | EESR_TDE | EESR_ECI) 264 265 /* EESIPR */ 266 enum DMAC_IM_BIT { 267 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 268 DMAC_M_RABT = 0x02000000, 269 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 270 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 271 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 272 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 273 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 274 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 275 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 276 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 277 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 278 DMAC_M_RINT1 = 0x00000001, 279 }; 280 281 /* Receive descriptor bit */ 282 enum RD_STS_BIT { 283 RD_RACT = 0x80000000, RD_RDEL = 0x40000000, 284 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 285 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 286 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 287 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 288 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 289 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 290 RD_RFS1 = 0x00000001, 291 }; 292 #define RDF1ST RD_RFP1 293 #define RDFEND RD_RFP0 294 #define RD_RFP (RD_RFP1|RD_RFP0) 295 296 /* FCFTR */ 297 enum FCFTR_BIT { 298 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 299 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 300 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 301 }; 302 #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0) 303 #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0) 304 305 /* Transmit descriptor bit */ 306 enum TD_STS_BIT { 307 TD_TACT = 0x80000000, TD_TDLE = 0x40000000, 308 TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000, 309 TD_TFE = 0x08000000, TD_TWBI = 0x04000000, 310 }; 311 #define TDF1ST TD_TFP1 312 #define TDFEND TD_TFP0 313 #define TD_TFP (TD_TFP1|TD_TFP0) 314 315 /* RMCR */ 316 #define DEFAULT_RMCR_VALUE 0x00000000 317 318 /* ECMR */ 319 enum FELIC_MODE_BIT { 320 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, 321 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, 322 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 323 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 324 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 325 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, 326 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001, 327 }; 328 329 /* ECSR */ 330 enum ECSR_STATUS_BIT { 331 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 332 ECSR_LCHNG = 0x04, 333 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 334 }; 335 336 #define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \ 337 ECSR_ICD | ECSIPR_MPDIP) 338 339 /* ECSIPR */ 340 enum ECSIPR_STATUS_MASK_BIT { 341 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, 342 ECSIPR_LCHNGIP = 0x04, 343 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, 344 }; 345 346 #define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \ 347 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 348 349 /* APR */ 350 enum APR_BIT { 351 APR_AP = 0x00000001, 352 }; 353 354 /* MPR */ 355 enum MPR_BIT { 356 MPR_MP = 0x00000001, 357 }; 358 359 /* TRSCER */ 360 enum DESC_I_BIT { 361 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 362 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 363 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 364 DESC_I_RINT1 = 0x0001, 365 }; 366 367 /* RPADIR */ 368 enum RPADIR_BIT { 369 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 370 RPADIR_PADR = 0x0003f, 371 }; 372 373 /* FDR */ 374 #define DEFAULT_FDR_INIT 0x00000707 375 376 /* ARSTR */ 377 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, }; 378 379 /* TSU_FWEN0 */ 380 enum TSU_FWEN0_BIT { 381 TSU_FWEN0_0 = 0x00000001, 382 }; 383 384 /* TSU_ADSBSY */ 385 enum TSU_ADSBSY_BIT { 386 TSU_ADSBSY_0 = 0x00000001, 387 }; 388 389 /* TSU_TEN */ 390 enum TSU_TEN_BIT { 391 TSU_TEN_0 = 0x80000000, 392 }; 393 394 /* TSU_FWSL0 */ 395 enum TSU_FWSL0_BIT { 396 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800, 397 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200, 398 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010, 399 }; 400 401 /* TSU_FWSLC */ 402 enum TSU_FWSLC_BIT { 403 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000, 404 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040, 405 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010, 406 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004, 407 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001, 408 }; 409 410 /* TSU_VTAGn */ 411 #define TSU_VTAG_ENABLE 0x80000000 412 #define TSU_VTAG_VID_MASK 0x00000fff 413 414 /* 415 * The sh ether Tx buffer descriptors. 416 * This structure should be 20 bytes. 417 */ 418 struct sh_eth_txdesc { 419 u32 status; /* TD0 */ 420 #if defined(__LITTLE_ENDIAN) 421 u16 pad0; /* TD1 */ 422 u16 buffer_length; /* TD1 */ 423 #else 424 u16 buffer_length; /* TD1 */ 425 u16 pad0; /* TD1 */ 426 #endif 427 u32 addr; /* TD2 */ 428 u32 pad1; /* padding data */ 429 } __attribute__((aligned(2), packed)); 430 431 /* 432 * The sh ether Rx buffer descriptors. 433 * This structure should be 20 bytes. 434 */ 435 struct sh_eth_rxdesc { 436 u32 status; /* RD0 */ 437 #if defined(__LITTLE_ENDIAN) 438 u16 frame_length; /* RD1 */ 439 u16 buffer_length; /* RD1 */ 440 #else 441 u16 buffer_length; /* RD1 */ 442 u16 frame_length; /* RD1 */ 443 #endif 444 u32 addr; /* RD2 */ 445 u32 pad0; /* padding data */ 446 } __attribute__((aligned(2), packed)); 447 448 /* This structure is used by each CPU dependency handling. */ 449 struct sh_eth_cpu_data { 450 /* optional functions */ 451 void (*chip_reset)(struct net_device *ndev); 452 void (*set_duplex)(struct net_device *ndev); 453 void (*set_rate)(struct net_device *ndev); 454 455 /* mandatory initialize value */ 456 unsigned long eesipr_value; 457 458 /* optional initialize value */ 459 unsigned long ecsr_value; 460 unsigned long ecsipr_value; 461 unsigned long fdr_value; 462 unsigned long fcftr_value; 463 unsigned long rpadir_value; 464 unsigned long rmcr_value; 465 466 /* interrupt checking mask */ 467 unsigned long tx_check; 468 unsigned long eesr_err_check; 469 470 /* hardware features */ 471 unsigned long irq_flags; /* IRQ configuration flags */ 472 unsigned no_psr:1; /* EtherC DO NOT have PSR */ 473 unsigned apr:1; /* EtherC have APR */ 474 unsigned mpr:1; /* EtherC have MPR */ 475 unsigned tpauser:1; /* EtherC have TPAUSER */ 476 unsigned bculr:1; /* EtherC have BCULR */ 477 unsigned tsu:1; /* EtherC have TSU */ 478 unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */ 479 unsigned rpadir:1; /* E-DMAC have RPADIR */ 480 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */ 481 unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */ 482 unsigned hw_crc:1; /* E-DMAC have CSMR */ 483 unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */ 484 unsigned shift_rd0:1; /* shift Rx descriptor word 0 right by 16 */ 485 }; 486 487 struct sh_eth_private { 488 struct platform_device *pdev; 489 struct sh_eth_cpu_data *cd; 490 const u16 *reg_offset; 491 void __iomem *addr; 492 void __iomem *tsu_addr; 493 u32 num_rx_ring; 494 u32 num_tx_ring; 495 dma_addr_t rx_desc_dma; 496 dma_addr_t tx_desc_dma; 497 struct sh_eth_rxdesc *rx_ring; 498 struct sh_eth_txdesc *tx_ring; 499 struct sk_buff **rx_skbuff; 500 struct sk_buff **tx_skbuff; 501 spinlock_t lock; 502 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */ 503 u32 cur_tx, dirty_tx; 504 u32 rx_buf_sz; /* Based on MTU+slack. */ 505 int edmac_endian; 506 struct napi_struct napi; 507 /* MII transceiver section. */ 508 u32 phy_id; /* PHY ID */ 509 struct mii_bus *mii_bus; /* MDIO bus control */ 510 struct phy_device *phydev; /* PHY device control */ 511 int link; 512 phy_interface_t phy_interface; 513 int msg_enable; 514 int speed; 515 int duplex; 516 int port; /* for TSU */ 517 int vlan_num_ids; /* for VLAN tag filter */ 518 519 unsigned no_ether_link:1; 520 unsigned ether_link_active_low:1; 521 }; 522 523 static inline void sh_eth_soft_swap(char *src, int len) 524 { 525 #ifdef __LITTLE_ENDIAN__ 526 u32 *p = (u32 *)src; 527 u32 *maxp; 528 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32)); 529 530 for (; p < maxp; p++) 531 *p = swab32(*p); 532 #endif 533 } 534 535 static inline void sh_eth_write(struct net_device *ndev, unsigned long data, 536 int enum_index) 537 { 538 struct sh_eth_private *mdp = netdev_priv(ndev); 539 540 iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]); 541 } 542 543 static inline unsigned long sh_eth_read(struct net_device *ndev, 544 int enum_index) 545 { 546 struct sh_eth_private *mdp = netdev_priv(ndev); 547 548 return ioread32(mdp->addr + mdp->reg_offset[enum_index]); 549 } 550 551 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp, 552 int enum_index) 553 { 554 return mdp->tsu_addr + mdp->reg_offset[enum_index]; 555 } 556 557 static inline void sh_eth_tsu_write(struct sh_eth_private *mdp, 558 unsigned long data, int enum_index) 559 { 560 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]); 561 } 562 563 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp, 564 int enum_index) 565 { 566 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]); 567 } 568 569 #endif /* #ifndef __SH_ETH_H__ */ 570