1 /* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2014 Renesas Electronics Corporation 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2014 Renesas Solutions Corp. 6 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 7 * Copyright (C) 2014 Codethink Limited 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 */ 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/etherdevice.h> 28 #include <linux/delay.h> 29 #include <linux/platform_device.h> 30 #include <linux/mdio-bitbang.h> 31 #include <linux/netdevice.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_net.h> 36 #include <linux/phy.h> 37 #include <linux/cache.h> 38 #include <linux/io.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/slab.h> 41 #include <linux/ethtool.h> 42 #include <linux/if_vlan.h> 43 #include <linux/sh_eth.h> 44 #include <linux/of_mdio.h> 45 46 #include "sh_eth.h" 47 48 #define SH_ETH_DEF_MSG_ENABLE \ 49 (NETIF_MSG_LINK | \ 50 NETIF_MSG_TIMER | \ 51 NETIF_MSG_RX_ERR| \ 52 NETIF_MSG_TX_ERR) 53 54 #define SH_ETH_OFFSET_INVALID ((u16)~0) 55 56 #define SH_ETH_OFFSET_DEFAULTS \ 57 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 58 59 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 60 SH_ETH_OFFSET_DEFAULTS, 61 62 [EDSR] = 0x0000, 63 [EDMR] = 0x0400, 64 [EDTRR] = 0x0408, 65 [EDRRR] = 0x0410, 66 [EESR] = 0x0428, 67 [EESIPR] = 0x0430, 68 [TDLAR] = 0x0010, 69 [TDFAR] = 0x0014, 70 [TDFXR] = 0x0018, 71 [TDFFR] = 0x001c, 72 [RDLAR] = 0x0030, 73 [RDFAR] = 0x0034, 74 [RDFXR] = 0x0038, 75 [RDFFR] = 0x003c, 76 [TRSCER] = 0x0438, 77 [RMFCR] = 0x0440, 78 [TFTR] = 0x0448, 79 [FDR] = 0x0450, 80 [RMCR] = 0x0458, 81 [RPADIR] = 0x0460, 82 [FCFTR] = 0x0468, 83 [CSMR] = 0x04E4, 84 85 [ECMR] = 0x0500, 86 [ECSR] = 0x0510, 87 [ECSIPR] = 0x0518, 88 [PIR] = 0x0520, 89 [PSR] = 0x0528, 90 [PIPR] = 0x052c, 91 [RFLR] = 0x0508, 92 [APR] = 0x0554, 93 [MPR] = 0x0558, 94 [PFTCR] = 0x055c, 95 [PFRCR] = 0x0560, 96 [TPAUSER] = 0x0564, 97 [GECMR] = 0x05b0, 98 [BCULR] = 0x05b4, 99 [MAHR] = 0x05c0, 100 [MALR] = 0x05c8, 101 [TROCR] = 0x0700, 102 [CDCR] = 0x0708, 103 [LCCR] = 0x0710, 104 [CEFCR] = 0x0740, 105 [FRECR] = 0x0748, 106 [TSFRCR] = 0x0750, 107 [TLFRCR] = 0x0758, 108 [RFCR] = 0x0760, 109 [CERCR] = 0x0768, 110 [CEECR] = 0x0770, 111 [MAFCR] = 0x0778, 112 [RMII_MII] = 0x0790, 113 114 [ARSTR] = 0x0000, 115 [TSU_CTRST] = 0x0004, 116 [TSU_FWEN0] = 0x0010, 117 [TSU_FWEN1] = 0x0014, 118 [TSU_FCM] = 0x0018, 119 [TSU_BSYSL0] = 0x0020, 120 [TSU_BSYSL1] = 0x0024, 121 [TSU_PRISL0] = 0x0028, 122 [TSU_PRISL1] = 0x002c, 123 [TSU_FWSL0] = 0x0030, 124 [TSU_FWSL1] = 0x0034, 125 [TSU_FWSLC] = 0x0038, 126 [TSU_QTAGM0] = 0x0040, 127 [TSU_QTAGM1] = 0x0044, 128 [TSU_FWSR] = 0x0050, 129 [TSU_FWINMK] = 0x0054, 130 [TSU_ADQT0] = 0x0048, 131 [TSU_ADQT1] = 0x004c, 132 [TSU_VTAG0] = 0x0058, 133 [TSU_VTAG1] = 0x005c, 134 [TSU_ADSBSY] = 0x0060, 135 [TSU_TEN] = 0x0064, 136 [TSU_POST1] = 0x0070, 137 [TSU_POST2] = 0x0074, 138 [TSU_POST3] = 0x0078, 139 [TSU_POST4] = 0x007c, 140 [TSU_ADRH0] = 0x0100, 141 142 [TXNLCR0] = 0x0080, 143 [TXALCR0] = 0x0084, 144 [RXNLCR0] = 0x0088, 145 [RXALCR0] = 0x008c, 146 [FWNLCR0] = 0x0090, 147 [FWALCR0] = 0x0094, 148 [TXNLCR1] = 0x00a0, 149 [TXALCR1] = 0x00a4, 150 [RXNLCR1] = 0x00a8, 151 [RXALCR1] = 0x00ac, 152 [FWNLCR1] = 0x00b0, 153 [FWALCR1] = 0x00b4, 154 }; 155 156 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 157 SH_ETH_OFFSET_DEFAULTS, 158 159 [EDSR] = 0x0000, 160 [EDMR] = 0x0400, 161 [EDTRR] = 0x0408, 162 [EDRRR] = 0x0410, 163 [EESR] = 0x0428, 164 [EESIPR] = 0x0430, 165 [TDLAR] = 0x0010, 166 [TDFAR] = 0x0014, 167 [TDFXR] = 0x0018, 168 [TDFFR] = 0x001c, 169 [RDLAR] = 0x0030, 170 [RDFAR] = 0x0034, 171 [RDFXR] = 0x0038, 172 [RDFFR] = 0x003c, 173 [TRSCER] = 0x0438, 174 [RMFCR] = 0x0440, 175 [TFTR] = 0x0448, 176 [FDR] = 0x0450, 177 [RMCR] = 0x0458, 178 [RPADIR] = 0x0460, 179 [FCFTR] = 0x0468, 180 [CSMR] = 0x04E4, 181 182 [ECMR] = 0x0500, 183 [RFLR] = 0x0508, 184 [ECSR] = 0x0510, 185 [ECSIPR] = 0x0518, 186 [PIR] = 0x0520, 187 [APR] = 0x0554, 188 [MPR] = 0x0558, 189 [PFTCR] = 0x055c, 190 [PFRCR] = 0x0560, 191 [TPAUSER] = 0x0564, 192 [MAHR] = 0x05c0, 193 [MALR] = 0x05c8, 194 [CEFCR] = 0x0740, 195 [FRECR] = 0x0748, 196 [TSFRCR] = 0x0750, 197 [TLFRCR] = 0x0758, 198 [RFCR] = 0x0760, 199 [MAFCR] = 0x0778, 200 201 [ARSTR] = 0x0000, 202 [TSU_CTRST] = 0x0004, 203 [TSU_FWSLC] = 0x0038, 204 [TSU_VTAG0] = 0x0058, 205 [TSU_ADSBSY] = 0x0060, 206 [TSU_TEN] = 0x0064, 207 [TSU_POST1] = 0x0070, 208 [TSU_POST2] = 0x0074, 209 [TSU_POST3] = 0x0078, 210 [TSU_POST4] = 0x007c, 211 [TSU_ADRH0] = 0x0100, 212 213 [TXNLCR0] = 0x0080, 214 [TXALCR0] = 0x0084, 215 [RXNLCR0] = 0x0088, 216 [RXALCR0] = 0x008C, 217 }; 218 219 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 220 SH_ETH_OFFSET_DEFAULTS, 221 222 [ECMR] = 0x0300, 223 [RFLR] = 0x0308, 224 [ECSR] = 0x0310, 225 [ECSIPR] = 0x0318, 226 [PIR] = 0x0320, 227 [PSR] = 0x0328, 228 [RDMLR] = 0x0340, 229 [IPGR] = 0x0350, 230 [APR] = 0x0354, 231 [MPR] = 0x0358, 232 [RFCF] = 0x0360, 233 [TPAUSER] = 0x0364, 234 [TPAUSECR] = 0x0368, 235 [MAHR] = 0x03c0, 236 [MALR] = 0x03c8, 237 [TROCR] = 0x03d0, 238 [CDCR] = 0x03d4, 239 [LCCR] = 0x03d8, 240 [CNDCR] = 0x03dc, 241 [CEFCR] = 0x03e4, 242 [FRECR] = 0x03e8, 243 [TSFRCR] = 0x03ec, 244 [TLFRCR] = 0x03f0, 245 [RFCR] = 0x03f4, 246 [MAFCR] = 0x03f8, 247 248 [EDMR] = 0x0200, 249 [EDTRR] = 0x0208, 250 [EDRRR] = 0x0210, 251 [TDLAR] = 0x0218, 252 [RDLAR] = 0x0220, 253 [EESR] = 0x0228, 254 [EESIPR] = 0x0230, 255 [TRSCER] = 0x0238, 256 [RMFCR] = 0x0240, 257 [TFTR] = 0x0248, 258 [FDR] = 0x0250, 259 [RMCR] = 0x0258, 260 [TFUCR] = 0x0264, 261 [RFOCR] = 0x0268, 262 [RMIIMODE] = 0x026c, 263 [FCFTR] = 0x0270, 264 [TRIMD] = 0x027c, 265 }; 266 267 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 268 SH_ETH_OFFSET_DEFAULTS, 269 270 [ECMR] = 0x0100, 271 [RFLR] = 0x0108, 272 [ECSR] = 0x0110, 273 [ECSIPR] = 0x0118, 274 [PIR] = 0x0120, 275 [PSR] = 0x0128, 276 [RDMLR] = 0x0140, 277 [IPGR] = 0x0150, 278 [APR] = 0x0154, 279 [MPR] = 0x0158, 280 [TPAUSER] = 0x0164, 281 [RFCF] = 0x0160, 282 [TPAUSECR] = 0x0168, 283 [BCFRR] = 0x016c, 284 [MAHR] = 0x01c0, 285 [MALR] = 0x01c8, 286 [TROCR] = 0x01d0, 287 [CDCR] = 0x01d4, 288 [LCCR] = 0x01d8, 289 [CNDCR] = 0x01dc, 290 [CEFCR] = 0x01e4, 291 [FRECR] = 0x01e8, 292 [TSFRCR] = 0x01ec, 293 [TLFRCR] = 0x01f0, 294 [RFCR] = 0x01f4, 295 [MAFCR] = 0x01f8, 296 [RTRATE] = 0x01fc, 297 298 [EDMR] = 0x0000, 299 [EDTRR] = 0x0008, 300 [EDRRR] = 0x0010, 301 [TDLAR] = 0x0018, 302 [RDLAR] = 0x0020, 303 [EESR] = 0x0028, 304 [EESIPR] = 0x0030, 305 [TRSCER] = 0x0038, 306 [RMFCR] = 0x0040, 307 [TFTR] = 0x0048, 308 [FDR] = 0x0050, 309 [RMCR] = 0x0058, 310 [TFUCR] = 0x0064, 311 [RFOCR] = 0x0068, 312 [FCFTR] = 0x0070, 313 [RPADIR] = 0x0078, 314 [TRIMD] = 0x007c, 315 [RBWAR] = 0x00c8, 316 [RDFAR] = 0x00cc, 317 [TBRAR] = 0x00d4, 318 [TDFAR] = 0x00d8, 319 }; 320 321 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 322 SH_ETH_OFFSET_DEFAULTS, 323 324 [EDMR] = 0x0000, 325 [EDTRR] = 0x0004, 326 [EDRRR] = 0x0008, 327 [TDLAR] = 0x000c, 328 [RDLAR] = 0x0010, 329 [EESR] = 0x0014, 330 [EESIPR] = 0x0018, 331 [TRSCER] = 0x001c, 332 [RMFCR] = 0x0020, 333 [TFTR] = 0x0024, 334 [FDR] = 0x0028, 335 [RMCR] = 0x002c, 336 [EDOCR] = 0x0030, 337 [FCFTR] = 0x0034, 338 [RPADIR] = 0x0038, 339 [TRIMD] = 0x003c, 340 [RBWAR] = 0x0040, 341 [RDFAR] = 0x0044, 342 [TBRAR] = 0x004c, 343 [TDFAR] = 0x0050, 344 345 [ECMR] = 0x0160, 346 [ECSR] = 0x0164, 347 [ECSIPR] = 0x0168, 348 [PIR] = 0x016c, 349 [MAHR] = 0x0170, 350 [MALR] = 0x0174, 351 [RFLR] = 0x0178, 352 [PSR] = 0x017c, 353 [TROCR] = 0x0180, 354 [CDCR] = 0x0184, 355 [LCCR] = 0x0188, 356 [CNDCR] = 0x018c, 357 [CEFCR] = 0x0194, 358 [FRECR] = 0x0198, 359 [TSFRCR] = 0x019c, 360 [TLFRCR] = 0x01a0, 361 [RFCR] = 0x01a4, 362 [MAFCR] = 0x01a8, 363 [IPGR] = 0x01b4, 364 [APR] = 0x01b8, 365 [MPR] = 0x01bc, 366 [TPAUSER] = 0x01c4, 367 [BCFR] = 0x01cc, 368 369 [ARSTR] = 0x0000, 370 [TSU_CTRST] = 0x0004, 371 [TSU_FWEN0] = 0x0010, 372 [TSU_FWEN1] = 0x0014, 373 [TSU_FCM] = 0x0018, 374 [TSU_BSYSL0] = 0x0020, 375 [TSU_BSYSL1] = 0x0024, 376 [TSU_PRISL0] = 0x0028, 377 [TSU_PRISL1] = 0x002c, 378 [TSU_FWSL0] = 0x0030, 379 [TSU_FWSL1] = 0x0034, 380 [TSU_FWSLC] = 0x0038, 381 [TSU_QTAGM0] = 0x0040, 382 [TSU_QTAGM1] = 0x0044, 383 [TSU_ADQT0] = 0x0048, 384 [TSU_ADQT1] = 0x004c, 385 [TSU_FWSR] = 0x0050, 386 [TSU_FWINMK] = 0x0054, 387 [TSU_ADSBSY] = 0x0060, 388 [TSU_TEN] = 0x0064, 389 [TSU_POST1] = 0x0070, 390 [TSU_POST2] = 0x0074, 391 [TSU_POST3] = 0x0078, 392 [TSU_POST4] = 0x007c, 393 394 [TXNLCR0] = 0x0080, 395 [TXALCR0] = 0x0084, 396 [RXNLCR0] = 0x0088, 397 [RXALCR0] = 0x008c, 398 [FWNLCR0] = 0x0090, 399 [FWALCR0] = 0x0094, 400 [TXNLCR1] = 0x00a0, 401 [TXALCR1] = 0x00a4, 402 [RXNLCR1] = 0x00a8, 403 [RXALCR1] = 0x00ac, 404 [FWNLCR1] = 0x00b0, 405 [FWALCR1] = 0x00b4, 406 407 [TSU_ADRH0] = 0x0100, 408 }; 409 410 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 411 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 412 413 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 414 { 415 struct sh_eth_private *mdp = netdev_priv(ndev); 416 u16 offset = mdp->reg_offset[enum_index]; 417 418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 419 return; 420 421 iowrite32(data, mdp->addr + offset); 422 } 423 424 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 425 { 426 struct sh_eth_private *mdp = netdev_priv(ndev); 427 u16 offset = mdp->reg_offset[enum_index]; 428 429 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 430 return ~0U; 431 432 return ioread32(mdp->addr + offset); 433 } 434 435 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 436 u32 set) 437 { 438 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 439 enum_index); 440 } 441 442 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index) 443 { 444 return mdp->reg_offset[enum_index]; 445 } 446 447 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data, 448 int enum_index) 449 { 450 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 451 452 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 453 return; 454 455 iowrite32(data, mdp->tsu_addr + offset); 456 } 457 458 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index) 459 { 460 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 461 462 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 463 return ~0U; 464 465 return ioread32(mdp->tsu_addr + offset); 466 } 467 468 static void sh_eth_soft_swap(char *src, int len) 469 { 470 #ifdef __LITTLE_ENDIAN 471 u32 *p = (u32 *)src; 472 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32)); 473 474 for (; p < maxp; p++) 475 *p = swab32(*p); 476 #endif 477 } 478 479 static void sh_eth_select_mii(struct net_device *ndev) 480 { 481 struct sh_eth_private *mdp = netdev_priv(ndev); 482 u32 value; 483 484 switch (mdp->phy_interface) { 485 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID: 486 value = 0x3; 487 break; 488 case PHY_INTERFACE_MODE_GMII: 489 value = 0x2; 490 break; 491 case PHY_INTERFACE_MODE_MII: 492 value = 0x1; 493 break; 494 case PHY_INTERFACE_MODE_RMII: 495 value = 0x0; 496 break; 497 default: 498 netdev_warn(ndev, 499 "PHY interface mode was not setup. Set to MII.\n"); 500 value = 0x1; 501 break; 502 } 503 504 sh_eth_write(ndev, value, RMII_MII); 505 } 506 507 static void sh_eth_set_duplex(struct net_device *ndev) 508 { 509 struct sh_eth_private *mdp = netdev_priv(ndev); 510 511 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 512 } 513 514 static void sh_eth_chip_reset(struct net_device *ndev) 515 { 516 struct sh_eth_private *mdp = netdev_priv(ndev); 517 518 /* reset device */ 519 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 520 mdelay(1); 521 } 522 523 static int sh_eth_soft_reset(struct net_device *ndev) 524 { 525 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 526 mdelay(3); 527 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 528 529 return 0; 530 } 531 532 static int sh_eth_check_soft_reset(struct net_device *ndev) 533 { 534 int cnt; 535 536 for (cnt = 100; cnt > 0; cnt--) { 537 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 538 return 0; 539 mdelay(1); 540 } 541 542 netdev_err(ndev, "Device reset failed\n"); 543 return -ETIMEDOUT; 544 } 545 546 static int sh_eth_soft_reset_gether(struct net_device *ndev) 547 { 548 struct sh_eth_private *mdp = netdev_priv(ndev); 549 int ret; 550 551 sh_eth_write(ndev, EDSR_ENALL, EDSR); 552 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 553 554 ret = sh_eth_check_soft_reset(ndev); 555 if (ret) 556 return ret; 557 558 /* Table Init */ 559 sh_eth_write(ndev, 0, TDLAR); 560 sh_eth_write(ndev, 0, TDFAR); 561 sh_eth_write(ndev, 0, TDFXR); 562 sh_eth_write(ndev, 0, TDFFR); 563 sh_eth_write(ndev, 0, RDLAR); 564 sh_eth_write(ndev, 0, RDFAR); 565 sh_eth_write(ndev, 0, RDFXR); 566 sh_eth_write(ndev, 0, RDFFR); 567 568 /* Reset HW CRC register */ 569 if (mdp->cd->hw_checksum) 570 sh_eth_write(ndev, 0, CSMR); 571 572 /* Select MII mode */ 573 if (mdp->cd->select_mii) 574 sh_eth_select_mii(ndev); 575 576 return ret; 577 } 578 579 static void sh_eth_set_rate_gether(struct net_device *ndev) 580 { 581 struct sh_eth_private *mdp = netdev_priv(ndev); 582 583 switch (mdp->speed) { 584 case 10: /* 10BASE */ 585 sh_eth_write(ndev, GECMR_10, GECMR); 586 break; 587 case 100:/* 100BASE */ 588 sh_eth_write(ndev, GECMR_100, GECMR); 589 break; 590 case 1000: /* 1000BASE */ 591 sh_eth_write(ndev, GECMR_1000, GECMR); 592 break; 593 } 594 } 595 596 #ifdef CONFIG_OF 597 /* R7S72100 */ 598 static struct sh_eth_cpu_data r7s72100_data = { 599 .soft_reset = sh_eth_soft_reset_gether, 600 601 .chip_reset = sh_eth_chip_reset, 602 .set_duplex = sh_eth_set_duplex, 603 604 .register_type = SH_ETH_REG_FAST_RZ, 605 606 .edtrr_trns = EDTRR_TRNS_GETHER, 607 .ecsr_value = ECSR_ICD, 608 .ecsipr_value = ECSIPR_ICDIP, 609 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 610 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 611 EESIPR_ECIIP | 612 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 613 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 614 EESIPR_RMAFIP | EESIPR_RRFIP | 615 EESIPR_RTLFIP | EESIPR_RTSFIP | 616 EESIPR_PREIP | EESIPR_CERFIP, 617 618 .tx_check = EESR_TC1 | EESR_FTC, 619 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 620 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 621 EESR_TDE, 622 .fdr_value = 0x0000070f, 623 624 .no_psr = 1, 625 .apr = 1, 626 .mpr = 1, 627 .tpauser = 1, 628 .hw_swap = 1, 629 .rpadir = 1, 630 .no_trimd = 1, 631 .no_ade = 1, 632 .xdfar_rw = 1, 633 .hw_checksum = 1, 634 .tsu = 1, 635 .no_tx_cntrs = 1, 636 }; 637 638 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 639 { 640 sh_eth_chip_reset(ndev); 641 642 sh_eth_select_mii(ndev); 643 } 644 645 /* R8A7740 */ 646 static struct sh_eth_cpu_data r8a7740_data = { 647 .soft_reset = sh_eth_soft_reset_gether, 648 649 .chip_reset = sh_eth_chip_reset_r8a7740, 650 .set_duplex = sh_eth_set_duplex, 651 .set_rate = sh_eth_set_rate_gether, 652 653 .register_type = SH_ETH_REG_GIGABIT, 654 655 .edtrr_trns = EDTRR_TRNS_GETHER, 656 .ecsr_value = ECSR_ICD | ECSR_MPD, 657 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 658 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 659 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 660 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 661 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 662 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 663 EESIPR_CEEFIP | EESIPR_CELFIP | 664 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 665 EESIPR_PREIP | EESIPR_CERFIP, 666 667 .tx_check = EESR_TC1 | EESR_FTC, 668 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 669 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 670 EESR_TDE, 671 .fdr_value = 0x0000070f, 672 673 .apr = 1, 674 .mpr = 1, 675 .tpauser = 1, 676 .bculr = 1, 677 .hw_swap = 1, 678 .rpadir = 1, 679 .no_trimd = 1, 680 .no_ade = 1, 681 .xdfar_rw = 1, 682 .hw_checksum = 1, 683 .tsu = 1, 684 .select_mii = 1, 685 .magic = 1, 686 .cexcr = 1, 687 }; 688 689 /* There is CPU dependent code */ 690 static void sh_eth_set_rate_rcar(struct net_device *ndev) 691 { 692 struct sh_eth_private *mdp = netdev_priv(ndev); 693 694 switch (mdp->speed) { 695 case 10: /* 10BASE */ 696 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 697 break; 698 case 100:/* 100BASE */ 699 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 700 break; 701 } 702 } 703 704 /* R-Car Gen1 */ 705 static struct sh_eth_cpu_data rcar_gen1_data = { 706 .soft_reset = sh_eth_soft_reset, 707 708 .set_duplex = sh_eth_set_duplex, 709 .set_rate = sh_eth_set_rate_rcar, 710 711 .register_type = SH_ETH_REG_FAST_RCAR, 712 713 .edtrr_trns = EDTRR_TRNS_ETHER, 714 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 715 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 716 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 717 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 718 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 719 EESIPR_RMAFIP | EESIPR_RRFIP | 720 EESIPR_RTLFIP | EESIPR_RTSFIP | 721 EESIPR_PREIP | EESIPR_CERFIP, 722 723 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 724 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 725 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 726 .fdr_value = 0x00000f0f, 727 728 .apr = 1, 729 .mpr = 1, 730 .tpauser = 1, 731 .hw_swap = 1, 732 .no_xdfar = 1, 733 }; 734 735 /* R-Car Gen2 and RZ/G1 */ 736 static struct sh_eth_cpu_data rcar_gen2_data = { 737 .soft_reset = sh_eth_soft_reset, 738 739 .set_duplex = sh_eth_set_duplex, 740 .set_rate = sh_eth_set_rate_rcar, 741 742 .register_type = SH_ETH_REG_FAST_RCAR, 743 744 .edtrr_trns = EDTRR_TRNS_ETHER, 745 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 746 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 747 ECSIPR_MPDIP, 748 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 749 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 750 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 751 EESIPR_RMAFIP | EESIPR_RRFIP | 752 EESIPR_RTLFIP | EESIPR_RTSFIP | 753 EESIPR_PREIP | EESIPR_CERFIP, 754 755 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 756 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 757 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 758 .fdr_value = 0x00000f0f, 759 760 .trscer_err_mask = DESC_I_RINT8, 761 762 .apr = 1, 763 .mpr = 1, 764 .tpauser = 1, 765 .hw_swap = 1, 766 .no_xdfar = 1, 767 .rmiimode = 1, 768 .magic = 1, 769 }; 770 771 /* R8A77980 */ 772 static struct sh_eth_cpu_data r8a77980_data = { 773 .soft_reset = sh_eth_soft_reset_gether, 774 775 .set_duplex = sh_eth_set_duplex, 776 .set_rate = sh_eth_set_rate_gether, 777 778 .register_type = SH_ETH_REG_GIGABIT, 779 780 .edtrr_trns = EDTRR_TRNS_GETHER, 781 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 782 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 783 ECSIPR_MPDIP, 784 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 785 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 786 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 787 EESIPR_RMAFIP | EESIPR_RRFIP | 788 EESIPR_RTLFIP | EESIPR_RTSFIP | 789 EESIPR_PREIP | EESIPR_CERFIP, 790 791 .tx_check = EESR_FTC | EESR_CD | EESR_TRO, 792 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 793 EESR_RFE | EESR_RDE | EESR_RFRMER | 794 EESR_TFE | EESR_TDE | EESR_ECI, 795 .fdr_value = 0x0000070f, 796 797 .apr = 1, 798 .mpr = 1, 799 .tpauser = 1, 800 .bculr = 1, 801 .hw_swap = 1, 802 .nbst = 1, 803 .rpadir = 1, 804 .no_trimd = 1, 805 .no_ade = 1, 806 .xdfar_rw = 1, 807 .hw_checksum = 1, 808 .select_mii = 1, 809 .magic = 1, 810 .cexcr = 1, 811 }; 812 #endif /* CONFIG_OF */ 813 814 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 815 { 816 struct sh_eth_private *mdp = netdev_priv(ndev); 817 818 switch (mdp->speed) { 819 case 10: /* 10BASE */ 820 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 821 break; 822 case 100:/* 100BASE */ 823 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 824 break; 825 } 826 } 827 828 /* SH7724 */ 829 static struct sh_eth_cpu_data sh7724_data = { 830 .soft_reset = sh_eth_soft_reset, 831 832 .set_duplex = sh_eth_set_duplex, 833 .set_rate = sh_eth_set_rate_sh7724, 834 835 .register_type = SH_ETH_REG_FAST_SH4, 836 837 .edtrr_trns = EDTRR_TRNS_ETHER, 838 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 839 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 840 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 841 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 842 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 843 EESIPR_RMAFIP | EESIPR_RRFIP | 844 EESIPR_RTLFIP | EESIPR_RTSFIP | 845 EESIPR_PREIP | EESIPR_CERFIP, 846 847 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 848 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 849 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 850 851 .apr = 1, 852 .mpr = 1, 853 .tpauser = 1, 854 .hw_swap = 1, 855 .rpadir = 1, 856 }; 857 858 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 859 { 860 struct sh_eth_private *mdp = netdev_priv(ndev); 861 862 switch (mdp->speed) { 863 case 10: /* 10BASE */ 864 sh_eth_write(ndev, 0, RTRATE); 865 break; 866 case 100:/* 100BASE */ 867 sh_eth_write(ndev, 1, RTRATE); 868 break; 869 } 870 } 871 872 /* SH7757 */ 873 static struct sh_eth_cpu_data sh7757_data = { 874 .soft_reset = sh_eth_soft_reset, 875 876 .set_duplex = sh_eth_set_duplex, 877 .set_rate = sh_eth_set_rate_sh7757, 878 879 .register_type = SH_ETH_REG_FAST_SH4, 880 881 .edtrr_trns = EDTRR_TRNS_ETHER, 882 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 883 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 884 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 885 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 886 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 887 EESIPR_CEEFIP | EESIPR_CELFIP | 888 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 889 EESIPR_PREIP | EESIPR_CERFIP, 890 891 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 892 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 893 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 894 895 .irq_flags = IRQF_SHARED, 896 .apr = 1, 897 .mpr = 1, 898 .tpauser = 1, 899 .hw_swap = 1, 900 .no_ade = 1, 901 .rpadir = 1, 902 .rtrate = 1, 903 .dual_port = 1, 904 }; 905 906 #define SH_GIGA_ETH_BASE 0xfee00000UL 907 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 908 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 909 static void sh_eth_chip_reset_giga(struct net_device *ndev) 910 { 911 u32 mahr[2], malr[2]; 912 int i; 913 914 /* save MAHR and MALR */ 915 for (i = 0; i < 2; i++) { 916 malr[i] = ioread32((void *)GIGA_MALR(i)); 917 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 918 } 919 920 sh_eth_chip_reset(ndev); 921 922 /* restore MAHR and MALR */ 923 for (i = 0; i < 2; i++) { 924 iowrite32(malr[i], (void *)GIGA_MALR(i)); 925 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 926 } 927 } 928 929 static void sh_eth_set_rate_giga(struct net_device *ndev) 930 { 931 struct sh_eth_private *mdp = netdev_priv(ndev); 932 933 switch (mdp->speed) { 934 case 10: /* 10BASE */ 935 sh_eth_write(ndev, 0x00000000, GECMR); 936 break; 937 case 100:/* 100BASE */ 938 sh_eth_write(ndev, 0x00000010, GECMR); 939 break; 940 case 1000: /* 1000BASE */ 941 sh_eth_write(ndev, 0x00000020, GECMR); 942 break; 943 } 944 } 945 946 /* SH7757(GETHERC) */ 947 static struct sh_eth_cpu_data sh7757_data_giga = { 948 .soft_reset = sh_eth_soft_reset_gether, 949 950 .chip_reset = sh_eth_chip_reset_giga, 951 .set_duplex = sh_eth_set_duplex, 952 .set_rate = sh_eth_set_rate_giga, 953 954 .register_type = SH_ETH_REG_GIGABIT, 955 956 .edtrr_trns = EDTRR_TRNS_GETHER, 957 .ecsr_value = ECSR_ICD | ECSR_MPD, 958 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 959 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 960 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 961 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 962 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 963 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 964 EESIPR_CEEFIP | EESIPR_CELFIP | 965 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 966 EESIPR_PREIP | EESIPR_CERFIP, 967 968 .tx_check = EESR_TC1 | EESR_FTC, 969 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 970 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 971 EESR_TDE, 972 .fdr_value = 0x0000072f, 973 974 .irq_flags = IRQF_SHARED, 975 .apr = 1, 976 .mpr = 1, 977 .tpauser = 1, 978 .bculr = 1, 979 .hw_swap = 1, 980 .rpadir = 1, 981 .no_trimd = 1, 982 .no_ade = 1, 983 .xdfar_rw = 1, 984 .tsu = 1, 985 .cexcr = 1, 986 .dual_port = 1, 987 }; 988 989 /* SH7734 */ 990 static struct sh_eth_cpu_data sh7734_data = { 991 .soft_reset = sh_eth_soft_reset_gether, 992 993 .chip_reset = sh_eth_chip_reset, 994 .set_duplex = sh_eth_set_duplex, 995 .set_rate = sh_eth_set_rate_gether, 996 997 .register_type = SH_ETH_REG_GIGABIT, 998 999 .edtrr_trns = EDTRR_TRNS_GETHER, 1000 .ecsr_value = ECSR_ICD | ECSR_MPD, 1001 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 1002 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1003 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1004 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1005 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1006 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1007 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1008 EESIPR_PREIP | EESIPR_CERFIP, 1009 1010 .tx_check = EESR_TC1 | EESR_FTC, 1011 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1012 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 1013 EESR_TDE, 1014 1015 .apr = 1, 1016 .mpr = 1, 1017 .tpauser = 1, 1018 .bculr = 1, 1019 .hw_swap = 1, 1020 .no_trimd = 1, 1021 .no_ade = 1, 1022 .xdfar_rw = 1, 1023 .tsu = 1, 1024 .hw_checksum = 1, 1025 .select_mii = 1, 1026 .magic = 1, 1027 .cexcr = 1, 1028 }; 1029 1030 /* SH7763 */ 1031 static struct sh_eth_cpu_data sh7763_data = { 1032 .soft_reset = sh_eth_soft_reset_gether, 1033 1034 .chip_reset = sh_eth_chip_reset, 1035 .set_duplex = sh_eth_set_duplex, 1036 .set_rate = sh_eth_set_rate_gether, 1037 1038 .register_type = SH_ETH_REG_GIGABIT, 1039 1040 .edtrr_trns = EDTRR_TRNS_GETHER, 1041 .ecsr_value = ECSR_ICD | ECSR_MPD, 1042 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 1043 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1044 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1045 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1046 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1047 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1048 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1049 EESIPR_PREIP | EESIPR_CERFIP, 1050 1051 .tx_check = EESR_TC1 | EESR_FTC, 1052 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1053 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 1054 1055 .apr = 1, 1056 .mpr = 1, 1057 .tpauser = 1, 1058 .bculr = 1, 1059 .hw_swap = 1, 1060 .no_trimd = 1, 1061 .no_ade = 1, 1062 .xdfar_rw = 1, 1063 .tsu = 1, 1064 .irq_flags = IRQF_SHARED, 1065 .magic = 1, 1066 .cexcr = 1, 1067 .dual_port = 1, 1068 }; 1069 1070 static struct sh_eth_cpu_data sh7619_data = { 1071 .soft_reset = sh_eth_soft_reset, 1072 1073 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1074 1075 .edtrr_trns = EDTRR_TRNS_ETHER, 1076 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1077 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1078 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1079 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1080 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1081 EESIPR_CEEFIP | EESIPR_CELFIP | 1082 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1083 EESIPR_PREIP | EESIPR_CERFIP, 1084 1085 .apr = 1, 1086 .mpr = 1, 1087 .tpauser = 1, 1088 .hw_swap = 1, 1089 }; 1090 1091 static struct sh_eth_cpu_data sh771x_data = { 1092 .soft_reset = sh_eth_soft_reset, 1093 1094 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1095 1096 .edtrr_trns = EDTRR_TRNS_ETHER, 1097 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1098 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1099 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1100 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1101 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1102 EESIPR_CEEFIP | EESIPR_CELFIP | 1103 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1104 EESIPR_PREIP | EESIPR_CERFIP, 1105 .tsu = 1, 1106 .dual_port = 1, 1107 }; 1108 1109 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 1110 { 1111 if (!cd->ecsr_value) 1112 cd->ecsr_value = DEFAULT_ECSR_INIT; 1113 1114 if (!cd->ecsipr_value) 1115 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 1116 1117 if (!cd->fcftr_value) 1118 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 1119 DEFAULT_FIFO_F_D_RFD; 1120 1121 if (!cd->fdr_value) 1122 cd->fdr_value = DEFAULT_FDR_INIT; 1123 1124 if (!cd->tx_check) 1125 cd->tx_check = DEFAULT_TX_CHECK; 1126 1127 if (!cd->eesr_err_check) 1128 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 1129 1130 if (!cd->trscer_err_mask) 1131 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 1132 } 1133 1134 static void sh_eth_set_receive_align(struct sk_buff *skb) 1135 { 1136 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1137 1138 if (reserve) 1139 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1140 } 1141 1142 /* Program the hardware MAC address from dev->dev_addr. */ 1143 static void update_mac_address(struct net_device *ndev) 1144 { 1145 sh_eth_write(ndev, 1146 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1147 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1148 sh_eth_write(ndev, 1149 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1150 } 1151 1152 /* Get MAC address from SuperH MAC address register 1153 * 1154 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1155 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1156 * When you want use this device, you must set MAC address in bootloader. 1157 * 1158 */ 1159 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1160 { 1161 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1162 memcpy(ndev->dev_addr, mac, ETH_ALEN); 1163 } else { 1164 u32 mahr = sh_eth_read(ndev, MAHR); 1165 u32 malr = sh_eth_read(ndev, MALR); 1166 1167 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 1168 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 1169 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 1170 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 1171 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 1172 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 1173 } 1174 } 1175 1176 struct bb_info { 1177 void (*set_gate)(void *addr); 1178 struct mdiobb_ctrl ctrl; 1179 void *addr; 1180 }; 1181 1182 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1183 { 1184 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1185 u32 pir; 1186 1187 if (bitbang->set_gate) 1188 bitbang->set_gate(bitbang->addr); 1189 1190 pir = ioread32(bitbang->addr); 1191 if (set) 1192 pir |= mask; 1193 else 1194 pir &= ~mask; 1195 iowrite32(pir, bitbang->addr); 1196 } 1197 1198 /* Data I/O pin control */ 1199 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1200 { 1201 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1202 } 1203 1204 /* Set bit data*/ 1205 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1206 { 1207 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1208 } 1209 1210 /* Get bit data*/ 1211 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1212 { 1213 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1214 1215 if (bitbang->set_gate) 1216 bitbang->set_gate(bitbang->addr); 1217 1218 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1219 } 1220 1221 /* MDC pin control */ 1222 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1223 { 1224 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1225 } 1226 1227 /* mdio bus control struct */ 1228 static struct mdiobb_ops bb_ops = { 1229 .owner = THIS_MODULE, 1230 .set_mdc = sh_mdc_ctrl, 1231 .set_mdio_dir = sh_mmd_ctrl, 1232 .set_mdio_data = sh_set_mdio, 1233 .get_mdio_data = sh_get_mdio, 1234 }; 1235 1236 /* free Tx skb function */ 1237 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) 1238 { 1239 struct sh_eth_private *mdp = netdev_priv(ndev); 1240 struct sh_eth_txdesc *txdesc; 1241 int free_num = 0; 1242 int entry; 1243 bool sent; 1244 1245 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1246 entry = mdp->dirty_tx % mdp->num_tx_ring; 1247 txdesc = &mdp->tx_ring[entry]; 1248 sent = !(txdesc->status & cpu_to_le32(TD_TACT)); 1249 if (sent_only && !sent) 1250 break; 1251 /* TACT bit must be checked before all the following reads */ 1252 dma_rmb(); 1253 netif_info(mdp, tx_done, ndev, 1254 "tx entry %d status 0x%08x\n", 1255 entry, le32_to_cpu(txdesc->status)); 1256 /* Free the original skb. */ 1257 if (mdp->tx_skbuff[entry]) { 1258 dma_unmap_single(&mdp->pdev->dev, 1259 le32_to_cpu(txdesc->addr), 1260 le32_to_cpu(txdesc->len) >> 16, 1261 DMA_TO_DEVICE); 1262 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1263 mdp->tx_skbuff[entry] = NULL; 1264 free_num++; 1265 } 1266 txdesc->status = cpu_to_le32(TD_TFP); 1267 if (entry >= mdp->num_tx_ring - 1) 1268 txdesc->status |= cpu_to_le32(TD_TDLE); 1269 1270 if (sent) { 1271 ndev->stats.tx_packets++; 1272 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1273 } 1274 } 1275 return free_num; 1276 } 1277 1278 /* free skb and descriptor buffer */ 1279 static void sh_eth_ring_free(struct net_device *ndev) 1280 { 1281 struct sh_eth_private *mdp = netdev_priv(ndev); 1282 int ringsize, i; 1283 1284 if (mdp->rx_ring) { 1285 for (i = 0; i < mdp->num_rx_ring; i++) { 1286 if (mdp->rx_skbuff[i]) { 1287 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; 1288 1289 dma_unmap_single(&mdp->pdev->dev, 1290 le32_to_cpu(rxdesc->addr), 1291 ALIGN(mdp->rx_buf_sz, 32), 1292 DMA_FROM_DEVICE); 1293 } 1294 } 1295 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1296 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, 1297 mdp->rx_desc_dma); 1298 mdp->rx_ring = NULL; 1299 } 1300 1301 /* Free Rx skb ringbuffer */ 1302 if (mdp->rx_skbuff) { 1303 for (i = 0; i < mdp->num_rx_ring; i++) 1304 dev_kfree_skb(mdp->rx_skbuff[i]); 1305 } 1306 kfree(mdp->rx_skbuff); 1307 mdp->rx_skbuff = NULL; 1308 1309 if (mdp->tx_ring) { 1310 sh_eth_tx_free(ndev, false); 1311 1312 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1313 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, 1314 mdp->tx_desc_dma); 1315 mdp->tx_ring = NULL; 1316 } 1317 1318 /* Free Tx skb ringbuffer */ 1319 kfree(mdp->tx_skbuff); 1320 mdp->tx_skbuff = NULL; 1321 } 1322 1323 /* format skb and descriptor buffer */ 1324 static void sh_eth_ring_format(struct net_device *ndev) 1325 { 1326 struct sh_eth_private *mdp = netdev_priv(ndev); 1327 int i; 1328 struct sk_buff *skb; 1329 struct sh_eth_rxdesc *rxdesc = NULL; 1330 struct sh_eth_txdesc *txdesc = NULL; 1331 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1332 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1333 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1334 dma_addr_t dma_addr; 1335 u32 buf_len; 1336 1337 mdp->cur_rx = 0; 1338 mdp->cur_tx = 0; 1339 mdp->dirty_rx = 0; 1340 mdp->dirty_tx = 0; 1341 1342 memset(mdp->rx_ring, 0, rx_ringsize); 1343 1344 /* build Rx ring buffer */ 1345 for (i = 0; i < mdp->num_rx_ring; i++) { 1346 /* skb */ 1347 mdp->rx_skbuff[i] = NULL; 1348 skb = netdev_alloc_skb(ndev, skbuff_size); 1349 if (skb == NULL) 1350 break; 1351 sh_eth_set_receive_align(skb); 1352 1353 /* The size of the buffer is a multiple of 32 bytes. */ 1354 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1355 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, 1356 DMA_FROM_DEVICE); 1357 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1358 kfree_skb(skb); 1359 break; 1360 } 1361 mdp->rx_skbuff[i] = skb; 1362 1363 /* RX descriptor */ 1364 rxdesc = &mdp->rx_ring[i]; 1365 rxdesc->len = cpu_to_le32(buf_len << 16); 1366 rxdesc->addr = cpu_to_le32(dma_addr); 1367 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1368 1369 /* Rx descriptor address set */ 1370 if (i == 0) { 1371 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1372 if (mdp->cd->xdfar_rw) 1373 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1374 } 1375 } 1376 1377 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1378 1379 /* Mark the last entry as wrapping the ring. */ 1380 if (rxdesc) 1381 rxdesc->status |= cpu_to_le32(RD_RDLE); 1382 1383 memset(mdp->tx_ring, 0, tx_ringsize); 1384 1385 /* build Tx ring buffer */ 1386 for (i = 0; i < mdp->num_tx_ring; i++) { 1387 mdp->tx_skbuff[i] = NULL; 1388 txdesc = &mdp->tx_ring[i]; 1389 txdesc->status = cpu_to_le32(TD_TFP); 1390 txdesc->len = cpu_to_le32(0); 1391 if (i == 0) { 1392 /* Tx descriptor address set */ 1393 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1394 if (mdp->cd->xdfar_rw) 1395 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1396 } 1397 } 1398 1399 txdesc->status |= cpu_to_le32(TD_TDLE); 1400 } 1401 1402 /* Get skb and descriptor buffer */ 1403 static int sh_eth_ring_init(struct net_device *ndev) 1404 { 1405 struct sh_eth_private *mdp = netdev_priv(ndev); 1406 int rx_ringsize, tx_ringsize; 1407 1408 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1409 * card needs room to do 8 byte alignment, +2 so we can reserve 1410 * the first 2 bytes, and +16 gets room for the status word from the 1411 * card. 1412 */ 1413 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1414 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1415 if (mdp->cd->rpadir) 1416 mdp->rx_buf_sz += NET_IP_ALIGN; 1417 1418 /* Allocate RX and TX skb rings */ 1419 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1420 GFP_KERNEL); 1421 if (!mdp->rx_skbuff) 1422 return -ENOMEM; 1423 1424 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1425 GFP_KERNEL); 1426 if (!mdp->tx_skbuff) 1427 goto ring_free; 1428 1429 /* Allocate all Rx descriptors. */ 1430 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1431 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, 1432 &mdp->rx_desc_dma, GFP_KERNEL); 1433 if (!mdp->rx_ring) 1434 goto ring_free; 1435 1436 mdp->dirty_rx = 0; 1437 1438 /* Allocate all Tx descriptors. */ 1439 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1440 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, 1441 &mdp->tx_desc_dma, GFP_KERNEL); 1442 if (!mdp->tx_ring) 1443 goto ring_free; 1444 return 0; 1445 1446 ring_free: 1447 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1448 sh_eth_ring_free(ndev); 1449 1450 return -ENOMEM; 1451 } 1452 1453 static int sh_eth_dev_init(struct net_device *ndev) 1454 { 1455 struct sh_eth_private *mdp = netdev_priv(ndev); 1456 int ret; 1457 1458 /* Soft Reset */ 1459 ret = mdp->cd->soft_reset(ndev); 1460 if (ret) 1461 return ret; 1462 1463 if (mdp->cd->rmiimode) 1464 sh_eth_write(ndev, 0x1, RMIIMODE); 1465 1466 /* Descriptor format */ 1467 sh_eth_ring_format(ndev); 1468 if (mdp->cd->rpadir) 1469 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR); 1470 1471 /* all sh_eth int mask */ 1472 sh_eth_write(ndev, 0, EESIPR); 1473 1474 #if defined(__LITTLE_ENDIAN) 1475 if (mdp->cd->hw_swap) 1476 sh_eth_write(ndev, EDMR_EL, EDMR); 1477 else 1478 #endif 1479 sh_eth_write(ndev, 0, EDMR); 1480 1481 /* FIFO size set */ 1482 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1483 sh_eth_write(ndev, 0, TFTR); 1484 1485 /* Frame recv control (enable multiple-packets per rx irq) */ 1486 sh_eth_write(ndev, RMCR_RNC, RMCR); 1487 1488 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1489 1490 /* DMA transfer burst mode */ 1491 if (mdp->cd->nbst) 1492 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST); 1493 1494 /* Burst cycle count upper-limit */ 1495 if (mdp->cd->bculr) 1496 sh_eth_write(ndev, 0x800, BCULR); 1497 1498 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1499 1500 if (!mdp->cd->no_trimd) 1501 sh_eth_write(ndev, 0, TRIMD); 1502 1503 /* Recv frame limit set register */ 1504 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1505 RFLR); 1506 1507 sh_eth_modify(ndev, EESR, 0, 0); 1508 mdp->irq_enabled = true; 1509 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1510 1511 /* PAUSE Prohibition */ 1512 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1513 ECMR_TE | ECMR_RE, ECMR); 1514 1515 if (mdp->cd->set_rate) 1516 mdp->cd->set_rate(ndev); 1517 1518 /* E-MAC Status Register clear */ 1519 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1520 1521 /* E-MAC Interrupt Enable register */ 1522 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1523 1524 /* Set MAC address */ 1525 update_mac_address(ndev); 1526 1527 /* mask reset */ 1528 if (mdp->cd->apr) 1529 sh_eth_write(ndev, 1, APR); 1530 if (mdp->cd->mpr) 1531 sh_eth_write(ndev, 1, MPR); 1532 if (mdp->cd->tpauser) 1533 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1534 1535 /* Setting the Rx mode will start the Rx process. */ 1536 sh_eth_write(ndev, EDRRR_R, EDRRR); 1537 1538 return ret; 1539 } 1540 1541 static void sh_eth_dev_exit(struct net_device *ndev) 1542 { 1543 struct sh_eth_private *mdp = netdev_priv(ndev); 1544 int i; 1545 1546 /* Deactivate all TX descriptors, so DMA should stop at next 1547 * packet boundary if it's currently running 1548 */ 1549 for (i = 0; i < mdp->num_tx_ring; i++) 1550 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1551 1552 /* Disable TX FIFO egress to MAC */ 1553 sh_eth_rcv_snd_disable(ndev); 1554 1555 /* Stop RX DMA at next packet boundary */ 1556 sh_eth_write(ndev, 0, EDRRR); 1557 1558 /* Aside from TX DMA, we can't tell when the hardware is 1559 * really stopped, so we need to reset to make sure. 1560 * Before doing that, wait for long enough to *probably* 1561 * finish transmitting the last packet and poll stats. 1562 */ 1563 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1564 sh_eth_get_stats(ndev); 1565 mdp->cd->soft_reset(ndev); 1566 1567 /* Set MAC address again */ 1568 update_mac_address(ndev); 1569 } 1570 1571 /* Packet receive function */ 1572 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1573 { 1574 struct sh_eth_private *mdp = netdev_priv(ndev); 1575 struct sh_eth_rxdesc *rxdesc; 1576 1577 int entry = mdp->cur_rx % mdp->num_rx_ring; 1578 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1579 int limit; 1580 struct sk_buff *skb; 1581 u32 desc_status; 1582 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1583 dma_addr_t dma_addr; 1584 u16 pkt_len; 1585 u32 buf_len; 1586 1587 boguscnt = min(boguscnt, *quota); 1588 limit = boguscnt; 1589 rxdesc = &mdp->rx_ring[entry]; 1590 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1591 /* RACT bit must be checked before all the following reads */ 1592 dma_rmb(); 1593 desc_status = le32_to_cpu(rxdesc->status); 1594 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1595 1596 if (--boguscnt < 0) 1597 break; 1598 1599 netif_info(mdp, rx_status, ndev, 1600 "rx entry %d status 0x%08x len %d\n", 1601 entry, desc_status, pkt_len); 1602 1603 if (!(desc_status & RDFEND)) 1604 ndev->stats.rx_length_errors++; 1605 1606 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1607 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1608 * bit 0. However, in case of the R8A7740 and R7S72100 1609 * the RFS bits are from bit 25 to bit 16. So, the 1610 * driver needs right shifting by 16. 1611 */ 1612 if (mdp->cd->hw_checksum) 1613 desc_status >>= 16; 1614 1615 skb = mdp->rx_skbuff[entry]; 1616 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1617 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1618 ndev->stats.rx_errors++; 1619 if (desc_status & RD_RFS1) 1620 ndev->stats.rx_crc_errors++; 1621 if (desc_status & RD_RFS2) 1622 ndev->stats.rx_frame_errors++; 1623 if (desc_status & RD_RFS3) 1624 ndev->stats.rx_length_errors++; 1625 if (desc_status & RD_RFS4) 1626 ndev->stats.rx_length_errors++; 1627 if (desc_status & RD_RFS6) 1628 ndev->stats.rx_missed_errors++; 1629 if (desc_status & RD_RFS10) 1630 ndev->stats.rx_over_errors++; 1631 } else if (skb) { 1632 dma_addr = le32_to_cpu(rxdesc->addr); 1633 if (!mdp->cd->hw_swap) 1634 sh_eth_soft_swap( 1635 phys_to_virt(ALIGN(dma_addr, 4)), 1636 pkt_len + 2); 1637 mdp->rx_skbuff[entry] = NULL; 1638 if (mdp->cd->rpadir) 1639 skb_reserve(skb, NET_IP_ALIGN); 1640 dma_unmap_single(&mdp->pdev->dev, dma_addr, 1641 ALIGN(mdp->rx_buf_sz, 32), 1642 DMA_FROM_DEVICE); 1643 skb_put(skb, pkt_len); 1644 skb->protocol = eth_type_trans(skb, ndev); 1645 netif_receive_skb(skb); 1646 ndev->stats.rx_packets++; 1647 ndev->stats.rx_bytes += pkt_len; 1648 if (desc_status & RD_RFS8) 1649 ndev->stats.multicast++; 1650 } 1651 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1652 rxdesc = &mdp->rx_ring[entry]; 1653 } 1654 1655 /* Refill the Rx ring buffers. */ 1656 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1657 entry = mdp->dirty_rx % mdp->num_rx_ring; 1658 rxdesc = &mdp->rx_ring[entry]; 1659 /* The size of the buffer is 32 byte boundary. */ 1660 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1661 rxdesc->len = cpu_to_le32(buf_len << 16); 1662 1663 if (mdp->rx_skbuff[entry] == NULL) { 1664 skb = netdev_alloc_skb(ndev, skbuff_size); 1665 if (skb == NULL) 1666 break; /* Better luck next round. */ 1667 sh_eth_set_receive_align(skb); 1668 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, 1669 buf_len, DMA_FROM_DEVICE); 1670 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1671 kfree_skb(skb); 1672 break; 1673 } 1674 mdp->rx_skbuff[entry] = skb; 1675 1676 skb_checksum_none_assert(skb); 1677 rxdesc->addr = cpu_to_le32(dma_addr); 1678 } 1679 dma_wmb(); /* RACT bit must be set after all the above writes */ 1680 if (entry >= mdp->num_rx_ring - 1) 1681 rxdesc->status |= 1682 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1683 else 1684 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1685 } 1686 1687 /* Restart Rx engine if stopped. */ 1688 /* If we don't need to check status, don't. -KDU */ 1689 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1690 /* fix the values for the next receiving if RDE is set */ 1691 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) { 1692 u32 count = (sh_eth_read(ndev, RDFAR) - 1693 sh_eth_read(ndev, RDLAR)) >> 4; 1694 1695 mdp->cur_rx = count; 1696 mdp->dirty_rx = count; 1697 } 1698 sh_eth_write(ndev, EDRRR_R, EDRRR); 1699 } 1700 1701 *quota -= limit - boguscnt - 1; 1702 1703 return *quota <= 0; 1704 } 1705 1706 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1707 { 1708 /* disable tx and rx */ 1709 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1710 } 1711 1712 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1713 { 1714 /* enable tx and rx */ 1715 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1716 } 1717 1718 /* E-MAC interrupt handler */ 1719 static void sh_eth_emac_interrupt(struct net_device *ndev) 1720 { 1721 struct sh_eth_private *mdp = netdev_priv(ndev); 1722 u32 felic_stat; 1723 u32 link_stat; 1724 1725 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1726 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1727 if (felic_stat & ECSR_ICD) 1728 ndev->stats.tx_carrier_errors++; 1729 if (felic_stat & ECSR_MPD) 1730 pm_wakeup_event(&mdp->pdev->dev, 0); 1731 if (felic_stat & ECSR_LCHNG) { 1732 /* Link Changed */ 1733 if (mdp->cd->no_psr || mdp->no_ether_link) 1734 return; 1735 link_stat = sh_eth_read(ndev, PSR); 1736 if (mdp->ether_link_active_low) 1737 link_stat = ~link_stat; 1738 if (!(link_stat & PHY_ST_LINK)) { 1739 sh_eth_rcv_snd_disable(ndev); 1740 } else { 1741 /* Link Up */ 1742 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1743 /* clear int */ 1744 sh_eth_modify(ndev, ECSR, 0, 0); 1745 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1746 /* enable tx and rx */ 1747 sh_eth_rcv_snd_enable(ndev); 1748 } 1749 } 1750 } 1751 1752 /* error control function */ 1753 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1754 { 1755 struct sh_eth_private *mdp = netdev_priv(ndev); 1756 u32 mask; 1757 1758 if (intr_status & EESR_TWB) { 1759 /* Unused write back interrupt */ 1760 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1761 ndev->stats.tx_aborted_errors++; 1762 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1763 } 1764 } 1765 1766 if (intr_status & EESR_RABT) { 1767 /* Receive Abort int */ 1768 if (intr_status & EESR_RFRMER) { 1769 /* Receive Frame Overflow int */ 1770 ndev->stats.rx_frame_errors++; 1771 } 1772 } 1773 1774 if (intr_status & EESR_TDE) { 1775 /* Transmit Descriptor Empty int */ 1776 ndev->stats.tx_fifo_errors++; 1777 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1778 } 1779 1780 if (intr_status & EESR_TFE) { 1781 /* FIFO under flow */ 1782 ndev->stats.tx_fifo_errors++; 1783 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1784 } 1785 1786 if (intr_status & EESR_RDE) { 1787 /* Receive Descriptor Empty int */ 1788 ndev->stats.rx_over_errors++; 1789 } 1790 1791 if (intr_status & EESR_RFE) { 1792 /* Receive FIFO Overflow int */ 1793 ndev->stats.rx_fifo_errors++; 1794 } 1795 1796 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1797 /* Address Error */ 1798 ndev->stats.tx_fifo_errors++; 1799 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1800 } 1801 1802 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1803 if (mdp->cd->no_ade) 1804 mask &= ~EESR_ADE; 1805 if (intr_status & mask) { 1806 /* Tx error */ 1807 u32 edtrr = sh_eth_read(ndev, EDTRR); 1808 1809 /* dmesg */ 1810 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1811 intr_status, mdp->cur_tx, mdp->dirty_tx, 1812 (u32)ndev->state, edtrr); 1813 /* dirty buffer free */ 1814 sh_eth_tx_free(ndev, true); 1815 1816 /* SH7712 BUG */ 1817 if (edtrr ^ mdp->cd->edtrr_trns) { 1818 /* tx dma start */ 1819 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 1820 } 1821 /* wakeup */ 1822 netif_wake_queue(ndev); 1823 } 1824 } 1825 1826 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1827 { 1828 struct net_device *ndev = netdev; 1829 struct sh_eth_private *mdp = netdev_priv(ndev); 1830 struct sh_eth_cpu_data *cd = mdp->cd; 1831 irqreturn_t ret = IRQ_NONE; 1832 u32 intr_status, intr_enable; 1833 1834 spin_lock(&mdp->lock); 1835 1836 /* Get interrupt status */ 1837 intr_status = sh_eth_read(ndev, EESR); 1838 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1839 * enabled since it's the one that comes thru regardless of the mask, 1840 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1841 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1842 * bit... 1843 */ 1844 intr_enable = sh_eth_read(ndev, EESIPR); 1845 intr_status &= intr_enable | EESIPR_ECIIP; 1846 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1847 cd->eesr_err_check)) 1848 ret = IRQ_HANDLED; 1849 else 1850 goto out; 1851 1852 if (unlikely(!mdp->irq_enabled)) { 1853 sh_eth_write(ndev, 0, EESIPR); 1854 goto out; 1855 } 1856 1857 if (intr_status & EESR_RX_CHECK) { 1858 if (napi_schedule_prep(&mdp->napi)) { 1859 /* Mask Rx interrupts */ 1860 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1861 EESIPR); 1862 __napi_schedule(&mdp->napi); 1863 } else { 1864 netdev_warn(ndev, 1865 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1866 intr_status, intr_enable); 1867 } 1868 } 1869 1870 /* Tx Check */ 1871 if (intr_status & cd->tx_check) { 1872 /* Clear Tx interrupts */ 1873 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1874 1875 sh_eth_tx_free(ndev, true); 1876 netif_wake_queue(ndev); 1877 } 1878 1879 /* E-MAC interrupt */ 1880 if (intr_status & EESR_ECI) 1881 sh_eth_emac_interrupt(ndev); 1882 1883 if (intr_status & cd->eesr_err_check) { 1884 /* Clear error interrupts */ 1885 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1886 1887 sh_eth_error(ndev, intr_status); 1888 } 1889 1890 out: 1891 spin_unlock(&mdp->lock); 1892 1893 return ret; 1894 } 1895 1896 static int sh_eth_poll(struct napi_struct *napi, int budget) 1897 { 1898 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1899 napi); 1900 struct net_device *ndev = napi->dev; 1901 int quota = budget; 1902 u32 intr_status; 1903 1904 for (;;) { 1905 intr_status = sh_eth_read(ndev, EESR); 1906 if (!(intr_status & EESR_RX_CHECK)) 1907 break; 1908 /* Clear Rx interrupts */ 1909 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1910 1911 if (sh_eth_rx(ndev, intr_status, "a)) 1912 goto out; 1913 } 1914 1915 napi_complete(napi); 1916 1917 /* Reenable Rx interrupts */ 1918 if (mdp->irq_enabled) 1919 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1920 out: 1921 return budget - quota; 1922 } 1923 1924 /* PHY state control function */ 1925 static void sh_eth_adjust_link(struct net_device *ndev) 1926 { 1927 struct sh_eth_private *mdp = netdev_priv(ndev); 1928 struct phy_device *phydev = ndev->phydev; 1929 unsigned long flags; 1930 int new_state = 0; 1931 1932 spin_lock_irqsave(&mdp->lock, flags); 1933 1934 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1935 if (mdp->cd->no_psr || mdp->no_ether_link) 1936 sh_eth_rcv_snd_disable(ndev); 1937 1938 if (phydev->link) { 1939 if (phydev->duplex != mdp->duplex) { 1940 new_state = 1; 1941 mdp->duplex = phydev->duplex; 1942 if (mdp->cd->set_duplex) 1943 mdp->cd->set_duplex(ndev); 1944 } 1945 1946 if (phydev->speed != mdp->speed) { 1947 new_state = 1; 1948 mdp->speed = phydev->speed; 1949 if (mdp->cd->set_rate) 1950 mdp->cd->set_rate(ndev); 1951 } 1952 if (!mdp->link) { 1953 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 1954 new_state = 1; 1955 mdp->link = phydev->link; 1956 } 1957 } else if (mdp->link) { 1958 new_state = 1; 1959 mdp->link = 0; 1960 mdp->speed = 0; 1961 mdp->duplex = -1; 1962 } 1963 1964 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1965 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link) 1966 sh_eth_rcv_snd_enable(ndev); 1967 1968 mmiowb(); 1969 spin_unlock_irqrestore(&mdp->lock, flags); 1970 1971 if (new_state && netif_msg_link(mdp)) 1972 phy_print_status(phydev); 1973 } 1974 1975 /* PHY init function */ 1976 static int sh_eth_phy_init(struct net_device *ndev) 1977 { 1978 struct device_node *np = ndev->dev.parent->of_node; 1979 struct sh_eth_private *mdp = netdev_priv(ndev); 1980 struct phy_device *phydev; 1981 1982 mdp->link = 0; 1983 mdp->speed = 0; 1984 mdp->duplex = -1; 1985 1986 /* Try connect to PHY */ 1987 if (np) { 1988 struct device_node *pn; 1989 1990 pn = of_parse_phandle(np, "phy-handle", 0); 1991 phydev = of_phy_connect(ndev, pn, 1992 sh_eth_adjust_link, 0, 1993 mdp->phy_interface); 1994 1995 of_node_put(pn); 1996 if (!phydev) 1997 phydev = ERR_PTR(-ENOENT); 1998 } else { 1999 char phy_id[MII_BUS_ID_SIZE + 3]; 2000 2001 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 2002 mdp->mii_bus->id, mdp->phy_id); 2003 2004 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 2005 mdp->phy_interface); 2006 } 2007 2008 if (IS_ERR(phydev)) { 2009 netdev_err(ndev, "failed to connect PHY\n"); 2010 return PTR_ERR(phydev); 2011 } 2012 2013 /* mask with MAC supported features */ 2014 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) { 2015 int err = phy_set_max_speed(phydev, SPEED_100); 2016 if (err) { 2017 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n"); 2018 phy_disconnect(phydev); 2019 return err; 2020 } 2021 } 2022 2023 phy_attached_info(phydev); 2024 2025 return 0; 2026 } 2027 2028 /* PHY control start function */ 2029 static int sh_eth_phy_start(struct net_device *ndev) 2030 { 2031 int ret; 2032 2033 ret = sh_eth_phy_init(ndev); 2034 if (ret) 2035 return ret; 2036 2037 phy_start(ndev->phydev); 2038 2039 return 0; 2040 } 2041 2042 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 2043 * version must be bumped as well. Just adding registers up to that 2044 * limit is fine, as long as the existing register indices don't 2045 * change. 2046 */ 2047 #define SH_ETH_REG_DUMP_VERSION 1 2048 #define SH_ETH_REG_DUMP_MAX_REGS 256 2049 2050 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 2051 { 2052 struct sh_eth_private *mdp = netdev_priv(ndev); 2053 struct sh_eth_cpu_data *cd = mdp->cd; 2054 u32 *valid_map; 2055 size_t len; 2056 2057 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 2058 2059 /* Dump starts with a bitmap that tells ethtool which 2060 * registers are defined for this chip. 2061 */ 2062 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 2063 if (buf) { 2064 valid_map = buf; 2065 buf += len; 2066 } else { 2067 valid_map = NULL; 2068 } 2069 2070 /* Add a register to the dump, if it has a defined offset. 2071 * This automatically skips most undefined registers, but for 2072 * some it is also necessary to check a capability flag in 2073 * struct sh_eth_cpu_data. 2074 */ 2075 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 2076 #define add_reg_from(reg, read_expr) do { \ 2077 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2078 if (buf) { \ 2079 mark_reg_valid(reg); \ 2080 *buf++ = read_expr; \ 2081 } \ 2082 ++len; \ 2083 } \ 2084 } while (0) 2085 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2086 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2087 2088 add_reg(EDSR); 2089 add_reg(EDMR); 2090 add_reg(EDTRR); 2091 add_reg(EDRRR); 2092 add_reg(EESR); 2093 add_reg(EESIPR); 2094 add_reg(TDLAR); 2095 add_reg(TDFAR); 2096 add_reg(TDFXR); 2097 add_reg(TDFFR); 2098 add_reg(RDLAR); 2099 add_reg(RDFAR); 2100 add_reg(RDFXR); 2101 add_reg(RDFFR); 2102 add_reg(TRSCER); 2103 add_reg(RMFCR); 2104 add_reg(TFTR); 2105 add_reg(FDR); 2106 add_reg(RMCR); 2107 add_reg(TFUCR); 2108 add_reg(RFOCR); 2109 if (cd->rmiimode) 2110 add_reg(RMIIMODE); 2111 add_reg(FCFTR); 2112 if (cd->rpadir) 2113 add_reg(RPADIR); 2114 if (!cd->no_trimd) 2115 add_reg(TRIMD); 2116 add_reg(ECMR); 2117 add_reg(ECSR); 2118 add_reg(ECSIPR); 2119 add_reg(PIR); 2120 if (!cd->no_psr) 2121 add_reg(PSR); 2122 add_reg(RDMLR); 2123 add_reg(RFLR); 2124 add_reg(IPGR); 2125 if (cd->apr) 2126 add_reg(APR); 2127 if (cd->mpr) 2128 add_reg(MPR); 2129 add_reg(RFCR); 2130 add_reg(RFCF); 2131 if (cd->tpauser) 2132 add_reg(TPAUSER); 2133 add_reg(TPAUSECR); 2134 add_reg(GECMR); 2135 if (cd->bculr) 2136 add_reg(BCULR); 2137 add_reg(MAHR); 2138 add_reg(MALR); 2139 add_reg(TROCR); 2140 add_reg(CDCR); 2141 add_reg(LCCR); 2142 add_reg(CNDCR); 2143 add_reg(CEFCR); 2144 add_reg(FRECR); 2145 add_reg(TSFRCR); 2146 add_reg(TLFRCR); 2147 add_reg(CERCR); 2148 add_reg(CEECR); 2149 add_reg(MAFCR); 2150 if (cd->rtrate) 2151 add_reg(RTRATE); 2152 if (cd->hw_checksum) 2153 add_reg(CSMR); 2154 if (cd->select_mii) 2155 add_reg(RMII_MII); 2156 if (cd->tsu) { 2157 add_tsu_reg(ARSTR); 2158 add_tsu_reg(TSU_CTRST); 2159 add_tsu_reg(TSU_FWEN0); 2160 add_tsu_reg(TSU_FWEN1); 2161 add_tsu_reg(TSU_FCM); 2162 add_tsu_reg(TSU_BSYSL0); 2163 add_tsu_reg(TSU_BSYSL1); 2164 add_tsu_reg(TSU_PRISL0); 2165 add_tsu_reg(TSU_PRISL1); 2166 add_tsu_reg(TSU_FWSL0); 2167 add_tsu_reg(TSU_FWSL1); 2168 add_tsu_reg(TSU_FWSLC); 2169 add_tsu_reg(TSU_QTAGM0); 2170 add_tsu_reg(TSU_QTAGM1); 2171 add_tsu_reg(TSU_FWSR); 2172 add_tsu_reg(TSU_FWINMK); 2173 add_tsu_reg(TSU_ADQT0); 2174 add_tsu_reg(TSU_ADQT1); 2175 add_tsu_reg(TSU_VTAG0); 2176 add_tsu_reg(TSU_VTAG1); 2177 add_tsu_reg(TSU_ADSBSY); 2178 add_tsu_reg(TSU_TEN); 2179 add_tsu_reg(TSU_POST1); 2180 add_tsu_reg(TSU_POST2); 2181 add_tsu_reg(TSU_POST3); 2182 add_tsu_reg(TSU_POST4); 2183 /* This is the start of a table, not just a single register. */ 2184 if (buf) { 2185 unsigned int i; 2186 2187 mark_reg_valid(TSU_ADRH0); 2188 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2189 *buf++ = ioread32(mdp->tsu_addr + 2190 mdp->reg_offset[TSU_ADRH0] + 2191 i * 4); 2192 } 2193 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2194 } 2195 2196 #undef mark_reg_valid 2197 #undef add_reg_from 2198 #undef add_reg 2199 #undef add_tsu_reg 2200 2201 return len * 4; 2202 } 2203 2204 static int sh_eth_get_regs_len(struct net_device *ndev) 2205 { 2206 return __sh_eth_get_regs(ndev, NULL); 2207 } 2208 2209 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2210 void *buf) 2211 { 2212 struct sh_eth_private *mdp = netdev_priv(ndev); 2213 2214 regs->version = SH_ETH_REG_DUMP_VERSION; 2215 2216 pm_runtime_get_sync(&mdp->pdev->dev); 2217 __sh_eth_get_regs(ndev, buf); 2218 pm_runtime_put_sync(&mdp->pdev->dev); 2219 } 2220 2221 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2222 { 2223 struct sh_eth_private *mdp = netdev_priv(ndev); 2224 return mdp->msg_enable; 2225 } 2226 2227 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2228 { 2229 struct sh_eth_private *mdp = netdev_priv(ndev); 2230 mdp->msg_enable = value; 2231 } 2232 2233 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2234 "rx_current", "tx_current", 2235 "rx_dirty", "tx_dirty", 2236 }; 2237 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2238 2239 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2240 { 2241 switch (sset) { 2242 case ETH_SS_STATS: 2243 return SH_ETH_STATS_LEN; 2244 default: 2245 return -EOPNOTSUPP; 2246 } 2247 } 2248 2249 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2250 struct ethtool_stats *stats, u64 *data) 2251 { 2252 struct sh_eth_private *mdp = netdev_priv(ndev); 2253 int i = 0; 2254 2255 /* device-specific stats */ 2256 data[i++] = mdp->cur_rx; 2257 data[i++] = mdp->cur_tx; 2258 data[i++] = mdp->dirty_rx; 2259 data[i++] = mdp->dirty_tx; 2260 } 2261 2262 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2263 { 2264 switch (stringset) { 2265 case ETH_SS_STATS: 2266 memcpy(data, *sh_eth_gstrings_stats, 2267 sizeof(sh_eth_gstrings_stats)); 2268 break; 2269 } 2270 } 2271 2272 static void sh_eth_get_ringparam(struct net_device *ndev, 2273 struct ethtool_ringparam *ring) 2274 { 2275 struct sh_eth_private *mdp = netdev_priv(ndev); 2276 2277 ring->rx_max_pending = RX_RING_MAX; 2278 ring->tx_max_pending = TX_RING_MAX; 2279 ring->rx_pending = mdp->num_rx_ring; 2280 ring->tx_pending = mdp->num_tx_ring; 2281 } 2282 2283 static int sh_eth_set_ringparam(struct net_device *ndev, 2284 struct ethtool_ringparam *ring) 2285 { 2286 struct sh_eth_private *mdp = netdev_priv(ndev); 2287 int ret; 2288 2289 if (ring->tx_pending > TX_RING_MAX || 2290 ring->rx_pending > RX_RING_MAX || 2291 ring->tx_pending < TX_RING_MIN || 2292 ring->rx_pending < RX_RING_MIN) 2293 return -EINVAL; 2294 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2295 return -EINVAL; 2296 2297 if (netif_running(ndev)) { 2298 netif_device_detach(ndev); 2299 netif_tx_disable(ndev); 2300 2301 /* Serialise with the interrupt handler and NAPI, then 2302 * disable interrupts. We have to clear the 2303 * irq_enabled flag first to ensure that interrupts 2304 * won't be re-enabled. 2305 */ 2306 mdp->irq_enabled = false; 2307 synchronize_irq(ndev->irq); 2308 napi_synchronize(&mdp->napi); 2309 sh_eth_write(ndev, 0x0000, EESIPR); 2310 2311 sh_eth_dev_exit(ndev); 2312 2313 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2314 sh_eth_ring_free(ndev); 2315 } 2316 2317 /* Set new parameters */ 2318 mdp->num_rx_ring = ring->rx_pending; 2319 mdp->num_tx_ring = ring->tx_pending; 2320 2321 if (netif_running(ndev)) { 2322 ret = sh_eth_ring_init(ndev); 2323 if (ret < 0) { 2324 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2325 __func__); 2326 return ret; 2327 } 2328 ret = sh_eth_dev_init(ndev); 2329 if (ret < 0) { 2330 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2331 __func__); 2332 return ret; 2333 } 2334 2335 netif_device_attach(ndev); 2336 } 2337 2338 return 0; 2339 } 2340 2341 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2342 { 2343 struct sh_eth_private *mdp = netdev_priv(ndev); 2344 2345 wol->supported = 0; 2346 wol->wolopts = 0; 2347 2348 if (mdp->cd->magic) { 2349 wol->supported = WAKE_MAGIC; 2350 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2351 } 2352 } 2353 2354 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2355 { 2356 struct sh_eth_private *mdp = netdev_priv(ndev); 2357 2358 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC) 2359 return -EOPNOTSUPP; 2360 2361 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2362 2363 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2364 2365 return 0; 2366 } 2367 2368 static const struct ethtool_ops sh_eth_ethtool_ops = { 2369 .get_regs_len = sh_eth_get_regs_len, 2370 .get_regs = sh_eth_get_regs, 2371 .nway_reset = phy_ethtool_nway_reset, 2372 .get_msglevel = sh_eth_get_msglevel, 2373 .set_msglevel = sh_eth_set_msglevel, 2374 .get_link = ethtool_op_get_link, 2375 .get_strings = sh_eth_get_strings, 2376 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2377 .get_sset_count = sh_eth_get_sset_count, 2378 .get_ringparam = sh_eth_get_ringparam, 2379 .set_ringparam = sh_eth_set_ringparam, 2380 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2381 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2382 .get_wol = sh_eth_get_wol, 2383 .set_wol = sh_eth_set_wol, 2384 }; 2385 2386 /* network device open function */ 2387 static int sh_eth_open(struct net_device *ndev) 2388 { 2389 struct sh_eth_private *mdp = netdev_priv(ndev); 2390 int ret; 2391 2392 pm_runtime_get_sync(&mdp->pdev->dev); 2393 2394 napi_enable(&mdp->napi); 2395 2396 ret = request_irq(ndev->irq, sh_eth_interrupt, 2397 mdp->cd->irq_flags, ndev->name, ndev); 2398 if (ret) { 2399 netdev_err(ndev, "Can not assign IRQ number\n"); 2400 goto out_napi_off; 2401 } 2402 2403 /* Descriptor set */ 2404 ret = sh_eth_ring_init(ndev); 2405 if (ret) 2406 goto out_free_irq; 2407 2408 /* device init */ 2409 ret = sh_eth_dev_init(ndev); 2410 if (ret) 2411 goto out_free_irq; 2412 2413 /* PHY control start*/ 2414 ret = sh_eth_phy_start(ndev); 2415 if (ret) 2416 goto out_free_irq; 2417 2418 netif_start_queue(ndev); 2419 2420 mdp->is_opened = 1; 2421 2422 return ret; 2423 2424 out_free_irq: 2425 free_irq(ndev->irq, ndev); 2426 out_napi_off: 2427 napi_disable(&mdp->napi); 2428 pm_runtime_put_sync(&mdp->pdev->dev); 2429 return ret; 2430 } 2431 2432 /* Timeout function */ 2433 static void sh_eth_tx_timeout(struct net_device *ndev) 2434 { 2435 struct sh_eth_private *mdp = netdev_priv(ndev); 2436 struct sh_eth_rxdesc *rxdesc; 2437 int i; 2438 2439 netif_stop_queue(ndev); 2440 2441 netif_err(mdp, timer, ndev, 2442 "transmit timed out, status %8.8x, resetting...\n", 2443 sh_eth_read(ndev, EESR)); 2444 2445 /* tx_errors count up */ 2446 ndev->stats.tx_errors++; 2447 2448 /* Free all the skbuffs in the Rx queue. */ 2449 for (i = 0; i < mdp->num_rx_ring; i++) { 2450 rxdesc = &mdp->rx_ring[i]; 2451 rxdesc->status = cpu_to_le32(0); 2452 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2453 dev_kfree_skb(mdp->rx_skbuff[i]); 2454 mdp->rx_skbuff[i] = NULL; 2455 } 2456 for (i = 0; i < mdp->num_tx_ring; i++) { 2457 dev_kfree_skb(mdp->tx_skbuff[i]); 2458 mdp->tx_skbuff[i] = NULL; 2459 } 2460 2461 /* device init */ 2462 sh_eth_dev_init(ndev); 2463 2464 netif_start_queue(ndev); 2465 } 2466 2467 /* Packet transmit function */ 2468 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2469 { 2470 struct sh_eth_private *mdp = netdev_priv(ndev); 2471 struct sh_eth_txdesc *txdesc; 2472 dma_addr_t dma_addr; 2473 u32 entry; 2474 unsigned long flags; 2475 2476 spin_lock_irqsave(&mdp->lock, flags); 2477 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2478 if (!sh_eth_tx_free(ndev, true)) { 2479 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2480 netif_stop_queue(ndev); 2481 spin_unlock_irqrestore(&mdp->lock, flags); 2482 return NETDEV_TX_BUSY; 2483 } 2484 } 2485 spin_unlock_irqrestore(&mdp->lock, flags); 2486 2487 if (skb_put_padto(skb, ETH_ZLEN)) 2488 return NETDEV_TX_OK; 2489 2490 entry = mdp->cur_tx % mdp->num_tx_ring; 2491 mdp->tx_skbuff[entry] = skb; 2492 txdesc = &mdp->tx_ring[entry]; 2493 /* soft swap. */ 2494 if (!mdp->cd->hw_swap) 2495 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2496 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, 2497 DMA_TO_DEVICE); 2498 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 2499 kfree_skb(skb); 2500 return NETDEV_TX_OK; 2501 } 2502 txdesc->addr = cpu_to_le32(dma_addr); 2503 txdesc->len = cpu_to_le32(skb->len << 16); 2504 2505 dma_wmb(); /* TACT bit must be set after all the above writes */ 2506 if (entry >= mdp->num_tx_ring - 1) 2507 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2508 else 2509 txdesc->status |= cpu_to_le32(TD_TACT); 2510 2511 mdp->cur_tx++; 2512 2513 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns)) 2514 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 2515 2516 return NETDEV_TX_OK; 2517 } 2518 2519 /* The statistics registers have write-clear behaviour, which means we 2520 * will lose any increment between the read and write. We mitigate 2521 * this by only clearing when we read a non-zero value, so we will 2522 * never falsely report a total of zero. 2523 */ 2524 static void 2525 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2526 { 2527 u32 delta = sh_eth_read(ndev, reg); 2528 2529 if (delta) { 2530 *stat += delta; 2531 sh_eth_write(ndev, 0, reg); 2532 } 2533 } 2534 2535 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2536 { 2537 struct sh_eth_private *mdp = netdev_priv(ndev); 2538 2539 if (mdp->cd->no_tx_cntrs) 2540 return &ndev->stats; 2541 2542 if (!mdp->is_opened) 2543 return &ndev->stats; 2544 2545 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2546 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2547 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2548 2549 if (mdp->cd->cexcr) { 2550 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2551 CERCR); 2552 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2553 CEECR); 2554 } else { 2555 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2556 CNDCR); 2557 } 2558 2559 return &ndev->stats; 2560 } 2561 2562 /* device close function */ 2563 static int sh_eth_close(struct net_device *ndev) 2564 { 2565 struct sh_eth_private *mdp = netdev_priv(ndev); 2566 2567 netif_stop_queue(ndev); 2568 2569 /* Serialise with the interrupt handler and NAPI, then disable 2570 * interrupts. We have to clear the irq_enabled flag first to 2571 * ensure that interrupts won't be re-enabled. 2572 */ 2573 mdp->irq_enabled = false; 2574 synchronize_irq(ndev->irq); 2575 napi_disable(&mdp->napi); 2576 sh_eth_write(ndev, 0x0000, EESIPR); 2577 2578 sh_eth_dev_exit(ndev); 2579 2580 /* PHY Disconnect */ 2581 if (ndev->phydev) { 2582 phy_stop(ndev->phydev); 2583 phy_disconnect(ndev->phydev); 2584 } 2585 2586 free_irq(ndev->irq, ndev); 2587 2588 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2589 sh_eth_ring_free(ndev); 2590 2591 pm_runtime_put_sync(&mdp->pdev->dev); 2592 2593 mdp->is_opened = 0; 2594 2595 return 0; 2596 } 2597 2598 /* ioctl to device function */ 2599 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2600 { 2601 struct phy_device *phydev = ndev->phydev; 2602 2603 if (!netif_running(ndev)) 2604 return -EINVAL; 2605 2606 if (!phydev) 2607 return -ENODEV; 2608 2609 return phy_mii_ioctl(phydev, rq, cmd); 2610 } 2611 2612 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) 2613 { 2614 if (netif_running(ndev)) 2615 return -EBUSY; 2616 2617 ndev->mtu = new_mtu; 2618 netdev_update_features(ndev); 2619 2620 return 0; 2621 } 2622 2623 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2624 static u32 sh_eth_tsu_get_post_mask(int entry) 2625 { 2626 return 0x0f << (28 - ((entry % 8) * 4)); 2627 } 2628 2629 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2630 { 2631 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2632 } 2633 2634 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2635 int entry) 2636 { 2637 struct sh_eth_private *mdp = netdev_priv(ndev); 2638 int reg = TSU_POST1 + entry / 8; 2639 u32 tmp; 2640 2641 tmp = sh_eth_tsu_read(mdp, reg); 2642 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg); 2643 } 2644 2645 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2646 int entry) 2647 { 2648 struct sh_eth_private *mdp = netdev_priv(ndev); 2649 int reg = TSU_POST1 + entry / 8; 2650 u32 post_mask, ref_mask, tmp; 2651 2652 post_mask = sh_eth_tsu_get_post_mask(entry); 2653 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2654 2655 tmp = sh_eth_tsu_read(mdp, reg); 2656 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg); 2657 2658 /* If other port enables, the function returns "true" */ 2659 return tmp & ref_mask; 2660 } 2661 2662 static int sh_eth_tsu_busy(struct net_device *ndev) 2663 { 2664 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2665 struct sh_eth_private *mdp = netdev_priv(ndev); 2666 2667 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2668 udelay(10); 2669 timeout--; 2670 if (timeout <= 0) { 2671 netdev_err(ndev, "%s: timeout\n", __func__); 2672 return -ETIMEDOUT; 2673 } 2674 } 2675 2676 return 0; 2677 } 2678 2679 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset, 2680 const u8 *addr) 2681 { 2682 struct sh_eth_private *mdp = netdev_priv(ndev); 2683 u32 val; 2684 2685 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2686 iowrite32(val, mdp->tsu_addr + offset); 2687 if (sh_eth_tsu_busy(ndev) < 0) 2688 return -EBUSY; 2689 2690 val = addr[4] << 8 | addr[5]; 2691 iowrite32(val, mdp->tsu_addr + offset + 4); 2692 if (sh_eth_tsu_busy(ndev) < 0) 2693 return -EBUSY; 2694 2695 return 0; 2696 } 2697 2698 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr) 2699 { 2700 struct sh_eth_private *mdp = netdev_priv(ndev); 2701 u32 val; 2702 2703 val = ioread32(mdp->tsu_addr + offset); 2704 addr[0] = (val >> 24) & 0xff; 2705 addr[1] = (val >> 16) & 0xff; 2706 addr[2] = (val >> 8) & 0xff; 2707 addr[3] = val & 0xff; 2708 val = ioread32(mdp->tsu_addr + offset + 4); 2709 addr[4] = (val >> 8) & 0xff; 2710 addr[5] = val & 0xff; 2711 } 2712 2713 2714 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2715 { 2716 struct sh_eth_private *mdp = netdev_priv(ndev); 2717 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2718 int i; 2719 u8 c_addr[ETH_ALEN]; 2720 2721 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2722 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr); 2723 if (ether_addr_equal(addr, c_addr)) 2724 return i; 2725 } 2726 2727 return -ENOENT; 2728 } 2729 2730 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2731 { 2732 u8 blank[ETH_ALEN]; 2733 int entry; 2734 2735 memset(blank, 0, sizeof(blank)); 2736 entry = sh_eth_tsu_find_entry(ndev, blank); 2737 return (entry < 0) ? -ENOMEM : entry; 2738 } 2739 2740 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2741 int entry) 2742 { 2743 struct sh_eth_private *mdp = netdev_priv(ndev); 2744 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2745 int ret; 2746 u8 blank[ETH_ALEN]; 2747 2748 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2749 ~(1 << (31 - entry)), TSU_TEN); 2750 2751 memset(blank, 0, sizeof(blank)); 2752 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2753 if (ret < 0) 2754 return ret; 2755 return 0; 2756 } 2757 2758 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2759 { 2760 struct sh_eth_private *mdp = netdev_priv(ndev); 2761 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2762 int i, ret; 2763 2764 if (!mdp->cd->tsu) 2765 return 0; 2766 2767 i = sh_eth_tsu_find_entry(ndev, addr); 2768 if (i < 0) { 2769 /* No entry found, create one */ 2770 i = sh_eth_tsu_find_empty(ndev); 2771 if (i < 0) 2772 return -ENOMEM; 2773 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2774 if (ret < 0) 2775 return ret; 2776 2777 /* Enable the entry */ 2778 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2779 (1 << (31 - i)), TSU_TEN); 2780 } 2781 2782 /* Entry found or created, enable POST */ 2783 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2784 2785 return 0; 2786 } 2787 2788 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2789 { 2790 struct sh_eth_private *mdp = netdev_priv(ndev); 2791 int i, ret; 2792 2793 if (!mdp->cd->tsu) 2794 return 0; 2795 2796 i = sh_eth_tsu_find_entry(ndev, addr); 2797 if (i) { 2798 /* Entry found */ 2799 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2800 goto done; 2801 2802 /* Disable the entry if both ports was disabled */ 2803 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2804 if (ret < 0) 2805 return ret; 2806 } 2807 done: 2808 return 0; 2809 } 2810 2811 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2812 { 2813 struct sh_eth_private *mdp = netdev_priv(ndev); 2814 int i, ret; 2815 2816 if (!mdp->cd->tsu) 2817 return 0; 2818 2819 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2820 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2821 continue; 2822 2823 /* Disable the entry if both ports was disabled */ 2824 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2825 if (ret < 0) 2826 return ret; 2827 } 2828 2829 return 0; 2830 } 2831 2832 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2833 { 2834 struct sh_eth_private *mdp = netdev_priv(ndev); 2835 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2836 u8 addr[ETH_ALEN]; 2837 int i; 2838 2839 if (!mdp->cd->tsu) 2840 return; 2841 2842 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2843 sh_eth_tsu_read_entry(ndev, reg_offset, addr); 2844 if (is_multicast_ether_addr(addr)) 2845 sh_eth_tsu_del_entry(ndev, addr); 2846 } 2847 } 2848 2849 /* Update promiscuous flag and multicast filter */ 2850 static void sh_eth_set_rx_mode(struct net_device *ndev) 2851 { 2852 struct sh_eth_private *mdp = netdev_priv(ndev); 2853 u32 ecmr_bits; 2854 int mcast_all = 0; 2855 unsigned long flags; 2856 2857 spin_lock_irqsave(&mdp->lock, flags); 2858 /* Initial condition is MCT = 1, PRM = 0. 2859 * Depending on ndev->flags, set PRM or clear MCT 2860 */ 2861 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2862 if (mdp->cd->tsu) 2863 ecmr_bits |= ECMR_MCT; 2864 2865 if (!(ndev->flags & IFF_MULTICAST)) { 2866 sh_eth_tsu_purge_mcast(ndev); 2867 mcast_all = 1; 2868 } 2869 if (ndev->flags & IFF_ALLMULTI) { 2870 sh_eth_tsu_purge_mcast(ndev); 2871 ecmr_bits &= ~ECMR_MCT; 2872 mcast_all = 1; 2873 } 2874 2875 if (ndev->flags & IFF_PROMISC) { 2876 sh_eth_tsu_purge_all(ndev); 2877 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2878 } else if (mdp->cd->tsu) { 2879 struct netdev_hw_addr *ha; 2880 netdev_for_each_mc_addr(ha, ndev) { 2881 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2882 continue; 2883 2884 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2885 if (!mcast_all) { 2886 sh_eth_tsu_purge_mcast(ndev); 2887 ecmr_bits &= ~ECMR_MCT; 2888 mcast_all = 1; 2889 } 2890 } 2891 } 2892 } 2893 2894 /* update the ethernet mode */ 2895 sh_eth_write(ndev, ecmr_bits, ECMR); 2896 2897 spin_unlock_irqrestore(&mdp->lock, flags); 2898 } 2899 2900 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2901 { 2902 if (!mdp->port) 2903 return TSU_VTAG0; 2904 else 2905 return TSU_VTAG1; 2906 } 2907 2908 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2909 __be16 proto, u16 vid) 2910 { 2911 struct sh_eth_private *mdp = netdev_priv(ndev); 2912 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2913 2914 if (unlikely(!mdp->cd->tsu)) 2915 return -EPERM; 2916 2917 /* No filtering if vid = 0 */ 2918 if (!vid) 2919 return 0; 2920 2921 mdp->vlan_num_ids++; 2922 2923 /* The controller has one VLAN tag HW filter. So, if the filter is 2924 * already enabled, the driver disables it and the filte 2925 */ 2926 if (mdp->vlan_num_ids > 1) { 2927 /* disable VLAN filter */ 2928 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2929 return 0; 2930 } 2931 2932 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2933 vtag_reg_index); 2934 2935 return 0; 2936 } 2937 2938 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2939 __be16 proto, u16 vid) 2940 { 2941 struct sh_eth_private *mdp = netdev_priv(ndev); 2942 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2943 2944 if (unlikely(!mdp->cd->tsu)) 2945 return -EPERM; 2946 2947 /* No filtering if vid = 0 */ 2948 if (!vid) 2949 return 0; 2950 2951 mdp->vlan_num_ids--; 2952 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2953 2954 return 0; 2955 } 2956 2957 /* SuperH's TSU register init function */ 2958 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2959 { 2960 if (!mdp->cd->dual_port) { 2961 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2962 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 2963 TSU_FWSLC); /* Enable POST registers */ 2964 return; 2965 } 2966 2967 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2968 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2969 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2970 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2971 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2972 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2973 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2974 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2975 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2976 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2977 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2978 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2979 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2980 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2981 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2982 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2983 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2984 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2985 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2986 } 2987 2988 /* MDIO bus release function */ 2989 static int sh_mdio_release(struct sh_eth_private *mdp) 2990 { 2991 /* unregister mdio bus */ 2992 mdiobus_unregister(mdp->mii_bus); 2993 2994 /* free bitbang info */ 2995 free_mdio_bitbang(mdp->mii_bus); 2996 2997 return 0; 2998 } 2999 3000 /* MDIO bus init function */ 3001 static int sh_mdio_init(struct sh_eth_private *mdp, 3002 struct sh_eth_plat_data *pd) 3003 { 3004 int ret; 3005 struct bb_info *bitbang; 3006 struct platform_device *pdev = mdp->pdev; 3007 struct device *dev = &mdp->pdev->dev; 3008 3009 /* create bit control struct for PHY */ 3010 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 3011 if (!bitbang) 3012 return -ENOMEM; 3013 3014 /* bitbang init */ 3015 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 3016 bitbang->set_gate = pd->set_mdio_gate; 3017 bitbang->ctrl.ops = &bb_ops; 3018 3019 /* MII controller setting */ 3020 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 3021 if (!mdp->mii_bus) 3022 return -ENOMEM; 3023 3024 /* Hook up MII support for ethtool */ 3025 mdp->mii_bus->name = "sh_mii"; 3026 mdp->mii_bus->parent = dev; 3027 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 3028 pdev->name, pdev->id); 3029 3030 /* register MDIO bus */ 3031 if (pd->phy_irq > 0) 3032 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 3033 3034 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 3035 if (ret) 3036 goto out_free_bus; 3037 3038 return 0; 3039 3040 out_free_bus: 3041 free_mdio_bitbang(mdp->mii_bus); 3042 return ret; 3043 } 3044 3045 static const u16 *sh_eth_get_register_offset(int register_type) 3046 { 3047 const u16 *reg_offset = NULL; 3048 3049 switch (register_type) { 3050 case SH_ETH_REG_GIGABIT: 3051 reg_offset = sh_eth_offset_gigabit; 3052 break; 3053 case SH_ETH_REG_FAST_RZ: 3054 reg_offset = sh_eth_offset_fast_rz; 3055 break; 3056 case SH_ETH_REG_FAST_RCAR: 3057 reg_offset = sh_eth_offset_fast_rcar; 3058 break; 3059 case SH_ETH_REG_FAST_SH4: 3060 reg_offset = sh_eth_offset_fast_sh4; 3061 break; 3062 case SH_ETH_REG_FAST_SH3_SH2: 3063 reg_offset = sh_eth_offset_fast_sh3_sh2; 3064 break; 3065 } 3066 3067 return reg_offset; 3068 } 3069 3070 static const struct net_device_ops sh_eth_netdev_ops = { 3071 .ndo_open = sh_eth_open, 3072 .ndo_stop = sh_eth_close, 3073 .ndo_start_xmit = sh_eth_start_xmit, 3074 .ndo_get_stats = sh_eth_get_stats, 3075 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3076 .ndo_tx_timeout = sh_eth_tx_timeout, 3077 .ndo_do_ioctl = sh_eth_do_ioctl, 3078 .ndo_change_mtu = sh_eth_change_mtu, 3079 .ndo_validate_addr = eth_validate_addr, 3080 .ndo_set_mac_address = eth_mac_addr, 3081 }; 3082 3083 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3084 .ndo_open = sh_eth_open, 3085 .ndo_stop = sh_eth_close, 3086 .ndo_start_xmit = sh_eth_start_xmit, 3087 .ndo_get_stats = sh_eth_get_stats, 3088 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3089 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3090 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3091 .ndo_tx_timeout = sh_eth_tx_timeout, 3092 .ndo_do_ioctl = sh_eth_do_ioctl, 3093 .ndo_change_mtu = sh_eth_change_mtu, 3094 .ndo_validate_addr = eth_validate_addr, 3095 .ndo_set_mac_address = eth_mac_addr, 3096 }; 3097 3098 #ifdef CONFIG_OF 3099 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3100 { 3101 struct device_node *np = dev->of_node; 3102 struct sh_eth_plat_data *pdata; 3103 const char *mac_addr; 3104 3105 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3106 if (!pdata) 3107 return NULL; 3108 3109 pdata->phy_interface = of_get_phy_mode(np); 3110 3111 mac_addr = of_get_mac_address(np); 3112 if (mac_addr) 3113 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 3114 3115 pdata->no_ether_link = 3116 of_property_read_bool(np, "renesas,no-ether-link"); 3117 pdata->ether_link_active_low = 3118 of_property_read_bool(np, "renesas,ether-link-active-low"); 3119 3120 return pdata; 3121 } 3122 3123 static const struct of_device_id sh_eth_match_table[] = { 3124 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3125 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data }, 3126 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data }, 3127 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data }, 3128 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data }, 3129 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data }, 3130 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data }, 3131 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data }, 3132 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data }, 3133 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data }, 3134 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3135 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data }, 3136 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data }, 3137 { } 3138 }; 3139 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3140 #else 3141 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3142 { 3143 return NULL; 3144 } 3145 #endif 3146 3147 static int sh_eth_drv_probe(struct platform_device *pdev) 3148 { 3149 struct resource *res; 3150 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3151 const struct platform_device_id *id = platform_get_device_id(pdev); 3152 struct sh_eth_private *mdp; 3153 struct net_device *ndev; 3154 int ret; 3155 3156 /* get base addr */ 3157 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3158 3159 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3160 if (!ndev) 3161 return -ENOMEM; 3162 3163 pm_runtime_enable(&pdev->dev); 3164 pm_runtime_get_sync(&pdev->dev); 3165 3166 ret = platform_get_irq(pdev, 0); 3167 if (ret < 0) 3168 goto out_release; 3169 ndev->irq = ret; 3170 3171 SET_NETDEV_DEV(ndev, &pdev->dev); 3172 3173 mdp = netdev_priv(ndev); 3174 mdp->num_tx_ring = TX_RING_SIZE; 3175 mdp->num_rx_ring = RX_RING_SIZE; 3176 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3177 if (IS_ERR(mdp->addr)) { 3178 ret = PTR_ERR(mdp->addr); 3179 goto out_release; 3180 } 3181 3182 ndev->base_addr = res->start; 3183 3184 spin_lock_init(&mdp->lock); 3185 mdp->pdev = pdev; 3186 3187 if (pdev->dev.of_node) 3188 pd = sh_eth_parse_dt(&pdev->dev); 3189 if (!pd) { 3190 dev_err(&pdev->dev, "no platform data\n"); 3191 ret = -EINVAL; 3192 goto out_release; 3193 } 3194 3195 /* get PHY ID */ 3196 mdp->phy_id = pd->phy; 3197 mdp->phy_interface = pd->phy_interface; 3198 mdp->no_ether_link = pd->no_ether_link; 3199 mdp->ether_link_active_low = pd->ether_link_active_low; 3200 3201 /* set cpu data */ 3202 if (id) 3203 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3204 else 3205 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3206 3207 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3208 if (!mdp->reg_offset) { 3209 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3210 mdp->cd->register_type); 3211 ret = -EINVAL; 3212 goto out_release; 3213 } 3214 sh_eth_set_default_cpu_data(mdp->cd); 3215 3216 /* User's manual states max MTU should be 2048 but due to the 3217 * alignment calculations in sh_eth_ring_init() the practical 3218 * MTU is a bit less. Maybe this can be optimized some more. 3219 */ 3220 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3221 ndev->min_mtu = ETH_MIN_MTU; 3222 3223 /* set function */ 3224 if (mdp->cd->tsu) 3225 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3226 else 3227 ndev->netdev_ops = &sh_eth_netdev_ops; 3228 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3229 ndev->watchdog_timeo = TX_TIMEOUT; 3230 3231 /* debug message level */ 3232 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3233 3234 /* read and set MAC address */ 3235 read_mac_address(ndev, pd->mac_addr); 3236 if (!is_valid_ether_addr(ndev->dev_addr)) { 3237 dev_warn(&pdev->dev, 3238 "no valid MAC address supplied, using a random one.\n"); 3239 eth_hw_addr_random(ndev); 3240 } 3241 3242 if (mdp->cd->tsu) { 3243 int port = pdev->id < 0 ? 0 : pdev->id % 2; 3244 struct resource *rtsu; 3245 3246 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3247 if (!rtsu) { 3248 dev_err(&pdev->dev, "no TSU resource\n"); 3249 ret = -ENODEV; 3250 goto out_release; 3251 } 3252 /* We can only request the TSU region for the first port 3253 * of the two sharing this TSU for the probe to succeed... 3254 */ 3255 if (port == 0 && 3256 !devm_request_mem_region(&pdev->dev, rtsu->start, 3257 resource_size(rtsu), 3258 dev_name(&pdev->dev))) { 3259 dev_err(&pdev->dev, "can't request TSU resource.\n"); 3260 ret = -EBUSY; 3261 goto out_release; 3262 } 3263 /* ioremap the TSU registers */ 3264 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, 3265 resource_size(rtsu)); 3266 if (!mdp->tsu_addr) { 3267 dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); 3268 ret = -ENOMEM; 3269 goto out_release; 3270 } 3271 mdp->port = port; 3272 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 3273 3274 /* Need to init only the first port of the two sharing a TSU */ 3275 if (port == 0) { 3276 if (mdp->cd->chip_reset) 3277 mdp->cd->chip_reset(ndev); 3278 3279 /* TSU init (Init only)*/ 3280 sh_eth_tsu_init(mdp); 3281 } 3282 } 3283 3284 if (mdp->cd->rmiimode) 3285 sh_eth_write(ndev, 0x1, RMIIMODE); 3286 3287 /* MDIO bus init */ 3288 ret = sh_mdio_init(mdp, pd); 3289 if (ret) { 3290 if (ret != -EPROBE_DEFER) 3291 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret); 3292 goto out_release; 3293 } 3294 3295 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3296 3297 /* network device register */ 3298 ret = register_netdev(ndev); 3299 if (ret) 3300 goto out_napi_del; 3301 3302 if (mdp->cd->magic) 3303 device_set_wakeup_capable(&pdev->dev, 1); 3304 3305 /* print device information */ 3306 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3307 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3308 3309 pm_runtime_put(&pdev->dev); 3310 platform_set_drvdata(pdev, ndev); 3311 3312 return ret; 3313 3314 out_napi_del: 3315 netif_napi_del(&mdp->napi); 3316 sh_mdio_release(mdp); 3317 3318 out_release: 3319 /* net_dev free */ 3320 free_netdev(ndev); 3321 3322 pm_runtime_put(&pdev->dev); 3323 pm_runtime_disable(&pdev->dev); 3324 return ret; 3325 } 3326 3327 static int sh_eth_drv_remove(struct platform_device *pdev) 3328 { 3329 struct net_device *ndev = platform_get_drvdata(pdev); 3330 struct sh_eth_private *mdp = netdev_priv(ndev); 3331 3332 unregister_netdev(ndev); 3333 netif_napi_del(&mdp->napi); 3334 sh_mdio_release(mdp); 3335 pm_runtime_disable(&pdev->dev); 3336 free_netdev(ndev); 3337 3338 return 0; 3339 } 3340 3341 #ifdef CONFIG_PM 3342 #ifdef CONFIG_PM_SLEEP 3343 static int sh_eth_wol_setup(struct net_device *ndev) 3344 { 3345 struct sh_eth_private *mdp = netdev_priv(ndev); 3346 3347 /* Only allow ECI interrupts */ 3348 synchronize_irq(ndev->irq); 3349 napi_disable(&mdp->napi); 3350 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3351 3352 /* Enable MagicPacket */ 3353 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3354 3355 return enable_irq_wake(ndev->irq); 3356 } 3357 3358 static int sh_eth_wol_restore(struct net_device *ndev) 3359 { 3360 struct sh_eth_private *mdp = netdev_priv(ndev); 3361 int ret; 3362 3363 napi_enable(&mdp->napi); 3364 3365 /* Disable MagicPacket */ 3366 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3367 3368 /* The device needs to be reset to restore MagicPacket logic 3369 * for next wakeup. If we close and open the device it will 3370 * both be reset and all registers restored. This is what 3371 * happens during suspend and resume without WoL enabled. 3372 */ 3373 ret = sh_eth_close(ndev); 3374 if (ret < 0) 3375 return ret; 3376 ret = sh_eth_open(ndev); 3377 if (ret < 0) 3378 return ret; 3379 3380 return disable_irq_wake(ndev->irq); 3381 } 3382 3383 static int sh_eth_suspend(struct device *dev) 3384 { 3385 struct net_device *ndev = dev_get_drvdata(dev); 3386 struct sh_eth_private *mdp = netdev_priv(ndev); 3387 int ret = 0; 3388 3389 if (!netif_running(ndev)) 3390 return 0; 3391 3392 netif_device_detach(ndev); 3393 3394 if (mdp->wol_enabled) 3395 ret = sh_eth_wol_setup(ndev); 3396 else 3397 ret = sh_eth_close(ndev); 3398 3399 return ret; 3400 } 3401 3402 static int sh_eth_resume(struct device *dev) 3403 { 3404 struct net_device *ndev = dev_get_drvdata(dev); 3405 struct sh_eth_private *mdp = netdev_priv(ndev); 3406 int ret = 0; 3407 3408 if (!netif_running(ndev)) 3409 return 0; 3410 3411 if (mdp->wol_enabled) 3412 ret = sh_eth_wol_restore(ndev); 3413 else 3414 ret = sh_eth_open(ndev); 3415 3416 if (ret < 0) 3417 return ret; 3418 3419 netif_device_attach(ndev); 3420 3421 return ret; 3422 } 3423 #endif 3424 3425 static int sh_eth_runtime_nop(struct device *dev) 3426 { 3427 /* Runtime PM callback shared between ->runtime_suspend() 3428 * and ->runtime_resume(). Simply returns success. 3429 * 3430 * This driver re-initializes all registers after 3431 * pm_runtime_get_sync() anyway so there is no need 3432 * to save and restore registers here. 3433 */ 3434 return 0; 3435 } 3436 3437 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3438 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3439 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3440 }; 3441 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3442 #else 3443 #define SH_ETH_PM_OPS NULL 3444 #endif 3445 3446 static const struct platform_device_id sh_eth_id_table[] = { 3447 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3448 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3449 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3450 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3451 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3452 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3453 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3454 { } 3455 }; 3456 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3457 3458 static struct platform_driver sh_eth_driver = { 3459 .probe = sh_eth_drv_probe, 3460 .remove = sh_eth_drv_remove, 3461 .id_table = sh_eth_id_table, 3462 .driver = { 3463 .name = CARDNAME, 3464 .pm = SH_ETH_PM_OPS, 3465 .of_match_table = of_match_ptr(sh_eth_match_table), 3466 }, 3467 }; 3468 3469 module_platform_driver(sh_eth_driver); 3470 3471 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3472 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3473 MODULE_LICENSE("GPL v2"); 3474