1 /* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2014 Renesas Electronics Corporation 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2014 Renesas Solutions Corp. 6 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 7 * Copyright (C) 2014 Codethink Limited 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 */ 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/etherdevice.h> 28 #include <linux/delay.h> 29 #include <linux/platform_device.h> 30 #include <linux/mdio-bitbang.h> 31 #include <linux/netdevice.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_net.h> 36 #include <linux/phy.h> 37 #include <linux/cache.h> 38 #include <linux/io.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/slab.h> 41 #include <linux/ethtool.h> 42 #include <linux/if_vlan.h> 43 #include <linux/sh_eth.h> 44 #include <linux/of_mdio.h> 45 46 #include "sh_eth.h" 47 48 #define SH_ETH_DEF_MSG_ENABLE \ 49 (NETIF_MSG_LINK | \ 50 NETIF_MSG_TIMER | \ 51 NETIF_MSG_RX_ERR| \ 52 NETIF_MSG_TX_ERR) 53 54 #define SH_ETH_OFFSET_INVALID ((u16)~0) 55 56 #define SH_ETH_OFFSET_DEFAULTS \ 57 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 58 59 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 60 SH_ETH_OFFSET_DEFAULTS, 61 62 [EDSR] = 0x0000, 63 [EDMR] = 0x0400, 64 [EDTRR] = 0x0408, 65 [EDRRR] = 0x0410, 66 [EESR] = 0x0428, 67 [EESIPR] = 0x0430, 68 [TDLAR] = 0x0010, 69 [TDFAR] = 0x0014, 70 [TDFXR] = 0x0018, 71 [TDFFR] = 0x001c, 72 [RDLAR] = 0x0030, 73 [RDFAR] = 0x0034, 74 [RDFXR] = 0x0038, 75 [RDFFR] = 0x003c, 76 [TRSCER] = 0x0438, 77 [RMFCR] = 0x0440, 78 [TFTR] = 0x0448, 79 [FDR] = 0x0450, 80 [RMCR] = 0x0458, 81 [RPADIR] = 0x0460, 82 [FCFTR] = 0x0468, 83 [CSMR] = 0x04E4, 84 85 [ECMR] = 0x0500, 86 [ECSR] = 0x0510, 87 [ECSIPR] = 0x0518, 88 [PIR] = 0x0520, 89 [PSR] = 0x0528, 90 [PIPR] = 0x052c, 91 [RFLR] = 0x0508, 92 [APR] = 0x0554, 93 [MPR] = 0x0558, 94 [PFTCR] = 0x055c, 95 [PFRCR] = 0x0560, 96 [TPAUSER] = 0x0564, 97 [GECMR] = 0x05b0, 98 [BCULR] = 0x05b4, 99 [MAHR] = 0x05c0, 100 [MALR] = 0x05c8, 101 [TROCR] = 0x0700, 102 [CDCR] = 0x0708, 103 [LCCR] = 0x0710, 104 [CEFCR] = 0x0740, 105 [FRECR] = 0x0748, 106 [TSFRCR] = 0x0750, 107 [TLFRCR] = 0x0758, 108 [RFCR] = 0x0760, 109 [CERCR] = 0x0768, 110 [CEECR] = 0x0770, 111 [MAFCR] = 0x0778, 112 [RMII_MII] = 0x0790, 113 114 [ARSTR] = 0x0000, 115 [TSU_CTRST] = 0x0004, 116 [TSU_FWEN0] = 0x0010, 117 [TSU_FWEN1] = 0x0014, 118 [TSU_FCM] = 0x0018, 119 [TSU_BSYSL0] = 0x0020, 120 [TSU_BSYSL1] = 0x0024, 121 [TSU_PRISL0] = 0x0028, 122 [TSU_PRISL1] = 0x002c, 123 [TSU_FWSL0] = 0x0030, 124 [TSU_FWSL1] = 0x0034, 125 [TSU_FWSLC] = 0x0038, 126 [TSU_QTAGM0] = 0x0040, 127 [TSU_QTAGM1] = 0x0044, 128 [TSU_FWSR] = 0x0050, 129 [TSU_FWINMK] = 0x0054, 130 [TSU_ADQT0] = 0x0048, 131 [TSU_ADQT1] = 0x004c, 132 [TSU_VTAG0] = 0x0058, 133 [TSU_VTAG1] = 0x005c, 134 [TSU_ADSBSY] = 0x0060, 135 [TSU_TEN] = 0x0064, 136 [TSU_POST1] = 0x0070, 137 [TSU_POST2] = 0x0074, 138 [TSU_POST3] = 0x0078, 139 [TSU_POST4] = 0x007c, 140 [TSU_ADRH0] = 0x0100, 141 142 [TXNLCR0] = 0x0080, 143 [TXALCR0] = 0x0084, 144 [RXNLCR0] = 0x0088, 145 [RXALCR0] = 0x008c, 146 [FWNLCR0] = 0x0090, 147 [FWALCR0] = 0x0094, 148 [TXNLCR1] = 0x00a0, 149 [TXALCR1] = 0x00a4, 150 [RXNLCR1] = 0x00a8, 151 [RXALCR1] = 0x00ac, 152 [FWNLCR1] = 0x00b0, 153 [FWALCR1] = 0x00b4, 154 }; 155 156 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 157 SH_ETH_OFFSET_DEFAULTS, 158 159 [EDSR] = 0x0000, 160 [EDMR] = 0x0400, 161 [EDTRR] = 0x0408, 162 [EDRRR] = 0x0410, 163 [EESR] = 0x0428, 164 [EESIPR] = 0x0430, 165 [TDLAR] = 0x0010, 166 [TDFAR] = 0x0014, 167 [TDFXR] = 0x0018, 168 [TDFFR] = 0x001c, 169 [RDLAR] = 0x0030, 170 [RDFAR] = 0x0034, 171 [RDFXR] = 0x0038, 172 [RDFFR] = 0x003c, 173 [TRSCER] = 0x0438, 174 [RMFCR] = 0x0440, 175 [TFTR] = 0x0448, 176 [FDR] = 0x0450, 177 [RMCR] = 0x0458, 178 [RPADIR] = 0x0460, 179 [FCFTR] = 0x0468, 180 [CSMR] = 0x04E4, 181 182 [ECMR] = 0x0500, 183 [RFLR] = 0x0508, 184 [ECSR] = 0x0510, 185 [ECSIPR] = 0x0518, 186 [PIR] = 0x0520, 187 [APR] = 0x0554, 188 [MPR] = 0x0558, 189 [PFTCR] = 0x055c, 190 [PFRCR] = 0x0560, 191 [TPAUSER] = 0x0564, 192 [MAHR] = 0x05c0, 193 [MALR] = 0x05c8, 194 [CEFCR] = 0x0740, 195 [FRECR] = 0x0748, 196 [TSFRCR] = 0x0750, 197 [TLFRCR] = 0x0758, 198 [RFCR] = 0x0760, 199 [MAFCR] = 0x0778, 200 201 [ARSTR] = 0x0000, 202 [TSU_CTRST] = 0x0004, 203 [TSU_FWSLC] = 0x0038, 204 [TSU_VTAG0] = 0x0058, 205 [TSU_ADSBSY] = 0x0060, 206 [TSU_TEN] = 0x0064, 207 [TSU_POST1] = 0x0070, 208 [TSU_POST2] = 0x0074, 209 [TSU_POST3] = 0x0078, 210 [TSU_POST4] = 0x007c, 211 [TSU_ADRH0] = 0x0100, 212 213 [TXNLCR0] = 0x0080, 214 [TXALCR0] = 0x0084, 215 [RXNLCR0] = 0x0088, 216 [RXALCR0] = 0x008C, 217 }; 218 219 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 220 SH_ETH_OFFSET_DEFAULTS, 221 222 [ECMR] = 0x0300, 223 [RFLR] = 0x0308, 224 [ECSR] = 0x0310, 225 [ECSIPR] = 0x0318, 226 [PIR] = 0x0320, 227 [PSR] = 0x0328, 228 [RDMLR] = 0x0340, 229 [IPGR] = 0x0350, 230 [APR] = 0x0354, 231 [MPR] = 0x0358, 232 [RFCF] = 0x0360, 233 [TPAUSER] = 0x0364, 234 [TPAUSECR] = 0x0368, 235 [MAHR] = 0x03c0, 236 [MALR] = 0x03c8, 237 [TROCR] = 0x03d0, 238 [CDCR] = 0x03d4, 239 [LCCR] = 0x03d8, 240 [CNDCR] = 0x03dc, 241 [CEFCR] = 0x03e4, 242 [FRECR] = 0x03e8, 243 [TSFRCR] = 0x03ec, 244 [TLFRCR] = 0x03f0, 245 [RFCR] = 0x03f4, 246 [MAFCR] = 0x03f8, 247 248 [EDMR] = 0x0200, 249 [EDTRR] = 0x0208, 250 [EDRRR] = 0x0210, 251 [TDLAR] = 0x0218, 252 [RDLAR] = 0x0220, 253 [EESR] = 0x0228, 254 [EESIPR] = 0x0230, 255 [TRSCER] = 0x0238, 256 [RMFCR] = 0x0240, 257 [TFTR] = 0x0248, 258 [FDR] = 0x0250, 259 [RMCR] = 0x0258, 260 [TFUCR] = 0x0264, 261 [RFOCR] = 0x0268, 262 [RMIIMODE] = 0x026c, 263 [FCFTR] = 0x0270, 264 [TRIMD] = 0x027c, 265 }; 266 267 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 268 SH_ETH_OFFSET_DEFAULTS, 269 270 [ECMR] = 0x0100, 271 [RFLR] = 0x0108, 272 [ECSR] = 0x0110, 273 [ECSIPR] = 0x0118, 274 [PIR] = 0x0120, 275 [PSR] = 0x0128, 276 [RDMLR] = 0x0140, 277 [IPGR] = 0x0150, 278 [APR] = 0x0154, 279 [MPR] = 0x0158, 280 [TPAUSER] = 0x0164, 281 [RFCF] = 0x0160, 282 [TPAUSECR] = 0x0168, 283 [BCFRR] = 0x016c, 284 [MAHR] = 0x01c0, 285 [MALR] = 0x01c8, 286 [TROCR] = 0x01d0, 287 [CDCR] = 0x01d4, 288 [LCCR] = 0x01d8, 289 [CNDCR] = 0x01dc, 290 [CEFCR] = 0x01e4, 291 [FRECR] = 0x01e8, 292 [TSFRCR] = 0x01ec, 293 [TLFRCR] = 0x01f0, 294 [RFCR] = 0x01f4, 295 [MAFCR] = 0x01f8, 296 [RTRATE] = 0x01fc, 297 298 [EDMR] = 0x0000, 299 [EDTRR] = 0x0008, 300 [EDRRR] = 0x0010, 301 [TDLAR] = 0x0018, 302 [RDLAR] = 0x0020, 303 [EESR] = 0x0028, 304 [EESIPR] = 0x0030, 305 [TRSCER] = 0x0038, 306 [RMFCR] = 0x0040, 307 [TFTR] = 0x0048, 308 [FDR] = 0x0050, 309 [RMCR] = 0x0058, 310 [TFUCR] = 0x0064, 311 [RFOCR] = 0x0068, 312 [FCFTR] = 0x0070, 313 [RPADIR] = 0x0078, 314 [TRIMD] = 0x007c, 315 [RBWAR] = 0x00c8, 316 [RDFAR] = 0x00cc, 317 [TBRAR] = 0x00d4, 318 [TDFAR] = 0x00d8, 319 }; 320 321 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 322 SH_ETH_OFFSET_DEFAULTS, 323 324 [EDMR] = 0x0000, 325 [EDTRR] = 0x0004, 326 [EDRRR] = 0x0008, 327 [TDLAR] = 0x000c, 328 [RDLAR] = 0x0010, 329 [EESR] = 0x0014, 330 [EESIPR] = 0x0018, 331 [TRSCER] = 0x001c, 332 [RMFCR] = 0x0020, 333 [TFTR] = 0x0024, 334 [FDR] = 0x0028, 335 [RMCR] = 0x002c, 336 [EDOCR] = 0x0030, 337 [FCFTR] = 0x0034, 338 [RPADIR] = 0x0038, 339 [TRIMD] = 0x003c, 340 [RBWAR] = 0x0040, 341 [RDFAR] = 0x0044, 342 [TBRAR] = 0x004c, 343 [TDFAR] = 0x0050, 344 345 [ECMR] = 0x0160, 346 [ECSR] = 0x0164, 347 [ECSIPR] = 0x0168, 348 [PIR] = 0x016c, 349 [MAHR] = 0x0170, 350 [MALR] = 0x0174, 351 [RFLR] = 0x0178, 352 [PSR] = 0x017c, 353 [TROCR] = 0x0180, 354 [CDCR] = 0x0184, 355 [LCCR] = 0x0188, 356 [CNDCR] = 0x018c, 357 [CEFCR] = 0x0194, 358 [FRECR] = 0x0198, 359 [TSFRCR] = 0x019c, 360 [TLFRCR] = 0x01a0, 361 [RFCR] = 0x01a4, 362 [MAFCR] = 0x01a8, 363 [IPGR] = 0x01b4, 364 [APR] = 0x01b8, 365 [MPR] = 0x01bc, 366 [TPAUSER] = 0x01c4, 367 [BCFR] = 0x01cc, 368 369 [ARSTR] = 0x0000, 370 [TSU_CTRST] = 0x0004, 371 [TSU_FWEN0] = 0x0010, 372 [TSU_FWEN1] = 0x0014, 373 [TSU_FCM] = 0x0018, 374 [TSU_BSYSL0] = 0x0020, 375 [TSU_BSYSL1] = 0x0024, 376 [TSU_PRISL0] = 0x0028, 377 [TSU_PRISL1] = 0x002c, 378 [TSU_FWSL0] = 0x0030, 379 [TSU_FWSL1] = 0x0034, 380 [TSU_FWSLC] = 0x0038, 381 [TSU_QTAGM0] = 0x0040, 382 [TSU_QTAGM1] = 0x0044, 383 [TSU_ADQT0] = 0x0048, 384 [TSU_ADQT1] = 0x004c, 385 [TSU_FWSR] = 0x0050, 386 [TSU_FWINMK] = 0x0054, 387 [TSU_ADSBSY] = 0x0060, 388 [TSU_TEN] = 0x0064, 389 [TSU_POST1] = 0x0070, 390 [TSU_POST2] = 0x0074, 391 [TSU_POST3] = 0x0078, 392 [TSU_POST4] = 0x007c, 393 394 [TXNLCR0] = 0x0080, 395 [TXALCR0] = 0x0084, 396 [RXNLCR0] = 0x0088, 397 [RXALCR0] = 0x008c, 398 [FWNLCR0] = 0x0090, 399 [FWALCR0] = 0x0094, 400 [TXNLCR1] = 0x00a0, 401 [TXALCR1] = 0x00a4, 402 [RXNLCR1] = 0x00a8, 403 [RXALCR1] = 0x00ac, 404 [FWNLCR1] = 0x00b0, 405 [FWALCR1] = 0x00b4, 406 407 [TSU_ADRH0] = 0x0100, 408 }; 409 410 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 411 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 412 413 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 414 { 415 struct sh_eth_private *mdp = netdev_priv(ndev); 416 u16 offset = mdp->reg_offset[enum_index]; 417 418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 419 return; 420 421 iowrite32(data, mdp->addr + offset); 422 } 423 424 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 425 { 426 struct sh_eth_private *mdp = netdev_priv(ndev); 427 u16 offset = mdp->reg_offset[enum_index]; 428 429 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 430 return ~0U; 431 432 return ioread32(mdp->addr + offset); 433 } 434 435 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 436 u32 set) 437 { 438 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 439 enum_index); 440 } 441 442 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data, 443 int enum_index) 444 { 445 u16 offset = mdp->reg_offset[enum_index]; 446 447 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 448 return; 449 450 iowrite32(data, mdp->tsu_addr + offset); 451 } 452 453 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index) 454 { 455 u16 offset = mdp->reg_offset[enum_index]; 456 457 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 458 return ~0U; 459 460 return ioread32(mdp->tsu_addr + offset); 461 } 462 463 static void sh_eth_select_mii(struct net_device *ndev) 464 { 465 struct sh_eth_private *mdp = netdev_priv(ndev); 466 u32 value; 467 468 switch (mdp->phy_interface) { 469 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID: 470 value = 0x3; 471 break; 472 case PHY_INTERFACE_MODE_GMII: 473 value = 0x2; 474 break; 475 case PHY_INTERFACE_MODE_MII: 476 value = 0x1; 477 break; 478 case PHY_INTERFACE_MODE_RMII: 479 value = 0x0; 480 break; 481 default: 482 netdev_warn(ndev, 483 "PHY interface mode was not setup. Set to MII.\n"); 484 value = 0x1; 485 break; 486 } 487 488 sh_eth_write(ndev, value, RMII_MII); 489 } 490 491 static void sh_eth_set_duplex(struct net_device *ndev) 492 { 493 struct sh_eth_private *mdp = netdev_priv(ndev); 494 495 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 496 } 497 498 static void sh_eth_chip_reset(struct net_device *ndev) 499 { 500 struct sh_eth_private *mdp = netdev_priv(ndev); 501 502 /* reset device */ 503 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 504 mdelay(1); 505 } 506 507 static int sh_eth_soft_reset(struct net_device *ndev) 508 { 509 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 510 mdelay(3); 511 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 512 513 return 0; 514 } 515 516 static int sh_eth_check_soft_reset(struct net_device *ndev) 517 { 518 int cnt; 519 520 for (cnt = 100; cnt > 0; cnt--) { 521 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 522 return 0; 523 mdelay(1); 524 } 525 526 netdev_err(ndev, "Device reset failed\n"); 527 return -ETIMEDOUT; 528 } 529 530 static int sh_eth_soft_reset_gether(struct net_device *ndev) 531 { 532 struct sh_eth_private *mdp = netdev_priv(ndev); 533 int ret; 534 535 sh_eth_write(ndev, EDSR_ENALL, EDSR); 536 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 537 538 ret = sh_eth_check_soft_reset(ndev); 539 if (ret) 540 return ret; 541 542 /* Table Init */ 543 sh_eth_write(ndev, 0, TDLAR); 544 sh_eth_write(ndev, 0, TDFAR); 545 sh_eth_write(ndev, 0, TDFXR); 546 sh_eth_write(ndev, 0, TDFFR); 547 sh_eth_write(ndev, 0, RDLAR); 548 sh_eth_write(ndev, 0, RDFAR); 549 sh_eth_write(ndev, 0, RDFXR); 550 sh_eth_write(ndev, 0, RDFFR); 551 552 /* Reset HW CRC register */ 553 if (mdp->cd->hw_checksum) 554 sh_eth_write(ndev, 0, CSMR); 555 556 /* Select MII mode */ 557 if (mdp->cd->select_mii) 558 sh_eth_select_mii(ndev); 559 560 return ret; 561 } 562 563 static void sh_eth_set_rate_gether(struct net_device *ndev) 564 { 565 struct sh_eth_private *mdp = netdev_priv(ndev); 566 567 switch (mdp->speed) { 568 case 10: /* 10BASE */ 569 sh_eth_write(ndev, GECMR_10, GECMR); 570 break; 571 case 100:/* 100BASE */ 572 sh_eth_write(ndev, GECMR_100, GECMR); 573 break; 574 case 1000: /* 1000BASE */ 575 sh_eth_write(ndev, GECMR_1000, GECMR); 576 break; 577 } 578 } 579 580 #ifdef CONFIG_OF 581 /* R7S72100 */ 582 static struct sh_eth_cpu_data r7s72100_data = { 583 .soft_reset = sh_eth_soft_reset_gether, 584 585 .chip_reset = sh_eth_chip_reset, 586 .set_duplex = sh_eth_set_duplex, 587 588 .register_type = SH_ETH_REG_FAST_RZ, 589 590 .edtrr_trns = EDTRR_TRNS_GETHER, 591 .ecsr_value = ECSR_ICD, 592 .ecsipr_value = ECSIPR_ICDIP, 593 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 594 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 595 EESIPR_ECIIP | 596 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 597 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 598 EESIPR_RMAFIP | EESIPR_RRFIP | 599 EESIPR_RTLFIP | EESIPR_RTSFIP | 600 EESIPR_PREIP | EESIPR_CERFIP, 601 602 .tx_check = EESR_TC1 | EESR_FTC, 603 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 604 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 605 EESR_TDE, 606 .fdr_value = 0x0000070f, 607 608 .no_psr = 1, 609 .apr = 1, 610 .mpr = 1, 611 .tpauser = 1, 612 .hw_swap = 1, 613 .rpadir = 1, 614 .rpadir_value = 2 << 16, 615 .no_trimd = 1, 616 .no_ade = 1, 617 .xdfar_rw = 1, 618 .hw_checksum = 1, 619 .tsu = 1, 620 .no_tx_cntrs = 1, 621 }; 622 623 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 624 { 625 sh_eth_chip_reset(ndev); 626 627 sh_eth_select_mii(ndev); 628 } 629 630 /* R8A7740 */ 631 static struct sh_eth_cpu_data r8a7740_data = { 632 .soft_reset = sh_eth_soft_reset_gether, 633 634 .chip_reset = sh_eth_chip_reset_r8a7740, 635 .set_duplex = sh_eth_set_duplex, 636 .set_rate = sh_eth_set_rate_gether, 637 638 .register_type = SH_ETH_REG_GIGABIT, 639 640 .edtrr_trns = EDTRR_TRNS_GETHER, 641 .ecsr_value = ECSR_ICD | ECSR_MPD, 642 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 643 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 644 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 645 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 646 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 647 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 648 EESIPR_CEEFIP | EESIPR_CELFIP | 649 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 650 EESIPR_PREIP | EESIPR_CERFIP, 651 652 .tx_check = EESR_TC1 | EESR_FTC, 653 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 654 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 655 EESR_TDE, 656 .fdr_value = 0x0000070f, 657 658 .apr = 1, 659 .mpr = 1, 660 .tpauser = 1, 661 .bculr = 1, 662 .hw_swap = 1, 663 .rpadir = 1, 664 .rpadir_value = 2 << 16, 665 .no_trimd = 1, 666 .no_ade = 1, 667 .xdfar_rw = 1, 668 .hw_checksum = 1, 669 .tsu = 1, 670 .select_mii = 1, 671 .magic = 1, 672 .cexcr = 1, 673 }; 674 675 /* There is CPU dependent code */ 676 static void sh_eth_set_rate_rcar(struct net_device *ndev) 677 { 678 struct sh_eth_private *mdp = netdev_priv(ndev); 679 680 switch (mdp->speed) { 681 case 10: /* 10BASE */ 682 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 683 break; 684 case 100:/* 100BASE */ 685 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 686 break; 687 } 688 } 689 690 /* R-Car Gen1 */ 691 static struct sh_eth_cpu_data rcar_gen1_data = { 692 .soft_reset = sh_eth_soft_reset, 693 694 .set_duplex = sh_eth_set_duplex, 695 .set_rate = sh_eth_set_rate_rcar, 696 697 .register_type = SH_ETH_REG_FAST_RCAR, 698 699 .edtrr_trns = EDTRR_TRNS_ETHER, 700 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 701 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 702 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 703 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 704 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 705 EESIPR_RMAFIP | EESIPR_RRFIP | 706 EESIPR_RTLFIP | EESIPR_RTSFIP | 707 EESIPR_PREIP | EESIPR_CERFIP, 708 709 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 710 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 711 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 712 .fdr_value = 0x00000f0f, 713 714 .apr = 1, 715 .mpr = 1, 716 .tpauser = 1, 717 .hw_swap = 1, 718 .no_xdfar = 1, 719 }; 720 721 /* R-Car Gen2 and RZ/G1 */ 722 static struct sh_eth_cpu_data rcar_gen2_data = { 723 .soft_reset = sh_eth_soft_reset, 724 725 .set_duplex = sh_eth_set_duplex, 726 .set_rate = sh_eth_set_rate_rcar, 727 728 .register_type = SH_ETH_REG_FAST_RCAR, 729 730 .edtrr_trns = EDTRR_TRNS_ETHER, 731 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 732 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 733 ECSIPR_MPDIP, 734 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 735 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 736 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 737 EESIPR_RMAFIP | EESIPR_RRFIP | 738 EESIPR_RTLFIP | EESIPR_RTSFIP | 739 EESIPR_PREIP | EESIPR_CERFIP, 740 741 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 742 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 743 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 744 .fdr_value = 0x00000f0f, 745 746 .trscer_err_mask = DESC_I_RINT8, 747 748 .apr = 1, 749 .mpr = 1, 750 .tpauser = 1, 751 .hw_swap = 1, 752 .no_xdfar = 1, 753 .rmiimode = 1, 754 .magic = 1, 755 }; 756 757 /* R8A77980 */ 758 static struct sh_eth_cpu_data r8a77980_data = { 759 .soft_reset = sh_eth_soft_reset_gether, 760 761 .set_duplex = sh_eth_set_duplex, 762 .set_rate = sh_eth_set_rate_gether, 763 764 .register_type = SH_ETH_REG_GIGABIT, 765 766 .edtrr_trns = EDTRR_TRNS_GETHER, 767 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 768 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 769 ECSIPR_MPDIP, 770 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 771 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 772 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 773 EESIPR_RMAFIP | EESIPR_RRFIP | 774 EESIPR_RTLFIP | EESIPR_RTSFIP | 775 EESIPR_PREIP | EESIPR_CERFIP, 776 777 .tx_check = EESR_FTC | EESR_CD | EESR_TRO, 778 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 779 EESR_RFE | EESR_RDE | EESR_RFRMER | 780 EESR_TFE | EESR_TDE | EESR_ECI, 781 .fdr_value = 0x0000070f, 782 783 .apr = 1, 784 .mpr = 1, 785 .tpauser = 1, 786 .bculr = 1, 787 .hw_swap = 1, 788 .nbst = 1, 789 .rpadir = 1, 790 .rpadir_value = 2 << 16, 791 .no_trimd = 1, 792 .no_ade = 1, 793 .xdfar_rw = 1, 794 .hw_checksum = 1, 795 .select_mii = 1, 796 .magic = 1, 797 .cexcr = 1, 798 }; 799 #endif /* CONFIG_OF */ 800 801 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 802 { 803 struct sh_eth_private *mdp = netdev_priv(ndev); 804 805 switch (mdp->speed) { 806 case 10: /* 10BASE */ 807 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 808 break; 809 case 100:/* 100BASE */ 810 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 811 break; 812 } 813 } 814 815 /* SH7724 */ 816 static struct sh_eth_cpu_data sh7724_data = { 817 .soft_reset = sh_eth_soft_reset, 818 819 .set_duplex = sh_eth_set_duplex, 820 .set_rate = sh_eth_set_rate_sh7724, 821 822 .register_type = SH_ETH_REG_FAST_SH4, 823 824 .edtrr_trns = EDTRR_TRNS_ETHER, 825 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 826 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 827 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 828 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 829 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 830 EESIPR_RMAFIP | EESIPR_RRFIP | 831 EESIPR_RTLFIP | EESIPR_RTSFIP | 832 EESIPR_PREIP | EESIPR_CERFIP, 833 834 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 835 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 836 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 837 838 .apr = 1, 839 .mpr = 1, 840 .tpauser = 1, 841 .hw_swap = 1, 842 .rpadir = 1, 843 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 844 }; 845 846 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 847 { 848 struct sh_eth_private *mdp = netdev_priv(ndev); 849 850 switch (mdp->speed) { 851 case 10: /* 10BASE */ 852 sh_eth_write(ndev, 0, RTRATE); 853 break; 854 case 100:/* 100BASE */ 855 sh_eth_write(ndev, 1, RTRATE); 856 break; 857 } 858 } 859 860 /* SH7757 */ 861 static struct sh_eth_cpu_data sh7757_data = { 862 .soft_reset = sh_eth_soft_reset, 863 864 .set_duplex = sh_eth_set_duplex, 865 .set_rate = sh_eth_set_rate_sh7757, 866 867 .register_type = SH_ETH_REG_FAST_SH4, 868 869 .edtrr_trns = EDTRR_TRNS_ETHER, 870 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 871 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 872 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 873 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 874 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 875 EESIPR_CEEFIP | EESIPR_CELFIP | 876 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 877 EESIPR_PREIP | EESIPR_CERFIP, 878 879 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 880 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 881 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 882 883 .irq_flags = IRQF_SHARED, 884 .apr = 1, 885 .mpr = 1, 886 .tpauser = 1, 887 .hw_swap = 1, 888 .no_ade = 1, 889 .rpadir = 1, 890 .rpadir_value = 2 << 16, 891 .rtrate = 1, 892 .dual_port = 1, 893 }; 894 895 #define SH_GIGA_ETH_BASE 0xfee00000UL 896 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 897 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 898 static void sh_eth_chip_reset_giga(struct net_device *ndev) 899 { 900 u32 mahr[2], malr[2]; 901 int i; 902 903 /* save MAHR and MALR */ 904 for (i = 0; i < 2; i++) { 905 malr[i] = ioread32((void *)GIGA_MALR(i)); 906 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 907 } 908 909 sh_eth_chip_reset(ndev); 910 911 /* restore MAHR and MALR */ 912 for (i = 0; i < 2; i++) { 913 iowrite32(malr[i], (void *)GIGA_MALR(i)); 914 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 915 } 916 } 917 918 static void sh_eth_set_rate_giga(struct net_device *ndev) 919 { 920 struct sh_eth_private *mdp = netdev_priv(ndev); 921 922 switch (mdp->speed) { 923 case 10: /* 10BASE */ 924 sh_eth_write(ndev, 0x00000000, GECMR); 925 break; 926 case 100:/* 100BASE */ 927 sh_eth_write(ndev, 0x00000010, GECMR); 928 break; 929 case 1000: /* 1000BASE */ 930 sh_eth_write(ndev, 0x00000020, GECMR); 931 break; 932 } 933 } 934 935 /* SH7757(GETHERC) */ 936 static struct sh_eth_cpu_data sh7757_data_giga = { 937 .soft_reset = sh_eth_soft_reset_gether, 938 939 .chip_reset = sh_eth_chip_reset_giga, 940 .set_duplex = sh_eth_set_duplex, 941 .set_rate = sh_eth_set_rate_giga, 942 943 .register_type = SH_ETH_REG_GIGABIT, 944 945 .edtrr_trns = EDTRR_TRNS_GETHER, 946 .ecsr_value = ECSR_ICD | ECSR_MPD, 947 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 948 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 949 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 950 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 951 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 952 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 953 EESIPR_CEEFIP | EESIPR_CELFIP | 954 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 955 EESIPR_PREIP | EESIPR_CERFIP, 956 957 .tx_check = EESR_TC1 | EESR_FTC, 958 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 959 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 960 EESR_TDE, 961 .fdr_value = 0x0000072f, 962 963 .irq_flags = IRQF_SHARED, 964 .apr = 1, 965 .mpr = 1, 966 .tpauser = 1, 967 .bculr = 1, 968 .hw_swap = 1, 969 .rpadir = 1, 970 .rpadir_value = 2 << 16, 971 .no_trimd = 1, 972 .no_ade = 1, 973 .xdfar_rw = 1, 974 .tsu = 1, 975 .cexcr = 1, 976 .dual_port = 1, 977 }; 978 979 /* SH7734 */ 980 static struct sh_eth_cpu_data sh7734_data = { 981 .soft_reset = sh_eth_soft_reset_gether, 982 983 .chip_reset = sh_eth_chip_reset, 984 .set_duplex = sh_eth_set_duplex, 985 .set_rate = sh_eth_set_rate_gether, 986 987 .register_type = SH_ETH_REG_GIGABIT, 988 989 .edtrr_trns = EDTRR_TRNS_GETHER, 990 .ecsr_value = ECSR_ICD | ECSR_MPD, 991 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 992 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 993 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 994 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 995 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 996 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 997 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 998 EESIPR_PREIP | EESIPR_CERFIP, 999 1000 .tx_check = EESR_TC1 | EESR_FTC, 1001 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1002 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 1003 EESR_TDE, 1004 1005 .apr = 1, 1006 .mpr = 1, 1007 .tpauser = 1, 1008 .bculr = 1, 1009 .hw_swap = 1, 1010 .no_trimd = 1, 1011 .no_ade = 1, 1012 .xdfar_rw = 1, 1013 .tsu = 1, 1014 .hw_checksum = 1, 1015 .select_mii = 1, 1016 .magic = 1, 1017 .cexcr = 1, 1018 }; 1019 1020 /* SH7763 */ 1021 static struct sh_eth_cpu_data sh7763_data = { 1022 .soft_reset = sh_eth_soft_reset_gether, 1023 1024 .chip_reset = sh_eth_chip_reset, 1025 .set_duplex = sh_eth_set_duplex, 1026 .set_rate = sh_eth_set_rate_gether, 1027 1028 .register_type = SH_ETH_REG_GIGABIT, 1029 1030 .edtrr_trns = EDTRR_TRNS_GETHER, 1031 .ecsr_value = ECSR_ICD | ECSR_MPD, 1032 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 1033 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1034 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1035 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1036 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1037 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1038 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1039 EESIPR_PREIP | EESIPR_CERFIP, 1040 1041 .tx_check = EESR_TC1 | EESR_FTC, 1042 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1043 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 1044 1045 .apr = 1, 1046 .mpr = 1, 1047 .tpauser = 1, 1048 .bculr = 1, 1049 .hw_swap = 1, 1050 .no_trimd = 1, 1051 .no_ade = 1, 1052 .xdfar_rw = 1, 1053 .tsu = 1, 1054 .irq_flags = IRQF_SHARED, 1055 .magic = 1, 1056 .cexcr = 1, 1057 .dual_port = 1, 1058 }; 1059 1060 static struct sh_eth_cpu_data sh7619_data = { 1061 .soft_reset = sh_eth_soft_reset, 1062 1063 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1064 1065 .edtrr_trns = EDTRR_TRNS_ETHER, 1066 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1067 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1068 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1069 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1070 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1071 EESIPR_CEEFIP | EESIPR_CELFIP | 1072 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1073 EESIPR_PREIP | EESIPR_CERFIP, 1074 1075 .apr = 1, 1076 .mpr = 1, 1077 .tpauser = 1, 1078 .hw_swap = 1, 1079 }; 1080 1081 static struct sh_eth_cpu_data sh771x_data = { 1082 .soft_reset = sh_eth_soft_reset, 1083 1084 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1085 1086 .edtrr_trns = EDTRR_TRNS_ETHER, 1087 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1088 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1089 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1090 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1091 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1092 EESIPR_CEEFIP | EESIPR_CELFIP | 1093 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1094 EESIPR_PREIP | EESIPR_CERFIP, 1095 .tsu = 1, 1096 .dual_port = 1, 1097 }; 1098 1099 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 1100 { 1101 if (!cd->ecsr_value) 1102 cd->ecsr_value = DEFAULT_ECSR_INIT; 1103 1104 if (!cd->ecsipr_value) 1105 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 1106 1107 if (!cd->fcftr_value) 1108 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 1109 DEFAULT_FIFO_F_D_RFD; 1110 1111 if (!cd->fdr_value) 1112 cd->fdr_value = DEFAULT_FDR_INIT; 1113 1114 if (!cd->tx_check) 1115 cd->tx_check = DEFAULT_TX_CHECK; 1116 1117 if (!cd->eesr_err_check) 1118 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 1119 1120 if (!cd->trscer_err_mask) 1121 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 1122 } 1123 1124 static void sh_eth_set_receive_align(struct sk_buff *skb) 1125 { 1126 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1127 1128 if (reserve) 1129 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1130 } 1131 1132 /* Program the hardware MAC address from dev->dev_addr. */ 1133 static void update_mac_address(struct net_device *ndev) 1134 { 1135 sh_eth_write(ndev, 1136 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1137 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1138 sh_eth_write(ndev, 1139 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1140 } 1141 1142 /* Get MAC address from SuperH MAC address register 1143 * 1144 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1145 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1146 * When you want use this device, you must set MAC address in bootloader. 1147 * 1148 */ 1149 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1150 { 1151 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1152 memcpy(ndev->dev_addr, mac, ETH_ALEN); 1153 } else { 1154 u32 mahr = sh_eth_read(ndev, MAHR); 1155 u32 malr = sh_eth_read(ndev, MALR); 1156 1157 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 1158 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 1159 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 1160 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 1161 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 1162 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 1163 } 1164 } 1165 1166 struct bb_info { 1167 void (*set_gate)(void *addr); 1168 struct mdiobb_ctrl ctrl; 1169 void *addr; 1170 }; 1171 1172 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1173 { 1174 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1175 u32 pir; 1176 1177 if (bitbang->set_gate) 1178 bitbang->set_gate(bitbang->addr); 1179 1180 pir = ioread32(bitbang->addr); 1181 if (set) 1182 pir |= mask; 1183 else 1184 pir &= ~mask; 1185 iowrite32(pir, bitbang->addr); 1186 } 1187 1188 /* Data I/O pin control */ 1189 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1190 { 1191 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1192 } 1193 1194 /* Set bit data*/ 1195 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1196 { 1197 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1198 } 1199 1200 /* Get bit data*/ 1201 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1202 { 1203 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1204 1205 if (bitbang->set_gate) 1206 bitbang->set_gate(bitbang->addr); 1207 1208 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1209 } 1210 1211 /* MDC pin control */ 1212 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1213 { 1214 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1215 } 1216 1217 /* mdio bus control struct */ 1218 static struct mdiobb_ops bb_ops = { 1219 .owner = THIS_MODULE, 1220 .set_mdc = sh_mdc_ctrl, 1221 .set_mdio_dir = sh_mmd_ctrl, 1222 .set_mdio_data = sh_set_mdio, 1223 .get_mdio_data = sh_get_mdio, 1224 }; 1225 1226 /* free Tx skb function */ 1227 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) 1228 { 1229 struct sh_eth_private *mdp = netdev_priv(ndev); 1230 struct sh_eth_txdesc *txdesc; 1231 int free_num = 0; 1232 int entry; 1233 bool sent; 1234 1235 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1236 entry = mdp->dirty_tx % mdp->num_tx_ring; 1237 txdesc = &mdp->tx_ring[entry]; 1238 sent = !(txdesc->status & cpu_to_le32(TD_TACT)); 1239 if (sent_only && !sent) 1240 break; 1241 /* TACT bit must be checked before all the following reads */ 1242 dma_rmb(); 1243 netif_info(mdp, tx_done, ndev, 1244 "tx entry %d status 0x%08x\n", 1245 entry, le32_to_cpu(txdesc->status)); 1246 /* Free the original skb. */ 1247 if (mdp->tx_skbuff[entry]) { 1248 dma_unmap_single(&mdp->pdev->dev, 1249 le32_to_cpu(txdesc->addr), 1250 le32_to_cpu(txdesc->len) >> 16, 1251 DMA_TO_DEVICE); 1252 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1253 mdp->tx_skbuff[entry] = NULL; 1254 free_num++; 1255 } 1256 txdesc->status = cpu_to_le32(TD_TFP); 1257 if (entry >= mdp->num_tx_ring - 1) 1258 txdesc->status |= cpu_to_le32(TD_TDLE); 1259 1260 if (sent) { 1261 ndev->stats.tx_packets++; 1262 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1263 } 1264 } 1265 return free_num; 1266 } 1267 1268 /* free skb and descriptor buffer */ 1269 static void sh_eth_ring_free(struct net_device *ndev) 1270 { 1271 struct sh_eth_private *mdp = netdev_priv(ndev); 1272 int ringsize, i; 1273 1274 if (mdp->rx_ring) { 1275 for (i = 0; i < mdp->num_rx_ring; i++) { 1276 if (mdp->rx_skbuff[i]) { 1277 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; 1278 1279 dma_unmap_single(&mdp->pdev->dev, 1280 le32_to_cpu(rxdesc->addr), 1281 ALIGN(mdp->rx_buf_sz, 32), 1282 DMA_FROM_DEVICE); 1283 } 1284 } 1285 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1286 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, 1287 mdp->rx_desc_dma); 1288 mdp->rx_ring = NULL; 1289 } 1290 1291 /* Free Rx skb ringbuffer */ 1292 if (mdp->rx_skbuff) { 1293 for (i = 0; i < mdp->num_rx_ring; i++) 1294 dev_kfree_skb(mdp->rx_skbuff[i]); 1295 } 1296 kfree(mdp->rx_skbuff); 1297 mdp->rx_skbuff = NULL; 1298 1299 if (mdp->tx_ring) { 1300 sh_eth_tx_free(ndev, false); 1301 1302 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1303 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, 1304 mdp->tx_desc_dma); 1305 mdp->tx_ring = NULL; 1306 } 1307 1308 /* Free Tx skb ringbuffer */ 1309 kfree(mdp->tx_skbuff); 1310 mdp->tx_skbuff = NULL; 1311 } 1312 1313 /* format skb and descriptor buffer */ 1314 static void sh_eth_ring_format(struct net_device *ndev) 1315 { 1316 struct sh_eth_private *mdp = netdev_priv(ndev); 1317 int i; 1318 struct sk_buff *skb; 1319 struct sh_eth_rxdesc *rxdesc = NULL; 1320 struct sh_eth_txdesc *txdesc = NULL; 1321 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1322 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1323 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1324 dma_addr_t dma_addr; 1325 u32 buf_len; 1326 1327 mdp->cur_rx = 0; 1328 mdp->cur_tx = 0; 1329 mdp->dirty_rx = 0; 1330 mdp->dirty_tx = 0; 1331 1332 memset(mdp->rx_ring, 0, rx_ringsize); 1333 1334 /* build Rx ring buffer */ 1335 for (i = 0; i < mdp->num_rx_ring; i++) { 1336 /* skb */ 1337 mdp->rx_skbuff[i] = NULL; 1338 skb = netdev_alloc_skb(ndev, skbuff_size); 1339 if (skb == NULL) 1340 break; 1341 sh_eth_set_receive_align(skb); 1342 1343 /* The size of the buffer is a multiple of 32 bytes. */ 1344 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1345 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, 1346 DMA_FROM_DEVICE); 1347 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1348 kfree_skb(skb); 1349 break; 1350 } 1351 mdp->rx_skbuff[i] = skb; 1352 1353 /* RX descriptor */ 1354 rxdesc = &mdp->rx_ring[i]; 1355 rxdesc->len = cpu_to_le32(buf_len << 16); 1356 rxdesc->addr = cpu_to_le32(dma_addr); 1357 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1358 1359 /* Rx descriptor address set */ 1360 if (i == 0) { 1361 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1362 if (mdp->cd->xdfar_rw) 1363 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1364 } 1365 } 1366 1367 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1368 1369 /* Mark the last entry as wrapping the ring. */ 1370 if (rxdesc) 1371 rxdesc->status |= cpu_to_le32(RD_RDLE); 1372 1373 memset(mdp->tx_ring, 0, tx_ringsize); 1374 1375 /* build Tx ring buffer */ 1376 for (i = 0; i < mdp->num_tx_ring; i++) { 1377 mdp->tx_skbuff[i] = NULL; 1378 txdesc = &mdp->tx_ring[i]; 1379 txdesc->status = cpu_to_le32(TD_TFP); 1380 txdesc->len = cpu_to_le32(0); 1381 if (i == 0) { 1382 /* Tx descriptor address set */ 1383 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1384 if (mdp->cd->xdfar_rw) 1385 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1386 } 1387 } 1388 1389 txdesc->status |= cpu_to_le32(TD_TDLE); 1390 } 1391 1392 /* Get skb and descriptor buffer */ 1393 static int sh_eth_ring_init(struct net_device *ndev) 1394 { 1395 struct sh_eth_private *mdp = netdev_priv(ndev); 1396 int rx_ringsize, tx_ringsize; 1397 1398 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1399 * card needs room to do 8 byte alignment, +2 so we can reserve 1400 * the first 2 bytes, and +16 gets room for the status word from the 1401 * card. 1402 */ 1403 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1404 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1405 if (mdp->cd->rpadir) 1406 mdp->rx_buf_sz += NET_IP_ALIGN; 1407 1408 /* Allocate RX and TX skb rings */ 1409 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1410 GFP_KERNEL); 1411 if (!mdp->rx_skbuff) 1412 return -ENOMEM; 1413 1414 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1415 GFP_KERNEL); 1416 if (!mdp->tx_skbuff) 1417 goto ring_free; 1418 1419 /* Allocate all Rx descriptors. */ 1420 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1421 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, 1422 &mdp->rx_desc_dma, GFP_KERNEL); 1423 if (!mdp->rx_ring) 1424 goto ring_free; 1425 1426 mdp->dirty_rx = 0; 1427 1428 /* Allocate all Tx descriptors. */ 1429 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1430 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, 1431 &mdp->tx_desc_dma, GFP_KERNEL); 1432 if (!mdp->tx_ring) 1433 goto ring_free; 1434 return 0; 1435 1436 ring_free: 1437 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1438 sh_eth_ring_free(ndev); 1439 1440 return -ENOMEM; 1441 } 1442 1443 static int sh_eth_dev_init(struct net_device *ndev) 1444 { 1445 struct sh_eth_private *mdp = netdev_priv(ndev); 1446 int ret; 1447 1448 /* Soft Reset */ 1449 ret = mdp->cd->soft_reset(ndev); 1450 if (ret) 1451 return ret; 1452 1453 if (mdp->cd->rmiimode) 1454 sh_eth_write(ndev, 0x1, RMIIMODE); 1455 1456 /* Descriptor format */ 1457 sh_eth_ring_format(ndev); 1458 if (mdp->cd->rpadir) 1459 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1460 1461 /* all sh_eth int mask */ 1462 sh_eth_write(ndev, 0, EESIPR); 1463 1464 #if defined(__LITTLE_ENDIAN) 1465 if (mdp->cd->hw_swap) 1466 sh_eth_write(ndev, EDMR_EL, EDMR); 1467 else 1468 #endif 1469 sh_eth_write(ndev, 0, EDMR); 1470 1471 /* FIFO size set */ 1472 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1473 sh_eth_write(ndev, 0, TFTR); 1474 1475 /* Frame recv control (enable multiple-packets per rx irq) */ 1476 sh_eth_write(ndev, RMCR_RNC, RMCR); 1477 1478 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1479 1480 /* DMA transfer burst mode */ 1481 if (mdp->cd->nbst) 1482 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST); 1483 1484 /* Burst cycle count upper-limit */ 1485 if (mdp->cd->bculr) 1486 sh_eth_write(ndev, 0x800, BCULR); 1487 1488 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1489 1490 if (!mdp->cd->no_trimd) 1491 sh_eth_write(ndev, 0, TRIMD); 1492 1493 /* Recv frame limit set register */ 1494 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1495 RFLR); 1496 1497 sh_eth_modify(ndev, EESR, 0, 0); 1498 mdp->irq_enabled = true; 1499 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1500 1501 /* PAUSE Prohibition */ 1502 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1503 ECMR_TE | ECMR_RE, ECMR); 1504 1505 if (mdp->cd->set_rate) 1506 mdp->cd->set_rate(ndev); 1507 1508 /* E-MAC Status Register clear */ 1509 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1510 1511 /* E-MAC Interrupt Enable register */ 1512 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1513 1514 /* Set MAC address */ 1515 update_mac_address(ndev); 1516 1517 /* mask reset */ 1518 if (mdp->cd->apr) 1519 sh_eth_write(ndev, APR_AP, APR); 1520 if (mdp->cd->mpr) 1521 sh_eth_write(ndev, MPR_MP, MPR); 1522 if (mdp->cd->tpauser) 1523 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1524 1525 /* Setting the Rx mode will start the Rx process. */ 1526 sh_eth_write(ndev, EDRRR_R, EDRRR); 1527 1528 return ret; 1529 } 1530 1531 static void sh_eth_dev_exit(struct net_device *ndev) 1532 { 1533 struct sh_eth_private *mdp = netdev_priv(ndev); 1534 int i; 1535 1536 /* Deactivate all TX descriptors, so DMA should stop at next 1537 * packet boundary if it's currently running 1538 */ 1539 for (i = 0; i < mdp->num_tx_ring; i++) 1540 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1541 1542 /* Disable TX FIFO egress to MAC */ 1543 sh_eth_rcv_snd_disable(ndev); 1544 1545 /* Stop RX DMA at next packet boundary */ 1546 sh_eth_write(ndev, 0, EDRRR); 1547 1548 /* Aside from TX DMA, we can't tell when the hardware is 1549 * really stopped, so we need to reset to make sure. 1550 * Before doing that, wait for long enough to *probably* 1551 * finish transmitting the last packet and poll stats. 1552 */ 1553 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1554 sh_eth_get_stats(ndev); 1555 mdp->cd->soft_reset(ndev); 1556 1557 /* Set MAC address again */ 1558 update_mac_address(ndev); 1559 } 1560 1561 /* Packet receive function */ 1562 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1563 { 1564 struct sh_eth_private *mdp = netdev_priv(ndev); 1565 struct sh_eth_rxdesc *rxdesc; 1566 1567 int entry = mdp->cur_rx % mdp->num_rx_ring; 1568 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1569 int limit; 1570 struct sk_buff *skb; 1571 u32 desc_status; 1572 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1573 dma_addr_t dma_addr; 1574 u16 pkt_len; 1575 u32 buf_len; 1576 1577 boguscnt = min(boguscnt, *quota); 1578 limit = boguscnt; 1579 rxdesc = &mdp->rx_ring[entry]; 1580 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1581 /* RACT bit must be checked before all the following reads */ 1582 dma_rmb(); 1583 desc_status = le32_to_cpu(rxdesc->status); 1584 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1585 1586 if (--boguscnt < 0) 1587 break; 1588 1589 netif_info(mdp, rx_status, ndev, 1590 "rx entry %d status 0x%08x len %d\n", 1591 entry, desc_status, pkt_len); 1592 1593 if (!(desc_status & RDFEND)) 1594 ndev->stats.rx_length_errors++; 1595 1596 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1597 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1598 * bit 0. However, in case of the R8A7740 and R7S72100 1599 * the RFS bits are from bit 25 to bit 16. So, the 1600 * driver needs right shifting by 16. 1601 */ 1602 if (mdp->cd->hw_checksum) 1603 desc_status >>= 16; 1604 1605 skb = mdp->rx_skbuff[entry]; 1606 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1607 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1608 ndev->stats.rx_errors++; 1609 if (desc_status & RD_RFS1) 1610 ndev->stats.rx_crc_errors++; 1611 if (desc_status & RD_RFS2) 1612 ndev->stats.rx_frame_errors++; 1613 if (desc_status & RD_RFS3) 1614 ndev->stats.rx_length_errors++; 1615 if (desc_status & RD_RFS4) 1616 ndev->stats.rx_length_errors++; 1617 if (desc_status & RD_RFS6) 1618 ndev->stats.rx_missed_errors++; 1619 if (desc_status & RD_RFS10) 1620 ndev->stats.rx_over_errors++; 1621 } else if (skb) { 1622 dma_addr = le32_to_cpu(rxdesc->addr); 1623 if (!mdp->cd->hw_swap) 1624 sh_eth_soft_swap( 1625 phys_to_virt(ALIGN(dma_addr, 4)), 1626 pkt_len + 2); 1627 mdp->rx_skbuff[entry] = NULL; 1628 if (mdp->cd->rpadir) 1629 skb_reserve(skb, NET_IP_ALIGN); 1630 dma_unmap_single(&mdp->pdev->dev, dma_addr, 1631 ALIGN(mdp->rx_buf_sz, 32), 1632 DMA_FROM_DEVICE); 1633 skb_put(skb, pkt_len); 1634 skb->protocol = eth_type_trans(skb, ndev); 1635 netif_receive_skb(skb); 1636 ndev->stats.rx_packets++; 1637 ndev->stats.rx_bytes += pkt_len; 1638 if (desc_status & RD_RFS8) 1639 ndev->stats.multicast++; 1640 } 1641 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1642 rxdesc = &mdp->rx_ring[entry]; 1643 } 1644 1645 /* Refill the Rx ring buffers. */ 1646 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1647 entry = mdp->dirty_rx % mdp->num_rx_ring; 1648 rxdesc = &mdp->rx_ring[entry]; 1649 /* The size of the buffer is 32 byte boundary. */ 1650 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1651 rxdesc->len = cpu_to_le32(buf_len << 16); 1652 1653 if (mdp->rx_skbuff[entry] == NULL) { 1654 skb = netdev_alloc_skb(ndev, skbuff_size); 1655 if (skb == NULL) 1656 break; /* Better luck next round. */ 1657 sh_eth_set_receive_align(skb); 1658 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, 1659 buf_len, DMA_FROM_DEVICE); 1660 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1661 kfree_skb(skb); 1662 break; 1663 } 1664 mdp->rx_skbuff[entry] = skb; 1665 1666 skb_checksum_none_assert(skb); 1667 rxdesc->addr = cpu_to_le32(dma_addr); 1668 } 1669 dma_wmb(); /* RACT bit must be set after all the above writes */ 1670 if (entry >= mdp->num_rx_ring - 1) 1671 rxdesc->status |= 1672 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1673 else 1674 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1675 } 1676 1677 /* Restart Rx engine if stopped. */ 1678 /* If we don't need to check status, don't. -KDU */ 1679 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1680 /* fix the values for the next receiving if RDE is set */ 1681 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) { 1682 u32 count = (sh_eth_read(ndev, RDFAR) - 1683 sh_eth_read(ndev, RDLAR)) >> 4; 1684 1685 mdp->cur_rx = count; 1686 mdp->dirty_rx = count; 1687 } 1688 sh_eth_write(ndev, EDRRR_R, EDRRR); 1689 } 1690 1691 *quota -= limit - boguscnt - 1; 1692 1693 return *quota <= 0; 1694 } 1695 1696 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1697 { 1698 /* disable tx and rx */ 1699 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1700 } 1701 1702 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1703 { 1704 /* enable tx and rx */ 1705 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1706 } 1707 1708 /* E-MAC interrupt handler */ 1709 static void sh_eth_emac_interrupt(struct net_device *ndev) 1710 { 1711 struct sh_eth_private *mdp = netdev_priv(ndev); 1712 u32 felic_stat; 1713 u32 link_stat; 1714 1715 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1716 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1717 if (felic_stat & ECSR_ICD) 1718 ndev->stats.tx_carrier_errors++; 1719 if (felic_stat & ECSR_MPD) 1720 pm_wakeup_event(&mdp->pdev->dev, 0); 1721 if (felic_stat & ECSR_LCHNG) { 1722 /* Link Changed */ 1723 if (mdp->cd->no_psr || mdp->no_ether_link) 1724 return; 1725 link_stat = sh_eth_read(ndev, PSR); 1726 if (mdp->ether_link_active_low) 1727 link_stat = ~link_stat; 1728 if (!(link_stat & PHY_ST_LINK)) { 1729 sh_eth_rcv_snd_disable(ndev); 1730 } else { 1731 /* Link Up */ 1732 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1733 /* clear int */ 1734 sh_eth_modify(ndev, ECSR, 0, 0); 1735 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1736 /* enable tx and rx */ 1737 sh_eth_rcv_snd_enable(ndev); 1738 } 1739 } 1740 } 1741 1742 /* error control function */ 1743 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1744 { 1745 struct sh_eth_private *mdp = netdev_priv(ndev); 1746 u32 mask; 1747 1748 if (intr_status & EESR_TWB) { 1749 /* Unused write back interrupt */ 1750 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1751 ndev->stats.tx_aborted_errors++; 1752 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1753 } 1754 } 1755 1756 if (intr_status & EESR_RABT) { 1757 /* Receive Abort int */ 1758 if (intr_status & EESR_RFRMER) { 1759 /* Receive Frame Overflow int */ 1760 ndev->stats.rx_frame_errors++; 1761 } 1762 } 1763 1764 if (intr_status & EESR_TDE) { 1765 /* Transmit Descriptor Empty int */ 1766 ndev->stats.tx_fifo_errors++; 1767 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1768 } 1769 1770 if (intr_status & EESR_TFE) { 1771 /* FIFO under flow */ 1772 ndev->stats.tx_fifo_errors++; 1773 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1774 } 1775 1776 if (intr_status & EESR_RDE) { 1777 /* Receive Descriptor Empty int */ 1778 ndev->stats.rx_over_errors++; 1779 } 1780 1781 if (intr_status & EESR_RFE) { 1782 /* Receive FIFO Overflow int */ 1783 ndev->stats.rx_fifo_errors++; 1784 } 1785 1786 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1787 /* Address Error */ 1788 ndev->stats.tx_fifo_errors++; 1789 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1790 } 1791 1792 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1793 if (mdp->cd->no_ade) 1794 mask &= ~EESR_ADE; 1795 if (intr_status & mask) { 1796 /* Tx error */ 1797 u32 edtrr = sh_eth_read(ndev, EDTRR); 1798 1799 /* dmesg */ 1800 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1801 intr_status, mdp->cur_tx, mdp->dirty_tx, 1802 (u32)ndev->state, edtrr); 1803 /* dirty buffer free */ 1804 sh_eth_tx_free(ndev, true); 1805 1806 /* SH7712 BUG */ 1807 if (edtrr ^ mdp->cd->edtrr_trns) { 1808 /* tx dma start */ 1809 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 1810 } 1811 /* wakeup */ 1812 netif_wake_queue(ndev); 1813 } 1814 } 1815 1816 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1817 { 1818 struct net_device *ndev = netdev; 1819 struct sh_eth_private *mdp = netdev_priv(ndev); 1820 struct sh_eth_cpu_data *cd = mdp->cd; 1821 irqreturn_t ret = IRQ_NONE; 1822 u32 intr_status, intr_enable; 1823 1824 spin_lock(&mdp->lock); 1825 1826 /* Get interrupt status */ 1827 intr_status = sh_eth_read(ndev, EESR); 1828 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1829 * enabled since it's the one that comes thru regardless of the mask, 1830 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1831 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1832 * bit... 1833 */ 1834 intr_enable = sh_eth_read(ndev, EESIPR); 1835 intr_status &= intr_enable | EESIPR_ECIIP; 1836 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1837 cd->eesr_err_check)) 1838 ret = IRQ_HANDLED; 1839 else 1840 goto out; 1841 1842 if (unlikely(!mdp->irq_enabled)) { 1843 sh_eth_write(ndev, 0, EESIPR); 1844 goto out; 1845 } 1846 1847 if (intr_status & EESR_RX_CHECK) { 1848 if (napi_schedule_prep(&mdp->napi)) { 1849 /* Mask Rx interrupts */ 1850 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1851 EESIPR); 1852 __napi_schedule(&mdp->napi); 1853 } else { 1854 netdev_warn(ndev, 1855 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1856 intr_status, intr_enable); 1857 } 1858 } 1859 1860 /* Tx Check */ 1861 if (intr_status & cd->tx_check) { 1862 /* Clear Tx interrupts */ 1863 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1864 1865 sh_eth_tx_free(ndev, true); 1866 netif_wake_queue(ndev); 1867 } 1868 1869 /* E-MAC interrupt */ 1870 if (intr_status & EESR_ECI) 1871 sh_eth_emac_interrupt(ndev); 1872 1873 if (intr_status & cd->eesr_err_check) { 1874 /* Clear error interrupts */ 1875 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1876 1877 sh_eth_error(ndev, intr_status); 1878 } 1879 1880 out: 1881 spin_unlock(&mdp->lock); 1882 1883 return ret; 1884 } 1885 1886 static int sh_eth_poll(struct napi_struct *napi, int budget) 1887 { 1888 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1889 napi); 1890 struct net_device *ndev = napi->dev; 1891 int quota = budget; 1892 u32 intr_status; 1893 1894 for (;;) { 1895 intr_status = sh_eth_read(ndev, EESR); 1896 if (!(intr_status & EESR_RX_CHECK)) 1897 break; 1898 /* Clear Rx interrupts */ 1899 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1900 1901 if (sh_eth_rx(ndev, intr_status, "a)) 1902 goto out; 1903 } 1904 1905 napi_complete(napi); 1906 1907 /* Reenable Rx interrupts */ 1908 if (mdp->irq_enabled) 1909 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1910 out: 1911 return budget - quota; 1912 } 1913 1914 /* PHY state control function */ 1915 static void sh_eth_adjust_link(struct net_device *ndev) 1916 { 1917 struct sh_eth_private *mdp = netdev_priv(ndev); 1918 struct phy_device *phydev = ndev->phydev; 1919 int new_state = 0; 1920 1921 if (phydev->link) { 1922 if (phydev->duplex != mdp->duplex) { 1923 new_state = 1; 1924 mdp->duplex = phydev->duplex; 1925 if (mdp->cd->set_duplex) 1926 mdp->cd->set_duplex(ndev); 1927 } 1928 1929 if (phydev->speed != mdp->speed) { 1930 new_state = 1; 1931 mdp->speed = phydev->speed; 1932 if (mdp->cd->set_rate) 1933 mdp->cd->set_rate(ndev); 1934 } 1935 if (!mdp->link) { 1936 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 1937 new_state = 1; 1938 mdp->link = phydev->link; 1939 if (mdp->cd->no_psr || mdp->no_ether_link) 1940 sh_eth_rcv_snd_enable(ndev); 1941 } 1942 } else if (mdp->link) { 1943 new_state = 1; 1944 mdp->link = 0; 1945 mdp->speed = 0; 1946 mdp->duplex = -1; 1947 if (mdp->cd->no_psr || mdp->no_ether_link) 1948 sh_eth_rcv_snd_disable(ndev); 1949 } 1950 1951 if (new_state && netif_msg_link(mdp)) 1952 phy_print_status(phydev); 1953 } 1954 1955 /* PHY init function */ 1956 static int sh_eth_phy_init(struct net_device *ndev) 1957 { 1958 struct device_node *np = ndev->dev.parent->of_node; 1959 struct sh_eth_private *mdp = netdev_priv(ndev); 1960 struct phy_device *phydev; 1961 1962 mdp->link = 0; 1963 mdp->speed = 0; 1964 mdp->duplex = -1; 1965 1966 /* Try connect to PHY */ 1967 if (np) { 1968 struct device_node *pn; 1969 1970 pn = of_parse_phandle(np, "phy-handle", 0); 1971 phydev = of_phy_connect(ndev, pn, 1972 sh_eth_adjust_link, 0, 1973 mdp->phy_interface); 1974 1975 of_node_put(pn); 1976 if (!phydev) 1977 phydev = ERR_PTR(-ENOENT); 1978 } else { 1979 char phy_id[MII_BUS_ID_SIZE + 3]; 1980 1981 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1982 mdp->mii_bus->id, mdp->phy_id); 1983 1984 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1985 mdp->phy_interface); 1986 } 1987 1988 if (IS_ERR(phydev)) { 1989 netdev_err(ndev, "failed to connect PHY\n"); 1990 return PTR_ERR(phydev); 1991 } 1992 1993 /* mask with MAC supported features */ 1994 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) { 1995 int err = phy_set_max_speed(phydev, SPEED_100); 1996 if (err) { 1997 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n"); 1998 phy_disconnect(phydev); 1999 return err; 2000 } 2001 } 2002 2003 phy_attached_info(phydev); 2004 2005 return 0; 2006 } 2007 2008 /* PHY control start function */ 2009 static int sh_eth_phy_start(struct net_device *ndev) 2010 { 2011 int ret; 2012 2013 ret = sh_eth_phy_init(ndev); 2014 if (ret) 2015 return ret; 2016 2017 phy_start(ndev->phydev); 2018 2019 return 0; 2020 } 2021 2022 static int sh_eth_get_link_ksettings(struct net_device *ndev, 2023 struct ethtool_link_ksettings *cmd) 2024 { 2025 struct sh_eth_private *mdp = netdev_priv(ndev); 2026 unsigned long flags; 2027 2028 if (!ndev->phydev) 2029 return -ENODEV; 2030 2031 spin_lock_irqsave(&mdp->lock, flags); 2032 phy_ethtool_ksettings_get(ndev->phydev, cmd); 2033 spin_unlock_irqrestore(&mdp->lock, flags); 2034 2035 return 0; 2036 } 2037 2038 static int sh_eth_set_link_ksettings(struct net_device *ndev, 2039 const struct ethtool_link_ksettings *cmd) 2040 { 2041 struct sh_eth_private *mdp = netdev_priv(ndev); 2042 unsigned long flags; 2043 int ret; 2044 2045 if (!ndev->phydev) 2046 return -ENODEV; 2047 2048 spin_lock_irqsave(&mdp->lock, flags); 2049 2050 /* disable tx and rx */ 2051 sh_eth_rcv_snd_disable(ndev); 2052 2053 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd); 2054 if (ret) 2055 goto error_exit; 2056 2057 if (cmd->base.duplex == DUPLEX_FULL) 2058 mdp->duplex = 1; 2059 else 2060 mdp->duplex = 0; 2061 2062 if (mdp->cd->set_duplex) 2063 mdp->cd->set_duplex(ndev); 2064 2065 error_exit: 2066 mdelay(1); 2067 2068 /* enable tx and rx */ 2069 sh_eth_rcv_snd_enable(ndev); 2070 2071 spin_unlock_irqrestore(&mdp->lock, flags); 2072 2073 return ret; 2074 } 2075 2076 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 2077 * version must be bumped as well. Just adding registers up to that 2078 * limit is fine, as long as the existing register indices don't 2079 * change. 2080 */ 2081 #define SH_ETH_REG_DUMP_VERSION 1 2082 #define SH_ETH_REG_DUMP_MAX_REGS 256 2083 2084 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 2085 { 2086 struct sh_eth_private *mdp = netdev_priv(ndev); 2087 struct sh_eth_cpu_data *cd = mdp->cd; 2088 u32 *valid_map; 2089 size_t len; 2090 2091 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 2092 2093 /* Dump starts with a bitmap that tells ethtool which 2094 * registers are defined for this chip. 2095 */ 2096 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 2097 if (buf) { 2098 valid_map = buf; 2099 buf += len; 2100 } else { 2101 valid_map = NULL; 2102 } 2103 2104 /* Add a register to the dump, if it has a defined offset. 2105 * This automatically skips most undefined registers, but for 2106 * some it is also necessary to check a capability flag in 2107 * struct sh_eth_cpu_data. 2108 */ 2109 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 2110 #define add_reg_from(reg, read_expr) do { \ 2111 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2112 if (buf) { \ 2113 mark_reg_valid(reg); \ 2114 *buf++ = read_expr; \ 2115 } \ 2116 ++len; \ 2117 } \ 2118 } while (0) 2119 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2120 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2121 2122 add_reg(EDSR); 2123 add_reg(EDMR); 2124 add_reg(EDTRR); 2125 add_reg(EDRRR); 2126 add_reg(EESR); 2127 add_reg(EESIPR); 2128 add_reg(TDLAR); 2129 add_reg(TDFAR); 2130 add_reg(TDFXR); 2131 add_reg(TDFFR); 2132 add_reg(RDLAR); 2133 add_reg(RDFAR); 2134 add_reg(RDFXR); 2135 add_reg(RDFFR); 2136 add_reg(TRSCER); 2137 add_reg(RMFCR); 2138 add_reg(TFTR); 2139 add_reg(FDR); 2140 add_reg(RMCR); 2141 add_reg(TFUCR); 2142 add_reg(RFOCR); 2143 if (cd->rmiimode) 2144 add_reg(RMIIMODE); 2145 add_reg(FCFTR); 2146 if (cd->rpadir) 2147 add_reg(RPADIR); 2148 if (!cd->no_trimd) 2149 add_reg(TRIMD); 2150 add_reg(ECMR); 2151 add_reg(ECSR); 2152 add_reg(ECSIPR); 2153 add_reg(PIR); 2154 if (!cd->no_psr) 2155 add_reg(PSR); 2156 add_reg(RDMLR); 2157 add_reg(RFLR); 2158 add_reg(IPGR); 2159 if (cd->apr) 2160 add_reg(APR); 2161 if (cd->mpr) 2162 add_reg(MPR); 2163 add_reg(RFCR); 2164 add_reg(RFCF); 2165 if (cd->tpauser) 2166 add_reg(TPAUSER); 2167 add_reg(TPAUSECR); 2168 add_reg(GECMR); 2169 if (cd->bculr) 2170 add_reg(BCULR); 2171 add_reg(MAHR); 2172 add_reg(MALR); 2173 add_reg(TROCR); 2174 add_reg(CDCR); 2175 add_reg(LCCR); 2176 add_reg(CNDCR); 2177 add_reg(CEFCR); 2178 add_reg(FRECR); 2179 add_reg(TSFRCR); 2180 add_reg(TLFRCR); 2181 add_reg(CERCR); 2182 add_reg(CEECR); 2183 add_reg(MAFCR); 2184 if (cd->rtrate) 2185 add_reg(RTRATE); 2186 if (cd->hw_checksum) 2187 add_reg(CSMR); 2188 if (cd->select_mii) 2189 add_reg(RMII_MII); 2190 if (cd->tsu) { 2191 add_tsu_reg(ARSTR); 2192 add_tsu_reg(TSU_CTRST); 2193 add_tsu_reg(TSU_FWEN0); 2194 add_tsu_reg(TSU_FWEN1); 2195 add_tsu_reg(TSU_FCM); 2196 add_tsu_reg(TSU_BSYSL0); 2197 add_tsu_reg(TSU_BSYSL1); 2198 add_tsu_reg(TSU_PRISL0); 2199 add_tsu_reg(TSU_PRISL1); 2200 add_tsu_reg(TSU_FWSL0); 2201 add_tsu_reg(TSU_FWSL1); 2202 add_tsu_reg(TSU_FWSLC); 2203 add_tsu_reg(TSU_QTAGM0); 2204 add_tsu_reg(TSU_QTAGM1); 2205 add_tsu_reg(TSU_FWSR); 2206 add_tsu_reg(TSU_FWINMK); 2207 add_tsu_reg(TSU_ADQT0); 2208 add_tsu_reg(TSU_ADQT1); 2209 add_tsu_reg(TSU_VTAG0); 2210 add_tsu_reg(TSU_VTAG1); 2211 add_tsu_reg(TSU_ADSBSY); 2212 add_tsu_reg(TSU_TEN); 2213 add_tsu_reg(TSU_POST1); 2214 add_tsu_reg(TSU_POST2); 2215 add_tsu_reg(TSU_POST3); 2216 add_tsu_reg(TSU_POST4); 2217 /* This is the start of a table, not just a single register. */ 2218 if (buf) { 2219 unsigned int i; 2220 2221 mark_reg_valid(TSU_ADRH0); 2222 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2223 *buf++ = ioread32(mdp->tsu_addr + 2224 mdp->reg_offset[TSU_ADRH0] + 2225 i * 4); 2226 } 2227 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2228 } 2229 2230 #undef mark_reg_valid 2231 #undef add_reg_from 2232 #undef add_reg 2233 #undef add_tsu_reg 2234 2235 return len * 4; 2236 } 2237 2238 static int sh_eth_get_regs_len(struct net_device *ndev) 2239 { 2240 return __sh_eth_get_regs(ndev, NULL); 2241 } 2242 2243 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2244 void *buf) 2245 { 2246 struct sh_eth_private *mdp = netdev_priv(ndev); 2247 2248 regs->version = SH_ETH_REG_DUMP_VERSION; 2249 2250 pm_runtime_get_sync(&mdp->pdev->dev); 2251 __sh_eth_get_regs(ndev, buf); 2252 pm_runtime_put_sync(&mdp->pdev->dev); 2253 } 2254 2255 static int sh_eth_nway_reset(struct net_device *ndev) 2256 { 2257 struct sh_eth_private *mdp = netdev_priv(ndev); 2258 unsigned long flags; 2259 int ret; 2260 2261 if (!ndev->phydev) 2262 return -ENODEV; 2263 2264 spin_lock_irqsave(&mdp->lock, flags); 2265 ret = phy_start_aneg(ndev->phydev); 2266 spin_unlock_irqrestore(&mdp->lock, flags); 2267 2268 return ret; 2269 } 2270 2271 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2272 { 2273 struct sh_eth_private *mdp = netdev_priv(ndev); 2274 return mdp->msg_enable; 2275 } 2276 2277 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2278 { 2279 struct sh_eth_private *mdp = netdev_priv(ndev); 2280 mdp->msg_enable = value; 2281 } 2282 2283 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2284 "rx_current", "tx_current", 2285 "rx_dirty", "tx_dirty", 2286 }; 2287 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2288 2289 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2290 { 2291 switch (sset) { 2292 case ETH_SS_STATS: 2293 return SH_ETH_STATS_LEN; 2294 default: 2295 return -EOPNOTSUPP; 2296 } 2297 } 2298 2299 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2300 struct ethtool_stats *stats, u64 *data) 2301 { 2302 struct sh_eth_private *mdp = netdev_priv(ndev); 2303 int i = 0; 2304 2305 /* device-specific stats */ 2306 data[i++] = mdp->cur_rx; 2307 data[i++] = mdp->cur_tx; 2308 data[i++] = mdp->dirty_rx; 2309 data[i++] = mdp->dirty_tx; 2310 } 2311 2312 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2313 { 2314 switch (stringset) { 2315 case ETH_SS_STATS: 2316 memcpy(data, *sh_eth_gstrings_stats, 2317 sizeof(sh_eth_gstrings_stats)); 2318 break; 2319 } 2320 } 2321 2322 static void sh_eth_get_ringparam(struct net_device *ndev, 2323 struct ethtool_ringparam *ring) 2324 { 2325 struct sh_eth_private *mdp = netdev_priv(ndev); 2326 2327 ring->rx_max_pending = RX_RING_MAX; 2328 ring->tx_max_pending = TX_RING_MAX; 2329 ring->rx_pending = mdp->num_rx_ring; 2330 ring->tx_pending = mdp->num_tx_ring; 2331 } 2332 2333 static int sh_eth_set_ringparam(struct net_device *ndev, 2334 struct ethtool_ringparam *ring) 2335 { 2336 struct sh_eth_private *mdp = netdev_priv(ndev); 2337 int ret; 2338 2339 if (ring->tx_pending > TX_RING_MAX || 2340 ring->rx_pending > RX_RING_MAX || 2341 ring->tx_pending < TX_RING_MIN || 2342 ring->rx_pending < RX_RING_MIN) 2343 return -EINVAL; 2344 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2345 return -EINVAL; 2346 2347 if (netif_running(ndev)) { 2348 netif_device_detach(ndev); 2349 netif_tx_disable(ndev); 2350 2351 /* Serialise with the interrupt handler and NAPI, then 2352 * disable interrupts. We have to clear the 2353 * irq_enabled flag first to ensure that interrupts 2354 * won't be re-enabled. 2355 */ 2356 mdp->irq_enabled = false; 2357 synchronize_irq(ndev->irq); 2358 napi_synchronize(&mdp->napi); 2359 sh_eth_write(ndev, 0x0000, EESIPR); 2360 2361 sh_eth_dev_exit(ndev); 2362 2363 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2364 sh_eth_ring_free(ndev); 2365 } 2366 2367 /* Set new parameters */ 2368 mdp->num_rx_ring = ring->rx_pending; 2369 mdp->num_tx_ring = ring->tx_pending; 2370 2371 if (netif_running(ndev)) { 2372 ret = sh_eth_ring_init(ndev); 2373 if (ret < 0) { 2374 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2375 __func__); 2376 return ret; 2377 } 2378 ret = sh_eth_dev_init(ndev); 2379 if (ret < 0) { 2380 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2381 __func__); 2382 return ret; 2383 } 2384 2385 netif_device_attach(ndev); 2386 } 2387 2388 return 0; 2389 } 2390 2391 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2392 { 2393 struct sh_eth_private *mdp = netdev_priv(ndev); 2394 2395 wol->supported = 0; 2396 wol->wolopts = 0; 2397 2398 if (mdp->cd->magic) { 2399 wol->supported = WAKE_MAGIC; 2400 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2401 } 2402 } 2403 2404 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2405 { 2406 struct sh_eth_private *mdp = netdev_priv(ndev); 2407 2408 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC) 2409 return -EOPNOTSUPP; 2410 2411 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2412 2413 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2414 2415 return 0; 2416 } 2417 2418 static const struct ethtool_ops sh_eth_ethtool_ops = { 2419 .get_regs_len = sh_eth_get_regs_len, 2420 .get_regs = sh_eth_get_regs, 2421 .nway_reset = sh_eth_nway_reset, 2422 .get_msglevel = sh_eth_get_msglevel, 2423 .set_msglevel = sh_eth_set_msglevel, 2424 .get_link = ethtool_op_get_link, 2425 .get_strings = sh_eth_get_strings, 2426 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2427 .get_sset_count = sh_eth_get_sset_count, 2428 .get_ringparam = sh_eth_get_ringparam, 2429 .set_ringparam = sh_eth_set_ringparam, 2430 .get_link_ksettings = sh_eth_get_link_ksettings, 2431 .set_link_ksettings = sh_eth_set_link_ksettings, 2432 .get_wol = sh_eth_get_wol, 2433 .set_wol = sh_eth_set_wol, 2434 }; 2435 2436 /* network device open function */ 2437 static int sh_eth_open(struct net_device *ndev) 2438 { 2439 struct sh_eth_private *mdp = netdev_priv(ndev); 2440 int ret; 2441 2442 pm_runtime_get_sync(&mdp->pdev->dev); 2443 2444 napi_enable(&mdp->napi); 2445 2446 ret = request_irq(ndev->irq, sh_eth_interrupt, 2447 mdp->cd->irq_flags, ndev->name, ndev); 2448 if (ret) { 2449 netdev_err(ndev, "Can not assign IRQ number\n"); 2450 goto out_napi_off; 2451 } 2452 2453 /* Descriptor set */ 2454 ret = sh_eth_ring_init(ndev); 2455 if (ret) 2456 goto out_free_irq; 2457 2458 /* device init */ 2459 ret = sh_eth_dev_init(ndev); 2460 if (ret) 2461 goto out_free_irq; 2462 2463 /* PHY control start*/ 2464 ret = sh_eth_phy_start(ndev); 2465 if (ret) 2466 goto out_free_irq; 2467 2468 netif_start_queue(ndev); 2469 2470 mdp->is_opened = 1; 2471 2472 return ret; 2473 2474 out_free_irq: 2475 free_irq(ndev->irq, ndev); 2476 out_napi_off: 2477 napi_disable(&mdp->napi); 2478 pm_runtime_put_sync(&mdp->pdev->dev); 2479 return ret; 2480 } 2481 2482 /* Timeout function */ 2483 static void sh_eth_tx_timeout(struct net_device *ndev) 2484 { 2485 struct sh_eth_private *mdp = netdev_priv(ndev); 2486 struct sh_eth_rxdesc *rxdesc; 2487 int i; 2488 2489 netif_stop_queue(ndev); 2490 2491 netif_err(mdp, timer, ndev, 2492 "transmit timed out, status %8.8x, resetting...\n", 2493 sh_eth_read(ndev, EESR)); 2494 2495 /* tx_errors count up */ 2496 ndev->stats.tx_errors++; 2497 2498 /* Free all the skbuffs in the Rx queue. */ 2499 for (i = 0; i < mdp->num_rx_ring; i++) { 2500 rxdesc = &mdp->rx_ring[i]; 2501 rxdesc->status = cpu_to_le32(0); 2502 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2503 dev_kfree_skb(mdp->rx_skbuff[i]); 2504 mdp->rx_skbuff[i] = NULL; 2505 } 2506 for (i = 0; i < mdp->num_tx_ring; i++) { 2507 dev_kfree_skb(mdp->tx_skbuff[i]); 2508 mdp->tx_skbuff[i] = NULL; 2509 } 2510 2511 /* device init */ 2512 sh_eth_dev_init(ndev); 2513 2514 netif_start_queue(ndev); 2515 } 2516 2517 /* Packet transmit function */ 2518 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2519 { 2520 struct sh_eth_private *mdp = netdev_priv(ndev); 2521 struct sh_eth_txdesc *txdesc; 2522 dma_addr_t dma_addr; 2523 u32 entry; 2524 unsigned long flags; 2525 2526 spin_lock_irqsave(&mdp->lock, flags); 2527 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2528 if (!sh_eth_tx_free(ndev, true)) { 2529 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2530 netif_stop_queue(ndev); 2531 spin_unlock_irqrestore(&mdp->lock, flags); 2532 return NETDEV_TX_BUSY; 2533 } 2534 } 2535 spin_unlock_irqrestore(&mdp->lock, flags); 2536 2537 if (skb_put_padto(skb, ETH_ZLEN)) 2538 return NETDEV_TX_OK; 2539 2540 entry = mdp->cur_tx % mdp->num_tx_ring; 2541 mdp->tx_skbuff[entry] = skb; 2542 txdesc = &mdp->tx_ring[entry]; 2543 /* soft swap. */ 2544 if (!mdp->cd->hw_swap) 2545 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2546 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, 2547 DMA_TO_DEVICE); 2548 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 2549 kfree_skb(skb); 2550 return NETDEV_TX_OK; 2551 } 2552 txdesc->addr = cpu_to_le32(dma_addr); 2553 txdesc->len = cpu_to_le32(skb->len << 16); 2554 2555 dma_wmb(); /* TACT bit must be set after all the above writes */ 2556 if (entry >= mdp->num_tx_ring - 1) 2557 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2558 else 2559 txdesc->status |= cpu_to_le32(TD_TACT); 2560 2561 mdp->cur_tx++; 2562 2563 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns)) 2564 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 2565 2566 return NETDEV_TX_OK; 2567 } 2568 2569 /* The statistics registers have write-clear behaviour, which means we 2570 * will lose any increment between the read and write. We mitigate 2571 * this by only clearing when we read a non-zero value, so we will 2572 * never falsely report a total of zero. 2573 */ 2574 static void 2575 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2576 { 2577 u32 delta = sh_eth_read(ndev, reg); 2578 2579 if (delta) { 2580 *stat += delta; 2581 sh_eth_write(ndev, 0, reg); 2582 } 2583 } 2584 2585 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2586 { 2587 struct sh_eth_private *mdp = netdev_priv(ndev); 2588 2589 if (mdp->cd->no_tx_cntrs) 2590 return &ndev->stats; 2591 2592 if (!mdp->is_opened) 2593 return &ndev->stats; 2594 2595 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2596 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2597 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2598 2599 if (mdp->cd->cexcr) { 2600 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2601 CERCR); 2602 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2603 CEECR); 2604 } else { 2605 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2606 CNDCR); 2607 } 2608 2609 return &ndev->stats; 2610 } 2611 2612 /* device close function */ 2613 static int sh_eth_close(struct net_device *ndev) 2614 { 2615 struct sh_eth_private *mdp = netdev_priv(ndev); 2616 2617 netif_stop_queue(ndev); 2618 2619 /* Serialise with the interrupt handler and NAPI, then disable 2620 * interrupts. We have to clear the irq_enabled flag first to 2621 * ensure that interrupts won't be re-enabled. 2622 */ 2623 mdp->irq_enabled = false; 2624 synchronize_irq(ndev->irq); 2625 napi_disable(&mdp->napi); 2626 sh_eth_write(ndev, 0x0000, EESIPR); 2627 2628 sh_eth_dev_exit(ndev); 2629 2630 /* PHY Disconnect */ 2631 if (ndev->phydev) { 2632 phy_stop(ndev->phydev); 2633 phy_disconnect(ndev->phydev); 2634 } 2635 2636 free_irq(ndev->irq, ndev); 2637 2638 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2639 sh_eth_ring_free(ndev); 2640 2641 pm_runtime_put_sync(&mdp->pdev->dev); 2642 2643 mdp->is_opened = 0; 2644 2645 return 0; 2646 } 2647 2648 /* ioctl to device function */ 2649 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2650 { 2651 struct phy_device *phydev = ndev->phydev; 2652 2653 if (!netif_running(ndev)) 2654 return -EINVAL; 2655 2656 if (!phydev) 2657 return -ENODEV; 2658 2659 return phy_mii_ioctl(phydev, rq, cmd); 2660 } 2661 2662 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) 2663 { 2664 if (netif_running(ndev)) 2665 return -EBUSY; 2666 2667 ndev->mtu = new_mtu; 2668 netdev_update_features(ndev); 2669 2670 return 0; 2671 } 2672 2673 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2674 static u32 sh_eth_tsu_get_post_mask(int entry) 2675 { 2676 return 0x0f << (28 - ((entry % 8) * 4)); 2677 } 2678 2679 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2680 { 2681 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2682 } 2683 2684 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2685 int entry) 2686 { 2687 struct sh_eth_private *mdp = netdev_priv(ndev); 2688 int reg = TSU_POST1 + entry / 8; 2689 u32 tmp; 2690 2691 tmp = sh_eth_tsu_read(mdp, reg); 2692 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg); 2693 } 2694 2695 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2696 int entry) 2697 { 2698 struct sh_eth_private *mdp = netdev_priv(ndev); 2699 int reg = TSU_POST1 + entry / 8; 2700 u32 post_mask, ref_mask, tmp; 2701 2702 post_mask = sh_eth_tsu_get_post_mask(entry); 2703 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2704 2705 tmp = sh_eth_tsu_read(mdp, reg); 2706 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg); 2707 2708 /* If other port enables, the function returns "true" */ 2709 return tmp & ref_mask; 2710 } 2711 2712 static int sh_eth_tsu_busy(struct net_device *ndev) 2713 { 2714 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2715 struct sh_eth_private *mdp = netdev_priv(ndev); 2716 2717 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2718 udelay(10); 2719 timeout--; 2720 if (timeout <= 0) { 2721 netdev_err(ndev, "%s: timeout\n", __func__); 2722 return -ETIMEDOUT; 2723 } 2724 } 2725 2726 return 0; 2727 } 2728 2729 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2730 const u8 *addr) 2731 { 2732 u32 val; 2733 2734 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2735 iowrite32(val, reg); 2736 if (sh_eth_tsu_busy(ndev) < 0) 2737 return -EBUSY; 2738 2739 val = addr[4] << 8 | addr[5]; 2740 iowrite32(val, reg + 4); 2741 if (sh_eth_tsu_busy(ndev) < 0) 2742 return -EBUSY; 2743 2744 return 0; 2745 } 2746 2747 static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2748 { 2749 u32 val; 2750 2751 val = ioread32(reg); 2752 addr[0] = (val >> 24) & 0xff; 2753 addr[1] = (val >> 16) & 0xff; 2754 addr[2] = (val >> 8) & 0xff; 2755 addr[3] = val & 0xff; 2756 val = ioread32(reg + 4); 2757 addr[4] = (val >> 8) & 0xff; 2758 addr[5] = val & 0xff; 2759 } 2760 2761 2762 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2763 { 2764 struct sh_eth_private *mdp = netdev_priv(ndev); 2765 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2766 int i; 2767 u8 c_addr[ETH_ALEN]; 2768 2769 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2770 sh_eth_tsu_read_entry(reg_offset, c_addr); 2771 if (ether_addr_equal(addr, c_addr)) 2772 return i; 2773 } 2774 2775 return -ENOENT; 2776 } 2777 2778 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2779 { 2780 u8 blank[ETH_ALEN]; 2781 int entry; 2782 2783 memset(blank, 0, sizeof(blank)); 2784 entry = sh_eth_tsu_find_entry(ndev, blank); 2785 return (entry < 0) ? -ENOMEM : entry; 2786 } 2787 2788 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2789 int entry) 2790 { 2791 struct sh_eth_private *mdp = netdev_priv(ndev); 2792 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2793 int ret; 2794 u8 blank[ETH_ALEN]; 2795 2796 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2797 ~(1 << (31 - entry)), TSU_TEN); 2798 2799 memset(blank, 0, sizeof(blank)); 2800 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2801 if (ret < 0) 2802 return ret; 2803 return 0; 2804 } 2805 2806 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2807 { 2808 struct sh_eth_private *mdp = netdev_priv(ndev); 2809 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2810 int i, ret; 2811 2812 if (!mdp->cd->tsu) 2813 return 0; 2814 2815 i = sh_eth_tsu_find_entry(ndev, addr); 2816 if (i < 0) { 2817 /* No entry found, create one */ 2818 i = sh_eth_tsu_find_empty(ndev); 2819 if (i < 0) 2820 return -ENOMEM; 2821 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2822 if (ret < 0) 2823 return ret; 2824 2825 /* Enable the entry */ 2826 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2827 (1 << (31 - i)), TSU_TEN); 2828 } 2829 2830 /* Entry found or created, enable POST */ 2831 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2832 2833 return 0; 2834 } 2835 2836 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2837 { 2838 struct sh_eth_private *mdp = netdev_priv(ndev); 2839 int i, ret; 2840 2841 if (!mdp->cd->tsu) 2842 return 0; 2843 2844 i = sh_eth_tsu_find_entry(ndev, addr); 2845 if (i) { 2846 /* Entry found */ 2847 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2848 goto done; 2849 2850 /* Disable the entry if both ports was disabled */ 2851 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2852 if (ret < 0) 2853 return ret; 2854 } 2855 done: 2856 return 0; 2857 } 2858 2859 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2860 { 2861 struct sh_eth_private *mdp = netdev_priv(ndev); 2862 int i, ret; 2863 2864 if (!mdp->cd->tsu) 2865 return 0; 2866 2867 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2868 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2869 continue; 2870 2871 /* Disable the entry if both ports was disabled */ 2872 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2873 if (ret < 0) 2874 return ret; 2875 } 2876 2877 return 0; 2878 } 2879 2880 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2881 { 2882 struct sh_eth_private *mdp = netdev_priv(ndev); 2883 u8 addr[ETH_ALEN]; 2884 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2885 int i; 2886 2887 if (!mdp->cd->tsu) 2888 return; 2889 2890 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2891 sh_eth_tsu_read_entry(reg_offset, addr); 2892 if (is_multicast_ether_addr(addr)) 2893 sh_eth_tsu_del_entry(ndev, addr); 2894 } 2895 } 2896 2897 /* Update promiscuous flag and multicast filter */ 2898 static void sh_eth_set_rx_mode(struct net_device *ndev) 2899 { 2900 struct sh_eth_private *mdp = netdev_priv(ndev); 2901 u32 ecmr_bits; 2902 int mcast_all = 0; 2903 unsigned long flags; 2904 2905 spin_lock_irqsave(&mdp->lock, flags); 2906 /* Initial condition is MCT = 1, PRM = 0. 2907 * Depending on ndev->flags, set PRM or clear MCT 2908 */ 2909 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2910 if (mdp->cd->tsu) 2911 ecmr_bits |= ECMR_MCT; 2912 2913 if (!(ndev->flags & IFF_MULTICAST)) { 2914 sh_eth_tsu_purge_mcast(ndev); 2915 mcast_all = 1; 2916 } 2917 if (ndev->flags & IFF_ALLMULTI) { 2918 sh_eth_tsu_purge_mcast(ndev); 2919 ecmr_bits &= ~ECMR_MCT; 2920 mcast_all = 1; 2921 } 2922 2923 if (ndev->flags & IFF_PROMISC) { 2924 sh_eth_tsu_purge_all(ndev); 2925 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2926 } else if (mdp->cd->tsu) { 2927 struct netdev_hw_addr *ha; 2928 netdev_for_each_mc_addr(ha, ndev) { 2929 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2930 continue; 2931 2932 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2933 if (!mcast_all) { 2934 sh_eth_tsu_purge_mcast(ndev); 2935 ecmr_bits &= ~ECMR_MCT; 2936 mcast_all = 1; 2937 } 2938 } 2939 } 2940 } 2941 2942 /* update the ethernet mode */ 2943 sh_eth_write(ndev, ecmr_bits, ECMR); 2944 2945 spin_unlock_irqrestore(&mdp->lock, flags); 2946 } 2947 2948 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2949 { 2950 if (!mdp->port) 2951 return TSU_VTAG0; 2952 else 2953 return TSU_VTAG1; 2954 } 2955 2956 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2957 __be16 proto, u16 vid) 2958 { 2959 struct sh_eth_private *mdp = netdev_priv(ndev); 2960 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2961 2962 if (unlikely(!mdp->cd->tsu)) 2963 return -EPERM; 2964 2965 /* No filtering if vid = 0 */ 2966 if (!vid) 2967 return 0; 2968 2969 mdp->vlan_num_ids++; 2970 2971 /* The controller has one VLAN tag HW filter. So, if the filter is 2972 * already enabled, the driver disables it and the filte 2973 */ 2974 if (mdp->vlan_num_ids > 1) { 2975 /* disable VLAN filter */ 2976 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2977 return 0; 2978 } 2979 2980 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2981 vtag_reg_index); 2982 2983 return 0; 2984 } 2985 2986 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2987 __be16 proto, u16 vid) 2988 { 2989 struct sh_eth_private *mdp = netdev_priv(ndev); 2990 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2991 2992 if (unlikely(!mdp->cd->tsu)) 2993 return -EPERM; 2994 2995 /* No filtering if vid = 0 */ 2996 if (!vid) 2997 return 0; 2998 2999 mdp->vlan_num_ids--; 3000 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 3001 3002 return 0; 3003 } 3004 3005 /* SuperH's TSU register init function */ 3006 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 3007 { 3008 if (!mdp->cd->dual_port) { 3009 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3010 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 3011 TSU_FWSLC); /* Enable POST registers */ 3012 return; 3013 } 3014 3015 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 3016 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 3017 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 3018 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 3019 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 3020 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 3021 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 3022 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 3023 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 3024 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 3025 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 3026 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 3027 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 3028 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 3029 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3030 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 3031 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 3032 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 3033 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 3034 } 3035 3036 /* MDIO bus release function */ 3037 static int sh_mdio_release(struct sh_eth_private *mdp) 3038 { 3039 /* unregister mdio bus */ 3040 mdiobus_unregister(mdp->mii_bus); 3041 3042 /* free bitbang info */ 3043 free_mdio_bitbang(mdp->mii_bus); 3044 3045 return 0; 3046 } 3047 3048 /* MDIO bus init function */ 3049 static int sh_mdio_init(struct sh_eth_private *mdp, 3050 struct sh_eth_plat_data *pd) 3051 { 3052 int ret; 3053 struct bb_info *bitbang; 3054 struct platform_device *pdev = mdp->pdev; 3055 struct device *dev = &mdp->pdev->dev; 3056 3057 /* create bit control struct for PHY */ 3058 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 3059 if (!bitbang) 3060 return -ENOMEM; 3061 3062 /* bitbang init */ 3063 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 3064 bitbang->set_gate = pd->set_mdio_gate; 3065 bitbang->ctrl.ops = &bb_ops; 3066 3067 /* MII controller setting */ 3068 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 3069 if (!mdp->mii_bus) 3070 return -ENOMEM; 3071 3072 /* Hook up MII support for ethtool */ 3073 mdp->mii_bus->name = "sh_mii"; 3074 mdp->mii_bus->parent = dev; 3075 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 3076 pdev->name, pdev->id); 3077 3078 /* register MDIO bus */ 3079 if (pd->phy_irq > 0) 3080 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 3081 3082 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 3083 if (ret) 3084 goto out_free_bus; 3085 3086 return 0; 3087 3088 out_free_bus: 3089 free_mdio_bitbang(mdp->mii_bus); 3090 return ret; 3091 } 3092 3093 static const u16 *sh_eth_get_register_offset(int register_type) 3094 { 3095 const u16 *reg_offset = NULL; 3096 3097 switch (register_type) { 3098 case SH_ETH_REG_GIGABIT: 3099 reg_offset = sh_eth_offset_gigabit; 3100 break; 3101 case SH_ETH_REG_FAST_RZ: 3102 reg_offset = sh_eth_offset_fast_rz; 3103 break; 3104 case SH_ETH_REG_FAST_RCAR: 3105 reg_offset = sh_eth_offset_fast_rcar; 3106 break; 3107 case SH_ETH_REG_FAST_SH4: 3108 reg_offset = sh_eth_offset_fast_sh4; 3109 break; 3110 case SH_ETH_REG_FAST_SH3_SH2: 3111 reg_offset = sh_eth_offset_fast_sh3_sh2; 3112 break; 3113 } 3114 3115 return reg_offset; 3116 } 3117 3118 static const struct net_device_ops sh_eth_netdev_ops = { 3119 .ndo_open = sh_eth_open, 3120 .ndo_stop = sh_eth_close, 3121 .ndo_start_xmit = sh_eth_start_xmit, 3122 .ndo_get_stats = sh_eth_get_stats, 3123 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3124 .ndo_tx_timeout = sh_eth_tx_timeout, 3125 .ndo_do_ioctl = sh_eth_do_ioctl, 3126 .ndo_change_mtu = sh_eth_change_mtu, 3127 .ndo_validate_addr = eth_validate_addr, 3128 .ndo_set_mac_address = eth_mac_addr, 3129 }; 3130 3131 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3132 .ndo_open = sh_eth_open, 3133 .ndo_stop = sh_eth_close, 3134 .ndo_start_xmit = sh_eth_start_xmit, 3135 .ndo_get_stats = sh_eth_get_stats, 3136 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3137 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3138 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3139 .ndo_tx_timeout = sh_eth_tx_timeout, 3140 .ndo_do_ioctl = sh_eth_do_ioctl, 3141 .ndo_change_mtu = sh_eth_change_mtu, 3142 .ndo_validate_addr = eth_validate_addr, 3143 .ndo_set_mac_address = eth_mac_addr, 3144 }; 3145 3146 #ifdef CONFIG_OF 3147 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3148 { 3149 struct device_node *np = dev->of_node; 3150 struct sh_eth_plat_data *pdata; 3151 const char *mac_addr; 3152 3153 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3154 if (!pdata) 3155 return NULL; 3156 3157 pdata->phy_interface = of_get_phy_mode(np); 3158 3159 mac_addr = of_get_mac_address(np); 3160 if (mac_addr) 3161 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 3162 3163 pdata->no_ether_link = 3164 of_property_read_bool(np, "renesas,no-ether-link"); 3165 pdata->ether_link_active_low = 3166 of_property_read_bool(np, "renesas,ether-link-active-low"); 3167 3168 return pdata; 3169 } 3170 3171 static const struct of_device_id sh_eth_match_table[] = { 3172 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3173 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data }, 3174 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data }, 3175 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data }, 3176 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data }, 3177 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data }, 3178 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data }, 3179 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data }, 3180 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data }, 3181 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data }, 3182 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3183 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data }, 3184 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data }, 3185 { } 3186 }; 3187 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3188 #else 3189 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3190 { 3191 return NULL; 3192 } 3193 #endif 3194 3195 static int sh_eth_drv_probe(struct platform_device *pdev) 3196 { 3197 struct resource *res; 3198 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3199 const struct platform_device_id *id = platform_get_device_id(pdev); 3200 struct sh_eth_private *mdp; 3201 struct net_device *ndev; 3202 int ret; 3203 3204 /* get base addr */ 3205 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3206 3207 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3208 if (!ndev) 3209 return -ENOMEM; 3210 3211 pm_runtime_enable(&pdev->dev); 3212 pm_runtime_get_sync(&pdev->dev); 3213 3214 ret = platform_get_irq(pdev, 0); 3215 if (ret < 0) 3216 goto out_release; 3217 ndev->irq = ret; 3218 3219 SET_NETDEV_DEV(ndev, &pdev->dev); 3220 3221 mdp = netdev_priv(ndev); 3222 mdp->num_tx_ring = TX_RING_SIZE; 3223 mdp->num_rx_ring = RX_RING_SIZE; 3224 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3225 if (IS_ERR(mdp->addr)) { 3226 ret = PTR_ERR(mdp->addr); 3227 goto out_release; 3228 } 3229 3230 ndev->base_addr = res->start; 3231 3232 spin_lock_init(&mdp->lock); 3233 mdp->pdev = pdev; 3234 3235 if (pdev->dev.of_node) 3236 pd = sh_eth_parse_dt(&pdev->dev); 3237 if (!pd) { 3238 dev_err(&pdev->dev, "no platform data\n"); 3239 ret = -EINVAL; 3240 goto out_release; 3241 } 3242 3243 /* get PHY ID */ 3244 mdp->phy_id = pd->phy; 3245 mdp->phy_interface = pd->phy_interface; 3246 mdp->no_ether_link = pd->no_ether_link; 3247 mdp->ether_link_active_low = pd->ether_link_active_low; 3248 3249 /* set cpu data */ 3250 if (id) 3251 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3252 else 3253 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3254 3255 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3256 if (!mdp->reg_offset) { 3257 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3258 mdp->cd->register_type); 3259 ret = -EINVAL; 3260 goto out_release; 3261 } 3262 sh_eth_set_default_cpu_data(mdp->cd); 3263 3264 /* User's manual states max MTU should be 2048 but due to the 3265 * alignment calculations in sh_eth_ring_init() the practical 3266 * MTU is a bit less. Maybe this can be optimized some more. 3267 */ 3268 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3269 ndev->min_mtu = ETH_MIN_MTU; 3270 3271 /* set function */ 3272 if (mdp->cd->tsu) 3273 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3274 else 3275 ndev->netdev_ops = &sh_eth_netdev_ops; 3276 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3277 ndev->watchdog_timeo = TX_TIMEOUT; 3278 3279 /* debug message level */ 3280 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3281 3282 /* read and set MAC address */ 3283 read_mac_address(ndev, pd->mac_addr); 3284 if (!is_valid_ether_addr(ndev->dev_addr)) { 3285 dev_warn(&pdev->dev, 3286 "no valid MAC address supplied, using a random one.\n"); 3287 eth_hw_addr_random(ndev); 3288 } 3289 3290 if (mdp->cd->tsu) { 3291 int port = pdev->id < 0 ? 0 : pdev->id % 2; 3292 struct resource *rtsu; 3293 3294 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3295 if (!rtsu) { 3296 dev_err(&pdev->dev, "no TSU resource\n"); 3297 ret = -ENODEV; 3298 goto out_release; 3299 } 3300 /* We can only request the TSU region for the first port 3301 * of the two sharing this TSU for the probe to succeed... 3302 */ 3303 if (port == 0 && 3304 !devm_request_mem_region(&pdev->dev, rtsu->start, 3305 resource_size(rtsu), 3306 dev_name(&pdev->dev))) { 3307 dev_err(&pdev->dev, "can't request TSU resource.\n"); 3308 ret = -EBUSY; 3309 goto out_release; 3310 } 3311 /* ioremap the TSU registers */ 3312 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, 3313 resource_size(rtsu)); 3314 if (!mdp->tsu_addr) { 3315 dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); 3316 ret = -ENOMEM; 3317 goto out_release; 3318 } 3319 mdp->port = port; 3320 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 3321 3322 /* Need to init only the first port of the two sharing a TSU */ 3323 if (port == 0) { 3324 if (mdp->cd->chip_reset) 3325 mdp->cd->chip_reset(ndev); 3326 3327 /* TSU init (Init only)*/ 3328 sh_eth_tsu_init(mdp); 3329 } 3330 } 3331 3332 if (mdp->cd->rmiimode) 3333 sh_eth_write(ndev, 0x1, RMIIMODE); 3334 3335 /* MDIO bus init */ 3336 ret = sh_mdio_init(mdp, pd); 3337 if (ret) { 3338 if (ret != -EPROBE_DEFER) 3339 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret); 3340 goto out_release; 3341 } 3342 3343 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3344 3345 /* network device register */ 3346 ret = register_netdev(ndev); 3347 if (ret) 3348 goto out_napi_del; 3349 3350 if (mdp->cd->magic) 3351 device_set_wakeup_capable(&pdev->dev, 1); 3352 3353 /* print device information */ 3354 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3355 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3356 3357 pm_runtime_put(&pdev->dev); 3358 platform_set_drvdata(pdev, ndev); 3359 3360 return ret; 3361 3362 out_napi_del: 3363 netif_napi_del(&mdp->napi); 3364 sh_mdio_release(mdp); 3365 3366 out_release: 3367 /* net_dev free */ 3368 free_netdev(ndev); 3369 3370 pm_runtime_put(&pdev->dev); 3371 pm_runtime_disable(&pdev->dev); 3372 return ret; 3373 } 3374 3375 static int sh_eth_drv_remove(struct platform_device *pdev) 3376 { 3377 struct net_device *ndev = platform_get_drvdata(pdev); 3378 struct sh_eth_private *mdp = netdev_priv(ndev); 3379 3380 unregister_netdev(ndev); 3381 netif_napi_del(&mdp->napi); 3382 sh_mdio_release(mdp); 3383 pm_runtime_disable(&pdev->dev); 3384 free_netdev(ndev); 3385 3386 return 0; 3387 } 3388 3389 #ifdef CONFIG_PM 3390 #ifdef CONFIG_PM_SLEEP 3391 static int sh_eth_wol_setup(struct net_device *ndev) 3392 { 3393 struct sh_eth_private *mdp = netdev_priv(ndev); 3394 3395 /* Only allow ECI interrupts */ 3396 synchronize_irq(ndev->irq); 3397 napi_disable(&mdp->napi); 3398 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3399 3400 /* Enable MagicPacket */ 3401 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3402 3403 return enable_irq_wake(ndev->irq); 3404 } 3405 3406 static int sh_eth_wol_restore(struct net_device *ndev) 3407 { 3408 struct sh_eth_private *mdp = netdev_priv(ndev); 3409 int ret; 3410 3411 napi_enable(&mdp->napi); 3412 3413 /* Disable MagicPacket */ 3414 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3415 3416 /* The device needs to be reset to restore MagicPacket logic 3417 * for next wakeup. If we close and open the device it will 3418 * both be reset and all registers restored. This is what 3419 * happens during suspend and resume without WoL enabled. 3420 */ 3421 ret = sh_eth_close(ndev); 3422 if (ret < 0) 3423 return ret; 3424 ret = sh_eth_open(ndev); 3425 if (ret < 0) 3426 return ret; 3427 3428 return disable_irq_wake(ndev->irq); 3429 } 3430 3431 static int sh_eth_suspend(struct device *dev) 3432 { 3433 struct net_device *ndev = dev_get_drvdata(dev); 3434 struct sh_eth_private *mdp = netdev_priv(ndev); 3435 int ret = 0; 3436 3437 if (!netif_running(ndev)) 3438 return 0; 3439 3440 netif_device_detach(ndev); 3441 3442 if (mdp->wol_enabled) 3443 ret = sh_eth_wol_setup(ndev); 3444 else 3445 ret = sh_eth_close(ndev); 3446 3447 return ret; 3448 } 3449 3450 static int sh_eth_resume(struct device *dev) 3451 { 3452 struct net_device *ndev = dev_get_drvdata(dev); 3453 struct sh_eth_private *mdp = netdev_priv(ndev); 3454 int ret = 0; 3455 3456 if (!netif_running(ndev)) 3457 return 0; 3458 3459 if (mdp->wol_enabled) 3460 ret = sh_eth_wol_restore(ndev); 3461 else 3462 ret = sh_eth_open(ndev); 3463 3464 if (ret < 0) 3465 return ret; 3466 3467 netif_device_attach(ndev); 3468 3469 return ret; 3470 } 3471 #endif 3472 3473 static int sh_eth_runtime_nop(struct device *dev) 3474 { 3475 /* Runtime PM callback shared between ->runtime_suspend() 3476 * and ->runtime_resume(). Simply returns success. 3477 * 3478 * This driver re-initializes all registers after 3479 * pm_runtime_get_sync() anyway so there is no need 3480 * to save and restore registers here. 3481 */ 3482 return 0; 3483 } 3484 3485 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3486 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3487 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3488 }; 3489 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3490 #else 3491 #define SH_ETH_PM_OPS NULL 3492 #endif 3493 3494 static const struct platform_device_id sh_eth_id_table[] = { 3495 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3496 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3497 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3498 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3499 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3500 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3501 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3502 { } 3503 }; 3504 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3505 3506 static struct platform_driver sh_eth_driver = { 3507 .probe = sh_eth_drv_probe, 3508 .remove = sh_eth_drv_remove, 3509 .id_table = sh_eth_id_table, 3510 .driver = { 3511 .name = CARDNAME, 3512 .pm = SH_ETH_PM_OPS, 3513 .of_match_table = of_match_ptr(sh_eth_match_table), 3514 }, 3515 }; 3516 3517 module_platform_driver(sh_eth_driver); 3518 3519 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3520 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3521 MODULE_LICENSE("GPL v2"); 3522