1 /* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2014 Renesas Electronics Corporation 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2014 Renesas Solutions Corp. 6 * Copyright (C) 2013-2014 Cogent Embedded, Inc. 7 * Copyright (C) 2014 Codethink Limited 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 */ 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/etherdevice.h> 28 #include <linux/delay.h> 29 #include <linux/platform_device.h> 30 #include <linux/mdio-bitbang.h> 31 #include <linux/netdevice.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_net.h> 36 #include <linux/phy.h> 37 #include <linux/cache.h> 38 #include <linux/io.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/slab.h> 41 #include <linux/ethtool.h> 42 #include <linux/if_vlan.h> 43 #include <linux/clk.h> 44 #include <linux/sh_eth.h> 45 #include <linux/of_mdio.h> 46 47 #include "sh_eth.h" 48 49 #define SH_ETH_DEF_MSG_ENABLE \ 50 (NETIF_MSG_LINK | \ 51 NETIF_MSG_TIMER | \ 52 NETIF_MSG_RX_ERR| \ 53 NETIF_MSG_TX_ERR) 54 55 #define SH_ETH_OFFSET_INVALID ((u16)~0) 56 57 #define SH_ETH_OFFSET_DEFAULTS \ 58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 59 60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 61 SH_ETH_OFFSET_DEFAULTS, 62 63 [EDSR] = 0x0000, 64 [EDMR] = 0x0400, 65 [EDTRR] = 0x0408, 66 [EDRRR] = 0x0410, 67 [EESR] = 0x0428, 68 [EESIPR] = 0x0430, 69 [TDLAR] = 0x0010, 70 [TDFAR] = 0x0014, 71 [TDFXR] = 0x0018, 72 [TDFFR] = 0x001c, 73 [RDLAR] = 0x0030, 74 [RDFAR] = 0x0034, 75 [RDFXR] = 0x0038, 76 [RDFFR] = 0x003c, 77 [TRSCER] = 0x0438, 78 [RMFCR] = 0x0440, 79 [TFTR] = 0x0448, 80 [FDR] = 0x0450, 81 [RMCR] = 0x0458, 82 [RPADIR] = 0x0460, 83 [FCFTR] = 0x0468, 84 [CSMR] = 0x04E4, 85 86 [ECMR] = 0x0500, 87 [ECSR] = 0x0510, 88 [ECSIPR] = 0x0518, 89 [PIR] = 0x0520, 90 [PSR] = 0x0528, 91 [PIPR] = 0x052c, 92 [RFLR] = 0x0508, 93 [APR] = 0x0554, 94 [MPR] = 0x0558, 95 [PFTCR] = 0x055c, 96 [PFRCR] = 0x0560, 97 [TPAUSER] = 0x0564, 98 [GECMR] = 0x05b0, 99 [BCULR] = 0x05b4, 100 [MAHR] = 0x05c0, 101 [MALR] = 0x05c8, 102 [TROCR] = 0x0700, 103 [CDCR] = 0x0708, 104 [LCCR] = 0x0710, 105 [CEFCR] = 0x0740, 106 [FRECR] = 0x0748, 107 [TSFRCR] = 0x0750, 108 [TLFRCR] = 0x0758, 109 [RFCR] = 0x0760, 110 [CERCR] = 0x0768, 111 [CEECR] = 0x0770, 112 [MAFCR] = 0x0778, 113 [RMII_MII] = 0x0790, 114 115 [ARSTR] = 0x0000, 116 [TSU_CTRST] = 0x0004, 117 [TSU_FWEN0] = 0x0010, 118 [TSU_FWEN1] = 0x0014, 119 [TSU_FCM] = 0x0018, 120 [TSU_BSYSL0] = 0x0020, 121 [TSU_BSYSL1] = 0x0024, 122 [TSU_PRISL0] = 0x0028, 123 [TSU_PRISL1] = 0x002c, 124 [TSU_FWSL0] = 0x0030, 125 [TSU_FWSL1] = 0x0034, 126 [TSU_FWSLC] = 0x0038, 127 [TSU_QTAG0] = 0x0040, 128 [TSU_QTAG1] = 0x0044, 129 [TSU_FWSR] = 0x0050, 130 [TSU_FWINMK] = 0x0054, 131 [TSU_ADQT0] = 0x0048, 132 [TSU_ADQT1] = 0x004c, 133 [TSU_VTAG0] = 0x0058, 134 [TSU_VTAG1] = 0x005c, 135 [TSU_ADSBSY] = 0x0060, 136 [TSU_TEN] = 0x0064, 137 [TSU_POST1] = 0x0070, 138 [TSU_POST2] = 0x0074, 139 [TSU_POST3] = 0x0078, 140 [TSU_POST4] = 0x007c, 141 [TSU_ADRH0] = 0x0100, 142 143 [TXNLCR0] = 0x0080, 144 [TXALCR0] = 0x0084, 145 [RXNLCR0] = 0x0088, 146 [RXALCR0] = 0x008c, 147 [FWNLCR0] = 0x0090, 148 [FWALCR0] = 0x0094, 149 [TXNLCR1] = 0x00a0, 150 [TXALCR1] = 0x00a0, 151 [RXNLCR1] = 0x00a8, 152 [RXALCR1] = 0x00ac, 153 [FWNLCR1] = 0x00b0, 154 [FWALCR1] = 0x00b4, 155 }; 156 157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 158 SH_ETH_OFFSET_DEFAULTS, 159 160 [EDSR] = 0x0000, 161 [EDMR] = 0x0400, 162 [EDTRR] = 0x0408, 163 [EDRRR] = 0x0410, 164 [EESR] = 0x0428, 165 [EESIPR] = 0x0430, 166 [TDLAR] = 0x0010, 167 [TDFAR] = 0x0014, 168 [TDFXR] = 0x0018, 169 [TDFFR] = 0x001c, 170 [RDLAR] = 0x0030, 171 [RDFAR] = 0x0034, 172 [RDFXR] = 0x0038, 173 [RDFFR] = 0x003c, 174 [TRSCER] = 0x0438, 175 [RMFCR] = 0x0440, 176 [TFTR] = 0x0448, 177 [FDR] = 0x0450, 178 [RMCR] = 0x0458, 179 [RPADIR] = 0x0460, 180 [FCFTR] = 0x0468, 181 [CSMR] = 0x04E4, 182 183 [ECMR] = 0x0500, 184 [RFLR] = 0x0508, 185 [ECSR] = 0x0510, 186 [ECSIPR] = 0x0518, 187 [PIR] = 0x0520, 188 [APR] = 0x0554, 189 [MPR] = 0x0558, 190 [PFTCR] = 0x055c, 191 [PFRCR] = 0x0560, 192 [TPAUSER] = 0x0564, 193 [MAHR] = 0x05c0, 194 [MALR] = 0x05c8, 195 [CEFCR] = 0x0740, 196 [FRECR] = 0x0748, 197 [TSFRCR] = 0x0750, 198 [TLFRCR] = 0x0758, 199 [RFCR] = 0x0760, 200 [MAFCR] = 0x0778, 201 202 [ARSTR] = 0x0000, 203 [TSU_CTRST] = 0x0004, 204 [TSU_VTAG0] = 0x0058, 205 [TSU_ADSBSY] = 0x0060, 206 [TSU_TEN] = 0x0064, 207 [TSU_ADRH0] = 0x0100, 208 209 [TXNLCR0] = 0x0080, 210 [TXALCR0] = 0x0084, 211 [RXNLCR0] = 0x0088, 212 [RXALCR0] = 0x008C, 213 }; 214 215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 216 SH_ETH_OFFSET_DEFAULTS, 217 218 [ECMR] = 0x0300, 219 [RFLR] = 0x0308, 220 [ECSR] = 0x0310, 221 [ECSIPR] = 0x0318, 222 [PIR] = 0x0320, 223 [PSR] = 0x0328, 224 [RDMLR] = 0x0340, 225 [IPGR] = 0x0350, 226 [APR] = 0x0354, 227 [MPR] = 0x0358, 228 [RFCF] = 0x0360, 229 [TPAUSER] = 0x0364, 230 [TPAUSECR] = 0x0368, 231 [MAHR] = 0x03c0, 232 [MALR] = 0x03c8, 233 [TROCR] = 0x03d0, 234 [CDCR] = 0x03d4, 235 [LCCR] = 0x03d8, 236 [CNDCR] = 0x03dc, 237 [CEFCR] = 0x03e4, 238 [FRECR] = 0x03e8, 239 [TSFRCR] = 0x03ec, 240 [TLFRCR] = 0x03f0, 241 [RFCR] = 0x03f4, 242 [MAFCR] = 0x03f8, 243 244 [EDMR] = 0x0200, 245 [EDTRR] = 0x0208, 246 [EDRRR] = 0x0210, 247 [TDLAR] = 0x0218, 248 [RDLAR] = 0x0220, 249 [EESR] = 0x0228, 250 [EESIPR] = 0x0230, 251 [TRSCER] = 0x0238, 252 [RMFCR] = 0x0240, 253 [TFTR] = 0x0248, 254 [FDR] = 0x0250, 255 [RMCR] = 0x0258, 256 [TFUCR] = 0x0264, 257 [RFOCR] = 0x0268, 258 [RMIIMODE] = 0x026c, 259 [FCFTR] = 0x0270, 260 [TRIMD] = 0x027c, 261 }; 262 263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 264 SH_ETH_OFFSET_DEFAULTS, 265 266 [ECMR] = 0x0100, 267 [RFLR] = 0x0108, 268 [ECSR] = 0x0110, 269 [ECSIPR] = 0x0118, 270 [PIR] = 0x0120, 271 [PSR] = 0x0128, 272 [RDMLR] = 0x0140, 273 [IPGR] = 0x0150, 274 [APR] = 0x0154, 275 [MPR] = 0x0158, 276 [TPAUSER] = 0x0164, 277 [RFCF] = 0x0160, 278 [TPAUSECR] = 0x0168, 279 [BCFRR] = 0x016c, 280 [MAHR] = 0x01c0, 281 [MALR] = 0x01c8, 282 [TROCR] = 0x01d0, 283 [CDCR] = 0x01d4, 284 [LCCR] = 0x01d8, 285 [CNDCR] = 0x01dc, 286 [CEFCR] = 0x01e4, 287 [FRECR] = 0x01e8, 288 [TSFRCR] = 0x01ec, 289 [TLFRCR] = 0x01f0, 290 [RFCR] = 0x01f4, 291 [MAFCR] = 0x01f8, 292 [RTRATE] = 0x01fc, 293 294 [EDMR] = 0x0000, 295 [EDTRR] = 0x0008, 296 [EDRRR] = 0x0010, 297 [TDLAR] = 0x0018, 298 [RDLAR] = 0x0020, 299 [EESR] = 0x0028, 300 [EESIPR] = 0x0030, 301 [TRSCER] = 0x0038, 302 [RMFCR] = 0x0040, 303 [TFTR] = 0x0048, 304 [FDR] = 0x0050, 305 [RMCR] = 0x0058, 306 [TFUCR] = 0x0064, 307 [RFOCR] = 0x0068, 308 [FCFTR] = 0x0070, 309 [RPADIR] = 0x0078, 310 [TRIMD] = 0x007c, 311 [RBWAR] = 0x00c8, 312 [RDFAR] = 0x00cc, 313 [TBRAR] = 0x00d4, 314 [TDFAR] = 0x00d8, 315 }; 316 317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 318 SH_ETH_OFFSET_DEFAULTS, 319 320 [EDMR] = 0x0000, 321 [EDTRR] = 0x0004, 322 [EDRRR] = 0x0008, 323 [TDLAR] = 0x000c, 324 [RDLAR] = 0x0010, 325 [EESR] = 0x0014, 326 [EESIPR] = 0x0018, 327 [TRSCER] = 0x001c, 328 [RMFCR] = 0x0020, 329 [TFTR] = 0x0024, 330 [FDR] = 0x0028, 331 [RMCR] = 0x002c, 332 [EDOCR] = 0x0030, 333 [FCFTR] = 0x0034, 334 [RPADIR] = 0x0038, 335 [TRIMD] = 0x003c, 336 [RBWAR] = 0x0040, 337 [RDFAR] = 0x0044, 338 [TBRAR] = 0x004c, 339 [TDFAR] = 0x0050, 340 341 [ECMR] = 0x0160, 342 [ECSR] = 0x0164, 343 [ECSIPR] = 0x0168, 344 [PIR] = 0x016c, 345 [MAHR] = 0x0170, 346 [MALR] = 0x0174, 347 [RFLR] = 0x0178, 348 [PSR] = 0x017c, 349 [TROCR] = 0x0180, 350 [CDCR] = 0x0184, 351 [LCCR] = 0x0188, 352 [CNDCR] = 0x018c, 353 [CEFCR] = 0x0194, 354 [FRECR] = 0x0198, 355 [TSFRCR] = 0x019c, 356 [TLFRCR] = 0x01a0, 357 [RFCR] = 0x01a4, 358 [MAFCR] = 0x01a8, 359 [IPGR] = 0x01b4, 360 [APR] = 0x01b8, 361 [MPR] = 0x01bc, 362 [TPAUSER] = 0x01c4, 363 [BCFR] = 0x01cc, 364 365 [ARSTR] = 0x0000, 366 [TSU_CTRST] = 0x0004, 367 [TSU_FWEN0] = 0x0010, 368 [TSU_FWEN1] = 0x0014, 369 [TSU_FCM] = 0x0018, 370 [TSU_BSYSL0] = 0x0020, 371 [TSU_BSYSL1] = 0x0024, 372 [TSU_PRISL0] = 0x0028, 373 [TSU_PRISL1] = 0x002c, 374 [TSU_FWSL0] = 0x0030, 375 [TSU_FWSL1] = 0x0034, 376 [TSU_FWSLC] = 0x0038, 377 [TSU_QTAGM0] = 0x0040, 378 [TSU_QTAGM1] = 0x0044, 379 [TSU_ADQT0] = 0x0048, 380 [TSU_ADQT1] = 0x004c, 381 [TSU_FWSR] = 0x0050, 382 [TSU_FWINMK] = 0x0054, 383 [TSU_ADSBSY] = 0x0060, 384 [TSU_TEN] = 0x0064, 385 [TSU_POST1] = 0x0070, 386 [TSU_POST2] = 0x0074, 387 [TSU_POST3] = 0x0078, 388 [TSU_POST4] = 0x007c, 389 390 [TXNLCR0] = 0x0080, 391 [TXALCR0] = 0x0084, 392 [RXNLCR0] = 0x0088, 393 [RXALCR0] = 0x008c, 394 [FWNLCR0] = 0x0090, 395 [FWALCR0] = 0x0094, 396 [TXNLCR1] = 0x00a0, 397 [TXALCR1] = 0x00a0, 398 [RXNLCR1] = 0x00a8, 399 [RXALCR1] = 0x00ac, 400 [FWNLCR1] = 0x00b0, 401 [FWALCR1] = 0x00b4, 402 403 [TSU_ADRH0] = 0x0100, 404 }; 405 406 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 408 409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 410 { 411 struct sh_eth_private *mdp = netdev_priv(ndev); 412 u16 offset = mdp->reg_offset[enum_index]; 413 414 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 415 return; 416 417 iowrite32(data, mdp->addr + offset); 418 } 419 420 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 421 { 422 struct sh_eth_private *mdp = netdev_priv(ndev); 423 u16 offset = mdp->reg_offset[enum_index]; 424 425 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 426 return ~0U; 427 428 return ioread32(mdp->addr + offset); 429 } 430 431 static bool sh_eth_is_gether(struct sh_eth_private *mdp) 432 { 433 return mdp->reg_offset == sh_eth_offset_gigabit; 434 } 435 436 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp) 437 { 438 return mdp->reg_offset == sh_eth_offset_fast_rz; 439 } 440 441 static void sh_eth_select_mii(struct net_device *ndev) 442 { 443 u32 value = 0x0; 444 struct sh_eth_private *mdp = netdev_priv(ndev); 445 446 switch (mdp->phy_interface) { 447 case PHY_INTERFACE_MODE_GMII: 448 value = 0x2; 449 break; 450 case PHY_INTERFACE_MODE_MII: 451 value = 0x1; 452 break; 453 case PHY_INTERFACE_MODE_RMII: 454 value = 0x0; 455 break; 456 default: 457 netdev_warn(ndev, 458 "PHY interface mode was not setup. Set to MII.\n"); 459 value = 0x1; 460 break; 461 } 462 463 sh_eth_write(ndev, value, RMII_MII); 464 } 465 466 static void sh_eth_set_duplex(struct net_device *ndev) 467 { 468 struct sh_eth_private *mdp = netdev_priv(ndev); 469 470 if (mdp->duplex) /* Full */ 471 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 472 else /* Half */ 473 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 474 } 475 476 static void sh_eth_chip_reset(struct net_device *ndev) 477 { 478 struct sh_eth_private *mdp = netdev_priv(ndev); 479 480 /* reset device */ 481 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 482 mdelay(1); 483 } 484 485 static void sh_eth_set_rate_gether(struct net_device *ndev) 486 { 487 struct sh_eth_private *mdp = netdev_priv(ndev); 488 489 switch (mdp->speed) { 490 case 10: /* 10BASE */ 491 sh_eth_write(ndev, GECMR_10, GECMR); 492 break; 493 case 100:/* 100BASE */ 494 sh_eth_write(ndev, GECMR_100, GECMR); 495 break; 496 case 1000: /* 1000BASE */ 497 sh_eth_write(ndev, GECMR_1000, GECMR); 498 break; 499 default: 500 break; 501 } 502 } 503 504 #ifdef CONFIG_OF 505 /* R7S72100 */ 506 static struct sh_eth_cpu_data r7s72100_data = { 507 .chip_reset = sh_eth_chip_reset, 508 .set_duplex = sh_eth_set_duplex, 509 510 .register_type = SH_ETH_REG_FAST_RZ, 511 512 .ecsr_value = ECSR_ICD, 513 .ecsipr_value = ECSIPR_ICDIP, 514 .eesipr_value = 0xff7f009f, 515 516 .tx_check = EESR_TC1 | EESR_FTC, 517 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 518 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 519 EESR_TDE | EESR_ECI, 520 .fdr_value = 0x0000070f, 521 522 .no_psr = 1, 523 .apr = 1, 524 .mpr = 1, 525 .tpauser = 1, 526 .hw_swap = 1, 527 .rpadir = 1, 528 .rpadir_value = 2 << 16, 529 .no_trimd = 1, 530 .no_ade = 1, 531 .hw_crc = 1, 532 .tsu = 1, 533 .shift_rd0 = 1, 534 }; 535 536 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 537 { 538 struct sh_eth_private *mdp = netdev_priv(ndev); 539 540 /* reset device */ 541 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 542 mdelay(1); 543 544 sh_eth_select_mii(ndev); 545 } 546 547 /* R8A7740 */ 548 static struct sh_eth_cpu_data r8a7740_data = { 549 .chip_reset = sh_eth_chip_reset_r8a7740, 550 .set_duplex = sh_eth_set_duplex, 551 .set_rate = sh_eth_set_rate_gether, 552 553 .register_type = SH_ETH_REG_GIGABIT, 554 555 .ecsr_value = ECSR_ICD | ECSR_MPD, 556 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 557 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 558 559 .tx_check = EESR_TC1 | EESR_FTC, 560 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 561 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 562 EESR_TDE | EESR_ECI, 563 .fdr_value = 0x0000070f, 564 565 .apr = 1, 566 .mpr = 1, 567 .tpauser = 1, 568 .bculr = 1, 569 .hw_swap = 1, 570 .rpadir = 1, 571 .rpadir_value = 2 << 16, 572 .no_trimd = 1, 573 .no_ade = 1, 574 .tsu = 1, 575 .select_mii = 1, 576 .shift_rd0 = 1, 577 }; 578 579 /* There is CPU dependent code */ 580 static void sh_eth_set_rate_r8a777x(struct net_device *ndev) 581 { 582 struct sh_eth_private *mdp = netdev_priv(ndev); 583 584 switch (mdp->speed) { 585 case 10: /* 10BASE */ 586 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR); 587 break; 588 case 100:/* 100BASE */ 589 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR); 590 break; 591 default: 592 break; 593 } 594 } 595 596 /* R8A7778/9 */ 597 static struct sh_eth_cpu_data r8a777x_data = { 598 .set_duplex = sh_eth_set_duplex, 599 .set_rate = sh_eth_set_rate_r8a777x, 600 601 .register_type = SH_ETH_REG_FAST_RCAR, 602 603 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 604 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 605 .eesipr_value = 0x01ff009f, 606 607 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 608 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 609 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 610 EESR_ECI, 611 .fdr_value = 0x00000f0f, 612 613 .apr = 1, 614 .mpr = 1, 615 .tpauser = 1, 616 .hw_swap = 1, 617 }; 618 619 /* R8A7790/1 */ 620 static struct sh_eth_cpu_data r8a779x_data = { 621 .set_duplex = sh_eth_set_duplex, 622 .set_rate = sh_eth_set_rate_r8a777x, 623 624 .register_type = SH_ETH_REG_FAST_RCAR, 625 626 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 627 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 628 .eesipr_value = 0x01ff009f, 629 630 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 631 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 632 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 633 EESR_ECI, 634 .fdr_value = 0x00000f0f, 635 636 .trscer_err_mask = DESC_I_RINT8, 637 638 .apr = 1, 639 .mpr = 1, 640 .tpauser = 1, 641 .hw_swap = 1, 642 .rmiimode = 1, 643 }; 644 #endif /* CONFIG_OF */ 645 646 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 647 { 648 struct sh_eth_private *mdp = netdev_priv(ndev); 649 650 switch (mdp->speed) { 651 case 10: /* 10BASE */ 652 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR); 653 break; 654 case 100:/* 100BASE */ 655 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR); 656 break; 657 default: 658 break; 659 } 660 } 661 662 /* SH7724 */ 663 static struct sh_eth_cpu_data sh7724_data = { 664 .set_duplex = sh_eth_set_duplex, 665 .set_rate = sh_eth_set_rate_sh7724, 666 667 .register_type = SH_ETH_REG_FAST_SH4, 668 669 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 670 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 671 .eesipr_value = 0x01ff009f, 672 673 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 674 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 675 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 676 EESR_ECI, 677 678 .apr = 1, 679 .mpr = 1, 680 .tpauser = 1, 681 .hw_swap = 1, 682 .rpadir = 1, 683 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 684 }; 685 686 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 687 { 688 struct sh_eth_private *mdp = netdev_priv(ndev); 689 690 switch (mdp->speed) { 691 case 10: /* 10BASE */ 692 sh_eth_write(ndev, 0, RTRATE); 693 break; 694 case 100:/* 100BASE */ 695 sh_eth_write(ndev, 1, RTRATE); 696 break; 697 default: 698 break; 699 } 700 } 701 702 /* SH7757 */ 703 static struct sh_eth_cpu_data sh7757_data = { 704 .set_duplex = sh_eth_set_duplex, 705 .set_rate = sh_eth_set_rate_sh7757, 706 707 .register_type = SH_ETH_REG_FAST_SH4, 708 709 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 710 711 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 712 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 713 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 714 EESR_ECI, 715 716 .irq_flags = IRQF_SHARED, 717 .apr = 1, 718 .mpr = 1, 719 .tpauser = 1, 720 .hw_swap = 1, 721 .no_ade = 1, 722 .rpadir = 1, 723 .rpadir_value = 2 << 16, 724 .rtrate = 1, 725 }; 726 727 #define SH_GIGA_ETH_BASE 0xfee00000UL 728 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 729 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 730 static void sh_eth_chip_reset_giga(struct net_device *ndev) 731 { 732 int i; 733 u32 mahr[2], malr[2]; 734 735 /* save MAHR and MALR */ 736 for (i = 0; i < 2; i++) { 737 malr[i] = ioread32((void *)GIGA_MALR(i)); 738 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 739 } 740 741 /* reset device */ 742 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800)); 743 mdelay(1); 744 745 /* restore MAHR and MALR */ 746 for (i = 0; i < 2; i++) { 747 iowrite32(malr[i], (void *)GIGA_MALR(i)); 748 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 749 } 750 } 751 752 static void sh_eth_set_rate_giga(struct net_device *ndev) 753 { 754 struct sh_eth_private *mdp = netdev_priv(ndev); 755 756 switch (mdp->speed) { 757 case 10: /* 10BASE */ 758 sh_eth_write(ndev, 0x00000000, GECMR); 759 break; 760 case 100:/* 100BASE */ 761 sh_eth_write(ndev, 0x00000010, GECMR); 762 break; 763 case 1000: /* 1000BASE */ 764 sh_eth_write(ndev, 0x00000020, GECMR); 765 break; 766 default: 767 break; 768 } 769 } 770 771 /* SH7757(GETHERC) */ 772 static struct sh_eth_cpu_data sh7757_data_giga = { 773 .chip_reset = sh_eth_chip_reset_giga, 774 .set_duplex = sh_eth_set_duplex, 775 .set_rate = sh_eth_set_rate_giga, 776 777 .register_type = SH_ETH_REG_GIGABIT, 778 779 .ecsr_value = ECSR_ICD | ECSR_MPD, 780 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 781 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 782 783 .tx_check = EESR_TC1 | EESR_FTC, 784 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 785 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 786 EESR_TDE | EESR_ECI, 787 .fdr_value = 0x0000072f, 788 789 .irq_flags = IRQF_SHARED, 790 .apr = 1, 791 .mpr = 1, 792 .tpauser = 1, 793 .bculr = 1, 794 .hw_swap = 1, 795 .rpadir = 1, 796 .rpadir_value = 2 << 16, 797 .no_trimd = 1, 798 .no_ade = 1, 799 .tsu = 1, 800 }; 801 802 /* SH7734 */ 803 static struct sh_eth_cpu_data sh7734_data = { 804 .chip_reset = sh_eth_chip_reset, 805 .set_duplex = sh_eth_set_duplex, 806 .set_rate = sh_eth_set_rate_gether, 807 808 .register_type = SH_ETH_REG_GIGABIT, 809 810 .ecsr_value = ECSR_ICD | ECSR_MPD, 811 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 812 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 813 814 .tx_check = EESR_TC1 | EESR_FTC, 815 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 816 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 817 EESR_TDE | EESR_ECI, 818 819 .apr = 1, 820 .mpr = 1, 821 .tpauser = 1, 822 .bculr = 1, 823 .hw_swap = 1, 824 .no_trimd = 1, 825 .no_ade = 1, 826 .tsu = 1, 827 .hw_crc = 1, 828 .select_mii = 1, 829 }; 830 831 /* SH7763 */ 832 static struct sh_eth_cpu_data sh7763_data = { 833 .chip_reset = sh_eth_chip_reset, 834 .set_duplex = sh_eth_set_duplex, 835 .set_rate = sh_eth_set_rate_gether, 836 837 .register_type = SH_ETH_REG_GIGABIT, 838 839 .ecsr_value = ECSR_ICD | ECSR_MPD, 840 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 841 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 842 843 .tx_check = EESR_TC1 | EESR_FTC, 844 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 845 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 846 EESR_ECI, 847 848 .apr = 1, 849 .mpr = 1, 850 .tpauser = 1, 851 .bculr = 1, 852 .hw_swap = 1, 853 .no_trimd = 1, 854 .no_ade = 1, 855 .tsu = 1, 856 .irq_flags = IRQF_SHARED, 857 }; 858 859 static struct sh_eth_cpu_data sh7619_data = { 860 .register_type = SH_ETH_REG_FAST_SH3_SH2, 861 862 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 863 864 .apr = 1, 865 .mpr = 1, 866 .tpauser = 1, 867 .hw_swap = 1, 868 }; 869 870 static struct sh_eth_cpu_data sh771x_data = { 871 .register_type = SH_ETH_REG_FAST_SH3_SH2, 872 873 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 874 .tsu = 1, 875 }; 876 877 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 878 { 879 if (!cd->ecsr_value) 880 cd->ecsr_value = DEFAULT_ECSR_INIT; 881 882 if (!cd->ecsipr_value) 883 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 884 885 if (!cd->fcftr_value) 886 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 887 DEFAULT_FIFO_F_D_RFD; 888 889 if (!cd->fdr_value) 890 cd->fdr_value = DEFAULT_FDR_INIT; 891 892 if (!cd->tx_check) 893 cd->tx_check = DEFAULT_TX_CHECK; 894 895 if (!cd->eesr_err_check) 896 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 897 898 if (!cd->trscer_err_mask) 899 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 900 } 901 902 static int sh_eth_check_reset(struct net_device *ndev) 903 { 904 int ret = 0; 905 int cnt = 100; 906 907 while (cnt > 0) { 908 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 909 break; 910 mdelay(1); 911 cnt--; 912 } 913 if (cnt <= 0) { 914 netdev_err(ndev, "Device reset failed\n"); 915 ret = -ETIMEDOUT; 916 } 917 return ret; 918 } 919 920 static int sh_eth_reset(struct net_device *ndev) 921 { 922 struct sh_eth_private *mdp = netdev_priv(ndev); 923 int ret = 0; 924 925 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) { 926 sh_eth_write(ndev, EDSR_ENALL, EDSR); 927 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, 928 EDMR); 929 930 ret = sh_eth_check_reset(ndev); 931 if (ret) 932 return ret; 933 934 /* Table Init */ 935 sh_eth_write(ndev, 0x0, TDLAR); 936 sh_eth_write(ndev, 0x0, TDFAR); 937 sh_eth_write(ndev, 0x0, TDFXR); 938 sh_eth_write(ndev, 0x0, TDFFR); 939 sh_eth_write(ndev, 0x0, RDLAR); 940 sh_eth_write(ndev, 0x0, RDFAR); 941 sh_eth_write(ndev, 0x0, RDFXR); 942 sh_eth_write(ndev, 0x0, RDFFR); 943 944 /* Reset HW CRC register */ 945 if (mdp->cd->hw_crc) 946 sh_eth_write(ndev, 0x0, CSMR); 947 948 /* Select MII mode */ 949 if (mdp->cd->select_mii) 950 sh_eth_select_mii(ndev); 951 } else { 952 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, 953 EDMR); 954 mdelay(3); 955 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, 956 EDMR); 957 } 958 959 return ret; 960 } 961 962 static void sh_eth_set_receive_align(struct sk_buff *skb) 963 { 964 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 965 966 if (reserve) 967 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 968 } 969 970 /* Program the hardware MAC address from dev->dev_addr. */ 971 static void update_mac_address(struct net_device *ndev) 972 { 973 sh_eth_write(ndev, 974 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 975 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 976 sh_eth_write(ndev, 977 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 978 } 979 980 /* Get MAC address from SuperH MAC address register 981 * 982 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 983 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 984 * When you want use this device, you must set MAC address in bootloader. 985 * 986 */ 987 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 988 { 989 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 990 memcpy(ndev->dev_addr, mac, ETH_ALEN); 991 } else { 992 u32 mahr = sh_eth_read(ndev, MAHR); 993 u32 malr = sh_eth_read(ndev, MALR); 994 995 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 996 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 997 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 998 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 999 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 1000 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 1001 } 1002 } 1003 1004 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 1005 { 1006 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) 1007 return EDTRR_TRNS_GETHER; 1008 else 1009 return EDTRR_TRNS_ETHER; 1010 } 1011 1012 struct bb_info { 1013 void (*set_gate)(void *addr); 1014 struct mdiobb_ctrl ctrl; 1015 void *addr; 1016 }; 1017 1018 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1019 { 1020 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1021 u32 pir; 1022 1023 if (bitbang->set_gate) 1024 bitbang->set_gate(bitbang->addr); 1025 1026 pir = ioread32(bitbang->addr); 1027 if (set) 1028 pir |= mask; 1029 else 1030 pir &= ~mask; 1031 iowrite32(pir, bitbang->addr); 1032 } 1033 1034 /* Data I/O pin control */ 1035 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1036 { 1037 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1038 } 1039 1040 /* Set bit data*/ 1041 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1042 { 1043 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1044 } 1045 1046 /* Get bit data*/ 1047 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1048 { 1049 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1050 1051 if (bitbang->set_gate) 1052 bitbang->set_gate(bitbang->addr); 1053 1054 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1055 } 1056 1057 /* MDC pin control */ 1058 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1059 { 1060 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1061 } 1062 1063 /* mdio bus control struct */ 1064 static struct mdiobb_ops bb_ops = { 1065 .owner = THIS_MODULE, 1066 .set_mdc = sh_mdc_ctrl, 1067 .set_mdio_dir = sh_mmd_ctrl, 1068 .set_mdio_data = sh_set_mdio, 1069 .get_mdio_data = sh_get_mdio, 1070 }; 1071 1072 /* free skb and descriptor buffer */ 1073 static void sh_eth_ring_free(struct net_device *ndev) 1074 { 1075 struct sh_eth_private *mdp = netdev_priv(ndev); 1076 int ringsize, i; 1077 1078 /* Free Rx skb ringbuffer */ 1079 if (mdp->rx_skbuff) { 1080 for (i = 0; i < mdp->num_rx_ring; i++) 1081 dev_kfree_skb(mdp->rx_skbuff[i]); 1082 } 1083 kfree(mdp->rx_skbuff); 1084 mdp->rx_skbuff = NULL; 1085 1086 /* Free Tx skb ringbuffer */ 1087 if (mdp->tx_skbuff) { 1088 for (i = 0; i < mdp->num_tx_ring; i++) 1089 dev_kfree_skb(mdp->tx_skbuff[i]); 1090 } 1091 kfree(mdp->tx_skbuff); 1092 mdp->tx_skbuff = NULL; 1093 1094 if (mdp->rx_ring) { 1095 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1096 dma_free_coherent(NULL, ringsize, mdp->rx_ring, 1097 mdp->rx_desc_dma); 1098 mdp->rx_ring = NULL; 1099 } 1100 1101 if (mdp->tx_ring) { 1102 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1103 dma_free_coherent(NULL, ringsize, mdp->tx_ring, 1104 mdp->tx_desc_dma); 1105 mdp->tx_ring = NULL; 1106 } 1107 } 1108 1109 /* format skb and descriptor buffer */ 1110 static void sh_eth_ring_format(struct net_device *ndev) 1111 { 1112 struct sh_eth_private *mdp = netdev_priv(ndev); 1113 int i; 1114 struct sk_buff *skb; 1115 struct sh_eth_rxdesc *rxdesc = NULL; 1116 struct sh_eth_txdesc *txdesc = NULL; 1117 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1118 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1119 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1120 dma_addr_t dma_addr; 1121 u32 buf_len; 1122 1123 mdp->cur_rx = 0; 1124 mdp->cur_tx = 0; 1125 mdp->dirty_rx = 0; 1126 mdp->dirty_tx = 0; 1127 1128 memset(mdp->rx_ring, 0, rx_ringsize); 1129 1130 /* build Rx ring buffer */ 1131 for (i = 0; i < mdp->num_rx_ring; i++) { 1132 /* skb */ 1133 mdp->rx_skbuff[i] = NULL; 1134 skb = netdev_alloc_skb(ndev, skbuff_size); 1135 if (skb == NULL) 1136 break; 1137 sh_eth_set_receive_align(skb); 1138 1139 /* RX descriptor */ 1140 rxdesc = &mdp->rx_ring[i]; 1141 /* The size of the buffer is a multiple of 32 bytes. */ 1142 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1143 rxdesc->len = cpu_to_le32(buf_len << 16); 1144 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len, 1145 DMA_FROM_DEVICE); 1146 if (dma_mapping_error(&ndev->dev, dma_addr)) { 1147 kfree_skb(skb); 1148 break; 1149 } 1150 mdp->rx_skbuff[i] = skb; 1151 rxdesc->addr = cpu_to_le32(dma_addr); 1152 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1153 1154 /* Rx descriptor address set */ 1155 if (i == 0) { 1156 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1157 if (sh_eth_is_gether(mdp) || 1158 sh_eth_is_rz_fast_ether(mdp)) 1159 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1160 } 1161 } 1162 1163 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1164 1165 /* Mark the last entry as wrapping the ring. */ 1166 rxdesc->status |= cpu_to_le32(RD_RDLE); 1167 1168 memset(mdp->tx_ring, 0, tx_ringsize); 1169 1170 /* build Tx ring buffer */ 1171 for (i = 0; i < mdp->num_tx_ring; i++) { 1172 mdp->tx_skbuff[i] = NULL; 1173 txdesc = &mdp->tx_ring[i]; 1174 txdesc->status = cpu_to_le32(TD_TFP); 1175 txdesc->len = cpu_to_le32(0); 1176 if (i == 0) { 1177 /* Tx descriptor address set */ 1178 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1179 if (sh_eth_is_gether(mdp) || 1180 sh_eth_is_rz_fast_ether(mdp)) 1181 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1182 } 1183 } 1184 1185 txdesc->status |= cpu_to_le32(TD_TDLE); 1186 } 1187 1188 /* Get skb and descriptor buffer */ 1189 static int sh_eth_ring_init(struct net_device *ndev) 1190 { 1191 struct sh_eth_private *mdp = netdev_priv(ndev); 1192 int rx_ringsize, tx_ringsize; 1193 1194 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1195 * card needs room to do 8 byte alignment, +2 so we can reserve 1196 * the first 2 bytes, and +16 gets room for the status word from the 1197 * card. 1198 */ 1199 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1200 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1201 if (mdp->cd->rpadir) 1202 mdp->rx_buf_sz += NET_IP_ALIGN; 1203 1204 /* Allocate RX and TX skb rings */ 1205 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1206 GFP_KERNEL); 1207 if (!mdp->rx_skbuff) 1208 return -ENOMEM; 1209 1210 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1211 GFP_KERNEL); 1212 if (!mdp->tx_skbuff) 1213 goto ring_free; 1214 1215 /* Allocate all Rx descriptors. */ 1216 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1217 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, 1218 GFP_KERNEL); 1219 if (!mdp->rx_ring) 1220 goto ring_free; 1221 1222 mdp->dirty_rx = 0; 1223 1224 /* Allocate all Tx descriptors. */ 1225 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1226 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 1227 GFP_KERNEL); 1228 if (!mdp->tx_ring) 1229 goto ring_free; 1230 return 0; 1231 1232 ring_free: 1233 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1234 sh_eth_ring_free(ndev); 1235 1236 return -ENOMEM; 1237 } 1238 1239 static int sh_eth_dev_init(struct net_device *ndev, bool start) 1240 { 1241 int ret = 0; 1242 struct sh_eth_private *mdp = netdev_priv(ndev); 1243 1244 /* Soft Reset */ 1245 ret = sh_eth_reset(ndev); 1246 if (ret) 1247 return ret; 1248 1249 if (mdp->cd->rmiimode) 1250 sh_eth_write(ndev, 0x1, RMIIMODE); 1251 1252 /* Descriptor format */ 1253 sh_eth_ring_format(ndev); 1254 if (mdp->cd->rpadir) 1255 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1256 1257 /* all sh_eth int mask */ 1258 sh_eth_write(ndev, 0, EESIPR); 1259 1260 #if defined(__LITTLE_ENDIAN) 1261 if (mdp->cd->hw_swap) 1262 sh_eth_write(ndev, EDMR_EL, EDMR); 1263 else 1264 #endif 1265 sh_eth_write(ndev, 0, EDMR); 1266 1267 /* FIFO size set */ 1268 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1269 sh_eth_write(ndev, 0, TFTR); 1270 1271 /* Frame recv control (enable multiple-packets per rx irq) */ 1272 sh_eth_write(ndev, RMCR_RNC, RMCR); 1273 1274 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1275 1276 if (mdp->cd->bculr) 1277 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1278 1279 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1280 1281 if (!mdp->cd->no_trimd) 1282 sh_eth_write(ndev, 0, TRIMD); 1283 1284 /* Recv frame limit set register */ 1285 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1286 RFLR); 1287 1288 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); 1289 if (start) { 1290 mdp->irq_enabled = true; 1291 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1292 } 1293 1294 /* PAUSE Prohibition */ 1295 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1296 ECMR_TE | ECMR_RE, ECMR); 1297 1298 if (mdp->cd->set_rate) 1299 mdp->cd->set_rate(ndev); 1300 1301 /* E-MAC Status Register clear */ 1302 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1303 1304 /* E-MAC Interrupt Enable register */ 1305 if (start) 1306 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1307 1308 /* Set MAC address */ 1309 update_mac_address(ndev); 1310 1311 /* mask reset */ 1312 if (mdp->cd->apr) 1313 sh_eth_write(ndev, APR_AP, APR); 1314 if (mdp->cd->mpr) 1315 sh_eth_write(ndev, MPR_MP, MPR); 1316 if (mdp->cd->tpauser) 1317 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1318 1319 if (start) { 1320 /* Setting the Rx mode will start the Rx process. */ 1321 sh_eth_write(ndev, EDRRR_R, EDRRR); 1322 1323 netif_start_queue(ndev); 1324 } 1325 1326 return ret; 1327 } 1328 1329 static void sh_eth_dev_exit(struct net_device *ndev) 1330 { 1331 struct sh_eth_private *mdp = netdev_priv(ndev); 1332 int i; 1333 1334 /* Deactivate all TX descriptors, so DMA should stop at next 1335 * packet boundary if it's currently running 1336 */ 1337 for (i = 0; i < mdp->num_tx_ring; i++) 1338 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1339 1340 /* Disable TX FIFO egress to MAC */ 1341 sh_eth_rcv_snd_disable(ndev); 1342 1343 /* Stop RX DMA at next packet boundary */ 1344 sh_eth_write(ndev, 0, EDRRR); 1345 1346 /* Aside from TX DMA, we can't tell when the hardware is 1347 * really stopped, so we need to reset to make sure. 1348 * Before doing that, wait for long enough to *probably* 1349 * finish transmitting the last packet and poll stats. 1350 */ 1351 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1352 sh_eth_get_stats(ndev); 1353 sh_eth_reset(ndev); 1354 1355 /* Set MAC address again */ 1356 update_mac_address(ndev); 1357 } 1358 1359 /* free Tx skb function */ 1360 static int sh_eth_txfree(struct net_device *ndev) 1361 { 1362 struct sh_eth_private *mdp = netdev_priv(ndev); 1363 struct sh_eth_txdesc *txdesc; 1364 int free_num = 0; 1365 int entry = 0; 1366 1367 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1368 entry = mdp->dirty_tx % mdp->num_tx_ring; 1369 txdesc = &mdp->tx_ring[entry]; 1370 if (txdesc->status & cpu_to_le32(TD_TACT)) 1371 break; 1372 /* TACT bit must be checked before all the following reads */ 1373 dma_rmb(); 1374 netif_info(mdp, tx_done, ndev, 1375 "tx entry %d status 0x%08x\n", 1376 entry, le32_to_cpu(txdesc->status)); 1377 /* Free the original skb. */ 1378 if (mdp->tx_skbuff[entry]) { 1379 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr), 1380 le32_to_cpu(txdesc->len) >> 16, 1381 DMA_TO_DEVICE); 1382 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1383 mdp->tx_skbuff[entry] = NULL; 1384 free_num++; 1385 } 1386 txdesc->status = cpu_to_le32(TD_TFP); 1387 if (entry >= mdp->num_tx_ring - 1) 1388 txdesc->status |= cpu_to_le32(TD_TDLE); 1389 1390 ndev->stats.tx_packets++; 1391 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1392 } 1393 return free_num; 1394 } 1395 1396 /* Packet receive function */ 1397 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1398 { 1399 struct sh_eth_private *mdp = netdev_priv(ndev); 1400 struct sh_eth_rxdesc *rxdesc; 1401 1402 int entry = mdp->cur_rx % mdp->num_rx_ring; 1403 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1404 int limit; 1405 struct sk_buff *skb; 1406 u16 pkt_len = 0; 1407 u32 desc_status; 1408 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1409 dma_addr_t dma_addr; 1410 u32 buf_len; 1411 1412 boguscnt = min(boguscnt, *quota); 1413 limit = boguscnt; 1414 rxdesc = &mdp->rx_ring[entry]; 1415 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1416 /* RACT bit must be checked before all the following reads */ 1417 dma_rmb(); 1418 desc_status = le32_to_cpu(rxdesc->status); 1419 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1420 1421 if (--boguscnt < 0) 1422 break; 1423 1424 netif_info(mdp, rx_status, ndev, 1425 "rx entry %d status 0x%08x len %d\n", 1426 entry, desc_status, pkt_len); 1427 1428 if (!(desc_status & RDFEND)) 1429 ndev->stats.rx_length_errors++; 1430 1431 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1432 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1433 * bit 0. However, in case of the R8A7740 and R7S72100 1434 * the RFS bits are from bit 25 to bit 16. So, the 1435 * driver needs right shifting by 16. 1436 */ 1437 if (mdp->cd->shift_rd0) 1438 desc_status >>= 16; 1439 1440 skb = mdp->rx_skbuff[entry]; 1441 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1442 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1443 ndev->stats.rx_errors++; 1444 if (desc_status & RD_RFS1) 1445 ndev->stats.rx_crc_errors++; 1446 if (desc_status & RD_RFS2) 1447 ndev->stats.rx_frame_errors++; 1448 if (desc_status & RD_RFS3) 1449 ndev->stats.rx_length_errors++; 1450 if (desc_status & RD_RFS4) 1451 ndev->stats.rx_length_errors++; 1452 if (desc_status & RD_RFS6) 1453 ndev->stats.rx_missed_errors++; 1454 if (desc_status & RD_RFS10) 1455 ndev->stats.rx_over_errors++; 1456 } else if (skb) { 1457 dma_addr = le32_to_cpu(rxdesc->addr); 1458 if (!mdp->cd->hw_swap) 1459 sh_eth_soft_swap( 1460 phys_to_virt(ALIGN(dma_addr, 4)), 1461 pkt_len + 2); 1462 mdp->rx_skbuff[entry] = NULL; 1463 if (mdp->cd->rpadir) 1464 skb_reserve(skb, NET_IP_ALIGN); 1465 dma_unmap_single(&ndev->dev, dma_addr, 1466 ALIGN(mdp->rx_buf_sz, 32), 1467 DMA_FROM_DEVICE); 1468 skb_put(skb, pkt_len); 1469 skb->protocol = eth_type_trans(skb, ndev); 1470 netif_receive_skb(skb); 1471 ndev->stats.rx_packets++; 1472 ndev->stats.rx_bytes += pkt_len; 1473 if (desc_status & RD_RFS8) 1474 ndev->stats.multicast++; 1475 } 1476 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1477 rxdesc = &mdp->rx_ring[entry]; 1478 } 1479 1480 /* Refill the Rx ring buffers. */ 1481 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1482 entry = mdp->dirty_rx % mdp->num_rx_ring; 1483 rxdesc = &mdp->rx_ring[entry]; 1484 /* The size of the buffer is 32 byte boundary. */ 1485 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1486 rxdesc->len = cpu_to_le32(buf_len << 16); 1487 1488 if (mdp->rx_skbuff[entry] == NULL) { 1489 skb = netdev_alloc_skb(ndev, skbuff_size); 1490 if (skb == NULL) 1491 break; /* Better luck next round. */ 1492 sh_eth_set_receive_align(skb); 1493 dma_addr = dma_map_single(&ndev->dev, skb->data, 1494 buf_len, DMA_FROM_DEVICE); 1495 if (dma_mapping_error(&ndev->dev, dma_addr)) { 1496 kfree_skb(skb); 1497 break; 1498 } 1499 mdp->rx_skbuff[entry] = skb; 1500 1501 skb_checksum_none_assert(skb); 1502 rxdesc->addr = cpu_to_le32(dma_addr); 1503 } 1504 dma_wmb(); /* RACT bit must be set after all the above writes */ 1505 if (entry >= mdp->num_rx_ring - 1) 1506 rxdesc->status |= 1507 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1508 else 1509 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1510 } 1511 1512 /* Restart Rx engine if stopped. */ 1513 /* If we don't need to check status, don't. -KDU */ 1514 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1515 /* fix the values for the next receiving if RDE is set */ 1516 if (intr_status & EESR_RDE && 1517 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) { 1518 u32 count = (sh_eth_read(ndev, RDFAR) - 1519 sh_eth_read(ndev, RDLAR)) >> 4; 1520 1521 mdp->cur_rx = count; 1522 mdp->dirty_rx = count; 1523 } 1524 sh_eth_write(ndev, EDRRR_R, EDRRR); 1525 } 1526 1527 *quota -= limit - boguscnt - 1; 1528 1529 return *quota <= 0; 1530 } 1531 1532 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1533 { 1534 /* disable tx and rx */ 1535 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & 1536 ~(ECMR_RE | ECMR_TE), ECMR); 1537 } 1538 1539 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1540 { 1541 /* enable tx and rx */ 1542 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | 1543 (ECMR_RE | ECMR_TE), ECMR); 1544 } 1545 1546 /* error control function */ 1547 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1548 { 1549 struct sh_eth_private *mdp = netdev_priv(ndev); 1550 u32 felic_stat; 1551 u32 link_stat; 1552 u32 mask; 1553 1554 if (intr_status & EESR_ECI) { 1555 felic_stat = sh_eth_read(ndev, ECSR); 1556 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1557 if (felic_stat & ECSR_ICD) 1558 ndev->stats.tx_carrier_errors++; 1559 if (felic_stat & ECSR_LCHNG) { 1560 /* Link Changed */ 1561 if (mdp->cd->no_psr || mdp->no_ether_link) { 1562 goto ignore_link; 1563 } else { 1564 link_stat = (sh_eth_read(ndev, PSR)); 1565 if (mdp->ether_link_active_low) 1566 link_stat = ~link_stat; 1567 } 1568 if (!(link_stat & PHY_ST_LINK)) { 1569 sh_eth_rcv_snd_disable(ndev); 1570 } else { 1571 /* Link Up */ 1572 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & 1573 ~DMAC_M_ECI, EESIPR); 1574 /* clear int */ 1575 sh_eth_write(ndev, sh_eth_read(ndev, ECSR), 1576 ECSR); 1577 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | 1578 DMAC_M_ECI, EESIPR); 1579 /* enable tx and rx */ 1580 sh_eth_rcv_snd_enable(ndev); 1581 } 1582 } 1583 } 1584 1585 ignore_link: 1586 if (intr_status & EESR_TWB) { 1587 /* Unused write back interrupt */ 1588 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1589 ndev->stats.tx_aborted_errors++; 1590 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1591 } 1592 } 1593 1594 if (intr_status & EESR_RABT) { 1595 /* Receive Abort int */ 1596 if (intr_status & EESR_RFRMER) { 1597 /* Receive Frame Overflow int */ 1598 ndev->stats.rx_frame_errors++; 1599 } 1600 } 1601 1602 if (intr_status & EESR_TDE) { 1603 /* Transmit Descriptor Empty int */ 1604 ndev->stats.tx_fifo_errors++; 1605 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1606 } 1607 1608 if (intr_status & EESR_TFE) { 1609 /* FIFO under flow */ 1610 ndev->stats.tx_fifo_errors++; 1611 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1612 } 1613 1614 if (intr_status & EESR_RDE) { 1615 /* Receive Descriptor Empty int */ 1616 ndev->stats.rx_over_errors++; 1617 } 1618 1619 if (intr_status & EESR_RFE) { 1620 /* Receive FIFO Overflow int */ 1621 ndev->stats.rx_fifo_errors++; 1622 } 1623 1624 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1625 /* Address Error */ 1626 ndev->stats.tx_fifo_errors++; 1627 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1628 } 1629 1630 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1631 if (mdp->cd->no_ade) 1632 mask &= ~EESR_ADE; 1633 if (intr_status & mask) { 1634 /* Tx error */ 1635 u32 edtrr = sh_eth_read(ndev, EDTRR); 1636 1637 /* dmesg */ 1638 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1639 intr_status, mdp->cur_tx, mdp->dirty_tx, 1640 (u32)ndev->state, edtrr); 1641 /* dirty buffer free */ 1642 sh_eth_txfree(ndev); 1643 1644 /* SH7712 BUG */ 1645 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1646 /* tx dma start */ 1647 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1648 } 1649 /* wakeup */ 1650 netif_wake_queue(ndev); 1651 } 1652 } 1653 1654 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1655 { 1656 struct net_device *ndev = netdev; 1657 struct sh_eth_private *mdp = netdev_priv(ndev); 1658 struct sh_eth_cpu_data *cd = mdp->cd; 1659 irqreturn_t ret = IRQ_NONE; 1660 u32 intr_status, intr_enable; 1661 1662 spin_lock(&mdp->lock); 1663 1664 /* Get interrupt status */ 1665 intr_status = sh_eth_read(ndev, EESR); 1666 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1667 * enabled since it's the one that comes thru regardless of the mask, 1668 * and we need to fully handle it in sh_eth_error() in order to quench 1669 * it as it doesn't get cleared by just writing 1 to the ECI bit... 1670 */ 1671 intr_enable = sh_eth_read(ndev, EESIPR); 1672 intr_status &= intr_enable | DMAC_M_ECI; 1673 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) 1674 ret = IRQ_HANDLED; 1675 else 1676 goto out; 1677 1678 if (!likely(mdp->irq_enabled)) { 1679 sh_eth_write(ndev, 0, EESIPR); 1680 goto out; 1681 } 1682 1683 if (intr_status & EESR_RX_CHECK) { 1684 if (napi_schedule_prep(&mdp->napi)) { 1685 /* Mask Rx interrupts */ 1686 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1687 EESIPR); 1688 __napi_schedule(&mdp->napi); 1689 } else { 1690 netdev_warn(ndev, 1691 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1692 intr_status, intr_enable); 1693 } 1694 } 1695 1696 /* Tx Check */ 1697 if (intr_status & cd->tx_check) { 1698 /* Clear Tx interrupts */ 1699 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1700 1701 sh_eth_txfree(ndev); 1702 netif_wake_queue(ndev); 1703 } 1704 1705 if (intr_status & cd->eesr_err_check) { 1706 /* Clear error interrupts */ 1707 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1708 1709 sh_eth_error(ndev, intr_status); 1710 } 1711 1712 out: 1713 spin_unlock(&mdp->lock); 1714 1715 return ret; 1716 } 1717 1718 static int sh_eth_poll(struct napi_struct *napi, int budget) 1719 { 1720 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1721 napi); 1722 struct net_device *ndev = napi->dev; 1723 int quota = budget; 1724 u32 intr_status; 1725 1726 for (;;) { 1727 intr_status = sh_eth_read(ndev, EESR); 1728 if (!(intr_status & EESR_RX_CHECK)) 1729 break; 1730 /* Clear Rx interrupts */ 1731 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1732 1733 if (sh_eth_rx(ndev, intr_status, "a)) 1734 goto out; 1735 } 1736 1737 napi_complete(napi); 1738 1739 /* Reenable Rx interrupts */ 1740 if (mdp->irq_enabled) 1741 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1742 out: 1743 return budget - quota; 1744 } 1745 1746 /* PHY state control function */ 1747 static void sh_eth_adjust_link(struct net_device *ndev) 1748 { 1749 struct sh_eth_private *mdp = netdev_priv(ndev); 1750 struct phy_device *phydev = mdp->phydev; 1751 int new_state = 0; 1752 1753 if (phydev->link) { 1754 if (phydev->duplex != mdp->duplex) { 1755 new_state = 1; 1756 mdp->duplex = phydev->duplex; 1757 if (mdp->cd->set_duplex) 1758 mdp->cd->set_duplex(ndev); 1759 } 1760 1761 if (phydev->speed != mdp->speed) { 1762 new_state = 1; 1763 mdp->speed = phydev->speed; 1764 if (mdp->cd->set_rate) 1765 mdp->cd->set_rate(ndev); 1766 } 1767 if (!mdp->link) { 1768 sh_eth_write(ndev, 1769 sh_eth_read(ndev, ECMR) & ~ECMR_TXF, 1770 ECMR); 1771 new_state = 1; 1772 mdp->link = phydev->link; 1773 if (mdp->cd->no_psr || mdp->no_ether_link) 1774 sh_eth_rcv_snd_enable(ndev); 1775 } 1776 } else if (mdp->link) { 1777 new_state = 1; 1778 mdp->link = 0; 1779 mdp->speed = 0; 1780 mdp->duplex = -1; 1781 if (mdp->cd->no_psr || mdp->no_ether_link) 1782 sh_eth_rcv_snd_disable(ndev); 1783 } 1784 1785 if (new_state && netif_msg_link(mdp)) 1786 phy_print_status(phydev); 1787 } 1788 1789 /* PHY init function */ 1790 static int sh_eth_phy_init(struct net_device *ndev) 1791 { 1792 struct device_node *np = ndev->dev.parent->of_node; 1793 struct sh_eth_private *mdp = netdev_priv(ndev); 1794 struct phy_device *phydev = NULL; 1795 1796 mdp->link = 0; 1797 mdp->speed = 0; 1798 mdp->duplex = -1; 1799 1800 /* Try connect to PHY */ 1801 if (np) { 1802 struct device_node *pn; 1803 1804 pn = of_parse_phandle(np, "phy-handle", 0); 1805 phydev = of_phy_connect(ndev, pn, 1806 sh_eth_adjust_link, 0, 1807 mdp->phy_interface); 1808 1809 if (!phydev) 1810 phydev = ERR_PTR(-ENOENT); 1811 } else { 1812 char phy_id[MII_BUS_ID_SIZE + 3]; 1813 1814 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1815 mdp->mii_bus->id, mdp->phy_id); 1816 1817 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1818 mdp->phy_interface); 1819 } 1820 1821 if (IS_ERR(phydev)) { 1822 netdev_err(ndev, "failed to connect PHY\n"); 1823 return PTR_ERR(phydev); 1824 } 1825 1826 phy_attached_info(phydev); 1827 1828 mdp->phydev = phydev; 1829 1830 return 0; 1831 } 1832 1833 /* PHY control start function */ 1834 static int sh_eth_phy_start(struct net_device *ndev) 1835 { 1836 struct sh_eth_private *mdp = netdev_priv(ndev); 1837 int ret; 1838 1839 ret = sh_eth_phy_init(ndev); 1840 if (ret) 1841 return ret; 1842 1843 phy_start(mdp->phydev); 1844 1845 return 0; 1846 } 1847 1848 static int sh_eth_get_settings(struct net_device *ndev, 1849 struct ethtool_cmd *ecmd) 1850 { 1851 struct sh_eth_private *mdp = netdev_priv(ndev); 1852 unsigned long flags; 1853 int ret; 1854 1855 if (!mdp->phydev) 1856 return -ENODEV; 1857 1858 spin_lock_irqsave(&mdp->lock, flags); 1859 ret = phy_ethtool_gset(mdp->phydev, ecmd); 1860 spin_unlock_irqrestore(&mdp->lock, flags); 1861 1862 return ret; 1863 } 1864 1865 static int sh_eth_set_settings(struct net_device *ndev, 1866 struct ethtool_cmd *ecmd) 1867 { 1868 struct sh_eth_private *mdp = netdev_priv(ndev); 1869 unsigned long flags; 1870 int ret; 1871 1872 if (!mdp->phydev) 1873 return -ENODEV; 1874 1875 spin_lock_irqsave(&mdp->lock, flags); 1876 1877 /* disable tx and rx */ 1878 sh_eth_rcv_snd_disable(ndev); 1879 1880 ret = phy_ethtool_sset(mdp->phydev, ecmd); 1881 if (ret) 1882 goto error_exit; 1883 1884 if (ecmd->duplex == DUPLEX_FULL) 1885 mdp->duplex = 1; 1886 else 1887 mdp->duplex = 0; 1888 1889 if (mdp->cd->set_duplex) 1890 mdp->cd->set_duplex(ndev); 1891 1892 error_exit: 1893 mdelay(1); 1894 1895 /* enable tx and rx */ 1896 sh_eth_rcv_snd_enable(ndev); 1897 1898 spin_unlock_irqrestore(&mdp->lock, flags); 1899 1900 return ret; 1901 } 1902 1903 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 1904 * version must be bumped as well. Just adding registers up to that 1905 * limit is fine, as long as the existing register indices don't 1906 * change. 1907 */ 1908 #define SH_ETH_REG_DUMP_VERSION 1 1909 #define SH_ETH_REG_DUMP_MAX_REGS 256 1910 1911 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 1912 { 1913 struct sh_eth_private *mdp = netdev_priv(ndev); 1914 struct sh_eth_cpu_data *cd = mdp->cd; 1915 u32 *valid_map; 1916 size_t len; 1917 1918 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 1919 1920 /* Dump starts with a bitmap that tells ethtool which 1921 * registers are defined for this chip. 1922 */ 1923 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 1924 if (buf) { 1925 valid_map = buf; 1926 buf += len; 1927 } else { 1928 valid_map = NULL; 1929 } 1930 1931 /* Add a register to the dump, if it has a defined offset. 1932 * This automatically skips most undefined registers, but for 1933 * some it is also necessary to check a capability flag in 1934 * struct sh_eth_cpu_data. 1935 */ 1936 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 1937 #define add_reg_from(reg, read_expr) do { \ 1938 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 1939 if (buf) { \ 1940 mark_reg_valid(reg); \ 1941 *buf++ = read_expr; \ 1942 } \ 1943 ++len; \ 1944 } \ 1945 } while (0) 1946 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 1947 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 1948 1949 add_reg(EDSR); 1950 add_reg(EDMR); 1951 add_reg(EDTRR); 1952 add_reg(EDRRR); 1953 add_reg(EESR); 1954 add_reg(EESIPR); 1955 add_reg(TDLAR); 1956 add_reg(TDFAR); 1957 add_reg(TDFXR); 1958 add_reg(TDFFR); 1959 add_reg(RDLAR); 1960 add_reg(RDFAR); 1961 add_reg(RDFXR); 1962 add_reg(RDFFR); 1963 add_reg(TRSCER); 1964 add_reg(RMFCR); 1965 add_reg(TFTR); 1966 add_reg(FDR); 1967 add_reg(RMCR); 1968 add_reg(TFUCR); 1969 add_reg(RFOCR); 1970 if (cd->rmiimode) 1971 add_reg(RMIIMODE); 1972 add_reg(FCFTR); 1973 if (cd->rpadir) 1974 add_reg(RPADIR); 1975 if (!cd->no_trimd) 1976 add_reg(TRIMD); 1977 add_reg(ECMR); 1978 add_reg(ECSR); 1979 add_reg(ECSIPR); 1980 add_reg(PIR); 1981 if (!cd->no_psr) 1982 add_reg(PSR); 1983 add_reg(RDMLR); 1984 add_reg(RFLR); 1985 add_reg(IPGR); 1986 if (cd->apr) 1987 add_reg(APR); 1988 if (cd->mpr) 1989 add_reg(MPR); 1990 add_reg(RFCR); 1991 add_reg(RFCF); 1992 if (cd->tpauser) 1993 add_reg(TPAUSER); 1994 add_reg(TPAUSECR); 1995 add_reg(GECMR); 1996 if (cd->bculr) 1997 add_reg(BCULR); 1998 add_reg(MAHR); 1999 add_reg(MALR); 2000 add_reg(TROCR); 2001 add_reg(CDCR); 2002 add_reg(LCCR); 2003 add_reg(CNDCR); 2004 add_reg(CEFCR); 2005 add_reg(FRECR); 2006 add_reg(TSFRCR); 2007 add_reg(TLFRCR); 2008 add_reg(CERCR); 2009 add_reg(CEECR); 2010 add_reg(MAFCR); 2011 if (cd->rtrate) 2012 add_reg(RTRATE); 2013 if (cd->hw_crc) 2014 add_reg(CSMR); 2015 if (cd->select_mii) 2016 add_reg(RMII_MII); 2017 add_reg(ARSTR); 2018 if (cd->tsu) { 2019 add_tsu_reg(TSU_CTRST); 2020 add_tsu_reg(TSU_FWEN0); 2021 add_tsu_reg(TSU_FWEN1); 2022 add_tsu_reg(TSU_FCM); 2023 add_tsu_reg(TSU_BSYSL0); 2024 add_tsu_reg(TSU_BSYSL1); 2025 add_tsu_reg(TSU_PRISL0); 2026 add_tsu_reg(TSU_PRISL1); 2027 add_tsu_reg(TSU_FWSL0); 2028 add_tsu_reg(TSU_FWSL1); 2029 add_tsu_reg(TSU_FWSLC); 2030 add_tsu_reg(TSU_QTAG0); 2031 add_tsu_reg(TSU_QTAG1); 2032 add_tsu_reg(TSU_QTAGM0); 2033 add_tsu_reg(TSU_QTAGM1); 2034 add_tsu_reg(TSU_FWSR); 2035 add_tsu_reg(TSU_FWINMK); 2036 add_tsu_reg(TSU_ADQT0); 2037 add_tsu_reg(TSU_ADQT1); 2038 add_tsu_reg(TSU_VTAG0); 2039 add_tsu_reg(TSU_VTAG1); 2040 add_tsu_reg(TSU_ADSBSY); 2041 add_tsu_reg(TSU_TEN); 2042 add_tsu_reg(TSU_POST1); 2043 add_tsu_reg(TSU_POST2); 2044 add_tsu_reg(TSU_POST3); 2045 add_tsu_reg(TSU_POST4); 2046 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) { 2047 /* This is the start of a table, not just a single 2048 * register. 2049 */ 2050 if (buf) { 2051 unsigned int i; 2052 2053 mark_reg_valid(TSU_ADRH0); 2054 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2055 *buf++ = ioread32( 2056 mdp->tsu_addr + 2057 mdp->reg_offset[TSU_ADRH0] + 2058 i * 4); 2059 } 2060 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2061 } 2062 } 2063 2064 #undef mark_reg_valid 2065 #undef add_reg_from 2066 #undef add_reg 2067 #undef add_tsu_reg 2068 2069 return len * 4; 2070 } 2071 2072 static int sh_eth_get_regs_len(struct net_device *ndev) 2073 { 2074 return __sh_eth_get_regs(ndev, NULL); 2075 } 2076 2077 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2078 void *buf) 2079 { 2080 struct sh_eth_private *mdp = netdev_priv(ndev); 2081 2082 regs->version = SH_ETH_REG_DUMP_VERSION; 2083 2084 pm_runtime_get_sync(&mdp->pdev->dev); 2085 __sh_eth_get_regs(ndev, buf); 2086 pm_runtime_put_sync(&mdp->pdev->dev); 2087 } 2088 2089 static int sh_eth_nway_reset(struct net_device *ndev) 2090 { 2091 struct sh_eth_private *mdp = netdev_priv(ndev); 2092 unsigned long flags; 2093 int ret; 2094 2095 if (!mdp->phydev) 2096 return -ENODEV; 2097 2098 spin_lock_irqsave(&mdp->lock, flags); 2099 ret = phy_start_aneg(mdp->phydev); 2100 spin_unlock_irqrestore(&mdp->lock, flags); 2101 2102 return ret; 2103 } 2104 2105 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2106 { 2107 struct sh_eth_private *mdp = netdev_priv(ndev); 2108 return mdp->msg_enable; 2109 } 2110 2111 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2112 { 2113 struct sh_eth_private *mdp = netdev_priv(ndev); 2114 mdp->msg_enable = value; 2115 } 2116 2117 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2118 "rx_current", "tx_current", 2119 "rx_dirty", "tx_dirty", 2120 }; 2121 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2122 2123 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2124 { 2125 switch (sset) { 2126 case ETH_SS_STATS: 2127 return SH_ETH_STATS_LEN; 2128 default: 2129 return -EOPNOTSUPP; 2130 } 2131 } 2132 2133 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2134 struct ethtool_stats *stats, u64 *data) 2135 { 2136 struct sh_eth_private *mdp = netdev_priv(ndev); 2137 int i = 0; 2138 2139 /* device-specific stats */ 2140 data[i++] = mdp->cur_rx; 2141 data[i++] = mdp->cur_tx; 2142 data[i++] = mdp->dirty_rx; 2143 data[i++] = mdp->dirty_tx; 2144 } 2145 2146 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2147 { 2148 switch (stringset) { 2149 case ETH_SS_STATS: 2150 memcpy(data, *sh_eth_gstrings_stats, 2151 sizeof(sh_eth_gstrings_stats)); 2152 break; 2153 } 2154 } 2155 2156 static void sh_eth_get_ringparam(struct net_device *ndev, 2157 struct ethtool_ringparam *ring) 2158 { 2159 struct sh_eth_private *mdp = netdev_priv(ndev); 2160 2161 ring->rx_max_pending = RX_RING_MAX; 2162 ring->tx_max_pending = TX_RING_MAX; 2163 ring->rx_pending = mdp->num_rx_ring; 2164 ring->tx_pending = mdp->num_tx_ring; 2165 } 2166 2167 static int sh_eth_set_ringparam(struct net_device *ndev, 2168 struct ethtool_ringparam *ring) 2169 { 2170 struct sh_eth_private *mdp = netdev_priv(ndev); 2171 int ret; 2172 2173 if (ring->tx_pending > TX_RING_MAX || 2174 ring->rx_pending > RX_RING_MAX || 2175 ring->tx_pending < TX_RING_MIN || 2176 ring->rx_pending < RX_RING_MIN) 2177 return -EINVAL; 2178 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2179 return -EINVAL; 2180 2181 if (netif_running(ndev)) { 2182 netif_device_detach(ndev); 2183 netif_tx_disable(ndev); 2184 2185 /* Serialise with the interrupt handler and NAPI, then 2186 * disable interrupts. We have to clear the 2187 * irq_enabled flag first to ensure that interrupts 2188 * won't be re-enabled. 2189 */ 2190 mdp->irq_enabled = false; 2191 synchronize_irq(ndev->irq); 2192 napi_synchronize(&mdp->napi); 2193 sh_eth_write(ndev, 0x0000, EESIPR); 2194 2195 sh_eth_dev_exit(ndev); 2196 2197 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2198 sh_eth_ring_free(ndev); 2199 } 2200 2201 /* Set new parameters */ 2202 mdp->num_rx_ring = ring->rx_pending; 2203 mdp->num_tx_ring = ring->tx_pending; 2204 2205 if (netif_running(ndev)) { 2206 ret = sh_eth_ring_init(ndev); 2207 if (ret < 0) { 2208 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2209 __func__); 2210 return ret; 2211 } 2212 ret = sh_eth_dev_init(ndev, false); 2213 if (ret < 0) { 2214 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2215 __func__); 2216 return ret; 2217 } 2218 2219 mdp->irq_enabled = true; 2220 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 2221 /* Setting the Rx mode will start the Rx process. */ 2222 sh_eth_write(ndev, EDRRR_R, EDRRR); 2223 netif_device_attach(ndev); 2224 } 2225 2226 return 0; 2227 } 2228 2229 static const struct ethtool_ops sh_eth_ethtool_ops = { 2230 .get_settings = sh_eth_get_settings, 2231 .set_settings = sh_eth_set_settings, 2232 .get_regs_len = sh_eth_get_regs_len, 2233 .get_regs = sh_eth_get_regs, 2234 .nway_reset = sh_eth_nway_reset, 2235 .get_msglevel = sh_eth_get_msglevel, 2236 .set_msglevel = sh_eth_set_msglevel, 2237 .get_link = ethtool_op_get_link, 2238 .get_strings = sh_eth_get_strings, 2239 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2240 .get_sset_count = sh_eth_get_sset_count, 2241 .get_ringparam = sh_eth_get_ringparam, 2242 .set_ringparam = sh_eth_set_ringparam, 2243 }; 2244 2245 /* network device open function */ 2246 static int sh_eth_open(struct net_device *ndev) 2247 { 2248 int ret = 0; 2249 struct sh_eth_private *mdp = netdev_priv(ndev); 2250 2251 pm_runtime_get_sync(&mdp->pdev->dev); 2252 2253 napi_enable(&mdp->napi); 2254 2255 ret = request_irq(ndev->irq, sh_eth_interrupt, 2256 mdp->cd->irq_flags, ndev->name, ndev); 2257 if (ret) { 2258 netdev_err(ndev, "Can not assign IRQ number\n"); 2259 goto out_napi_off; 2260 } 2261 2262 /* Descriptor set */ 2263 ret = sh_eth_ring_init(ndev); 2264 if (ret) 2265 goto out_free_irq; 2266 2267 /* device init */ 2268 ret = sh_eth_dev_init(ndev, true); 2269 if (ret) 2270 goto out_free_irq; 2271 2272 /* PHY control start*/ 2273 ret = sh_eth_phy_start(ndev); 2274 if (ret) 2275 goto out_free_irq; 2276 2277 mdp->is_opened = 1; 2278 2279 return ret; 2280 2281 out_free_irq: 2282 free_irq(ndev->irq, ndev); 2283 out_napi_off: 2284 napi_disable(&mdp->napi); 2285 pm_runtime_put_sync(&mdp->pdev->dev); 2286 return ret; 2287 } 2288 2289 /* Timeout function */ 2290 static void sh_eth_tx_timeout(struct net_device *ndev) 2291 { 2292 struct sh_eth_private *mdp = netdev_priv(ndev); 2293 struct sh_eth_rxdesc *rxdesc; 2294 int i; 2295 2296 netif_stop_queue(ndev); 2297 2298 netif_err(mdp, timer, ndev, 2299 "transmit timed out, status %8.8x, resetting...\n", 2300 sh_eth_read(ndev, EESR)); 2301 2302 /* tx_errors count up */ 2303 ndev->stats.tx_errors++; 2304 2305 /* Free all the skbuffs in the Rx queue. */ 2306 for (i = 0; i < mdp->num_rx_ring; i++) { 2307 rxdesc = &mdp->rx_ring[i]; 2308 rxdesc->status = cpu_to_le32(0); 2309 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2310 dev_kfree_skb(mdp->rx_skbuff[i]); 2311 mdp->rx_skbuff[i] = NULL; 2312 } 2313 for (i = 0; i < mdp->num_tx_ring; i++) { 2314 dev_kfree_skb(mdp->tx_skbuff[i]); 2315 mdp->tx_skbuff[i] = NULL; 2316 } 2317 2318 /* device init */ 2319 sh_eth_dev_init(ndev, true); 2320 } 2321 2322 /* Packet transmit function */ 2323 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2324 { 2325 struct sh_eth_private *mdp = netdev_priv(ndev); 2326 struct sh_eth_txdesc *txdesc; 2327 dma_addr_t dma_addr; 2328 u32 entry; 2329 unsigned long flags; 2330 2331 spin_lock_irqsave(&mdp->lock, flags); 2332 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2333 if (!sh_eth_txfree(ndev)) { 2334 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2335 netif_stop_queue(ndev); 2336 spin_unlock_irqrestore(&mdp->lock, flags); 2337 return NETDEV_TX_BUSY; 2338 } 2339 } 2340 spin_unlock_irqrestore(&mdp->lock, flags); 2341 2342 if (skb_put_padto(skb, ETH_ZLEN)) 2343 return NETDEV_TX_OK; 2344 2345 entry = mdp->cur_tx % mdp->num_tx_ring; 2346 mdp->tx_skbuff[entry] = skb; 2347 txdesc = &mdp->tx_ring[entry]; 2348 /* soft swap. */ 2349 if (!mdp->cd->hw_swap) 2350 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2351 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len, 2352 DMA_TO_DEVICE); 2353 if (dma_mapping_error(&ndev->dev, dma_addr)) { 2354 kfree_skb(skb); 2355 return NETDEV_TX_OK; 2356 } 2357 txdesc->addr = cpu_to_le32(dma_addr); 2358 txdesc->len = cpu_to_le32(skb->len << 16); 2359 2360 dma_wmb(); /* TACT bit must be set after all the above writes */ 2361 if (entry >= mdp->num_tx_ring - 1) 2362 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2363 else 2364 txdesc->status |= cpu_to_le32(TD_TACT); 2365 2366 mdp->cur_tx++; 2367 2368 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 2369 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 2370 2371 return NETDEV_TX_OK; 2372 } 2373 2374 /* The statistics registers have write-clear behaviour, which means we 2375 * will lose any increment between the read and write. We mitigate 2376 * this by only clearing when we read a non-zero value, so we will 2377 * never falsely report a total of zero. 2378 */ 2379 static void 2380 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2381 { 2382 u32 delta = sh_eth_read(ndev, reg); 2383 2384 if (delta) { 2385 *stat += delta; 2386 sh_eth_write(ndev, 0, reg); 2387 } 2388 } 2389 2390 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2391 { 2392 struct sh_eth_private *mdp = netdev_priv(ndev); 2393 2394 if (sh_eth_is_rz_fast_ether(mdp)) 2395 return &ndev->stats; 2396 2397 if (!mdp->is_opened) 2398 return &ndev->stats; 2399 2400 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2401 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2402 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2403 2404 if (sh_eth_is_gether(mdp)) { 2405 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2406 CERCR); 2407 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2408 CEECR); 2409 } else { 2410 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2411 CNDCR); 2412 } 2413 2414 return &ndev->stats; 2415 } 2416 2417 /* device close function */ 2418 static int sh_eth_close(struct net_device *ndev) 2419 { 2420 struct sh_eth_private *mdp = netdev_priv(ndev); 2421 2422 netif_stop_queue(ndev); 2423 2424 /* Serialise with the interrupt handler and NAPI, then disable 2425 * interrupts. We have to clear the irq_enabled flag first to 2426 * ensure that interrupts won't be re-enabled. 2427 */ 2428 mdp->irq_enabled = false; 2429 synchronize_irq(ndev->irq); 2430 napi_disable(&mdp->napi); 2431 sh_eth_write(ndev, 0x0000, EESIPR); 2432 2433 sh_eth_dev_exit(ndev); 2434 2435 /* PHY Disconnect */ 2436 if (mdp->phydev) { 2437 phy_stop(mdp->phydev); 2438 phy_disconnect(mdp->phydev); 2439 mdp->phydev = NULL; 2440 } 2441 2442 free_irq(ndev->irq, ndev); 2443 2444 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2445 sh_eth_ring_free(ndev); 2446 2447 pm_runtime_put_sync(&mdp->pdev->dev); 2448 2449 mdp->is_opened = 0; 2450 2451 return 0; 2452 } 2453 2454 /* ioctl to device function */ 2455 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2456 { 2457 struct sh_eth_private *mdp = netdev_priv(ndev); 2458 struct phy_device *phydev = mdp->phydev; 2459 2460 if (!netif_running(ndev)) 2461 return -EINVAL; 2462 2463 if (!phydev) 2464 return -ENODEV; 2465 2466 return phy_mii_ioctl(phydev, rq, cmd); 2467 } 2468 2469 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2470 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 2471 int entry) 2472 { 2473 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 2474 } 2475 2476 static u32 sh_eth_tsu_get_post_mask(int entry) 2477 { 2478 return 0x0f << (28 - ((entry % 8) * 4)); 2479 } 2480 2481 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2482 { 2483 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2484 } 2485 2486 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2487 int entry) 2488 { 2489 struct sh_eth_private *mdp = netdev_priv(ndev); 2490 u32 tmp; 2491 void *reg_offset; 2492 2493 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2494 tmp = ioread32(reg_offset); 2495 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 2496 } 2497 2498 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2499 int entry) 2500 { 2501 struct sh_eth_private *mdp = netdev_priv(ndev); 2502 u32 post_mask, ref_mask, tmp; 2503 void *reg_offset; 2504 2505 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2506 post_mask = sh_eth_tsu_get_post_mask(entry); 2507 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2508 2509 tmp = ioread32(reg_offset); 2510 iowrite32(tmp & ~post_mask, reg_offset); 2511 2512 /* If other port enables, the function returns "true" */ 2513 return tmp & ref_mask; 2514 } 2515 2516 static int sh_eth_tsu_busy(struct net_device *ndev) 2517 { 2518 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2519 struct sh_eth_private *mdp = netdev_priv(ndev); 2520 2521 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2522 udelay(10); 2523 timeout--; 2524 if (timeout <= 0) { 2525 netdev_err(ndev, "%s: timeout\n", __func__); 2526 return -ETIMEDOUT; 2527 } 2528 } 2529 2530 return 0; 2531 } 2532 2533 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2534 const u8 *addr) 2535 { 2536 u32 val; 2537 2538 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2539 iowrite32(val, reg); 2540 if (sh_eth_tsu_busy(ndev) < 0) 2541 return -EBUSY; 2542 2543 val = addr[4] << 8 | addr[5]; 2544 iowrite32(val, reg + 4); 2545 if (sh_eth_tsu_busy(ndev) < 0) 2546 return -EBUSY; 2547 2548 return 0; 2549 } 2550 2551 static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2552 { 2553 u32 val; 2554 2555 val = ioread32(reg); 2556 addr[0] = (val >> 24) & 0xff; 2557 addr[1] = (val >> 16) & 0xff; 2558 addr[2] = (val >> 8) & 0xff; 2559 addr[3] = val & 0xff; 2560 val = ioread32(reg + 4); 2561 addr[4] = (val >> 8) & 0xff; 2562 addr[5] = val & 0xff; 2563 } 2564 2565 2566 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2567 { 2568 struct sh_eth_private *mdp = netdev_priv(ndev); 2569 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2570 int i; 2571 u8 c_addr[ETH_ALEN]; 2572 2573 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2574 sh_eth_tsu_read_entry(reg_offset, c_addr); 2575 if (ether_addr_equal(addr, c_addr)) 2576 return i; 2577 } 2578 2579 return -ENOENT; 2580 } 2581 2582 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2583 { 2584 u8 blank[ETH_ALEN]; 2585 int entry; 2586 2587 memset(blank, 0, sizeof(blank)); 2588 entry = sh_eth_tsu_find_entry(ndev, blank); 2589 return (entry < 0) ? -ENOMEM : entry; 2590 } 2591 2592 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2593 int entry) 2594 { 2595 struct sh_eth_private *mdp = netdev_priv(ndev); 2596 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2597 int ret; 2598 u8 blank[ETH_ALEN]; 2599 2600 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2601 ~(1 << (31 - entry)), TSU_TEN); 2602 2603 memset(blank, 0, sizeof(blank)); 2604 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2605 if (ret < 0) 2606 return ret; 2607 return 0; 2608 } 2609 2610 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2611 { 2612 struct sh_eth_private *mdp = netdev_priv(ndev); 2613 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2614 int i, ret; 2615 2616 if (!mdp->cd->tsu) 2617 return 0; 2618 2619 i = sh_eth_tsu_find_entry(ndev, addr); 2620 if (i < 0) { 2621 /* No entry found, create one */ 2622 i = sh_eth_tsu_find_empty(ndev); 2623 if (i < 0) 2624 return -ENOMEM; 2625 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2626 if (ret < 0) 2627 return ret; 2628 2629 /* Enable the entry */ 2630 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2631 (1 << (31 - i)), TSU_TEN); 2632 } 2633 2634 /* Entry found or created, enable POST */ 2635 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2636 2637 return 0; 2638 } 2639 2640 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2641 { 2642 struct sh_eth_private *mdp = netdev_priv(ndev); 2643 int i, ret; 2644 2645 if (!mdp->cd->tsu) 2646 return 0; 2647 2648 i = sh_eth_tsu_find_entry(ndev, addr); 2649 if (i) { 2650 /* Entry found */ 2651 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2652 goto done; 2653 2654 /* Disable the entry if both ports was disabled */ 2655 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2656 if (ret < 0) 2657 return ret; 2658 } 2659 done: 2660 return 0; 2661 } 2662 2663 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2664 { 2665 struct sh_eth_private *mdp = netdev_priv(ndev); 2666 int i, ret; 2667 2668 if (!mdp->cd->tsu) 2669 return 0; 2670 2671 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2672 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2673 continue; 2674 2675 /* Disable the entry if both ports was disabled */ 2676 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2677 if (ret < 0) 2678 return ret; 2679 } 2680 2681 return 0; 2682 } 2683 2684 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2685 { 2686 struct sh_eth_private *mdp = netdev_priv(ndev); 2687 u8 addr[ETH_ALEN]; 2688 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2689 int i; 2690 2691 if (!mdp->cd->tsu) 2692 return; 2693 2694 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2695 sh_eth_tsu_read_entry(reg_offset, addr); 2696 if (is_multicast_ether_addr(addr)) 2697 sh_eth_tsu_del_entry(ndev, addr); 2698 } 2699 } 2700 2701 /* Update promiscuous flag and multicast filter */ 2702 static void sh_eth_set_rx_mode(struct net_device *ndev) 2703 { 2704 struct sh_eth_private *mdp = netdev_priv(ndev); 2705 u32 ecmr_bits; 2706 int mcast_all = 0; 2707 unsigned long flags; 2708 2709 spin_lock_irqsave(&mdp->lock, flags); 2710 /* Initial condition is MCT = 1, PRM = 0. 2711 * Depending on ndev->flags, set PRM or clear MCT 2712 */ 2713 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2714 if (mdp->cd->tsu) 2715 ecmr_bits |= ECMR_MCT; 2716 2717 if (!(ndev->flags & IFF_MULTICAST)) { 2718 sh_eth_tsu_purge_mcast(ndev); 2719 mcast_all = 1; 2720 } 2721 if (ndev->flags & IFF_ALLMULTI) { 2722 sh_eth_tsu_purge_mcast(ndev); 2723 ecmr_bits &= ~ECMR_MCT; 2724 mcast_all = 1; 2725 } 2726 2727 if (ndev->flags & IFF_PROMISC) { 2728 sh_eth_tsu_purge_all(ndev); 2729 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2730 } else if (mdp->cd->tsu) { 2731 struct netdev_hw_addr *ha; 2732 netdev_for_each_mc_addr(ha, ndev) { 2733 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2734 continue; 2735 2736 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2737 if (!mcast_all) { 2738 sh_eth_tsu_purge_mcast(ndev); 2739 ecmr_bits &= ~ECMR_MCT; 2740 mcast_all = 1; 2741 } 2742 } 2743 } 2744 } 2745 2746 /* update the ethernet mode */ 2747 sh_eth_write(ndev, ecmr_bits, ECMR); 2748 2749 spin_unlock_irqrestore(&mdp->lock, flags); 2750 } 2751 2752 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2753 { 2754 if (!mdp->port) 2755 return TSU_VTAG0; 2756 else 2757 return TSU_VTAG1; 2758 } 2759 2760 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2761 __be16 proto, u16 vid) 2762 { 2763 struct sh_eth_private *mdp = netdev_priv(ndev); 2764 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2765 2766 if (unlikely(!mdp->cd->tsu)) 2767 return -EPERM; 2768 2769 /* No filtering if vid = 0 */ 2770 if (!vid) 2771 return 0; 2772 2773 mdp->vlan_num_ids++; 2774 2775 /* The controller has one VLAN tag HW filter. So, if the filter is 2776 * already enabled, the driver disables it and the filte 2777 */ 2778 if (mdp->vlan_num_ids > 1) { 2779 /* disable VLAN filter */ 2780 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2781 return 0; 2782 } 2783 2784 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2785 vtag_reg_index); 2786 2787 return 0; 2788 } 2789 2790 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2791 __be16 proto, u16 vid) 2792 { 2793 struct sh_eth_private *mdp = netdev_priv(ndev); 2794 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2795 2796 if (unlikely(!mdp->cd->tsu)) 2797 return -EPERM; 2798 2799 /* No filtering if vid = 0 */ 2800 if (!vid) 2801 return 0; 2802 2803 mdp->vlan_num_ids--; 2804 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2805 2806 return 0; 2807 } 2808 2809 /* SuperH's TSU register init function */ 2810 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2811 { 2812 if (sh_eth_is_rz_fast_ether(mdp)) { 2813 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2814 return; 2815 } 2816 2817 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2818 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2819 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2820 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2821 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2822 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2823 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2824 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2825 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2826 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2827 if (sh_eth_is_gether(mdp)) { 2828 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2829 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2830 } else { 2831 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2832 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2833 } 2834 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2835 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2836 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2837 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2838 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2839 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2840 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2841 } 2842 2843 /* MDIO bus release function */ 2844 static int sh_mdio_release(struct sh_eth_private *mdp) 2845 { 2846 /* unregister mdio bus */ 2847 mdiobus_unregister(mdp->mii_bus); 2848 2849 /* free bitbang info */ 2850 free_mdio_bitbang(mdp->mii_bus); 2851 2852 return 0; 2853 } 2854 2855 /* MDIO bus init function */ 2856 static int sh_mdio_init(struct sh_eth_private *mdp, 2857 struct sh_eth_plat_data *pd) 2858 { 2859 int ret; 2860 struct bb_info *bitbang; 2861 struct platform_device *pdev = mdp->pdev; 2862 struct device *dev = &mdp->pdev->dev; 2863 2864 /* create bit control struct for PHY */ 2865 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 2866 if (!bitbang) 2867 return -ENOMEM; 2868 2869 /* bitbang init */ 2870 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2871 bitbang->set_gate = pd->set_mdio_gate; 2872 bitbang->ctrl.ops = &bb_ops; 2873 2874 /* MII controller setting */ 2875 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2876 if (!mdp->mii_bus) 2877 return -ENOMEM; 2878 2879 /* Hook up MII support for ethtool */ 2880 mdp->mii_bus->name = "sh_mii"; 2881 mdp->mii_bus->parent = dev; 2882 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2883 pdev->name, pdev->id); 2884 2885 /* register MDIO bus */ 2886 if (dev->of_node) { 2887 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 2888 } else { 2889 if (pd->phy_irq > 0) 2890 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 2891 2892 ret = mdiobus_register(mdp->mii_bus); 2893 } 2894 2895 if (ret) 2896 goto out_free_bus; 2897 2898 return 0; 2899 2900 out_free_bus: 2901 free_mdio_bitbang(mdp->mii_bus); 2902 return ret; 2903 } 2904 2905 static const u16 *sh_eth_get_register_offset(int register_type) 2906 { 2907 const u16 *reg_offset = NULL; 2908 2909 switch (register_type) { 2910 case SH_ETH_REG_GIGABIT: 2911 reg_offset = sh_eth_offset_gigabit; 2912 break; 2913 case SH_ETH_REG_FAST_RZ: 2914 reg_offset = sh_eth_offset_fast_rz; 2915 break; 2916 case SH_ETH_REG_FAST_RCAR: 2917 reg_offset = sh_eth_offset_fast_rcar; 2918 break; 2919 case SH_ETH_REG_FAST_SH4: 2920 reg_offset = sh_eth_offset_fast_sh4; 2921 break; 2922 case SH_ETH_REG_FAST_SH3_SH2: 2923 reg_offset = sh_eth_offset_fast_sh3_sh2; 2924 break; 2925 default: 2926 break; 2927 } 2928 2929 return reg_offset; 2930 } 2931 2932 static const struct net_device_ops sh_eth_netdev_ops = { 2933 .ndo_open = sh_eth_open, 2934 .ndo_stop = sh_eth_close, 2935 .ndo_start_xmit = sh_eth_start_xmit, 2936 .ndo_get_stats = sh_eth_get_stats, 2937 .ndo_set_rx_mode = sh_eth_set_rx_mode, 2938 .ndo_tx_timeout = sh_eth_tx_timeout, 2939 .ndo_do_ioctl = sh_eth_do_ioctl, 2940 .ndo_validate_addr = eth_validate_addr, 2941 .ndo_set_mac_address = eth_mac_addr, 2942 .ndo_change_mtu = eth_change_mtu, 2943 }; 2944 2945 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 2946 .ndo_open = sh_eth_open, 2947 .ndo_stop = sh_eth_close, 2948 .ndo_start_xmit = sh_eth_start_xmit, 2949 .ndo_get_stats = sh_eth_get_stats, 2950 .ndo_set_rx_mode = sh_eth_set_rx_mode, 2951 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 2952 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 2953 .ndo_tx_timeout = sh_eth_tx_timeout, 2954 .ndo_do_ioctl = sh_eth_do_ioctl, 2955 .ndo_validate_addr = eth_validate_addr, 2956 .ndo_set_mac_address = eth_mac_addr, 2957 .ndo_change_mtu = eth_change_mtu, 2958 }; 2959 2960 #ifdef CONFIG_OF 2961 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 2962 { 2963 struct device_node *np = dev->of_node; 2964 struct sh_eth_plat_data *pdata; 2965 const char *mac_addr; 2966 2967 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2968 if (!pdata) 2969 return NULL; 2970 2971 pdata->phy_interface = of_get_phy_mode(np); 2972 2973 mac_addr = of_get_mac_address(np); 2974 if (mac_addr) 2975 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 2976 2977 pdata->no_ether_link = 2978 of_property_read_bool(np, "renesas,no-ether-link"); 2979 pdata->ether_link_active_low = 2980 of_property_read_bool(np, "renesas,ether-link-active-low"); 2981 2982 return pdata; 2983 } 2984 2985 static const struct of_device_id sh_eth_match_table[] = { 2986 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 2987 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data }, 2988 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data }, 2989 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data }, 2990 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data }, 2991 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data }, 2992 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data }, 2993 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 2994 { } 2995 }; 2996 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 2997 #else 2998 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 2999 { 3000 return NULL; 3001 } 3002 #endif 3003 3004 static int sh_eth_drv_probe(struct platform_device *pdev) 3005 { 3006 int ret, devno = 0; 3007 struct resource *res; 3008 struct net_device *ndev = NULL; 3009 struct sh_eth_private *mdp = NULL; 3010 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3011 const struct platform_device_id *id = platform_get_device_id(pdev); 3012 3013 /* get base addr */ 3014 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3015 3016 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3017 if (!ndev) 3018 return -ENOMEM; 3019 3020 pm_runtime_enable(&pdev->dev); 3021 pm_runtime_get_sync(&pdev->dev); 3022 3023 devno = pdev->id; 3024 if (devno < 0) 3025 devno = 0; 3026 3027 ndev->dma = -1; 3028 ret = platform_get_irq(pdev, 0); 3029 if (ret < 0) 3030 goto out_release; 3031 ndev->irq = ret; 3032 3033 SET_NETDEV_DEV(ndev, &pdev->dev); 3034 3035 mdp = netdev_priv(ndev); 3036 mdp->num_tx_ring = TX_RING_SIZE; 3037 mdp->num_rx_ring = RX_RING_SIZE; 3038 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3039 if (IS_ERR(mdp->addr)) { 3040 ret = PTR_ERR(mdp->addr); 3041 goto out_release; 3042 } 3043 3044 ndev->base_addr = res->start; 3045 3046 spin_lock_init(&mdp->lock); 3047 mdp->pdev = pdev; 3048 3049 if (pdev->dev.of_node) 3050 pd = sh_eth_parse_dt(&pdev->dev); 3051 if (!pd) { 3052 dev_err(&pdev->dev, "no platform data\n"); 3053 ret = -EINVAL; 3054 goto out_release; 3055 } 3056 3057 /* get PHY ID */ 3058 mdp->phy_id = pd->phy; 3059 mdp->phy_interface = pd->phy_interface; 3060 mdp->no_ether_link = pd->no_ether_link; 3061 mdp->ether_link_active_low = pd->ether_link_active_low; 3062 3063 /* set cpu data */ 3064 if (id) { 3065 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3066 } else { 3067 const struct of_device_id *match; 3068 3069 match = of_match_device(of_match_ptr(sh_eth_match_table), 3070 &pdev->dev); 3071 mdp->cd = (struct sh_eth_cpu_data *)match->data; 3072 } 3073 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3074 if (!mdp->reg_offset) { 3075 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3076 mdp->cd->register_type); 3077 ret = -EINVAL; 3078 goto out_release; 3079 } 3080 sh_eth_set_default_cpu_data(mdp->cd); 3081 3082 /* set function */ 3083 if (mdp->cd->tsu) 3084 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3085 else 3086 ndev->netdev_ops = &sh_eth_netdev_ops; 3087 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3088 ndev->watchdog_timeo = TX_TIMEOUT; 3089 3090 /* debug message level */ 3091 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3092 3093 /* read and set MAC address */ 3094 read_mac_address(ndev, pd->mac_addr); 3095 if (!is_valid_ether_addr(ndev->dev_addr)) { 3096 dev_warn(&pdev->dev, 3097 "no valid MAC address supplied, using a random one.\n"); 3098 eth_hw_addr_random(ndev); 3099 } 3100 3101 /* ioremap the TSU registers */ 3102 if (mdp->cd->tsu) { 3103 struct resource *rtsu; 3104 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3105 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu); 3106 if (IS_ERR(mdp->tsu_addr)) { 3107 ret = PTR_ERR(mdp->tsu_addr); 3108 goto out_release; 3109 } 3110 mdp->port = devno % 2; 3111 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 3112 } 3113 3114 /* initialize first or needed device */ 3115 if (!devno || pd->needs_init) { 3116 if (mdp->cd->chip_reset) 3117 mdp->cd->chip_reset(ndev); 3118 3119 if (mdp->cd->tsu) { 3120 /* TSU init (Init only)*/ 3121 sh_eth_tsu_init(mdp); 3122 } 3123 } 3124 3125 if (mdp->cd->rmiimode) 3126 sh_eth_write(ndev, 0x1, RMIIMODE); 3127 3128 /* MDIO bus init */ 3129 ret = sh_mdio_init(mdp, pd); 3130 if (ret) { 3131 dev_err(&ndev->dev, "failed to initialise MDIO\n"); 3132 goto out_release; 3133 } 3134 3135 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3136 3137 /* network device register */ 3138 ret = register_netdev(ndev); 3139 if (ret) 3140 goto out_napi_del; 3141 3142 /* print device information */ 3143 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3144 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3145 3146 pm_runtime_put(&pdev->dev); 3147 platform_set_drvdata(pdev, ndev); 3148 3149 return ret; 3150 3151 out_napi_del: 3152 netif_napi_del(&mdp->napi); 3153 sh_mdio_release(mdp); 3154 3155 out_release: 3156 /* net_dev free */ 3157 if (ndev) 3158 free_netdev(ndev); 3159 3160 pm_runtime_put(&pdev->dev); 3161 pm_runtime_disable(&pdev->dev); 3162 return ret; 3163 } 3164 3165 static int sh_eth_drv_remove(struct platform_device *pdev) 3166 { 3167 struct net_device *ndev = platform_get_drvdata(pdev); 3168 struct sh_eth_private *mdp = netdev_priv(ndev); 3169 3170 unregister_netdev(ndev); 3171 netif_napi_del(&mdp->napi); 3172 sh_mdio_release(mdp); 3173 pm_runtime_disable(&pdev->dev); 3174 free_netdev(ndev); 3175 3176 return 0; 3177 } 3178 3179 #ifdef CONFIG_PM 3180 #ifdef CONFIG_PM_SLEEP 3181 static int sh_eth_suspend(struct device *dev) 3182 { 3183 struct net_device *ndev = dev_get_drvdata(dev); 3184 int ret = 0; 3185 3186 if (netif_running(ndev)) { 3187 netif_device_detach(ndev); 3188 ret = sh_eth_close(ndev); 3189 } 3190 3191 return ret; 3192 } 3193 3194 static int sh_eth_resume(struct device *dev) 3195 { 3196 struct net_device *ndev = dev_get_drvdata(dev); 3197 int ret = 0; 3198 3199 if (netif_running(ndev)) { 3200 ret = sh_eth_open(ndev); 3201 if (ret < 0) 3202 return ret; 3203 netif_device_attach(ndev); 3204 } 3205 3206 return ret; 3207 } 3208 #endif 3209 3210 static int sh_eth_runtime_nop(struct device *dev) 3211 { 3212 /* Runtime PM callback shared between ->runtime_suspend() 3213 * and ->runtime_resume(). Simply returns success. 3214 * 3215 * This driver re-initializes all registers after 3216 * pm_runtime_get_sync() anyway so there is no need 3217 * to save and restore registers here. 3218 */ 3219 return 0; 3220 } 3221 3222 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3223 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3224 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3225 }; 3226 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3227 #else 3228 #define SH_ETH_PM_OPS NULL 3229 #endif 3230 3231 static struct platform_device_id sh_eth_id_table[] = { 3232 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3233 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3234 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3235 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3236 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3237 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3238 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3239 { } 3240 }; 3241 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3242 3243 static struct platform_driver sh_eth_driver = { 3244 .probe = sh_eth_drv_probe, 3245 .remove = sh_eth_drv_remove, 3246 .id_table = sh_eth_id_table, 3247 .driver = { 3248 .name = CARDNAME, 3249 .pm = SH_ETH_PM_OPS, 3250 .of_match_table = of_match_ptr(sh_eth_match_table), 3251 }, 3252 }; 3253 3254 module_platform_driver(sh_eth_driver); 3255 3256 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3257 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3258 MODULE_LICENSE("GPL v2"); 3259