1 // SPDX-License-Identifier: GPL-2.0 2 /* SuperH Ethernet device driver 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 6 * Copyright (C) 2008-2014 Renesas Solutions Corp. 7 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 8 * Copyright (C) 2014 Codethink Limited 9 */ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/spinlock.h> 14 #include <linux/interrupt.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/etherdevice.h> 17 #include <linux/delay.h> 18 #include <linux/platform_device.h> 19 #include <linux/mdio-bitbang.h> 20 #include <linux/netdevice.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_net.h> 25 #include <linux/phy.h> 26 #include <linux/cache.h> 27 #include <linux/io.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/ethtool.h> 31 #include <linux/if_vlan.h> 32 #include <linux/sh_eth.h> 33 #include <linux/of_mdio.h> 34 35 #include "sh_eth.h" 36 37 #define SH_ETH_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR| \ 41 NETIF_MSG_TX_ERR) 42 43 #define SH_ETH_OFFSET_INVALID ((u16)~0) 44 45 #define SH_ETH_OFFSET_DEFAULTS \ 46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 47 48 /* use some intentionally tricky logic here to initialize the whole struct to 49 * 0xffff, but then override certain fields, requiring us to indicate that we 50 * "know" that there are overrides in this structure, and we'll need to disable 51 * that warning from W=1 builds. GCC has supported this option since 4.2.X, but 52 * the macros available to do this only define GCC 8. 53 */ 54 __diag_push(); 55 __diag_ignore(GCC, 8, "-Woverride-init", 56 "logic to initialize all and then override some is OK"); 57 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 58 SH_ETH_OFFSET_DEFAULTS, 59 60 [EDSR] = 0x0000, 61 [EDMR] = 0x0400, 62 [EDTRR] = 0x0408, 63 [EDRRR] = 0x0410, 64 [EESR] = 0x0428, 65 [EESIPR] = 0x0430, 66 [TDLAR] = 0x0010, 67 [TDFAR] = 0x0014, 68 [TDFXR] = 0x0018, 69 [TDFFR] = 0x001c, 70 [RDLAR] = 0x0030, 71 [RDFAR] = 0x0034, 72 [RDFXR] = 0x0038, 73 [RDFFR] = 0x003c, 74 [TRSCER] = 0x0438, 75 [RMFCR] = 0x0440, 76 [TFTR] = 0x0448, 77 [FDR] = 0x0450, 78 [RMCR] = 0x0458, 79 [RPADIR] = 0x0460, 80 [FCFTR] = 0x0468, 81 [CSMR] = 0x04E4, 82 83 [ECMR] = 0x0500, 84 [ECSR] = 0x0510, 85 [ECSIPR] = 0x0518, 86 [PIR] = 0x0520, 87 [PSR] = 0x0528, 88 [PIPR] = 0x052c, 89 [RFLR] = 0x0508, 90 [APR] = 0x0554, 91 [MPR] = 0x0558, 92 [PFTCR] = 0x055c, 93 [PFRCR] = 0x0560, 94 [TPAUSER] = 0x0564, 95 [GECMR] = 0x05b0, 96 [BCULR] = 0x05b4, 97 [MAHR] = 0x05c0, 98 [MALR] = 0x05c8, 99 [TROCR] = 0x0700, 100 [CDCR] = 0x0708, 101 [LCCR] = 0x0710, 102 [CEFCR] = 0x0740, 103 [FRECR] = 0x0748, 104 [TSFRCR] = 0x0750, 105 [TLFRCR] = 0x0758, 106 [RFCR] = 0x0760, 107 [CERCR] = 0x0768, 108 [CEECR] = 0x0770, 109 [MAFCR] = 0x0778, 110 [RMII_MII] = 0x0790, 111 112 [ARSTR] = 0x0000, 113 [TSU_CTRST] = 0x0004, 114 [TSU_FWEN0] = 0x0010, 115 [TSU_FWEN1] = 0x0014, 116 [TSU_FCM] = 0x0018, 117 [TSU_BSYSL0] = 0x0020, 118 [TSU_BSYSL1] = 0x0024, 119 [TSU_PRISL0] = 0x0028, 120 [TSU_PRISL1] = 0x002c, 121 [TSU_FWSL0] = 0x0030, 122 [TSU_FWSL1] = 0x0034, 123 [TSU_FWSLC] = 0x0038, 124 [TSU_QTAGM0] = 0x0040, 125 [TSU_QTAGM1] = 0x0044, 126 [TSU_FWSR] = 0x0050, 127 [TSU_FWINMK] = 0x0054, 128 [TSU_ADQT0] = 0x0048, 129 [TSU_ADQT1] = 0x004c, 130 [TSU_VTAG0] = 0x0058, 131 [TSU_VTAG1] = 0x005c, 132 [TSU_ADSBSY] = 0x0060, 133 [TSU_TEN] = 0x0064, 134 [TSU_POST1] = 0x0070, 135 [TSU_POST2] = 0x0074, 136 [TSU_POST3] = 0x0078, 137 [TSU_POST4] = 0x007c, 138 [TSU_ADRH0] = 0x0100, 139 140 [TXNLCR0] = 0x0080, 141 [TXALCR0] = 0x0084, 142 [RXNLCR0] = 0x0088, 143 [RXALCR0] = 0x008c, 144 [FWNLCR0] = 0x0090, 145 [FWALCR0] = 0x0094, 146 [TXNLCR1] = 0x00a0, 147 [TXALCR1] = 0x00a4, 148 [RXNLCR1] = 0x00a8, 149 [RXALCR1] = 0x00ac, 150 [FWNLCR1] = 0x00b0, 151 [FWALCR1] = 0x00b4, 152 }; 153 154 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 155 SH_ETH_OFFSET_DEFAULTS, 156 157 [ECMR] = 0x0300, 158 [RFLR] = 0x0308, 159 [ECSR] = 0x0310, 160 [ECSIPR] = 0x0318, 161 [PIR] = 0x0320, 162 [PSR] = 0x0328, 163 [RDMLR] = 0x0340, 164 [IPGR] = 0x0350, 165 [APR] = 0x0354, 166 [MPR] = 0x0358, 167 [RFCF] = 0x0360, 168 [TPAUSER] = 0x0364, 169 [TPAUSECR] = 0x0368, 170 [MAHR] = 0x03c0, 171 [MALR] = 0x03c8, 172 [TROCR] = 0x03d0, 173 [CDCR] = 0x03d4, 174 [LCCR] = 0x03d8, 175 [CNDCR] = 0x03dc, 176 [CEFCR] = 0x03e4, 177 [FRECR] = 0x03e8, 178 [TSFRCR] = 0x03ec, 179 [TLFRCR] = 0x03f0, 180 [RFCR] = 0x03f4, 181 [MAFCR] = 0x03f8, 182 183 [EDMR] = 0x0200, 184 [EDTRR] = 0x0208, 185 [EDRRR] = 0x0210, 186 [TDLAR] = 0x0218, 187 [RDLAR] = 0x0220, 188 [EESR] = 0x0228, 189 [EESIPR] = 0x0230, 190 [TRSCER] = 0x0238, 191 [RMFCR] = 0x0240, 192 [TFTR] = 0x0248, 193 [FDR] = 0x0250, 194 [RMCR] = 0x0258, 195 [TFUCR] = 0x0264, 196 [RFOCR] = 0x0268, 197 [RMIIMODE] = 0x026c, 198 [FCFTR] = 0x0270, 199 [TRIMD] = 0x027c, 200 }; 201 202 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 203 SH_ETH_OFFSET_DEFAULTS, 204 205 [ECMR] = 0x0100, 206 [RFLR] = 0x0108, 207 [ECSR] = 0x0110, 208 [ECSIPR] = 0x0118, 209 [PIR] = 0x0120, 210 [PSR] = 0x0128, 211 [RDMLR] = 0x0140, 212 [IPGR] = 0x0150, 213 [APR] = 0x0154, 214 [MPR] = 0x0158, 215 [TPAUSER] = 0x0164, 216 [RFCF] = 0x0160, 217 [TPAUSECR] = 0x0168, 218 [BCFRR] = 0x016c, 219 [MAHR] = 0x01c0, 220 [MALR] = 0x01c8, 221 [TROCR] = 0x01d0, 222 [CDCR] = 0x01d4, 223 [LCCR] = 0x01d8, 224 [CNDCR] = 0x01dc, 225 [CEFCR] = 0x01e4, 226 [FRECR] = 0x01e8, 227 [TSFRCR] = 0x01ec, 228 [TLFRCR] = 0x01f0, 229 [RFCR] = 0x01f4, 230 [MAFCR] = 0x01f8, 231 [RTRATE] = 0x01fc, 232 233 [EDMR] = 0x0000, 234 [EDTRR] = 0x0008, 235 [EDRRR] = 0x0010, 236 [TDLAR] = 0x0018, 237 [RDLAR] = 0x0020, 238 [EESR] = 0x0028, 239 [EESIPR] = 0x0030, 240 [TRSCER] = 0x0038, 241 [RMFCR] = 0x0040, 242 [TFTR] = 0x0048, 243 [FDR] = 0x0050, 244 [RMCR] = 0x0058, 245 [TFUCR] = 0x0064, 246 [RFOCR] = 0x0068, 247 [FCFTR] = 0x0070, 248 [RPADIR] = 0x0078, 249 [TRIMD] = 0x007c, 250 [RBWAR] = 0x00c8, 251 [RDFAR] = 0x00cc, 252 [TBRAR] = 0x00d4, 253 [TDFAR] = 0x00d8, 254 }; 255 256 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 257 SH_ETH_OFFSET_DEFAULTS, 258 259 [EDMR] = 0x0000, 260 [EDTRR] = 0x0004, 261 [EDRRR] = 0x0008, 262 [TDLAR] = 0x000c, 263 [RDLAR] = 0x0010, 264 [EESR] = 0x0014, 265 [EESIPR] = 0x0018, 266 [TRSCER] = 0x001c, 267 [RMFCR] = 0x0020, 268 [TFTR] = 0x0024, 269 [FDR] = 0x0028, 270 [RMCR] = 0x002c, 271 [EDOCR] = 0x0030, 272 [FCFTR] = 0x0034, 273 [RPADIR] = 0x0038, 274 [TRIMD] = 0x003c, 275 [RBWAR] = 0x0040, 276 [RDFAR] = 0x0044, 277 [TBRAR] = 0x004c, 278 [TDFAR] = 0x0050, 279 280 [ECMR] = 0x0160, 281 [ECSR] = 0x0164, 282 [ECSIPR] = 0x0168, 283 [PIR] = 0x016c, 284 [MAHR] = 0x0170, 285 [MALR] = 0x0174, 286 [RFLR] = 0x0178, 287 [PSR] = 0x017c, 288 [TROCR] = 0x0180, 289 [CDCR] = 0x0184, 290 [LCCR] = 0x0188, 291 [CNDCR] = 0x018c, 292 [CEFCR] = 0x0194, 293 [FRECR] = 0x0198, 294 [TSFRCR] = 0x019c, 295 [TLFRCR] = 0x01a0, 296 [RFCR] = 0x01a4, 297 [MAFCR] = 0x01a8, 298 [IPGR] = 0x01b4, 299 [APR] = 0x01b8, 300 [MPR] = 0x01bc, 301 [TPAUSER] = 0x01c4, 302 [BCFR] = 0x01cc, 303 304 [ARSTR] = 0x0000, 305 [TSU_CTRST] = 0x0004, 306 [TSU_FWEN0] = 0x0010, 307 [TSU_FWEN1] = 0x0014, 308 [TSU_FCM] = 0x0018, 309 [TSU_BSYSL0] = 0x0020, 310 [TSU_BSYSL1] = 0x0024, 311 [TSU_PRISL0] = 0x0028, 312 [TSU_PRISL1] = 0x002c, 313 [TSU_FWSL0] = 0x0030, 314 [TSU_FWSL1] = 0x0034, 315 [TSU_FWSLC] = 0x0038, 316 [TSU_QTAGM0] = 0x0040, 317 [TSU_QTAGM1] = 0x0044, 318 [TSU_ADQT0] = 0x0048, 319 [TSU_ADQT1] = 0x004c, 320 [TSU_FWSR] = 0x0050, 321 [TSU_FWINMK] = 0x0054, 322 [TSU_ADSBSY] = 0x0060, 323 [TSU_TEN] = 0x0064, 324 [TSU_POST1] = 0x0070, 325 [TSU_POST2] = 0x0074, 326 [TSU_POST3] = 0x0078, 327 [TSU_POST4] = 0x007c, 328 329 [TXNLCR0] = 0x0080, 330 [TXALCR0] = 0x0084, 331 [RXNLCR0] = 0x0088, 332 [RXALCR0] = 0x008c, 333 [FWNLCR0] = 0x0090, 334 [FWALCR0] = 0x0094, 335 [TXNLCR1] = 0x00a0, 336 [TXALCR1] = 0x00a4, 337 [RXNLCR1] = 0x00a8, 338 [RXALCR1] = 0x00ac, 339 [FWNLCR1] = 0x00b0, 340 [FWALCR1] = 0x00b4, 341 342 [TSU_ADRH0] = 0x0100, 343 }; 344 __diag_pop(); 345 346 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 347 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 348 349 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 350 { 351 struct sh_eth_private *mdp = netdev_priv(ndev); 352 u16 offset = mdp->reg_offset[enum_index]; 353 354 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 355 return; 356 357 iowrite32(data, mdp->addr + offset); 358 } 359 360 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 361 { 362 struct sh_eth_private *mdp = netdev_priv(ndev); 363 u16 offset = mdp->reg_offset[enum_index]; 364 365 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 366 return ~0U; 367 368 return ioread32(mdp->addr + offset); 369 } 370 371 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 372 u32 set) 373 { 374 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 375 enum_index); 376 } 377 378 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index) 379 { 380 return mdp->reg_offset[enum_index]; 381 } 382 383 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data, 384 int enum_index) 385 { 386 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 387 388 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 389 return; 390 391 iowrite32(data, mdp->tsu_addr + offset); 392 } 393 394 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index) 395 { 396 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 397 398 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 399 return ~0U; 400 401 return ioread32(mdp->tsu_addr + offset); 402 } 403 404 static void sh_eth_soft_swap(char *src, int len) 405 { 406 #ifdef __LITTLE_ENDIAN 407 u32 *p = (u32 *)src; 408 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32)); 409 410 for (; p < maxp; p++) 411 *p = swab32(*p); 412 #endif 413 } 414 415 static void sh_eth_select_mii(struct net_device *ndev) 416 { 417 struct sh_eth_private *mdp = netdev_priv(ndev); 418 u32 value; 419 420 switch (mdp->phy_interface) { 421 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID: 422 value = 0x3; 423 break; 424 case PHY_INTERFACE_MODE_GMII: 425 value = 0x2; 426 break; 427 case PHY_INTERFACE_MODE_MII: 428 value = 0x1; 429 break; 430 case PHY_INTERFACE_MODE_RMII: 431 value = 0x0; 432 break; 433 default: 434 netdev_warn(ndev, 435 "PHY interface mode was not setup. Set to MII.\n"); 436 value = 0x1; 437 break; 438 } 439 440 sh_eth_write(ndev, value, RMII_MII); 441 } 442 443 static void sh_eth_set_duplex(struct net_device *ndev) 444 { 445 struct sh_eth_private *mdp = netdev_priv(ndev); 446 447 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 448 } 449 450 static void sh_eth_chip_reset(struct net_device *ndev) 451 { 452 struct sh_eth_private *mdp = netdev_priv(ndev); 453 454 /* reset device */ 455 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 456 mdelay(1); 457 } 458 459 static int sh_eth_soft_reset(struct net_device *ndev) 460 { 461 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 462 mdelay(3); 463 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 464 465 return 0; 466 } 467 468 static int sh_eth_check_soft_reset(struct net_device *ndev) 469 { 470 int cnt; 471 472 for (cnt = 100; cnt > 0; cnt--) { 473 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 474 return 0; 475 mdelay(1); 476 } 477 478 netdev_err(ndev, "Device reset failed\n"); 479 return -ETIMEDOUT; 480 } 481 482 static int sh_eth_soft_reset_gether(struct net_device *ndev) 483 { 484 struct sh_eth_private *mdp = netdev_priv(ndev); 485 int ret; 486 487 sh_eth_write(ndev, EDSR_ENALL, EDSR); 488 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 489 490 ret = sh_eth_check_soft_reset(ndev); 491 if (ret) 492 return ret; 493 494 /* Table Init */ 495 sh_eth_write(ndev, 0, TDLAR); 496 sh_eth_write(ndev, 0, TDFAR); 497 sh_eth_write(ndev, 0, TDFXR); 498 sh_eth_write(ndev, 0, TDFFR); 499 sh_eth_write(ndev, 0, RDLAR); 500 sh_eth_write(ndev, 0, RDFAR); 501 sh_eth_write(ndev, 0, RDFXR); 502 sh_eth_write(ndev, 0, RDFFR); 503 504 /* Reset HW CRC register */ 505 if (mdp->cd->csmr) 506 sh_eth_write(ndev, 0, CSMR); 507 508 /* Select MII mode */ 509 if (mdp->cd->select_mii) 510 sh_eth_select_mii(ndev); 511 512 return ret; 513 } 514 515 static void sh_eth_set_rate_gether(struct net_device *ndev) 516 { 517 struct sh_eth_private *mdp = netdev_priv(ndev); 518 519 if (WARN_ON(!mdp->cd->gecmr)) 520 return; 521 522 switch (mdp->speed) { 523 case 10: /* 10BASE */ 524 sh_eth_write(ndev, GECMR_10, GECMR); 525 break; 526 case 100:/* 100BASE */ 527 sh_eth_write(ndev, GECMR_100, GECMR); 528 break; 529 case 1000: /* 1000BASE */ 530 sh_eth_write(ndev, GECMR_1000, GECMR); 531 break; 532 } 533 } 534 535 #ifdef CONFIG_OF 536 /* R7S72100 */ 537 static struct sh_eth_cpu_data r7s72100_data = { 538 .soft_reset = sh_eth_soft_reset_gether, 539 540 .chip_reset = sh_eth_chip_reset, 541 .set_duplex = sh_eth_set_duplex, 542 543 .register_type = SH_ETH_REG_GIGABIT, 544 545 .edtrr_trns = EDTRR_TRNS_GETHER, 546 .ecsr_value = ECSR_ICD, 547 .ecsipr_value = ECSIPR_ICDIP, 548 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 549 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 550 EESIPR_ECIIP | 551 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 552 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 553 EESIPR_RMAFIP | EESIPR_RRFIP | 554 EESIPR_RTLFIP | EESIPR_RTSFIP | 555 EESIPR_PREIP | EESIPR_CERFIP, 556 557 .tx_check = EESR_TC1 | EESR_FTC, 558 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 559 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 560 EESR_TDE, 561 .fdr_value = 0x0000070f, 562 563 .no_psr = 1, 564 .apr = 1, 565 .mpr = 1, 566 .tpauser = 1, 567 .hw_swap = 1, 568 .rpadir = 1, 569 .no_trimd = 1, 570 .no_ade = 1, 571 .xdfar_rw = 1, 572 .csmr = 1, 573 .rx_csum = 1, 574 .tsu = 1, 575 .no_tx_cntrs = 1, 576 }; 577 578 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 579 { 580 sh_eth_chip_reset(ndev); 581 582 sh_eth_select_mii(ndev); 583 } 584 585 /* R8A7740 */ 586 static struct sh_eth_cpu_data r8a7740_data = { 587 .soft_reset = sh_eth_soft_reset_gether, 588 589 .chip_reset = sh_eth_chip_reset_r8a7740, 590 .set_duplex = sh_eth_set_duplex, 591 .set_rate = sh_eth_set_rate_gether, 592 593 .register_type = SH_ETH_REG_GIGABIT, 594 595 .edtrr_trns = EDTRR_TRNS_GETHER, 596 .ecsr_value = ECSR_ICD | ECSR_MPD, 597 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 598 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 599 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 600 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 601 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 602 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 603 EESIPR_CEEFIP | EESIPR_CELFIP | 604 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 605 EESIPR_PREIP | EESIPR_CERFIP, 606 607 .tx_check = EESR_TC1 | EESR_FTC, 608 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 609 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 610 EESR_TDE, 611 .fdr_value = 0x0000070f, 612 613 .apr = 1, 614 .mpr = 1, 615 .tpauser = 1, 616 .gecmr = 1, 617 .bculr = 1, 618 .hw_swap = 1, 619 .rpadir = 1, 620 .no_trimd = 1, 621 .no_ade = 1, 622 .xdfar_rw = 1, 623 .csmr = 1, 624 .rx_csum = 1, 625 .tsu = 1, 626 .select_mii = 1, 627 .magic = 1, 628 .cexcr = 1, 629 }; 630 631 /* There is CPU dependent code */ 632 static void sh_eth_set_rate_rcar(struct net_device *ndev) 633 { 634 struct sh_eth_private *mdp = netdev_priv(ndev); 635 636 switch (mdp->speed) { 637 case 10: /* 10BASE */ 638 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 639 break; 640 case 100:/* 100BASE */ 641 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 642 break; 643 } 644 } 645 646 /* R-Car Gen1 */ 647 static struct sh_eth_cpu_data rcar_gen1_data = { 648 .soft_reset = sh_eth_soft_reset, 649 650 .set_duplex = sh_eth_set_duplex, 651 .set_rate = sh_eth_set_rate_rcar, 652 653 .register_type = SH_ETH_REG_FAST_RCAR, 654 655 .edtrr_trns = EDTRR_TRNS_ETHER, 656 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 657 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 658 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 659 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 660 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 661 EESIPR_RMAFIP | EESIPR_RRFIP | 662 EESIPR_RTLFIP | EESIPR_RTSFIP | 663 EESIPR_PREIP | EESIPR_CERFIP, 664 665 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 666 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 667 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 668 .fdr_value = 0x00000f0f, 669 670 .apr = 1, 671 .mpr = 1, 672 .tpauser = 1, 673 .hw_swap = 1, 674 .no_xdfar = 1, 675 }; 676 677 /* R-Car Gen2 and RZ/G1 */ 678 static struct sh_eth_cpu_data rcar_gen2_data = { 679 .soft_reset = sh_eth_soft_reset, 680 681 .set_duplex = sh_eth_set_duplex, 682 .set_rate = sh_eth_set_rate_rcar, 683 684 .register_type = SH_ETH_REG_FAST_RCAR, 685 686 .edtrr_trns = EDTRR_TRNS_ETHER, 687 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 688 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 689 ECSIPR_MPDIP, 690 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 691 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 692 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 693 EESIPR_RMAFIP | EESIPR_RRFIP | 694 EESIPR_RTLFIP | EESIPR_RTSFIP | 695 EESIPR_PREIP | EESIPR_CERFIP, 696 697 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 698 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 699 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 700 .fdr_value = 0x00000f0f, 701 702 .trscer_err_mask = DESC_I_RINT8, 703 704 .apr = 1, 705 .mpr = 1, 706 .tpauser = 1, 707 .hw_swap = 1, 708 .no_xdfar = 1, 709 .rmiimode = 1, 710 .magic = 1, 711 }; 712 713 /* R8A77980 */ 714 static struct sh_eth_cpu_data r8a77980_data = { 715 .soft_reset = sh_eth_soft_reset_gether, 716 717 .set_duplex = sh_eth_set_duplex, 718 .set_rate = sh_eth_set_rate_gether, 719 720 .register_type = SH_ETH_REG_GIGABIT, 721 722 .edtrr_trns = EDTRR_TRNS_GETHER, 723 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 724 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 725 ECSIPR_MPDIP, 726 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 727 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 728 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 729 EESIPR_RMAFIP | EESIPR_RRFIP | 730 EESIPR_RTLFIP | EESIPR_RTSFIP | 731 EESIPR_PREIP | EESIPR_CERFIP, 732 733 .tx_check = EESR_FTC | EESR_CD | EESR_TRO, 734 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 735 EESR_RFE | EESR_RDE | EESR_RFRMER | 736 EESR_TFE | EESR_TDE | EESR_ECI, 737 .fdr_value = 0x0000070f, 738 739 .apr = 1, 740 .mpr = 1, 741 .tpauser = 1, 742 .gecmr = 1, 743 .bculr = 1, 744 .hw_swap = 1, 745 .nbst = 1, 746 .rpadir = 1, 747 .no_trimd = 1, 748 .no_ade = 1, 749 .xdfar_rw = 1, 750 .csmr = 1, 751 .rx_csum = 1, 752 .select_mii = 1, 753 .magic = 1, 754 .cexcr = 1, 755 }; 756 757 /* R7S9210 */ 758 static struct sh_eth_cpu_data r7s9210_data = { 759 .soft_reset = sh_eth_soft_reset, 760 761 .set_duplex = sh_eth_set_duplex, 762 .set_rate = sh_eth_set_rate_rcar, 763 764 .register_type = SH_ETH_REG_FAST_SH4, 765 766 .edtrr_trns = EDTRR_TRNS_ETHER, 767 .ecsr_value = ECSR_ICD, 768 .ecsipr_value = ECSIPR_ICDIP, 769 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP | 770 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP | 771 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP | 772 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP | 773 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 774 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP | 775 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP, 776 777 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 778 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 779 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 780 781 .fdr_value = 0x0000070f, 782 783 .apr = 1, 784 .mpr = 1, 785 .tpauser = 1, 786 .hw_swap = 1, 787 .rpadir = 1, 788 .no_ade = 1, 789 .xdfar_rw = 1, 790 }; 791 #endif /* CONFIG_OF */ 792 793 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 794 { 795 struct sh_eth_private *mdp = netdev_priv(ndev); 796 797 switch (mdp->speed) { 798 case 10: /* 10BASE */ 799 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 800 break; 801 case 100:/* 100BASE */ 802 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 803 break; 804 } 805 } 806 807 /* SH7724 */ 808 static struct sh_eth_cpu_data sh7724_data = { 809 .soft_reset = sh_eth_soft_reset, 810 811 .set_duplex = sh_eth_set_duplex, 812 .set_rate = sh_eth_set_rate_sh7724, 813 814 .register_type = SH_ETH_REG_FAST_SH4, 815 816 .edtrr_trns = EDTRR_TRNS_ETHER, 817 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 818 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 819 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 820 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 821 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 822 EESIPR_RMAFIP | EESIPR_RRFIP | 823 EESIPR_RTLFIP | EESIPR_RTSFIP | 824 EESIPR_PREIP | EESIPR_CERFIP, 825 826 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 827 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 828 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 829 830 .apr = 1, 831 .mpr = 1, 832 .tpauser = 1, 833 .hw_swap = 1, 834 .rpadir = 1, 835 }; 836 837 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 838 { 839 struct sh_eth_private *mdp = netdev_priv(ndev); 840 841 switch (mdp->speed) { 842 case 10: /* 10BASE */ 843 sh_eth_write(ndev, 0, RTRATE); 844 break; 845 case 100:/* 100BASE */ 846 sh_eth_write(ndev, 1, RTRATE); 847 break; 848 } 849 } 850 851 /* SH7757 */ 852 static struct sh_eth_cpu_data sh7757_data = { 853 .soft_reset = sh_eth_soft_reset, 854 855 .set_duplex = sh_eth_set_duplex, 856 .set_rate = sh_eth_set_rate_sh7757, 857 858 .register_type = SH_ETH_REG_FAST_SH4, 859 860 .edtrr_trns = EDTRR_TRNS_ETHER, 861 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 862 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 863 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 864 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 865 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 866 EESIPR_CEEFIP | EESIPR_CELFIP | 867 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 868 EESIPR_PREIP | EESIPR_CERFIP, 869 870 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 871 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 872 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 873 874 .irq_flags = IRQF_SHARED, 875 .apr = 1, 876 .mpr = 1, 877 .tpauser = 1, 878 .hw_swap = 1, 879 .no_ade = 1, 880 .rpadir = 1, 881 .rtrate = 1, 882 .dual_port = 1, 883 }; 884 885 #define SH_GIGA_ETH_BASE 0xfee00000UL 886 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 887 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 888 static void sh_eth_chip_reset_giga(struct net_device *ndev) 889 { 890 u32 mahr[2], malr[2]; 891 int i; 892 893 /* save MAHR and MALR */ 894 for (i = 0; i < 2; i++) { 895 malr[i] = ioread32((void *)GIGA_MALR(i)); 896 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 897 } 898 899 sh_eth_chip_reset(ndev); 900 901 /* restore MAHR and MALR */ 902 for (i = 0; i < 2; i++) { 903 iowrite32(malr[i], (void *)GIGA_MALR(i)); 904 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 905 } 906 } 907 908 static void sh_eth_set_rate_giga(struct net_device *ndev) 909 { 910 struct sh_eth_private *mdp = netdev_priv(ndev); 911 912 if (WARN_ON(!mdp->cd->gecmr)) 913 return; 914 915 switch (mdp->speed) { 916 case 10: /* 10BASE */ 917 sh_eth_write(ndev, 0x00000000, GECMR); 918 break; 919 case 100:/* 100BASE */ 920 sh_eth_write(ndev, 0x00000010, GECMR); 921 break; 922 case 1000: /* 1000BASE */ 923 sh_eth_write(ndev, 0x00000020, GECMR); 924 break; 925 } 926 } 927 928 /* SH7757(GETHERC) */ 929 static struct sh_eth_cpu_data sh7757_data_giga = { 930 .soft_reset = sh_eth_soft_reset_gether, 931 932 .chip_reset = sh_eth_chip_reset_giga, 933 .set_duplex = sh_eth_set_duplex, 934 .set_rate = sh_eth_set_rate_giga, 935 936 .register_type = SH_ETH_REG_GIGABIT, 937 938 .edtrr_trns = EDTRR_TRNS_GETHER, 939 .ecsr_value = ECSR_ICD | ECSR_MPD, 940 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 941 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 942 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 943 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 944 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 945 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 946 EESIPR_CEEFIP | EESIPR_CELFIP | 947 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 948 EESIPR_PREIP | EESIPR_CERFIP, 949 950 .tx_check = EESR_TC1 | EESR_FTC, 951 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 952 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 953 EESR_TDE, 954 .fdr_value = 0x0000072f, 955 956 .irq_flags = IRQF_SHARED, 957 .apr = 1, 958 .mpr = 1, 959 .tpauser = 1, 960 .gecmr = 1, 961 .bculr = 1, 962 .hw_swap = 1, 963 .rpadir = 1, 964 .no_trimd = 1, 965 .no_ade = 1, 966 .xdfar_rw = 1, 967 .tsu = 1, 968 .cexcr = 1, 969 .dual_port = 1, 970 }; 971 972 /* SH7734 */ 973 static struct sh_eth_cpu_data sh7734_data = { 974 .soft_reset = sh_eth_soft_reset_gether, 975 976 .chip_reset = sh_eth_chip_reset, 977 .set_duplex = sh_eth_set_duplex, 978 .set_rate = sh_eth_set_rate_gether, 979 980 .register_type = SH_ETH_REG_GIGABIT, 981 982 .edtrr_trns = EDTRR_TRNS_GETHER, 983 .ecsr_value = ECSR_ICD | ECSR_MPD, 984 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 985 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 986 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 987 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 988 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 989 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 990 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 991 EESIPR_PREIP | EESIPR_CERFIP, 992 993 .tx_check = EESR_TC1 | EESR_FTC, 994 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 995 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 996 EESR_TDE, 997 998 .apr = 1, 999 .mpr = 1, 1000 .tpauser = 1, 1001 .gecmr = 1, 1002 .bculr = 1, 1003 .hw_swap = 1, 1004 .no_trimd = 1, 1005 .no_ade = 1, 1006 .xdfar_rw = 1, 1007 .tsu = 1, 1008 .csmr = 1, 1009 .rx_csum = 1, 1010 .select_mii = 1, 1011 .magic = 1, 1012 .cexcr = 1, 1013 }; 1014 1015 /* SH7763 */ 1016 static struct sh_eth_cpu_data sh7763_data = { 1017 .soft_reset = sh_eth_soft_reset_gether, 1018 1019 .chip_reset = sh_eth_chip_reset, 1020 .set_duplex = sh_eth_set_duplex, 1021 .set_rate = sh_eth_set_rate_gether, 1022 1023 .register_type = SH_ETH_REG_GIGABIT, 1024 1025 .edtrr_trns = EDTRR_TRNS_GETHER, 1026 .ecsr_value = ECSR_ICD | ECSR_MPD, 1027 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 1028 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1029 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1030 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1031 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1032 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1033 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1034 EESIPR_PREIP | EESIPR_CERFIP, 1035 1036 .tx_check = EESR_TC1 | EESR_FTC, 1037 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1038 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 1039 1040 .apr = 1, 1041 .mpr = 1, 1042 .tpauser = 1, 1043 .gecmr = 1, 1044 .bculr = 1, 1045 .hw_swap = 1, 1046 .no_trimd = 1, 1047 .no_ade = 1, 1048 .xdfar_rw = 1, 1049 .tsu = 1, 1050 .irq_flags = IRQF_SHARED, 1051 .magic = 1, 1052 .cexcr = 1, 1053 .rx_csum = 1, 1054 .dual_port = 1, 1055 }; 1056 1057 static struct sh_eth_cpu_data sh7619_data = { 1058 .soft_reset = sh_eth_soft_reset, 1059 1060 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1061 1062 .edtrr_trns = EDTRR_TRNS_ETHER, 1063 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1064 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1065 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1066 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1067 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1068 EESIPR_CEEFIP | EESIPR_CELFIP | 1069 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1070 EESIPR_PREIP | EESIPR_CERFIP, 1071 1072 .apr = 1, 1073 .mpr = 1, 1074 .tpauser = 1, 1075 .hw_swap = 1, 1076 }; 1077 1078 static struct sh_eth_cpu_data sh771x_data = { 1079 .soft_reset = sh_eth_soft_reset, 1080 1081 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1082 1083 .edtrr_trns = EDTRR_TRNS_ETHER, 1084 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1085 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1086 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1087 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1088 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1089 EESIPR_CEEFIP | EESIPR_CELFIP | 1090 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1091 EESIPR_PREIP | EESIPR_CERFIP, 1092 .tsu = 1, 1093 .dual_port = 1, 1094 }; 1095 1096 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 1097 { 1098 if (!cd->ecsr_value) 1099 cd->ecsr_value = DEFAULT_ECSR_INIT; 1100 1101 if (!cd->ecsipr_value) 1102 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 1103 1104 if (!cd->fcftr_value) 1105 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 1106 DEFAULT_FIFO_F_D_RFD; 1107 1108 if (!cd->fdr_value) 1109 cd->fdr_value = DEFAULT_FDR_INIT; 1110 1111 if (!cd->tx_check) 1112 cd->tx_check = DEFAULT_TX_CHECK; 1113 1114 if (!cd->eesr_err_check) 1115 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 1116 1117 if (!cd->trscer_err_mask) 1118 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 1119 } 1120 1121 static void sh_eth_set_receive_align(struct sk_buff *skb) 1122 { 1123 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1124 1125 if (reserve) 1126 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1127 } 1128 1129 /* Program the hardware MAC address from dev->dev_addr. */ 1130 static void update_mac_address(struct net_device *ndev) 1131 { 1132 sh_eth_write(ndev, 1133 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1134 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1135 sh_eth_write(ndev, 1136 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1137 } 1138 1139 /* Get MAC address from SuperH MAC address register 1140 * 1141 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1142 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1143 * When you want use this device, you must set MAC address in bootloader. 1144 * 1145 */ 1146 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1147 { 1148 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1149 memcpy(ndev->dev_addr, mac, ETH_ALEN); 1150 } else { 1151 u32 mahr = sh_eth_read(ndev, MAHR); 1152 u32 malr = sh_eth_read(ndev, MALR); 1153 1154 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 1155 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 1156 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 1157 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 1158 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 1159 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 1160 } 1161 } 1162 1163 struct bb_info { 1164 void (*set_gate)(void *addr); 1165 struct mdiobb_ctrl ctrl; 1166 void *addr; 1167 }; 1168 1169 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1170 { 1171 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1172 u32 pir; 1173 1174 if (bitbang->set_gate) 1175 bitbang->set_gate(bitbang->addr); 1176 1177 pir = ioread32(bitbang->addr); 1178 if (set) 1179 pir |= mask; 1180 else 1181 pir &= ~mask; 1182 iowrite32(pir, bitbang->addr); 1183 } 1184 1185 /* Data I/O pin control */ 1186 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1187 { 1188 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1189 } 1190 1191 /* Set bit data*/ 1192 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1193 { 1194 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1195 } 1196 1197 /* Get bit data*/ 1198 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1199 { 1200 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1201 1202 if (bitbang->set_gate) 1203 bitbang->set_gate(bitbang->addr); 1204 1205 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1206 } 1207 1208 /* MDC pin control */ 1209 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1210 { 1211 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1212 } 1213 1214 /* mdio bus control struct */ 1215 static const struct mdiobb_ops bb_ops = { 1216 .owner = THIS_MODULE, 1217 .set_mdc = sh_mdc_ctrl, 1218 .set_mdio_dir = sh_mmd_ctrl, 1219 .set_mdio_data = sh_set_mdio, 1220 .get_mdio_data = sh_get_mdio, 1221 }; 1222 1223 /* free Tx skb function */ 1224 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) 1225 { 1226 struct sh_eth_private *mdp = netdev_priv(ndev); 1227 struct sh_eth_txdesc *txdesc; 1228 int free_num = 0; 1229 int entry; 1230 bool sent; 1231 1232 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1233 entry = mdp->dirty_tx % mdp->num_tx_ring; 1234 txdesc = &mdp->tx_ring[entry]; 1235 sent = !(txdesc->status & cpu_to_le32(TD_TACT)); 1236 if (sent_only && !sent) 1237 break; 1238 /* TACT bit must be checked before all the following reads */ 1239 dma_rmb(); 1240 netif_info(mdp, tx_done, ndev, 1241 "tx entry %d status 0x%08x\n", 1242 entry, le32_to_cpu(txdesc->status)); 1243 /* Free the original skb. */ 1244 if (mdp->tx_skbuff[entry]) { 1245 dma_unmap_single(&mdp->pdev->dev, 1246 le32_to_cpu(txdesc->addr), 1247 le32_to_cpu(txdesc->len) >> 16, 1248 DMA_TO_DEVICE); 1249 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1250 mdp->tx_skbuff[entry] = NULL; 1251 free_num++; 1252 } 1253 txdesc->status = cpu_to_le32(TD_TFP); 1254 if (entry >= mdp->num_tx_ring - 1) 1255 txdesc->status |= cpu_to_le32(TD_TDLE); 1256 1257 if (sent) { 1258 ndev->stats.tx_packets++; 1259 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1260 } 1261 } 1262 return free_num; 1263 } 1264 1265 /* free skb and descriptor buffer */ 1266 static void sh_eth_ring_free(struct net_device *ndev) 1267 { 1268 struct sh_eth_private *mdp = netdev_priv(ndev); 1269 int ringsize, i; 1270 1271 if (mdp->rx_ring) { 1272 for (i = 0; i < mdp->num_rx_ring; i++) { 1273 if (mdp->rx_skbuff[i]) { 1274 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; 1275 1276 dma_unmap_single(&mdp->pdev->dev, 1277 le32_to_cpu(rxdesc->addr), 1278 ALIGN(mdp->rx_buf_sz, 32), 1279 DMA_FROM_DEVICE); 1280 } 1281 } 1282 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1283 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, 1284 mdp->rx_desc_dma); 1285 mdp->rx_ring = NULL; 1286 } 1287 1288 /* Free Rx skb ringbuffer */ 1289 if (mdp->rx_skbuff) { 1290 for (i = 0; i < mdp->num_rx_ring; i++) 1291 dev_kfree_skb(mdp->rx_skbuff[i]); 1292 } 1293 kfree(mdp->rx_skbuff); 1294 mdp->rx_skbuff = NULL; 1295 1296 if (mdp->tx_ring) { 1297 sh_eth_tx_free(ndev, false); 1298 1299 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1300 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, 1301 mdp->tx_desc_dma); 1302 mdp->tx_ring = NULL; 1303 } 1304 1305 /* Free Tx skb ringbuffer */ 1306 kfree(mdp->tx_skbuff); 1307 mdp->tx_skbuff = NULL; 1308 } 1309 1310 /* format skb and descriptor buffer */ 1311 static void sh_eth_ring_format(struct net_device *ndev) 1312 { 1313 struct sh_eth_private *mdp = netdev_priv(ndev); 1314 int i; 1315 struct sk_buff *skb; 1316 struct sh_eth_rxdesc *rxdesc = NULL; 1317 struct sh_eth_txdesc *txdesc = NULL; 1318 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1319 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1320 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1321 dma_addr_t dma_addr; 1322 u32 buf_len; 1323 1324 mdp->cur_rx = 0; 1325 mdp->cur_tx = 0; 1326 mdp->dirty_rx = 0; 1327 mdp->dirty_tx = 0; 1328 1329 memset(mdp->rx_ring, 0, rx_ringsize); 1330 1331 /* build Rx ring buffer */ 1332 for (i = 0; i < mdp->num_rx_ring; i++) { 1333 /* skb */ 1334 mdp->rx_skbuff[i] = NULL; 1335 skb = netdev_alloc_skb(ndev, skbuff_size); 1336 if (skb == NULL) 1337 break; 1338 sh_eth_set_receive_align(skb); 1339 1340 /* The size of the buffer is a multiple of 32 bytes. */ 1341 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1342 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, 1343 DMA_FROM_DEVICE); 1344 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1345 kfree_skb(skb); 1346 break; 1347 } 1348 mdp->rx_skbuff[i] = skb; 1349 1350 /* RX descriptor */ 1351 rxdesc = &mdp->rx_ring[i]; 1352 rxdesc->len = cpu_to_le32(buf_len << 16); 1353 rxdesc->addr = cpu_to_le32(dma_addr); 1354 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1355 1356 /* Rx descriptor address set */ 1357 if (i == 0) { 1358 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1359 if (mdp->cd->xdfar_rw) 1360 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1361 } 1362 } 1363 1364 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1365 1366 /* Mark the last entry as wrapping the ring. */ 1367 if (rxdesc) 1368 rxdesc->status |= cpu_to_le32(RD_RDLE); 1369 1370 memset(mdp->tx_ring, 0, tx_ringsize); 1371 1372 /* build Tx ring buffer */ 1373 for (i = 0; i < mdp->num_tx_ring; i++) { 1374 mdp->tx_skbuff[i] = NULL; 1375 txdesc = &mdp->tx_ring[i]; 1376 txdesc->status = cpu_to_le32(TD_TFP); 1377 txdesc->len = cpu_to_le32(0); 1378 if (i == 0) { 1379 /* Tx descriptor address set */ 1380 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1381 if (mdp->cd->xdfar_rw) 1382 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1383 } 1384 } 1385 1386 txdesc->status |= cpu_to_le32(TD_TDLE); 1387 } 1388 1389 /* Get skb and descriptor buffer */ 1390 static int sh_eth_ring_init(struct net_device *ndev) 1391 { 1392 struct sh_eth_private *mdp = netdev_priv(ndev); 1393 int rx_ringsize, tx_ringsize; 1394 1395 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1396 * card needs room to do 8 byte alignment, +2 so we can reserve 1397 * the first 2 bytes, and +16 gets room for the status word from the 1398 * card. 1399 */ 1400 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1401 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1402 if (mdp->cd->rpadir) 1403 mdp->rx_buf_sz += NET_IP_ALIGN; 1404 1405 /* Allocate RX and TX skb rings */ 1406 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1407 GFP_KERNEL); 1408 if (!mdp->rx_skbuff) 1409 return -ENOMEM; 1410 1411 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1412 GFP_KERNEL); 1413 if (!mdp->tx_skbuff) 1414 goto ring_free; 1415 1416 /* Allocate all Rx descriptors. */ 1417 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1418 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, 1419 &mdp->rx_desc_dma, GFP_KERNEL); 1420 if (!mdp->rx_ring) 1421 goto ring_free; 1422 1423 mdp->dirty_rx = 0; 1424 1425 /* Allocate all Tx descriptors. */ 1426 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1427 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, 1428 &mdp->tx_desc_dma, GFP_KERNEL); 1429 if (!mdp->tx_ring) 1430 goto ring_free; 1431 return 0; 1432 1433 ring_free: 1434 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1435 sh_eth_ring_free(ndev); 1436 1437 return -ENOMEM; 1438 } 1439 1440 static int sh_eth_dev_init(struct net_device *ndev) 1441 { 1442 struct sh_eth_private *mdp = netdev_priv(ndev); 1443 int ret; 1444 1445 /* Soft Reset */ 1446 ret = mdp->cd->soft_reset(ndev); 1447 if (ret) 1448 return ret; 1449 1450 if (mdp->cd->rmiimode) 1451 sh_eth_write(ndev, 0x1, RMIIMODE); 1452 1453 /* Descriptor format */ 1454 sh_eth_ring_format(ndev); 1455 if (mdp->cd->rpadir) 1456 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR); 1457 1458 /* all sh_eth int mask */ 1459 sh_eth_write(ndev, 0, EESIPR); 1460 1461 #if defined(__LITTLE_ENDIAN) 1462 if (mdp->cd->hw_swap) 1463 sh_eth_write(ndev, EDMR_EL, EDMR); 1464 else 1465 #endif 1466 sh_eth_write(ndev, 0, EDMR); 1467 1468 /* FIFO size set */ 1469 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1470 sh_eth_write(ndev, 0, TFTR); 1471 1472 /* Frame recv control (enable multiple-packets per rx irq) */ 1473 sh_eth_write(ndev, RMCR_RNC, RMCR); 1474 1475 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1476 1477 /* DMA transfer burst mode */ 1478 if (mdp->cd->nbst) 1479 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST); 1480 1481 /* Burst cycle count upper-limit */ 1482 if (mdp->cd->bculr) 1483 sh_eth_write(ndev, 0x800, BCULR); 1484 1485 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1486 1487 if (!mdp->cd->no_trimd) 1488 sh_eth_write(ndev, 0, TRIMD); 1489 1490 /* Recv frame limit set register */ 1491 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1492 RFLR); 1493 1494 sh_eth_modify(ndev, EESR, 0, 0); 1495 mdp->irq_enabled = true; 1496 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1497 1498 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 1499 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1500 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 1501 ECMR_TE | ECMR_RE, ECMR); 1502 1503 if (mdp->cd->set_rate) 1504 mdp->cd->set_rate(ndev); 1505 1506 /* E-MAC Status Register clear */ 1507 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1508 1509 /* E-MAC Interrupt Enable register */ 1510 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1511 1512 /* Set MAC address */ 1513 update_mac_address(ndev); 1514 1515 /* mask reset */ 1516 if (mdp->cd->apr) 1517 sh_eth_write(ndev, 1, APR); 1518 if (mdp->cd->mpr) 1519 sh_eth_write(ndev, 1, MPR); 1520 if (mdp->cd->tpauser) 1521 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1522 1523 /* Setting the Rx mode will start the Rx process. */ 1524 sh_eth_write(ndev, EDRRR_R, EDRRR); 1525 1526 return ret; 1527 } 1528 1529 static void sh_eth_dev_exit(struct net_device *ndev) 1530 { 1531 struct sh_eth_private *mdp = netdev_priv(ndev); 1532 int i; 1533 1534 /* Deactivate all TX descriptors, so DMA should stop at next 1535 * packet boundary if it's currently running 1536 */ 1537 for (i = 0; i < mdp->num_tx_ring; i++) 1538 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1539 1540 /* Disable TX FIFO egress to MAC */ 1541 sh_eth_rcv_snd_disable(ndev); 1542 1543 /* Stop RX DMA at next packet boundary */ 1544 sh_eth_write(ndev, 0, EDRRR); 1545 1546 /* Aside from TX DMA, we can't tell when the hardware is 1547 * really stopped, so we need to reset to make sure. 1548 * Before doing that, wait for long enough to *probably* 1549 * finish transmitting the last packet and poll stats. 1550 */ 1551 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1552 sh_eth_get_stats(ndev); 1553 mdp->cd->soft_reset(ndev); 1554 1555 /* Set the RMII mode again if required */ 1556 if (mdp->cd->rmiimode) 1557 sh_eth_write(ndev, 0x1, RMIIMODE); 1558 1559 /* Set MAC address again */ 1560 update_mac_address(ndev); 1561 } 1562 1563 static void sh_eth_rx_csum(struct sk_buff *skb) 1564 { 1565 u8 *hw_csum; 1566 1567 /* The hardware checksum is 2 bytes appended to packet data */ 1568 if (unlikely(skb->len < sizeof(__sum16))) 1569 return; 1570 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 1571 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 1572 skb->ip_summed = CHECKSUM_COMPLETE; 1573 skb_trim(skb, skb->len - sizeof(__sum16)); 1574 } 1575 1576 /* Packet receive function */ 1577 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1578 { 1579 struct sh_eth_private *mdp = netdev_priv(ndev); 1580 struct sh_eth_rxdesc *rxdesc; 1581 1582 int entry = mdp->cur_rx % mdp->num_rx_ring; 1583 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1584 int limit; 1585 struct sk_buff *skb; 1586 u32 desc_status; 1587 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1588 dma_addr_t dma_addr; 1589 u16 pkt_len; 1590 u32 buf_len; 1591 1592 boguscnt = min(boguscnt, *quota); 1593 limit = boguscnt; 1594 rxdesc = &mdp->rx_ring[entry]; 1595 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1596 /* RACT bit must be checked before all the following reads */ 1597 dma_rmb(); 1598 desc_status = le32_to_cpu(rxdesc->status); 1599 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1600 1601 if (--boguscnt < 0) 1602 break; 1603 1604 netif_info(mdp, rx_status, ndev, 1605 "rx entry %d status 0x%08x len %d\n", 1606 entry, desc_status, pkt_len); 1607 1608 if (!(desc_status & RDFEND)) 1609 ndev->stats.rx_length_errors++; 1610 1611 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1612 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1613 * bit 0. However, in case of the R8A7740 and R7S72100 1614 * the RFS bits are from bit 25 to bit 16. So, the 1615 * driver needs right shifting by 16. 1616 */ 1617 if (mdp->cd->csmr) 1618 desc_status >>= 16; 1619 1620 skb = mdp->rx_skbuff[entry]; 1621 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1622 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1623 ndev->stats.rx_errors++; 1624 if (desc_status & RD_RFS1) 1625 ndev->stats.rx_crc_errors++; 1626 if (desc_status & RD_RFS2) 1627 ndev->stats.rx_frame_errors++; 1628 if (desc_status & RD_RFS3) 1629 ndev->stats.rx_length_errors++; 1630 if (desc_status & RD_RFS4) 1631 ndev->stats.rx_length_errors++; 1632 if (desc_status & RD_RFS6) 1633 ndev->stats.rx_missed_errors++; 1634 if (desc_status & RD_RFS10) 1635 ndev->stats.rx_over_errors++; 1636 } else if (skb) { 1637 dma_addr = le32_to_cpu(rxdesc->addr); 1638 if (!mdp->cd->hw_swap) 1639 sh_eth_soft_swap( 1640 phys_to_virt(ALIGN(dma_addr, 4)), 1641 pkt_len + 2); 1642 mdp->rx_skbuff[entry] = NULL; 1643 if (mdp->cd->rpadir) 1644 skb_reserve(skb, NET_IP_ALIGN); 1645 dma_unmap_single(&mdp->pdev->dev, dma_addr, 1646 ALIGN(mdp->rx_buf_sz, 32), 1647 DMA_FROM_DEVICE); 1648 skb_put(skb, pkt_len); 1649 skb->protocol = eth_type_trans(skb, ndev); 1650 if (ndev->features & NETIF_F_RXCSUM) 1651 sh_eth_rx_csum(skb); 1652 netif_receive_skb(skb); 1653 ndev->stats.rx_packets++; 1654 ndev->stats.rx_bytes += pkt_len; 1655 if (desc_status & RD_RFS8) 1656 ndev->stats.multicast++; 1657 } 1658 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1659 rxdesc = &mdp->rx_ring[entry]; 1660 } 1661 1662 /* Refill the Rx ring buffers. */ 1663 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1664 entry = mdp->dirty_rx % mdp->num_rx_ring; 1665 rxdesc = &mdp->rx_ring[entry]; 1666 /* The size of the buffer is 32 byte boundary. */ 1667 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1668 rxdesc->len = cpu_to_le32(buf_len << 16); 1669 1670 if (mdp->rx_skbuff[entry] == NULL) { 1671 skb = netdev_alloc_skb(ndev, skbuff_size); 1672 if (skb == NULL) 1673 break; /* Better luck next round. */ 1674 sh_eth_set_receive_align(skb); 1675 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, 1676 buf_len, DMA_FROM_DEVICE); 1677 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1678 kfree_skb(skb); 1679 break; 1680 } 1681 mdp->rx_skbuff[entry] = skb; 1682 1683 skb_checksum_none_assert(skb); 1684 rxdesc->addr = cpu_to_le32(dma_addr); 1685 } 1686 dma_wmb(); /* RACT bit must be set after all the above writes */ 1687 if (entry >= mdp->num_rx_ring - 1) 1688 rxdesc->status |= 1689 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1690 else 1691 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1692 } 1693 1694 /* Restart Rx engine if stopped. */ 1695 /* If we don't need to check status, don't. -KDU */ 1696 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1697 /* fix the values for the next receiving if RDE is set */ 1698 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) { 1699 u32 count = (sh_eth_read(ndev, RDFAR) - 1700 sh_eth_read(ndev, RDLAR)) >> 4; 1701 1702 mdp->cur_rx = count; 1703 mdp->dirty_rx = count; 1704 } 1705 sh_eth_write(ndev, EDRRR_R, EDRRR); 1706 } 1707 1708 *quota -= limit - boguscnt - 1; 1709 1710 return *quota <= 0; 1711 } 1712 1713 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1714 { 1715 /* disable tx and rx */ 1716 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1717 } 1718 1719 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1720 { 1721 /* enable tx and rx */ 1722 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1723 } 1724 1725 /* E-MAC interrupt handler */ 1726 static void sh_eth_emac_interrupt(struct net_device *ndev) 1727 { 1728 struct sh_eth_private *mdp = netdev_priv(ndev); 1729 u32 felic_stat; 1730 u32 link_stat; 1731 1732 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1733 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1734 if (felic_stat & ECSR_ICD) 1735 ndev->stats.tx_carrier_errors++; 1736 if (felic_stat & ECSR_MPD) 1737 pm_wakeup_event(&mdp->pdev->dev, 0); 1738 if (felic_stat & ECSR_LCHNG) { 1739 /* Link Changed */ 1740 if (mdp->cd->no_psr || mdp->no_ether_link) 1741 return; 1742 link_stat = sh_eth_read(ndev, PSR); 1743 if (mdp->ether_link_active_low) 1744 link_stat = ~link_stat; 1745 if (!(link_stat & PHY_ST_LINK)) { 1746 sh_eth_rcv_snd_disable(ndev); 1747 } else { 1748 /* Link Up */ 1749 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1750 /* clear int */ 1751 sh_eth_modify(ndev, ECSR, 0, 0); 1752 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1753 /* enable tx and rx */ 1754 sh_eth_rcv_snd_enable(ndev); 1755 } 1756 } 1757 } 1758 1759 /* error control function */ 1760 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1761 { 1762 struct sh_eth_private *mdp = netdev_priv(ndev); 1763 u32 mask; 1764 1765 if (intr_status & EESR_TWB) { 1766 /* Unused write back interrupt */ 1767 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1768 ndev->stats.tx_aborted_errors++; 1769 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1770 } 1771 } 1772 1773 if (intr_status & EESR_RABT) { 1774 /* Receive Abort int */ 1775 if (intr_status & EESR_RFRMER) { 1776 /* Receive Frame Overflow int */ 1777 ndev->stats.rx_frame_errors++; 1778 } 1779 } 1780 1781 if (intr_status & EESR_TDE) { 1782 /* Transmit Descriptor Empty int */ 1783 ndev->stats.tx_fifo_errors++; 1784 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1785 } 1786 1787 if (intr_status & EESR_TFE) { 1788 /* FIFO under flow */ 1789 ndev->stats.tx_fifo_errors++; 1790 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1791 } 1792 1793 if (intr_status & EESR_RDE) { 1794 /* Receive Descriptor Empty int */ 1795 ndev->stats.rx_over_errors++; 1796 } 1797 1798 if (intr_status & EESR_RFE) { 1799 /* Receive FIFO Overflow int */ 1800 ndev->stats.rx_fifo_errors++; 1801 } 1802 1803 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1804 /* Address Error */ 1805 ndev->stats.tx_fifo_errors++; 1806 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1807 } 1808 1809 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1810 if (mdp->cd->no_ade) 1811 mask &= ~EESR_ADE; 1812 if (intr_status & mask) { 1813 /* Tx error */ 1814 u32 edtrr = sh_eth_read(ndev, EDTRR); 1815 1816 /* dmesg */ 1817 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1818 intr_status, mdp->cur_tx, mdp->dirty_tx, 1819 (u32)ndev->state, edtrr); 1820 /* dirty buffer free */ 1821 sh_eth_tx_free(ndev, true); 1822 1823 /* SH7712 BUG */ 1824 if (edtrr ^ mdp->cd->edtrr_trns) { 1825 /* tx dma start */ 1826 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 1827 } 1828 /* wakeup */ 1829 netif_wake_queue(ndev); 1830 } 1831 } 1832 1833 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1834 { 1835 struct net_device *ndev = netdev; 1836 struct sh_eth_private *mdp = netdev_priv(ndev); 1837 struct sh_eth_cpu_data *cd = mdp->cd; 1838 irqreturn_t ret = IRQ_NONE; 1839 u32 intr_status, intr_enable; 1840 1841 spin_lock(&mdp->lock); 1842 1843 /* Get interrupt status */ 1844 intr_status = sh_eth_read(ndev, EESR); 1845 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1846 * enabled since it's the one that comes thru regardless of the mask, 1847 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1848 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1849 * bit... 1850 */ 1851 intr_enable = sh_eth_read(ndev, EESIPR); 1852 intr_status &= intr_enable | EESIPR_ECIIP; 1853 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1854 cd->eesr_err_check)) 1855 ret = IRQ_HANDLED; 1856 else 1857 goto out; 1858 1859 if (unlikely(!mdp->irq_enabled)) { 1860 sh_eth_write(ndev, 0, EESIPR); 1861 goto out; 1862 } 1863 1864 if (intr_status & EESR_RX_CHECK) { 1865 if (napi_schedule_prep(&mdp->napi)) { 1866 /* Mask Rx interrupts */ 1867 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1868 EESIPR); 1869 __napi_schedule(&mdp->napi); 1870 } else { 1871 netdev_warn(ndev, 1872 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1873 intr_status, intr_enable); 1874 } 1875 } 1876 1877 /* Tx Check */ 1878 if (intr_status & cd->tx_check) { 1879 /* Clear Tx interrupts */ 1880 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1881 1882 sh_eth_tx_free(ndev, true); 1883 netif_wake_queue(ndev); 1884 } 1885 1886 /* E-MAC interrupt */ 1887 if (intr_status & EESR_ECI) 1888 sh_eth_emac_interrupt(ndev); 1889 1890 if (intr_status & cd->eesr_err_check) { 1891 /* Clear error interrupts */ 1892 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1893 1894 sh_eth_error(ndev, intr_status); 1895 } 1896 1897 out: 1898 spin_unlock(&mdp->lock); 1899 1900 return ret; 1901 } 1902 1903 static int sh_eth_poll(struct napi_struct *napi, int budget) 1904 { 1905 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1906 napi); 1907 struct net_device *ndev = napi->dev; 1908 int quota = budget; 1909 u32 intr_status; 1910 1911 for (;;) { 1912 intr_status = sh_eth_read(ndev, EESR); 1913 if (!(intr_status & EESR_RX_CHECK)) 1914 break; 1915 /* Clear Rx interrupts */ 1916 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1917 1918 if (sh_eth_rx(ndev, intr_status, "a)) 1919 goto out; 1920 } 1921 1922 napi_complete(napi); 1923 1924 /* Reenable Rx interrupts */ 1925 if (mdp->irq_enabled) 1926 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1927 out: 1928 return budget - quota; 1929 } 1930 1931 /* PHY state control function */ 1932 static void sh_eth_adjust_link(struct net_device *ndev) 1933 { 1934 struct sh_eth_private *mdp = netdev_priv(ndev); 1935 struct phy_device *phydev = ndev->phydev; 1936 unsigned long flags; 1937 int new_state = 0; 1938 1939 spin_lock_irqsave(&mdp->lock, flags); 1940 1941 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1942 if (mdp->cd->no_psr || mdp->no_ether_link) 1943 sh_eth_rcv_snd_disable(ndev); 1944 1945 if (phydev->link) { 1946 if (phydev->duplex != mdp->duplex) { 1947 new_state = 1; 1948 mdp->duplex = phydev->duplex; 1949 if (mdp->cd->set_duplex) 1950 mdp->cd->set_duplex(ndev); 1951 } 1952 1953 if (phydev->speed != mdp->speed) { 1954 new_state = 1; 1955 mdp->speed = phydev->speed; 1956 if (mdp->cd->set_rate) 1957 mdp->cd->set_rate(ndev); 1958 } 1959 if (!mdp->link) { 1960 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 1961 new_state = 1; 1962 mdp->link = phydev->link; 1963 } 1964 } else if (mdp->link) { 1965 new_state = 1; 1966 mdp->link = 0; 1967 mdp->speed = 0; 1968 mdp->duplex = -1; 1969 } 1970 1971 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1972 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link) 1973 sh_eth_rcv_snd_enable(ndev); 1974 1975 spin_unlock_irqrestore(&mdp->lock, flags); 1976 1977 if (new_state && netif_msg_link(mdp)) 1978 phy_print_status(phydev); 1979 } 1980 1981 /* PHY init function */ 1982 static int sh_eth_phy_init(struct net_device *ndev) 1983 { 1984 struct device_node *np = ndev->dev.parent->of_node; 1985 struct sh_eth_private *mdp = netdev_priv(ndev); 1986 struct phy_device *phydev; 1987 1988 mdp->link = 0; 1989 mdp->speed = 0; 1990 mdp->duplex = -1; 1991 1992 /* Try connect to PHY */ 1993 if (np) { 1994 struct device_node *pn; 1995 1996 pn = of_parse_phandle(np, "phy-handle", 0); 1997 phydev = of_phy_connect(ndev, pn, 1998 sh_eth_adjust_link, 0, 1999 mdp->phy_interface); 2000 2001 of_node_put(pn); 2002 if (!phydev) 2003 phydev = ERR_PTR(-ENOENT); 2004 } else { 2005 char phy_id[MII_BUS_ID_SIZE + 3]; 2006 2007 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 2008 mdp->mii_bus->id, mdp->phy_id); 2009 2010 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 2011 mdp->phy_interface); 2012 } 2013 2014 if (IS_ERR(phydev)) { 2015 netdev_err(ndev, "failed to connect PHY\n"); 2016 return PTR_ERR(phydev); 2017 } 2018 2019 /* mask with MAC supported features */ 2020 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) { 2021 int err = phy_set_max_speed(phydev, SPEED_100); 2022 if (err) { 2023 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n"); 2024 phy_disconnect(phydev); 2025 return err; 2026 } 2027 } 2028 2029 phy_attached_info(phydev); 2030 2031 return 0; 2032 } 2033 2034 /* PHY control start function */ 2035 static int sh_eth_phy_start(struct net_device *ndev) 2036 { 2037 int ret; 2038 2039 ret = sh_eth_phy_init(ndev); 2040 if (ret) 2041 return ret; 2042 2043 phy_start(ndev->phydev); 2044 2045 return 0; 2046 } 2047 2048 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 2049 * version must be bumped as well. Just adding registers up to that 2050 * limit is fine, as long as the existing register indices don't 2051 * change. 2052 */ 2053 #define SH_ETH_REG_DUMP_VERSION 1 2054 #define SH_ETH_REG_DUMP_MAX_REGS 256 2055 2056 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 2057 { 2058 struct sh_eth_private *mdp = netdev_priv(ndev); 2059 struct sh_eth_cpu_data *cd = mdp->cd; 2060 u32 *valid_map; 2061 size_t len; 2062 2063 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 2064 2065 /* Dump starts with a bitmap that tells ethtool which 2066 * registers are defined for this chip. 2067 */ 2068 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 2069 if (buf) { 2070 valid_map = buf; 2071 buf += len; 2072 } else { 2073 valid_map = NULL; 2074 } 2075 2076 /* Add a register to the dump, if it has a defined offset. 2077 * This automatically skips most undefined registers, but for 2078 * some it is also necessary to check a capability flag in 2079 * struct sh_eth_cpu_data. 2080 */ 2081 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 2082 #define add_reg_from(reg, read_expr) do { \ 2083 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2084 if (buf) { \ 2085 mark_reg_valid(reg); \ 2086 *buf++ = read_expr; \ 2087 } \ 2088 ++len; \ 2089 } \ 2090 } while (0) 2091 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2092 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2093 2094 add_reg(EDSR); 2095 add_reg(EDMR); 2096 add_reg(EDTRR); 2097 add_reg(EDRRR); 2098 add_reg(EESR); 2099 add_reg(EESIPR); 2100 add_reg(TDLAR); 2101 if (!cd->no_xdfar) 2102 add_reg(TDFAR); 2103 add_reg(TDFXR); 2104 add_reg(TDFFR); 2105 add_reg(RDLAR); 2106 if (!cd->no_xdfar) 2107 add_reg(RDFAR); 2108 add_reg(RDFXR); 2109 add_reg(RDFFR); 2110 add_reg(TRSCER); 2111 add_reg(RMFCR); 2112 add_reg(TFTR); 2113 add_reg(FDR); 2114 add_reg(RMCR); 2115 add_reg(TFUCR); 2116 add_reg(RFOCR); 2117 if (cd->rmiimode) 2118 add_reg(RMIIMODE); 2119 add_reg(FCFTR); 2120 if (cd->rpadir) 2121 add_reg(RPADIR); 2122 if (!cd->no_trimd) 2123 add_reg(TRIMD); 2124 add_reg(ECMR); 2125 add_reg(ECSR); 2126 add_reg(ECSIPR); 2127 add_reg(PIR); 2128 if (!cd->no_psr) 2129 add_reg(PSR); 2130 add_reg(RDMLR); 2131 add_reg(RFLR); 2132 add_reg(IPGR); 2133 if (cd->apr) 2134 add_reg(APR); 2135 if (cd->mpr) 2136 add_reg(MPR); 2137 add_reg(RFCR); 2138 add_reg(RFCF); 2139 if (cd->tpauser) 2140 add_reg(TPAUSER); 2141 add_reg(TPAUSECR); 2142 if (cd->gecmr) 2143 add_reg(GECMR); 2144 if (cd->bculr) 2145 add_reg(BCULR); 2146 add_reg(MAHR); 2147 add_reg(MALR); 2148 if (!cd->no_tx_cntrs) { 2149 add_reg(TROCR); 2150 add_reg(CDCR); 2151 add_reg(LCCR); 2152 add_reg(CNDCR); 2153 } 2154 add_reg(CEFCR); 2155 add_reg(FRECR); 2156 add_reg(TSFRCR); 2157 add_reg(TLFRCR); 2158 if (cd->cexcr) { 2159 add_reg(CERCR); 2160 add_reg(CEECR); 2161 } 2162 add_reg(MAFCR); 2163 if (cd->rtrate) 2164 add_reg(RTRATE); 2165 if (cd->csmr) 2166 add_reg(CSMR); 2167 if (cd->select_mii) 2168 add_reg(RMII_MII); 2169 if (cd->tsu) { 2170 add_tsu_reg(ARSTR); 2171 add_tsu_reg(TSU_CTRST); 2172 if (cd->dual_port) { 2173 add_tsu_reg(TSU_FWEN0); 2174 add_tsu_reg(TSU_FWEN1); 2175 add_tsu_reg(TSU_FCM); 2176 add_tsu_reg(TSU_BSYSL0); 2177 add_tsu_reg(TSU_BSYSL1); 2178 add_tsu_reg(TSU_PRISL0); 2179 add_tsu_reg(TSU_PRISL1); 2180 add_tsu_reg(TSU_FWSL0); 2181 add_tsu_reg(TSU_FWSL1); 2182 } 2183 add_tsu_reg(TSU_FWSLC); 2184 if (cd->dual_port) { 2185 add_tsu_reg(TSU_QTAGM0); 2186 add_tsu_reg(TSU_QTAGM1); 2187 add_tsu_reg(TSU_FWSR); 2188 add_tsu_reg(TSU_FWINMK); 2189 add_tsu_reg(TSU_ADQT0); 2190 add_tsu_reg(TSU_ADQT1); 2191 add_tsu_reg(TSU_VTAG0); 2192 add_tsu_reg(TSU_VTAG1); 2193 } 2194 add_tsu_reg(TSU_ADSBSY); 2195 add_tsu_reg(TSU_TEN); 2196 add_tsu_reg(TSU_POST1); 2197 add_tsu_reg(TSU_POST2); 2198 add_tsu_reg(TSU_POST3); 2199 add_tsu_reg(TSU_POST4); 2200 /* This is the start of a table, not just a single register. */ 2201 if (buf) { 2202 unsigned int i; 2203 2204 mark_reg_valid(TSU_ADRH0); 2205 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2206 *buf++ = ioread32(mdp->tsu_addr + 2207 mdp->reg_offset[TSU_ADRH0] + 2208 i * 4); 2209 } 2210 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2211 } 2212 2213 #undef mark_reg_valid 2214 #undef add_reg_from 2215 #undef add_reg 2216 #undef add_tsu_reg 2217 2218 return len * 4; 2219 } 2220 2221 static int sh_eth_get_regs_len(struct net_device *ndev) 2222 { 2223 return __sh_eth_get_regs(ndev, NULL); 2224 } 2225 2226 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2227 void *buf) 2228 { 2229 struct sh_eth_private *mdp = netdev_priv(ndev); 2230 2231 regs->version = SH_ETH_REG_DUMP_VERSION; 2232 2233 pm_runtime_get_sync(&mdp->pdev->dev); 2234 __sh_eth_get_regs(ndev, buf); 2235 pm_runtime_put_sync(&mdp->pdev->dev); 2236 } 2237 2238 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2239 { 2240 struct sh_eth_private *mdp = netdev_priv(ndev); 2241 return mdp->msg_enable; 2242 } 2243 2244 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2245 { 2246 struct sh_eth_private *mdp = netdev_priv(ndev); 2247 mdp->msg_enable = value; 2248 } 2249 2250 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2251 "rx_current", "tx_current", 2252 "rx_dirty", "tx_dirty", 2253 }; 2254 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2255 2256 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2257 { 2258 switch (sset) { 2259 case ETH_SS_STATS: 2260 return SH_ETH_STATS_LEN; 2261 default: 2262 return -EOPNOTSUPP; 2263 } 2264 } 2265 2266 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2267 struct ethtool_stats *stats, u64 *data) 2268 { 2269 struct sh_eth_private *mdp = netdev_priv(ndev); 2270 int i = 0; 2271 2272 /* device-specific stats */ 2273 data[i++] = mdp->cur_rx; 2274 data[i++] = mdp->cur_tx; 2275 data[i++] = mdp->dirty_rx; 2276 data[i++] = mdp->dirty_tx; 2277 } 2278 2279 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2280 { 2281 switch (stringset) { 2282 case ETH_SS_STATS: 2283 memcpy(data, *sh_eth_gstrings_stats, 2284 sizeof(sh_eth_gstrings_stats)); 2285 break; 2286 } 2287 } 2288 2289 static void sh_eth_get_ringparam(struct net_device *ndev, 2290 struct ethtool_ringparam *ring) 2291 { 2292 struct sh_eth_private *mdp = netdev_priv(ndev); 2293 2294 ring->rx_max_pending = RX_RING_MAX; 2295 ring->tx_max_pending = TX_RING_MAX; 2296 ring->rx_pending = mdp->num_rx_ring; 2297 ring->tx_pending = mdp->num_tx_ring; 2298 } 2299 2300 static int sh_eth_set_ringparam(struct net_device *ndev, 2301 struct ethtool_ringparam *ring) 2302 { 2303 struct sh_eth_private *mdp = netdev_priv(ndev); 2304 int ret; 2305 2306 if (ring->tx_pending > TX_RING_MAX || 2307 ring->rx_pending > RX_RING_MAX || 2308 ring->tx_pending < TX_RING_MIN || 2309 ring->rx_pending < RX_RING_MIN) 2310 return -EINVAL; 2311 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2312 return -EINVAL; 2313 2314 if (netif_running(ndev)) { 2315 netif_device_detach(ndev); 2316 netif_tx_disable(ndev); 2317 2318 /* Serialise with the interrupt handler and NAPI, then 2319 * disable interrupts. We have to clear the 2320 * irq_enabled flag first to ensure that interrupts 2321 * won't be re-enabled. 2322 */ 2323 mdp->irq_enabled = false; 2324 synchronize_irq(ndev->irq); 2325 napi_synchronize(&mdp->napi); 2326 sh_eth_write(ndev, 0x0000, EESIPR); 2327 2328 sh_eth_dev_exit(ndev); 2329 2330 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2331 sh_eth_ring_free(ndev); 2332 } 2333 2334 /* Set new parameters */ 2335 mdp->num_rx_ring = ring->rx_pending; 2336 mdp->num_tx_ring = ring->tx_pending; 2337 2338 if (netif_running(ndev)) { 2339 ret = sh_eth_ring_init(ndev); 2340 if (ret < 0) { 2341 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2342 __func__); 2343 return ret; 2344 } 2345 ret = sh_eth_dev_init(ndev); 2346 if (ret < 0) { 2347 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2348 __func__); 2349 return ret; 2350 } 2351 2352 netif_device_attach(ndev); 2353 } 2354 2355 return 0; 2356 } 2357 2358 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2359 { 2360 struct sh_eth_private *mdp = netdev_priv(ndev); 2361 2362 wol->supported = 0; 2363 wol->wolopts = 0; 2364 2365 if (mdp->cd->magic) { 2366 wol->supported = WAKE_MAGIC; 2367 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2368 } 2369 } 2370 2371 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2372 { 2373 struct sh_eth_private *mdp = netdev_priv(ndev); 2374 2375 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC) 2376 return -EOPNOTSUPP; 2377 2378 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2379 2380 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2381 2382 return 0; 2383 } 2384 2385 static const struct ethtool_ops sh_eth_ethtool_ops = { 2386 .get_regs_len = sh_eth_get_regs_len, 2387 .get_regs = sh_eth_get_regs, 2388 .nway_reset = phy_ethtool_nway_reset, 2389 .get_msglevel = sh_eth_get_msglevel, 2390 .set_msglevel = sh_eth_set_msglevel, 2391 .get_link = ethtool_op_get_link, 2392 .get_strings = sh_eth_get_strings, 2393 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2394 .get_sset_count = sh_eth_get_sset_count, 2395 .get_ringparam = sh_eth_get_ringparam, 2396 .set_ringparam = sh_eth_set_ringparam, 2397 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2398 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2399 .get_wol = sh_eth_get_wol, 2400 .set_wol = sh_eth_set_wol, 2401 }; 2402 2403 /* network device open function */ 2404 static int sh_eth_open(struct net_device *ndev) 2405 { 2406 struct sh_eth_private *mdp = netdev_priv(ndev); 2407 int ret; 2408 2409 pm_runtime_get_sync(&mdp->pdev->dev); 2410 2411 napi_enable(&mdp->napi); 2412 2413 ret = request_irq(ndev->irq, sh_eth_interrupt, 2414 mdp->cd->irq_flags, ndev->name, ndev); 2415 if (ret) { 2416 netdev_err(ndev, "Can not assign IRQ number\n"); 2417 goto out_napi_off; 2418 } 2419 2420 /* Descriptor set */ 2421 ret = sh_eth_ring_init(ndev); 2422 if (ret) 2423 goto out_free_irq; 2424 2425 /* device init */ 2426 ret = sh_eth_dev_init(ndev); 2427 if (ret) 2428 goto out_free_irq; 2429 2430 /* PHY control start*/ 2431 ret = sh_eth_phy_start(ndev); 2432 if (ret) 2433 goto out_free_irq; 2434 2435 netif_start_queue(ndev); 2436 2437 mdp->is_opened = 1; 2438 2439 return ret; 2440 2441 out_free_irq: 2442 free_irq(ndev->irq, ndev); 2443 out_napi_off: 2444 napi_disable(&mdp->napi); 2445 pm_runtime_put_sync(&mdp->pdev->dev); 2446 return ret; 2447 } 2448 2449 /* Timeout function */ 2450 static void sh_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue) 2451 { 2452 struct sh_eth_private *mdp = netdev_priv(ndev); 2453 struct sh_eth_rxdesc *rxdesc; 2454 int i; 2455 2456 netif_stop_queue(ndev); 2457 2458 netif_err(mdp, timer, ndev, 2459 "transmit timed out, status %8.8x, resetting...\n", 2460 sh_eth_read(ndev, EESR)); 2461 2462 /* tx_errors count up */ 2463 ndev->stats.tx_errors++; 2464 2465 /* Free all the skbuffs in the Rx queue. */ 2466 for (i = 0; i < mdp->num_rx_ring; i++) { 2467 rxdesc = &mdp->rx_ring[i]; 2468 rxdesc->status = cpu_to_le32(0); 2469 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2470 dev_kfree_skb(mdp->rx_skbuff[i]); 2471 mdp->rx_skbuff[i] = NULL; 2472 } 2473 for (i = 0; i < mdp->num_tx_ring; i++) { 2474 dev_kfree_skb(mdp->tx_skbuff[i]); 2475 mdp->tx_skbuff[i] = NULL; 2476 } 2477 2478 /* device init */ 2479 sh_eth_dev_init(ndev); 2480 2481 netif_start_queue(ndev); 2482 } 2483 2484 /* Packet transmit function */ 2485 static netdev_tx_t sh_eth_start_xmit(struct sk_buff *skb, 2486 struct net_device *ndev) 2487 { 2488 struct sh_eth_private *mdp = netdev_priv(ndev); 2489 struct sh_eth_txdesc *txdesc; 2490 dma_addr_t dma_addr; 2491 u32 entry; 2492 unsigned long flags; 2493 2494 spin_lock_irqsave(&mdp->lock, flags); 2495 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2496 if (!sh_eth_tx_free(ndev, true)) { 2497 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2498 netif_stop_queue(ndev); 2499 spin_unlock_irqrestore(&mdp->lock, flags); 2500 return NETDEV_TX_BUSY; 2501 } 2502 } 2503 spin_unlock_irqrestore(&mdp->lock, flags); 2504 2505 if (skb_put_padto(skb, ETH_ZLEN)) 2506 return NETDEV_TX_OK; 2507 2508 entry = mdp->cur_tx % mdp->num_tx_ring; 2509 mdp->tx_skbuff[entry] = skb; 2510 txdesc = &mdp->tx_ring[entry]; 2511 /* soft swap. */ 2512 if (!mdp->cd->hw_swap) 2513 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2514 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, 2515 DMA_TO_DEVICE); 2516 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 2517 kfree_skb(skb); 2518 return NETDEV_TX_OK; 2519 } 2520 txdesc->addr = cpu_to_le32(dma_addr); 2521 txdesc->len = cpu_to_le32(skb->len << 16); 2522 2523 dma_wmb(); /* TACT bit must be set after all the above writes */ 2524 if (entry >= mdp->num_tx_ring - 1) 2525 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2526 else 2527 txdesc->status |= cpu_to_le32(TD_TACT); 2528 2529 mdp->cur_tx++; 2530 2531 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns)) 2532 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 2533 2534 return NETDEV_TX_OK; 2535 } 2536 2537 /* The statistics registers have write-clear behaviour, which means we 2538 * will lose any increment between the read and write. We mitigate 2539 * this by only clearing when we read a non-zero value, so we will 2540 * never falsely report a total of zero. 2541 */ 2542 static void 2543 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2544 { 2545 u32 delta = sh_eth_read(ndev, reg); 2546 2547 if (delta) { 2548 *stat += delta; 2549 sh_eth_write(ndev, 0, reg); 2550 } 2551 } 2552 2553 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2554 { 2555 struct sh_eth_private *mdp = netdev_priv(ndev); 2556 2557 if (mdp->cd->no_tx_cntrs) 2558 return &ndev->stats; 2559 2560 if (!mdp->is_opened) 2561 return &ndev->stats; 2562 2563 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2564 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2565 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2566 2567 if (mdp->cd->cexcr) { 2568 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2569 CERCR); 2570 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2571 CEECR); 2572 } else { 2573 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2574 CNDCR); 2575 } 2576 2577 return &ndev->stats; 2578 } 2579 2580 /* device close function */ 2581 static int sh_eth_close(struct net_device *ndev) 2582 { 2583 struct sh_eth_private *mdp = netdev_priv(ndev); 2584 2585 netif_stop_queue(ndev); 2586 2587 /* Serialise with the interrupt handler and NAPI, then disable 2588 * interrupts. We have to clear the irq_enabled flag first to 2589 * ensure that interrupts won't be re-enabled. 2590 */ 2591 mdp->irq_enabled = false; 2592 synchronize_irq(ndev->irq); 2593 napi_disable(&mdp->napi); 2594 sh_eth_write(ndev, 0x0000, EESIPR); 2595 2596 sh_eth_dev_exit(ndev); 2597 2598 /* PHY Disconnect */ 2599 if (ndev->phydev) { 2600 phy_stop(ndev->phydev); 2601 phy_disconnect(ndev->phydev); 2602 } 2603 2604 free_irq(ndev->irq, ndev); 2605 2606 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2607 sh_eth_ring_free(ndev); 2608 2609 mdp->is_opened = 0; 2610 2611 pm_runtime_put(&mdp->pdev->dev); 2612 2613 return 0; 2614 } 2615 2616 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) 2617 { 2618 if (netif_running(ndev)) 2619 return -EBUSY; 2620 2621 ndev->mtu = new_mtu; 2622 netdev_update_features(ndev); 2623 2624 return 0; 2625 } 2626 2627 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2628 static u32 sh_eth_tsu_get_post_mask(int entry) 2629 { 2630 return 0x0f << (28 - ((entry % 8) * 4)); 2631 } 2632 2633 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2634 { 2635 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2636 } 2637 2638 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2639 int entry) 2640 { 2641 struct sh_eth_private *mdp = netdev_priv(ndev); 2642 int reg = TSU_POST1 + entry / 8; 2643 u32 tmp; 2644 2645 tmp = sh_eth_tsu_read(mdp, reg); 2646 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg); 2647 } 2648 2649 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2650 int entry) 2651 { 2652 struct sh_eth_private *mdp = netdev_priv(ndev); 2653 int reg = TSU_POST1 + entry / 8; 2654 u32 post_mask, ref_mask, tmp; 2655 2656 post_mask = sh_eth_tsu_get_post_mask(entry); 2657 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2658 2659 tmp = sh_eth_tsu_read(mdp, reg); 2660 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg); 2661 2662 /* If other port enables, the function returns "true" */ 2663 return tmp & ref_mask; 2664 } 2665 2666 static int sh_eth_tsu_busy(struct net_device *ndev) 2667 { 2668 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2669 struct sh_eth_private *mdp = netdev_priv(ndev); 2670 2671 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2672 udelay(10); 2673 timeout--; 2674 if (timeout <= 0) { 2675 netdev_err(ndev, "%s: timeout\n", __func__); 2676 return -ETIMEDOUT; 2677 } 2678 } 2679 2680 return 0; 2681 } 2682 2683 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset, 2684 const u8 *addr) 2685 { 2686 struct sh_eth_private *mdp = netdev_priv(ndev); 2687 u32 val; 2688 2689 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2690 iowrite32(val, mdp->tsu_addr + offset); 2691 if (sh_eth_tsu_busy(ndev) < 0) 2692 return -EBUSY; 2693 2694 val = addr[4] << 8 | addr[5]; 2695 iowrite32(val, mdp->tsu_addr + offset + 4); 2696 if (sh_eth_tsu_busy(ndev) < 0) 2697 return -EBUSY; 2698 2699 return 0; 2700 } 2701 2702 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr) 2703 { 2704 struct sh_eth_private *mdp = netdev_priv(ndev); 2705 u32 val; 2706 2707 val = ioread32(mdp->tsu_addr + offset); 2708 addr[0] = (val >> 24) & 0xff; 2709 addr[1] = (val >> 16) & 0xff; 2710 addr[2] = (val >> 8) & 0xff; 2711 addr[3] = val & 0xff; 2712 val = ioread32(mdp->tsu_addr + offset + 4); 2713 addr[4] = (val >> 8) & 0xff; 2714 addr[5] = val & 0xff; 2715 } 2716 2717 2718 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2719 { 2720 struct sh_eth_private *mdp = netdev_priv(ndev); 2721 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2722 int i; 2723 u8 c_addr[ETH_ALEN]; 2724 2725 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2726 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr); 2727 if (ether_addr_equal(addr, c_addr)) 2728 return i; 2729 } 2730 2731 return -ENOENT; 2732 } 2733 2734 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2735 { 2736 u8 blank[ETH_ALEN]; 2737 int entry; 2738 2739 memset(blank, 0, sizeof(blank)); 2740 entry = sh_eth_tsu_find_entry(ndev, blank); 2741 return (entry < 0) ? -ENOMEM : entry; 2742 } 2743 2744 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2745 int entry) 2746 { 2747 struct sh_eth_private *mdp = netdev_priv(ndev); 2748 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2749 int ret; 2750 u8 blank[ETH_ALEN]; 2751 2752 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2753 ~(1 << (31 - entry)), TSU_TEN); 2754 2755 memset(blank, 0, sizeof(blank)); 2756 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2757 if (ret < 0) 2758 return ret; 2759 return 0; 2760 } 2761 2762 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2763 { 2764 struct sh_eth_private *mdp = netdev_priv(ndev); 2765 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2766 int i, ret; 2767 2768 if (!mdp->cd->tsu) 2769 return 0; 2770 2771 i = sh_eth_tsu_find_entry(ndev, addr); 2772 if (i < 0) { 2773 /* No entry found, create one */ 2774 i = sh_eth_tsu_find_empty(ndev); 2775 if (i < 0) 2776 return -ENOMEM; 2777 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2778 if (ret < 0) 2779 return ret; 2780 2781 /* Enable the entry */ 2782 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2783 (1 << (31 - i)), TSU_TEN); 2784 } 2785 2786 /* Entry found or created, enable POST */ 2787 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2788 2789 return 0; 2790 } 2791 2792 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2793 { 2794 struct sh_eth_private *mdp = netdev_priv(ndev); 2795 int i, ret; 2796 2797 if (!mdp->cd->tsu) 2798 return 0; 2799 2800 i = sh_eth_tsu_find_entry(ndev, addr); 2801 if (i) { 2802 /* Entry found */ 2803 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2804 goto done; 2805 2806 /* Disable the entry if both ports was disabled */ 2807 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2808 if (ret < 0) 2809 return ret; 2810 } 2811 done: 2812 return 0; 2813 } 2814 2815 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2816 { 2817 struct sh_eth_private *mdp = netdev_priv(ndev); 2818 int i, ret; 2819 2820 if (!mdp->cd->tsu) 2821 return 0; 2822 2823 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2824 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2825 continue; 2826 2827 /* Disable the entry if both ports was disabled */ 2828 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2829 if (ret < 0) 2830 return ret; 2831 } 2832 2833 return 0; 2834 } 2835 2836 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2837 { 2838 struct sh_eth_private *mdp = netdev_priv(ndev); 2839 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2840 u8 addr[ETH_ALEN]; 2841 int i; 2842 2843 if (!mdp->cd->tsu) 2844 return; 2845 2846 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2847 sh_eth_tsu_read_entry(ndev, reg_offset, addr); 2848 if (is_multicast_ether_addr(addr)) 2849 sh_eth_tsu_del_entry(ndev, addr); 2850 } 2851 } 2852 2853 /* Update promiscuous flag and multicast filter */ 2854 static void sh_eth_set_rx_mode(struct net_device *ndev) 2855 { 2856 struct sh_eth_private *mdp = netdev_priv(ndev); 2857 u32 ecmr_bits; 2858 int mcast_all = 0; 2859 unsigned long flags; 2860 2861 spin_lock_irqsave(&mdp->lock, flags); 2862 /* Initial condition is MCT = 1, PRM = 0. 2863 * Depending on ndev->flags, set PRM or clear MCT 2864 */ 2865 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2866 if (mdp->cd->tsu) 2867 ecmr_bits |= ECMR_MCT; 2868 2869 if (!(ndev->flags & IFF_MULTICAST)) { 2870 sh_eth_tsu_purge_mcast(ndev); 2871 mcast_all = 1; 2872 } 2873 if (ndev->flags & IFF_ALLMULTI) { 2874 sh_eth_tsu_purge_mcast(ndev); 2875 ecmr_bits &= ~ECMR_MCT; 2876 mcast_all = 1; 2877 } 2878 2879 if (ndev->flags & IFF_PROMISC) { 2880 sh_eth_tsu_purge_all(ndev); 2881 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2882 } else if (mdp->cd->tsu) { 2883 struct netdev_hw_addr *ha; 2884 netdev_for_each_mc_addr(ha, ndev) { 2885 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2886 continue; 2887 2888 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2889 if (!mcast_all) { 2890 sh_eth_tsu_purge_mcast(ndev); 2891 ecmr_bits &= ~ECMR_MCT; 2892 mcast_all = 1; 2893 } 2894 } 2895 } 2896 } 2897 2898 /* update the ethernet mode */ 2899 sh_eth_write(ndev, ecmr_bits, ECMR); 2900 2901 spin_unlock_irqrestore(&mdp->lock, flags); 2902 } 2903 2904 static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable) 2905 { 2906 struct sh_eth_private *mdp = netdev_priv(ndev); 2907 unsigned long flags; 2908 2909 spin_lock_irqsave(&mdp->lock, flags); 2910 2911 /* Disable TX and RX */ 2912 sh_eth_rcv_snd_disable(ndev); 2913 2914 /* Modify RX Checksum setting */ 2915 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2916 2917 /* Enable TX and RX */ 2918 sh_eth_rcv_snd_enable(ndev); 2919 2920 spin_unlock_irqrestore(&mdp->lock, flags); 2921 } 2922 2923 static int sh_eth_set_features(struct net_device *ndev, 2924 netdev_features_t features) 2925 { 2926 netdev_features_t changed = ndev->features ^ features; 2927 struct sh_eth_private *mdp = netdev_priv(ndev); 2928 2929 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum) 2930 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2931 2932 ndev->features = features; 2933 2934 return 0; 2935 } 2936 2937 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2938 { 2939 if (!mdp->port) 2940 return TSU_VTAG0; 2941 else 2942 return TSU_VTAG1; 2943 } 2944 2945 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2946 __be16 proto, u16 vid) 2947 { 2948 struct sh_eth_private *mdp = netdev_priv(ndev); 2949 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2950 2951 if (unlikely(!mdp->cd->tsu)) 2952 return -EPERM; 2953 2954 /* No filtering if vid = 0 */ 2955 if (!vid) 2956 return 0; 2957 2958 mdp->vlan_num_ids++; 2959 2960 /* The controller has one VLAN tag HW filter. So, if the filter is 2961 * already enabled, the driver disables it and the filte 2962 */ 2963 if (mdp->vlan_num_ids > 1) { 2964 /* disable VLAN filter */ 2965 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2966 return 0; 2967 } 2968 2969 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2970 vtag_reg_index); 2971 2972 return 0; 2973 } 2974 2975 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2976 __be16 proto, u16 vid) 2977 { 2978 struct sh_eth_private *mdp = netdev_priv(ndev); 2979 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2980 2981 if (unlikely(!mdp->cd->tsu)) 2982 return -EPERM; 2983 2984 /* No filtering if vid = 0 */ 2985 if (!vid) 2986 return 0; 2987 2988 mdp->vlan_num_ids--; 2989 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2990 2991 return 0; 2992 } 2993 2994 /* SuperH's TSU register init function */ 2995 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2996 { 2997 if (!mdp->cd->dual_port) { 2998 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2999 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 3000 TSU_FWSLC); /* Enable POST registers */ 3001 return; 3002 } 3003 3004 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 3005 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 3006 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 3007 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 3008 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 3009 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 3010 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 3011 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 3012 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 3013 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 3014 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 3015 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 3016 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 3017 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 3018 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3019 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 3020 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 3021 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 3022 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 3023 } 3024 3025 /* MDIO bus release function */ 3026 static int sh_mdio_release(struct sh_eth_private *mdp) 3027 { 3028 /* unregister mdio bus */ 3029 mdiobus_unregister(mdp->mii_bus); 3030 3031 /* free bitbang info */ 3032 free_mdio_bitbang(mdp->mii_bus); 3033 3034 return 0; 3035 } 3036 3037 static int sh_mdiobb_read(struct mii_bus *bus, int phy, int reg) 3038 { 3039 int res; 3040 3041 pm_runtime_get_sync(bus->parent); 3042 res = mdiobb_read(bus, phy, reg); 3043 pm_runtime_put(bus->parent); 3044 3045 return res; 3046 } 3047 3048 static int sh_mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) 3049 { 3050 int res; 3051 3052 pm_runtime_get_sync(bus->parent); 3053 res = mdiobb_write(bus, phy, reg, val); 3054 pm_runtime_put(bus->parent); 3055 3056 return res; 3057 } 3058 3059 /* MDIO bus init function */ 3060 static int sh_mdio_init(struct sh_eth_private *mdp, 3061 struct sh_eth_plat_data *pd) 3062 { 3063 int ret; 3064 struct bb_info *bitbang; 3065 struct platform_device *pdev = mdp->pdev; 3066 struct device *dev = &mdp->pdev->dev; 3067 3068 /* create bit control struct for PHY */ 3069 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 3070 if (!bitbang) 3071 return -ENOMEM; 3072 3073 /* bitbang init */ 3074 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 3075 bitbang->set_gate = pd->set_mdio_gate; 3076 bitbang->ctrl.ops = &bb_ops; 3077 3078 /* MII controller setting */ 3079 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 3080 if (!mdp->mii_bus) 3081 return -ENOMEM; 3082 3083 /* Wrap accessors with Runtime PM-aware ops */ 3084 mdp->mii_bus->read = sh_mdiobb_read; 3085 mdp->mii_bus->write = sh_mdiobb_write; 3086 3087 /* Hook up MII support for ethtool */ 3088 mdp->mii_bus->name = "sh_mii"; 3089 mdp->mii_bus->parent = dev; 3090 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 3091 pdev->name, pdev->id); 3092 3093 /* register MDIO bus */ 3094 if (pd->phy_irq > 0) 3095 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 3096 3097 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 3098 if (ret) 3099 goto out_free_bus; 3100 3101 return 0; 3102 3103 out_free_bus: 3104 free_mdio_bitbang(mdp->mii_bus); 3105 return ret; 3106 } 3107 3108 static const u16 *sh_eth_get_register_offset(int register_type) 3109 { 3110 const u16 *reg_offset = NULL; 3111 3112 switch (register_type) { 3113 case SH_ETH_REG_GIGABIT: 3114 reg_offset = sh_eth_offset_gigabit; 3115 break; 3116 case SH_ETH_REG_FAST_RCAR: 3117 reg_offset = sh_eth_offset_fast_rcar; 3118 break; 3119 case SH_ETH_REG_FAST_SH4: 3120 reg_offset = sh_eth_offset_fast_sh4; 3121 break; 3122 case SH_ETH_REG_FAST_SH3_SH2: 3123 reg_offset = sh_eth_offset_fast_sh3_sh2; 3124 break; 3125 } 3126 3127 return reg_offset; 3128 } 3129 3130 static const struct net_device_ops sh_eth_netdev_ops = { 3131 .ndo_open = sh_eth_open, 3132 .ndo_stop = sh_eth_close, 3133 .ndo_start_xmit = sh_eth_start_xmit, 3134 .ndo_get_stats = sh_eth_get_stats, 3135 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3136 .ndo_tx_timeout = sh_eth_tx_timeout, 3137 .ndo_do_ioctl = phy_do_ioctl_running, 3138 .ndo_change_mtu = sh_eth_change_mtu, 3139 .ndo_validate_addr = eth_validate_addr, 3140 .ndo_set_mac_address = eth_mac_addr, 3141 .ndo_set_features = sh_eth_set_features, 3142 }; 3143 3144 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3145 .ndo_open = sh_eth_open, 3146 .ndo_stop = sh_eth_close, 3147 .ndo_start_xmit = sh_eth_start_xmit, 3148 .ndo_get_stats = sh_eth_get_stats, 3149 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3150 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3151 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3152 .ndo_tx_timeout = sh_eth_tx_timeout, 3153 .ndo_do_ioctl = phy_do_ioctl_running, 3154 .ndo_change_mtu = sh_eth_change_mtu, 3155 .ndo_validate_addr = eth_validate_addr, 3156 .ndo_set_mac_address = eth_mac_addr, 3157 .ndo_set_features = sh_eth_set_features, 3158 }; 3159 3160 #ifdef CONFIG_OF 3161 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3162 { 3163 struct device_node *np = dev->of_node; 3164 struct sh_eth_plat_data *pdata; 3165 phy_interface_t interface; 3166 const char *mac_addr; 3167 int ret; 3168 3169 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3170 if (!pdata) 3171 return NULL; 3172 3173 ret = of_get_phy_mode(np, &interface); 3174 if (ret) 3175 return NULL; 3176 pdata->phy_interface = interface; 3177 3178 mac_addr = of_get_mac_address(np); 3179 if (!IS_ERR(mac_addr)) 3180 ether_addr_copy(pdata->mac_addr, mac_addr); 3181 3182 pdata->no_ether_link = 3183 of_property_read_bool(np, "renesas,no-ether-link"); 3184 pdata->ether_link_active_low = 3185 of_property_read_bool(np, "renesas,ether-link-active-low"); 3186 3187 return pdata; 3188 } 3189 3190 static const struct of_device_id sh_eth_match_table[] = { 3191 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3192 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data }, 3193 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data }, 3194 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data }, 3195 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data }, 3196 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data }, 3197 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data }, 3198 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data }, 3199 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data }, 3200 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data }, 3201 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3202 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data }, 3203 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data }, 3204 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data }, 3205 { } 3206 }; 3207 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3208 #else 3209 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3210 { 3211 return NULL; 3212 } 3213 #endif 3214 3215 static int sh_eth_drv_probe(struct platform_device *pdev) 3216 { 3217 struct resource *res; 3218 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3219 const struct platform_device_id *id = platform_get_device_id(pdev); 3220 struct sh_eth_private *mdp; 3221 struct net_device *ndev; 3222 int ret; 3223 3224 /* get base addr */ 3225 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3226 3227 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3228 if (!ndev) 3229 return -ENOMEM; 3230 3231 pm_runtime_enable(&pdev->dev); 3232 pm_runtime_get_sync(&pdev->dev); 3233 3234 ret = platform_get_irq(pdev, 0); 3235 if (ret < 0) 3236 goto out_release; 3237 ndev->irq = ret; 3238 3239 SET_NETDEV_DEV(ndev, &pdev->dev); 3240 3241 mdp = netdev_priv(ndev); 3242 mdp->num_tx_ring = TX_RING_SIZE; 3243 mdp->num_rx_ring = RX_RING_SIZE; 3244 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3245 if (IS_ERR(mdp->addr)) { 3246 ret = PTR_ERR(mdp->addr); 3247 goto out_release; 3248 } 3249 3250 ndev->base_addr = res->start; 3251 3252 spin_lock_init(&mdp->lock); 3253 mdp->pdev = pdev; 3254 3255 if (pdev->dev.of_node) 3256 pd = sh_eth_parse_dt(&pdev->dev); 3257 if (!pd) { 3258 dev_err(&pdev->dev, "no platform data\n"); 3259 ret = -EINVAL; 3260 goto out_release; 3261 } 3262 3263 /* get PHY ID */ 3264 mdp->phy_id = pd->phy; 3265 mdp->phy_interface = pd->phy_interface; 3266 mdp->no_ether_link = pd->no_ether_link; 3267 mdp->ether_link_active_low = pd->ether_link_active_low; 3268 3269 /* set cpu data */ 3270 if (id) 3271 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3272 else 3273 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3274 3275 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3276 if (!mdp->reg_offset) { 3277 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3278 mdp->cd->register_type); 3279 ret = -EINVAL; 3280 goto out_release; 3281 } 3282 sh_eth_set_default_cpu_data(mdp->cd); 3283 3284 /* User's manual states max MTU should be 2048 but due to the 3285 * alignment calculations in sh_eth_ring_init() the practical 3286 * MTU is a bit less. Maybe this can be optimized some more. 3287 */ 3288 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3289 ndev->min_mtu = ETH_MIN_MTU; 3290 3291 if (mdp->cd->rx_csum) { 3292 ndev->features = NETIF_F_RXCSUM; 3293 ndev->hw_features = NETIF_F_RXCSUM; 3294 } 3295 3296 /* set function */ 3297 if (mdp->cd->tsu) 3298 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3299 else 3300 ndev->netdev_ops = &sh_eth_netdev_ops; 3301 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3302 ndev->watchdog_timeo = TX_TIMEOUT; 3303 3304 /* debug message level */ 3305 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3306 3307 /* read and set MAC address */ 3308 read_mac_address(ndev, pd->mac_addr); 3309 if (!is_valid_ether_addr(ndev->dev_addr)) { 3310 dev_warn(&pdev->dev, 3311 "no valid MAC address supplied, using a random one.\n"); 3312 eth_hw_addr_random(ndev); 3313 } 3314 3315 if (mdp->cd->tsu) { 3316 int port = pdev->id < 0 ? 0 : pdev->id % 2; 3317 struct resource *rtsu; 3318 3319 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3320 if (!rtsu) { 3321 dev_err(&pdev->dev, "no TSU resource\n"); 3322 ret = -ENODEV; 3323 goto out_release; 3324 } 3325 /* We can only request the TSU region for the first port 3326 * of the two sharing this TSU for the probe to succeed... 3327 */ 3328 if (port == 0 && 3329 !devm_request_mem_region(&pdev->dev, rtsu->start, 3330 resource_size(rtsu), 3331 dev_name(&pdev->dev))) { 3332 dev_err(&pdev->dev, "can't request TSU resource.\n"); 3333 ret = -EBUSY; 3334 goto out_release; 3335 } 3336 /* ioremap the TSU registers */ 3337 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, 3338 resource_size(rtsu)); 3339 if (!mdp->tsu_addr) { 3340 dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); 3341 ret = -ENOMEM; 3342 goto out_release; 3343 } 3344 mdp->port = port; 3345 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 3346 3347 /* Need to init only the first port of the two sharing a TSU */ 3348 if (port == 0) { 3349 if (mdp->cd->chip_reset) 3350 mdp->cd->chip_reset(ndev); 3351 3352 /* TSU init (Init only)*/ 3353 sh_eth_tsu_init(mdp); 3354 } 3355 } 3356 3357 if (mdp->cd->rmiimode) 3358 sh_eth_write(ndev, 0x1, RMIIMODE); 3359 3360 /* MDIO bus init */ 3361 ret = sh_mdio_init(mdp, pd); 3362 if (ret) { 3363 if (ret != -EPROBE_DEFER) 3364 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret); 3365 goto out_release; 3366 } 3367 3368 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3369 3370 /* network device register */ 3371 ret = register_netdev(ndev); 3372 if (ret) 3373 goto out_napi_del; 3374 3375 if (mdp->cd->magic) 3376 device_set_wakeup_capable(&pdev->dev, 1); 3377 3378 /* print device information */ 3379 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3380 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3381 3382 pm_runtime_put(&pdev->dev); 3383 platform_set_drvdata(pdev, ndev); 3384 3385 return ret; 3386 3387 out_napi_del: 3388 netif_napi_del(&mdp->napi); 3389 sh_mdio_release(mdp); 3390 3391 out_release: 3392 /* net_dev free */ 3393 free_netdev(ndev); 3394 3395 pm_runtime_put(&pdev->dev); 3396 pm_runtime_disable(&pdev->dev); 3397 return ret; 3398 } 3399 3400 static int sh_eth_drv_remove(struct platform_device *pdev) 3401 { 3402 struct net_device *ndev = platform_get_drvdata(pdev); 3403 struct sh_eth_private *mdp = netdev_priv(ndev); 3404 3405 unregister_netdev(ndev); 3406 netif_napi_del(&mdp->napi); 3407 sh_mdio_release(mdp); 3408 pm_runtime_disable(&pdev->dev); 3409 free_netdev(ndev); 3410 3411 return 0; 3412 } 3413 3414 #ifdef CONFIG_PM 3415 #ifdef CONFIG_PM_SLEEP 3416 static int sh_eth_wol_setup(struct net_device *ndev) 3417 { 3418 struct sh_eth_private *mdp = netdev_priv(ndev); 3419 3420 /* Only allow ECI interrupts */ 3421 synchronize_irq(ndev->irq); 3422 napi_disable(&mdp->napi); 3423 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3424 3425 /* Enable MagicPacket */ 3426 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3427 3428 return enable_irq_wake(ndev->irq); 3429 } 3430 3431 static int sh_eth_wol_restore(struct net_device *ndev) 3432 { 3433 struct sh_eth_private *mdp = netdev_priv(ndev); 3434 int ret; 3435 3436 napi_enable(&mdp->napi); 3437 3438 /* Disable MagicPacket */ 3439 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3440 3441 /* The device needs to be reset to restore MagicPacket logic 3442 * for next wakeup. If we close and open the device it will 3443 * both be reset and all registers restored. This is what 3444 * happens during suspend and resume without WoL enabled. 3445 */ 3446 ret = sh_eth_close(ndev); 3447 if (ret < 0) 3448 return ret; 3449 ret = sh_eth_open(ndev); 3450 if (ret < 0) 3451 return ret; 3452 3453 return disable_irq_wake(ndev->irq); 3454 } 3455 3456 static int sh_eth_suspend(struct device *dev) 3457 { 3458 struct net_device *ndev = dev_get_drvdata(dev); 3459 struct sh_eth_private *mdp = netdev_priv(ndev); 3460 int ret = 0; 3461 3462 if (!netif_running(ndev)) 3463 return 0; 3464 3465 netif_device_detach(ndev); 3466 3467 if (mdp->wol_enabled) 3468 ret = sh_eth_wol_setup(ndev); 3469 else 3470 ret = sh_eth_close(ndev); 3471 3472 return ret; 3473 } 3474 3475 static int sh_eth_resume(struct device *dev) 3476 { 3477 struct net_device *ndev = dev_get_drvdata(dev); 3478 struct sh_eth_private *mdp = netdev_priv(ndev); 3479 int ret = 0; 3480 3481 if (!netif_running(ndev)) 3482 return 0; 3483 3484 if (mdp->wol_enabled) 3485 ret = sh_eth_wol_restore(ndev); 3486 else 3487 ret = sh_eth_open(ndev); 3488 3489 if (ret < 0) 3490 return ret; 3491 3492 netif_device_attach(ndev); 3493 3494 return ret; 3495 } 3496 #endif 3497 3498 static int sh_eth_runtime_nop(struct device *dev) 3499 { 3500 /* Runtime PM callback shared between ->runtime_suspend() 3501 * and ->runtime_resume(). Simply returns success. 3502 * 3503 * This driver re-initializes all registers after 3504 * pm_runtime_get_sync() anyway so there is no need 3505 * to save and restore registers here. 3506 */ 3507 return 0; 3508 } 3509 3510 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3511 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3512 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3513 }; 3514 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3515 #else 3516 #define SH_ETH_PM_OPS NULL 3517 #endif 3518 3519 static const struct platform_device_id sh_eth_id_table[] = { 3520 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3521 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3522 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3523 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3524 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3525 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3526 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3527 { } 3528 }; 3529 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3530 3531 static struct platform_driver sh_eth_driver = { 3532 .probe = sh_eth_drv_probe, 3533 .remove = sh_eth_drv_remove, 3534 .id_table = sh_eth_id_table, 3535 .driver = { 3536 .name = CARDNAME, 3537 .pm = SH_ETH_PM_OPS, 3538 .of_match_table = of_match_ptr(sh_eth_match_table), 3539 }, 3540 }; 3541 3542 module_platform_driver(sh_eth_driver); 3543 3544 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3545 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3546 MODULE_LICENSE("GPL v2"); 3547