1 // SPDX-License-Identifier: GPL-2.0 2 /* SuperH Ethernet device driver 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 6 * Copyright (C) 2008-2014 Renesas Solutions Corp. 7 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 8 * Copyright (C) 2014 Codethink Limited 9 */ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/spinlock.h> 14 #include <linux/interrupt.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/etherdevice.h> 17 #include <linux/delay.h> 18 #include <linux/platform_device.h> 19 #include <linux/mdio-bitbang.h> 20 #include <linux/netdevice.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_net.h> 25 #include <linux/phy.h> 26 #include <linux/cache.h> 27 #include <linux/io.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/ethtool.h> 31 #include <linux/if_vlan.h> 32 #include <linux/sh_eth.h> 33 #include <linux/of_mdio.h> 34 35 #include "sh_eth.h" 36 37 #define SH_ETH_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR| \ 41 NETIF_MSG_TX_ERR) 42 43 #define SH_ETH_OFFSET_INVALID ((u16)~0) 44 45 #define SH_ETH_OFFSET_DEFAULTS \ 46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 47 48 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 49 SH_ETH_OFFSET_DEFAULTS, 50 51 [EDSR] = 0x0000, 52 [EDMR] = 0x0400, 53 [EDTRR] = 0x0408, 54 [EDRRR] = 0x0410, 55 [EESR] = 0x0428, 56 [EESIPR] = 0x0430, 57 [TDLAR] = 0x0010, 58 [TDFAR] = 0x0014, 59 [TDFXR] = 0x0018, 60 [TDFFR] = 0x001c, 61 [RDLAR] = 0x0030, 62 [RDFAR] = 0x0034, 63 [RDFXR] = 0x0038, 64 [RDFFR] = 0x003c, 65 [TRSCER] = 0x0438, 66 [RMFCR] = 0x0440, 67 [TFTR] = 0x0448, 68 [FDR] = 0x0450, 69 [RMCR] = 0x0458, 70 [RPADIR] = 0x0460, 71 [FCFTR] = 0x0468, 72 [CSMR] = 0x04E4, 73 74 [ECMR] = 0x0500, 75 [ECSR] = 0x0510, 76 [ECSIPR] = 0x0518, 77 [PIR] = 0x0520, 78 [PSR] = 0x0528, 79 [PIPR] = 0x052c, 80 [RFLR] = 0x0508, 81 [APR] = 0x0554, 82 [MPR] = 0x0558, 83 [PFTCR] = 0x055c, 84 [PFRCR] = 0x0560, 85 [TPAUSER] = 0x0564, 86 [GECMR] = 0x05b0, 87 [BCULR] = 0x05b4, 88 [MAHR] = 0x05c0, 89 [MALR] = 0x05c8, 90 [TROCR] = 0x0700, 91 [CDCR] = 0x0708, 92 [LCCR] = 0x0710, 93 [CEFCR] = 0x0740, 94 [FRECR] = 0x0748, 95 [TSFRCR] = 0x0750, 96 [TLFRCR] = 0x0758, 97 [RFCR] = 0x0760, 98 [CERCR] = 0x0768, 99 [CEECR] = 0x0770, 100 [MAFCR] = 0x0778, 101 [RMII_MII] = 0x0790, 102 103 [ARSTR] = 0x0000, 104 [TSU_CTRST] = 0x0004, 105 [TSU_FWEN0] = 0x0010, 106 [TSU_FWEN1] = 0x0014, 107 [TSU_FCM] = 0x0018, 108 [TSU_BSYSL0] = 0x0020, 109 [TSU_BSYSL1] = 0x0024, 110 [TSU_PRISL0] = 0x0028, 111 [TSU_PRISL1] = 0x002c, 112 [TSU_FWSL0] = 0x0030, 113 [TSU_FWSL1] = 0x0034, 114 [TSU_FWSLC] = 0x0038, 115 [TSU_QTAGM0] = 0x0040, 116 [TSU_QTAGM1] = 0x0044, 117 [TSU_FWSR] = 0x0050, 118 [TSU_FWINMK] = 0x0054, 119 [TSU_ADQT0] = 0x0048, 120 [TSU_ADQT1] = 0x004c, 121 [TSU_VTAG0] = 0x0058, 122 [TSU_VTAG1] = 0x005c, 123 [TSU_ADSBSY] = 0x0060, 124 [TSU_TEN] = 0x0064, 125 [TSU_POST1] = 0x0070, 126 [TSU_POST2] = 0x0074, 127 [TSU_POST3] = 0x0078, 128 [TSU_POST4] = 0x007c, 129 [TSU_ADRH0] = 0x0100, 130 131 [TXNLCR0] = 0x0080, 132 [TXALCR0] = 0x0084, 133 [RXNLCR0] = 0x0088, 134 [RXALCR0] = 0x008c, 135 [FWNLCR0] = 0x0090, 136 [FWALCR0] = 0x0094, 137 [TXNLCR1] = 0x00a0, 138 [TXALCR1] = 0x00a4, 139 [RXNLCR1] = 0x00a8, 140 [RXALCR1] = 0x00ac, 141 [FWNLCR1] = 0x00b0, 142 [FWALCR1] = 0x00b4, 143 }; 144 145 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 146 SH_ETH_OFFSET_DEFAULTS, 147 148 [EDSR] = 0x0000, 149 [EDMR] = 0x0400, 150 [EDTRR] = 0x0408, 151 [EDRRR] = 0x0410, 152 [EESR] = 0x0428, 153 [EESIPR] = 0x0430, 154 [TDLAR] = 0x0010, 155 [TDFAR] = 0x0014, 156 [TDFXR] = 0x0018, 157 [TDFFR] = 0x001c, 158 [RDLAR] = 0x0030, 159 [RDFAR] = 0x0034, 160 [RDFXR] = 0x0038, 161 [RDFFR] = 0x003c, 162 [TRSCER] = 0x0438, 163 [RMFCR] = 0x0440, 164 [TFTR] = 0x0448, 165 [FDR] = 0x0450, 166 [RMCR] = 0x0458, 167 [RPADIR] = 0x0460, 168 [FCFTR] = 0x0468, 169 [CSMR] = 0x04E4, 170 171 [ECMR] = 0x0500, 172 [RFLR] = 0x0508, 173 [ECSR] = 0x0510, 174 [ECSIPR] = 0x0518, 175 [PIR] = 0x0520, 176 [APR] = 0x0554, 177 [MPR] = 0x0558, 178 [PFTCR] = 0x055c, 179 [PFRCR] = 0x0560, 180 [TPAUSER] = 0x0564, 181 [MAHR] = 0x05c0, 182 [MALR] = 0x05c8, 183 [CEFCR] = 0x0740, 184 [FRECR] = 0x0748, 185 [TSFRCR] = 0x0750, 186 [TLFRCR] = 0x0758, 187 [RFCR] = 0x0760, 188 [MAFCR] = 0x0778, 189 190 [ARSTR] = 0x0000, 191 [TSU_CTRST] = 0x0004, 192 [TSU_FWSLC] = 0x0038, 193 [TSU_VTAG0] = 0x0058, 194 [TSU_ADSBSY] = 0x0060, 195 [TSU_TEN] = 0x0064, 196 [TSU_POST1] = 0x0070, 197 [TSU_POST2] = 0x0074, 198 [TSU_POST3] = 0x0078, 199 [TSU_POST4] = 0x007c, 200 [TSU_ADRH0] = 0x0100, 201 202 [TXNLCR0] = 0x0080, 203 [TXALCR0] = 0x0084, 204 [RXNLCR0] = 0x0088, 205 [RXALCR0] = 0x008C, 206 }; 207 208 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 209 SH_ETH_OFFSET_DEFAULTS, 210 211 [ECMR] = 0x0300, 212 [RFLR] = 0x0308, 213 [ECSR] = 0x0310, 214 [ECSIPR] = 0x0318, 215 [PIR] = 0x0320, 216 [PSR] = 0x0328, 217 [RDMLR] = 0x0340, 218 [IPGR] = 0x0350, 219 [APR] = 0x0354, 220 [MPR] = 0x0358, 221 [RFCF] = 0x0360, 222 [TPAUSER] = 0x0364, 223 [TPAUSECR] = 0x0368, 224 [MAHR] = 0x03c0, 225 [MALR] = 0x03c8, 226 [TROCR] = 0x03d0, 227 [CDCR] = 0x03d4, 228 [LCCR] = 0x03d8, 229 [CNDCR] = 0x03dc, 230 [CEFCR] = 0x03e4, 231 [FRECR] = 0x03e8, 232 [TSFRCR] = 0x03ec, 233 [TLFRCR] = 0x03f0, 234 [RFCR] = 0x03f4, 235 [MAFCR] = 0x03f8, 236 237 [EDMR] = 0x0200, 238 [EDTRR] = 0x0208, 239 [EDRRR] = 0x0210, 240 [TDLAR] = 0x0218, 241 [RDLAR] = 0x0220, 242 [EESR] = 0x0228, 243 [EESIPR] = 0x0230, 244 [TRSCER] = 0x0238, 245 [RMFCR] = 0x0240, 246 [TFTR] = 0x0248, 247 [FDR] = 0x0250, 248 [RMCR] = 0x0258, 249 [TFUCR] = 0x0264, 250 [RFOCR] = 0x0268, 251 [RMIIMODE] = 0x026c, 252 [FCFTR] = 0x0270, 253 [TRIMD] = 0x027c, 254 }; 255 256 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 257 SH_ETH_OFFSET_DEFAULTS, 258 259 [ECMR] = 0x0100, 260 [RFLR] = 0x0108, 261 [ECSR] = 0x0110, 262 [ECSIPR] = 0x0118, 263 [PIR] = 0x0120, 264 [PSR] = 0x0128, 265 [RDMLR] = 0x0140, 266 [IPGR] = 0x0150, 267 [APR] = 0x0154, 268 [MPR] = 0x0158, 269 [TPAUSER] = 0x0164, 270 [RFCF] = 0x0160, 271 [TPAUSECR] = 0x0168, 272 [BCFRR] = 0x016c, 273 [MAHR] = 0x01c0, 274 [MALR] = 0x01c8, 275 [TROCR] = 0x01d0, 276 [CDCR] = 0x01d4, 277 [LCCR] = 0x01d8, 278 [CNDCR] = 0x01dc, 279 [CEFCR] = 0x01e4, 280 [FRECR] = 0x01e8, 281 [TSFRCR] = 0x01ec, 282 [TLFRCR] = 0x01f0, 283 [RFCR] = 0x01f4, 284 [MAFCR] = 0x01f8, 285 [RTRATE] = 0x01fc, 286 287 [EDMR] = 0x0000, 288 [EDTRR] = 0x0008, 289 [EDRRR] = 0x0010, 290 [TDLAR] = 0x0018, 291 [RDLAR] = 0x0020, 292 [EESR] = 0x0028, 293 [EESIPR] = 0x0030, 294 [TRSCER] = 0x0038, 295 [RMFCR] = 0x0040, 296 [TFTR] = 0x0048, 297 [FDR] = 0x0050, 298 [RMCR] = 0x0058, 299 [TFUCR] = 0x0064, 300 [RFOCR] = 0x0068, 301 [FCFTR] = 0x0070, 302 [RPADIR] = 0x0078, 303 [TRIMD] = 0x007c, 304 [RBWAR] = 0x00c8, 305 [RDFAR] = 0x00cc, 306 [TBRAR] = 0x00d4, 307 [TDFAR] = 0x00d8, 308 }; 309 310 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 311 SH_ETH_OFFSET_DEFAULTS, 312 313 [EDMR] = 0x0000, 314 [EDTRR] = 0x0004, 315 [EDRRR] = 0x0008, 316 [TDLAR] = 0x000c, 317 [RDLAR] = 0x0010, 318 [EESR] = 0x0014, 319 [EESIPR] = 0x0018, 320 [TRSCER] = 0x001c, 321 [RMFCR] = 0x0020, 322 [TFTR] = 0x0024, 323 [FDR] = 0x0028, 324 [RMCR] = 0x002c, 325 [EDOCR] = 0x0030, 326 [FCFTR] = 0x0034, 327 [RPADIR] = 0x0038, 328 [TRIMD] = 0x003c, 329 [RBWAR] = 0x0040, 330 [RDFAR] = 0x0044, 331 [TBRAR] = 0x004c, 332 [TDFAR] = 0x0050, 333 334 [ECMR] = 0x0160, 335 [ECSR] = 0x0164, 336 [ECSIPR] = 0x0168, 337 [PIR] = 0x016c, 338 [MAHR] = 0x0170, 339 [MALR] = 0x0174, 340 [RFLR] = 0x0178, 341 [PSR] = 0x017c, 342 [TROCR] = 0x0180, 343 [CDCR] = 0x0184, 344 [LCCR] = 0x0188, 345 [CNDCR] = 0x018c, 346 [CEFCR] = 0x0194, 347 [FRECR] = 0x0198, 348 [TSFRCR] = 0x019c, 349 [TLFRCR] = 0x01a0, 350 [RFCR] = 0x01a4, 351 [MAFCR] = 0x01a8, 352 [IPGR] = 0x01b4, 353 [APR] = 0x01b8, 354 [MPR] = 0x01bc, 355 [TPAUSER] = 0x01c4, 356 [BCFR] = 0x01cc, 357 358 [ARSTR] = 0x0000, 359 [TSU_CTRST] = 0x0004, 360 [TSU_FWEN0] = 0x0010, 361 [TSU_FWEN1] = 0x0014, 362 [TSU_FCM] = 0x0018, 363 [TSU_BSYSL0] = 0x0020, 364 [TSU_BSYSL1] = 0x0024, 365 [TSU_PRISL0] = 0x0028, 366 [TSU_PRISL1] = 0x002c, 367 [TSU_FWSL0] = 0x0030, 368 [TSU_FWSL1] = 0x0034, 369 [TSU_FWSLC] = 0x0038, 370 [TSU_QTAGM0] = 0x0040, 371 [TSU_QTAGM1] = 0x0044, 372 [TSU_ADQT0] = 0x0048, 373 [TSU_ADQT1] = 0x004c, 374 [TSU_FWSR] = 0x0050, 375 [TSU_FWINMK] = 0x0054, 376 [TSU_ADSBSY] = 0x0060, 377 [TSU_TEN] = 0x0064, 378 [TSU_POST1] = 0x0070, 379 [TSU_POST2] = 0x0074, 380 [TSU_POST3] = 0x0078, 381 [TSU_POST4] = 0x007c, 382 383 [TXNLCR0] = 0x0080, 384 [TXALCR0] = 0x0084, 385 [RXNLCR0] = 0x0088, 386 [RXALCR0] = 0x008c, 387 [FWNLCR0] = 0x0090, 388 [FWALCR0] = 0x0094, 389 [TXNLCR1] = 0x00a0, 390 [TXALCR1] = 0x00a4, 391 [RXNLCR1] = 0x00a8, 392 [RXALCR1] = 0x00ac, 393 [FWNLCR1] = 0x00b0, 394 [FWALCR1] = 0x00b4, 395 396 [TSU_ADRH0] = 0x0100, 397 }; 398 399 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 400 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 401 402 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 403 { 404 struct sh_eth_private *mdp = netdev_priv(ndev); 405 u16 offset = mdp->reg_offset[enum_index]; 406 407 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 408 return; 409 410 iowrite32(data, mdp->addr + offset); 411 } 412 413 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 414 { 415 struct sh_eth_private *mdp = netdev_priv(ndev); 416 u16 offset = mdp->reg_offset[enum_index]; 417 418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 419 return ~0U; 420 421 return ioread32(mdp->addr + offset); 422 } 423 424 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 425 u32 set) 426 { 427 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 428 enum_index); 429 } 430 431 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index) 432 { 433 return mdp->reg_offset[enum_index]; 434 } 435 436 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data, 437 int enum_index) 438 { 439 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 440 441 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 442 return; 443 444 iowrite32(data, mdp->tsu_addr + offset); 445 } 446 447 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index) 448 { 449 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 450 451 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 452 return ~0U; 453 454 return ioread32(mdp->tsu_addr + offset); 455 } 456 457 static void sh_eth_soft_swap(char *src, int len) 458 { 459 #ifdef __LITTLE_ENDIAN 460 u32 *p = (u32 *)src; 461 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32)); 462 463 for (; p < maxp; p++) 464 *p = swab32(*p); 465 #endif 466 } 467 468 static void sh_eth_select_mii(struct net_device *ndev) 469 { 470 struct sh_eth_private *mdp = netdev_priv(ndev); 471 u32 value; 472 473 switch (mdp->phy_interface) { 474 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID: 475 value = 0x3; 476 break; 477 case PHY_INTERFACE_MODE_GMII: 478 value = 0x2; 479 break; 480 case PHY_INTERFACE_MODE_MII: 481 value = 0x1; 482 break; 483 case PHY_INTERFACE_MODE_RMII: 484 value = 0x0; 485 break; 486 default: 487 netdev_warn(ndev, 488 "PHY interface mode was not setup. Set to MII.\n"); 489 value = 0x1; 490 break; 491 } 492 493 sh_eth_write(ndev, value, RMII_MII); 494 } 495 496 static void sh_eth_set_duplex(struct net_device *ndev) 497 { 498 struct sh_eth_private *mdp = netdev_priv(ndev); 499 500 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 501 } 502 503 static void sh_eth_chip_reset(struct net_device *ndev) 504 { 505 struct sh_eth_private *mdp = netdev_priv(ndev); 506 507 /* reset device */ 508 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 509 mdelay(1); 510 } 511 512 static int sh_eth_soft_reset(struct net_device *ndev) 513 { 514 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 515 mdelay(3); 516 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 517 518 return 0; 519 } 520 521 static int sh_eth_check_soft_reset(struct net_device *ndev) 522 { 523 int cnt; 524 525 for (cnt = 100; cnt > 0; cnt--) { 526 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 527 return 0; 528 mdelay(1); 529 } 530 531 netdev_err(ndev, "Device reset failed\n"); 532 return -ETIMEDOUT; 533 } 534 535 static int sh_eth_soft_reset_gether(struct net_device *ndev) 536 { 537 struct sh_eth_private *mdp = netdev_priv(ndev); 538 int ret; 539 540 sh_eth_write(ndev, EDSR_ENALL, EDSR); 541 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 542 543 ret = sh_eth_check_soft_reset(ndev); 544 if (ret) 545 return ret; 546 547 /* Table Init */ 548 sh_eth_write(ndev, 0, TDLAR); 549 sh_eth_write(ndev, 0, TDFAR); 550 sh_eth_write(ndev, 0, TDFXR); 551 sh_eth_write(ndev, 0, TDFFR); 552 sh_eth_write(ndev, 0, RDLAR); 553 sh_eth_write(ndev, 0, RDFAR); 554 sh_eth_write(ndev, 0, RDFXR); 555 sh_eth_write(ndev, 0, RDFFR); 556 557 /* Reset HW CRC register */ 558 if (mdp->cd->hw_checksum) 559 sh_eth_write(ndev, 0, CSMR); 560 561 /* Select MII mode */ 562 if (mdp->cd->select_mii) 563 sh_eth_select_mii(ndev); 564 565 return ret; 566 } 567 568 static void sh_eth_set_rate_gether(struct net_device *ndev) 569 { 570 struct sh_eth_private *mdp = netdev_priv(ndev); 571 572 switch (mdp->speed) { 573 case 10: /* 10BASE */ 574 sh_eth_write(ndev, GECMR_10, GECMR); 575 break; 576 case 100:/* 100BASE */ 577 sh_eth_write(ndev, GECMR_100, GECMR); 578 break; 579 case 1000: /* 1000BASE */ 580 sh_eth_write(ndev, GECMR_1000, GECMR); 581 break; 582 } 583 } 584 585 #ifdef CONFIG_OF 586 /* R7S72100 */ 587 static struct sh_eth_cpu_data r7s72100_data = { 588 .soft_reset = sh_eth_soft_reset_gether, 589 590 .chip_reset = sh_eth_chip_reset, 591 .set_duplex = sh_eth_set_duplex, 592 593 .register_type = SH_ETH_REG_FAST_RZ, 594 595 .edtrr_trns = EDTRR_TRNS_GETHER, 596 .ecsr_value = ECSR_ICD, 597 .ecsipr_value = ECSIPR_ICDIP, 598 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 599 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 600 EESIPR_ECIIP | 601 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 602 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 603 EESIPR_RMAFIP | EESIPR_RRFIP | 604 EESIPR_RTLFIP | EESIPR_RTSFIP | 605 EESIPR_PREIP | EESIPR_CERFIP, 606 607 .tx_check = EESR_TC1 | EESR_FTC, 608 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 609 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 610 EESR_TDE, 611 .fdr_value = 0x0000070f, 612 613 .no_psr = 1, 614 .apr = 1, 615 .mpr = 1, 616 .tpauser = 1, 617 .hw_swap = 1, 618 .rpadir = 1, 619 .no_trimd = 1, 620 .no_ade = 1, 621 .xdfar_rw = 1, 622 .hw_checksum = 1, 623 .tsu = 1, 624 .no_tx_cntrs = 1, 625 }; 626 627 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 628 { 629 sh_eth_chip_reset(ndev); 630 631 sh_eth_select_mii(ndev); 632 } 633 634 /* R8A7740 */ 635 static struct sh_eth_cpu_data r8a7740_data = { 636 .soft_reset = sh_eth_soft_reset_gether, 637 638 .chip_reset = sh_eth_chip_reset_r8a7740, 639 .set_duplex = sh_eth_set_duplex, 640 .set_rate = sh_eth_set_rate_gether, 641 642 .register_type = SH_ETH_REG_GIGABIT, 643 644 .edtrr_trns = EDTRR_TRNS_GETHER, 645 .ecsr_value = ECSR_ICD | ECSR_MPD, 646 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 647 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 648 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 649 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 650 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 651 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 652 EESIPR_CEEFIP | EESIPR_CELFIP | 653 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 654 EESIPR_PREIP | EESIPR_CERFIP, 655 656 .tx_check = EESR_TC1 | EESR_FTC, 657 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 658 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 659 EESR_TDE, 660 .fdr_value = 0x0000070f, 661 662 .apr = 1, 663 .mpr = 1, 664 .tpauser = 1, 665 .bculr = 1, 666 .hw_swap = 1, 667 .rpadir = 1, 668 .no_trimd = 1, 669 .no_ade = 1, 670 .xdfar_rw = 1, 671 .hw_checksum = 1, 672 .tsu = 1, 673 .select_mii = 1, 674 .magic = 1, 675 .cexcr = 1, 676 }; 677 678 /* There is CPU dependent code */ 679 static void sh_eth_set_rate_rcar(struct net_device *ndev) 680 { 681 struct sh_eth_private *mdp = netdev_priv(ndev); 682 683 switch (mdp->speed) { 684 case 10: /* 10BASE */ 685 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 686 break; 687 case 100:/* 100BASE */ 688 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 689 break; 690 } 691 } 692 693 /* R-Car Gen1 */ 694 static struct sh_eth_cpu_data rcar_gen1_data = { 695 .soft_reset = sh_eth_soft_reset, 696 697 .set_duplex = sh_eth_set_duplex, 698 .set_rate = sh_eth_set_rate_rcar, 699 700 .register_type = SH_ETH_REG_FAST_RCAR, 701 702 .edtrr_trns = EDTRR_TRNS_ETHER, 703 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 704 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 705 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 706 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 707 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 708 EESIPR_RMAFIP | EESIPR_RRFIP | 709 EESIPR_RTLFIP | EESIPR_RTSFIP | 710 EESIPR_PREIP | EESIPR_CERFIP, 711 712 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 713 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 714 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 715 .fdr_value = 0x00000f0f, 716 717 .apr = 1, 718 .mpr = 1, 719 .tpauser = 1, 720 .hw_swap = 1, 721 .no_xdfar = 1, 722 }; 723 724 /* R-Car Gen2 and RZ/G1 */ 725 static struct sh_eth_cpu_data rcar_gen2_data = { 726 .soft_reset = sh_eth_soft_reset, 727 728 .set_duplex = sh_eth_set_duplex, 729 .set_rate = sh_eth_set_rate_rcar, 730 731 .register_type = SH_ETH_REG_FAST_RCAR, 732 733 .edtrr_trns = EDTRR_TRNS_ETHER, 734 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 735 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 736 ECSIPR_MPDIP, 737 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 738 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 739 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 740 EESIPR_RMAFIP | EESIPR_RRFIP | 741 EESIPR_RTLFIP | EESIPR_RTSFIP | 742 EESIPR_PREIP | EESIPR_CERFIP, 743 744 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 745 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 746 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 747 .fdr_value = 0x00000f0f, 748 749 .trscer_err_mask = DESC_I_RINT8, 750 751 .apr = 1, 752 .mpr = 1, 753 .tpauser = 1, 754 .hw_swap = 1, 755 .no_xdfar = 1, 756 .rmiimode = 1, 757 .magic = 1, 758 }; 759 760 /* R8A77980 */ 761 static struct sh_eth_cpu_data r8a77980_data = { 762 .soft_reset = sh_eth_soft_reset_gether, 763 764 .set_duplex = sh_eth_set_duplex, 765 .set_rate = sh_eth_set_rate_gether, 766 767 .register_type = SH_ETH_REG_GIGABIT, 768 769 .edtrr_trns = EDTRR_TRNS_GETHER, 770 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 771 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 772 ECSIPR_MPDIP, 773 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 774 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 775 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 776 EESIPR_RMAFIP | EESIPR_RRFIP | 777 EESIPR_RTLFIP | EESIPR_RTSFIP | 778 EESIPR_PREIP | EESIPR_CERFIP, 779 780 .tx_check = EESR_FTC | EESR_CD | EESR_TRO, 781 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 782 EESR_RFE | EESR_RDE | EESR_RFRMER | 783 EESR_TFE | EESR_TDE | EESR_ECI, 784 .fdr_value = 0x0000070f, 785 786 .apr = 1, 787 .mpr = 1, 788 .tpauser = 1, 789 .bculr = 1, 790 .hw_swap = 1, 791 .nbst = 1, 792 .rpadir = 1, 793 .no_trimd = 1, 794 .no_ade = 1, 795 .xdfar_rw = 1, 796 .hw_checksum = 1, 797 .select_mii = 1, 798 .magic = 1, 799 .cexcr = 1, 800 }; 801 802 /* R7S9210 */ 803 static struct sh_eth_cpu_data r7s9210_data = { 804 .soft_reset = sh_eth_soft_reset, 805 806 .set_duplex = sh_eth_set_duplex, 807 .set_rate = sh_eth_set_rate_rcar, 808 809 .register_type = SH_ETH_REG_FAST_SH4, 810 811 .edtrr_trns = EDTRR_TRNS_ETHER, 812 .ecsr_value = ECSR_ICD, 813 .ecsipr_value = ECSIPR_ICDIP, 814 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP | 815 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP | 816 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP | 817 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP | 818 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 819 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP | 820 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP, 821 822 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 823 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 824 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 825 826 .fdr_value = 0x0000070f, 827 828 .apr = 1, 829 .mpr = 1, 830 .tpauser = 1, 831 .hw_swap = 1, 832 .rpadir = 1, 833 .no_ade = 1, 834 .xdfar_rw = 1, 835 }; 836 #endif /* CONFIG_OF */ 837 838 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 839 { 840 struct sh_eth_private *mdp = netdev_priv(ndev); 841 842 switch (mdp->speed) { 843 case 10: /* 10BASE */ 844 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 845 break; 846 case 100:/* 100BASE */ 847 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 848 break; 849 } 850 } 851 852 /* SH7724 */ 853 static struct sh_eth_cpu_data sh7724_data = { 854 .soft_reset = sh_eth_soft_reset, 855 856 .set_duplex = sh_eth_set_duplex, 857 .set_rate = sh_eth_set_rate_sh7724, 858 859 .register_type = SH_ETH_REG_FAST_SH4, 860 861 .edtrr_trns = EDTRR_TRNS_ETHER, 862 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 863 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 864 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 865 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 866 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 867 EESIPR_RMAFIP | EESIPR_RRFIP | 868 EESIPR_RTLFIP | EESIPR_RTSFIP | 869 EESIPR_PREIP | EESIPR_CERFIP, 870 871 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 872 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 873 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 874 875 .apr = 1, 876 .mpr = 1, 877 .tpauser = 1, 878 .hw_swap = 1, 879 .rpadir = 1, 880 }; 881 882 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 883 { 884 struct sh_eth_private *mdp = netdev_priv(ndev); 885 886 switch (mdp->speed) { 887 case 10: /* 10BASE */ 888 sh_eth_write(ndev, 0, RTRATE); 889 break; 890 case 100:/* 100BASE */ 891 sh_eth_write(ndev, 1, RTRATE); 892 break; 893 } 894 } 895 896 /* SH7757 */ 897 static struct sh_eth_cpu_data sh7757_data = { 898 .soft_reset = sh_eth_soft_reset, 899 900 .set_duplex = sh_eth_set_duplex, 901 .set_rate = sh_eth_set_rate_sh7757, 902 903 .register_type = SH_ETH_REG_FAST_SH4, 904 905 .edtrr_trns = EDTRR_TRNS_ETHER, 906 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 907 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 908 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 909 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 910 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 911 EESIPR_CEEFIP | EESIPR_CELFIP | 912 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 913 EESIPR_PREIP | EESIPR_CERFIP, 914 915 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 916 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 917 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 918 919 .irq_flags = IRQF_SHARED, 920 .apr = 1, 921 .mpr = 1, 922 .tpauser = 1, 923 .hw_swap = 1, 924 .no_ade = 1, 925 .rpadir = 1, 926 .rtrate = 1, 927 .dual_port = 1, 928 }; 929 930 #define SH_GIGA_ETH_BASE 0xfee00000UL 931 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 932 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 933 static void sh_eth_chip_reset_giga(struct net_device *ndev) 934 { 935 u32 mahr[2], malr[2]; 936 int i; 937 938 /* save MAHR and MALR */ 939 for (i = 0; i < 2; i++) { 940 malr[i] = ioread32((void *)GIGA_MALR(i)); 941 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 942 } 943 944 sh_eth_chip_reset(ndev); 945 946 /* restore MAHR and MALR */ 947 for (i = 0; i < 2; i++) { 948 iowrite32(malr[i], (void *)GIGA_MALR(i)); 949 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 950 } 951 } 952 953 static void sh_eth_set_rate_giga(struct net_device *ndev) 954 { 955 struct sh_eth_private *mdp = netdev_priv(ndev); 956 957 switch (mdp->speed) { 958 case 10: /* 10BASE */ 959 sh_eth_write(ndev, 0x00000000, GECMR); 960 break; 961 case 100:/* 100BASE */ 962 sh_eth_write(ndev, 0x00000010, GECMR); 963 break; 964 case 1000: /* 1000BASE */ 965 sh_eth_write(ndev, 0x00000020, GECMR); 966 break; 967 } 968 } 969 970 /* SH7757(GETHERC) */ 971 static struct sh_eth_cpu_data sh7757_data_giga = { 972 .soft_reset = sh_eth_soft_reset_gether, 973 974 .chip_reset = sh_eth_chip_reset_giga, 975 .set_duplex = sh_eth_set_duplex, 976 .set_rate = sh_eth_set_rate_giga, 977 978 .register_type = SH_ETH_REG_GIGABIT, 979 980 .edtrr_trns = EDTRR_TRNS_GETHER, 981 .ecsr_value = ECSR_ICD | ECSR_MPD, 982 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 983 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 984 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 985 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 986 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 987 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 988 EESIPR_CEEFIP | EESIPR_CELFIP | 989 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 990 EESIPR_PREIP | EESIPR_CERFIP, 991 992 .tx_check = EESR_TC1 | EESR_FTC, 993 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 994 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 995 EESR_TDE, 996 .fdr_value = 0x0000072f, 997 998 .irq_flags = IRQF_SHARED, 999 .apr = 1, 1000 .mpr = 1, 1001 .tpauser = 1, 1002 .bculr = 1, 1003 .hw_swap = 1, 1004 .rpadir = 1, 1005 .no_trimd = 1, 1006 .no_ade = 1, 1007 .xdfar_rw = 1, 1008 .tsu = 1, 1009 .cexcr = 1, 1010 .dual_port = 1, 1011 }; 1012 1013 /* SH7734 */ 1014 static struct sh_eth_cpu_data sh7734_data = { 1015 .soft_reset = sh_eth_soft_reset_gether, 1016 1017 .chip_reset = sh_eth_chip_reset, 1018 .set_duplex = sh_eth_set_duplex, 1019 .set_rate = sh_eth_set_rate_gether, 1020 1021 .register_type = SH_ETH_REG_GIGABIT, 1022 1023 .edtrr_trns = EDTRR_TRNS_GETHER, 1024 .ecsr_value = ECSR_ICD | ECSR_MPD, 1025 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 1026 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1027 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1028 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1029 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1030 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1031 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1032 EESIPR_PREIP | EESIPR_CERFIP, 1033 1034 .tx_check = EESR_TC1 | EESR_FTC, 1035 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1036 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 1037 EESR_TDE, 1038 1039 .apr = 1, 1040 .mpr = 1, 1041 .tpauser = 1, 1042 .bculr = 1, 1043 .hw_swap = 1, 1044 .no_trimd = 1, 1045 .no_ade = 1, 1046 .xdfar_rw = 1, 1047 .tsu = 1, 1048 .hw_checksum = 1, 1049 .select_mii = 1, 1050 .magic = 1, 1051 .cexcr = 1, 1052 }; 1053 1054 /* SH7763 */ 1055 static struct sh_eth_cpu_data sh7763_data = { 1056 .soft_reset = sh_eth_soft_reset_gether, 1057 1058 .chip_reset = sh_eth_chip_reset, 1059 .set_duplex = sh_eth_set_duplex, 1060 .set_rate = sh_eth_set_rate_gether, 1061 1062 .register_type = SH_ETH_REG_GIGABIT, 1063 1064 .edtrr_trns = EDTRR_TRNS_GETHER, 1065 .ecsr_value = ECSR_ICD | ECSR_MPD, 1066 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 1067 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1068 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1069 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1070 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1071 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1072 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1073 EESIPR_PREIP | EESIPR_CERFIP, 1074 1075 .tx_check = EESR_TC1 | EESR_FTC, 1076 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1077 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 1078 1079 .apr = 1, 1080 .mpr = 1, 1081 .tpauser = 1, 1082 .bculr = 1, 1083 .hw_swap = 1, 1084 .no_trimd = 1, 1085 .no_ade = 1, 1086 .xdfar_rw = 1, 1087 .tsu = 1, 1088 .irq_flags = IRQF_SHARED, 1089 .magic = 1, 1090 .cexcr = 1, 1091 .dual_port = 1, 1092 }; 1093 1094 static struct sh_eth_cpu_data sh7619_data = { 1095 .soft_reset = sh_eth_soft_reset, 1096 1097 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1098 1099 .edtrr_trns = EDTRR_TRNS_ETHER, 1100 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1101 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1102 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1103 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1104 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1105 EESIPR_CEEFIP | EESIPR_CELFIP | 1106 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1107 EESIPR_PREIP | EESIPR_CERFIP, 1108 1109 .apr = 1, 1110 .mpr = 1, 1111 .tpauser = 1, 1112 .hw_swap = 1, 1113 }; 1114 1115 static struct sh_eth_cpu_data sh771x_data = { 1116 .soft_reset = sh_eth_soft_reset, 1117 1118 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1119 1120 .edtrr_trns = EDTRR_TRNS_ETHER, 1121 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1122 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1123 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1124 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1125 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1126 EESIPR_CEEFIP | EESIPR_CELFIP | 1127 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1128 EESIPR_PREIP | EESIPR_CERFIP, 1129 .tsu = 1, 1130 .dual_port = 1, 1131 }; 1132 1133 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 1134 { 1135 if (!cd->ecsr_value) 1136 cd->ecsr_value = DEFAULT_ECSR_INIT; 1137 1138 if (!cd->ecsipr_value) 1139 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 1140 1141 if (!cd->fcftr_value) 1142 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 1143 DEFAULT_FIFO_F_D_RFD; 1144 1145 if (!cd->fdr_value) 1146 cd->fdr_value = DEFAULT_FDR_INIT; 1147 1148 if (!cd->tx_check) 1149 cd->tx_check = DEFAULT_TX_CHECK; 1150 1151 if (!cd->eesr_err_check) 1152 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 1153 1154 if (!cd->trscer_err_mask) 1155 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 1156 } 1157 1158 static void sh_eth_set_receive_align(struct sk_buff *skb) 1159 { 1160 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1161 1162 if (reserve) 1163 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1164 } 1165 1166 /* Program the hardware MAC address from dev->dev_addr. */ 1167 static void update_mac_address(struct net_device *ndev) 1168 { 1169 sh_eth_write(ndev, 1170 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1171 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1172 sh_eth_write(ndev, 1173 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1174 } 1175 1176 /* Get MAC address from SuperH MAC address register 1177 * 1178 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1179 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1180 * When you want use this device, you must set MAC address in bootloader. 1181 * 1182 */ 1183 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1184 { 1185 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1186 memcpy(ndev->dev_addr, mac, ETH_ALEN); 1187 } else { 1188 u32 mahr = sh_eth_read(ndev, MAHR); 1189 u32 malr = sh_eth_read(ndev, MALR); 1190 1191 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 1192 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 1193 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 1194 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 1195 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 1196 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 1197 } 1198 } 1199 1200 struct bb_info { 1201 void (*set_gate)(void *addr); 1202 struct mdiobb_ctrl ctrl; 1203 void *addr; 1204 }; 1205 1206 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1207 { 1208 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1209 u32 pir; 1210 1211 if (bitbang->set_gate) 1212 bitbang->set_gate(bitbang->addr); 1213 1214 pir = ioread32(bitbang->addr); 1215 if (set) 1216 pir |= mask; 1217 else 1218 pir &= ~mask; 1219 iowrite32(pir, bitbang->addr); 1220 } 1221 1222 /* Data I/O pin control */ 1223 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1224 { 1225 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1226 } 1227 1228 /* Set bit data*/ 1229 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1230 { 1231 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1232 } 1233 1234 /* Get bit data*/ 1235 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1236 { 1237 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1238 1239 if (bitbang->set_gate) 1240 bitbang->set_gate(bitbang->addr); 1241 1242 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1243 } 1244 1245 /* MDC pin control */ 1246 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1247 { 1248 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1249 } 1250 1251 /* mdio bus control struct */ 1252 static struct mdiobb_ops bb_ops = { 1253 .owner = THIS_MODULE, 1254 .set_mdc = sh_mdc_ctrl, 1255 .set_mdio_dir = sh_mmd_ctrl, 1256 .set_mdio_data = sh_set_mdio, 1257 .get_mdio_data = sh_get_mdio, 1258 }; 1259 1260 /* free Tx skb function */ 1261 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) 1262 { 1263 struct sh_eth_private *mdp = netdev_priv(ndev); 1264 struct sh_eth_txdesc *txdesc; 1265 int free_num = 0; 1266 int entry; 1267 bool sent; 1268 1269 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1270 entry = mdp->dirty_tx % mdp->num_tx_ring; 1271 txdesc = &mdp->tx_ring[entry]; 1272 sent = !(txdesc->status & cpu_to_le32(TD_TACT)); 1273 if (sent_only && !sent) 1274 break; 1275 /* TACT bit must be checked before all the following reads */ 1276 dma_rmb(); 1277 netif_info(mdp, tx_done, ndev, 1278 "tx entry %d status 0x%08x\n", 1279 entry, le32_to_cpu(txdesc->status)); 1280 /* Free the original skb. */ 1281 if (mdp->tx_skbuff[entry]) { 1282 dma_unmap_single(&mdp->pdev->dev, 1283 le32_to_cpu(txdesc->addr), 1284 le32_to_cpu(txdesc->len) >> 16, 1285 DMA_TO_DEVICE); 1286 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1287 mdp->tx_skbuff[entry] = NULL; 1288 free_num++; 1289 } 1290 txdesc->status = cpu_to_le32(TD_TFP); 1291 if (entry >= mdp->num_tx_ring - 1) 1292 txdesc->status |= cpu_to_le32(TD_TDLE); 1293 1294 if (sent) { 1295 ndev->stats.tx_packets++; 1296 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1297 } 1298 } 1299 return free_num; 1300 } 1301 1302 /* free skb and descriptor buffer */ 1303 static void sh_eth_ring_free(struct net_device *ndev) 1304 { 1305 struct sh_eth_private *mdp = netdev_priv(ndev); 1306 int ringsize, i; 1307 1308 if (mdp->rx_ring) { 1309 for (i = 0; i < mdp->num_rx_ring; i++) { 1310 if (mdp->rx_skbuff[i]) { 1311 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; 1312 1313 dma_unmap_single(&mdp->pdev->dev, 1314 le32_to_cpu(rxdesc->addr), 1315 ALIGN(mdp->rx_buf_sz, 32), 1316 DMA_FROM_DEVICE); 1317 } 1318 } 1319 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1320 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, 1321 mdp->rx_desc_dma); 1322 mdp->rx_ring = NULL; 1323 } 1324 1325 /* Free Rx skb ringbuffer */ 1326 if (mdp->rx_skbuff) { 1327 for (i = 0; i < mdp->num_rx_ring; i++) 1328 dev_kfree_skb(mdp->rx_skbuff[i]); 1329 } 1330 kfree(mdp->rx_skbuff); 1331 mdp->rx_skbuff = NULL; 1332 1333 if (mdp->tx_ring) { 1334 sh_eth_tx_free(ndev, false); 1335 1336 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1337 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, 1338 mdp->tx_desc_dma); 1339 mdp->tx_ring = NULL; 1340 } 1341 1342 /* Free Tx skb ringbuffer */ 1343 kfree(mdp->tx_skbuff); 1344 mdp->tx_skbuff = NULL; 1345 } 1346 1347 /* format skb and descriptor buffer */ 1348 static void sh_eth_ring_format(struct net_device *ndev) 1349 { 1350 struct sh_eth_private *mdp = netdev_priv(ndev); 1351 int i; 1352 struct sk_buff *skb; 1353 struct sh_eth_rxdesc *rxdesc = NULL; 1354 struct sh_eth_txdesc *txdesc = NULL; 1355 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1356 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1357 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1358 dma_addr_t dma_addr; 1359 u32 buf_len; 1360 1361 mdp->cur_rx = 0; 1362 mdp->cur_tx = 0; 1363 mdp->dirty_rx = 0; 1364 mdp->dirty_tx = 0; 1365 1366 memset(mdp->rx_ring, 0, rx_ringsize); 1367 1368 /* build Rx ring buffer */ 1369 for (i = 0; i < mdp->num_rx_ring; i++) { 1370 /* skb */ 1371 mdp->rx_skbuff[i] = NULL; 1372 skb = netdev_alloc_skb(ndev, skbuff_size); 1373 if (skb == NULL) 1374 break; 1375 sh_eth_set_receive_align(skb); 1376 1377 /* The size of the buffer is a multiple of 32 bytes. */ 1378 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1379 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, 1380 DMA_FROM_DEVICE); 1381 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1382 kfree_skb(skb); 1383 break; 1384 } 1385 mdp->rx_skbuff[i] = skb; 1386 1387 /* RX descriptor */ 1388 rxdesc = &mdp->rx_ring[i]; 1389 rxdesc->len = cpu_to_le32(buf_len << 16); 1390 rxdesc->addr = cpu_to_le32(dma_addr); 1391 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1392 1393 /* Rx descriptor address set */ 1394 if (i == 0) { 1395 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1396 if (mdp->cd->xdfar_rw) 1397 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1398 } 1399 } 1400 1401 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1402 1403 /* Mark the last entry as wrapping the ring. */ 1404 if (rxdesc) 1405 rxdesc->status |= cpu_to_le32(RD_RDLE); 1406 1407 memset(mdp->tx_ring, 0, tx_ringsize); 1408 1409 /* build Tx ring buffer */ 1410 for (i = 0; i < mdp->num_tx_ring; i++) { 1411 mdp->tx_skbuff[i] = NULL; 1412 txdesc = &mdp->tx_ring[i]; 1413 txdesc->status = cpu_to_le32(TD_TFP); 1414 txdesc->len = cpu_to_le32(0); 1415 if (i == 0) { 1416 /* Tx descriptor address set */ 1417 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1418 if (mdp->cd->xdfar_rw) 1419 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1420 } 1421 } 1422 1423 txdesc->status |= cpu_to_le32(TD_TDLE); 1424 } 1425 1426 /* Get skb and descriptor buffer */ 1427 static int sh_eth_ring_init(struct net_device *ndev) 1428 { 1429 struct sh_eth_private *mdp = netdev_priv(ndev); 1430 int rx_ringsize, tx_ringsize; 1431 1432 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1433 * card needs room to do 8 byte alignment, +2 so we can reserve 1434 * the first 2 bytes, and +16 gets room for the status word from the 1435 * card. 1436 */ 1437 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1438 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1439 if (mdp->cd->rpadir) 1440 mdp->rx_buf_sz += NET_IP_ALIGN; 1441 1442 /* Allocate RX and TX skb rings */ 1443 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1444 GFP_KERNEL); 1445 if (!mdp->rx_skbuff) 1446 return -ENOMEM; 1447 1448 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1449 GFP_KERNEL); 1450 if (!mdp->tx_skbuff) 1451 goto ring_free; 1452 1453 /* Allocate all Rx descriptors. */ 1454 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1455 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, 1456 &mdp->rx_desc_dma, GFP_KERNEL); 1457 if (!mdp->rx_ring) 1458 goto ring_free; 1459 1460 mdp->dirty_rx = 0; 1461 1462 /* Allocate all Tx descriptors. */ 1463 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1464 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, 1465 &mdp->tx_desc_dma, GFP_KERNEL); 1466 if (!mdp->tx_ring) 1467 goto ring_free; 1468 return 0; 1469 1470 ring_free: 1471 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1472 sh_eth_ring_free(ndev); 1473 1474 return -ENOMEM; 1475 } 1476 1477 static int sh_eth_dev_init(struct net_device *ndev) 1478 { 1479 struct sh_eth_private *mdp = netdev_priv(ndev); 1480 int ret; 1481 1482 /* Soft Reset */ 1483 ret = mdp->cd->soft_reset(ndev); 1484 if (ret) 1485 return ret; 1486 1487 if (mdp->cd->rmiimode) 1488 sh_eth_write(ndev, 0x1, RMIIMODE); 1489 1490 /* Descriptor format */ 1491 sh_eth_ring_format(ndev); 1492 if (mdp->cd->rpadir) 1493 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR); 1494 1495 /* all sh_eth int mask */ 1496 sh_eth_write(ndev, 0, EESIPR); 1497 1498 #if defined(__LITTLE_ENDIAN) 1499 if (mdp->cd->hw_swap) 1500 sh_eth_write(ndev, EDMR_EL, EDMR); 1501 else 1502 #endif 1503 sh_eth_write(ndev, 0, EDMR); 1504 1505 /* FIFO size set */ 1506 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1507 sh_eth_write(ndev, 0, TFTR); 1508 1509 /* Frame recv control (enable multiple-packets per rx irq) */ 1510 sh_eth_write(ndev, RMCR_RNC, RMCR); 1511 1512 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1513 1514 /* DMA transfer burst mode */ 1515 if (mdp->cd->nbst) 1516 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST); 1517 1518 /* Burst cycle count upper-limit */ 1519 if (mdp->cd->bculr) 1520 sh_eth_write(ndev, 0x800, BCULR); 1521 1522 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1523 1524 if (!mdp->cd->no_trimd) 1525 sh_eth_write(ndev, 0, TRIMD); 1526 1527 /* Recv frame limit set register */ 1528 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1529 RFLR); 1530 1531 sh_eth_modify(ndev, EESR, 0, 0); 1532 mdp->irq_enabled = true; 1533 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1534 1535 /* PAUSE Prohibition */ 1536 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1537 ECMR_TE | ECMR_RE, ECMR); 1538 1539 if (mdp->cd->set_rate) 1540 mdp->cd->set_rate(ndev); 1541 1542 /* E-MAC Status Register clear */ 1543 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1544 1545 /* E-MAC Interrupt Enable register */ 1546 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1547 1548 /* Set MAC address */ 1549 update_mac_address(ndev); 1550 1551 /* mask reset */ 1552 if (mdp->cd->apr) 1553 sh_eth_write(ndev, 1, APR); 1554 if (mdp->cd->mpr) 1555 sh_eth_write(ndev, 1, MPR); 1556 if (mdp->cd->tpauser) 1557 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1558 1559 /* Setting the Rx mode will start the Rx process. */ 1560 sh_eth_write(ndev, EDRRR_R, EDRRR); 1561 1562 return ret; 1563 } 1564 1565 static void sh_eth_dev_exit(struct net_device *ndev) 1566 { 1567 struct sh_eth_private *mdp = netdev_priv(ndev); 1568 int i; 1569 1570 /* Deactivate all TX descriptors, so DMA should stop at next 1571 * packet boundary if it's currently running 1572 */ 1573 for (i = 0; i < mdp->num_tx_ring; i++) 1574 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1575 1576 /* Disable TX FIFO egress to MAC */ 1577 sh_eth_rcv_snd_disable(ndev); 1578 1579 /* Stop RX DMA at next packet boundary */ 1580 sh_eth_write(ndev, 0, EDRRR); 1581 1582 /* Aside from TX DMA, we can't tell when the hardware is 1583 * really stopped, so we need to reset to make sure. 1584 * Before doing that, wait for long enough to *probably* 1585 * finish transmitting the last packet and poll stats. 1586 */ 1587 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1588 sh_eth_get_stats(ndev); 1589 mdp->cd->soft_reset(ndev); 1590 1591 /* Set MAC address again */ 1592 update_mac_address(ndev); 1593 } 1594 1595 /* Packet receive function */ 1596 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1597 { 1598 struct sh_eth_private *mdp = netdev_priv(ndev); 1599 struct sh_eth_rxdesc *rxdesc; 1600 1601 int entry = mdp->cur_rx % mdp->num_rx_ring; 1602 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1603 int limit; 1604 struct sk_buff *skb; 1605 u32 desc_status; 1606 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1607 dma_addr_t dma_addr; 1608 u16 pkt_len; 1609 u32 buf_len; 1610 1611 boguscnt = min(boguscnt, *quota); 1612 limit = boguscnt; 1613 rxdesc = &mdp->rx_ring[entry]; 1614 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1615 /* RACT bit must be checked before all the following reads */ 1616 dma_rmb(); 1617 desc_status = le32_to_cpu(rxdesc->status); 1618 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1619 1620 if (--boguscnt < 0) 1621 break; 1622 1623 netif_info(mdp, rx_status, ndev, 1624 "rx entry %d status 0x%08x len %d\n", 1625 entry, desc_status, pkt_len); 1626 1627 if (!(desc_status & RDFEND)) 1628 ndev->stats.rx_length_errors++; 1629 1630 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1631 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1632 * bit 0. However, in case of the R8A7740 and R7S72100 1633 * the RFS bits are from bit 25 to bit 16. So, the 1634 * driver needs right shifting by 16. 1635 */ 1636 if (mdp->cd->hw_checksum) 1637 desc_status >>= 16; 1638 1639 skb = mdp->rx_skbuff[entry]; 1640 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1641 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1642 ndev->stats.rx_errors++; 1643 if (desc_status & RD_RFS1) 1644 ndev->stats.rx_crc_errors++; 1645 if (desc_status & RD_RFS2) 1646 ndev->stats.rx_frame_errors++; 1647 if (desc_status & RD_RFS3) 1648 ndev->stats.rx_length_errors++; 1649 if (desc_status & RD_RFS4) 1650 ndev->stats.rx_length_errors++; 1651 if (desc_status & RD_RFS6) 1652 ndev->stats.rx_missed_errors++; 1653 if (desc_status & RD_RFS10) 1654 ndev->stats.rx_over_errors++; 1655 } else if (skb) { 1656 dma_addr = le32_to_cpu(rxdesc->addr); 1657 if (!mdp->cd->hw_swap) 1658 sh_eth_soft_swap( 1659 phys_to_virt(ALIGN(dma_addr, 4)), 1660 pkt_len + 2); 1661 mdp->rx_skbuff[entry] = NULL; 1662 if (mdp->cd->rpadir) 1663 skb_reserve(skb, NET_IP_ALIGN); 1664 dma_unmap_single(&mdp->pdev->dev, dma_addr, 1665 ALIGN(mdp->rx_buf_sz, 32), 1666 DMA_FROM_DEVICE); 1667 skb_put(skb, pkt_len); 1668 skb->protocol = eth_type_trans(skb, ndev); 1669 netif_receive_skb(skb); 1670 ndev->stats.rx_packets++; 1671 ndev->stats.rx_bytes += pkt_len; 1672 if (desc_status & RD_RFS8) 1673 ndev->stats.multicast++; 1674 } 1675 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1676 rxdesc = &mdp->rx_ring[entry]; 1677 } 1678 1679 /* Refill the Rx ring buffers. */ 1680 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1681 entry = mdp->dirty_rx % mdp->num_rx_ring; 1682 rxdesc = &mdp->rx_ring[entry]; 1683 /* The size of the buffer is 32 byte boundary. */ 1684 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1685 rxdesc->len = cpu_to_le32(buf_len << 16); 1686 1687 if (mdp->rx_skbuff[entry] == NULL) { 1688 skb = netdev_alloc_skb(ndev, skbuff_size); 1689 if (skb == NULL) 1690 break; /* Better luck next round. */ 1691 sh_eth_set_receive_align(skb); 1692 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, 1693 buf_len, DMA_FROM_DEVICE); 1694 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1695 kfree_skb(skb); 1696 break; 1697 } 1698 mdp->rx_skbuff[entry] = skb; 1699 1700 skb_checksum_none_assert(skb); 1701 rxdesc->addr = cpu_to_le32(dma_addr); 1702 } 1703 dma_wmb(); /* RACT bit must be set after all the above writes */ 1704 if (entry >= mdp->num_rx_ring - 1) 1705 rxdesc->status |= 1706 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1707 else 1708 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1709 } 1710 1711 /* Restart Rx engine if stopped. */ 1712 /* If we don't need to check status, don't. -KDU */ 1713 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1714 /* fix the values for the next receiving if RDE is set */ 1715 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) { 1716 u32 count = (sh_eth_read(ndev, RDFAR) - 1717 sh_eth_read(ndev, RDLAR)) >> 4; 1718 1719 mdp->cur_rx = count; 1720 mdp->dirty_rx = count; 1721 } 1722 sh_eth_write(ndev, EDRRR_R, EDRRR); 1723 } 1724 1725 *quota -= limit - boguscnt - 1; 1726 1727 return *quota <= 0; 1728 } 1729 1730 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1731 { 1732 /* disable tx and rx */ 1733 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1734 } 1735 1736 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1737 { 1738 /* enable tx and rx */ 1739 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1740 } 1741 1742 /* E-MAC interrupt handler */ 1743 static void sh_eth_emac_interrupt(struct net_device *ndev) 1744 { 1745 struct sh_eth_private *mdp = netdev_priv(ndev); 1746 u32 felic_stat; 1747 u32 link_stat; 1748 1749 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1750 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1751 if (felic_stat & ECSR_ICD) 1752 ndev->stats.tx_carrier_errors++; 1753 if (felic_stat & ECSR_MPD) 1754 pm_wakeup_event(&mdp->pdev->dev, 0); 1755 if (felic_stat & ECSR_LCHNG) { 1756 /* Link Changed */ 1757 if (mdp->cd->no_psr || mdp->no_ether_link) 1758 return; 1759 link_stat = sh_eth_read(ndev, PSR); 1760 if (mdp->ether_link_active_low) 1761 link_stat = ~link_stat; 1762 if (!(link_stat & PHY_ST_LINK)) { 1763 sh_eth_rcv_snd_disable(ndev); 1764 } else { 1765 /* Link Up */ 1766 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1767 /* clear int */ 1768 sh_eth_modify(ndev, ECSR, 0, 0); 1769 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1770 /* enable tx and rx */ 1771 sh_eth_rcv_snd_enable(ndev); 1772 } 1773 } 1774 } 1775 1776 /* error control function */ 1777 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1778 { 1779 struct sh_eth_private *mdp = netdev_priv(ndev); 1780 u32 mask; 1781 1782 if (intr_status & EESR_TWB) { 1783 /* Unused write back interrupt */ 1784 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1785 ndev->stats.tx_aborted_errors++; 1786 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1787 } 1788 } 1789 1790 if (intr_status & EESR_RABT) { 1791 /* Receive Abort int */ 1792 if (intr_status & EESR_RFRMER) { 1793 /* Receive Frame Overflow int */ 1794 ndev->stats.rx_frame_errors++; 1795 } 1796 } 1797 1798 if (intr_status & EESR_TDE) { 1799 /* Transmit Descriptor Empty int */ 1800 ndev->stats.tx_fifo_errors++; 1801 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1802 } 1803 1804 if (intr_status & EESR_TFE) { 1805 /* FIFO under flow */ 1806 ndev->stats.tx_fifo_errors++; 1807 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1808 } 1809 1810 if (intr_status & EESR_RDE) { 1811 /* Receive Descriptor Empty int */ 1812 ndev->stats.rx_over_errors++; 1813 } 1814 1815 if (intr_status & EESR_RFE) { 1816 /* Receive FIFO Overflow int */ 1817 ndev->stats.rx_fifo_errors++; 1818 } 1819 1820 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1821 /* Address Error */ 1822 ndev->stats.tx_fifo_errors++; 1823 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1824 } 1825 1826 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1827 if (mdp->cd->no_ade) 1828 mask &= ~EESR_ADE; 1829 if (intr_status & mask) { 1830 /* Tx error */ 1831 u32 edtrr = sh_eth_read(ndev, EDTRR); 1832 1833 /* dmesg */ 1834 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1835 intr_status, mdp->cur_tx, mdp->dirty_tx, 1836 (u32)ndev->state, edtrr); 1837 /* dirty buffer free */ 1838 sh_eth_tx_free(ndev, true); 1839 1840 /* SH7712 BUG */ 1841 if (edtrr ^ mdp->cd->edtrr_trns) { 1842 /* tx dma start */ 1843 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 1844 } 1845 /* wakeup */ 1846 netif_wake_queue(ndev); 1847 } 1848 } 1849 1850 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1851 { 1852 struct net_device *ndev = netdev; 1853 struct sh_eth_private *mdp = netdev_priv(ndev); 1854 struct sh_eth_cpu_data *cd = mdp->cd; 1855 irqreturn_t ret = IRQ_NONE; 1856 u32 intr_status, intr_enable; 1857 1858 spin_lock(&mdp->lock); 1859 1860 /* Get interrupt status */ 1861 intr_status = sh_eth_read(ndev, EESR); 1862 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1863 * enabled since it's the one that comes thru regardless of the mask, 1864 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1865 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1866 * bit... 1867 */ 1868 intr_enable = sh_eth_read(ndev, EESIPR); 1869 intr_status &= intr_enable | EESIPR_ECIIP; 1870 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1871 cd->eesr_err_check)) 1872 ret = IRQ_HANDLED; 1873 else 1874 goto out; 1875 1876 if (unlikely(!mdp->irq_enabled)) { 1877 sh_eth_write(ndev, 0, EESIPR); 1878 goto out; 1879 } 1880 1881 if (intr_status & EESR_RX_CHECK) { 1882 if (napi_schedule_prep(&mdp->napi)) { 1883 /* Mask Rx interrupts */ 1884 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1885 EESIPR); 1886 __napi_schedule(&mdp->napi); 1887 } else { 1888 netdev_warn(ndev, 1889 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1890 intr_status, intr_enable); 1891 } 1892 } 1893 1894 /* Tx Check */ 1895 if (intr_status & cd->tx_check) { 1896 /* Clear Tx interrupts */ 1897 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1898 1899 sh_eth_tx_free(ndev, true); 1900 netif_wake_queue(ndev); 1901 } 1902 1903 /* E-MAC interrupt */ 1904 if (intr_status & EESR_ECI) 1905 sh_eth_emac_interrupt(ndev); 1906 1907 if (intr_status & cd->eesr_err_check) { 1908 /* Clear error interrupts */ 1909 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1910 1911 sh_eth_error(ndev, intr_status); 1912 } 1913 1914 out: 1915 spin_unlock(&mdp->lock); 1916 1917 return ret; 1918 } 1919 1920 static int sh_eth_poll(struct napi_struct *napi, int budget) 1921 { 1922 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1923 napi); 1924 struct net_device *ndev = napi->dev; 1925 int quota = budget; 1926 u32 intr_status; 1927 1928 for (;;) { 1929 intr_status = sh_eth_read(ndev, EESR); 1930 if (!(intr_status & EESR_RX_CHECK)) 1931 break; 1932 /* Clear Rx interrupts */ 1933 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1934 1935 if (sh_eth_rx(ndev, intr_status, "a)) 1936 goto out; 1937 } 1938 1939 napi_complete(napi); 1940 1941 /* Reenable Rx interrupts */ 1942 if (mdp->irq_enabled) 1943 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1944 out: 1945 return budget - quota; 1946 } 1947 1948 /* PHY state control function */ 1949 static void sh_eth_adjust_link(struct net_device *ndev) 1950 { 1951 struct sh_eth_private *mdp = netdev_priv(ndev); 1952 struct phy_device *phydev = ndev->phydev; 1953 unsigned long flags; 1954 int new_state = 0; 1955 1956 spin_lock_irqsave(&mdp->lock, flags); 1957 1958 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1959 if (mdp->cd->no_psr || mdp->no_ether_link) 1960 sh_eth_rcv_snd_disable(ndev); 1961 1962 if (phydev->link) { 1963 if (phydev->duplex != mdp->duplex) { 1964 new_state = 1; 1965 mdp->duplex = phydev->duplex; 1966 if (mdp->cd->set_duplex) 1967 mdp->cd->set_duplex(ndev); 1968 } 1969 1970 if (phydev->speed != mdp->speed) { 1971 new_state = 1; 1972 mdp->speed = phydev->speed; 1973 if (mdp->cd->set_rate) 1974 mdp->cd->set_rate(ndev); 1975 } 1976 if (!mdp->link) { 1977 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 1978 new_state = 1; 1979 mdp->link = phydev->link; 1980 } 1981 } else if (mdp->link) { 1982 new_state = 1; 1983 mdp->link = 0; 1984 mdp->speed = 0; 1985 mdp->duplex = -1; 1986 } 1987 1988 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1989 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link) 1990 sh_eth_rcv_snd_enable(ndev); 1991 1992 mmiowb(); 1993 spin_unlock_irqrestore(&mdp->lock, flags); 1994 1995 if (new_state && netif_msg_link(mdp)) 1996 phy_print_status(phydev); 1997 } 1998 1999 /* PHY init function */ 2000 static int sh_eth_phy_init(struct net_device *ndev) 2001 { 2002 struct device_node *np = ndev->dev.parent->of_node; 2003 struct sh_eth_private *mdp = netdev_priv(ndev); 2004 struct phy_device *phydev; 2005 2006 mdp->link = 0; 2007 mdp->speed = 0; 2008 mdp->duplex = -1; 2009 2010 /* Try connect to PHY */ 2011 if (np) { 2012 struct device_node *pn; 2013 2014 pn = of_parse_phandle(np, "phy-handle", 0); 2015 phydev = of_phy_connect(ndev, pn, 2016 sh_eth_adjust_link, 0, 2017 mdp->phy_interface); 2018 2019 of_node_put(pn); 2020 if (!phydev) 2021 phydev = ERR_PTR(-ENOENT); 2022 } else { 2023 char phy_id[MII_BUS_ID_SIZE + 3]; 2024 2025 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 2026 mdp->mii_bus->id, mdp->phy_id); 2027 2028 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 2029 mdp->phy_interface); 2030 } 2031 2032 if (IS_ERR(phydev)) { 2033 netdev_err(ndev, "failed to connect PHY\n"); 2034 return PTR_ERR(phydev); 2035 } 2036 2037 /* mask with MAC supported features */ 2038 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) { 2039 int err = phy_set_max_speed(phydev, SPEED_100); 2040 if (err) { 2041 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n"); 2042 phy_disconnect(phydev); 2043 return err; 2044 } 2045 } 2046 2047 phy_attached_info(phydev); 2048 2049 return 0; 2050 } 2051 2052 /* PHY control start function */ 2053 static int sh_eth_phy_start(struct net_device *ndev) 2054 { 2055 int ret; 2056 2057 ret = sh_eth_phy_init(ndev); 2058 if (ret) 2059 return ret; 2060 2061 phy_start(ndev->phydev); 2062 2063 return 0; 2064 } 2065 2066 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 2067 * version must be bumped as well. Just adding registers up to that 2068 * limit is fine, as long as the existing register indices don't 2069 * change. 2070 */ 2071 #define SH_ETH_REG_DUMP_VERSION 1 2072 #define SH_ETH_REG_DUMP_MAX_REGS 256 2073 2074 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 2075 { 2076 struct sh_eth_private *mdp = netdev_priv(ndev); 2077 struct sh_eth_cpu_data *cd = mdp->cd; 2078 u32 *valid_map; 2079 size_t len; 2080 2081 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 2082 2083 /* Dump starts with a bitmap that tells ethtool which 2084 * registers are defined for this chip. 2085 */ 2086 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 2087 if (buf) { 2088 valid_map = buf; 2089 buf += len; 2090 } else { 2091 valid_map = NULL; 2092 } 2093 2094 /* Add a register to the dump, if it has a defined offset. 2095 * This automatically skips most undefined registers, but for 2096 * some it is also necessary to check a capability flag in 2097 * struct sh_eth_cpu_data. 2098 */ 2099 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 2100 #define add_reg_from(reg, read_expr) do { \ 2101 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2102 if (buf) { \ 2103 mark_reg_valid(reg); \ 2104 *buf++ = read_expr; \ 2105 } \ 2106 ++len; \ 2107 } \ 2108 } while (0) 2109 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2110 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2111 2112 add_reg(EDSR); 2113 add_reg(EDMR); 2114 add_reg(EDTRR); 2115 add_reg(EDRRR); 2116 add_reg(EESR); 2117 add_reg(EESIPR); 2118 add_reg(TDLAR); 2119 add_reg(TDFAR); 2120 add_reg(TDFXR); 2121 add_reg(TDFFR); 2122 add_reg(RDLAR); 2123 add_reg(RDFAR); 2124 add_reg(RDFXR); 2125 add_reg(RDFFR); 2126 add_reg(TRSCER); 2127 add_reg(RMFCR); 2128 add_reg(TFTR); 2129 add_reg(FDR); 2130 add_reg(RMCR); 2131 add_reg(TFUCR); 2132 add_reg(RFOCR); 2133 if (cd->rmiimode) 2134 add_reg(RMIIMODE); 2135 add_reg(FCFTR); 2136 if (cd->rpadir) 2137 add_reg(RPADIR); 2138 if (!cd->no_trimd) 2139 add_reg(TRIMD); 2140 add_reg(ECMR); 2141 add_reg(ECSR); 2142 add_reg(ECSIPR); 2143 add_reg(PIR); 2144 if (!cd->no_psr) 2145 add_reg(PSR); 2146 add_reg(RDMLR); 2147 add_reg(RFLR); 2148 add_reg(IPGR); 2149 if (cd->apr) 2150 add_reg(APR); 2151 if (cd->mpr) 2152 add_reg(MPR); 2153 add_reg(RFCR); 2154 add_reg(RFCF); 2155 if (cd->tpauser) 2156 add_reg(TPAUSER); 2157 add_reg(TPAUSECR); 2158 add_reg(GECMR); 2159 if (cd->bculr) 2160 add_reg(BCULR); 2161 add_reg(MAHR); 2162 add_reg(MALR); 2163 add_reg(TROCR); 2164 add_reg(CDCR); 2165 add_reg(LCCR); 2166 add_reg(CNDCR); 2167 add_reg(CEFCR); 2168 add_reg(FRECR); 2169 add_reg(TSFRCR); 2170 add_reg(TLFRCR); 2171 add_reg(CERCR); 2172 add_reg(CEECR); 2173 add_reg(MAFCR); 2174 if (cd->rtrate) 2175 add_reg(RTRATE); 2176 if (cd->hw_checksum) 2177 add_reg(CSMR); 2178 if (cd->select_mii) 2179 add_reg(RMII_MII); 2180 if (cd->tsu) { 2181 add_tsu_reg(ARSTR); 2182 add_tsu_reg(TSU_CTRST); 2183 add_tsu_reg(TSU_FWEN0); 2184 add_tsu_reg(TSU_FWEN1); 2185 add_tsu_reg(TSU_FCM); 2186 add_tsu_reg(TSU_BSYSL0); 2187 add_tsu_reg(TSU_BSYSL1); 2188 add_tsu_reg(TSU_PRISL0); 2189 add_tsu_reg(TSU_PRISL1); 2190 add_tsu_reg(TSU_FWSL0); 2191 add_tsu_reg(TSU_FWSL1); 2192 add_tsu_reg(TSU_FWSLC); 2193 add_tsu_reg(TSU_QTAGM0); 2194 add_tsu_reg(TSU_QTAGM1); 2195 add_tsu_reg(TSU_FWSR); 2196 add_tsu_reg(TSU_FWINMK); 2197 add_tsu_reg(TSU_ADQT0); 2198 add_tsu_reg(TSU_ADQT1); 2199 add_tsu_reg(TSU_VTAG0); 2200 add_tsu_reg(TSU_VTAG1); 2201 add_tsu_reg(TSU_ADSBSY); 2202 add_tsu_reg(TSU_TEN); 2203 add_tsu_reg(TSU_POST1); 2204 add_tsu_reg(TSU_POST2); 2205 add_tsu_reg(TSU_POST3); 2206 add_tsu_reg(TSU_POST4); 2207 /* This is the start of a table, not just a single register. */ 2208 if (buf) { 2209 unsigned int i; 2210 2211 mark_reg_valid(TSU_ADRH0); 2212 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2213 *buf++ = ioread32(mdp->tsu_addr + 2214 mdp->reg_offset[TSU_ADRH0] + 2215 i * 4); 2216 } 2217 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2218 } 2219 2220 #undef mark_reg_valid 2221 #undef add_reg_from 2222 #undef add_reg 2223 #undef add_tsu_reg 2224 2225 return len * 4; 2226 } 2227 2228 static int sh_eth_get_regs_len(struct net_device *ndev) 2229 { 2230 return __sh_eth_get_regs(ndev, NULL); 2231 } 2232 2233 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2234 void *buf) 2235 { 2236 struct sh_eth_private *mdp = netdev_priv(ndev); 2237 2238 regs->version = SH_ETH_REG_DUMP_VERSION; 2239 2240 pm_runtime_get_sync(&mdp->pdev->dev); 2241 __sh_eth_get_regs(ndev, buf); 2242 pm_runtime_put_sync(&mdp->pdev->dev); 2243 } 2244 2245 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2246 { 2247 struct sh_eth_private *mdp = netdev_priv(ndev); 2248 return mdp->msg_enable; 2249 } 2250 2251 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2252 { 2253 struct sh_eth_private *mdp = netdev_priv(ndev); 2254 mdp->msg_enable = value; 2255 } 2256 2257 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2258 "rx_current", "tx_current", 2259 "rx_dirty", "tx_dirty", 2260 }; 2261 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2262 2263 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2264 { 2265 switch (sset) { 2266 case ETH_SS_STATS: 2267 return SH_ETH_STATS_LEN; 2268 default: 2269 return -EOPNOTSUPP; 2270 } 2271 } 2272 2273 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2274 struct ethtool_stats *stats, u64 *data) 2275 { 2276 struct sh_eth_private *mdp = netdev_priv(ndev); 2277 int i = 0; 2278 2279 /* device-specific stats */ 2280 data[i++] = mdp->cur_rx; 2281 data[i++] = mdp->cur_tx; 2282 data[i++] = mdp->dirty_rx; 2283 data[i++] = mdp->dirty_tx; 2284 } 2285 2286 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2287 { 2288 switch (stringset) { 2289 case ETH_SS_STATS: 2290 memcpy(data, *sh_eth_gstrings_stats, 2291 sizeof(sh_eth_gstrings_stats)); 2292 break; 2293 } 2294 } 2295 2296 static void sh_eth_get_ringparam(struct net_device *ndev, 2297 struct ethtool_ringparam *ring) 2298 { 2299 struct sh_eth_private *mdp = netdev_priv(ndev); 2300 2301 ring->rx_max_pending = RX_RING_MAX; 2302 ring->tx_max_pending = TX_RING_MAX; 2303 ring->rx_pending = mdp->num_rx_ring; 2304 ring->tx_pending = mdp->num_tx_ring; 2305 } 2306 2307 static int sh_eth_set_ringparam(struct net_device *ndev, 2308 struct ethtool_ringparam *ring) 2309 { 2310 struct sh_eth_private *mdp = netdev_priv(ndev); 2311 int ret; 2312 2313 if (ring->tx_pending > TX_RING_MAX || 2314 ring->rx_pending > RX_RING_MAX || 2315 ring->tx_pending < TX_RING_MIN || 2316 ring->rx_pending < RX_RING_MIN) 2317 return -EINVAL; 2318 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2319 return -EINVAL; 2320 2321 if (netif_running(ndev)) { 2322 netif_device_detach(ndev); 2323 netif_tx_disable(ndev); 2324 2325 /* Serialise with the interrupt handler and NAPI, then 2326 * disable interrupts. We have to clear the 2327 * irq_enabled flag first to ensure that interrupts 2328 * won't be re-enabled. 2329 */ 2330 mdp->irq_enabled = false; 2331 synchronize_irq(ndev->irq); 2332 napi_synchronize(&mdp->napi); 2333 sh_eth_write(ndev, 0x0000, EESIPR); 2334 2335 sh_eth_dev_exit(ndev); 2336 2337 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2338 sh_eth_ring_free(ndev); 2339 } 2340 2341 /* Set new parameters */ 2342 mdp->num_rx_ring = ring->rx_pending; 2343 mdp->num_tx_ring = ring->tx_pending; 2344 2345 if (netif_running(ndev)) { 2346 ret = sh_eth_ring_init(ndev); 2347 if (ret < 0) { 2348 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2349 __func__); 2350 return ret; 2351 } 2352 ret = sh_eth_dev_init(ndev); 2353 if (ret < 0) { 2354 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2355 __func__); 2356 return ret; 2357 } 2358 2359 netif_device_attach(ndev); 2360 } 2361 2362 return 0; 2363 } 2364 2365 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2366 { 2367 struct sh_eth_private *mdp = netdev_priv(ndev); 2368 2369 wol->supported = 0; 2370 wol->wolopts = 0; 2371 2372 if (mdp->cd->magic) { 2373 wol->supported = WAKE_MAGIC; 2374 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2375 } 2376 } 2377 2378 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2379 { 2380 struct sh_eth_private *mdp = netdev_priv(ndev); 2381 2382 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC) 2383 return -EOPNOTSUPP; 2384 2385 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2386 2387 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2388 2389 return 0; 2390 } 2391 2392 static const struct ethtool_ops sh_eth_ethtool_ops = { 2393 .get_regs_len = sh_eth_get_regs_len, 2394 .get_regs = sh_eth_get_regs, 2395 .nway_reset = phy_ethtool_nway_reset, 2396 .get_msglevel = sh_eth_get_msglevel, 2397 .set_msglevel = sh_eth_set_msglevel, 2398 .get_link = ethtool_op_get_link, 2399 .get_strings = sh_eth_get_strings, 2400 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2401 .get_sset_count = sh_eth_get_sset_count, 2402 .get_ringparam = sh_eth_get_ringparam, 2403 .set_ringparam = sh_eth_set_ringparam, 2404 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2405 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2406 .get_wol = sh_eth_get_wol, 2407 .set_wol = sh_eth_set_wol, 2408 }; 2409 2410 /* network device open function */ 2411 static int sh_eth_open(struct net_device *ndev) 2412 { 2413 struct sh_eth_private *mdp = netdev_priv(ndev); 2414 int ret; 2415 2416 pm_runtime_get_sync(&mdp->pdev->dev); 2417 2418 napi_enable(&mdp->napi); 2419 2420 ret = request_irq(ndev->irq, sh_eth_interrupt, 2421 mdp->cd->irq_flags, ndev->name, ndev); 2422 if (ret) { 2423 netdev_err(ndev, "Can not assign IRQ number\n"); 2424 goto out_napi_off; 2425 } 2426 2427 /* Descriptor set */ 2428 ret = sh_eth_ring_init(ndev); 2429 if (ret) 2430 goto out_free_irq; 2431 2432 /* device init */ 2433 ret = sh_eth_dev_init(ndev); 2434 if (ret) 2435 goto out_free_irq; 2436 2437 /* PHY control start*/ 2438 ret = sh_eth_phy_start(ndev); 2439 if (ret) 2440 goto out_free_irq; 2441 2442 netif_start_queue(ndev); 2443 2444 mdp->is_opened = 1; 2445 2446 return ret; 2447 2448 out_free_irq: 2449 free_irq(ndev->irq, ndev); 2450 out_napi_off: 2451 napi_disable(&mdp->napi); 2452 pm_runtime_put_sync(&mdp->pdev->dev); 2453 return ret; 2454 } 2455 2456 /* Timeout function */ 2457 static void sh_eth_tx_timeout(struct net_device *ndev) 2458 { 2459 struct sh_eth_private *mdp = netdev_priv(ndev); 2460 struct sh_eth_rxdesc *rxdesc; 2461 int i; 2462 2463 netif_stop_queue(ndev); 2464 2465 netif_err(mdp, timer, ndev, 2466 "transmit timed out, status %8.8x, resetting...\n", 2467 sh_eth_read(ndev, EESR)); 2468 2469 /* tx_errors count up */ 2470 ndev->stats.tx_errors++; 2471 2472 /* Free all the skbuffs in the Rx queue. */ 2473 for (i = 0; i < mdp->num_rx_ring; i++) { 2474 rxdesc = &mdp->rx_ring[i]; 2475 rxdesc->status = cpu_to_le32(0); 2476 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2477 dev_kfree_skb(mdp->rx_skbuff[i]); 2478 mdp->rx_skbuff[i] = NULL; 2479 } 2480 for (i = 0; i < mdp->num_tx_ring; i++) { 2481 dev_kfree_skb(mdp->tx_skbuff[i]); 2482 mdp->tx_skbuff[i] = NULL; 2483 } 2484 2485 /* device init */ 2486 sh_eth_dev_init(ndev); 2487 2488 netif_start_queue(ndev); 2489 } 2490 2491 /* Packet transmit function */ 2492 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2493 { 2494 struct sh_eth_private *mdp = netdev_priv(ndev); 2495 struct sh_eth_txdesc *txdesc; 2496 dma_addr_t dma_addr; 2497 u32 entry; 2498 unsigned long flags; 2499 2500 spin_lock_irqsave(&mdp->lock, flags); 2501 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2502 if (!sh_eth_tx_free(ndev, true)) { 2503 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2504 netif_stop_queue(ndev); 2505 spin_unlock_irqrestore(&mdp->lock, flags); 2506 return NETDEV_TX_BUSY; 2507 } 2508 } 2509 spin_unlock_irqrestore(&mdp->lock, flags); 2510 2511 if (skb_put_padto(skb, ETH_ZLEN)) 2512 return NETDEV_TX_OK; 2513 2514 entry = mdp->cur_tx % mdp->num_tx_ring; 2515 mdp->tx_skbuff[entry] = skb; 2516 txdesc = &mdp->tx_ring[entry]; 2517 /* soft swap. */ 2518 if (!mdp->cd->hw_swap) 2519 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2520 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, 2521 DMA_TO_DEVICE); 2522 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 2523 kfree_skb(skb); 2524 return NETDEV_TX_OK; 2525 } 2526 txdesc->addr = cpu_to_le32(dma_addr); 2527 txdesc->len = cpu_to_le32(skb->len << 16); 2528 2529 dma_wmb(); /* TACT bit must be set after all the above writes */ 2530 if (entry >= mdp->num_tx_ring - 1) 2531 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2532 else 2533 txdesc->status |= cpu_to_le32(TD_TACT); 2534 2535 mdp->cur_tx++; 2536 2537 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns)) 2538 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 2539 2540 return NETDEV_TX_OK; 2541 } 2542 2543 /* The statistics registers have write-clear behaviour, which means we 2544 * will lose any increment between the read and write. We mitigate 2545 * this by only clearing when we read a non-zero value, so we will 2546 * never falsely report a total of zero. 2547 */ 2548 static void 2549 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2550 { 2551 u32 delta = sh_eth_read(ndev, reg); 2552 2553 if (delta) { 2554 *stat += delta; 2555 sh_eth_write(ndev, 0, reg); 2556 } 2557 } 2558 2559 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2560 { 2561 struct sh_eth_private *mdp = netdev_priv(ndev); 2562 2563 if (mdp->cd->no_tx_cntrs) 2564 return &ndev->stats; 2565 2566 if (!mdp->is_opened) 2567 return &ndev->stats; 2568 2569 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2570 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2571 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2572 2573 if (mdp->cd->cexcr) { 2574 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2575 CERCR); 2576 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2577 CEECR); 2578 } else { 2579 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2580 CNDCR); 2581 } 2582 2583 return &ndev->stats; 2584 } 2585 2586 /* device close function */ 2587 static int sh_eth_close(struct net_device *ndev) 2588 { 2589 struct sh_eth_private *mdp = netdev_priv(ndev); 2590 2591 netif_stop_queue(ndev); 2592 2593 /* Serialise with the interrupt handler and NAPI, then disable 2594 * interrupts. We have to clear the irq_enabled flag first to 2595 * ensure that interrupts won't be re-enabled. 2596 */ 2597 mdp->irq_enabled = false; 2598 synchronize_irq(ndev->irq); 2599 napi_disable(&mdp->napi); 2600 sh_eth_write(ndev, 0x0000, EESIPR); 2601 2602 sh_eth_dev_exit(ndev); 2603 2604 /* PHY Disconnect */ 2605 if (ndev->phydev) { 2606 phy_stop(ndev->phydev); 2607 phy_disconnect(ndev->phydev); 2608 } 2609 2610 free_irq(ndev->irq, ndev); 2611 2612 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2613 sh_eth_ring_free(ndev); 2614 2615 pm_runtime_put_sync(&mdp->pdev->dev); 2616 2617 mdp->is_opened = 0; 2618 2619 return 0; 2620 } 2621 2622 /* ioctl to device function */ 2623 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2624 { 2625 struct phy_device *phydev = ndev->phydev; 2626 2627 if (!netif_running(ndev)) 2628 return -EINVAL; 2629 2630 if (!phydev) 2631 return -ENODEV; 2632 2633 return phy_mii_ioctl(phydev, rq, cmd); 2634 } 2635 2636 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) 2637 { 2638 if (netif_running(ndev)) 2639 return -EBUSY; 2640 2641 ndev->mtu = new_mtu; 2642 netdev_update_features(ndev); 2643 2644 return 0; 2645 } 2646 2647 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2648 static u32 sh_eth_tsu_get_post_mask(int entry) 2649 { 2650 return 0x0f << (28 - ((entry % 8) * 4)); 2651 } 2652 2653 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2654 { 2655 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2656 } 2657 2658 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2659 int entry) 2660 { 2661 struct sh_eth_private *mdp = netdev_priv(ndev); 2662 int reg = TSU_POST1 + entry / 8; 2663 u32 tmp; 2664 2665 tmp = sh_eth_tsu_read(mdp, reg); 2666 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg); 2667 } 2668 2669 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2670 int entry) 2671 { 2672 struct sh_eth_private *mdp = netdev_priv(ndev); 2673 int reg = TSU_POST1 + entry / 8; 2674 u32 post_mask, ref_mask, tmp; 2675 2676 post_mask = sh_eth_tsu_get_post_mask(entry); 2677 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2678 2679 tmp = sh_eth_tsu_read(mdp, reg); 2680 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg); 2681 2682 /* If other port enables, the function returns "true" */ 2683 return tmp & ref_mask; 2684 } 2685 2686 static int sh_eth_tsu_busy(struct net_device *ndev) 2687 { 2688 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2689 struct sh_eth_private *mdp = netdev_priv(ndev); 2690 2691 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2692 udelay(10); 2693 timeout--; 2694 if (timeout <= 0) { 2695 netdev_err(ndev, "%s: timeout\n", __func__); 2696 return -ETIMEDOUT; 2697 } 2698 } 2699 2700 return 0; 2701 } 2702 2703 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset, 2704 const u8 *addr) 2705 { 2706 struct sh_eth_private *mdp = netdev_priv(ndev); 2707 u32 val; 2708 2709 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2710 iowrite32(val, mdp->tsu_addr + offset); 2711 if (sh_eth_tsu_busy(ndev) < 0) 2712 return -EBUSY; 2713 2714 val = addr[4] << 8 | addr[5]; 2715 iowrite32(val, mdp->tsu_addr + offset + 4); 2716 if (sh_eth_tsu_busy(ndev) < 0) 2717 return -EBUSY; 2718 2719 return 0; 2720 } 2721 2722 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr) 2723 { 2724 struct sh_eth_private *mdp = netdev_priv(ndev); 2725 u32 val; 2726 2727 val = ioread32(mdp->tsu_addr + offset); 2728 addr[0] = (val >> 24) & 0xff; 2729 addr[1] = (val >> 16) & 0xff; 2730 addr[2] = (val >> 8) & 0xff; 2731 addr[3] = val & 0xff; 2732 val = ioread32(mdp->tsu_addr + offset + 4); 2733 addr[4] = (val >> 8) & 0xff; 2734 addr[5] = val & 0xff; 2735 } 2736 2737 2738 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2739 { 2740 struct sh_eth_private *mdp = netdev_priv(ndev); 2741 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2742 int i; 2743 u8 c_addr[ETH_ALEN]; 2744 2745 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2746 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr); 2747 if (ether_addr_equal(addr, c_addr)) 2748 return i; 2749 } 2750 2751 return -ENOENT; 2752 } 2753 2754 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2755 { 2756 u8 blank[ETH_ALEN]; 2757 int entry; 2758 2759 memset(blank, 0, sizeof(blank)); 2760 entry = sh_eth_tsu_find_entry(ndev, blank); 2761 return (entry < 0) ? -ENOMEM : entry; 2762 } 2763 2764 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2765 int entry) 2766 { 2767 struct sh_eth_private *mdp = netdev_priv(ndev); 2768 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2769 int ret; 2770 u8 blank[ETH_ALEN]; 2771 2772 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2773 ~(1 << (31 - entry)), TSU_TEN); 2774 2775 memset(blank, 0, sizeof(blank)); 2776 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2777 if (ret < 0) 2778 return ret; 2779 return 0; 2780 } 2781 2782 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2783 { 2784 struct sh_eth_private *mdp = netdev_priv(ndev); 2785 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2786 int i, ret; 2787 2788 if (!mdp->cd->tsu) 2789 return 0; 2790 2791 i = sh_eth_tsu_find_entry(ndev, addr); 2792 if (i < 0) { 2793 /* No entry found, create one */ 2794 i = sh_eth_tsu_find_empty(ndev); 2795 if (i < 0) 2796 return -ENOMEM; 2797 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2798 if (ret < 0) 2799 return ret; 2800 2801 /* Enable the entry */ 2802 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2803 (1 << (31 - i)), TSU_TEN); 2804 } 2805 2806 /* Entry found or created, enable POST */ 2807 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2808 2809 return 0; 2810 } 2811 2812 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2813 { 2814 struct sh_eth_private *mdp = netdev_priv(ndev); 2815 int i, ret; 2816 2817 if (!mdp->cd->tsu) 2818 return 0; 2819 2820 i = sh_eth_tsu_find_entry(ndev, addr); 2821 if (i) { 2822 /* Entry found */ 2823 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2824 goto done; 2825 2826 /* Disable the entry if both ports was disabled */ 2827 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2828 if (ret < 0) 2829 return ret; 2830 } 2831 done: 2832 return 0; 2833 } 2834 2835 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2836 { 2837 struct sh_eth_private *mdp = netdev_priv(ndev); 2838 int i, ret; 2839 2840 if (!mdp->cd->tsu) 2841 return 0; 2842 2843 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2844 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2845 continue; 2846 2847 /* Disable the entry if both ports was disabled */ 2848 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2849 if (ret < 0) 2850 return ret; 2851 } 2852 2853 return 0; 2854 } 2855 2856 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2857 { 2858 struct sh_eth_private *mdp = netdev_priv(ndev); 2859 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2860 u8 addr[ETH_ALEN]; 2861 int i; 2862 2863 if (!mdp->cd->tsu) 2864 return; 2865 2866 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2867 sh_eth_tsu_read_entry(ndev, reg_offset, addr); 2868 if (is_multicast_ether_addr(addr)) 2869 sh_eth_tsu_del_entry(ndev, addr); 2870 } 2871 } 2872 2873 /* Update promiscuous flag and multicast filter */ 2874 static void sh_eth_set_rx_mode(struct net_device *ndev) 2875 { 2876 struct sh_eth_private *mdp = netdev_priv(ndev); 2877 u32 ecmr_bits; 2878 int mcast_all = 0; 2879 unsigned long flags; 2880 2881 spin_lock_irqsave(&mdp->lock, flags); 2882 /* Initial condition is MCT = 1, PRM = 0. 2883 * Depending on ndev->flags, set PRM or clear MCT 2884 */ 2885 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2886 if (mdp->cd->tsu) 2887 ecmr_bits |= ECMR_MCT; 2888 2889 if (!(ndev->flags & IFF_MULTICAST)) { 2890 sh_eth_tsu_purge_mcast(ndev); 2891 mcast_all = 1; 2892 } 2893 if (ndev->flags & IFF_ALLMULTI) { 2894 sh_eth_tsu_purge_mcast(ndev); 2895 ecmr_bits &= ~ECMR_MCT; 2896 mcast_all = 1; 2897 } 2898 2899 if (ndev->flags & IFF_PROMISC) { 2900 sh_eth_tsu_purge_all(ndev); 2901 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2902 } else if (mdp->cd->tsu) { 2903 struct netdev_hw_addr *ha; 2904 netdev_for_each_mc_addr(ha, ndev) { 2905 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2906 continue; 2907 2908 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2909 if (!mcast_all) { 2910 sh_eth_tsu_purge_mcast(ndev); 2911 ecmr_bits &= ~ECMR_MCT; 2912 mcast_all = 1; 2913 } 2914 } 2915 } 2916 } 2917 2918 /* update the ethernet mode */ 2919 sh_eth_write(ndev, ecmr_bits, ECMR); 2920 2921 spin_unlock_irqrestore(&mdp->lock, flags); 2922 } 2923 2924 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2925 { 2926 if (!mdp->port) 2927 return TSU_VTAG0; 2928 else 2929 return TSU_VTAG1; 2930 } 2931 2932 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2933 __be16 proto, u16 vid) 2934 { 2935 struct sh_eth_private *mdp = netdev_priv(ndev); 2936 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2937 2938 if (unlikely(!mdp->cd->tsu)) 2939 return -EPERM; 2940 2941 /* No filtering if vid = 0 */ 2942 if (!vid) 2943 return 0; 2944 2945 mdp->vlan_num_ids++; 2946 2947 /* The controller has one VLAN tag HW filter. So, if the filter is 2948 * already enabled, the driver disables it and the filte 2949 */ 2950 if (mdp->vlan_num_ids > 1) { 2951 /* disable VLAN filter */ 2952 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2953 return 0; 2954 } 2955 2956 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2957 vtag_reg_index); 2958 2959 return 0; 2960 } 2961 2962 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2963 __be16 proto, u16 vid) 2964 { 2965 struct sh_eth_private *mdp = netdev_priv(ndev); 2966 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2967 2968 if (unlikely(!mdp->cd->tsu)) 2969 return -EPERM; 2970 2971 /* No filtering if vid = 0 */ 2972 if (!vid) 2973 return 0; 2974 2975 mdp->vlan_num_ids--; 2976 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2977 2978 return 0; 2979 } 2980 2981 /* SuperH's TSU register init function */ 2982 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2983 { 2984 if (!mdp->cd->dual_port) { 2985 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2986 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 2987 TSU_FWSLC); /* Enable POST registers */ 2988 return; 2989 } 2990 2991 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2992 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2993 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2994 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2995 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2996 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2997 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2998 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2999 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 3000 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 3001 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 3002 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 3003 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 3004 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 3005 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3006 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 3007 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 3008 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 3009 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 3010 } 3011 3012 /* MDIO bus release function */ 3013 static int sh_mdio_release(struct sh_eth_private *mdp) 3014 { 3015 /* unregister mdio bus */ 3016 mdiobus_unregister(mdp->mii_bus); 3017 3018 /* free bitbang info */ 3019 free_mdio_bitbang(mdp->mii_bus); 3020 3021 return 0; 3022 } 3023 3024 /* MDIO bus init function */ 3025 static int sh_mdio_init(struct sh_eth_private *mdp, 3026 struct sh_eth_plat_data *pd) 3027 { 3028 int ret; 3029 struct bb_info *bitbang; 3030 struct platform_device *pdev = mdp->pdev; 3031 struct device *dev = &mdp->pdev->dev; 3032 3033 /* create bit control struct for PHY */ 3034 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 3035 if (!bitbang) 3036 return -ENOMEM; 3037 3038 /* bitbang init */ 3039 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 3040 bitbang->set_gate = pd->set_mdio_gate; 3041 bitbang->ctrl.ops = &bb_ops; 3042 3043 /* MII controller setting */ 3044 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 3045 if (!mdp->mii_bus) 3046 return -ENOMEM; 3047 3048 /* Hook up MII support for ethtool */ 3049 mdp->mii_bus->name = "sh_mii"; 3050 mdp->mii_bus->parent = dev; 3051 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 3052 pdev->name, pdev->id); 3053 3054 /* register MDIO bus */ 3055 if (pd->phy_irq > 0) 3056 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 3057 3058 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 3059 if (ret) 3060 goto out_free_bus; 3061 3062 return 0; 3063 3064 out_free_bus: 3065 free_mdio_bitbang(mdp->mii_bus); 3066 return ret; 3067 } 3068 3069 static const u16 *sh_eth_get_register_offset(int register_type) 3070 { 3071 const u16 *reg_offset = NULL; 3072 3073 switch (register_type) { 3074 case SH_ETH_REG_GIGABIT: 3075 reg_offset = sh_eth_offset_gigabit; 3076 break; 3077 case SH_ETH_REG_FAST_RZ: 3078 reg_offset = sh_eth_offset_fast_rz; 3079 break; 3080 case SH_ETH_REG_FAST_RCAR: 3081 reg_offset = sh_eth_offset_fast_rcar; 3082 break; 3083 case SH_ETH_REG_FAST_SH4: 3084 reg_offset = sh_eth_offset_fast_sh4; 3085 break; 3086 case SH_ETH_REG_FAST_SH3_SH2: 3087 reg_offset = sh_eth_offset_fast_sh3_sh2; 3088 break; 3089 } 3090 3091 return reg_offset; 3092 } 3093 3094 static const struct net_device_ops sh_eth_netdev_ops = { 3095 .ndo_open = sh_eth_open, 3096 .ndo_stop = sh_eth_close, 3097 .ndo_start_xmit = sh_eth_start_xmit, 3098 .ndo_get_stats = sh_eth_get_stats, 3099 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3100 .ndo_tx_timeout = sh_eth_tx_timeout, 3101 .ndo_do_ioctl = sh_eth_do_ioctl, 3102 .ndo_change_mtu = sh_eth_change_mtu, 3103 .ndo_validate_addr = eth_validate_addr, 3104 .ndo_set_mac_address = eth_mac_addr, 3105 }; 3106 3107 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3108 .ndo_open = sh_eth_open, 3109 .ndo_stop = sh_eth_close, 3110 .ndo_start_xmit = sh_eth_start_xmit, 3111 .ndo_get_stats = sh_eth_get_stats, 3112 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3113 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3114 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3115 .ndo_tx_timeout = sh_eth_tx_timeout, 3116 .ndo_do_ioctl = sh_eth_do_ioctl, 3117 .ndo_change_mtu = sh_eth_change_mtu, 3118 .ndo_validate_addr = eth_validate_addr, 3119 .ndo_set_mac_address = eth_mac_addr, 3120 }; 3121 3122 #ifdef CONFIG_OF 3123 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3124 { 3125 struct device_node *np = dev->of_node; 3126 struct sh_eth_plat_data *pdata; 3127 const char *mac_addr; 3128 3129 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3130 if (!pdata) 3131 return NULL; 3132 3133 pdata->phy_interface = of_get_phy_mode(np); 3134 3135 mac_addr = of_get_mac_address(np); 3136 if (mac_addr) 3137 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 3138 3139 pdata->no_ether_link = 3140 of_property_read_bool(np, "renesas,no-ether-link"); 3141 pdata->ether_link_active_low = 3142 of_property_read_bool(np, "renesas,ether-link-active-low"); 3143 3144 return pdata; 3145 } 3146 3147 static const struct of_device_id sh_eth_match_table[] = { 3148 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3149 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data }, 3150 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data }, 3151 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data }, 3152 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data }, 3153 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data }, 3154 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data }, 3155 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data }, 3156 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data }, 3157 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data }, 3158 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3159 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data }, 3160 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data }, 3161 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data }, 3162 { } 3163 }; 3164 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3165 #else 3166 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3167 { 3168 return NULL; 3169 } 3170 #endif 3171 3172 static int sh_eth_drv_probe(struct platform_device *pdev) 3173 { 3174 struct resource *res; 3175 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3176 const struct platform_device_id *id = platform_get_device_id(pdev); 3177 struct sh_eth_private *mdp; 3178 struct net_device *ndev; 3179 int ret; 3180 3181 /* get base addr */ 3182 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3183 3184 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3185 if (!ndev) 3186 return -ENOMEM; 3187 3188 pm_runtime_enable(&pdev->dev); 3189 pm_runtime_get_sync(&pdev->dev); 3190 3191 ret = platform_get_irq(pdev, 0); 3192 if (ret < 0) 3193 goto out_release; 3194 ndev->irq = ret; 3195 3196 SET_NETDEV_DEV(ndev, &pdev->dev); 3197 3198 mdp = netdev_priv(ndev); 3199 mdp->num_tx_ring = TX_RING_SIZE; 3200 mdp->num_rx_ring = RX_RING_SIZE; 3201 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3202 if (IS_ERR(mdp->addr)) { 3203 ret = PTR_ERR(mdp->addr); 3204 goto out_release; 3205 } 3206 3207 ndev->base_addr = res->start; 3208 3209 spin_lock_init(&mdp->lock); 3210 mdp->pdev = pdev; 3211 3212 if (pdev->dev.of_node) 3213 pd = sh_eth_parse_dt(&pdev->dev); 3214 if (!pd) { 3215 dev_err(&pdev->dev, "no platform data\n"); 3216 ret = -EINVAL; 3217 goto out_release; 3218 } 3219 3220 /* get PHY ID */ 3221 mdp->phy_id = pd->phy; 3222 mdp->phy_interface = pd->phy_interface; 3223 mdp->no_ether_link = pd->no_ether_link; 3224 mdp->ether_link_active_low = pd->ether_link_active_low; 3225 3226 /* set cpu data */ 3227 if (id) 3228 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3229 else 3230 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3231 3232 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3233 if (!mdp->reg_offset) { 3234 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3235 mdp->cd->register_type); 3236 ret = -EINVAL; 3237 goto out_release; 3238 } 3239 sh_eth_set_default_cpu_data(mdp->cd); 3240 3241 /* User's manual states max MTU should be 2048 but due to the 3242 * alignment calculations in sh_eth_ring_init() the practical 3243 * MTU is a bit less. Maybe this can be optimized some more. 3244 */ 3245 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3246 ndev->min_mtu = ETH_MIN_MTU; 3247 3248 /* set function */ 3249 if (mdp->cd->tsu) 3250 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3251 else 3252 ndev->netdev_ops = &sh_eth_netdev_ops; 3253 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3254 ndev->watchdog_timeo = TX_TIMEOUT; 3255 3256 /* debug message level */ 3257 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3258 3259 /* read and set MAC address */ 3260 read_mac_address(ndev, pd->mac_addr); 3261 if (!is_valid_ether_addr(ndev->dev_addr)) { 3262 dev_warn(&pdev->dev, 3263 "no valid MAC address supplied, using a random one.\n"); 3264 eth_hw_addr_random(ndev); 3265 } 3266 3267 if (mdp->cd->tsu) { 3268 int port = pdev->id < 0 ? 0 : pdev->id % 2; 3269 struct resource *rtsu; 3270 3271 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3272 if (!rtsu) { 3273 dev_err(&pdev->dev, "no TSU resource\n"); 3274 ret = -ENODEV; 3275 goto out_release; 3276 } 3277 /* We can only request the TSU region for the first port 3278 * of the two sharing this TSU for the probe to succeed... 3279 */ 3280 if (port == 0 && 3281 !devm_request_mem_region(&pdev->dev, rtsu->start, 3282 resource_size(rtsu), 3283 dev_name(&pdev->dev))) { 3284 dev_err(&pdev->dev, "can't request TSU resource.\n"); 3285 ret = -EBUSY; 3286 goto out_release; 3287 } 3288 /* ioremap the TSU registers */ 3289 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, 3290 resource_size(rtsu)); 3291 if (!mdp->tsu_addr) { 3292 dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); 3293 ret = -ENOMEM; 3294 goto out_release; 3295 } 3296 mdp->port = port; 3297 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 3298 3299 /* Need to init only the first port of the two sharing a TSU */ 3300 if (port == 0) { 3301 if (mdp->cd->chip_reset) 3302 mdp->cd->chip_reset(ndev); 3303 3304 /* TSU init (Init only)*/ 3305 sh_eth_tsu_init(mdp); 3306 } 3307 } 3308 3309 if (mdp->cd->rmiimode) 3310 sh_eth_write(ndev, 0x1, RMIIMODE); 3311 3312 /* MDIO bus init */ 3313 ret = sh_mdio_init(mdp, pd); 3314 if (ret) { 3315 if (ret != -EPROBE_DEFER) 3316 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret); 3317 goto out_release; 3318 } 3319 3320 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3321 3322 /* network device register */ 3323 ret = register_netdev(ndev); 3324 if (ret) 3325 goto out_napi_del; 3326 3327 if (mdp->cd->magic) 3328 device_set_wakeup_capable(&pdev->dev, 1); 3329 3330 /* print device information */ 3331 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3332 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3333 3334 pm_runtime_put(&pdev->dev); 3335 platform_set_drvdata(pdev, ndev); 3336 3337 return ret; 3338 3339 out_napi_del: 3340 netif_napi_del(&mdp->napi); 3341 sh_mdio_release(mdp); 3342 3343 out_release: 3344 /* net_dev free */ 3345 free_netdev(ndev); 3346 3347 pm_runtime_put(&pdev->dev); 3348 pm_runtime_disable(&pdev->dev); 3349 return ret; 3350 } 3351 3352 static int sh_eth_drv_remove(struct platform_device *pdev) 3353 { 3354 struct net_device *ndev = platform_get_drvdata(pdev); 3355 struct sh_eth_private *mdp = netdev_priv(ndev); 3356 3357 unregister_netdev(ndev); 3358 netif_napi_del(&mdp->napi); 3359 sh_mdio_release(mdp); 3360 pm_runtime_disable(&pdev->dev); 3361 free_netdev(ndev); 3362 3363 return 0; 3364 } 3365 3366 #ifdef CONFIG_PM 3367 #ifdef CONFIG_PM_SLEEP 3368 static int sh_eth_wol_setup(struct net_device *ndev) 3369 { 3370 struct sh_eth_private *mdp = netdev_priv(ndev); 3371 3372 /* Only allow ECI interrupts */ 3373 synchronize_irq(ndev->irq); 3374 napi_disable(&mdp->napi); 3375 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3376 3377 /* Enable MagicPacket */ 3378 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3379 3380 return enable_irq_wake(ndev->irq); 3381 } 3382 3383 static int sh_eth_wol_restore(struct net_device *ndev) 3384 { 3385 struct sh_eth_private *mdp = netdev_priv(ndev); 3386 int ret; 3387 3388 napi_enable(&mdp->napi); 3389 3390 /* Disable MagicPacket */ 3391 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3392 3393 /* The device needs to be reset to restore MagicPacket logic 3394 * for next wakeup. If we close and open the device it will 3395 * both be reset and all registers restored. This is what 3396 * happens during suspend and resume without WoL enabled. 3397 */ 3398 ret = sh_eth_close(ndev); 3399 if (ret < 0) 3400 return ret; 3401 ret = sh_eth_open(ndev); 3402 if (ret < 0) 3403 return ret; 3404 3405 return disable_irq_wake(ndev->irq); 3406 } 3407 3408 static int sh_eth_suspend(struct device *dev) 3409 { 3410 struct net_device *ndev = dev_get_drvdata(dev); 3411 struct sh_eth_private *mdp = netdev_priv(ndev); 3412 int ret = 0; 3413 3414 if (!netif_running(ndev)) 3415 return 0; 3416 3417 netif_device_detach(ndev); 3418 3419 if (mdp->wol_enabled) 3420 ret = sh_eth_wol_setup(ndev); 3421 else 3422 ret = sh_eth_close(ndev); 3423 3424 return ret; 3425 } 3426 3427 static int sh_eth_resume(struct device *dev) 3428 { 3429 struct net_device *ndev = dev_get_drvdata(dev); 3430 struct sh_eth_private *mdp = netdev_priv(ndev); 3431 int ret = 0; 3432 3433 if (!netif_running(ndev)) 3434 return 0; 3435 3436 if (mdp->wol_enabled) 3437 ret = sh_eth_wol_restore(ndev); 3438 else 3439 ret = sh_eth_open(ndev); 3440 3441 if (ret < 0) 3442 return ret; 3443 3444 netif_device_attach(ndev); 3445 3446 return ret; 3447 } 3448 #endif 3449 3450 static int sh_eth_runtime_nop(struct device *dev) 3451 { 3452 /* Runtime PM callback shared between ->runtime_suspend() 3453 * and ->runtime_resume(). Simply returns success. 3454 * 3455 * This driver re-initializes all registers after 3456 * pm_runtime_get_sync() anyway so there is no need 3457 * to save and restore registers here. 3458 */ 3459 return 0; 3460 } 3461 3462 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3463 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3464 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3465 }; 3466 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3467 #else 3468 #define SH_ETH_PM_OPS NULL 3469 #endif 3470 3471 static const struct platform_device_id sh_eth_id_table[] = { 3472 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3473 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3474 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3475 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3476 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3477 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3478 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3479 { } 3480 }; 3481 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3482 3483 static struct platform_driver sh_eth_driver = { 3484 .probe = sh_eth_drv_probe, 3485 .remove = sh_eth_drv_remove, 3486 .id_table = sh_eth_id_table, 3487 .driver = { 3488 .name = CARDNAME, 3489 .pm = SH_ETH_PM_OPS, 3490 .of_match_table = of_match_ptr(sh_eth_match_table), 3491 }, 3492 }; 3493 3494 module_platform_driver(sh_eth_driver); 3495 3496 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3497 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3498 MODULE_LICENSE("GPL v2"); 3499