1 /* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2014 Renesas Electronics Corporation 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2014 Renesas Solutions Corp. 6 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 7 * Copyright (C) 2014 Codethink Limited 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 */ 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/etherdevice.h> 28 #include <linux/delay.h> 29 #include <linux/platform_device.h> 30 #include <linux/mdio-bitbang.h> 31 #include <linux/netdevice.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_net.h> 36 #include <linux/phy.h> 37 #include <linux/cache.h> 38 #include <linux/io.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/slab.h> 41 #include <linux/ethtool.h> 42 #include <linux/if_vlan.h> 43 #include <linux/clk.h> 44 #include <linux/sh_eth.h> 45 #include <linux/of_mdio.h> 46 47 #include "sh_eth.h" 48 49 #define SH_ETH_DEF_MSG_ENABLE \ 50 (NETIF_MSG_LINK | \ 51 NETIF_MSG_TIMER | \ 52 NETIF_MSG_RX_ERR| \ 53 NETIF_MSG_TX_ERR) 54 55 #define SH_ETH_OFFSET_INVALID ((u16)~0) 56 57 #define SH_ETH_OFFSET_DEFAULTS \ 58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 59 60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 61 SH_ETH_OFFSET_DEFAULTS, 62 63 [EDSR] = 0x0000, 64 [EDMR] = 0x0400, 65 [EDTRR] = 0x0408, 66 [EDRRR] = 0x0410, 67 [EESR] = 0x0428, 68 [EESIPR] = 0x0430, 69 [TDLAR] = 0x0010, 70 [TDFAR] = 0x0014, 71 [TDFXR] = 0x0018, 72 [TDFFR] = 0x001c, 73 [RDLAR] = 0x0030, 74 [RDFAR] = 0x0034, 75 [RDFXR] = 0x0038, 76 [RDFFR] = 0x003c, 77 [TRSCER] = 0x0438, 78 [RMFCR] = 0x0440, 79 [TFTR] = 0x0448, 80 [FDR] = 0x0450, 81 [RMCR] = 0x0458, 82 [RPADIR] = 0x0460, 83 [FCFTR] = 0x0468, 84 [CSMR] = 0x04E4, 85 86 [ECMR] = 0x0500, 87 [ECSR] = 0x0510, 88 [ECSIPR] = 0x0518, 89 [PIR] = 0x0520, 90 [PSR] = 0x0528, 91 [PIPR] = 0x052c, 92 [RFLR] = 0x0508, 93 [APR] = 0x0554, 94 [MPR] = 0x0558, 95 [PFTCR] = 0x055c, 96 [PFRCR] = 0x0560, 97 [TPAUSER] = 0x0564, 98 [GECMR] = 0x05b0, 99 [BCULR] = 0x05b4, 100 [MAHR] = 0x05c0, 101 [MALR] = 0x05c8, 102 [TROCR] = 0x0700, 103 [CDCR] = 0x0708, 104 [LCCR] = 0x0710, 105 [CEFCR] = 0x0740, 106 [FRECR] = 0x0748, 107 [TSFRCR] = 0x0750, 108 [TLFRCR] = 0x0758, 109 [RFCR] = 0x0760, 110 [CERCR] = 0x0768, 111 [CEECR] = 0x0770, 112 [MAFCR] = 0x0778, 113 [RMII_MII] = 0x0790, 114 115 [ARSTR] = 0x0000, 116 [TSU_CTRST] = 0x0004, 117 [TSU_FWEN0] = 0x0010, 118 [TSU_FWEN1] = 0x0014, 119 [TSU_FCM] = 0x0018, 120 [TSU_BSYSL0] = 0x0020, 121 [TSU_BSYSL1] = 0x0024, 122 [TSU_PRISL0] = 0x0028, 123 [TSU_PRISL1] = 0x002c, 124 [TSU_FWSL0] = 0x0030, 125 [TSU_FWSL1] = 0x0034, 126 [TSU_FWSLC] = 0x0038, 127 [TSU_QTAG0] = 0x0040, 128 [TSU_QTAG1] = 0x0044, 129 [TSU_FWSR] = 0x0050, 130 [TSU_FWINMK] = 0x0054, 131 [TSU_ADQT0] = 0x0048, 132 [TSU_ADQT1] = 0x004c, 133 [TSU_VTAG0] = 0x0058, 134 [TSU_VTAG1] = 0x005c, 135 [TSU_ADSBSY] = 0x0060, 136 [TSU_TEN] = 0x0064, 137 [TSU_POST1] = 0x0070, 138 [TSU_POST2] = 0x0074, 139 [TSU_POST3] = 0x0078, 140 [TSU_POST4] = 0x007c, 141 [TSU_ADRH0] = 0x0100, 142 143 [TXNLCR0] = 0x0080, 144 [TXALCR0] = 0x0084, 145 [RXNLCR0] = 0x0088, 146 [RXALCR0] = 0x008c, 147 [FWNLCR0] = 0x0090, 148 [FWALCR0] = 0x0094, 149 [TXNLCR1] = 0x00a0, 150 [TXALCR1] = 0x00a0, 151 [RXNLCR1] = 0x00a8, 152 [RXALCR1] = 0x00ac, 153 [FWNLCR1] = 0x00b0, 154 [FWALCR1] = 0x00b4, 155 }; 156 157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 158 SH_ETH_OFFSET_DEFAULTS, 159 160 [EDSR] = 0x0000, 161 [EDMR] = 0x0400, 162 [EDTRR] = 0x0408, 163 [EDRRR] = 0x0410, 164 [EESR] = 0x0428, 165 [EESIPR] = 0x0430, 166 [TDLAR] = 0x0010, 167 [TDFAR] = 0x0014, 168 [TDFXR] = 0x0018, 169 [TDFFR] = 0x001c, 170 [RDLAR] = 0x0030, 171 [RDFAR] = 0x0034, 172 [RDFXR] = 0x0038, 173 [RDFFR] = 0x003c, 174 [TRSCER] = 0x0438, 175 [RMFCR] = 0x0440, 176 [TFTR] = 0x0448, 177 [FDR] = 0x0450, 178 [RMCR] = 0x0458, 179 [RPADIR] = 0x0460, 180 [FCFTR] = 0x0468, 181 [CSMR] = 0x04E4, 182 183 [ECMR] = 0x0500, 184 [RFLR] = 0x0508, 185 [ECSR] = 0x0510, 186 [ECSIPR] = 0x0518, 187 [PIR] = 0x0520, 188 [APR] = 0x0554, 189 [MPR] = 0x0558, 190 [PFTCR] = 0x055c, 191 [PFRCR] = 0x0560, 192 [TPAUSER] = 0x0564, 193 [MAHR] = 0x05c0, 194 [MALR] = 0x05c8, 195 [CEFCR] = 0x0740, 196 [FRECR] = 0x0748, 197 [TSFRCR] = 0x0750, 198 [TLFRCR] = 0x0758, 199 [RFCR] = 0x0760, 200 [MAFCR] = 0x0778, 201 202 [ARSTR] = 0x0000, 203 [TSU_CTRST] = 0x0004, 204 [TSU_FWSLC] = 0x0038, 205 [TSU_VTAG0] = 0x0058, 206 [TSU_ADSBSY] = 0x0060, 207 [TSU_TEN] = 0x0064, 208 [TSU_POST1] = 0x0070, 209 [TSU_POST2] = 0x0074, 210 [TSU_POST3] = 0x0078, 211 [TSU_POST4] = 0x007c, 212 [TSU_ADRH0] = 0x0100, 213 214 [TXNLCR0] = 0x0080, 215 [TXALCR0] = 0x0084, 216 [RXNLCR0] = 0x0088, 217 [RXALCR0] = 0x008C, 218 }; 219 220 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 221 SH_ETH_OFFSET_DEFAULTS, 222 223 [ECMR] = 0x0300, 224 [RFLR] = 0x0308, 225 [ECSR] = 0x0310, 226 [ECSIPR] = 0x0318, 227 [PIR] = 0x0320, 228 [PSR] = 0x0328, 229 [RDMLR] = 0x0340, 230 [IPGR] = 0x0350, 231 [APR] = 0x0354, 232 [MPR] = 0x0358, 233 [RFCF] = 0x0360, 234 [TPAUSER] = 0x0364, 235 [TPAUSECR] = 0x0368, 236 [MAHR] = 0x03c0, 237 [MALR] = 0x03c8, 238 [TROCR] = 0x03d0, 239 [CDCR] = 0x03d4, 240 [LCCR] = 0x03d8, 241 [CNDCR] = 0x03dc, 242 [CEFCR] = 0x03e4, 243 [FRECR] = 0x03e8, 244 [TSFRCR] = 0x03ec, 245 [TLFRCR] = 0x03f0, 246 [RFCR] = 0x03f4, 247 [MAFCR] = 0x03f8, 248 249 [EDMR] = 0x0200, 250 [EDTRR] = 0x0208, 251 [EDRRR] = 0x0210, 252 [TDLAR] = 0x0218, 253 [RDLAR] = 0x0220, 254 [EESR] = 0x0228, 255 [EESIPR] = 0x0230, 256 [TRSCER] = 0x0238, 257 [RMFCR] = 0x0240, 258 [TFTR] = 0x0248, 259 [FDR] = 0x0250, 260 [RMCR] = 0x0258, 261 [TFUCR] = 0x0264, 262 [RFOCR] = 0x0268, 263 [RMIIMODE] = 0x026c, 264 [FCFTR] = 0x0270, 265 [TRIMD] = 0x027c, 266 }; 267 268 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 269 SH_ETH_OFFSET_DEFAULTS, 270 271 [ECMR] = 0x0100, 272 [RFLR] = 0x0108, 273 [ECSR] = 0x0110, 274 [ECSIPR] = 0x0118, 275 [PIR] = 0x0120, 276 [PSR] = 0x0128, 277 [RDMLR] = 0x0140, 278 [IPGR] = 0x0150, 279 [APR] = 0x0154, 280 [MPR] = 0x0158, 281 [TPAUSER] = 0x0164, 282 [RFCF] = 0x0160, 283 [TPAUSECR] = 0x0168, 284 [BCFRR] = 0x016c, 285 [MAHR] = 0x01c0, 286 [MALR] = 0x01c8, 287 [TROCR] = 0x01d0, 288 [CDCR] = 0x01d4, 289 [LCCR] = 0x01d8, 290 [CNDCR] = 0x01dc, 291 [CEFCR] = 0x01e4, 292 [FRECR] = 0x01e8, 293 [TSFRCR] = 0x01ec, 294 [TLFRCR] = 0x01f0, 295 [RFCR] = 0x01f4, 296 [MAFCR] = 0x01f8, 297 [RTRATE] = 0x01fc, 298 299 [EDMR] = 0x0000, 300 [EDTRR] = 0x0008, 301 [EDRRR] = 0x0010, 302 [TDLAR] = 0x0018, 303 [RDLAR] = 0x0020, 304 [EESR] = 0x0028, 305 [EESIPR] = 0x0030, 306 [TRSCER] = 0x0038, 307 [RMFCR] = 0x0040, 308 [TFTR] = 0x0048, 309 [FDR] = 0x0050, 310 [RMCR] = 0x0058, 311 [TFUCR] = 0x0064, 312 [RFOCR] = 0x0068, 313 [FCFTR] = 0x0070, 314 [RPADIR] = 0x0078, 315 [TRIMD] = 0x007c, 316 [RBWAR] = 0x00c8, 317 [RDFAR] = 0x00cc, 318 [TBRAR] = 0x00d4, 319 [TDFAR] = 0x00d8, 320 }; 321 322 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 323 SH_ETH_OFFSET_DEFAULTS, 324 325 [EDMR] = 0x0000, 326 [EDTRR] = 0x0004, 327 [EDRRR] = 0x0008, 328 [TDLAR] = 0x000c, 329 [RDLAR] = 0x0010, 330 [EESR] = 0x0014, 331 [EESIPR] = 0x0018, 332 [TRSCER] = 0x001c, 333 [RMFCR] = 0x0020, 334 [TFTR] = 0x0024, 335 [FDR] = 0x0028, 336 [RMCR] = 0x002c, 337 [EDOCR] = 0x0030, 338 [FCFTR] = 0x0034, 339 [RPADIR] = 0x0038, 340 [TRIMD] = 0x003c, 341 [RBWAR] = 0x0040, 342 [RDFAR] = 0x0044, 343 [TBRAR] = 0x004c, 344 [TDFAR] = 0x0050, 345 346 [ECMR] = 0x0160, 347 [ECSR] = 0x0164, 348 [ECSIPR] = 0x0168, 349 [PIR] = 0x016c, 350 [MAHR] = 0x0170, 351 [MALR] = 0x0174, 352 [RFLR] = 0x0178, 353 [PSR] = 0x017c, 354 [TROCR] = 0x0180, 355 [CDCR] = 0x0184, 356 [LCCR] = 0x0188, 357 [CNDCR] = 0x018c, 358 [CEFCR] = 0x0194, 359 [FRECR] = 0x0198, 360 [TSFRCR] = 0x019c, 361 [TLFRCR] = 0x01a0, 362 [RFCR] = 0x01a4, 363 [MAFCR] = 0x01a8, 364 [IPGR] = 0x01b4, 365 [APR] = 0x01b8, 366 [MPR] = 0x01bc, 367 [TPAUSER] = 0x01c4, 368 [BCFR] = 0x01cc, 369 370 [ARSTR] = 0x0000, 371 [TSU_CTRST] = 0x0004, 372 [TSU_FWEN0] = 0x0010, 373 [TSU_FWEN1] = 0x0014, 374 [TSU_FCM] = 0x0018, 375 [TSU_BSYSL0] = 0x0020, 376 [TSU_BSYSL1] = 0x0024, 377 [TSU_PRISL0] = 0x0028, 378 [TSU_PRISL1] = 0x002c, 379 [TSU_FWSL0] = 0x0030, 380 [TSU_FWSL1] = 0x0034, 381 [TSU_FWSLC] = 0x0038, 382 [TSU_QTAGM0] = 0x0040, 383 [TSU_QTAGM1] = 0x0044, 384 [TSU_ADQT0] = 0x0048, 385 [TSU_ADQT1] = 0x004c, 386 [TSU_FWSR] = 0x0050, 387 [TSU_FWINMK] = 0x0054, 388 [TSU_ADSBSY] = 0x0060, 389 [TSU_TEN] = 0x0064, 390 [TSU_POST1] = 0x0070, 391 [TSU_POST2] = 0x0074, 392 [TSU_POST3] = 0x0078, 393 [TSU_POST4] = 0x007c, 394 395 [TXNLCR0] = 0x0080, 396 [TXALCR0] = 0x0084, 397 [RXNLCR0] = 0x0088, 398 [RXALCR0] = 0x008c, 399 [FWNLCR0] = 0x0090, 400 [FWALCR0] = 0x0094, 401 [TXNLCR1] = 0x00a0, 402 [TXALCR1] = 0x00a0, 403 [RXNLCR1] = 0x00a8, 404 [RXALCR1] = 0x00ac, 405 [FWNLCR1] = 0x00b0, 406 [FWALCR1] = 0x00b4, 407 408 [TSU_ADRH0] = 0x0100, 409 }; 410 411 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 412 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 413 414 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 415 { 416 struct sh_eth_private *mdp = netdev_priv(ndev); 417 u16 offset = mdp->reg_offset[enum_index]; 418 419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 420 return; 421 422 iowrite32(data, mdp->addr + offset); 423 } 424 425 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 426 { 427 struct sh_eth_private *mdp = netdev_priv(ndev); 428 u16 offset = mdp->reg_offset[enum_index]; 429 430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 431 return ~0U; 432 433 return ioread32(mdp->addr + offset); 434 } 435 436 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 437 u32 set) 438 { 439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 440 enum_index); 441 } 442 443 static bool sh_eth_is_gether(struct sh_eth_private *mdp) 444 { 445 return mdp->reg_offset == sh_eth_offset_gigabit; 446 } 447 448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp) 449 { 450 return mdp->reg_offset == sh_eth_offset_fast_rz; 451 } 452 453 static void sh_eth_select_mii(struct net_device *ndev) 454 { 455 struct sh_eth_private *mdp = netdev_priv(ndev); 456 u32 value; 457 458 switch (mdp->phy_interface) { 459 case PHY_INTERFACE_MODE_GMII: 460 value = 0x2; 461 break; 462 case PHY_INTERFACE_MODE_MII: 463 value = 0x1; 464 break; 465 case PHY_INTERFACE_MODE_RMII: 466 value = 0x0; 467 break; 468 default: 469 netdev_warn(ndev, 470 "PHY interface mode was not setup. Set to MII.\n"); 471 value = 0x1; 472 break; 473 } 474 475 sh_eth_write(ndev, value, RMII_MII); 476 } 477 478 static void sh_eth_set_duplex(struct net_device *ndev) 479 { 480 struct sh_eth_private *mdp = netdev_priv(ndev); 481 482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 483 } 484 485 static void sh_eth_chip_reset(struct net_device *ndev) 486 { 487 struct sh_eth_private *mdp = netdev_priv(ndev); 488 489 /* reset device */ 490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 491 mdelay(1); 492 } 493 494 static void sh_eth_set_rate_gether(struct net_device *ndev) 495 { 496 struct sh_eth_private *mdp = netdev_priv(ndev); 497 498 switch (mdp->speed) { 499 case 10: /* 10BASE */ 500 sh_eth_write(ndev, GECMR_10, GECMR); 501 break; 502 case 100:/* 100BASE */ 503 sh_eth_write(ndev, GECMR_100, GECMR); 504 break; 505 case 1000: /* 1000BASE */ 506 sh_eth_write(ndev, GECMR_1000, GECMR); 507 break; 508 } 509 } 510 511 #ifdef CONFIG_OF 512 /* R7S72100 */ 513 static struct sh_eth_cpu_data r7s72100_data = { 514 .chip_reset = sh_eth_chip_reset, 515 .set_duplex = sh_eth_set_duplex, 516 517 .register_type = SH_ETH_REG_FAST_RZ, 518 519 .ecsr_value = ECSR_ICD, 520 .ecsipr_value = ECSIPR_ICDIP, 521 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 522 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 523 EESIPR_ECIIP | 524 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 525 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 526 EESIPR_RMAFIP | EESIPR_RRFIP | 527 EESIPR_RTLFIP | EESIPR_RTSFIP | 528 EESIPR_PREIP | EESIPR_CERFIP, 529 530 .tx_check = EESR_TC1 | EESR_FTC, 531 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 532 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 533 EESR_TDE, 534 .fdr_value = 0x0000070f, 535 536 .no_psr = 1, 537 .apr = 1, 538 .mpr = 1, 539 .tpauser = 1, 540 .hw_swap = 1, 541 .rpadir = 1, 542 .rpadir_value = 2 << 16, 543 .no_trimd = 1, 544 .no_ade = 1, 545 .hw_checksum = 1, 546 .tsu = 1, 547 }; 548 549 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 550 { 551 sh_eth_chip_reset(ndev); 552 553 sh_eth_select_mii(ndev); 554 } 555 556 /* R8A7740 */ 557 static struct sh_eth_cpu_data r8a7740_data = { 558 .chip_reset = sh_eth_chip_reset_r8a7740, 559 .set_duplex = sh_eth_set_duplex, 560 .set_rate = sh_eth_set_rate_gether, 561 562 .register_type = SH_ETH_REG_GIGABIT, 563 564 .ecsr_value = ECSR_ICD | ECSR_MPD, 565 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 566 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 567 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 568 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 569 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 570 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 571 EESIPR_CEEFIP | EESIPR_CELFIP | 572 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 573 EESIPR_PREIP | EESIPR_CERFIP, 574 575 .tx_check = EESR_TC1 | EESR_FTC, 576 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 577 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 578 EESR_TDE, 579 .fdr_value = 0x0000070f, 580 581 .apr = 1, 582 .mpr = 1, 583 .tpauser = 1, 584 .bculr = 1, 585 .hw_swap = 1, 586 .rpadir = 1, 587 .rpadir_value = 2 << 16, 588 .no_trimd = 1, 589 .no_ade = 1, 590 .hw_checksum = 1, 591 .tsu = 1, 592 .select_mii = 1, 593 .magic = 1, 594 }; 595 596 /* There is CPU dependent code */ 597 static void sh_eth_set_rate_r8a777x(struct net_device *ndev) 598 { 599 struct sh_eth_private *mdp = netdev_priv(ndev); 600 601 switch (mdp->speed) { 602 case 10: /* 10BASE */ 603 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 604 break; 605 case 100:/* 100BASE */ 606 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 607 break; 608 } 609 } 610 611 /* R8A7778/9 */ 612 static struct sh_eth_cpu_data r8a777x_data = { 613 .set_duplex = sh_eth_set_duplex, 614 .set_rate = sh_eth_set_rate_r8a777x, 615 616 .register_type = SH_ETH_REG_FAST_RCAR, 617 618 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 619 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 620 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 621 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 622 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 623 EESIPR_RMAFIP | EESIPR_RRFIP | 624 EESIPR_RTLFIP | EESIPR_RTSFIP | 625 EESIPR_PREIP | EESIPR_CERFIP, 626 627 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 628 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 629 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 630 .fdr_value = 0x00000f0f, 631 632 .apr = 1, 633 .mpr = 1, 634 .tpauser = 1, 635 .hw_swap = 1, 636 }; 637 638 /* R8A7790/1 */ 639 static struct sh_eth_cpu_data r8a779x_data = { 640 .set_duplex = sh_eth_set_duplex, 641 .set_rate = sh_eth_set_rate_r8a777x, 642 643 .register_type = SH_ETH_REG_FAST_RCAR, 644 645 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 646 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 647 ECSIPR_MPDIP, 648 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 649 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 650 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 651 EESIPR_RMAFIP | EESIPR_RRFIP | 652 EESIPR_RTLFIP | EESIPR_RTSFIP | 653 EESIPR_PREIP | EESIPR_CERFIP, 654 655 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 656 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 657 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 658 .fdr_value = 0x00000f0f, 659 660 .trscer_err_mask = DESC_I_RINT8, 661 662 .apr = 1, 663 .mpr = 1, 664 .tpauser = 1, 665 .hw_swap = 1, 666 .rmiimode = 1, 667 .magic = 1, 668 }; 669 #endif /* CONFIG_OF */ 670 671 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 672 { 673 struct sh_eth_private *mdp = netdev_priv(ndev); 674 675 switch (mdp->speed) { 676 case 10: /* 10BASE */ 677 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 678 break; 679 case 100:/* 100BASE */ 680 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 681 break; 682 } 683 } 684 685 /* SH7724 */ 686 static struct sh_eth_cpu_data sh7724_data = { 687 .set_duplex = sh_eth_set_duplex, 688 .set_rate = sh_eth_set_rate_sh7724, 689 690 .register_type = SH_ETH_REG_FAST_SH4, 691 692 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 693 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 694 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 695 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 696 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 697 EESIPR_RMAFIP | EESIPR_RRFIP | 698 EESIPR_RTLFIP | EESIPR_RTSFIP | 699 EESIPR_PREIP | EESIPR_CERFIP, 700 701 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 702 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 703 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 704 705 .apr = 1, 706 .mpr = 1, 707 .tpauser = 1, 708 .hw_swap = 1, 709 .rpadir = 1, 710 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 711 }; 712 713 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 714 { 715 struct sh_eth_private *mdp = netdev_priv(ndev); 716 717 switch (mdp->speed) { 718 case 10: /* 10BASE */ 719 sh_eth_write(ndev, 0, RTRATE); 720 break; 721 case 100:/* 100BASE */ 722 sh_eth_write(ndev, 1, RTRATE); 723 break; 724 } 725 } 726 727 /* SH7757 */ 728 static struct sh_eth_cpu_data sh7757_data = { 729 .set_duplex = sh_eth_set_duplex, 730 .set_rate = sh_eth_set_rate_sh7757, 731 732 .register_type = SH_ETH_REG_FAST_SH4, 733 734 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 735 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 736 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 737 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 738 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 739 EESIPR_CEEFIP | EESIPR_CELFIP | 740 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 741 EESIPR_PREIP | EESIPR_CERFIP, 742 743 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 744 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 745 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 746 747 .irq_flags = IRQF_SHARED, 748 .apr = 1, 749 .mpr = 1, 750 .tpauser = 1, 751 .hw_swap = 1, 752 .no_ade = 1, 753 .rpadir = 1, 754 .rpadir_value = 2 << 16, 755 .rtrate = 1, 756 }; 757 758 #define SH_GIGA_ETH_BASE 0xfee00000UL 759 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 760 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 761 static void sh_eth_chip_reset_giga(struct net_device *ndev) 762 { 763 u32 mahr[2], malr[2]; 764 int i; 765 766 /* save MAHR and MALR */ 767 for (i = 0; i < 2; i++) { 768 malr[i] = ioread32((void *)GIGA_MALR(i)); 769 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 770 } 771 772 sh_eth_chip_reset(ndev); 773 774 /* restore MAHR and MALR */ 775 for (i = 0; i < 2; i++) { 776 iowrite32(malr[i], (void *)GIGA_MALR(i)); 777 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 778 } 779 } 780 781 static void sh_eth_set_rate_giga(struct net_device *ndev) 782 { 783 struct sh_eth_private *mdp = netdev_priv(ndev); 784 785 switch (mdp->speed) { 786 case 10: /* 10BASE */ 787 sh_eth_write(ndev, 0x00000000, GECMR); 788 break; 789 case 100:/* 100BASE */ 790 sh_eth_write(ndev, 0x00000010, GECMR); 791 break; 792 case 1000: /* 1000BASE */ 793 sh_eth_write(ndev, 0x00000020, GECMR); 794 break; 795 } 796 } 797 798 /* SH7757(GETHERC) */ 799 static struct sh_eth_cpu_data sh7757_data_giga = { 800 .chip_reset = sh_eth_chip_reset_giga, 801 .set_duplex = sh_eth_set_duplex, 802 .set_rate = sh_eth_set_rate_giga, 803 804 .register_type = SH_ETH_REG_GIGABIT, 805 806 .ecsr_value = ECSR_ICD | ECSR_MPD, 807 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 808 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 809 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 810 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 811 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 812 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 813 EESIPR_CEEFIP | EESIPR_CELFIP | 814 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 815 EESIPR_PREIP | EESIPR_CERFIP, 816 817 .tx_check = EESR_TC1 | EESR_FTC, 818 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 819 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 820 EESR_TDE, 821 .fdr_value = 0x0000072f, 822 823 .irq_flags = IRQF_SHARED, 824 .apr = 1, 825 .mpr = 1, 826 .tpauser = 1, 827 .bculr = 1, 828 .hw_swap = 1, 829 .rpadir = 1, 830 .rpadir_value = 2 << 16, 831 .no_trimd = 1, 832 .no_ade = 1, 833 .tsu = 1, 834 }; 835 836 /* SH7734 */ 837 static struct sh_eth_cpu_data sh7734_data = { 838 .chip_reset = sh_eth_chip_reset, 839 .set_duplex = sh_eth_set_duplex, 840 .set_rate = sh_eth_set_rate_gether, 841 842 .register_type = SH_ETH_REG_GIGABIT, 843 844 .ecsr_value = ECSR_ICD | ECSR_MPD, 845 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 846 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 847 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 848 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 849 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 850 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 851 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 852 EESIPR_PREIP | EESIPR_CERFIP, 853 854 .tx_check = EESR_TC1 | EESR_FTC, 855 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 856 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 857 EESR_TDE, 858 859 .apr = 1, 860 .mpr = 1, 861 .tpauser = 1, 862 .bculr = 1, 863 .hw_swap = 1, 864 .no_trimd = 1, 865 .no_ade = 1, 866 .tsu = 1, 867 .hw_checksum = 1, 868 .select_mii = 1, 869 .magic = 1, 870 }; 871 872 /* SH7763 */ 873 static struct sh_eth_cpu_data sh7763_data = { 874 .chip_reset = sh_eth_chip_reset, 875 .set_duplex = sh_eth_set_duplex, 876 .set_rate = sh_eth_set_rate_gether, 877 878 .register_type = SH_ETH_REG_GIGABIT, 879 880 .ecsr_value = ECSR_ICD | ECSR_MPD, 881 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 882 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 883 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 884 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 885 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 886 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 887 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 888 EESIPR_PREIP | EESIPR_CERFIP, 889 890 .tx_check = EESR_TC1 | EESR_FTC, 891 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 892 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 893 894 .apr = 1, 895 .mpr = 1, 896 .tpauser = 1, 897 .bculr = 1, 898 .hw_swap = 1, 899 .no_trimd = 1, 900 .no_ade = 1, 901 .tsu = 1, 902 .irq_flags = IRQF_SHARED, 903 .magic = 1, 904 }; 905 906 static struct sh_eth_cpu_data sh7619_data = { 907 .register_type = SH_ETH_REG_FAST_SH3_SH2, 908 909 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 910 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 911 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 912 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 913 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 914 EESIPR_CEEFIP | EESIPR_CELFIP | 915 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 916 EESIPR_PREIP | EESIPR_CERFIP, 917 918 .apr = 1, 919 .mpr = 1, 920 .tpauser = 1, 921 .hw_swap = 1, 922 }; 923 924 static struct sh_eth_cpu_data sh771x_data = { 925 .register_type = SH_ETH_REG_FAST_SH3_SH2, 926 927 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 928 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 929 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 930 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 931 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 932 EESIPR_CEEFIP | EESIPR_CELFIP | 933 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 934 EESIPR_PREIP | EESIPR_CERFIP, 935 .tsu = 1, 936 }; 937 938 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 939 { 940 if (!cd->ecsr_value) 941 cd->ecsr_value = DEFAULT_ECSR_INIT; 942 943 if (!cd->ecsipr_value) 944 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 945 946 if (!cd->fcftr_value) 947 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 948 DEFAULT_FIFO_F_D_RFD; 949 950 if (!cd->fdr_value) 951 cd->fdr_value = DEFAULT_FDR_INIT; 952 953 if (!cd->tx_check) 954 cd->tx_check = DEFAULT_TX_CHECK; 955 956 if (!cd->eesr_err_check) 957 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 958 959 if (!cd->trscer_err_mask) 960 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 961 } 962 963 static int sh_eth_check_reset(struct net_device *ndev) 964 { 965 int ret = 0; 966 int cnt = 100; 967 968 while (cnt > 0) { 969 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 970 break; 971 mdelay(1); 972 cnt--; 973 } 974 if (cnt <= 0) { 975 netdev_err(ndev, "Device reset failed\n"); 976 ret = -ETIMEDOUT; 977 } 978 return ret; 979 } 980 981 static int sh_eth_reset(struct net_device *ndev) 982 { 983 struct sh_eth_private *mdp = netdev_priv(ndev); 984 int ret = 0; 985 986 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) { 987 sh_eth_write(ndev, EDSR_ENALL, EDSR); 988 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 989 990 ret = sh_eth_check_reset(ndev); 991 if (ret) 992 return ret; 993 994 /* Table Init */ 995 sh_eth_write(ndev, 0x0, TDLAR); 996 sh_eth_write(ndev, 0x0, TDFAR); 997 sh_eth_write(ndev, 0x0, TDFXR); 998 sh_eth_write(ndev, 0x0, TDFFR); 999 sh_eth_write(ndev, 0x0, RDLAR); 1000 sh_eth_write(ndev, 0x0, RDFAR); 1001 sh_eth_write(ndev, 0x0, RDFXR); 1002 sh_eth_write(ndev, 0x0, RDFFR); 1003 1004 /* Reset HW CRC register */ 1005 if (mdp->cd->hw_checksum) 1006 sh_eth_write(ndev, 0x0, CSMR); 1007 1008 /* Select MII mode */ 1009 if (mdp->cd->select_mii) 1010 sh_eth_select_mii(ndev); 1011 } else { 1012 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 1013 mdelay(3); 1014 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 1015 } 1016 1017 return ret; 1018 } 1019 1020 static void sh_eth_set_receive_align(struct sk_buff *skb) 1021 { 1022 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1023 1024 if (reserve) 1025 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1026 } 1027 1028 /* Program the hardware MAC address from dev->dev_addr. */ 1029 static void update_mac_address(struct net_device *ndev) 1030 { 1031 sh_eth_write(ndev, 1032 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1033 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1034 sh_eth_write(ndev, 1035 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1036 } 1037 1038 /* Get MAC address from SuperH MAC address register 1039 * 1040 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1041 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1042 * When you want use this device, you must set MAC address in bootloader. 1043 * 1044 */ 1045 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1046 { 1047 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1048 memcpy(ndev->dev_addr, mac, ETH_ALEN); 1049 } else { 1050 u32 mahr = sh_eth_read(ndev, MAHR); 1051 u32 malr = sh_eth_read(ndev, MALR); 1052 1053 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 1054 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 1055 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 1056 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 1057 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 1058 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 1059 } 1060 } 1061 1062 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 1063 { 1064 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) 1065 return EDTRR_TRNS_GETHER; 1066 else 1067 return EDTRR_TRNS_ETHER; 1068 } 1069 1070 struct bb_info { 1071 void (*set_gate)(void *addr); 1072 struct mdiobb_ctrl ctrl; 1073 void *addr; 1074 }; 1075 1076 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1077 { 1078 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1079 u32 pir; 1080 1081 if (bitbang->set_gate) 1082 bitbang->set_gate(bitbang->addr); 1083 1084 pir = ioread32(bitbang->addr); 1085 if (set) 1086 pir |= mask; 1087 else 1088 pir &= ~mask; 1089 iowrite32(pir, bitbang->addr); 1090 } 1091 1092 /* Data I/O pin control */ 1093 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1094 { 1095 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1096 } 1097 1098 /* Set bit data*/ 1099 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1100 { 1101 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1102 } 1103 1104 /* Get bit data*/ 1105 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1106 { 1107 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1108 1109 if (bitbang->set_gate) 1110 bitbang->set_gate(bitbang->addr); 1111 1112 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1113 } 1114 1115 /* MDC pin control */ 1116 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1117 { 1118 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1119 } 1120 1121 /* mdio bus control struct */ 1122 static struct mdiobb_ops bb_ops = { 1123 .owner = THIS_MODULE, 1124 .set_mdc = sh_mdc_ctrl, 1125 .set_mdio_dir = sh_mmd_ctrl, 1126 .set_mdio_data = sh_set_mdio, 1127 .get_mdio_data = sh_get_mdio, 1128 }; 1129 1130 /* free skb and descriptor buffer */ 1131 static void sh_eth_ring_free(struct net_device *ndev) 1132 { 1133 struct sh_eth_private *mdp = netdev_priv(ndev); 1134 int ringsize, i; 1135 1136 /* Free Rx skb ringbuffer */ 1137 if (mdp->rx_skbuff) { 1138 for (i = 0; i < mdp->num_rx_ring; i++) 1139 dev_kfree_skb(mdp->rx_skbuff[i]); 1140 } 1141 kfree(mdp->rx_skbuff); 1142 mdp->rx_skbuff = NULL; 1143 1144 /* Free Tx skb ringbuffer */ 1145 if (mdp->tx_skbuff) { 1146 for (i = 0; i < mdp->num_tx_ring; i++) 1147 dev_kfree_skb(mdp->tx_skbuff[i]); 1148 } 1149 kfree(mdp->tx_skbuff); 1150 mdp->tx_skbuff = NULL; 1151 1152 if (mdp->rx_ring) { 1153 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1154 dma_free_coherent(NULL, ringsize, mdp->rx_ring, 1155 mdp->rx_desc_dma); 1156 mdp->rx_ring = NULL; 1157 } 1158 1159 if (mdp->tx_ring) { 1160 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1161 dma_free_coherent(NULL, ringsize, mdp->tx_ring, 1162 mdp->tx_desc_dma); 1163 mdp->tx_ring = NULL; 1164 } 1165 } 1166 1167 /* format skb and descriptor buffer */ 1168 static void sh_eth_ring_format(struct net_device *ndev) 1169 { 1170 struct sh_eth_private *mdp = netdev_priv(ndev); 1171 int i; 1172 struct sk_buff *skb; 1173 struct sh_eth_rxdesc *rxdesc = NULL; 1174 struct sh_eth_txdesc *txdesc = NULL; 1175 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1176 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1177 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1178 dma_addr_t dma_addr; 1179 u32 buf_len; 1180 1181 mdp->cur_rx = 0; 1182 mdp->cur_tx = 0; 1183 mdp->dirty_rx = 0; 1184 mdp->dirty_tx = 0; 1185 1186 memset(mdp->rx_ring, 0, rx_ringsize); 1187 1188 /* build Rx ring buffer */ 1189 for (i = 0; i < mdp->num_rx_ring; i++) { 1190 /* skb */ 1191 mdp->rx_skbuff[i] = NULL; 1192 skb = netdev_alloc_skb(ndev, skbuff_size); 1193 if (skb == NULL) 1194 break; 1195 sh_eth_set_receive_align(skb); 1196 1197 /* The size of the buffer is a multiple of 32 bytes. */ 1198 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1199 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len, 1200 DMA_FROM_DEVICE); 1201 if (dma_mapping_error(&ndev->dev, dma_addr)) { 1202 kfree_skb(skb); 1203 break; 1204 } 1205 mdp->rx_skbuff[i] = skb; 1206 1207 /* RX descriptor */ 1208 rxdesc = &mdp->rx_ring[i]; 1209 rxdesc->len = cpu_to_le32(buf_len << 16); 1210 rxdesc->addr = cpu_to_le32(dma_addr); 1211 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1212 1213 /* Rx descriptor address set */ 1214 if (i == 0) { 1215 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1216 if (sh_eth_is_gether(mdp) || 1217 sh_eth_is_rz_fast_ether(mdp)) 1218 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1219 } 1220 } 1221 1222 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1223 1224 /* Mark the last entry as wrapping the ring. */ 1225 if (rxdesc) 1226 rxdesc->status |= cpu_to_le32(RD_RDLE); 1227 1228 memset(mdp->tx_ring, 0, tx_ringsize); 1229 1230 /* build Tx ring buffer */ 1231 for (i = 0; i < mdp->num_tx_ring; i++) { 1232 mdp->tx_skbuff[i] = NULL; 1233 txdesc = &mdp->tx_ring[i]; 1234 txdesc->status = cpu_to_le32(TD_TFP); 1235 txdesc->len = cpu_to_le32(0); 1236 if (i == 0) { 1237 /* Tx descriptor address set */ 1238 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1239 if (sh_eth_is_gether(mdp) || 1240 sh_eth_is_rz_fast_ether(mdp)) 1241 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1242 } 1243 } 1244 1245 txdesc->status |= cpu_to_le32(TD_TDLE); 1246 } 1247 1248 /* Get skb and descriptor buffer */ 1249 static int sh_eth_ring_init(struct net_device *ndev) 1250 { 1251 struct sh_eth_private *mdp = netdev_priv(ndev); 1252 int rx_ringsize, tx_ringsize; 1253 1254 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1255 * card needs room to do 8 byte alignment, +2 so we can reserve 1256 * the first 2 bytes, and +16 gets room for the status word from the 1257 * card. 1258 */ 1259 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1260 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1261 if (mdp->cd->rpadir) 1262 mdp->rx_buf_sz += NET_IP_ALIGN; 1263 1264 /* Allocate RX and TX skb rings */ 1265 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1266 GFP_KERNEL); 1267 if (!mdp->rx_skbuff) 1268 return -ENOMEM; 1269 1270 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1271 GFP_KERNEL); 1272 if (!mdp->tx_skbuff) 1273 goto ring_free; 1274 1275 /* Allocate all Rx descriptors. */ 1276 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1277 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, 1278 GFP_KERNEL); 1279 if (!mdp->rx_ring) 1280 goto ring_free; 1281 1282 mdp->dirty_rx = 0; 1283 1284 /* Allocate all Tx descriptors. */ 1285 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1286 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 1287 GFP_KERNEL); 1288 if (!mdp->tx_ring) 1289 goto ring_free; 1290 return 0; 1291 1292 ring_free: 1293 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1294 sh_eth_ring_free(ndev); 1295 1296 return -ENOMEM; 1297 } 1298 1299 static int sh_eth_dev_init(struct net_device *ndev) 1300 { 1301 struct sh_eth_private *mdp = netdev_priv(ndev); 1302 int ret; 1303 1304 /* Soft Reset */ 1305 ret = sh_eth_reset(ndev); 1306 if (ret) 1307 return ret; 1308 1309 if (mdp->cd->rmiimode) 1310 sh_eth_write(ndev, 0x1, RMIIMODE); 1311 1312 /* Descriptor format */ 1313 sh_eth_ring_format(ndev); 1314 if (mdp->cd->rpadir) 1315 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1316 1317 /* all sh_eth int mask */ 1318 sh_eth_write(ndev, 0, EESIPR); 1319 1320 #if defined(__LITTLE_ENDIAN) 1321 if (mdp->cd->hw_swap) 1322 sh_eth_write(ndev, EDMR_EL, EDMR); 1323 else 1324 #endif 1325 sh_eth_write(ndev, 0, EDMR); 1326 1327 /* FIFO size set */ 1328 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1329 sh_eth_write(ndev, 0, TFTR); 1330 1331 /* Frame recv control (enable multiple-packets per rx irq) */ 1332 sh_eth_write(ndev, RMCR_RNC, RMCR); 1333 1334 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1335 1336 if (mdp->cd->bculr) 1337 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1338 1339 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1340 1341 if (!mdp->cd->no_trimd) 1342 sh_eth_write(ndev, 0, TRIMD); 1343 1344 /* Recv frame limit set register */ 1345 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1346 RFLR); 1347 1348 sh_eth_modify(ndev, EESR, 0, 0); 1349 mdp->irq_enabled = true; 1350 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1351 1352 /* PAUSE Prohibition */ 1353 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1354 ECMR_TE | ECMR_RE, ECMR); 1355 1356 if (mdp->cd->set_rate) 1357 mdp->cd->set_rate(ndev); 1358 1359 /* E-MAC Status Register clear */ 1360 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1361 1362 /* E-MAC Interrupt Enable register */ 1363 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1364 1365 /* Set MAC address */ 1366 update_mac_address(ndev); 1367 1368 /* mask reset */ 1369 if (mdp->cd->apr) 1370 sh_eth_write(ndev, APR_AP, APR); 1371 if (mdp->cd->mpr) 1372 sh_eth_write(ndev, MPR_MP, MPR); 1373 if (mdp->cd->tpauser) 1374 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1375 1376 /* Setting the Rx mode will start the Rx process. */ 1377 sh_eth_write(ndev, EDRRR_R, EDRRR); 1378 1379 return ret; 1380 } 1381 1382 static void sh_eth_dev_exit(struct net_device *ndev) 1383 { 1384 struct sh_eth_private *mdp = netdev_priv(ndev); 1385 int i; 1386 1387 /* Deactivate all TX descriptors, so DMA should stop at next 1388 * packet boundary if it's currently running 1389 */ 1390 for (i = 0; i < mdp->num_tx_ring; i++) 1391 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1392 1393 /* Disable TX FIFO egress to MAC */ 1394 sh_eth_rcv_snd_disable(ndev); 1395 1396 /* Stop RX DMA at next packet boundary */ 1397 sh_eth_write(ndev, 0, EDRRR); 1398 1399 /* Aside from TX DMA, we can't tell when the hardware is 1400 * really stopped, so we need to reset to make sure. 1401 * Before doing that, wait for long enough to *probably* 1402 * finish transmitting the last packet and poll stats. 1403 */ 1404 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1405 sh_eth_get_stats(ndev); 1406 sh_eth_reset(ndev); 1407 1408 /* Set MAC address again */ 1409 update_mac_address(ndev); 1410 } 1411 1412 /* free Tx skb function */ 1413 static int sh_eth_txfree(struct net_device *ndev) 1414 { 1415 struct sh_eth_private *mdp = netdev_priv(ndev); 1416 struct sh_eth_txdesc *txdesc; 1417 int free_num = 0; 1418 int entry; 1419 1420 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1421 entry = mdp->dirty_tx % mdp->num_tx_ring; 1422 txdesc = &mdp->tx_ring[entry]; 1423 if (txdesc->status & cpu_to_le32(TD_TACT)) 1424 break; 1425 /* TACT bit must be checked before all the following reads */ 1426 dma_rmb(); 1427 netif_info(mdp, tx_done, ndev, 1428 "tx entry %d status 0x%08x\n", 1429 entry, le32_to_cpu(txdesc->status)); 1430 /* Free the original skb. */ 1431 if (mdp->tx_skbuff[entry]) { 1432 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr), 1433 le32_to_cpu(txdesc->len) >> 16, 1434 DMA_TO_DEVICE); 1435 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1436 mdp->tx_skbuff[entry] = NULL; 1437 free_num++; 1438 } 1439 txdesc->status = cpu_to_le32(TD_TFP); 1440 if (entry >= mdp->num_tx_ring - 1) 1441 txdesc->status |= cpu_to_le32(TD_TDLE); 1442 1443 ndev->stats.tx_packets++; 1444 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1445 } 1446 return free_num; 1447 } 1448 1449 /* Packet receive function */ 1450 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1451 { 1452 struct sh_eth_private *mdp = netdev_priv(ndev); 1453 struct sh_eth_rxdesc *rxdesc; 1454 1455 int entry = mdp->cur_rx % mdp->num_rx_ring; 1456 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1457 int limit; 1458 struct sk_buff *skb; 1459 u32 desc_status; 1460 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1461 dma_addr_t dma_addr; 1462 u16 pkt_len; 1463 u32 buf_len; 1464 1465 boguscnt = min(boguscnt, *quota); 1466 limit = boguscnt; 1467 rxdesc = &mdp->rx_ring[entry]; 1468 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1469 /* RACT bit must be checked before all the following reads */ 1470 dma_rmb(); 1471 desc_status = le32_to_cpu(rxdesc->status); 1472 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1473 1474 if (--boguscnt < 0) 1475 break; 1476 1477 netif_info(mdp, rx_status, ndev, 1478 "rx entry %d status 0x%08x len %d\n", 1479 entry, desc_status, pkt_len); 1480 1481 if (!(desc_status & RDFEND)) 1482 ndev->stats.rx_length_errors++; 1483 1484 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1485 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1486 * bit 0. However, in case of the R8A7740 and R7S72100 1487 * the RFS bits are from bit 25 to bit 16. So, the 1488 * driver needs right shifting by 16. 1489 */ 1490 if (mdp->cd->hw_checksum) 1491 desc_status >>= 16; 1492 1493 skb = mdp->rx_skbuff[entry]; 1494 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1495 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1496 ndev->stats.rx_errors++; 1497 if (desc_status & RD_RFS1) 1498 ndev->stats.rx_crc_errors++; 1499 if (desc_status & RD_RFS2) 1500 ndev->stats.rx_frame_errors++; 1501 if (desc_status & RD_RFS3) 1502 ndev->stats.rx_length_errors++; 1503 if (desc_status & RD_RFS4) 1504 ndev->stats.rx_length_errors++; 1505 if (desc_status & RD_RFS6) 1506 ndev->stats.rx_missed_errors++; 1507 if (desc_status & RD_RFS10) 1508 ndev->stats.rx_over_errors++; 1509 } else if (skb) { 1510 dma_addr = le32_to_cpu(rxdesc->addr); 1511 if (!mdp->cd->hw_swap) 1512 sh_eth_soft_swap( 1513 phys_to_virt(ALIGN(dma_addr, 4)), 1514 pkt_len + 2); 1515 mdp->rx_skbuff[entry] = NULL; 1516 if (mdp->cd->rpadir) 1517 skb_reserve(skb, NET_IP_ALIGN); 1518 dma_unmap_single(&ndev->dev, dma_addr, 1519 ALIGN(mdp->rx_buf_sz, 32), 1520 DMA_FROM_DEVICE); 1521 skb_put(skb, pkt_len); 1522 skb->protocol = eth_type_trans(skb, ndev); 1523 netif_receive_skb(skb); 1524 ndev->stats.rx_packets++; 1525 ndev->stats.rx_bytes += pkt_len; 1526 if (desc_status & RD_RFS8) 1527 ndev->stats.multicast++; 1528 } 1529 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1530 rxdesc = &mdp->rx_ring[entry]; 1531 } 1532 1533 /* Refill the Rx ring buffers. */ 1534 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1535 entry = mdp->dirty_rx % mdp->num_rx_ring; 1536 rxdesc = &mdp->rx_ring[entry]; 1537 /* The size of the buffer is 32 byte boundary. */ 1538 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1539 rxdesc->len = cpu_to_le32(buf_len << 16); 1540 1541 if (mdp->rx_skbuff[entry] == NULL) { 1542 skb = netdev_alloc_skb(ndev, skbuff_size); 1543 if (skb == NULL) 1544 break; /* Better luck next round. */ 1545 sh_eth_set_receive_align(skb); 1546 dma_addr = dma_map_single(&ndev->dev, skb->data, 1547 buf_len, DMA_FROM_DEVICE); 1548 if (dma_mapping_error(&ndev->dev, dma_addr)) { 1549 kfree_skb(skb); 1550 break; 1551 } 1552 mdp->rx_skbuff[entry] = skb; 1553 1554 skb_checksum_none_assert(skb); 1555 rxdesc->addr = cpu_to_le32(dma_addr); 1556 } 1557 dma_wmb(); /* RACT bit must be set after all the above writes */ 1558 if (entry >= mdp->num_rx_ring - 1) 1559 rxdesc->status |= 1560 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1561 else 1562 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1563 } 1564 1565 /* Restart Rx engine if stopped. */ 1566 /* If we don't need to check status, don't. -KDU */ 1567 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1568 /* fix the values for the next receiving if RDE is set */ 1569 if (intr_status & EESR_RDE && 1570 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) { 1571 u32 count = (sh_eth_read(ndev, RDFAR) - 1572 sh_eth_read(ndev, RDLAR)) >> 4; 1573 1574 mdp->cur_rx = count; 1575 mdp->dirty_rx = count; 1576 } 1577 sh_eth_write(ndev, EDRRR_R, EDRRR); 1578 } 1579 1580 *quota -= limit - boguscnt - 1; 1581 1582 return *quota <= 0; 1583 } 1584 1585 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1586 { 1587 /* disable tx and rx */ 1588 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1589 } 1590 1591 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1592 { 1593 /* enable tx and rx */ 1594 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1595 } 1596 1597 /* E-MAC interrupt handler */ 1598 static void sh_eth_emac_interrupt(struct net_device *ndev) 1599 { 1600 struct sh_eth_private *mdp = netdev_priv(ndev); 1601 u32 felic_stat; 1602 u32 link_stat; 1603 1604 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1605 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1606 if (felic_stat & ECSR_ICD) 1607 ndev->stats.tx_carrier_errors++; 1608 if (felic_stat & ECSR_MPD) 1609 pm_wakeup_event(&mdp->pdev->dev, 0); 1610 if (felic_stat & ECSR_LCHNG) { 1611 /* Link Changed */ 1612 if (mdp->cd->no_psr || mdp->no_ether_link) 1613 return; 1614 link_stat = sh_eth_read(ndev, PSR); 1615 if (mdp->ether_link_active_low) 1616 link_stat = ~link_stat; 1617 if (!(link_stat & PHY_ST_LINK)) { 1618 sh_eth_rcv_snd_disable(ndev); 1619 } else { 1620 /* Link Up */ 1621 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1622 /* clear int */ 1623 sh_eth_modify(ndev, ECSR, 0, 0); 1624 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1625 /* enable tx and rx */ 1626 sh_eth_rcv_snd_enable(ndev); 1627 } 1628 } 1629 } 1630 1631 /* error control function */ 1632 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1633 { 1634 struct sh_eth_private *mdp = netdev_priv(ndev); 1635 u32 mask; 1636 1637 if (intr_status & EESR_TWB) { 1638 /* Unused write back interrupt */ 1639 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1640 ndev->stats.tx_aborted_errors++; 1641 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1642 } 1643 } 1644 1645 if (intr_status & EESR_RABT) { 1646 /* Receive Abort int */ 1647 if (intr_status & EESR_RFRMER) { 1648 /* Receive Frame Overflow int */ 1649 ndev->stats.rx_frame_errors++; 1650 } 1651 } 1652 1653 if (intr_status & EESR_TDE) { 1654 /* Transmit Descriptor Empty int */ 1655 ndev->stats.tx_fifo_errors++; 1656 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1657 } 1658 1659 if (intr_status & EESR_TFE) { 1660 /* FIFO under flow */ 1661 ndev->stats.tx_fifo_errors++; 1662 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1663 } 1664 1665 if (intr_status & EESR_RDE) { 1666 /* Receive Descriptor Empty int */ 1667 ndev->stats.rx_over_errors++; 1668 } 1669 1670 if (intr_status & EESR_RFE) { 1671 /* Receive FIFO Overflow int */ 1672 ndev->stats.rx_fifo_errors++; 1673 } 1674 1675 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1676 /* Address Error */ 1677 ndev->stats.tx_fifo_errors++; 1678 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1679 } 1680 1681 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1682 if (mdp->cd->no_ade) 1683 mask &= ~EESR_ADE; 1684 if (intr_status & mask) { 1685 /* Tx error */ 1686 u32 edtrr = sh_eth_read(ndev, EDTRR); 1687 1688 /* dmesg */ 1689 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1690 intr_status, mdp->cur_tx, mdp->dirty_tx, 1691 (u32)ndev->state, edtrr); 1692 /* dirty buffer free */ 1693 sh_eth_txfree(ndev); 1694 1695 /* SH7712 BUG */ 1696 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1697 /* tx dma start */ 1698 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1699 } 1700 /* wakeup */ 1701 netif_wake_queue(ndev); 1702 } 1703 } 1704 1705 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1706 { 1707 struct net_device *ndev = netdev; 1708 struct sh_eth_private *mdp = netdev_priv(ndev); 1709 struct sh_eth_cpu_data *cd = mdp->cd; 1710 irqreturn_t ret = IRQ_NONE; 1711 u32 intr_status, intr_enable; 1712 1713 spin_lock(&mdp->lock); 1714 1715 /* Get interrupt status */ 1716 intr_status = sh_eth_read(ndev, EESR); 1717 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1718 * enabled since it's the one that comes thru regardless of the mask, 1719 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1720 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1721 * bit... 1722 */ 1723 intr_enable = sh_eth_read(ndev, EESIPR); 1724 intr_status &= intr_enable | EESIPR_ECIIP; 1725 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1726 cd->eesr_err_check)) 1727 ret = IRQ_HANDLED; 1728 else 1729 goto out; 1730 1731 if (unlikely(!mdp->irq_enabled)) { 1732 sh_eth_write(ndev, 0, EESIPR); 1733 goto out; 1734 } 1735 1736 if (intr_status & EESR_RX_CHECK) { 1737 if (napi_schedule_prep(&mdp->napi)) { 1738 /* Mask Rx interrupts */ 1739 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1740 EESIPR); 1741 __napi_schedule(&mdp->napi); 1742 } else { 1743 netdev_warn(ndev, 1744 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1745 intr_status, intr_enable); 1746 } 1747 } 1748 1749 /* Tx Check */ 1750 if (intr_status & cd->tx_check) { 1751 /* Clear Tx interrupts */ 1752 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1753 1754 sh_eth_txfree(ndev); 1755 netif_wake_queue(ndev); 1756 } 1757 1758 /* E-MAC interrupt */ 1759 if (intr_status & EESR_ECI) 1760 sh_eth_emac_interrupt(ndev); 1761 1762 if (intr_status & cd->eesr_err_check) { 1763 /* Clear error interrupts */ 1764 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1765 1766 sh_eth_error(ndev, intr_status); 1767 } 1768 1769 out: 1770 spin_unlock(&mdp->lock); 1771 1772 return ret; 1773 } 1774 1775 static int sh_eth_poll(struct napi_struct *napi, int budget) 1776 { 1777 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1778 napi); 1779 struct net_device *ndev = napi->dev; 1780 int quota = budget; 1781 u32 intr_status; 1782 1783 for (;;) { 1784 intr_status = sh_eth_read(ndev, EESR); 1785 if (!(intr_status & EESR_RX_CHECK)) 1786 break; 1787 /* Clear Rx interrupts */ 1788 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1789 1790 if (sh_eth_rx(ndev, intr_status, "a)) 1791 goto out; 1792 } 1793 1794 napi_complete(napi); 1795 1796 /* Reenable Rx interrupts */ 1797 if (mdp->irq_enabled) 1798 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1799 out: 1800 return budget - quota; 1801 } 1802 1803 /* PHY state control function */ 1804 static void sh_eth_adjust_link(struct net_device *ndev) 1805 { 1806 struct sh_eth_private *mdp = netdev_priv(ndev); 1807 struct phy_device *phydev = ndev->phydev; 1808 int new_state = 0; 1809 1810 if (phydev->link) { 1811 if (phydev->duplex != mdp->duplex) { 1812 new_state = 1; 1813 mdp->duplex = phydev->duplex; 1814 if (mdp->cd->set_duplex) 1815 mdp->cd->set_duplex(ndev); 1816 } 1817 1818 if (phydev->speed != mdp->speed) { 1819 new_state = 1; 1820 mdp->speed = phydev->speed; 1821 if (mdp->cd->set_rate) 1822 mdp->cd->set_rate(ndev); 1823 } 1824 if (!mdp->link) { 1825 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 1826 new_state = 1; 1827 mdp->link = phydev->link; 1828 if (mdp->cd->no_psr || mdp->no_ether_link) 1829 sh_eth_rcv_snd_enable(ndev); 1830 } 1831 } else if (mdp->link) { 1832 new_state = 1; 1833 mdp->link = 0; 1834 mdp->speed = 0; 1835 mdp->duplex = -1; 1836 if (mdp->cd->no_psr || mdp->no_ether_link) 1837 sh_eth_rcv_snd_disable(ndev); 1838 } 1839 1840 if (new_state && netif_msg_link(mdp)) 1841 phy_print_status(phydev); 1842 } 1843 1844 /* PHY init function */ 1845 static int sh_eth_phy_init(struct net_device *ndev) 1846 { 1847 struct device_node *np = ndev->dev.parent->of_node; 1848 struct sh_eth_private *mdp = netdev_priv(ndev); 1849 struct phy_device *phydev; 1850 1851 mdp->link = 0; 1852 mdp->speed = 0; 1853 mdp->duplex = -1; 1854 1855 /* Try connect to PHY */ 1856 if (np) { 1857 struct device_node *pn; 1858 1859 pn = of_parse_phandle(np, "phy-handle", 0); 1860 phydev = of_phy_connect(ndev, pn, 1861 sh_eth_adjust_link, 0, 1862 mdp->phy_interface); 1863 1864 of_node_put(pn); 1865 if (!phydev) 1866 phydev = ERR_PTR(-ENOENT); 1867 } else { 1868 char phy_id[MII_BUS_ID_SIZE + 3]; 1869 1870 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1871 mdp->mii_bus->id, mdp->phy_id); 1872 1873 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1874 mdp->phy_interface); 1875 } 1876 1877 if (IS_ERR(phydev)) { 1878 netdev_err(ndev, "failed to connect PHY\n"); 1879 return PTR_ERR(phydev); 1880 } 1881 1882 phy_attached_info(phydev); 1883 1884 return 0; 1885 } 1886 1887 /* PHY control start function */ 1888 static int sh_eth_phy_start(struct net_device *ndev) 1889 { 1890 int ret; 1891 1892 ret = sh_eth_phy_init(ndev); 1893 if (ret) 1894 return ret; 1895 1896 phy_start(ndev->phydev); 1897 1898 return 0; 1899 } 1900 1901 static int sh_eth_get_link_ksettings(struct net_device *ndev, 1902 struct ethtool_link_ksettings *cmd) 1903 { 1904 struct sh_eth_private *mdp = netdev_priv(ndev); 1905 unsigned long flags; 1906 int ret; 1907 1908 if (!ndev->phydev) 1909 return -ENODEV; 1910 1911 spin_lock_irqsave(&mdp->lock, flags); 1912 ret = phy_ethtool_ksettings_get(ndev->phydev, cmd); 1913 spin_unlock_irqrestore(&mdp->lock, flags); 1914 1915 return ret; 1916 } 1917 1918 static int sh_eth_set_link_ksettings(struct net_device *ndev, 1919 const struct ethtool_link_ksettings *cmd) 1920 { 1921 struct sh_eth_private *mdp = netdev_priv(ndev); 1922 unsigned long flags; 1923 int ret; 1924 1925 if (!ndev->phydev) 1926 return -ENODEV; 1927 1928 spin_lock_irqsave(&mdp->lock, flags); 1929 1930 /* disable tx and rx */ 1931 sh_eth_rcv_snd_disable(ndev); 1932 1933 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd); 1934 if (ret) 1935 goto error_exit; 1936 1937 if (cmd->base.duplex == DUPLEX_FULL) 1938 mdp->duplex = 1; 1939 else 1940 mdp->duplex = 0; 1941 1942 if (mdp->cd->set_duplex) 1943 mdp->cd->set_duplex(ndev); 1944 1945 error_exit: 1946 mdelay(1); 1947 1948 /* enable tx and rx */ 1949 sh_eth_rcv_snd_enable(ndev); 1950 1951 spin_unlock_irqrestore(&mdp->lock, flags); 1952 1953 return ret; 1954 } 1955 1956 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 1957 * version must be bumped as well. Just adding registers up to that 1958 * limit is fine, as long as the existing register indices don't 1959 * change. 1960 */ 1961 #define SH_ETH_REG_DUMP_VERSION 1 1962 #define SH_ETH_REG_DUMP_MAX_REGS 256 1963 1964 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 1965 { 1966 struct sh_eth_private *mdp = netdev_priv(ndev); 1967 struct sh_eth_cpu_data *cd = mdp->cd; 1968 u32 *valid_map; 1969 size_t len; 1970 1971 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 1972 1973 /* Dump starts with a bitmap that tells ethtool which 1974 * registers are defined for this chip. 1975 */ 1976 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 1977 if (buf) { 1978 valid_map = buf; 1979 buf += len; 1980 } else { 1981 valid_map = NULL; 1982 } 1983 1984 /* Add a register to the dump, if it has a defined offset. 1985 * This automatically skips most undefined registers, but for 1986 * some it is also necessary to check a capability flag in 1987 * struct sh_eth_cpu_data. 1988 */ 1989 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 1990 #define add_reg_from(reg, read_expr) do { \ 1991 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 1992 if (buf) { \ 1993 mark_reg_valid(reg); \ 1994 *buf++ = read_expr; \ 1995 } \ 1996 ++len; \ 1997 } \ 1998 } while (0) 1999 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2000 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2001 2002 add_reg(EDSR); 2003 add_reg(EDMR); 2004 add_reg(EDTRR); 2005 add_reg(EDRRR); 2006 add_reg(EESR); 2007 add_reg(EESIPR); 2008 add_reg(TDLAR); 2009 add_reg(TDFAR); 2010 add_reg(TDFXR); 2011 add_reg(TDFFR); 2012 add_reg(RDLAR); 2013 add_reg(RDFAR); 2014 add_reg(RDFXR); 2015 add_reg(RDFFR); 2016 add_reg(TRSCER); 2017 add_reg(RMFCR); 2018 add_reg(TFTR); 2019 add_reg(FDR); 2020 add_reg(RMCR); 2021 add_reg(TFUCR); 2022 add_reg(RFOCR); 2023 if (cd->rmiimode) 2024 add_reg(RMIIMODE); 2025 add_reg(FCFTR); 2026 if (cd->rpadir) 2027 add_reg(RPADIR); 2028 if (!cd->no_trimd) 2029 add_reg(TRIMD); 2030 add_reg(ECMR); 2031 add_reg(ECSR); 2032 add_reg(ECSIPR); 2033 add_reg(PIR); 2034 if (!cd->no_psr) 2035 add_reg(PSR); 2036 add_reg(RDMLR); 2037 add_reg(RFLR); 2038 add_reg(IPGR); 2039 if (cd->apr) 2040 add_reg(APR); 2041 if (cd->mpr) 2042 add_reg(MPR); 2043 add_reg(RFCR); 2044 add_reg(RFCF); 2045 if (cd->tpauser) 2046 add_reg(TPAUSER); 2047 add_reg(TPAUSECR); 2048 add_reg(GECMR); 2049 if (cd->bculr) 2050 add_reg(BCULR); 2051 add_reg(MAHR); 2052 add_reg(MALR); 2053 add_reg(TROCR); 2054 add_reg(CDCR); 2055 add_reg(LCCR); 2056 add_reg(CNDCR); 2057 add_reg(CEFCR); 2058 add_reg(FRECR); 2059 add_reg(TSFRCR); 2060 add_reg(TLFRCR); 2061 add_reg(CERCR); 2062 add_reg(CEECR); 2063 add_reg(MAFCR); 2064 if (cd->rtrate) 2065 add_reg(RTRATE); 2066 if (cd->hw_checksum) 2067 add_reg(CSMR); 2068 if (cd->select_mii) 2069 add_reg(RMII_MII); 2070 add_reg(ARSTR); 2071 if (cd->tsu) { 2072 add_tsu_reg(TSU_CTRST); 2073 add_tsu_reg(TSU_FWEN0); 2074 add_tsu_reg(TSU_FWEN1); 2075 add_tsu_reg(TSU_FCM); 2076 add_tsu_reg(TSU_BSYSL0); 2077 add_tsu_reg(TSU_BSYSL1); 2078 add_tsu_reg(TSU_PRISL0); 2079 add_tsu_reg(TSU_PRISL1); 2080 add_tsu_reg(TSU_FWSL0); 2081 add_tsu_reg(TSU_FWSL1); 2082 add_tsu_reg(TSU_FWSLC); 2083 add_tsu_reg(TSU_QTAG0); 2084 add_tsu_reg(TSU_QTAG1); 2085 add_tsu_reg(TSU_QTAGM0); 2086 add_tsu_reg(TSU_QTAGM1); 2087 add_tsu_reg(TSU_FWSR); 2088 add_tsu_reg(TSU_FWINMK); 2089 add_tsu_reg(TSU_ADQT0); 2090 add_tsu_reg(TSU_ADQT1); 2091 add_tsu_reg(TSU_VTAG0); 2092 add_tsu_reg(TSU_VTAG1); 2093 add_tsu_reg(TSU_ADSBSY); 2094 add_tsu_reg(TSU_TEN); 2095 add_tsu_reg(TSU_POST1); 2096 add_tsu_reg(TSU_POST2); 2097 add_tsu_reg(TSU_POST3); 2098 add_tsu_reg(TSU_POST4); 2099 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) { 2100 /* This is the start of a table, not just a single 2101 * register. 2102 */ 2103 if (buf) { 2104 unsigned int i; 2105 2106 mark_reg_valid(TSU_ADRH0); 2107 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2108 *buf++ = ioread32( 2109 mdp->tsu_addr + 2110 mdp->reg_offset[TSU_ADRH0] + 2111 i * 4); 2112 } 2113 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2114 } 2115 } 2116 2117 #undef mark_reg_valid 2118 #undef add_reg_from 2119 #undef add_reg 2120 #undef add_tsu_reg 2121 2122 return len * 4; 2123 } 2124 2125 static int sh_eth_get_regs_len(struct net_device *ndev) 2126 { 2127 return __sh_eth_get_regs(ndev, NULL); 2128 } 2129 2130 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2131 void *buf) 2132 { 2133 struct sh_eth_private *mdp = netdev_priv(ndev); 2134 2135 regs->version = SH_ETH_REG_DUMP_VERSION; 2136 2137 pm_runtime_get_sync(&mdp->pdev->dev); 2138 __sh_eth_get_regs(ndev, buf); 2139 pm_runtime_put_sync(&mdp->pdev->dev); 2140 } 2141 2142 static int sh_eth_nway_reset(struct net_device *ndev) 2143 { 2144 struct sh_eth_private *mdp = netdev_priv(ndev); 2145 unsigned long flags; 2146 int ret; 2147 2148 if (!ndev->phydev) 2149 return -ENODEV; 2150 2151 spin_lock_irqsave(&mdp->lock, flags); 2152 ret = phy_start_aneg(ndev->phydev); 2153 spin_unlock_irqrestore(&mdp->lock, flags); 2154 2155 return ret; 2156 } 2157 2158 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2159 { 2160 struct sh_eth_private *mdp = netdev_priv(ndev); 2161 return mdp->msg_enable; 2162 } 2163 2164 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2165 { 2166 struct sh_eth_private *mdp = netdev_priv(ndev); 2167 mdp->msg_enable = value; 2168 } 2169 2170 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2171 "rx_current", "tx_current", 2172 "rx_dirty", "tx_dirty", 2173 }; 2174 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2175 2176 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2177 { 2178 switch (sset) { 2179 case ETH_SS_STATS: 2180 return SH_ETH_STATS_LEN; 2181 default: 2182 return -EOPNOTSUPP; 2183 } 2184 } 2185 2186 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2187 struct ethtool_stats *stats, u64 *data) 2188 { 2189 struct sh_eth_private *mdp = netdev_priv(ndev); 2190 int i = 0; 2191 2192 /* device-specific stats */ 2193 data[i++] = mdp->cur_rx; 2194 data[i++] = mdp->cur_tx; 2195 data[i++] = mdp->dirty_rx; 2196 data[i++] = mdp->dirty_tx; 2197 } 2198 2199 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2200 { 2201 switch (stringset) { 2202 case ETH_SS_STATS: 2203 memcpy(data, *sh_eth_gstrings_stats, 2204 sizeof(sh_eth_gstrings_stats)); 2205 break; 2206 } 2207 } 2208 2209 static void sh_eth_get_ringparam(struct net_device *ndev, 2210 struct ethtool_ringparam *ring) 2211 { 2212 struct sh_eth_private *mdp = netdev_priv(ndev); 2213 2214 ring->rx_max_pending = RX_RING_MAX; 2215 ring->tx_max_pending = TX_RING_MAX; 2216 ring->rx_pending = mdp->num_rx_ring; 2217 ring->tx_pending = mdp->num_tx_ring; 2218 } 2219 2220 static int sh_eth_set_ringparam(struct net_device *ndev, 2221 struct ethtool_ringparam *ring) 2222 { 2223 struct sh_eth_private *mdp = netdev_priv(ndev); 2224 int ret; 2225 2226 if (ring->tx_pending > TX_RING_MAX || 2227 ring->rx_pending > RX_RING_MAX || 2228 ring->tx_pending < TX_RING_MIN || 2229 ring->rx_pending < RX_RING_MIN) 2230 return -EINVAL; 2231 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2232 return -EINVAL; 2233 2234 if (netif_running(ndev)) { 2235 netif_device_detach(ndev); 2236 netif_tx_disable(ndev); 2237 2238 /* Serialise with the interrupt handler and NAPI, then 2239 * disable interrupts. We have to clear the 2240 * irq_enabled flag first to ensure that interrupts 2241 * won't be re-enabled. 2242 */ 2243 mdp->irq_enabled = false; 2244 synchronize_irq(ndev->irq); 2245 napi_synchronize(&mdp->napi); 2246 sh_eth_write(ndev, 0x0000, EESIPR); 2247 2248 sh_eth_dev_exit(ndev); 2249 2250 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2251 sh_eth_ring_free(ndev); 2252 } 2253 2254 /* Set new parameters */ 2255 mdp->num_rx_ring = ring->rx_pending; 2256 mdp->num_tx_ring = ring->tx_pending; 2257 2258 if (netif_running(ndev)) { 2259 ret = sh_eth_ring_init(ndev); 2260 if (ret < 0) { 2261 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2262 __func__); 2263 return ret; 2264 } 2265 ret = sh_eth_dev_init(ndev); 2266 if (ret < 0) { 2267 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2268 __func__); 2269 return ret; 2270 } 2271 2272 netif_device_attach(ndev); 2273 } 2274 2275 return 0; 2276 } 2277 2278 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2279 { 2280 struct sh_eth_private *mdp = netdev_priv(ndev); 2281 2282 wol->supported = 0; 2283 wol->wolopts = 0; 2284 2285 if (mdp->cd->magic && mdp->clk) { 2286 wol->supported = WAKE_MAGIC; 2287 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2288 } 2289 } 2290 2291 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2292 { 2293 struct sh_eth_private *mdp = netdev_priv(ndev); 2294 2295 if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC) 2296 return -EOPNOTSUPP; 2297 2298 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2299 2300 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2301 2302 return 0; 2303 } 2304 2305 static const struct ethtool_ops sh_eth_ethtool_ops = { 2306 .get_regs_len = sh_eth_get_regs_len, 2307 .get_regs = sh_eth_get_regs, 2308 .nway_reset = sh_eth_nway_reset, 2309 .get_msglevel = sh_eth_get_msglevel, 2310 .set_msglevel = sh_eth_set_msglevel, 2311 .get_link = ethtool_op_get_link, 2312 .get_strings = sh_eth_get_strings, 2313 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2314 .get_sset_count = sh_eth_get_sset_count, 2315 .get_ringparam = sh_eth_get_ringparam, 2316 .set_ringparam = sh_eth_set_ringparam, 2317 .get_link_ksettings = sh_eth_get_link_ksettings, 2318 .set_link_ksettings = sh_eth_set_link_ksettings, 2319 .get_wol = sh_eth_get_wol, 2320 .set_wol = sh_eth_set_wol, 2321 }; 2322 2323 /* network device open function */ 2324 static int sh_eth_open(struct net_device *ndev) 2325 { 2326 struct sh_eth_private *mdp = netdev_priv(ndev); 2327 int ret; 2328 2329 pm_runtime_get_sync(&mdp->pdev->dev); 2330 2331 napi_enable(&mdp->napi); 2332 2333 ret = request_irq(ndev->irq, sh_eth_interrupt, 2334 mdp->cd->irq_flags, ndev->name, ndev); 2335 if (ret) { 2336 netdev_err(ndev, "Can not assign IRQ number\n"); 2337 goto out_napi_off; 2338 } 2339 2340 /* Descriptor set */ 2341 ret = sh_eth_ring_init(ndev); 2342 if (ret) 2343 goto out_free_irq; 2344 2345 /* device init */ 2346 ret = sh_eth_dev_init(ndev); 2347 if (ret) 2348 goto out_free_irq; 2349 2350 /* PHY control start*/ 2351 ret = sh_eth_phy_start(ndev); 2352 if (ret) 2353 goto out_free_irq; 2354 2355 netif_start_queue(ndev); 2356 2357 mdp->is_opened = 1; 2358 2359 return ret; 2360 2361 out_free_irq: 2362 free_irq(ndev->irq, ndev); 2363 out_napi_off: 2364 napi_disable(&mdp->napi); 2365 pm_runtime_put_sync(&mdp->pdev->dev); 2366 return ret; 2367 } 2368 2369 /* Timeout function */ 2370 static void sh_eth_tx_timeout(struct net_device *ndev) 2371 { 2372 struct sh_eth_private *mdp = netdev_priv(ndev); 2373 struct sh_eth_rxdesc *rxdesc; 2374 int i; 2375 2376 netif_stop_queue(ndev); 2377 2378 netif_err(mdp, timer, ndev, 2379 "transmit timed out, status %8.8x, resetting...\n", 2380 sh_eth_read(ndev, EESR)); 2381 2382 /* tx_errors count up */ 2383 ndev->stats.tx_errors++; 2384 2385 /* Free all the skbuffs in the Rx queue. */ 2386 for (i = 0; i < mdp->num_rx_ring; i++) { 2387 rxdesc = &mdp->rx_ring[i]; 2388 rxdesc->status = cpu_to_le32(0); 2389 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2390 dev_kfree_skb(mdp->rx_skbuff[i]); 2391 mdp->rx_skbuff[i] = NULL; 2392 } 2393 for (i = 0; i < mdp->num_tx_ring; i++) { 2394 dev_kfree_skb(mdp->tx_skbuff[i]); 2395 mdp->tx_skbuff[i] = NULL; 2396 } 2397 2398 /* device init */ 2399 sh_eth_dev_init(ndev); 2400 2401 netif_start_queue(ndev); 2402 } 2403 2404 /* Packet transmit function */ 2405 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2406 { 2407 struct sh_eth_private *mdp = netdev_priv(ndev); 2408 struct sh_eth_txdesc *txdesc; 2409 dma_addr_t dma_addr; 2410 u32 entry; 2411 unsigned long flags; 2412 2413 spin_lock_irqsave(&mdp->lock, flags); 2414 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2415 if (!sh_eth_txfree(ndev)) { 2416 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2417 netif_stop_queue(ndev); 2418 spin_unlock_irqrestore(&mdp->lock, flags); 2419 return NETDEV_TX_BUSY; 2420 } 2421 } 2422 spin_unlock_irqrestore(&mdp->lock, flags); 2423 2424 if (skb_put_padto(skb, ETH_ZLEN)) 2425 return NETDEV_TX_OK; 2426 2427 entry = mdp->cur_tx % mdp->num_tx_ring; 2428 mdp->tx_skbuff[entry] = skb; 2429 txdesc = &mdp->tx_ring[entry]; 2430 /* soft swap. */ 2431 if (!mdp->cd->hw_swap) 2432 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2433 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len, 2434 DMA_TO_DEVICE); 2435 if (dma_mapping_error(&ndev->dev, dma_addr)) { 2436 kfree_skb(skb); 2437 return NETDEV_TX_OK; 2438 } 2439 txdesc->addr = cpu_to_le32(dma_addr); 2440 txdesc->len = cpu_to_le32(skb->len << 16); 2441 2442 dma_wmb(); /* TACT bit must be set after all the above writes */ 2443 if (entry >= mdp->num_tx_ring - 1) 2444 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2445 else 2446 txdesc->status |= cpu_to_le32(TD_TACT); 2447 2448 mdp->cur_tx++; 2449 2450 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 2451 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 2452 2453 return NETDEV_TX_OK; 2454 } 2455 2456 /* The statistics registers have write-clear behaviour, which means we 2457 * will lose any increment between the read and write. We mitigate 2458 * this by only clearing when we read a non-zero value, so we will 2459 * never falsely report a total of zero. 2460 */ 2461 static void 2462 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2463 { 2464 u32 delta = sh_eth_read(ndev, reg); 2465 2466 if (delta) { 2467 *stat += delta; 2468 sh_eth_write(ndev, 0, reg); 2469 } 2470 } 2471 2472 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2473 { 2474 struct sh_eth_private *mdp = netdev_priv(ndev); 2475 2476 if (sh_eth_is_rz_fast_ether(mdp)) 2477 return &ndev->stats; 2478 2479 if (!mdp->is_opened) 2480 return &ndev->stats; 2481 2482 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2483 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2484 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2485 2486 if (sh_eth_is_gether(mdp)) { 2487 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2488 CERCR); 2489 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2490 CEECR); 2491 } else { 2492 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2493 CNDCR); 2494 } 2495 2496 return &ndev->stats; 2497 } 2498 2499 /* device close function */ 2500 static int sh_eth_close(struct net_device *ndev) 2501 { 2502 struct sh_eth_private *mdp = netdev_priv(ndev); 2503 2504 netif_stop_queue(ndev); 2505 2506 /* Serialise with the interrupt handler and NAPI, then disable 2507 * interrupts. We have to clear the irq_enabled flag first to 2508 * ensure that interrupts won't be re-enabled. 2509 */ 2510 mdp->irq_enabled = false; 2511 synchronize_irq(ndev->irq); 2512 napi_disable(&mdp->napi); 2513 sh_eth_write(ndev, 0x0000, EESIPR); 2514 2515 sh_eth_dev_exit(ndev); 2516 2517 /* PHY Disconnect */ 2518 if (ndev->phydev) { 2519 phy_stop(ndev->phydev); 2520 phy_disconnect(ndev->phydev); 2521 } 2522 2523 free_irq(ndev->irq, ndev); 2524 2525 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2526 sh_eth_ring_free(ndev); 2527 2528 pm_runtime_put_sync(&mdp->pdev->dev); 2529 2530 mdp->is_opened = 0; 2531 2532 return 0; 2533 } 2534 2535 /* ioctl to device function */ 2536 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2537 { 2538 struct phy_device *phydev = ndev->phydev; 2539 2540 if (!netif_running(ndev)) 2541 return -EINVAL; 2542 2543 if (!phydev) 2544 return -ENODEV; 2545 2546 return phy_mii_ioctl(phydev, rq, cmd); 2547 } 2548 2549 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2550 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 2551 int entry) 2552 { 2553 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 2554 } 2555 2556 static u32 sh_eth_tsu_get_post_mask(int entry) 2557 { 2558 return 0x0f << (28 - ((entry % 8) * 4)); 2559 } 2560 2561 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2562 { 2563 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2564 } 2565 2566 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2567 int entry) 2568 { 2569 struct sh_eth_private *mdp = netdev_priv(ndev); 2570 u32 tmp; 2571 void *reg_offset; 2572 2573 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2574 tmp = ioread32(reg_offset); 2575 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 2576 } 2577 2578 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2579 int entry) 2580 { 2581 struct sh_eth_private *mdp = netdev_priv(ndev); 2582 u32 post_mask, ref_mask, tmp; 2583 void *reg_offset; 2584 2585 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2586 post_mask = sh_eth_tsu_get_post_mask(entry); 2587 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2588 2589 tmp = ioread32(reg_offset); 2590 iowrite32(tmp & ~post_mask, reg_offset); 2591 2592 /* If other port enables, the function returns "true" */ 2593 return tmp & ref_mask; 2594 } 2595 2596 static int sh_eth_tsu_busy(struct net_device *ndev) 2597 { 2598 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2599 struct sh_eth_private *mdp = netdev_priv(ndev); 2600 2601 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2602 udelay(10); 2603 timeout--; 2604 if (timeout <= 0) { 2605 netdev_err(ndev, "%s: timeout\n", __func__); 2606 return -ETIMEDOUT; 2607 } 2608 } 2609 2610 return 0; 2611 } 2612 2613 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2614 const u8 *addr) 2615 { 2616 u32 val; 2617 2618 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2619 iowrite32(val, reg); 2620 if (sh_eth_tsu_busy(ndev) < 0) 2621 return -EBUSY; 2622 2623 val = addr[4] << 8 | addr[5]; 2624 iowrite32(val, reg + 4); 2625 if (sh_eth_tsu_busy(ndev) < 0) 2626 return -EBUSY; 2627 2628 return 0; 2629 } 2630 2631 static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2632 { 2633 u32 val; 2634 2635 val = ioread32(reg); 2636 addr[0] = (val >> 24) & 0xff; 2637 addr[1] = (val >> 16) & 0xff; 2638 addr[2] = (val >> 8) & 0xff; 2639 addr[3] = val & 0xff; 2640 val = ioread32(reg + 4); 2641 addr[4] = (val >> 8) & 0xff; 2642 addr[5] = val & 0xff; 2643 } 2644 2645 2646 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2647 { 2648 struct sh_eth_private *mdp = netdev_priv(ndev); 2649 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2650 int i; 2651 u8 c_addr[ETH_ALEN]; 2652 2653 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2654 sh_eth_tsu_read_entry(reg_offset, c_addr); 2655 if (ether_addr_equal(addr, c_addr)) 2656 return i; 2657 } 2658 2659 return -ENOENT; 2660 } 2661 2662 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2663 { 2664 u8 blank[ETH_ALEN]; 2665 int entry; 2666 2667 memset(blank, 0, sizeof(blank)); 2668 entry = sh_eth_tsu_find_entry(ndev, blank); 2669 return (entry < 0) ? -ENOMEM : entry; 2670 } 2671 2672 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2673 int entry) 2674 { 2675 struct sh_eth_private *mdp = netdev_priv(ndev); 2676 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2677 int ret; 2678 u8 blank[ETH_ALEN]; 2679 2680 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2681 ~(1 << (31 - entry)), TSU_TEN); 2682 2683 memset(blank, 0, sizeof(blank)); 2684 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2685 if (ret < 0) 2686 return ret; 2687 return 0; 2688 } 2689 2690 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2691 { 2692 struct sh_eth_private *mdp = netdev_priv(ndev); 2693 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2694 int i, ret; 2695 2696 if (!mdp->cd->tsu) 2697 return 0; 2698 2699 i = sh_eth_tsu_find_entry(ndev, addr); 2700 if (i < 0) { 2701 /* No entry found, create one */ 2702 i = sh_eth_tsu_find_empty(ndev); 2703 if (i < 0) 2704 return -ENOMEM; 2705 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2706 if (ret < 0) 2707 return ret; 2708 2709 /* Enable the entry */ 2710 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2711 (1 << (31 - i)), TSU_TEN); 2712 } 2713 2714 /* Entry found or created, enable POST */ 2715 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2716 2717 return 0; 2718 } 2719 2720 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2721 { 2722 struct sh_eth_private *mdp = netdev_priv(ndev); 2723 int i, ret; 2724 2725 if (!mdp->cd->tsu) 2726 return 0; 2727 2728 i = sh_eth_tsu_find_entry(ndev, addr); 2729 if (i) { 2730 /* Entry found */ 2731 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2732 goto done; 2733 2734 /* Disable the entry if both ports was disabled */ 2735 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2736 if (ret < 0) 2737 return ret; 2738 } 2739 done: 2740 return 0; 2741 } 2742 2743 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2744 { 2745 struct sh_eth_private *mdp = netdev_priv(ndev); 2746 int i, ret; 2747 2748 if (!mdp->cd->tsu) 2749 return 0; 2750 2751 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2752 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2753 continue; 2754 2755 /* Disable the entry if both ports was disabled */ 2756 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2757 if (ret < 0) 2758 return ret; 2759 } 2760 2761 return 0; 2762 } 2763 2764 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2765 { 2766 struct sh_eth_private *mdp = netdev_priv(ndev); 2767 u8 addr[ETH_ALEN]; 2768 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2769 int i; 2770 2771 if (!mdp->cd->tsu) 2772 return; 2773 2774 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2775 sh_eth_tsu_read_entry(reg_offset, addr); 2776 if (is_multicast_ether_addr(addr)) 2777 sh_eth_tsu_del_entry(ndev, addr); 2778 } 2779 } 2780 2781 /* Update promiscuous flag and multicast filter */ 2782 static void sh_eth_set_rx_mode(struct net_device *ndev) 2783 { 2784 struct sh_eth_private *mdp = netdev_priv(ndev); 2785 u32 ecmr_bits; 2786 int mcast_all = 0; 2787 unsigned long flags; 2788 2789 spin_lock_irqsave(&mdp->lock, flags); 2790 /* Initial condition is MCT = 1, PRM = 0. 2791 * Depending on ndev->flags, set PRM or clear MCT 2792 */ 2793 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2794 if (mdp->cd->tsu) 2795 ecmr_bits |= ECMR_MCT; 2796 2797 if (!(ndev->flags & IFF_MULTICAST)) { 2798 sh_eth_tsu_purge_mcast(ndev); 2799 mcast_all = 1; 2800 } 2801 if (ndev->flags & IFF_ALLMULTI) { 2802 sh_eth_tsu_purge_mcast(ndev); 2803 ecmr_bits &= ~ECMR_MCT; 2804 mcast_all = 1; 2805 } 2806 2807 if (ndev->flags & IFF_PROMISC) { 2808 sh_eth_tsu_purge_all(ndev); 2809 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2810 } else if (mdp->cd->tsu) { 2811 struct netdev_hw_addr *ha; 2812 netdev_for_each_mc_addr(ha, ndev) { 2813 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2814 continue; 2815 2816 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2817 if (!mcast_all) { 2818 sh_eth_tsu_purge_mcast(ndev); 2819 ecmr_bits &= ~ECMR_MCT; 2820 mcast_all = 1; 2821 } 2822 } 2823 } 2824 } 2825 2826 /* update the ethernet mode */ 2827 sh_eth_write(ndev, ecmr_bits, ECMR); 2828 2829 spin_unlock_irqrestore(&mdp->lock, flags); 2830 } 2831 2832 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2833 { 2834 if (!mdp->port) 2835 return TSU_VTAG0; 2836 else 2837 return TSU_VTAG1; 2838 } 2839 2840 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2841 __be16 proto, u16 vid) 2842 { 2843 struct sh_eth_private *mdp = netdev_priv(ndev); 2844 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2845 2846 if (unlikely(!mdp->cd->tsu)) 2847 return -EPERM; 2848 2849 /* No filtering if vid = 0 */ 2850 if (!vid) 2851 return 0; 2852 2853 mdp->vlan_num_ids++; 2854 2855 /* The controller has one VLAN tag HW filter. So, if the filter is 2856 * already enabled, the driver disables it and the filte 2857 */ 2858 if (mdp->vlan_num_ids > 1) { 2859 /* disable VLAN filter */ 2860 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2861 return 0; 2862 } 2863 2864 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2865 vtag_reg_index); 2866 2867 return 0; 2868 } 2869 2870 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2871 __be16 proto, u16 vid) 2872 { 2873 struct sh_eth_private *mdp = netdev_priv(ndev); 2874 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2875 2876 if (unlikely(!mdp->cd->tsu)) 2877 return -EPERM; 2878 2879 /* No filtering if vid = 0 */ 2880 if (!vid) 2881 return 0; 2882 2883 mdp->vlan_num_ids--; 2884 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2885 2886 return 0; 2887 } 2888 2889 /* SuperH's TSU register init function */ 2890 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2891 { 2892 if (sh_eth_is_rz_fast_ether(mdp)) { 2893 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2894 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 2895 TSU_FWSLC); /* Enable POST registers */ 2896 return; 2897 } 2898 2899 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2900 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2901 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2902 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2903 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2904 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2905 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2906 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2907 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2908 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2909 if (sh_eth_is_gether(mdp)) { 2910 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2911 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2912 } else { 2913 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2914 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2915 } 2916 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2917 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2918 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2919 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2920 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2921 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2922 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2923 } 2924 2925 /* MDIO bus release function */ 2926 static int sh_mdio_release(struct sh_eth_private *mdp) 2927 { 2928 /* unregister mdio bus */ 2929 mdiobus_unregister(mdp->mii_bus); 2930 2931 /* free bitbang info */ 2932 free_mdio_bitbang(mdp->mii_bus); 2933 2934 return 0; 2935 } 2936 2937 /* MDIO bus init function */ 2938 static int sh_mdio_init(struct sh_eth_private *mdp, 2939 struct sh_eth_plat_data *pd) 2940 { 2941 int ret; 2942 struct bb_info *bitbang; 2943 struct platform_device *pdev = mdp->pdev; 2944 struct device *dev = &mdp->pdev->dev; 2945 2946 /* create bit control struct for PHY */ 2947 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 2948 if (!bitbang) 2949 return -ENOMEM; 2950 2951 /* bitbang init */ 2952 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2953 bitbang->set_gate = pd->set_mdio_gate; 2954 bitbang->ctrl.ops = &bb_ops; 2955 2956 /* MII controller setting */ 2957 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2958 if (!mdp->mii_bus) 2959 return -ENOMEM; 2960 2961 /* Hook up MII support for ethtool */ 2962 mdp->mii_bus->name = "sh_mii"; 2963 mdp->mii_bus->parent = dev; 2964 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2965 pdev->name, pdev->id); 2966 2967 /* register MDIO bus */ 2968 if (dev->of_node) { 2969 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 2970 } else { 2971 if (pd->phy_irq > 0) 2972 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 2973 2974 ret = mdiobus_register(mdp->mii_bus); 2975 } 2976 2977 if (ret) 2978 goto out_free_bus; 2979 2980 return 0; 2981 2982 out_free_bus: 2983 free_mdio_bitbang(mdp->mii_bus); 2984 return ret; 2985 } 2986 2987 static const u16 *sh_eth_get_register_offset(int register_type) 2988 { 2989 const u16 *reg_offset = NULL; 2990 2991 switch (register_type) { 2992 case SH_ETH_REG_GIGABIT: 2993 reg_offset = sh_eth_offset_gigabit; 2994 break; 2995 case SH_ETH_REG_FAST_RZ: 2996 reg_offset = sh_eth_offset_fast_rz; 2997 break; 2998 case SH_ETH_REG_FAST_RCAR: 2999 reg_offset = sh_eth_offset_fast_rcar; 3000 break; 3001 case SH_ETH_REG_FAST_SH4: 3002 reg_offset = sh_eth_offset_fast_sh4; 3003 break; 3004 case SH_ETH_REG_FAST_SH3_SH2: 3005 reg_offset = sh_eth_offset_fast_sh3_sh2; 3006 break; 3007 } 3008 3009 return reg_offset; 3010 } 3011 3012 static const struct net_device_ops sh_eth_netdev_ops = { 3013 .ndo_open = sh_eth_open, 3014 .ndo_stop = sh_eth_close, 3015 .ndo_start_xmit = sh_eth_start_xmit, 3016 .ndo_get_stats = sh_eth_get_stats, 3017 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3018 .ndo_tx_timeout = sh_eth_tx_timeout, 3019 .ndo_do_ioctl = sh_eth_do_ioctl, 3020 .ndo_validate_addr = eth_validate_addr, 3021 .ndo_set_mac_address = eth_mac_addr, 3022 }; 3023 3024 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3025 .ndo_open = sh_eth_open, 3026 .ndo_stop = sh_eth_close, 3027 .ndo_start_xmit = sh_eth_start_xmit, 3028 .ndo_get_stats = sh_eth_get_stats, 3029 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3030 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3031 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3032 .ndo_tx_timeout = sh_eth_tx_timeout, 3033 .ndo_do_ioctl = sh_eth_do_ioctl, 3034 .ndo_validate_addr = eth_validate_addr, 3035 .ndo_set_mac_address = eth_mac_addr, 3036 }; 3037 3038 #ifdef CONFIG_OF 3039 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3040 { 3041 struct device_node *np = dev->of_node; 3042 struct sh_eth_plat_data *pdata; 3043 const char *mac_addr; 3044 3045 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3046 if (!pdata) 3047 return NULL; 3048 3049 pdata->phy_interface = of_get_phy_mode(np); 3050 3051 mac_addr = of_get_mac_address(np); 3052 if (mac_addr) 3053 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 3054 3055 pdata->no_ether_link = 3056 of_property_read_bool(np, "renesas,no-ether-link"); 3057 pdata->ether_link_active_low = 3058 of_property_read_bool(np, "renesas,ether-link-active-low"); 3059 3060 return pdata; 3061 } 3062 3063 static const struct of_device_id sh_eth_match_table[] = { 3064 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3065 { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data }, 3066 { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data }, 3067 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data }, 3068 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data }, 3069 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data }, 3070 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data }, 3071 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data }, 3072 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data }, 3073 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3074 { } 3075 }; 3076 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3077 #else 3078 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3079 { 3080 return NULL; 3081 } 3082 #endif 3083 3084 static int sh_eth_drv_probe(struct platform_device *pdev) 3085 { 3086 struct resource *res; 3087 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3088 const struct platform_device_id *id = platform_get_device_id(pdev); 3089 struct sh_eth_private *mdp; 3090 struct net_device *ndev; 3091 int ret, devno; 3092 3093 /* get base addr */ 3094 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3095 3096 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3097 if (!ndev) 3098 return -ENOMEM; 3099 3100 pm_runtime_enable(&pdev->dev); 3101 pm_runtime_get_sync(&pdev->dev); 3102 3103 devno = pdev->id; 3104 if (devno < 0) 3105 devno = 0; 3106 3107 ret = platform_get_irq(pdev, 0); 3108 if (ret < 0) 3109 goto out_release; 3110 ndev->irq = ret; 3111 3112 SET_NETDEV_DEV(ndev, &pdev->dev); 3113 3114 mdp = netdev_priv(ndev); 3115 mdp->num_tx_ring = TX_RING_SIZE; 3116 mdp->num_rx_ring = RX_RING_SIZE; 3117 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3118 if (IS_ERR(mdp->addr)) { 3119 ret = PTR_ERR(mdp->addr); 3120 goto out_release; 3121 } 3122 3123 /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */ 3124 mdp->clk = devm_clk_get(&pdev->dev, NULL); 3125 if (IS_ERR(mdp->clk)) 3126 mdp->clk = NULL; 3127 3128 ndev->base_addr = res->start; 3129 3130 spin_lock_init(&mdp->lock); 3131 mdp->pdev = pdev; 3132 3133 if (pdev->dev.of_node) 3134 pd = sh_eth_parse_dt(&pdev->dev); 3135 if (!pd) { 3136 dev_err(&pdev->dev, "no platform data\n"); 3137 ret = -EINVAL; 3138 goto out_release; 3139 } 3140 3141 /* get PHY ID */ 3142 mdp->phy_id = pd->phy; 3143 mdp->phy_interface = pd->phy_interface; 3144 mdp->no_ether_link = pd->no_ether_link; 3145 mdp->ether_link_active_low = pd->ether_link_active_low; 3146 3147 /* set cpu data */ 3148 if (id) 3149 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3150 else 3151 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3152 3153 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3154 if (!mdp->reg_offset) { 3155 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3156 mdp->cd->register_type); 3157 ret = -EINVAL; 3158 goto out_release; 3159 } 3160 sh_eth_set_default_cpu_data(mdp->cd); 3161 3162 /* set function */ 3163 if (mdp->cd->tsu) 3164 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3165 else 3166 ndev->netdev_ops = &sh_eth_netdev_ops; 3167 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3168 ndev->watchdog_timeo = TX_TIMEOUT; 3169 3170 /* debug message level */ 3171 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3172 3173 /* read and set MAC address */ 3174 read_mac_address(ndev, pd->mac_addr); 3175 if (!is_valid_ether_addr(ndev->dev_addr)) { 3176 dev_warn(&pdev->dev, 3177 "no valid MAC address supplied, using a random one.\n"); 3178 eth_hw_addr_random(ndev); 3179 } 3180 3181 /* ioremap the TSU registers */ 3182 if (mdp->cd->tsu) { 3183 struct resource *rtsu; 3184 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3185 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu); 3186 if (IS_ERR(mdp->tsu_addr)) { 3187 ret = PTR_ERR(mdp->tsu_addr); 3188 goto out_release; 3189 } 3190 mdp->port = devno % 2; 3191 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 3192 } 3193 3194 /* initialize first or needed device */ 3195 if (!devno || pd->needs_init) { 3196 if (mdp->cd->chip_reset) 3197 mdp->cd->chip_reset(ndev); 3198 3199 if (mdp->cd->tsu) { 3200 /* TSU init (Init only)*/ 3201 sh_eth_tsu_init(mdp); 3202 } 3203 } 3204 3205 if (mdp->cd->rmiimode) 3206 sh_eth_write(ndev, 0x1, RMIIMODE); 3207 3208 /* MDIO bus init */ 3209 ret = sh_mdio_init(mdp, pd); 3210 if (ret) { 3211 dev_err(&ndev->dev, "failed to initialise MDIO\n"); 3212 goto out_release; 3213 } 3214 3215 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3216 3217 /* network device register */ 3218 ret = register_netdev(ndev); 3219 if (ret) 3220 goto out_napi_del; 3221 3222 if (mdp->cd->magic && mdp->clk) 3223 device_set_wakeup_capable(&pdev->dev, 1); 3224 3225 /* print device information */ 3226 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3227 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3228 3229 pm_runtime_put(&pdev->dev); 3230 platform_set_drvdata(pdev, ndev); 3231 3232 return ret; 3233 3234 out_napi_del: 3235 netif_napi_del(&mdp->napi); 3236 sh_mdio_release(mdp); 3237 3238 out_release: 3239 /* net_dev free */ 3240 if (ndev) 3241 free_netdev(ndev); 3242 3243 pm_runtime_put(&pdev->dev); 3244 pm_runtime_disable(&pdev->dev); 3245 return ret; 3246 } 3247 3248 static int sh_eth_drv_remove(struct platform_device *pdev) 3249 { 3250 struct net_device *ndev = platform_get_drvdata(pdev); 3251 struct sh_eth_private *mdp = netdev_priv(ndev); 3252 3253 unregister_netdev(ndev); 3254 netif_napi_del(&mdp->napi); 3255 sh_mdio_release(mdp); 3256 pm_runtime_disable(&pdev->dev); 3257 free_netdev(ndev); 3258 3259 return 0; 3260 } 3261 3262 #ifdef CONFIG_PM 3263 #ifdef CONFIG_PM_SLEEP 3264 static int sh_eth_wol_setup(struct net_device *ndev) 3265 { 3266 struct sh_eth_private *mdp = netdev_priv(ndev); 3267 3268 /* Only allow ECI interrupts */ 3269 synchronize_irq(ndev->irq); 3270 napi_disable(&mdp->napi); 3271 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3272 3273 /* Enable MagicPacket */ 3274 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3275 3276 /* Increased clock usage so device won't be suspended */ 3277 clk_enable(mdp->clk); 3278 3279 return enable_irq_wake(ndev->irq); 3280 } 3281 3282 static int sh_eth_wol_restore(struct net_device *ndev) 3283 { 3284 struct sh_eth_private *mdp = netdev_priv(ndev); 3285 int ret; 3286 3287 napi_enable(&mdp->napi); 3288 3289 /* Disable MagicPacket */ 3290 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3291 3292 /* The device needs to be reset to restore MagicPacket logic 3293 * for next wakeup. If we close and open the device it will 3294 * both be reset and all registers restored. This is what 3295 * happens during suspend and resume without WoL enabled. 3296 */ 3297 ret = sh_eth_close(ndev); 3298 if (ret < 0) 3299 return ret; 3300 ret = sh_eth_open(ndev); 3301 if (ret < 0) 3302 return ret; 3303 3304 /* Restore clock usage count */ 3305 clk_disable(mdp->clk); 3306 3307 return disable_irq_wake(ndev->irq); 3308 } 3309 3310 static int sh_eth_suspend(struct device *dev) 3311 { 3312 struct net_device *ndev = dev_get_drvdata(dev); 3313 struct sh_eth_private *mdp = netdev_priv(ndev); 3314 int ret = 0; 3315 3316 if (!netif_running(ndev)) 3317 return 0; 3318 3319 netif_device_detach(ndev); 3320 3321 if (mdp->wol_enabled) 3322 ret = sh_eth_wol_setup(ndev); 3323 else 3324 ret = sh_eth_close(ndev); 3325 3326 return ret; 3327 } 3328 3329 static int sh_eth_resume(struct device *dev) 3330 { 3331 struct net_device *ndev = dev_get_drvdata(dev); 3332 struct sh_eth_private *mdp = netdev_priv(ndev); 3333 int ret = 0; 3334 3335 if (!netif_running(ndev)) 3336 return 0; 3337 3338 if (mdp->wol_enabled) 3339 ret = sh_eth_wol_restore(ndev); 3340 else 3341 ret = sh_eth_open(ndev); 3342 3343 if (ret < 0) 3344 return ret; 3345 3346 netif_device_attach(ndev); 3347 3348 return ret; 3349 } 3350 #endif 3351 3352 static int sh_eth_runtime_nop(struct device *dev) 3353 { 3354 /* Runtime PM callback shared between ->runtime_suspend() 3355 * and ->runtime_resume(). Simply returns success. 3356 * 3357 * This driver re-initializes all registers after 3358 * pm_runtime_get_sync() anyway so there is no need 3359 * to save and restore registers here. 3360 */ 3361 return 0; 3362 } 3363 3364 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3365 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3366 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3367 }; 3368 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3369 #else 3370 #define SH_ETH_PM_OPS NULL 3371 #endif 3372 3373 static struct platform_device_id sh_eth_id_table[] = { 3374 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3375 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3376 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3377 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3378 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3379 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3380 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3381 { } 3382 }; 3383 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3384 3385 static struct platform_driver sh_eth_driver = { 3386 .probe = sh_eth_drv_probe, 3387 .remove = sh_eth_drv_remove, 3388 .id_table = sh_eth_id_table, 3389 .driver = { 3390 .name = CARDNAME, 3391 .pm = SH_ETH_PM_OPS, 3392 .of_match_table = of_match_ptr(sh_eth_match_table), 3393 }, 3394 }; 3395 3396 module_platform_driver(sh_eth_driver); 3397 3398 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3399 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3400 MODULE_LICENSE("GPL v2"); 3401