1 // SPDX-License-Identifier: GPL-2.0 2 /* SuperH Ethernet device driver 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 6 * Copyright (C) 2008-2014 Renesas Solutions Corp. 7 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 8 * Copyright (C) 2014 Codethink Limited 9 */ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/spinlock.h> 14 #include <linux/interrupt.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/etherdevice.h> 17 #include <linux/delay.h> 18 #include <linux/platform_device.h> 19 #include <linux/mdio-bitbang.h> 20 #include <linux/netdevice.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_net.h> 25 #include <linux/phy.h> 26 #include <linux/cache.h> 27 #include <linux/io.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/ethtool.h> 31 #include <linux/if_vlan.h> 32 #include <linux/sh_eth.h> 33 #include <linux/of_mdio.h> 34 35 #include "sh_eth.h" 36 37 #define SH_ETH_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR| \ 41 NETIF_MSG_TX_ERR) 42 43 #define SH_ETH_OFFSET_INVALID ((u16)~0) 44 45 #define SH_ETH_OFFSET_DEFAULTS \ 46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 47 48 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 49 SH_ETH_OFFSET_DEFAULTS, 50 51 [EDSR] = 0x0000, 52 [EDMR] = 0x0400, 53 [EDTRR] = 0x0408, 54 [EDRRR] = 0x0410, 55 [EESR] = 0x0428, 56 [EESIPR] = 0x0430, 57 [TDLAR] = 0x0010, 58 [TDFAR] = 0x0014, 59 [TDFXR] = 0x0018, 60 [TDFFR] = 0x001c, 61 [RDLAR] = 0x0030, 62 [RDFAR] = 0x0034, 63 [RDFXR] = 0x0038, 64 [RDFFR] = 0x003c, 65 [TRSCER] = 0x0438, 66 [RMFCR] = 0x0440, 67 [TFTR] = 0x0448, 68 [FDR] = 0x0450, 69 [RMCR] = 0x0458, 70 [RPADIR] = 0x0460, 71 [FCFTR] = 0x0468, 72 [CSMR] = 0x04E4, 73 74 [ECMR] = 0x0500, 75 [ECSR] = 0x0510, 76 [ECSIPR] = 0x0518, 77 [PIR] = 0x0520, 78 [PSR] = 0x0528, 79 [PIPR] = 0x052c, 80 [RFLR] = 0x0508, 81 [APR] = 0x0554, 82 [MPR] = 0x0558, 83 [PFTCR] = 0x055c, 84 [PFRCR] = 0x0560, 85 [TPAUSER] = 0x0564, 86 [GECMR] = 0x05b0, 87 [BCULR] = 0x05b4, 88 [MAHR] = 0x05c0, 89 [MALR] = 0x05c8, 90 [TROCR] = 0x0700, 91 [CDCR] = 0x0708, 92 [LCCR] = 0x0710, 93 [CEFCR] = 0x0740, 94 [FRECR] = 0x0748, 95 [TSFRCR] = 0x0750, 96 [TLFRCR] = 0x0758, 97 [RFCR] = 0x0760, 98 [CERCR] = 0x0768, 99 [CEECR] = 0x0770, 100 [MAFCR] = 0x0778, 101 [RMII_MII] = 0x0790, 102 103 [ARSTR] = 0x0000, 104 [TSU_CTRST] = 0x0004, 105 [TSU_FWEN0] = 0x0010, 106 [TSU_FWEN1] = 0x0014, 107 [TSU_FCM] = 0x0018, 108 [TSU_BSYSL0] = 0x0020, 109 [TSU_BSYSL1] = 0x0024, 110 [TSU_PRISL0] = 0x0028, 111 [TSU_PRISL1] = 0x002c, 112 [TSU_FWSL0] = 0x0030, 113 [TSU_FWSL1] = 0x0034, 114 [TSU_FWSLC] = 0x0038, 115 [TSU_QTAGM0] = 0x0040, 116 [TSU_QTAGM1] = 0x0044, 117 [TSU_FWSR] = 0x0050, 118 [TSU_FWINMK] = 0x0054, 119 [TSU_ADQT0] = 0x0048, 120 [TSU_ADQT1] = 0x004c, 121 [TSU_VTAG0] = 0x0058, 122 [TSU_VTAG1] = 0x005c, 123 [TSU_ADSBSY] = 0x0060, 124 [TSU_TEN] = 0x0064, 125 [TSU_POST1] = 0x0070, 126 [TSU_POST2] = 0x0074, 127 [TSU_POST3] = 0x0078, 128 [TSU_POST4] = 0x007c, 129 [TSU_ADRH0] = 0x0100, 130 131 [TXNLCR0] = 0x0080, 132 [TXALCR0] = 0x0084, 133 [RXNLCR0] = 0x0088, 134 [RXALCR0] = 0x008c, 135 [FWNLCR0] = 0x0090, 136 [FWALCR0] = 0x0094, 137 [TXNLCR1] = 0x00a0, 138 [TXALCR1] = 0x00a4, 139 [RXNLCR1] = 0x00a8, 140 [RXALCR1] = 0x00ac, 141 [FWNLCR1] = 0x00b0, 142 [FWALCR1] = 0x00b4, 143 }; 144 145 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 146 SH_ETH_OFFSET_DEFAULTS, 147 148 [EDSR] = 0x0000, 149 [EDMR] = 0x0400, 150 [EDTRR] = 0x0408, 151 [EDRRR] = 0x0410, 152 [EESR] = 0x0428, 153 [EESIPR] = 0x0430, 154 [TDLAR] = 0x0010, 155 [TDFAR] = 0x0014, 156 [TDFXR] = 0x0018, 157 [TDFFR] = 0x001c, 158 [RDLAR] = 0x0030, 159 [RDFAR] = 0x0034, 160 [RDFXR] = 0x0038, 161 [RDFFR] = 0x003c, 162 [TRSCER] = 0x0438, 163 [RMFCR] = 0x0440, 164 [TFTR] = 0x0448, 165 [FDR] = 0x0450, 166 [RMCR] = 0x0458, 167 [RPADIR] = 0x0460, 168 [FCFTR] = 0x0468, 169 [CSMR] = 0x04E4, 170 171 [ECMR] = 0x0500, 172 [RFLR] = 0x0508, 173 [ECSR] = 0x0510, 174 [ECSIPR] = 0x0518, 175 [PIR] = 0x0520, 176 [APR] = 0x0554, 177 [MPR] = 0x0558, 178 [PFTCR] = 0x055c, 179 [PFRCR] = 0x0560, 180 [TPAUSER] = 0x0564, 181 [MAHR] = 0x05c0, 182 [MALR] = 0x05c8, 183 [CEFCR] = 0x0740, 184 [FRECR] = 0x0748, 185 [TSFRCR] = 0x0750, 186 [TLFRCR] = 0x0758, 187 [RFCR] = 0x0760, 188 [MAFCR] = 0x0778, 189 190 [ARSTR] = 0x0000, 191 [TSU_CTRST] = 0x0004, 192 [TSU_FWSLC] = 0x0038, 193 [TSU_VTAG0] = 0x0058, 194 [TSU_ADSBSY] = 0x0060, 195 [TSU_TEN] = 0x0064, 196 [TSU_POST1] = 0x0070, 197 [TSU_POST2] = 0x0074, 198 [TSU_POST3] = 0x0078, 199 [TSU_POST4] = 0x007c, 200 [TSU_ADRH0] = 0x0100, 201 202 [TXNLCR0] = 0x0080, 203 [TXALCR0] = 0x0084, 204 [RXNLCR0] = 0x0088, 205 [RXALCR0] = 0x008C, 206 }; 207 208 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 209 SH_ETH_OFFSET_DEFAULTS, 210 211 [ECMR] = 0x0300, 212 [RFLR] = 0x0308, 213 [ECSR] = 0x0310, 214 [ECSIPR] = 0x0318, 215 [PIR] = 0x0320, 216 [PSR] = 0x0328, 217 [RDMLR] = 0x0340, 218 [IPGR] = 0x0350, 219 [APR] = 0x0354, 220 [MPR] = 0x0358, 221 [RFCF] = 0x0360, 222 [TPAUSER] = 0x0364, 223 [TPAUSECR] = 0x0368, 224 [MAHR] = 0x03c0, 225 [MALR] = 0x03c8, 226 [TROCR] = 0x03d0, 227 [CDCR] = 0x03d4, 228 [LCCR] = 0x03d8, 229 [CNDCR] = 0x03dc, 230 [CEFCR] = 0x03e4, 231 [FRECR] = 0x03e8, 232 [TSFRCR] = 0x03ec, 233 [TLFRCR] = 0x03f0, 234 [RFCR] = 0x03f4, 235 [MAFCR] = 0x03f8, 236 237 [EDMR] = 0x0200, 238 [EDTRR] = 0x0208, 239 [EDRRR] = 0x0210, 240 [TDLAR] = 0x0218, 241 [RDLAR] = 0x0220, 242 [EESR] = 0x0228, 243 [EESIPR] = 0x0230, 244 [TRSCER] = 0x0238, 245 [RMFCR] = 0x0240, 246 [TFTR] = 0x0248, 247 [FDR] = 0x0250, 248 [RMCR] = 0x0258, 249 [TFUCR] = 0x0264, 250 [RFOCR] = 0x0268, 251 [RMIIMODE] = 0x026c, 252 [FCFTR] = 0x0270, 253 [TRIMD] = 0x027c, 254 }; 255 256 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 257 SH_ETH_OFFSET_DEFAULTS, 258 259 [ECMR] = 0x0100, 260 [RFLR] = 0x0108, 261 [ECSR] = 0x0110, 262 [ECSIPR] = 0x0118, 263 [PIR] = 0x0120, 264 [PSR] = 0x0128, 265 [RDMLR] = 0x0140, 266 [IPGR] = 0x0150, 267 [APR] = 0x0154, 268 [MPR] = 0x0158, 269 [TPAUSER] = 0x0164, 270 [RFCF] = 0x0160, 271 [TPAUSECR] = 0x0168, 272 [BCFRR] = 0x016c, 273 [MAHR] = 0x01c0, 274 [MALR] = 0x01c8, 275 [TROCR] = 0x01d0, 276 [CDCR] = 0x01d4, 277 [LCCR] = 0x01d8, 278 [CNDCR] = 0x01dc, 279 [CEFCR] = 0x01e4, 280 [FRECR] = 0x01e8, 281 [TSFRCR] = 0x01ec, 282 [TLFRCR] = 0x01f0, 283 [RFCR] = 0x01f4, 284 [MAFCR] = 0x01f8, 285 [RTRATE] = 0x01fc, 286 287 [EDMR] = 0x0000, 288 [EDTRR] = 0x0008, 289 [EDRRR] = 0x0010, 290 [TDLAR] = 0x0018, 291 [RDLAR] = 0x0020, 292 [EESR] = 0x0028, 293 [EESIPR] = 0x0030, 294 [TRSCER] = 0x0038, 295 [RMFCR] = 0x0040, 296 [TFTR] = 0x0048, 297 [FDR] = 0x0050, 298 [RMCR] = 0x0058, 299 [TFUCR] = 0x0064, 300 [RFOCR] = 0x0068, 301 [FCFTR] = 0x0070, 302 [RPADIR] = 0x0078, 303 [TRIMD] = 0x007c, 304 [RBWAR] = 0x00c8, 305 [RDFAR] = 0x00cc, 306 [TBRAR] = 0x00d4, 307 [TDFAR] = 0x00d8, 308 }; 309 310 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 311 SH_ETH_OFFSET_DEFAULTS, 312 313 [EDMR] = 0x0000, 314 [EDTRR] = 0x0004, 315 [EDRRR] = 0x0008, 316 [TDLAR] = 0x000c, 317 [RDLAR] = 0x0010, 318 [EESR] = 0x0014, 319 [EESIPR] = 0x0018, 320 [TRSCER] = 0x001c, 321 [RMFCR] = 0x0020, 322 [TFTR] = 0x0024, 323 [FDR] = 0x0028, 324 [RMCR] = 0x002c, 325 [EDOCR] = 0x0030, 326 [FCFTR] = 0x0034, 327 [RPADIR] = 0x0038, 328 [TRIMD] = 0x003c, 329 [RBWAR] = 0x0040, 330 [RDFAR] = 0x0044, 331 [TBRAR] = 0x004c, 332 [TDFAR] = 0x0050, 333 334 [ECMR] = 0x0160, 335 [ECSR] = 0x0164, 336 [ECSIPR] = 0x0168, 337 [PIR] = 0x016c, 338 [MAHR] = 0x0170, 339 [MALR] = 0x0174, 340 [RFLR] = 0x0178, 341 [PSR] = 0x017c, 342 [TROCR] = 0x0180, 343 [CDCR] = 0x0184, 344 [LCCR] = 0x0188, 345 [CNDCR] = 0x018c, 346 [CEFCR] = 0x0194, 347 [FRECR] = 0x0198, 348 [TSFRCR] = 0x019c, 349 [TLFRCR] = 0x01a0, 350 [RFCR] = 0x01a4, 351 [MAFCR] = 0x01a8, 352 [IPGR] = 0x01b4, 353 [APR] = 0x01b8, 354 [MPR] = 0x01bc, 355 [TPAUSER] = 0x01c4, 356 [BCFR] = 0x01cc, 357 358 [ARSTR] = 0x0000, 359 [TSU_CTRST] = 0x0004, 360 [TSU_FWEN0] = 0x0010, 361 [TSU_FWEN1] = 0x0014, 362 [TSU_FCM] = 0x0018, 363 [TSU_BSYSL0] = 0x0020, 364 [TSU_BSYSL1] = 0x0024, 365 [TSU_PRISL0] = 0x0028, 366 [TSU_PRISL1] = 0x002c, 367 [TSU_FWSL0] = 0x0030, 368 [TSU_FWSL1] = 0x0034, 369 [TSU_FWSLC] = 0x0038, 370 [TSU_QTAGM0] = 0x0040, 371 [TSU_QTAGM1] = 0x0044, 372 [TSU_ADQT0] = 0x0048, 373 [TSU_ADQT1] = 0x004c, 374 [TSU_FWSR] = 0x0050, 375 [TSU_FWINMK] = 0x0054, 376 [TSU_ADSBSY] = 0x0060, 377 [TSU_TEN] = 0x0064, 378 [TSU_POST1] = 0x0070, 379 [TSU_POST2] = 0x0074, 380 [TSU_POST3] = 0x0078, 381 [TSU_POST4] = 0x007c, 382 383 [TXNLCR0] = 0x0080, 384 [TXALCR0] = 0x0084, 385 [RXNLCR0] = 0x0088, 386 [RXALCR0] = 0x008c, 387 [FWNLCR0] = 0x0090, 388 [FWALCR0] = 0x0094, 389 [TXNLCR1] = 0x00a0, 390 [TXALCR1] = 0x00a4, 391 [RXNLCR1] = 0x00a8, 392 [RXALCR1] = 0x00ac, 393 [FWNLCR1] = 0x00b0, 394 [FWALCR1] = 0x00b4, 395 396 [TSU_ADRH0] = 0x0100, 397 }; 398 399 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 400 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 401 402 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 403 { 404 struct sh_eth_private *mdp = netdev_priv(ndev); 405 u16 offset = mdp->reg_offset[enum_index]; 406 407 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 408 return; 409 410 iowrite32(data, mdp->addr + offset); 411 } 412 413 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 414 { 415 struct sh_eth_private *mdp = netdev_priv(ndev); 416 u16 offset = mdp->reg_offset[enum_index]; 417 418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 419 return ~0U; 420 421 return ioread32(mdp->addr + offset); 422 } 423 424 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 425 u32 set) 426 { 427 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 428 enum_index); 429 } 430 431 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index) 432 { 433 return mdp->reg_offset[enum_index]; 434 } 435 436 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data, 437 int enum_index) 438 { 439 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 440 441 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 442 return; 443 444 iowrite32(data, mdp->tsu_addr + offset); 445 } 446 447 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index) 448 { 449 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 450 451 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 452 return ~0U; 453 454 return ioread32(mdp->tsu_addr + offset); 455 } 456 457 static void sh_eth_soft_swap(char *src, int len) 458 { 459 #ifdef __LITTLE_ENDIAN 460 u32 *p = (u32 *)src; 461 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32)); 462 463 for (; p < maxp; p++) 464 *p = swab32(*p); 465 #endif 466 } 467 468 static void sh_eth_select_mii(struct net_device *ndev) 469 { 470 struct sh_eth_private *mdp = netdev_priv(ndev); 471 u32 value; 472 473 switch (mdp->phy_interface) { 474 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID: 475 value = 0x3; 476 break; 477 case PHY_INTERFACE_MODE_GMII: 478 value = 0x2; 479 break; 480 case PHY_INTERFACE_MODE_MII: 481 value = 0x1; 482 break; 483 case PHY_INTERFACE_MODE_RMII: 484 value = 0x0; 485 break; 486 default: 487 netdev_warn(ndev, 488 "PHY interface mode was not setup. Set to MII.\n"); 489 value = 0x1; 490 break; 491 } 492 493 sh_eth_write(ndev, value, RMII_MII); 494 } 495 496 static void sh_eth_set_duplex(struct net_device *ndev) 497 { 498 struct sh_eth_private *mdp = netdev_priv(ndev); 499 500 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 501 } 502 503 static void sh_eth_chip_reset(struct net_device *ndev) 504 { 505 struct sh_eth_private *mdp = netdev_priv(ndev); 506 507 /* reset device */ 508 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 509 mdelay(1); 510 } 511 512 static int sh_eth_soft_reset(struct net_device *ndev) 513 { 514 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 515 mdelay(3); 516 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 517 518 return 0; 519 } 520 521 static int sh_eth_check_soft_reset(struct net_device *ndev) 522 { 523 int cnt; 524 525 for (cnt = 100; cnt > 0; cnt--) { 526 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 527 return 0; 528 mdelay(1); 529 } 530 531 netdev_err(ndev, "Device reset failed\n"); 532 return -ETIMEDOUT; 533 } 534 535 static int sh_eth_soft_reset_gether(struct net_device *ndev) 536 { 537 struct sh_eth_private *mdp = netdev_priv(ndev); 538 int ret; 539 540 sh_eth_write(ndev, EDSR_ENALL, EDSR); 541 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 542 543 ret = sh_eth_check_soft_reset(ndev); 544 if (ret) 545 return ret; 546 547 /* Table Init */ 548 sh_eth_write(ndev, 0, TDLAR); 549 sh_eth_write(ndev, 0, TDFAR); 550 sh_eth_write(ndev, 0, TDFXR); 551 sh_eth_write(ndev, 0, TDFFR); 552 sh_eth_write(ndev, 0, RDLAR); 553 sh_eth_write(ndev, 0, RDFAR); 554 sh_eth_write(ndev, 0, RDFXR); 555 sh_eth_write(ndev, 0, RDFFR); 556 557 /* Reset HW CRC register */ 558 if (mdp->cd->csmr) 559 sh_eth_write(ndev, 0, CSMR); 560 561 /* Select MII mode */ 562 if (mdp->cd->select_mii) 563 sh_eth_select_mii(ndev); 564 565 return ret; 566 } 567 568 static void sh_eth_set_rate_gether(struct net_device *ndev) 569 { 570 struct sh_eth_private *mdp = netdev_priv(ndev); 571 572 switch (mdp->speed) { 573 case 10: /* 10BASE */ 574 sh_eth_write(ndev, GECMR_10, GECMR); 575 break; 576 case 100:/* 100BASE */ 577 sh_eth_write(ndev, GECMR_100, GECMR); 578 break; 579 case 1000: /* 1000BASE */ 580 sh_eth_write(ndev, GECMR_1000, GECMR); 581 break; 582 } 583 } 584 585 #ifdef CONFIG_OF 586 /* R7S72100 */ 587 static struct sh_eth_cpu_data r7s72100_data = { 588 .soft_reset = sh_eth_soft_reset_gether, 589 590 .chip_reset = sh_eth_chip_reset, 591 .set_duplex = sh_eth_set_duplex, 592 593 .register_type = SH_ETH_REG_FAST_RZ, 594 595 .edtrr_trns = EDTRR_TRNS_GETHER, 596 .ecsr_value = ECSR_ICD, 597 .ecsipr_value = ECSIPR_ICDIP, 598 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 599 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 600 EESIPR_ECIIP | 601 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 602 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 603 EESIPR_RMAFIP | EESIPR_RRFIP | 604 EESIPR_RTLFIP | EESIPR_RTSFIP | 605 EESIPR_PREIP | EESIPR_CERFIP, 606 607 .tx_check = EESR_TC1 | EESR_FTC, 608 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 609 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 610 EESR_TDE, 611 .fdr_value = 0x0000070f, 612 613 .no_psr = 1, 614 .apr = 1, 615 .mpr = 1, 616 .tpauser = 1, 617 .hw_swap = 1, 618 .rpadir = 1, 619 .no_trimd = 1, 620 .no_ade = 1, 621 .xdfar_rw = 1, 622 .csmr = 1, 623 .rx_csum = 1, 624 .tsu = 1, 625 .no_tx_cntrs = 1, 626 }; 627 628 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 629 { 630 sh_eth_chip_reset(ndev); 631 632 sh_eth_select_mii(ndev); 633 } 634 635 /* R8A7740 */ 636 static struct sh_eth_cpu_data r8a7740_data = { 637 .soft_reset = sh_eth_soft_reset_gether, 638 639 .chip_reset = sh_eth_chip_reset_r8a7740, 640 .set_duplex = sh_eth_set_duplex, 641 .set_rate = sh_eth_set_rate_gether, 642 643 .register_type = SH_ETH_REG_GIGABIT, 644 645 .edtrr_trns = EDTRR_TRNS_GETHER, 646 .ecsr_value = ECSR_ICD | ECSR_MPD, 647 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 648 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 649 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 650 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 651 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 652 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 653 EESIPR_CEEFIP | EESIPR_CELFIP | 654 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 655 EESIPR_PREIP | EESIPR_CERFIP, 656 657 .tx_check = EESR_TC1 | EESR_FTC, 658 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 659 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 660 EESR_TDE, 661 .fdr_value = 0x0000070f, 662 663 .apr = 1, 664 .mpr = 1, 665 .tpauser = 1, 666 .bculr = 1, 667 .hw_swap = 1, 668 .rpadir = 1, 669 .no_trimd = 1, 670 .no_ade = 1, 671 .xdfar_rw = 1, 672 .csmr = 1, 673 .rx_csum = 1, 674 .tsu = 1, 675 .select_mii = 1, 676 .magic = 1, 677 .cexcr = 1, 678 }; 679 680 /* There is CPU dependent code */ 681 static void sh_eth_set_rate_rcar(struct net_device *ndev) 682 { 683 struct sh_eth_private *mdp = netdev_priv(ndev); 684 685 switch (mdp->speed) { 686 case 10: /* 10BASE */ 687 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 688 break; 689 case 100:/* 100BASE */ 690 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 691 break; 692 } 693 } 694 695 /* R-Car Gen1 */ 696 static struct sh_eth_cpu_data rcar_gen1_data = { 697 .soft_reset = sh_eth_soft_reset, 698 699 .set_duplex = sh_eth_set_duplex, 700 .set_rate = sh_eth_set_rate_rcar, 701 702 .register_type = SH_ETH_REG_FAST_RCAR, 703 704 .edtrr_trns = EDTRR_TRNS_ETHER, 705 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 706 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 707 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 708 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 709 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 710 EESIPR_RMAFIP | EESIPR_RRFIP | 711 EESIPR_RTLFIP | EESIPR_RTSFIP | 712 EESIPR_PREIP | EESIPR_CERFIP, 713 714 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 715 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 716 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 717 .fdr_value = 0x00000f0f, 718 719 .apr = 1, 720 .mpr = 1, 721 .tpauser = 1, 722 .hw_swap = 1, 723 .no_xdfar = 1, 724 }; 725 726 /* R-Car Gen2 and RZ/G1 */ 727 static struct sh_eth_cpu_data rcar_gen2_data = { 728 .soft_reset = sh_eth_soft_reset, 729 730 .set_duplex = sh_eth_set_duplex, 731 .set_rate = sh_eth_set_rate_rcar, 732 733 .register_type = SH_ETH_REG_FAST_RCAR, 734 735 .edtrr_trns = EDTRR_TRNS_ETHER, 736 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 737 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 738 ECSIPR_MPDIP, 739 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 740 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 741 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 742 EESIPR_RMAFIP | EESIPR_RRFIP | 743 EESIPR_RTLFIP | EESIPR_RTSFIP | 744 EESIPR_PREIP | EESIPR_CERFIP, 745 746 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 747 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 748 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 749 .fdr_value = 0x00000f0f, 750 751 .trscer_err_mask = DESC_I_RINT8, 752 753 .apr = 1, 754 .mpr = 1, 755 .tpauser = 1, 756 .hw_swap = 1, 757 .no_xdfar = 1, 758 .rmiimode = 1, 759 .magic = 1, 760 }; 761 762 /* R8A77980 */ 763 static struct sh_eth_cpu_data r8a77980_data = { 764 .soft_reset = sh_eth_soft_reset_gether, 765 766 .set_duplex = sh_eth_set_duplex, 767 .set_rate = sh_eth_set_rate_gether, 768 769 .register_type = SH_ETH_REG_GIGABIT, 770 771 .edtrr_trns = EDTRR_TRNS_GETHER, 772 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 773 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 774 ECSIPR_MPDIP, 775 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 776 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 777 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 778 EESIPR_RMAFIP | EESIPR_RRFIP | 779 EESIPR_RTLFIP | EESIPR_RTSFIP | 780 EESIPR_PREIP | EESIPR_CERFIP, 781 782 .tx_check = EESR_FTC | EESR_CD | EESR_TRO, 783 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 784 EESR_RFE | EESR_RDE | EESR_RFRMER | 785 EESR_TFE | EESR_TDE | EESR_ECI, 786 .fdr_value = 0x0000070f, 787 788 .apr = 1, 789 .mpr = 1, 790 .tpauser = 1, 791 .bculr = 1, 792 .hw_swap = 1, 793 .nbst = 1, 794 .rpadir = 1, 795 .no_trimd = 1, 796 .no_ade = 1, 797 .xdfar_rw = 1, 798 .csmr = 1, 799 .rx_csum = 1, 800 .select_mii = 1, 801 .magic = 1, 802 .cexcr = 1, 803 }; 804 805 /* R7S9210 */ 806 static struct sh_eth_cpu_data r7s9210_data = { 807 .soft_reset = sh_eth_soft_reset, 808 809 .set_duplex = sh_eth_set_duplex, 810 .set_rate = sh_eth_set_rate_rcar, 811 812 .register_type = SH_ETH_REG_FAST_SH4, 813 814 .edtrr_trns = EDTRR_TRNS_ETHER, 815 .ecsr_value = ECSR_ICD, 816 .ecsipr_value = ECSIPR_ICDIP, 817 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP | 818 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP | 819 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP | 820 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP | 821 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 822 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP | 823 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP, 824 825 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 826 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 827 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 828 829 .fdr_value = 0x0000070f, 830 831 .apr = 1, 832 .mpr = 1, 833 .tpauser = 1, 834 .hw_swap = 1, 835 .rpadir = 1, 836 .no_ade = 1, 837 .xdfar_rw = 1, 838 }; 839 #endif /* CONFIG_OF */ 840 841 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 842 { 843 struct sh_eth_private *mdp = netdev_priv(ndev); 844 845 switch (mdp->speed) { 846 case 10: /* 10BASE */ 847 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 848 break; 849 case 100:/* 100BASE */ 850 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 851 break; 852 } 853 } 854 855 /* SH7724 */ 856 static struct sh_eth_cpu_data sh7724_data = { 857 .soft_reset = sh_eth_soft_reset, 858 859 .set_duplex = sh_eth_set_duplex, 860 .set_rate = sh_eth_set_rate_sh7724, 861 862 .register_type = SH_ETH_REG_FAST_SH4, 863 864 .edtrr_trns = EDTRR_TRNS_ETHER, 865 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 866 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 867 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 868 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 869 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 870 EESIPR_RMAFIP | EESIPR_RRFIP | 871 EESIPR_RTLFIP | EESIPR_RTSFIP | 872 EESIPR_PREIP | EESIPR_CERFIP, 873 874 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 875 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 876 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 877 878 .apr = 1, 879 .mpr = 1, 880 .tpauser = 1, 881 .hw_swap = 1, 882 .rpadir = 1, 883 }; 884 885 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 886 { 887 struct sh_eth_private *mdp = netdev_priv(ndev); 888 889 switch (mdp->speed) { 890 case 10: /* 10BASE */ 891 sh_eth_write(ndev, 0, RTRATE); 892 break; 893 case 100:/* 100BASE */ 894 sh_eth_write(ndev, 1, RTRATE); 895 break; 896 } 897 } 898 899 /* SH7757 */ 900 static struct sh_eth_cpu_data sh7757_data = { 901 .soft_reset = sh_eth_soft_reset, 902 903 .set_duplex = sh_eth_set_duplex, 904 .set_rate = sh_eth_set_rate_sh7757, 905 906 .register_type = SH_ETH_REG_FAST_SH4, 907 908 .edtrr_trns = EDTRR_TRNS_ETHER, 909 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 910 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 911 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 912 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 913 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 914 EESIPR_CEEFIP | EESIPR_CELFIP | 915 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 916 EESIPR_PREIP | EESIPR_CERFIP, 917 918 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 919 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 920 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 921 922 .irq_flags = IRQF_SHARED, 923 .apr = 1, 924 .mpr = 1, 925 .tpauser = 1, 926 .hw_swap = 1, 927 .no_ade = 1, 928 .rpadir = 1, 929 .rtrate = 1, 930 .dual_port = 1, 931 }; 932 933 #define SH_GIGA_ETH_BASE 0xfee00000UL 934 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 935 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 936 static void sh_eth_chip_reset_giga(struct net_device *ndev) 937 { 938 u32 mahr[2], malr[2]; 939 int i; 940 941 /* save MAHR and MALR */ 942 for (i = 0; i < 2; i++) { 943 malr[i] = ioread32((void *)GIGA_MALR(i)); 944 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 945 } 946 947 sh_eth_chip_reset(ndev); 948 949 /* restore MAHR and MALR */ 950 for (i = 0; i < 2; i++) { 951 iowrite32(malr[i], (void *)GIGA_MALR(i)); 952 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 953 } 954 } 955 956 static void sh_eth_set_rate_giga(struct net_device *ndev) 957 { 958 struct sh_eth_private *mdp = netdev_priv(ndev); 959 960 switch (mdp->speed) { 961 case 10: /* 10BASE */ 962 sh_eth_write(ndev, 0x00000000, GECMR); 963 break; 964 case 100:/* 100BASE */ 965 sh_eth_write(ndev, 0x00000010, GECMR); 966 break; 967 case 1000: /* 1000BASE */ 968 sh_eth_write(ndev, 0x00000020, GECMR); 969 break; 970 } 971 } 972 973 /* SH7757(GETHERC) */ 974 static struct sh_eth_cpu_data sh7757_data_giga = { 975 .soft_reset = sh_eth_soft_reset_gether, 976 977 .chip_reset = sh_eth_chip_reset_giga, 978 .set_duplex = sh_eth_set_duplex, 979 .set_rate = sh_eth_set_rate_giga, 980 981 .register_type = SH_ETH_REG_GIGABIT, 982 983 .edtrr_trns = EDTRR_TRNS_GETHER, 984 .ecsr_value = ECSR_ICD | ECSR_MPD, 985 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 986 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 987 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 988 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 989 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 990 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 991 EESIPR_CEEFIP | EESIPR_CELFIP | 992 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 993 EESIPR_PREIP | EESIPR_CERFIP, 994 995 .tx_check = EESR_TC1 | EESR_FTC, 996 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 997 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 998 EESR_TDE, 999 .fdr_value = 0x0000072f, 1000 1001 .irq_flags = IRQF_SHARED, 1002 .apr = 1, 1003 .mpr = 1, 1004 .tpauser = 1, 1005 .bculr = 1, 1006 .hw_swap = 1, 1007 .rpadir = 1, 1008 .no_trimd = 1, 1009 .no_ade = 1, 1010 .xdfar_rw = 1, 1011 .tsu = 1, 1012 .cexcr = 1, 1013 .dual_port = 1, 1014 }; 1015 1016 /* SH7734 */ 1017 static struct sh_eth_cpu_data sh7734_data = { 1018 .soft_reset = sh_eth_soft_reset_gether, 1019 1020 .chip_reset = sh_eth_chip_reset, 1021 .set_duplex = sh_eth_set_duplex, 1022 .set_rate = sh_eth_set_rate_gether, 1023 1024 .register_type = SH_ETH_REG_GIGABIT, 1025 1026 .edtrr_trns = EDTRR_TRNS_GETHER, 1027 .ecsr_value = ECSR_ICD | ECSR_MPD, 1028 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 1029 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1030 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1031 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1032 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1033 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1034 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1035 EESIPR_PREIP | EESIPR_CERFIP, 1036 1037 .tx_check = EESR_TC1 | EESR_FTC, 1038 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1039 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 1040 EESR_TDE, 1041 1042 .apr = 1, 1043 .mpr = 1, 1044 .tpauser = 1, 1045 .bculr = 1, 1046 .hw_swap = 1, 1047 .no_trimd = 1, 1048 .no_ade = 1, 1049 .xdfar_rw = 1, 1050 .tsu = 1, 1051 .csmr = 1, 1052 .rx_csum = 1, 1053 .select_mii = 1, 1054 .magic = 1, 1055 .cexcr = 1, 1056 }; 1057 1058 /* SH7763 */ 1059 static struct sh_eth_cpu_data sh7763_data = { 1060 .soft_reset = sh_eth_soft_reset_gether, 1061 1062 .chip_reset = sh_eth_chip_reset, 1063 .set_duplex = sh_eth_set_duplex, 1064 .set_rate = sh_eth_set_rate_gether, 1065 1066 .register_type = SH_ETH_REG_GIGABIT, 1067 1068 .edtrr_trns = EDTRR_TRNS_GETHER, 1069 .ecsr_value = ECSR_ICD | ECSR_MPD, 1070 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 1071 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1072 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1073 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1074 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1075 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1076 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1077 EESIPR_PREIP | EESIPR_CERFIP, 1078 1079 .tx_check = EESR_TC1 | EESR_FTC, 1080 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1081 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 1082 1083 .apr = 1, 1084 .mpr = 1, 1085 .tpauser = 1, 1086 .bculr = 1, 1087 .hw_swap = 1, 1088 .no_trimd = 1, 1089 .no_ade = 1, 1090 .xdfar_rw = 1, 1091 .tsu = 1, 1092 .irq_flags = IRQF_SHARED, 1093 .magic = 1, 1094 .cexcr = 1, 1095 .rx_csum = 1, 1096 .dual_port = 1, 1097 }; 1098 1099 static struct sh_eth_cpu_data sh7619_data = { 1100 .soft_reset = sh_eth_soft_reset, 1101 1102 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1103 1104 .edtrr_trns = EDTRR_TRNS_ETHER, 1105 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1106 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1107 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1108 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1109 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1110 EESIPR_CEEFIP | EESIPR_CELFIP | 1111 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1112 EESIPR_PREIP | EESIPR_CERFIP, 1113 1114 .apr = 1, 1115 .mpr = 1, 1116 .tpauser = 1, 1117 .hw_swap = 1, 1118 }; 1119 1120 static struct sh_eth_cpu_data sh771x_data = { 1121 .soft_reset = sh_eth_soft_reset, 1122 1123 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1124 1125 .edtrr_trns = EDTRR_TRNS_ETHER, 1126 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1127 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1128 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1129 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1130 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1131 EESIPR_CEEFIP | EESIPR_CELFIP | 1132 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1133 EESIPR_PREIP | EESIPR_CERFIP, 1134 .tsu = 1, 1135 .dual_port = 1, 1136 }; 1137 1138 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 1139 { 1140 if (!cd->ecsr_value) 1141 cd->ecsr_value = DEFAULT_ECSR_INIT; 1142 1143 if (!cd->ecsipr_value) 1144 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 1145 1146 if (!cd->fcftr_value) 1147 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 1148 DEFAULT_FIFO_F_D_RFD; 1149 1150 if (!cd->fdr_value) 1151 cd->fdr_value = DEFAULT_FDR_INIT; 1152 1153 if (!cd->tx_check) 1154 cd->tx_check = DEFAULT_TX_CHECK; 1155 1156 if (!cd->eesr_err_check) 1157 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 1158 1159 if (!cd->trscer_err_mask) 1160 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 1161 } 1162 1163 static void sh_eth_set_receive_align(struct sk_buff *skb) 1164 { 1165 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1166 1167 if (reserve) 1168 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1169 } 1170 1171 /* Program the hardware MAC address from dev->dev_addr. */ 1172 static void update_mac_address(struct net_device *ndev) 1173 { 1174 sh_eth_write(ndev, 1175 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1176 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1177 sh_eth_write(ndev, 1178 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1179 } 1180 1181 /* Get MAC address from SuperH MAC address register 1182 * 1183 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1184 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1185 * When you want use this device, you must set MAC address in bootloader. 1186 * 1187 */ 1188 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1189 { 1190 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1191 memcpy(ndev->dev_addr, mac, ETH_ALEN); 1192 } else { 1193 u32 mahr = sh_eth_read(ndev, MAHR); 1194 u32 malr = sh_eth_read(ndev, MALR); 1195 1196 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 1197 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 1198 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 1199 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 1200 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 1201 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 1202 } 1203 } 1204 1205 struct bb_info { 1206 void (*set_gate)(void *addr); 1207 struct mdiobb_ctrl ctrl; 1208 void *addr; 1209 }; 1210 1211 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1212 { 1213 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1214 u32 pir; 1215 1216 if (bitbang->set_gate) 1217 bitbang->set_gate(bitbang->addr); 1218 1219 pir = ioread32(bitbang->addr); 1220 if (set) 1221 pir |= mask; 1222 else 1223 pir &= ~mask; 1224 iowrite32(pir, bitbang->addr); 1225 } 1226 1227 /* Data I/O pin control */ 1228 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1229 { 1230 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1231 } 1232 1233 /* Set bit data*/ 1234 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1235 { 1236 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1237 } 1238 1239 /* Get bit data*/ 1240 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1241 { 1242 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1243 1244 if (bitbang->set_gate) 1245 bitbang->set_gate(bitbang->addr); 1246 1247 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1248 } 1249 1250 /* MDC pin control */ 1251 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1252 { 1253 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1254 } 1255 1256 /* mdio bus control struct */ 1257 static struct mdiobb_ops bb_ops = { 1258 .owner = THIS_MODULE, 1259 .set_mdc = sh_mdc_ctrl, 1260 .set_mdio_dir = sh_mmd_ctrl, 1261 .set_mdio_data = sh_set_mdio, 1262 .get_mdio_data = sh_get_mdio, 1263 }; 1264 1265 /* free Tx skb function */ 1266 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) 1267 { 1268 struct sh_eth_private *mdp = netdev_priv(ndev); 1269 struct sh_eth_txdesc *txdesc; 1270 int free_num = 0; 1271 int entry; 1272 bool sent; 1273 1274 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1275 entry = mdp->dirty_tx % mdp->num_tx_ring; 1276 txdesc = &mdp->tx_ring[entry]; 1277 sent = !(txdesc->status & cpu_to_le32(TD_TACT)); 1278 if (sent_only && !sent) 1279 break; 1280 /* TACT bit must be checked before all the following reads */ 1281 dma_rmb(); 1282 netif_info(mdp, tx_done, ndev, 1283 "tx entry %d status 0x%08x\n", 1284 entry, le32_to_cpu(txdesc->status)); 1285 /* Free the original skb. */ 1286 if (mdp->tx_skbuff[entry]) { 1287 dma_unmap_single(&mdp->pdev->dev, 1288 le32_to_cpu(txdesc->addr), 1289 le32_to_cpu(txdesc->len) >> 16, 1290 DMA_TO_DEVICE); 1291 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1292 mdp->tx_skbuff[entry] = NULL; 1293 free_num++; 1294 } 1295 txdesc->status = cpu_to_le32(TD_TFP); 1296 if (entry >= mdp->num_tx_ring - 1) 1297 txdesc->status |= cpu_to_le32(TD_TDLE); 1298 1299 if (sent) { 1300 ndev->stats.tx_packets++; 1301 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1302 } 1303 } 1304 return free_num; 1305 } 1306 1307 /* free skb and descriptor buffer */ 1308 static void sh_eth_ring_free(struct net_device *ndev) 1309 { 1310 struct sh_eth_private *mdp = netdev_priv(ndev); 1311 int ringsize, i; 1312 1313 if (mdp->rx_ring) { 1314 for (i = 0; i < mdp->num_rx_ring; i++) { 1315 if (mdp->rx_skbuff[i]) { 1316 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; 1317 1318 dma_unmap_single(&mdp->pdev->dev, 1319 le32_to_cpu(rxdesc->addr), 1320 ALIGN(mdp->rx_buf_sz, 32), 1321 DMA_FROM_DEVICE); 1322 } 1323 } 1324 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1325 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, 1326 mdp->rx_desc_dma); 1327 mdp->rx_ring = NULL; 1328 } 1329 1330 /* Free Rx skb ringbuffer */ 1331 if (mdp->rx_skbuff) { 1332 for (i = 0; i < mdp->num_rx_ring; i++) 1333 dev_kfree_skb(mdp->rx_skbuff[i]); 1334 } 1335 kfree(mdp->rx_skbuff); 1336 mdp->rx_skbuff = NULL; 1337 1338 if (mdp->tx_ring) { 1339 sh_eth_tx_free(ndev, false); 1340 1341 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1342 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, 1343 mdp->tx_desc_dma); 1344 mdp->tx_ring = NULL; 1345 } 1346 1347 /* Free Tx skb ringbuffer */ 1348 kfree(mdp->tx_skbuff); 1349 mdp->tx_skbuff = NULL; 1350 } 1351 1352 /* format skb and descriptor buffer */ 1353 static void sh_eth_ring_format(struct net_device *ndev) 1354 { 1355 struct sh_eth_private *mdp = netdev_priv(ndev); 1356 int i; 1357 struct sk_buff *skb; 1358 struct sh_eth_rxdesc *rxdesc = NULL; 1359 struct sh_eth_txdesc *txdesc = NULL; 1360 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1361 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1362 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1363 dma_addr_t dma_addr; 1364 u32 buf_len; 1365 1366 mdp->cur_rx = 0; 1367 mdp->cur_tx = 0; 1368 mdp->dirty_rx = 0; 1369 mdp->dirty_tx = 0; 1370 1371 memset(mdp->rx_ring, 0, rx_ringsize); 1372 1373 /* build Rx ring buffer */ 1374 for (i = 0; i < mdp->num_rx_ring; i++) { 1375 /* skb */ 1376 mdp->rx_skbuff[i] = NULL; 1377 skb = netdev_alloc_skb(ndev, skbuff_size); 1378 if (skb == NULL) 1379 break; 1380 sh_eth_set_receive_align(skb); 1381 1382 /* The size of the buffer is a multiple of 32 bytes. */ 1383 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1384 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, 1385 DMA_FROM_DEVICE); 1386 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1387 kfree_skb(skb); 1388 break; 1389 } 1390 mdp->rx_skbuff[i] = skb; 1391 1392 /* RX descriptor */ 1393 rxdesc = &mdp->rx_ring[i]; 1394 rxdesc->len = cpu_to_le32(buf_len << 16); 1395 rxdesc->addr = cpu_to_le32(dma_addr); 1396 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1397 1398 /* Rx descriptor address set */ 1399 if (i == 0) { 1400 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1401 if (mdp->cd->xdfar_rw) 1402 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1403 } 1404 } 1405 1406 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1407 1408 /* Mark the last entry as wrapping the ring. */ 1409 if (rxdesc) 1410 rxdesc->status |= cpu_to_le32(RD_RDLE); 1411 1412 memset(mdp->tx_ring, 0, tx_ringsize); 1413 1414 /* build Tx ring buffer */ 1415 for (i = 0; i < mdp->num_tx_ring; i++) { 1416 mdp->tx_skbuff[i] = NULL; 1417 txdesc = &mdp->tx_ring[i]; 1418 txdesc->status = cpu_to_le32(TD_TFP); 1419 txdesc->len = cpu_to_le32(0); 1420 if (i == 0) { 1421 /* Tx descriptor address set */ 1422 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1423 if (mdp->cd->xdfar_rw) 1424 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1425 } 1426 } 1427 1428 txdesc->status |= cpu_to_le32(TD_TDLE); 1429 } 1430 1431 /* Get skb and descriptor buffer */ 1432 static int sh_eth_ring_init(struct net_device *ndev) 1433 { 1434 struct sh_eth_private *mdp = netdev_priv(ndev); 1435 int rx_ringsize, tx_ringsize; 1436 1437 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1438 * card needs room to do 8 byte alignment, +2 so we can reserve 1439 * the first 2 bytes, and +16 gets room for the status word from the 1440 * card. 1441 */ 1442 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1443 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1444 if (mdp->cd->rpadir) 1445 mdp->rx_buf_sz += NET_IP_ALIGN; 1446 1447 /* Allocate RX and TX skb rings */ 1448 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1449 GFP_KERNEL); 1450 if (!mdp->rx_skbuff) 1451 return -ENOMEM; 1452 1453 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1454 GFP_KERNEL); 1455 if (!mdp->tx_skbuff) 1456 goto ring_free; 1457 1458 /* Allocate all Rx descriptors. */ 1459 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1460 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, 1461 &mdp->rx_desc_dma, GFP_KERNEL); 1462 if (!mdp->rx_ring) 1463 goto ring_free; 1464 1465 mdp->dirty_rx = 0; 1466 1467 /* Allocate all Tx descriptors. */ 1468 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1469 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, 1470 &mdp->tx_desc_dma, GFP_KERNEL); 1471 if (!mdp->tx_ring) 1472 goto ring_free; 1473 return 0; 1474 1475 ring_free: 1476 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1477 sh_eth_ring_free(ndev); 1478 1479 return -ENOMEM; 1480 } 1481 1482 static int sh_eth_dev_init(struct net_device *ndev) 1483 { 1484 struct sh_eth_private *mdp = netdev_priv(ndev); 1485 int ret; 1486 1487 /* Soft Reset */ 1488 ret = mdp->cd->soft_reset(ndev); 1489 if (ret) 1490 return ret; 1491 1492 if (mdp->cd->rmiimode) 1493 sh_eth_write(ndev, 0x1, RMIIMODE); 1494 1495 /* Descriptor format */ 1496 sh_eth_ring_format(ndev); 1497 if (mdp->cd->rpadir) 1498 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR); 1499 1500 /* all sh_eth int mask */ 1501 sh_eth_write(ndev, 0, EESIPR); 1502 1503 #if defined(__LITTLE_ENDIAN) 1504 if (mdp->cd->hw_swap) 1505 sh_eth_write(ndev, EDMR_EL, EDMR); 1506 else 1507 #endif 1508 sh_eth_write(ndev, 0, EDMR); 1509 1510 /* FIFO size set */ 1511 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1512 sh_eth_write(ndev, 0, TFTR); 1513 1514 /* Frame recv control (enable multiple-packets per rx irq) */ 1515 sh_eth_write(ndev, RMCR_RNC, RMCR); 1516 1517 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1518 1519 /* DMA transfer burst mode */ 1520 if (mdp->cd->nbst) 1521 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST); 1522 1523 /* Burst cycle count upper-limit */ 1524 if (mdp->cd->bculr) 1525 sh_eth_write(ndev, 0x800, BCULR); 1526 1527 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1528 1529 if (!mdp->cd->no_trimd) 1530 sh_eth_write(ndev, 0, TRIMD); 1531 1532 /* Recv frame limit set register */ 1533 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1534 RFLR); 1535 1536 sh_eth_modify(ndev, EESR, 0, 0); 1537 mdp->irq_enabled = true; 1538 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1539 1540 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 1541 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1542 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 1543 ECMR_TE | ECMR_RE, ECMR); 1544 1545 if (mdp->cd->set_rate) 1546 mdp->cd->set_rate(ndev); 1547 1548 /* E-MAC Status Register clear */ 1549 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1550 1551 /* E-MAC Interrupt Enable register */ 1552 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1553 1554 /* Set MAC address */ 1555 update_mac_address(ndev); 1556 1557 /* mask reset */ 1558 if (mdp->cd->apr) 1559 sh_eth_write(ndev, 1, APR); 1560 if (mdp->cd->mpr) 1561 sh_eth_write(ndev, 1, MPR); 1562 if (mdp->cd->tpauser) 1563 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1564 1565 /* Setting the Rx mode will start the Rx process. */ 1566 sh_eth_write(ndev, EDRRR_R, EDRRR); 1567 1568 return ret; 1569 } 1570 1571 static void sh_eth_dev_exit(struct net_device *ndev) 1572 { 1573 struct sh_eth_private *mdp = netdev_priv(ndev); 1574 int i; 1575 1576 /* Deactivate all TX descriptors, so DMA should stop at next 1577 * packet boundary if it's currently running 1578 */ 1579 for (i = 0; i < mdp->num_tx_ring; i++) 1580 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1581 1582 /* Disable TX FIFO egress to MAC */ 1583 sh_eth_rcv_snd_disable(ndev); 1584 1585 /* Stop RX DMA at next packet boundary */ 1586 sh_eth_write(ndev, 0, EDRRR); 1587 1588 /* Aside from TX DMA, we can't tell when the hardware is 1589 * really stopped, so we need to reset to make sure. 1590 * Before doing that, wait for long enough to *probably* 1591 * finish transmitting the last packet and poll stats. 1592 */ 1593 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1594 sh_eth_get_stats(ndev); 1595 mdp->cd->soft_reset(ndev); 1596 1597 /* Set the RMII mode again if required */ 1598 if (mdp->cd->rmiimode) 1599 sh_eth_write(ndev, 0x1, RMIIMODE); 1600 1601 /* Set MAC address again */ 1602 update_mac_address(ndev); 1603 } 1604 1605 static void sh_eth_rx_csum(struct sk_buff *skb) 1606 { 1607 u8 *hw_csum; 1608 1609 /* The hardware checksum is 2 bytes appended to packet data */ 1610 if (unlikely(skb->len < sizeof(__sum16))) 1611 return; 1612 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 1613 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 1614 skb->ip_summed = CHECKSUM_COMPLETE; 1615 skb_trim(skb, skb->len - sizeof(__sum16)); 1616 } 1617 1618 /* Packet receive function */ 1619 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1620 { 1621 struct sh_eth_private *mdp = netdev_priv(ndev); 1622 struct sh_eth_rxdesc *rxdesc; 1623 1624 int entry = mdp->cur_rx % mdp->num_rx_ring; 1625 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1626 int limit; 1627 struct sk_buff *skb; 1628 u32 desc_status; 1629 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1630 dma_addr_t dma_addr; 1631 u16 pkt_len; 1632 u32 buf_len; 1633 1634 boguscnt = min(boguscnt, *quota); 1635 limit = boguscnt; 1636 rxdesc = &mdp->rx_ring[entry]; 1637 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1638 /* RACT bit must be checked before all the following reads */ 1639 dma_rmb(); 1640 desc_status = le32_to_cpu(rxdesc->status); 1641 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1642 1643 if (--boguscnt < 0) 1644 break; 1645 1646 netif_info(mdp, rx_status, ndev, 1647 "rx entry %d status 0x%08x len %d\n", 1648 entry, desc_status, pkt_len); 1649 1650 if (!(desc_status & RDFEND)) 1651 ndev->stats.rx_length_errors++; 1652 1653 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1654 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1655 * bit 0. However, in case of the R8A7740 and R7S72100 1656 * the RFS bits are from bit 25 to bit 16. So, the 1657 * driver needs right shifting by 16. 1658 */ 1659 if (mdp->cd->csmr) 1660 desc_status >>= 16; 1661 1662 skb = mdp->rx_skbuff[entry]; 1663 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1664 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1665 ndev->stats.rx_errors++; 1666 if (desc_status & RD_RFS1) 1667 ndev->stats.rx_crc_errors++; 1668 if (desc_status & RD_RFS2) 1669 ndev->stats.rx_frame_errors++; 1670 if (desc_status & RD_RFS3) 1671 ndev->stats.rx_length_errors++; 1672 if (desc_status & RD_RFS4) 1673 ndev->stats.rx_length_errors++; 1674 if (desc_status & RD_RFS6) 1675 ndev->stats.rx_missed_errors++; 1676 if (desc_status & RD_RFS10) 1677 ndev->stats.rx_over_errors++; 1678 } else if (skb) { 1679 dma_addr = le32_to_cpu(rxdesc->addr); 1680 if (!mdp->cd->hw_swap) 1681 sh_eth_soft_swap( 1682 phys_to_virt(ALIGN(dma_addr, 4)), 1683 pkt_len + 2); 1684 mdp->rx_skbuff[entry] = NULL; 1685 if (mdp->cd->rpadir) 1686 skb_reserve(skb, NET_IP_ALIGN); 1687 dma_unmap_single(&mdp->pdev->dev, dma_addr, 1688 ALIGN(mdp->rx_buf_sz, 32), 1689 DMA_FROM_DEVICE); 1690 skb_put(skb, pkt_len); 1691 skb->protocol = eth_type_trans(skb, ndev); 1692 if (ndev->features & NETIF_F_RXCSUM) 1693 sh_eth_rx_csum(skb); 1694 netif_receive_skb(skb); 1695 ndev->stats.rx_packets++; 1696 ndev->stats.rx_bytes += pkt_len; 1697 if (desc_status & RD_RFS8) 1698 ndev->stats.multicast++; 1699 } 1700 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1701 rxdesc = &mdp->rx_ring[entry]; 1702 } 1703 1704 /* Refill the Rx ring buffers. */ 1705 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1706 entry = mdp->dirty_rx % mdp->num_rx_ring; 1707 rxdesc = &mdp->rx_ring[entry]; 1708 /* The size of the buffer is 32 byte boundary. */ 1709 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1710 rxdesc->len = cpu_to_le32(buf_len << 16); 1711 1712 if (mdp->rx_skbuff[entry] == NULL) { 1713 skb = netdev_alloc_skb(ndev, skbuff_size); 1714 if (skb == NULL) 1715 break; /* Better luck next round. */ 1716 sh_eth_set_receive_align(skb); 1717 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, 1718 buf_len, DMA_FROM_DEVICE); 1719 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1720 kfree_skb(skb); 1721 break; 1722 } 1723 mdp->rx_skbuff[entry] = skb; 1724 1725 skb_checksum_none_assert(skb); 1726 rxdesc->addr = cpu_to_le32(dma_addr); 1727 } 1728 dma_wmb(); /* RACT bit must be set after all the above writes */ 1729 if (entry >= mdp->num_rx_ring - 1) 1730 rxdesc->status |= 1731 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1732 else 1733 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1734 } 1735 1736 /* Restart Rx engine if stopped. */ 1737 /* If we don't need to check status, don't. -KDU */ 1738 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1739 /* fix the values for the next receiving if RDE is set */ 1740 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) { 1741 u32 count = (sh_eth_read(ndev, RDFAR) - 1742 sh_eth_read(ndev, RDLAR)) >> 4; 1743 1744 mdp->cur_rx = count; 1745 mdp->dirty_rx = count; 1746 } 1747 sh_eth_write(ndev, EDRRR_R, EDRRR); 1748 } 1749 1750 *quota -= limit - boguscnt - 1; 1751 1752 return *quota <= 0; 1753 } 1754 1755 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1756 { 1757 /* disable tx and rx */ 1758 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1759 } 1760 1761 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1762 { 1763 /* enable tx and rx */ 1764 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1765 } 1766 1767 /* E-MAC interrupt handler */ 1768 static void sh_eth_emac_interrupt(struct net_device *ndev) 1769 { 1770 struct sh_eth_private *mdp = netdev_priv(ndev); 1771 u32 felic_stat; 1772 u32 link_stat; 1773 1774 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1775 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1776 if (felic_stat & ECSR_ICD) 1777 ndev->stats.tx_carrier_errors++; 1778 if (felic_stat & ECSR_MPD) 1779 pm_wakeup_event(&mdp->pdev->dev, 0); 1780 if (felic_stat & ECSR_LCHNG) { 1781 /* Link Changed */ 1782 if (mdp->cd->no_psr || mdp->no_ether_link) 1783 return; 1784 link_stat = sh_eth_read(ndev, PSR); 1785 if (mdp->ether_link_active_low) 1786 link_stat = ~link_stat; 1787 if (!(link_stat & PHY_ST_LINK)) { 1788 sh_eth_rcv_snd_disable(ndev); 1789 } else { 1790 /* Link Up */ 1791 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1792 /* clear int */ 1793 sh_eth_modify(ndev, ECSR, 0, 0); 1794 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1795 /* enable tx and rx */ 1796 sh_eth_rcv_snd_enable(ndev); 1797 } 1798 } 1799 } 1800 1801 /* error control function */ 1802 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1803 { 1804 struct sh_eth_private *mdp = netdev_priv(ndev); 1805 u32 mask; 1806 1807 if (intr_status & EESR_TWB) { 1808 /* Unused write back interrupt */ 1809 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1810 ndev->stats.tx_aborted_errors++; 1811 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1812 } 1813 } 1814 1815 if (intr_status & EESR_RABT) { 1816 /* Receive Abort int */ 1817 if (intr_status & EESR_RFRMER) { 1818 /* Receive Frame Overflow int */ 1819 ndev->stats.rx_frame_errors++; 1820 } 1821 } 1822 1823 if (intr_status & EESR_TDE) { 1824 /* Transmit Descriptor Empty int */ 1825 ndev->stats.tx_fifo_errors++; 1826 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1827 } 1828 1829 if (intr_status & EESR_TFE) { 1830 /* FIFO under flow */ 1831 ndev->stats.tx_fifo_errors++; 1832 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1833 } 1834 1835 if (intr_status & EESR_RDE) { 1836 /* Receive Descriptor Empty int */ 1837 ndev->stats.rx_over_errors++; 1838 } 1839 1840 if (intr_status & EESR_RFE) { 1841 /* Receive FIFO Overflow int */ 1842 ndev->stats.rx_fifo_errors++; 1843 } 1844 1845 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1846 /* Address Error */ 1847 ndev->stats.tx_fifo_errors++; 1848 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1849 } 1850 1851 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1852 if (mdp->cd->no_ade) 1853 mask &= ~EESR_ADE; 1854 if (intr_status & mask) { 1855 /* Tx error */ 1856 u32 edtrr = sh_eth_read(ndev, EDTRR); 1857 1858 /* dmesg */ 1859 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1860 intr_status, mdp->cur_tx, mdp->dirty_tx, 1861 (u32)ndev->state, edtrr); 1862 /* dirty buffer free */ 1863 sh_eth_tx_free(ndev, true); 1864 1865 /* SH7712 BUG */ 1866 if (edtrr ^ mdp->cd->edtrr_trns) { 1867 /* tx dma start */ 1868 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 1869 } 1870 /* wakeup */ 1871 netif_wake_queue(ndev); 1872 } 1873 } 1874 1875 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1876 { 1877 struct net_device *ndev = netdev; 1878 struct sh_eth_private *mdp = netdev_priv(ndev); 1879 struct sh_eth_cpu_data *cd = mdp->cd; 1880 irqreturn_t ret = IRQ_NONE; 1881 u32 intr_status, intr_enable; 1882 1883 spin_lock(&mdp->lock); 1884 1885 /* Get interrupt status */ 1886 intr_status = sh_eth_read(ndev, EESR); 1887 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1888 * enabled since it's the one that comes thru regardless of the mask, 1889 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1890 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1891 * bit... 1892 */ 1893 intr_enable = sh_eth_read(ndev, EESIPR); 1894 intr_status &= intr_enable | EESIPR_ECIIP; 1895 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1896 cd->eesr_err_check)) 1897 ret = IRQ_HANDLED; 1898 else 1899 goto out; 1900 1901 if (unlikely(!mdp->irq_enabled)) { 1902 sh_eth_write(ndev, 0, EESIPR); 1903 goto out; 1904 } 1905 1906 if (intr_status & EESR_RX_CHECK) { 1907 if (napi_schedule_prep(&mdp->napi)) { 1908 /* Mask Rx interrupts */ 1909 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1910 EESIPR); 1911 __napi_schedule(&mdp->napi); 1912 } else { 1913 netdev_warn(ndev, 1914 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1915 intr_status, intr_enable); 1916 } 1917 } 1918 1919 /* Tx Check */ 1920 if (intr_status & cd->tx_check) { 1921 /* Clear Tx interrupts */ 1922 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1923 1924 sh_eth_tx_free(ndev, true); 1925 netif_wake_queue(ndev); 1926 } 1927 1928 /* E-MAC interrupt */ 1929 if (intr_status & EESR_ECI) 1930 sh_eth_emac_interrupt(ndev); 1931 1932 if (intr_status & cd->eesr_err_check) { 1933 /* Clear error interrupts */ 1934 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1935 1936 sh_eth_error(ndev, intr_status); 1937 } 1938 1939 out: 1940 spin_unlock(&mdp->lock); 1941 1942 return ret; 1943 } 1944 1945 static int sh_eth_poll(struct napi_struct *napi, int budget) 1946 { 1947 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1948 napi); 1949 struct net_device *ndev = napi->dev; 1950 int quota = budget; 1951 u32 intr_status; 1952 1953 for (;;) { 1954 intr_status = sh_eth_read(ndev, EESR); 1955 if (!(intr_status & EESR_RX_CHECK)) 1956 break; 1957 /* Clear Rx interrupts */ 1958 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1959 1960 if (sh_eth_rx(ndev, intr_status, "a)) 1961 goto out; 1962 } 1963 1964 napi_complete(napi); 1965 1966 /* Reenable Rx interrupts */ 1967 if (mdp->irq_enabled) 1968 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1969 out: 1970 return budget - quota; 1971 } 1972 1973 /* PHY state control function */ 1974 static void sh_eth_adjust_link(struct net_device *ndev) 1975 { 1976 struct sh_eth_private *mdp = netdev_priv(ndev); 1977 struct phy_device *phydev = ndev->phydev; 1978 unsigned long flags; 1979 int new_state = 0; 1980 1981 spin_lock_irqsave(&mdp->lock, flags); 1982 1983 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1984 if (mdp->cd->no_psr || mdp->no_ether_link) 1985 sh_eth_rcv_snd_disable(ndev); 1986 1987 if (phydev->link) { 1988 if (phydev->duplex != mdp->duplex) { 1989 new_state = 1; 1990 mdp->duplex = phydev->duplex; 1991 if (mdp->cd->set_duplex) 1992 mdp->cd->set_duplex(ndev); 1993 } 1994 1995 if (phydev->speed != mdp->speed) { 1996 new_state = 1; 1997 mdp->speed = phydev->speed; 1998 if (mdp->cd->set_rate) 1999 mdp->cd->set_rate(ndev); 2000 } 2001 if (!mdp->link) { 2002 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 2003 new_state = 1; 2004 mdp->link = phydev->link; 2005 } 2006 } else if (mdp->link) { 2007 new_state = 1; 2008 mdp->link = 0; 2009 mdp->speed = 0; 2010 mdp->duplex = -1; 2011 } 2012 2013 /* Enable TX and RX right over here, if E-MAC change is ignored */ 2014 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link) 2015 sh_eth_rcv_snd_enable(ndev); 2016 2017 spin_unlock_irqrestore(&mdp->lock, flags); 2018 2019 if (new_state && netif_msg_link(mdp)) 2020 phy_print_status(phydev); 2021 } 2022 2023 /* PHY init function */ 2024 static int sh_eth_phy_init(struct net_device *ndev) 2025 { 2026 struct device_node *np = ndev->dev.parent->of_node; 2027 struct sh_eth_private *mdp = netdev_priv(ndev); 2028 struct phy_device *phydev; 2029 2030 mdp->link = 0; 2031 mdp->speed = 0; 2032 mdp->duplex = -1; 2033 2034 /* Try connect to PHY */ 2035 if (np) { 2036 struct device_node *pn; 2037 2038 pn = of_parse_phandle(np, "phy-handle", 0); 2039 phydev = of_phy_connect(ndev, pn, 2040 sh_eth_adjust_link, 0, 2041 mdp->phy_interface); 2042 2043 of_node_put(pn); 2044 if (!phydev) 2045 phydev = ERR_PTR(-ENOENT); 2046 } else { 2047 char phy_id[MII_BUS_ID_SIZE + 3]; 2048 2049 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 2050 mdp->mii_bus->id, mdp->phy_id); 2051 2052 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 2053 mdp->phy_interface); 2054 } 2055 2056 if (IS_ERR(phydev)) { 2057 netdev_err(ndev, "failed to connect PHY\n"); 2058 return PTR_ERR(phydev); 2059 } 2060 2061 /* mask with MAC supported features */ 2062 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) { 2063 int err = phy_set_max_speed(phydev, SPEED_100); 2064 if (err) { 2065 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n"); 2066 phy_disconnect(phydev); 2067 return err; 2068 } 2069 } 2070 2071 phy_attached_info(phydev); 2072 2073 return 0; 2074 } 2075 2076 /* PHY control start function */ 2077 static int sh_eth_phy_start(struct net_device *ndev) 2078 { 2079 int ret; 2080 2081 ret = sh_eth_phy_init(ndev); 2082 if (ret) 2083 return ret; 2084 2085 phy_start(ndev->phydev); 2086 2087 return 0; 2088 } 2089 2090 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 2091 * version must be bumped as well. Just adding registers up to that 2092 * limit is fine, as long as the existing register indices don't 2093 * change. 2094 */ 2095 #define SH_ETH_REG_DUMP_VERSION 1 2096 #define SH_ETH_REG_DUMP_MAX_REGS 256 2097 2098 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 2099 { 2100 struct sh_eth_private *mdp = netdev_priv(ndev); 2101 struct sh_eth_cpu_data *cd = mdp->cd; 2102 u32 *valid_map; 2103 size_t len; 2104 2105 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 2106 2107 /* Dump starts with a bitmap that tells ethtool which 2108 * registers are defined for this chip. 2109 */ 2110 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 2111 if (buf) { 2112 valid_map = buf; 2113 buf += len; 2114 } else { 2115 valid_map = NULL; 2116 } 2117 2118 /* Add a register to the dump, if it has a defined offset. 2119 * This automatically skips most undefined registers, but for 2120 * some it is also necessary to check a capability flag in 2121 * struct sh_eth_cpu_data. 2122 */ 2123 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 2124 #define add_reg_from(reg, read_expr) do { \ 2125 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2126 if (buf) { \ 2127 mark_reg_valid(reg); \ 2128 *buf++ = read_expr; \ 2129 } \ 2130 ++len; \ 2131 } \ 2132 } while (0) 2133 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2134 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2135 2136 add_reg(EDSR); 2137 add_reg(EDMR); 2138 add_reg(EDTRR); 2139 add_reg(EDRRR); 2140 add_reg(EESR); 2141 add_reg(EESIPR); 2142 add_reg(TDLAR); 2143 add_reg(TDFAR); 2144 add_reg(TDFXR); 2145 add_reg(TDFFR); 2146 add_reg(RDLAR); 2147 add_reg(RDFAR); 2148 add_reg(RDFXR); 2149 add_reg(RDFFR); 2150 add_reg(TRSCER); 2151 add_reg(RMFCR); 2152 add_reg(TFTR); 2153 add_reg(FDR); 2154 add_reg(RMCR); 2155 add_reg(TFUCR); 2156 add_reg(RFOCR); 2157 if (cd->rmiimode) 2158 add_reg(RMIIMODE); 2159 add_reg(FCFTR); 2160 if (cd->rpadir) 2161 add_reg(RPADIR); 2162 if (!cd->no_trimd) 2163 add_reg(TRIMD); 2164 add_reg(ECMR); 2165 add_reg(ECSR); 2166 add_reg(ECSIPR); 2167 add_reg(PIR); 2168 if (!cd->no_psr) 2169 add_reg(PSR); 2170 add_reg(RDMLR); 2171 add_reg(RFLR); 2172 add_reg(IPGR); 2173 if (cd->apr) 2174 add_reg(APR); 2175 if (cd->mpr) 2176 add_reg(MPR); 2177 add_reg(RFCR); 2178 add_reg(RFCF); 2179 if (cd->tpauser) 2180 add_reg(TPAUSER); 2181 add_reg(TPAUSECR); 2182 add_reg(GECMR); 2183 if (cd->bculr) 2184 add_reg(BCULR); 2185 add_reg(MAHR); 2186 add_reg(MALR); 2187 add_reg(TROCR); 2188 add_reg(CDCR); 2189 add_reg(LCCR); 2190 add_reg(CNDCR); 2191 add_reg(CEFCR); 2192 add_reg(FRECR); 2193 add_reg(TSFRCR); 2194 add_reg(TLFRCR); 2195 add_reg(CERCR); 2196 add_reg(CEECR); 2197 add_reg(MAFCR); 2198 if (cd->rtrate) 2199 add_reg(RTRATE); 2200 if (cd->csmr) 2201 add_reg(CSMR); 2202 if (cd->select_mii) 2203 add_reg(RMII_MII); 2204 if (cd->tsu) { 2205 add_tsu_reg(ARSTR); 2206 add_tsu_reg(TSU_CTRST); 2207 if (cd->dual_port) { 2208 add_tsu_reg(TSU_FWEN0); 2209 add_tsu_reg(TSU_FWEN1); 2210 add_tsu_reg(TSU_FCM); 2211 add_tsu_reg(TSU_BSYSL0); 2212 add_tsu_reg(TSU_BSYSL1); 2213 add_tsu_reg(TSU_PRISL0); 2214 add_tsu_reg(TSU_PRISL1); 2215 add_tsu_reg(TSU_FWSL0); 2216 add_tsu_reg(TSU_FWSL1); 2217 } 2218 add_tsu_reg(TSU_FWSLC); 2219 if (cd->dual_port) { 2220 add_tsu_reg(TSU_QTAGM0); 2221 add_tsu_reg(TSU_QTAGM1); 2222 add_tsu_reg(TSU_FWSR); 2223 add_tsu_reg(TSU_FWINMK); 2224 add_tsu_reg(TSU_ADQT0); 2225 add_tsu_reg(TSU_ADQT1); 2226 add_tsu_reg(TSU_VTAG0); 2227 add_tsu_reg(TSU_VTAG1); 2228 } 2229 add_tsu_reg(TSU_ADSBSY); 2230 add_tsu_reg(TSU_TEN); 2231 add_tsu_reg(TSU_POST1); 2232 add_tsu_reg(TSU_POST2); 2233 add_tsu_reg(TSU_POST3); 2234 add_tsu_reg(TSU_POST4); 2235 /* This is the start of a table, not just a single register. */ 2236 if (buf) { 2237 unsigned int i; 2238 2239 mark_reg_valid(TSU_ADRH0); 2240 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2241 *buf++ = ioread32(mdp->tsu_addr + 2242 mdp->reg_offset[TSU_ADRH0] + 2243 i * 4); 2244 } 2245 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2246 } 2247 2248 #undef mark_reg_valid 2249 #undef add_reg_from 2250 #undef add_reg 2251 #undef add_tsu_reg 2252 2253 return len * 4; 2254 } 2255 2256 static int sh_eth_get_regs_len(struct net_device *ndev) 2257 { 2258 return __sh_eth_get_regs(ndev, NULL); 2259 } 2260 2261 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2262 void *buf) 2263 { 2264 struct sh_eth_private *mdp = netdev_priv(ndev); 2265 2266 regs->version = SH_ETH_REG_DUMP_VERSION; 2267 2268 pm_runtime_get_sync(&mdp->pdev->dev); 2269 __sh_eth_get_regs(ndev, buf); 2270 pm_runtime_put_sync(&mdp->pdev->dev); 2271 } 2272 2273 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2274 { 2275 struct sh_eth_private *mdp = netdev_priv(ndev); 2276 return mdp->msg_enable; 2277 } 2278 2279 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2280 { 2281 struct sh_eth_private *mdp = netdev_priv(ndev); 2282 mdp->msg_enable = value; 2283 } 2284 2285 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2286 "rx_current", "tx_current", 2287 "rx_dirty", "tx_dirty", 2288 }; 2289 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2290 2291 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2292 { 2293 switch (sset) { 2294 case ETH_SS_STATS: 2295 return SH_ETH_STATS_LEN; 2296 default: 2297 return -EOPNOTSUPP; 2298 } 2299 } 2300 2301 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2302 struct ethtool_stats *stats, u64 *data) 2303 { 2304 struct sh_eth_private *mdp = netdev_priv(ndev); 2305 int i = 0; 2306 2307 /* device-specific stats */ 2308 data[i++] = mdp->cur_rx; 2309 data[i++] = mdp->cur_tx; 2310 data[i++] = mdp->dirty_rx; 2311 data[i++] = mdp->dirty_tx; 2312 } 2313 2314 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2315 { 2316 switch (stringset) { 2317 case ETH_SS_STATS: 2318 memcpy(data, *sh_eth_gstrings_stats, 2319 sizeof(sh_eth_gstrings_stats)); 2320 break; 2321 } 2322 } 2323 2324 static void sh_eth_get_ringparam(struct net_device *ndev, 2325 struct ethtool_ringparam *ring) 2326 { 2327 struct sh_eth_private *mdp = netdev_priv(ndev); 2328 2329 ring->rx_max_pending = RX_RING_MAX; 2330 ring->tx_max_pending = TX_RING_MAX; 2331 ring->rx_pending = mdp->num_rx_ring; 2332 ring->tx_pending = mdp->num_tx_ring; 2333 } 2334 2335 static int sh_eth_set_ringparam(struct net_device *ndev, 2336 struct ethtool_ringparam *ring) 2337 { 2338 struct sh_eth_private *mdp = netdev_priv(ndev); 2339 int ret; 2340 2341 if (ring->tx_pending > TX_RING_MAX || 2342 ring->rx_pending > RX_RING_MAX || 2343 ring->tx_pending < TX_RING_MIN || 2344 ring->rx_pending < RX_RING_MIN) 2345 return -EINVAL; 2346 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2347 return -EINVAL; 2348 2349 if (netif_running(ndev)) { 2350 netif_device_detach(ndev); 2351 netif_tx_disable(ndev); 2352 2353 /* Serialise with the interrupt handler and NAPI, then 2354 * disable interrupts. We have to clear the 2355 * irq_enabled flag first to ensure that interrupts 2356 * won't be re-enabled. 2357 */ 2358 mdp->irq_enabled = false; 2359 synchronize_irq(ndev->irq); 2360 napi_synchronize(&mdp->napi); 2361 sh_eth_write(ndev, 0x0000, EESIPR); 2362 2363 sh_eth_dev_exit(ndev); 2364 2365 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2366 sh_eth_ring_free(ndev); 2367 } 2368 2369 /* Set new parameters */ 2370 mdp->num_rx_ring = ring->rx_pending; 2371 mdp->num_tx_ring = ring->tx_pending; 2372 2373 if (netif_running(ndev)) { 2374 ret = sh_eth_ring_init(ndev); 2375 if (ret < 0) { 2376 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2377 __func__); 2378 return ret; 2379 } 2380 ret = sh_eth_dev_init(ndev); 2381 if (ret < 0) { 2382 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2383 __func__); 2384 return ret; 2385 } 2386 2387 netif_device_attach(ndev); 2388 } 2389 2390 return 0; 2391 } 2392 2393 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2394 { 2395 struct sh_eth_private *mdp = netdev_priv(ndev); 2396 2397 wol->supported = 0; 2398 wol->wolopts = 0; 2399 2400 if (mdp->cd->magic) { 2401 wol->supported = WAKE_MAGIC; 2402 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2403 } 2404 } 2405 2406 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2407 { 2408 struct sh_eth_private *mdp = netdev_priv(ndev); 2409 2410 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC) 2411 return -EOPNOTSUPP; 2412 2413 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2414 2415 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2416 2417 return 0; 2418 } 2419 2420 static const struct ethtool_ops sh_eth_ethtool_ops = { 2421 .get_regs_len = sh_eth_get_regs_len, 2422 .get_regs = sh_eth_get_regs, 2423 .nway_reset = phy_ethtool_nway_reset, 2424 .get_msglevel = sh_eth_get_msglevel, 2425 .set_msglevel = sh_eth_set_msglevel, 2426 .get_link = ethtool_op_get_link, 2427 .get_strings = sh_eth_get_strings, 2428 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2429 .get_sset_count = sh_eth_get_sset_count, 2430 .get_ringparam = sh_eth_get_ringparam, 2431 .set_ringparam = sh_eth_set_ringparam, 2432 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2433 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2434 .get_wol = sh_eth_get_wol, 2435 .set_wol = sh_eth_set_wol, 2436 }; 2437 2438 /* network device open function */ 2439 static int sh_eth_open(struct net_device *ndev) 2440 { 2441 struct sh_eth_private *mdp = netdev_priv(ndev); 2442 int ret; 2443 2444 pm_runtime_get_sync(&mdp->pdev->dev); 2445 2446 napi_enable(&mdp->napi); 2447 2448 ret = request_irq(ndev->irq, sh_eth_interrupt, 2449 mdp->cd->irq_flags, ndev->name, ndev); 2450 if (ret) { 2451 netdev_err(ndev, "Can not assign IRQ number\n"); 2452 goto out_napi_off; 2453 } 2454 2455 /* Descriptor set */ 2456 ret = sh_eth_ring_init(ndev); 2457 if (ret) 2458 goto out_free_irq; 2459 2460 /* device init */ 2461 ret = sh_eth_dev_init(ndev); 2462 if (ret) 2463 goto out_free_irq; 2464 2465 /* PHY control start*/ 2466 ret = sh_eth_phy_start(ndev); 2467 if (ret) 2468 goto out_free_irq; 2469 2470 netif_start_queue(ndev); 2471 2472 mdp->is_opened = 1; 2473 2474 return ret; 2475 2476 out_free_irq: 2477 free_irq(ndev->irq, ndev); 2478 out_napi_off: 2479 napi_disable(&mdp->napi); 2480 pm_runtime_put_sync(&mdp->pdev->dev); 2481 return ret; 2482 } 2483 2484 /* Timeout function */ 2485 static void sh_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue) 2486 { 2487 struct sh_eth_private *mdp = netdev_priv(ndev); 2488 struct sh_eth_rxdesc *rxdesc; 2489 int i; 2490 2491 netif_stop_queue(ndev); 2492 2493 netif_err(mdp, timer, ndev, 2494 "transmit timed out, status %8.8x, resetting...\n", 2495 sh_eth_read(ndev, EESR)); 2496 2497 /* tx_errors count up */ 2498 ndev->stats.tx_errors++; 2499 2500 /* Free all the skbuffs in the Rx queue. */ 2501 for (i = 0; i < mdp->num_rx_ring; i++) { 2502 rxdesc = &mdp->rx_ring[i]; 2503 rxdesc->status = cpu_to_le32(0); 2504 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2505 dev_kfree_skb(mdp->rx_skbuff[i]); 2506 mdp->rx_skbuff[i] = NULL; 2507 } 2508 for (i = 0; i < mdp->num_tx_ring; i++) { 2509 dev_kfree_skb(mdp->tx_skbuff[i]); 2510 mdp->tx_skbuff[i] = NULL; 2511 } 2512 2513 /* device init */ 2514 sh_eth_dev_init(ndev); 2515 2516 netif_start_queue(ndev); 2517 } 2518 2519 /* Packet transmit function */ 2520 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2521 { 2522 struct sh_eth_private *mdp = netdev_priv(ndev); 2523 struct sh_eth_txdesc *txdesc; 2524 dma_addr_t dma_addr; 2525 u32 entry; 2526 unsigned long flags; 2527 2528 spin_lock_irqsave(&mdp->lock, flags); 2529 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2530 if (!sh_eth_tx_free(ndev, true)) { 2531 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2532 netif_stop_queue(ndev); 2533 spin_unlock_irqrestore(&mdp->lock, flags); 2534 return NETDEV_TX_BUSY; 2535 } 2536 } 2537 spin_unlock_irqrestore(&mdp->lock, flags); 2538 2539 if (skb_put_padto(skb, ETH_ZLEN)) 2540 return NETDEV_TX_OK; 2541 2542 entry = mdp->cur_tx % mdp->num_tx_ring; 2543 mdp->tx_skbuff[entry] = skb; 2544 txdesc = &mdp->tx_ring[entry]; 2545 /* soft swap. */ 2546 if (!mdp->cd->hw_swap) 2547 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2548 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, 2549 DMA_TO_DEVICE); 2550 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 2551 kfree_skb(skb); 2552 return NETDEV_TX_OK; 2553 } 2554 txdesc->addr = cpu_to_le32(dma_addr); 2555 txdesc->len = cpu_to_le32(skb->len << 16); 2556 2557 dma_wmb(); /* TACT bit must be set after all the above writes */ 2558 if (entry >= mdp->num_tx_ring - 1) 2559 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2560 else 2561 txdesc->status |= cpu_to_le32(TD_TACT); 2562 2563 mdp->cur_tx++; 2564 2565 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns)) 2566 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 2567 2568 return NETDEV_TX_OK; 2569 } 2570 2571 /* The statistics registers have write-clear behaviour, which means we 2572 * will lose any increment between the read and write. We mitigate 2573 * this by only clearing when we read a non-zero value, so we will 2574 * never falsely report a total of zero. 2575 */ 2576 static void 2577 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2578 { 2579 u32 delta = sh_eth_read(ndev, reg); 2580 2581 if (delta) { 2582 *stat += delta; 2583 sh_eth_write(ndev, 0, reg); 2584 } 2585 } 2586 2587 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2588 { 2589 struct sh_eth_private *mdp = netdev_priv(ndev); 2590 2591 if (mdp->cd->no_tx_cntrs) 2592 return &ndev->stats; 2593 2594 if (!mdp->is_opened) 2595 return &ndev->stats; 2596 2597 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2598 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2599 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2600 2601 if (mdp->cd->cexcr) { 2602 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2603 CERCR); 2604 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2605 CEECR); 2606 } else { 2607 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2608 CNDCR); 2609 } 2610 2611 return &ndev->stats; 2612 } 2613 2614 /* device close function */ 2615 static int sh_eth_close(struct net_device *ndev) 2616 { 2617 struct sh_eth_private *mdp = netdev_priv(ndev); 2618 2619 netif_stop_queue(ndev); 2620 2621 /* Serialise with the interrupt handler and NAPI, then disable 2622 * interrupts. We have to clear the irq_enabled flag first to 2623 * ensure that interrupts won't be re-enabled. 2624 */ 2625 mdp->irq_enabled = false; 2626 synchronize_irq(ndev->irq); 2627 napi_disable(&mdp->napi); 2628 sh_eth_write(ndev, 0x0000, EESIPR); 2629 2630 sh_eth_dev_exit(ndev); 2631 2632 /* PHY Disconnect */ 2633 if (ndev->phydev) { 2634 phy_stop(ndev->phydev); 2635 phy_disconnect(ndev->phydev); 2636 } 2637 2638 free_irq(ndev->irq, ndev); 2639 2640 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2641 sh_eth_ring_free(ndev); 2642 2643 pm_runtime_put_sync(&mdp->pdev->dev); 2644 2645 mdp->is_opened = 0; 2646 2647 return 0; 2648 } 2649 2650 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) 2651 { 2652 if (netif_running(ndev)) 2653 return -EBUSY; 2654 2655 ndev->mtu = new_mtu; 2656 netdev_update_features(ndev); 2657 2658 return 0; 2659 } 2660 2661 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2662 static u32 sh_eth_tsu_get_post_mask(int entry) 2663 { 2664 return 0x0f << (28 - ((entry % 8) * 4)); 2665 } 2666 2667 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2668 { 2669 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2670 } 2671 2672 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2673 int entry) 2674 { 2675 struct sh_eth_private *mdp = netdev_priv(ndev); 2676 int reg = TSU_POST1 + entry / 8; 2677 u32 tmp; 2678 2679 tmp = sh_eth_tsu_read(mdp, reg); 2680 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg); 2681 } 2682 2683 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2684 int entry) 2685 { 2686 struct sh_eth_private *mdp = netdev_priv(ndev); 2687 int reg = TSU_POST1 + entry / 8; 2688 u32 post_mask, ref_mask, tmp; 2689 2690 post_mask = sh_eth_tsu_get_post_mask(entry); 2691 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2692 2693 tmp = sh_eth_tsu_read(mdp, reg); 2694 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg); 2695 2696 /* If other port enables, the function returns "true" */ 2697 return tmp & ref_mask; 2698 } 2699 2700 static int sh_eth_tsu_busy(struct net_device *ndev) 2701 { 2702 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2703 struct sh_eth_private *mdp = netdev_priv(ndev); 2704 2705 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2706 udelay(10); 2707 timeout--; 2708 if (timeout <= 0) { 2709 netdev_err(ndev, "%s: timeout\n", __func__); 2710 return -ETIMEDOUT; 2711 } 2712 } 2713 2714 return 0; 2715 } 2716 2717 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset, 2718 const u8 *addr) 2719 { 2720 struct sh_eth_private *mdp = netdev_priv(ndev); 2721 u32 val; 2722 2723 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2724 iowrite32(val, mdp->tsu_addr + offset); 2725 if (sh_eth_tsu_busy(ndev) < 0) 2726 return -EBUSY; 2727 2728 val = addr[4] << 8 | addr[5]; 2729 iowrite32(val, mdp->tsu_addr + offset + 4); 2730 if (sh_eth_tsu_busy(ndev) < 0) 2731 return -EBUSY; 2732 2733 return 0; 2734 } 2735 2736 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr) 2737 { 2738 struct sh_eth_private *mdp = netdev_priv(ndev); 2739 u32 val; 2740 2741 val = ioread32(mdp->tsu_addr + offset); 2742 addr[0] = (val >> 24) & 0xff; 2743 addr[1] = (val >> 16) & 0xff; 2744 addr[2] = (val >> 8) & 0xff; 2745 addr[3] = val & 0xff; 2746 val = ioread32(mdp->tsu_addr + offset + 4); 2747 addr[4] = (val >> 8) & 0xff; 2748 addr[5] = val & 0xff; 2749 } 2750 2751 2752 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2753 { 2754 struct sh_eth_private *mdp = netdev_priv(ndev); 2755 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2756 int i; 2757 u8 c_addr[ETH_ALEN]; 2758 2759 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2760 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr); 2761 if (ether_addr_equal(addr, c_addr)) 2762 return i; 2763 } 2764 2765 return -ENOENT; 2766 } 2767 2768 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2769 { 2770 u8 blank[ETH_ALEN]; 2771 int entry; 2772 2773 memset(blank, 0, sizeof(blank)); 2774 entry = sh_eth_tsu_find_entry(ndev, blank); 2775 return (entry < 0) ? -ENOMEM : entry; 2776 } 2777 2778 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2779 int entry) 2780 { 2781 struct sh_eth_private *mdp = netdev_priv(ndev); 2782 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2783 int ret; 2784 u8 blank[ETH_ALEN]; 2785 2786 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2787 ~(1 << (31 - entry)), TSU_TEN); 2788 2789 memset(blank, 0, sizeof(blank)); 2790 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2791 if (ret < 0) 2792 return ret; 2793 return 0; 2794 } 2795 2796 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2797 { 2798 struct sh_eth_private *mdp = netdev_priv(ndev); 2799 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2800 int i, ret; 2801 2802 if (!mdp->cd->tsu) 2803 return 0; 2804 2805 i = sh_eth_tsu_find_entry(ndev, addr); 2806 if (i < 0) { 2807 /* No entry found, create one */ 2808 i = sh_eth_tsu_find_empty(ndev); 2809 if (i < 0) 2810 return -ENOMEM; 2811 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2812 if (ret < 0) 2813 return ret; 2814 2815 /* Enable the entry */ 2816 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2817 (1 << (31 - i)), TSU_TEN); 2818 } 2819 2820 /* Entry found or created, enable POST */ 2821 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2822 2823 return 0; 2824 } 2825 2826 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2827 { 2828 struct sh_eth_private *mdp = netdev_priv(ndev); 2829 int i, ret; 2830 2831 if (!mdp->cd->tsu) 2832 return 0; 2833 2834 i = sh_eth_tsu_find_entry(ndev, addr); 2835 if (i) { 2836 /* Entry found */ 2837 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2838 goto done; 2839 2840 /* Disable the entry if both ports was disabled */ 2841 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2842 if (ret < 0) 2843 return ret; 2844 } 2845 done: 2846 return 0; 2847 } 2848 2849 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2850 { 2851 struct sh_eth_private *mdp = netdev_priv(ndev); 2852 int i, ret; 2853 2854 if (!mdp->cd->tsu) 2855 return 0; 2856 2857 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2858 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2859 continue; 2860 2861 /* Disable the entry if both ports was disabled */ 2862 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2863 if (ret < 0) 2864 return ret; 2865 } 2866 2867 return 0; 2868 } 2869 2870 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2871 { 2872 struct sh_eth_private *mdp = netdev_priv(ndev); 2873 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2874 u8 addr[ETH_ALEN]; 2875 int i; 2876 2877 if (!mdp->cd->tsu) 2878 return; 2879 2880 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2881 sh_eth_tsu_read_entry(ndev, reg_offset, addr); 2882 if (is_multicast_ether_addr(addr)) 2883 sh_eth_tsu_del_entry(ndev, addr); 2884 } 2885 } 2886 2887 /* Update promiscuous flag and multicast filter */ 2888 static void sh_eth_set_rx_mode(struct net_device *ndev) 2889 { 2890 struct sh_eth_private *mdp = netdev_priv(ndev); 2891 u32 ecmr_bits; 2892 int mcast_all = 0; 2893 unsigned long flags; 2894 2895 spin_lock_irqsave(&mdp->lock, flags); 2896 /* Initial condition is MCT = 1, PRM = 0. 2897 * Depending on ndev->flags, set PRM or clear MCT 2898 */ 2899 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2900 if (mdp->cd->tsu) 2901 ecmr_bits |= ECMR_MCT; 2902 2903 if (!(ndev->flags & IFF_MULTICAST)) { 2904 sh_eth_tsu_purge_mcast(ndev); 2905 mcast_all = 1; 2906 } 2907 if (ndev->flags & IFF_ALLMULTI) { 2908 sh_eth_tsu_purge_mcast(ndev); 2909 ecmr_bits &= ~ECMR_MCT; 2910 mcast_all = 1; 2911 } 2912 2913 if (ndev->flags & IFF_PROMISC) { 2914 sh_eth_tsu_purge_all(ndev); 2915 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2916 } else if (mdp->cd->tsu) { 2917 struct netdev_hw_addr *ha; 2918 netdev_for_each_mc_addr(ha, ndev) { 2919 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2920 continue; 2921 2922 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2923 if (!mcast_all) { 2924 sh_eth_tsu_purge_mcast(ndev); 2925 ecmr_bits &= ~ECMR_MCT; 2926 mcast_all = 1; 2927 } 2928 } 2929 } 2930 } 2931 2932 /* update the ethernet mode */ 2933 sh_eth_write(ndev, ecmr_bits, ECMR); 2934 2935 spin_unlock_irqrestore(&mdp->lock, flags); 2936 } 2937 2938 static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable) 2939 { 2940 struct sh_eth_private *mdp = netdev_priv(ndev); 2941 unsigned long flags; 2942 2943 spin_lock_irqsave(&mdp->lock, flags); 2944 2945 /* Disable TX and RX */ 2946 sh_eth_rcv_snd_disable(ndev); 2947 2948 /* Modify RX Checksum setting */ 2949 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2950 2951 /* Enable TX and RX */ 2952 sh_eth_rcv_snd_enable(ndev); 2953 2954 spin_unlock_irqrestore(&mdp->lock, flags); 2955 } 2956 2957 static int sh_eth_set_features(struct net_device *ndev, 2958 netdev_features_t features) 2959 { 2960 netdev_features_t changed = ndev->features ^ features; 2961 struct sh_eth_private *mdp = netdev_priv(ndev); 2962 2963 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum) 2964 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2965 2966 ndev->features = features; 2967 2968 return 0; 2969 } 2970 2971 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2972 { 2973 if (!mdp->port) 2974 return TSU_VTAG0; 2975 else 2976 return TSU_VTAG1; 2977 } 2978 2979 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2980 __be16 proto, u16 vid) 2981 { 2982 struct sh_eth_private *mdp = netdev_priv(ndev); 2983 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2984 2985 if (unlikely(!mdp->cd->tsu)) 2986 return -EPERM; 2987 2988 /* No filtering if vid = 0 */ 2989 if (!vid) 2990 return 0; 2991 2992 mdp->vlan_num_ids++; 2993 2994 /* The controller has one VLAN tag HW filter. So, if the filter is 2995 * already enabled, the driver disables it and the filte 2996 */ 2997 if (mdp->vlan_num_ids > 1) { 2998 /* disable VLAN filter */ 2999 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 3000 return 0; 3001 } 3002 3003 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 3004 vtag_reg_index); 3005 3006 return 0; 3007 } 3008 3009 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 3010 __be16 proto, u16 vid) 3011 { 3012 struct sh_eth_private *mdp = netdev_priv(ndev); 3013 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 3014 3015 if (unlikely(!mdp->cd->tsu)) 3016 return -EPERM; 3017 3018 /* No filtering if vid = 0 */ 3019 if (!vid) 3020 return 0; 3021 3022 mdp->vlan_num_ids--; 3023 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 3024 3025 return 0; 3026 } 3027 3028 /* SuperH's TSU register init function */ 3029 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 3030 { 3031 if (!mdp->cd->dual_port) { 3032 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3033 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 3034 TSU_FWSLC); /* Enable POST registers */ 3035 return; 3036 } 3037 3038 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 3039 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 3040 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 3041 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 3042 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 3043 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 3044 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 3045 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 3046 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 3047 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 3048 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 3049 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 3050 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 3051 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 3052 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3053 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 3054 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 3055 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 3056 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 3057 } 3058 3059 /* MDIO bus release function */ 3060 static int sh_mdio_release(struct sh_eth_private *mdp) 3061 { 3062 /* unregister mdio bus */ 3063 mdiobus_unregister(mdp->mii_bus); 3064 3065 /* free bitbang info */ 3066 free_mdio_bitbang(mdp->mii_bus); 3067 3068 return 0; 3069 } 3070 3071 /* MDIO bus init function */ 3072 static int sh_mdio_init(struct sh_eth_private *mdp, 3073 struct sh_eth_plat_data *pd) 3074 { 3075 int ret; 3076 struct bb_info *bitbang; 3077 struct platform_device *pdev = mdp->pdev; 3078 struct device *dev = &mdp->pdev->dev; 3079 3080 /* create bit control struct for PHY */ 3081 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 3082 if (!bitbang) 3083 return -ENOMEM; 3084 3085 /* bitbang init */ 3086 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 3087 bitbang->set_gate = pd->set_mdio_gate; 3088 bitbang->ctrl.ops = &bb_ops; 3089 3090 /* MII controller setting */ 3091 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 3092 if (!mdp->mii_bus) 3093 return -ENOMEM; 3094 3095 /* Hook up MII support for ethtool */ 3096 mdp->mii_bus->name = "sh_mii"; 3097 mdp->mii_bus->parent = dev; 3098 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 3099 pdev->name, pdev->id); 3100 3101 /* register MDIO bus */ 3102 if (pd->phy_irq > 0) 3103 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 3104 3105 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 3106 if (ret) 3107 goto out_free_bus; 3108 3109 return 0; 3110 3111 out_free_bus: 3112 free_mdio_bitbang(mdp->mii_bus); 3113 return ret; 3114 } 3115 3116 static const u16 *sh_eth_get_register_offset(int register_type) 3117 { 3118 const u16 *reg_offset = NULL; 3119 3120 switch (register_type) { 3121 case SH_ETH_REG_GIGABIT: 3122 reg_offset = sh_eth_offset_gigabit; 3123 break; 3124 case SH_ETH_REG_FAST_RZ: 3125 reg_offset = sh_eth_offset_fast_rz; 3126 break; 3127 case SH_ETH_REG_FAST_RCAR: 3128 reg_offset = sh_eth_offset_fast_rcar; 3129 break; 3130 case SH_ETH_REG_FAST_SH4: 3131 reg_offset = sh_eth_offset_fast_sh4; 3132 break; 3133 case SH_ETH_REG_FAST_SH3_SH2: 3134 reg_offset = sh_eth_offset_fast_sh3_sh2; 3135 break; 3136 } 3137 3138 return reg_offset; 3139 } 3140 3141 static const struct net_device_ops sh_eth_netdev_ops = { 3142 .ndo_open = sh_eth_open, 3143 .ndo_stop = sh_eth_close, 3144 .ndo_start_xmit = sh_eth_start_xmit, 3145 .ndo_get_stats = sh_eth_get_stats, 3146 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3147 .ndo_tx_timeout = sh_eth_tx_timeout, 3148 .ndo_do_ioctl = phy_do_ioctl_running, 3149 .ndo_change_mtu = sh_eth_change_mtu, 3150 .ndo_validate_addr = eth_validate_addr, 3151 .ndo_set_mac_address = eth_mac_addr, 3152 .ndo_set_features = sh_eth_set_features, 3153 }; 3154 3155 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3156 .ndo_open = sh_eth_open, 3157 .ndo_stop = sh_eth_close, 3158 .ndo_start_xmit = sh_eth_start_xmit, 3159 .ndo_get_stats = sh_eth_get_stats, 3160 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3161 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3162 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3163 .ndo_tx_timeout = sh_eth_tx_timeout, 3164 .ndo_do_ioctl = phy_do_ioctl_running, 3165 .ndo_change_mtu = sh_eth_change_mtu, 3166 .ndo_validate_addr = eth_validate_addr, 3167 .ndo_set_mac_address = eth_mac_addr, 3168 .ndo_set_features = sh_eth_set_features, 3169 }; 3170 3171 #ifdef CONFIG_OF 3172 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3173 { 3174 struct device_node *np = dev->of_node; 3175 struct sh_eth_plat_data *pdata; 3176 phy_interface_t interface; 3177 const char *mac_addr; 3178 int ret; 3179 3180 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3181 if (!pdata) 3182 return NULL; 3183 3184 ret = of_get_phy_mode(np, &interface); 3185 if (ret) 3186 return NULL; 3187 pdata->phy_interface = interface; 3188 3189 mac_addr = of_get_mac_address(np); 3190 if (!IS_ERR(mac_addr)) 3191 ether_addr_copy(pdata->mac_addr, mac_addr); 3192 3193 pdata->no_ether_link = 3194 of_property_read_bool(np, "renesas,no-ether-link"); 3195 pdata->ether_link_active_low = 3196 of_property_read_bool(np, "renesas,ether-link-active-low"); 3197 3198 return pdata; 3199 } 3200 3201 static const struct of_device_id sh_eth_match_table[] = { 3202 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3203 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data }, 3204 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data }, 3205 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data }, 3206 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data }, 3207 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data }, 3208 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data }, 3209 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data }, 3210 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data }, 3211 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data }, 3212 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3213 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data }, 3214 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data }, 3215 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data }, 3216 { } 3217 }; 3218 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3219 #else 3220 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3221 { 3222 return NULL; 3223 } 3224 #endif 3225 3226 static int sh_eth_drv_probe(struct platform_device *pdev) 3227 { 3228 struct resource *res; 3229 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3230 const struct platform_device_id *id = platform_get_device_id(pdev); 3231 struct sh_eth_private *mdp; 3232 struct net_device *ndev; 3233 int ret; 3234 3235 /* get base addr */ 3236 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3237 3238 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3239 if (!ndev) 3240 return -ENOMEM; 3241 3242 pm_runtime_enable(&pdev->dev); 3243 pm_runtime_get_sync(&pdev->dev); 3244 3245 ret = platform_get_irq(pdev, 0); 3246 if (ret < 0) 3247 goto out_release; 3248 ndev->irq = ret; 3249 3250 SET_NETDEV_DEV(ndev, &pdev->dev); 3251 3252 mdp = netdev_priv(ndev); 3253 mdp->num_tx_ring = TX_RING_SIZE; 3254 mdp->num_rx_ring = RX_RING_SIZE; 3255 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3256 if (IS_ERR(mdp->addr)) { 3257 ret = PTR_ERR(mdp->addr); 3258 goto out_release; 3259 } 3260 3261 ndev->base_addr = res->start; 3262 3263 spin_lock_init(&mdp->lock); 3264 mdp->pdev = pdev; 3265 3266 if (pdev->dev.of_node) 3267 pd = sh_eth_parse_dt(&pdev->dev); 3268 if (!pd) { 3269 dev_err(&pdev->dev, "no platform data\n"); 3270 ret = -EINVAL; 3271 goto out_release; 3272 } 3273 3274 /* get PHY ID */ 3275 mdp->phy_id = pd->phy; 3276 mdp->phy_interface = pd->phy_interface; 3277 mdp->no_ether_link = pd->no_ether_link; 3278 mdp->ether_link_active_low = pd->ether_link_active_low; 3279 3280 /* set cpu data */ 3281 if (id) 3282 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3283 else 3284 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3285 3286 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3287 if (!mdp->reg_offset) { 3288 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3289 mdp->cd->register_type); 3290 ret = -EINVAL; 3291 goto out_release; 3292 } 3293 sh_eth_set_default_cpu_data(mdp->cd); 3294 3295 /* User's manual states max MTU should be 2048 but due to the 3296 * alignment calculations in sh_eth_ring_init() the practical 3297 * MTU is a bit less. Maybe this can be optimized some more. 3298 */ 3299 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3300 ndev->min_mtu = ETH_MIN_MTU; 3301 3302 if (mdp->cd->rx_csum) { 3303 ndev->features = NETIF_F_RXCSUM; 3304 ndev->hw_features = NETIF_F_RXCSUM; 3305 } 3306 3307 /* set function */ 3308 if (mdp->cd->tsu) 3309 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3310 else 3311 ndev->netdev_ops = &sh_eth_netdev_ops; 3312 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3313 ndev->watchdog_timeo = TX_TIMEOUT; 3314 3315 /* debug message level */ 3316 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3317 3318 /* read and set MAC address */ 3319 read_mac_address(ndev, pd->mac_addr); 3320 if (!is_valid_ether_addr(ndev->dev_addr)) { 3321 dev_warn(&pdev->dev, 3322 "no valid MAC address supplied, using a random one.\n"); 3323 eth_hw_addr_random(ndev); 3324 } 3325 3326 if (mdp->cd->tsu) { 3327 int port = pdev->id < 0 ? 0 : pdev->id % 2; 3328 struct resource *rtsu; 3329 3330 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3331 if (!rtsu) { 3332 dev_err(&pdev->dev, "no TSU resource\n"); 3333 ret = -ENODEV; 3334 goto out_release; 3335 } 3336 /* We can only request the TSU region for the first port 3337 * of the two sharing this TSU for the probe to succeed... 3338 */ 3339 if (port == 0 && 3340 !devm_request_mem_region(&pdev->dev, rtsu->start, 3341 resource_size(rtsu), 3342 dev_name(&pdev->dev))) { 3343 dev_err(&pdev->dev, "can't request TSU resource.\n"); 3344 ret = -EBUSY; 3345 goto out_release; 3346 } 3347 /* ioremap the TSU registers */ 3348 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, 3349 resource_size(rtsu)); 3350 if (!mdp->tsu_addr) { 3351 dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); 3352 ret = -ENOMEM; 3353 goto out_release; 3354 } 3355 mdp->port = port; 3356 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 3357 3358 /* Need to init only the first port of the two sharing a TSU */ 3359 if (port == 0) { 3360 if (mdp->cd->chip_reset) 3361 mdp->cd->chip_reset(ndev); 3362 3363 /* TSU init (Init only)*/ 3364 sh_eth_tsu_init(mdp); 3365 } 3366 } 3367 3368 if (mdp->cd->rmiimode) 3369 sh_eth_write(ndev, 0x1, RMIIMODE); 3370 3371 /* MDIO bus init */ 3372 ret = sh_mdio_init(mdp, pd); 3373 if (ret) { 3374 if (ret != -EPROBE_DEFER) 3375 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret); 3376 goto out_release; 3377 } 3378 3379 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3380 3381 /* network device register */ 3382 ret = register_netdev(ndev); 3383 if (ret) 3384 goto out_napi_del; 3385 3386 if (mdp->cd->magic) 3387 device_set_wakeup_capable(&pdev->dev, 1); 3388 3389 /* print device information */ 3390 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3391 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3392 3393 pm_runtime_put(&pdev->dev); 3394 platform_set_drvdata(pdev, ndev); 3395 3396 return ret; 3397 3398 out_napi_del: 3399 netif_napi_del(&mdp->napi); 3400 sh_mdio_release(mdp); 3401 3402 out_release: 3403 /* net_dev free */ 3404 free_netdev(ndev); 3405 3406 pm_runtime_put(&pdev->dev); 3407 pm_runtime_disable(&pdev->dev); 3408 return ret; 3409 } 3410 3411 static int sh_eth_drv_remove(struct platform_device *pdev) 3412 { 3413 struct net_device *ndev = platform_get_drvdata(pdev); 3414 struct sh_eth_private *mdp = netdev_priv(ndev); 3415 3416 unregister_netdev(ndev); 3417 netif_napi_del(&mdp->napi); 3418 sh_mdio_release(mdp); 3419 pm_runtime_disable(&pdev->dev); 3420 free_netdev(ndev); 3421 3422 return 0; 3423 } 3424 3425 #ifdef CONFIG_PM 3426 #ifdef CONFIG_PM_SLEEP 3427 static int sh_eth_wol_setup(struct net_device *ndev) 3428 { 3429 struct sh_eth_private *mdp = netdev_priv(ndev); 3430 3431 /* Only allow ECI interrupts */ 3432 synchronize_irq(ndev->irq); 3433 napi_disable(&mdp->napi); 3434 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3435 3436 /* Enable MagicPacket */ 3437 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3438 3439 return enable_irq_wake(ndev->irq); 3440 } 3441 3442 static int sh_eth_wol_restore(struct net_device *ndev) 3443 { 3444 struct sh_eth_private *mdp = netdev_priv(ndev); 3445 int ret; 3446 3447 napi_enable(&mdp->napi); 3448 3449 /* Disable MagicPacket */ 3450 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3451 3452 /* The device needs to be reset to restore MagicPacket logic 3453 * for next wakeup. If we close and open the device it will 3454 * both be reset and all registers restored. This is what 3455 * happens during suspend and resume without WoL enabled. 3456 */ 3457 ret = sh_eth_close(ndev); 3458 if (ret < 0) 3459 return ret; 3460 ret = sh_eth_open(ndev); 3461 if (ret < 0) 3462 return ret; 3463 3464 return disable_irq_wake(ndev->irq); 3465 } 3466 3467 static int sh_eth_suspend(struct device *dev) 3468 { 3469 struct net_device *ndev = dev_get_drvdata(dev); 3470 struct sh_eth_private *mdp = netdev_priv(ndev); 3471 int ret = 0; 3472 3473 if (!netif_running(ndev)) 3474 return 0; 3475 3476 netif_device_detach(ndev); 3477 3478 if (mdp->wol_enabled) 3479 ret = sh_eth_wol_setup(ndev); 3480 else 3481 ret = sh_eth_close(ndev); 3482 3483 return ret; 3484 } 3485 3486 static int sh_eth_resume(struct device *dev) 3487 { 3488 struct net_device *ndev = dev_get_drvdata(dev); 3489 struct sh_eth_private *mdp = netdev_priv(ndev); 3490 int ret = 0; 3491 3492 if (!netif_running(ndev)) 3493 return 0; 3494 3495 if (mdp->wol_enabled) 3496 ret = sh_eth_wol_restore(ndev); 3497 else 3498 ret = sh_eth_open(ndev); 3499 3500 if (ret < 0) 3501 return ret; 3502 3503 netif_device_attach(ndev); 3504 3505 return ret; 3506 } 3507 #endif 3508 3509 static int sh_eth_runtime_nop(struct device *dev) 3510 { 3511 /* Runtime PM callback shared between ->runtime_suspend() 3512 * and ->runtime_resume(). Simply returns success. 3513 * 3514 * This driver re-initializes all registers after 3515 * pm_runtime_get_sync() anyway so there is no need 3516 * to save and restore registers here. 3517 */ 3518 return 0; 3519 } 3520 3521 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3522 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3523 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3524 }; 3525 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3526 #else 3527 #define SH_ETH_PM_OPS NULL 3528 #endif 3529 3530 static const struct platform_device_id sh_eth_id_table[] = { 3531 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3532 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3533 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3534 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3535 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3536 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3537 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3538 { } 3539 }; 3540 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3541 3542 static struct platform_driver sh_eth_driver = { 3543 .probe = sh_eth_drv_probe, 3544 .remove = sh_eth_drv_remove, 3545 .id_table = sh_eth_id_table, 3546 .driver = { 3547 .name = CARDNAME, 3548 .pm = SH_ETH_PM_OPS, 3549 .of_match_table = of_match_ptr(sh_eth_match_table), 3550 }, 3551 }; 3552 3553 module_platform_driver(sh_eth_driver); 3554 3555 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3556 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3557 MODULE_LICENSE("GPL v2"); 3558