1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Renesas Ethernet Switch device driver 3 * 4 * Copyright (C) 2022 Renesas Electronics Corporation 5 */ 6 7 #ifndef __RSWITCH_H__ 8 #define __RSWITCH_H__ 9 10 #include <linux/platform_device.h> 11 #include "rcar_gen4_ptp.h" 12 13 #define RSWITCH_MAX_NUM_QUEUES 128 14 15 #define RSWITCH_NUM_PORTS 3 16 #define rswitch_for_each_enabled_port(priv, i) \ 17 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \ 18 if (priv->rdev[i]->disabled) \ 19 continue; \ 20 else 21 22 #define rswitch_for_each_enabled_port_continue_reverse(priv, i) \ 23 for (i--; i >= 0; i--) \ 24 if (priv->rdev[i]->disabled) \ 25 continue; \ 26 else 27 28 #define TX_RING_SIZE 1024 29 #define RX_RING_SIZE 1024 30 #define TS_RING_SIZE (TX_RING_SIZE * RSWITCH_NUM_PORTS) 31 32 #define PKT_BUF_SZ 1584 33 #define RSWITCH_ALIGN 128 34 #define RSWITCH_MAX_CTAG_PCP 7 35 36 #define RSWITCH_TIMEOUT_US 100000 37 38 #define RSWITCH_TOP_OFFSET 0x00008000 39 #define RSWITCH_COMA_OFFSET 0x00009000 40 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ 41 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ 42 #define RSWITCH_GWCA0_OFFSET 0x00010000 43 #define RSWITCH_GWCA1_OFFSET 0x00012000 44 45 /* TODO: hardcoded ETHA/GWCA settings for now */ 46 #define GWCA_IRQ_RESOURCE_NAME "gwca0_rxtx%d" 47 #define GWCA_IRQ_NAME "rswitch: gwca0_rxtx%d" 48 #define GWCA_NUM_IRQS 8 49 #define GWCA_INDEX 0 50 #define AGENT_INDEX_GWCA 3 51 #define GWRO RSWITCH_GWCA0_OFFSET 52 53 #define GWCA_TS_IRQ_RESOURCE_NAME "gwca0_rxts0" 54 #define GWCA_TS_IRQ_NAME "rswitch: gwca0_rxts0" 55 #define GWCA_TS_IRQ_BIT BIT(0) 56 57 #define FWRO 0 58 #define TPRO RSWITCH_TOP_OFFSET 59 #define CARO RSWITCH_COMA_OFFSET 60 #define TARO 0 61 #define RMRO 0x1000 62 enum rswitch_reg { 63 FWGC = FWRO + 0x0000, 64 FWTTC0 = FWRO + 0x0010, 65 FWTTC1 = FWRO + 0x0014, 66 FWLBMC = FWRO + 0x0018, 67 FWCEPTC = FWRO + 0x0020, 68 FWCEPRC0 = FWRO + 0x0024, 69 FWCEPRC1 = FWRO + 0x0028, 70 FWCEPRC2 = FWRO + 0x002c, 71 FWCLPTC = FWRO + 0x0030, 72 FWCLPRC = FWRO + 0x0034, 73 FWCMPTC = FWRO + 0x0040, 74 FWEMPTC = FWRO + 0x0044, 75 FWSDMPTC = FWRO + 0x0050, 76 FWSDMPVC = FWRO + 0x0054, 77 FWLBWMC0 = FWRO + 0x0080, 78 FWPC00 = FWRO + 0x0100, 79 FWPC10 = FWRO + 0x0104, 80 FWPC20 = FWRO + 0x0108, 81 FWCTGC00 = FWRO + 0x0400, 82 FWCTGC10 = FWRO + 0x0404, 83 FWCTTC00 = FWRO + 0x0408, 84 FWCTTC10 = FWRO + 0x040c, 85 FWCTTC200 = FWRO + 0x0410, 86 FWCTSC00 = FWRO + 0x0420, 87 FWCTSC10 = FWRO + 0x0424, 88 FWCTSC20 = FWRO + 0x0428, 89 FWCTSC30 = FWRO + 0x042c, 90 FWCTSC40 = FWRO + 0x0430, 91 FWTWBFC0 = FWRO + 0x1000, 92 FWTWBFVC0 = FWRO + 0x1004, 93 FWTHBFC0 = FWRO + 0x1400, 94 FWTHBFV0C0 = FWRO + 0x1404, 95 FWTHBFV1C0 = FWRO + 0x1408, 96 FWFOBFC0 = FWRO + 0x1800, 97 FWFOBFV0C0 = FWRO + 0x1804, 98 FWFOBFV1C0 = FWRO + 0x1808, 99 FWRFC0 = FWRO + 0x1c00, 100 FWRFVC0 = FWRO + 0x1c04, 101 FWCFC0 = FWRO + 0x2000, 102 FWCFMC00 = FWRO + 0x2004, 103 FWIP4SC = FWRO + 0x4008, 104 FWIP6SC = FWRO + 0x4018, 105 FWIP6OC = FWRO + 0x401c, 106 FWL2SC = FWRO + 0x4020, 107 FWSFHEC = FWRO + 0x4030, 108 FWSHCR0 = FWRO + 0x4040, 109 FWSHCR1 = FWRO + 0x4044, 110 FWSHCR2 = FWRO + 0x4048, 111 FWSHCR3 = FWRO + 0x404c, 112 FWSHCR4 = FWRO + 0x4050, 113 FWSHCR5 = FWRO + 0x4054, 114 FWSHCR6 = FWRO + 0x4058, 115 FWSHCR7 = FWRO + 0x405c, 116 FWSHCR8 = FWRO + 0x4060, 117 FWSHCR9 = FWRO + 0x4064, 118 FWSHCR10 = FWRO + 0x4068, 119 FWSHCR11 = FWRO + 0x406c, 120 FWSHCR12 = FWRO + 0x4070, 121 FWSHCR13 = FWRO + 0x4074, 122 FWSHCRR = FWRO + 0x4078, 123 FWLTHHEC = FWRO + 0x4090, 124 FWLTHHC = FWRO + 0x4094, 125 FWLTHTL0 = FWRO + 0x40a0, 126 FWLTHTL1 = FWRO + 0x40a4, 127 FWLTHTL2 = FWRO + 0x40a8, 128 FWLTHTL3 = FWRO + 0x40ac, 129 FWLTHTL4 = FWRO + 0x40b0, 130 FWLTHTL5 = FWRO + 0x40b4, 131 FWLTHTL6 = FWRO + 0x40b8, 132 FWLTHTL7 = FWRO + 0x40bc, 133 FWLTHTL80 = FWRO + 0x40c0, 134 FWLTHTL9 = FWRO + 0x40d0, 135 FWLTHTLR = FWRO + 0x40d4, 136 FWLTHTIM = FWRO + 0x40e0, 137 FWLTHTEM = FWRO + 0x40e4, 138 FWLTHTS0 = FWRO + 0x4100, 139 FWLTHTS1 = FWRO + 0x4104, 140 FWLTHTS2 = FWRO + 0x4108, 141 FWLTHTS3 = FWRO + 0x410c, 142 FWLTHTS4 = FWRO + 0x4110, 143 FWLTHTSR0 = FWRO + 0x4120, 144 FWLTHTSR1 = FWRO + 0x4124, 145 FWLTHTSR2 = FWRO + 0x4128, 146 FWLTHTSR3 = FWRO + 0x412c, 147 FWLTHTSR40 = FWRO + 0x4130, 148 FWLTHTSR5 = FWRO + 0x4140, 149 FWLTHTR = FWRO + 0x4150, 150 FWLTHTRR0 = FWRO + 0x4154, 151 FWLTHTRR1 = FWRO + 0x4158, 152 FWLTHTRR2 = FWRO + 0x415c, 153 FWLTHTRR3 = FWRO + 0x4160, 154 FWLTHTRR4 = FWRO + 0x4164, 155 FWLTHTRR5 = FWRO + 0x4168, 156 FWLTHTRR6 = FWRO + 0x416c, 157 FWLTHTRR7 = FWRO + 0x4170, 158 FWLTHTRR8 = FWRO + 0x4174, 159 FWLTHTRR9 = FWRO + 0x4180, 160 FWLTHTRR10 = FWRO + 0x4190, 161 FWIPHEC = FWRO + 0x4214, 162 FWIPHC = FWRO + 0x4218, 163 FWIPTL0 = FWRO + 0x4220, 164 FWIPTL1 = FWRO + 0x4224, 165 FWIPTL2 = FWRO + 0x4228, 166 FWIPTL3 = FWRO + 0x422c, 167 FWIPTL4 = FWRO + 0x4230, 168 FWIPTL5 = FWRO + 0x4234, 169 FWIPTL6 = FWRO + 0x4238, 170 FWIPTL7 = FWRO + 0x4240, 171 FWIPTL8 = FWRO + 0x4250, 172 FWIPTLR = FWRO + 0x4254, 173 FWIPTIM = FWRO + 0x4260, 174 FWIPTEM = FWRO + 0x4264, 175 FWIPTS0 = FWRO + 0x4270, 176 FWIPTS1 = FWRO + 0x4274, 177 FWIPTS2 = FWRO + 0x4278, 178 FWIPTS3 = FWRO + 0x427c, 179 FWIPTS4 = FWRO + 0x4280, 180 FWIPTSR0 = FWRO + 0x4284, 181 FWIPTSR1 = FWRO + 0x4288, 182 FWIPTSR2 = FWRO + 0x428c, 183 FWIPTSR3 = FWRO + 0x4290, 184 FWIPTSR4 = FWRO + 0x42a0, 185 FWIPTR = FWRO + 0x42b0, 186 FWIPTRR0 = FWRO + 0x42b4, 187 FWIPTRR1 = FWRO + 0x42b8, 188 FWIPTRR2 = FWRO + 0x42bc, 189 FWIPTRR3 = FWRO + 0x42c0, 190 FWIPTRR4 = FWRO + 0x42c4, 191 FWIPTRR5 = FWRO + 0x42c8, 192 FWIPTRR6 = FWRO + 0x42cc, 193 FWIPTRR7 = FWRO + 0x42d0, 194 FWIPTRR8 = FWRO + 0x42e0, 195 FWIPTRR9 = FWRO + 0x42f0, 196 FWIPHLEC = FWRO + 0x4300, 197 FWIPAGUSPC = FWRO + 0x4500, 198 FWIPAGC = FWRO + 0x4504, 199 FWIPAGM0 = FWRO + 0x4510, 200 FWIPAGM1 = FWRO + 0x4514, 201 FWIPAGM2 = FWRO + 0x4518, 202 FWIPAGM3 = FWRO + 0x451c, 203 FWIPAGM4 = FWRO + 0x4520, 204 FWMACHEC = FWRO + 0x4620, 205 FWMACHC = FWRO + 0x4624, 206 FWMACTL0 = FWRO + 0x4630, 207 FWMACTL1 = FWRO + 0x4634, 208 FWMACTL2 = FWRO + 0x4638, 209 FWMACTL3 = FWRO + 0x463c, 210 FWMACTL4 = FWRO + 0x4640, 211 FWMACTL5 = FWRO + 0x4650, 212 FWMACTLR = FWRO + 0x4654, 213 FWMACTIM = FWRO + 0x4660, 214 FWMACTEM = FWRO + 0x4664, 215 FWMACTS0 = FWRO + 0x4670, 216 FWMACTS1 = FWRO + 0x4674, 217 FWMACTSR0 = FWRO + 0x4678, 218 FWMACTSR1 = FWRO + 0x467c, 219 FWMACTSR2 = FWRO + 0x4680, 220 FWMACTSR3 = FWRO + 0x4690, 221 FWMACTR = FWRO + 0x46a0, 222 FWMACTRR0 = FWRO + 0x46a4, 223 FWMACTRR1 = FWRO + 0x46a8, 224 FWMACTRR2 = FWRO + 0x46ac, 225 FWMACTRR3 = FWRO + 0x46b0, 226 FWMACTRR4 = FWRO + 0x46b4, 227 FWMACTRR5 = FWRO + 0x46c0, 228 FWMACTRR6 = FWRO + 0x46d0, 229 FWMACHLEC = FWRO + 0x4700, 230 FWMACAGUSPC = FWRO + 0x4880, 231 FWMACAGC = FWRO + 0x4884, 232 FWMACAGM0 = FWRO + 0x4888, 233 FWMACAGM1 = FWRO + 0x488c, 234 FWVLANTEC = FWRO + 0x4900, 235 FWVLANTL0 = FWRO + 0x4910, 236 FWVLANTL1 = FWRO + 0x4914, 237 FWVLANTL2 = FWRO + 0x4918, 238 FWVLANTL3 = FWRO + 0x4920, 239 FWVLANTL4 = FWRO + 0x4930, 240 FWVLANTLR = FWRO + 0x4934, 241 FWVLANTIM = FWRO + 0x4940, 242 FWVLANTEM = FWRO + 0x4944, 243 FWVLANTS = FWRO + 0x4950, 244 FWVLANTSR0 = FWRO + 0x4954, 245 FWVLANTSR1 = FWRO + 0x4958, 246 FWVLANTSR2 = FWRO + 0x4960, 247 FWVLANTSR3 = FWRO + 0x4970, 248 FWPBFC0 = FWRO + 0x4a00, 249 FWPBFCSDC00 = FWRO + 0x4a04, 250 FWL23URL0 = FWRO + 0x4e00, 251 FWL23URL1 = FWRO + 0x4e04, 252 FWL23URL2 = FWRO + 0x4e08, 253 FWL23URL3 = FWRO + 0x4e0c, 254 FWL23URLR = FWRO + 0x4e10, 255 FWL23UTIM = FWRO + 0x4e20, 256 FWL23URR = FWRO + 0x4e30, 257 FWL23URRR0 = FWRO + 0x4e34, 258 FWL23URRR1 = FWRO + 0x4e38, 259 FWL23URRR2 = FWRO + 0x4e3c, 260 FWL23URRR3 = FWRO + 0x4e40, 261 FWL23URMC0 = FWRO + 0x4f00, 262 FWPMFGC0 = FWRO + 0x5000, 263 FWPGFC0 = FWRO + 0x5100, 264 FWPGFIGSC0 = FWRO + 0x5104, 265 FWPGFENC0 = FWRO + 0x5108, 266 FWPGFENM0 = FWRO + 0x510c, 267 FWPGFCSTC00 = FWRO + 0x5110, 268 FWPGFCSTC10 = FWRO + 0x5114, 269 FWPGFCSTM00 = FWRO + 0x5118, 270 FWPGFCSTM10 = FWRO + 0x511c, 271 FWPGFCTC0 = FWRO + 0x5120, 272 FWPGFCTM0 = FWRO + 0x5124, 273 FWPGFHCC0 = FWRO + 0x5128, 274 FWPGFSM0 = FWRO + 0x512c, 275 FWPGFGC0 = FWRO + 0x5130, 276 FWPGFGL0 = FWRO + 0x5500, 277 FWPGFGL1 = FWRO + 0x5504, 278 FWPGFGLR = FWRO + 0x5518, 279 FWPGFGR = FWRO + 0x5510, 280 FWPGFGRR0 = FWRO + 0x5514, 281 FWPGFGRR1 = FWRO + 0x5518, 282 FWPGFRIM = FWRO + 0x5520, 283 FWPMTRFC0 = FWRO + 0x5600, 284 FWPMTRCBSC0 = FWRO + 0x5604, 285 FWPMTRC0RC0 = FWRO + 0x5608, 286 FWPMTREBSC0 = FWRO + 0x560c, 287 FWPMTREIRC0 = FWRO + 0x5610, 288 FWPMTRFM0 = FWRO + 0x5614, 289 FWFTL0 = FWRO + 0x6000, 290 FWFTL1 = FWRO + 0x6004, 291 FWFTLR = FWRO + 0x6008, 292 FWFTOC = FWRO + 0x6010, 293 FWFTOPC = FWRO + 0x6014, 294 FWFTIM = FWRO + 0x6020, 295 FWFTR = FWRO + 0x6030, 296 FWFTRR0 = FWRO + 0x6034, 297 FWFTRR1 = FWRO + 0x6038, 298 FWFTRR2 = FWRO + 0x603c, 299 FWSEQNGC0 = FWRO + 0x6100, 300 FWSEQNGM0 = FWRO + 0x6104, 301 FWSEQNRC = FWRO + 0x6200, 302 FWCTFDCN0 = FWRO + 0x6300, 303 FWLTHFDCN0 = FWRO + 0x6304, 304 FWIPFDCN0 = FWRO + 0x6308, 305 FWLTWFDCN0 = FWRO + 0x630c, 306 FWPBFDCN0 = FWRO + 0x6310, 307 FWMHLCN0 = FWRO + 0x6314, 308 FWIHLCN0 = FWRO + 0x6318, 309 FWICRDCN0 = FWRO + 0x6500, 310 FWWMRDCN0 = FWRO + 0x6504, 311 FWCTRDCN0 = FWRO + 0x6508, 312 FWLTHRDCN0 = FWRO + 0x650c, 313 FWIPRDCN0 = FWRO + 0x6510, 314 FWLTWRDCN0 = FWRO + 0x6514, 315 FWPBRDCN0 = FWRO + 0x6518, 316 FWPMFDCN0 = FWRO + 0x6700, 317 FWPGFDCN0 = FWRO + 0x6780, 318 FWPMGDCN0 = FWRO + 0x6800, 319 FWPMYDCN0 = FWRO + 0x6804, 320 FWPMRDCN0 = FWRO + 0x6808, 321 FWFRPPCN0 = FWRO + 0x6a00, 322 FWFRDPCN0 = FWRO + 0x6a04, 323 FWEIS00 = FWRO + 0x7900, 324 FWEIE00 = FWRO + 0x7904, 325 FWEID00 = FWRO + 0x7908, 326 FWEIS1 = FWRO + 0x7a00, 327 FWEIE1 = FWRO + 0x7a04, 328 FWEID1 = FWRO + 0x7a08, 329 FWEIS2 = FWRO + 0x7a10, 330 FWEIE2 = FWRO + 0x7a14, 331 FWEID2 = FWRO + 0x7a18, 332 FWEIS3 = FWRO + 0x7a20, 333 FWEIE3 = FWRO + 0x7a24, 334 FWEID3 = FWRO + 0x7a28, 335 FWEIS4 = FWRO + 0x7a30, 336 FWEIE4 = FWRO + 0x7a34, 337 FWEID4 = FWRO + 0x7a38, 338 FWEIS5 = FWRO + 0x7a40, 339 FWEIE5 = FWRO + 0x7a44, 340 FWEID5 = FWRO + 0x7a48, 341 FWEIS60 = FWRO + 0x7a50, 342 FWEIE60 = FWRO + 0x7a54, 343 FWEID60 = FWRO + 0x7a58, 344 FWEIS61 = FWRO + 0x7a60, 345 FWEIE61 = FWRO + 0x7a64, 346 FWEID61 = FWRO + 0x7a68, 347 FWEIS62 = FWRO + 0x7a70, 348 FWEIE62 = FWRO + 0x7a74, 349 FWEID62 = FWRO + 0x7a78, 350 FWEIS63 = FWRO + 0x7a80, 351 FWEIE63 = FWRO + 0x7a84, 352 FWEID63 = FWRO + 0x7a88, 353 FWEIS70 = FWRO + 0x7a90, 354 FWEIE70 = FWRO + 0x7A94, 355 FWEID70 = FWRO + 0x7a98, 356 FWEIS71 = FWRO + 0x7aa0, 357 FWEIE71 = FWRO + 0x7aa4, 358 FWEID71 = FWRO + 0x7aa8, 359 FWEIS72 = FWRO + 0x7ab0, 360 FWEIE72 = FWRO + 0x7ab4, 361 FWEID72 = FWRO + 0x7ab8, 362 FWEIS73 = FWRO + 0x7ac0, 363 FWEIE73 = FWRO + 0x7ac4, 364 FWEID73 = FWRO + 0x7ac8, 365 FWEIS80 = FWRO + 0x7ad0, 366 FWEIE80 = FWRO + 0x7ad4, 367 FWEID80 = FWRO + 0x7ad8, 368 FWEIS81 = FWRO + 0x7ae0, 369 FWEIE81 = FWRO + 0x7ae4, 370 FWEID81 = FWRO + 0x7ae8, 371 FWEIS82 = FWRO + 0x7af0, 372 FWEIE82 = FWRO + 0x7af4, 373 FWEID82 = FWRO + 0x7af8, 374 FWEIS83 = FWRO + 0x7b00, 375 FWEIE83 = FWRO + 0x7b04, 376 FWEID83 = FWRO + 0x7b08, 377 FWMIS0 = FWRO + 0x7c00, 378 FWMIE0 = FWRO + 0x7c04, 379 FWMID0 = FWRO + 0x7c08, 380 FWSCR0 = FWRO + 0x7d00, 381 FWSCR1 = FWRO + 0x7d04, 382 FWSCR2 = FWRO + 0x7d08, 383 FWSCR3 = FWRO + 0x7d0c, 384 FWSCR4 = FWRO + 0x7d10, 385 FWSCR5 = FWRO + 0x7d14, 386 FWSCR6 = FWRO + 0x7d18, 387 FWSCR7 = FWRO + 0x7d1c, 388 FWSCR8 = FWRO + 0x7d20, 389 FWSCR9 = FWRO + 0x7d24, 390 FWSCR10 = FWRO + 0x7d28, 391 FWSCR11 = FWRO + 0x7d2c, 392 FWSCR12 = FWRO + 0x7d30, 393 FWSCR13 = FWRO + 0x7d34, 394 FWSCR14 = FWRO + 0x7d38, 395 FWSCR15 = FWRO + 0x7d3c, 396 FWSCR16 = FWRO + 0x7d40, 397 FWSCR17 = FWRO + 0x7d44, 398 FWSCR18 = FWRO + 0x7d48, 399 FWSCR19 = FWRO + 0x7d4c, 400 FWSCR20 = FWRO + 0x7d50, 401 FWSCR21 = FWRO + 0x7d54, 402 FWSCR22 = FWRO + 0x7d58, 403 FWSCR23 = FWRO + 0x7d5c, 404 FWSCR24 = FWRO + 0x7d60, 405 FWSCR25 = FWRO + 0x7d64, 406 FWSCR26 = FWRO + 0x7d68, 407 FWSCR27 = FWRO + 0x7d6c, 408 FWSCR28 = FWRO + 0x7d70, 409 FWSCR29 = FWRO + 0x7d74, 410 FWSCR30 = FWRO + 0x7d78, 411 FWSCR31 = FWRO + 0x7d7c, 412 FWSCR32 = FWRO + 0x7d80, 413 FWSCR33 = FWRO + 0x7d84, 414 FWSCR34 = FWRO + 0x7d88, 415 FWSCR35 = FWRO + 0x7d8c, 416 FWSCR36 = FWRO + 0x7d90, 417 FWSCR37 = FWRO + 0x7d94, 418 FWSCR38 = FWRO + 0x7d98, 419 FWSCR39 = FWRO + 0x7d9c, 420 FWSCR40 = FWRO + 0x7da0, 421 FWSCR41 = FWRO + 0x7da4, 422 FWSCR42 = FWRO + 0x7da8, 423 FWSCR43 = FWRO + 0x7dac, 424 FWSCR44 = FWRO + 0x7db0, 425 FWSCR45 = FWRO + 0x7db4, 426 FWSCR46 = FWRO + 0x7db8, 427 428 TPEMIMC0 = TPRO + 0x0000, 429 TPEMIMC1 = TPRO + 0x0004, 430 TPEMIMC2 = TPRO + 0x0008, 431 TPEMIMC3 = TPRO + 0x000c, 432 TPEMIMC4 = TPRO + 0x0010, 433 TPEMIMC5 = TPRO + 0x0014, 434 TPEMIMC60 = TPRO + 0x0080, 435 TPEMIMC70 = TPRO + 0x0100, 436 TSIM = TPRO + 0x0700, 437 TFIM = TPRO + 0x0704, 438 TCIM = TPRO + 0x0708, 439 TGIM0 = TPRO + 0x0710, 440 TGIM1 = TPRO + 0x0714, 441 TEIM0 = TPRO + 0x0720, 442 TEIM1 = TPRO + 0x0724, 443 TEIM2 = TPRO + 0x0728, 444 445 RIPV = CARO + 0x0000, 446 RRC = CARO + 0x0004, 447 RCEC = CARO + 0x0008, 448 RCDC = CARO + 0x000c, 449 RSSIS = CARO + 0x0010, 450 RSSIE = CARO + 0x0014, 451 RSSID = CARO + 0x0018, 452 CABPIBWMC = CARO + 0x0020, 453 CABPWMLC = CARO + 0x0040, 454 CABPPFLC0 = CARO + 0x0050, 455 CABPPWMLC0 = CARO + 0x0060, 456 CABPPPFLC00 = CARO + 0x00a0, 457 CABPULC = CARO + 0x0100, 458 CABPIRM = CARO + 0x0140, 459 CABPPCM = CARO + 0x0144, 460 CABPLCM = CARO + 0x0148, 461 CABPCPM = CARO + 0x0180, 462 CABPMCPM = CARO + 0x0200, 463 CARDNM = CARO + 0x0280, 464 CARDMNM = CARO + 0x0284, 465 CARDCN = CARO + 0x0290, 466 CAEIS0 = CARO + 0x0300, 467 CAEIE0 = CARO + 0x0304, 468 CAEID0 = CARO + 0x0308, 469 CAEIS1 = CARO + 0x0310, 470 CAEIE1 = CARO + 0x0314, 471 CAEID1 = CARO + 0x0318, 472 CAMIS0 = CARO + 0x0340, 473 CAMIE0 = CARO + 0x0344, 474 CAMID0 = CARO + 0x0348, 475 CAMIS1 = CARO + 0x0350, 476 CAMIE1 = CARO + 0x0354, 477 CAMID1 = CARO + 0x0358, 478 CASCR = CARO + 0x0380, 479 480 EAMC = TARO + 0x0000, 481 EAMS = TARO + 0x0004, 482 EAIRC = TARO + 0x0010, 483 EATDQSC = TARO + 0x0014, 484 EATDQC = TARO + 0x0018, 485 EATDQAC = TARO + 0x001c, 486 EATPEC = TARO + 0x0020, 487 EATMFSC0 = TARO + 0x0040, 488 EATDQDC0 = TARO + 0x0060, 489 EATDQM0 = TARO + 0x0080, 490 EATDQMLM0 = TARO + 0x00a0, 491 EACTQC = TARO + 0x0100, 492 EACTDQDC = TARO + 0x0104, 493 EACTDQM = TARO + 0x0108, 494 EACTDQMLM = TARO + 0x010c, 495 EAVCC = TARO + 0x0130, 496 EAVTC = TARO + 0x0134, 497 EATTFC = TARO + 0x0138, 498 EACAEC = TARO + 0x0200, 499 EACC = TARO + 0x0204, 500 EACAIVC0 = TARO + 0x0220, 501 EACAULC0 = TARO + 0x0240, 502 EACOEM = TARO + 0x0260, 503 EACOIVM0 = TARO + 0x0280, 504 EACOULM0 = TARO + 0x02a0, 505 EACGSM = TARO + 0x02c0, 506 EATASC = TARO + 0x0300, 507 EATASENC0 = TARO + 0x0320, 508 EATASCTENC = TARO + 0x0340, 509 EATASENM0 = TARO + 0x0360, 510 EATASCTENM = TARO + 0x0380, 511 EATASCSTC0 = TARO + 0x03a0, 512 EATASCSTC1 = TARO + 0x03a4, 513 EATASCSTM0 = TARO + 0x03a8, 514 EATASCSTM1 = TARO + 0x03ac, 515 EATASCTC = TARO + 0x03b0, 516 EATASCTM = TARO + 0x03b4, 517 EATASGL0 = TARO + 0x03c0, 518 EATASGL1 = TARO + 0x03c4, 519 EATASGLR = TARO + 0x03c8, 520 EATASGR = TARO + 0x03d0, 521 EATASGRR = TARO + 0x03d4, 522 EATASHCC = TARO + 0x03e0, 523 EATASRIRM = TARO + 0x03e4, 524 EATASSM = TARO + 0x03e8, 525 EAUSMFSECN = TARO + 0x0400, 526 EATFECN = TARO + 0x0404, 527 EAFSECN = TARO + 0x0408, 528 EADQOECN = TARO + 0x040c, 529 EADQSECN = TARO + 0x0410, 530 EACKSECN = TARO + 0x0414, 531 EAEIS0 = TARO + 0x0500, 532 EAEIE0 = TARO + 0x0504, 533 EAEID0 = TARO + 0x0508, 534 EAEIS1 = TARO + 0x0510, 535 EAEIE1 = TARO + 0x0514, 536 EAEID1 = TARO + 0x0518, 537 EAEIS2 = TARO + 0x0520, 538 EAEIE2 = TARO + 0x0524, 539 EAEID2 = TARO + 0x0528, 540 EASCR = TARO + 0x0580, 541 542 MPSM = RMRO + 0x0000, 543 MPIC = RMRO + 0x0004, 544 MPIM = RMRO + 0x0008, 545 MIOC = RMRO + 0x0010, 546 MIOM = RMRO + 0x0014, 547 MXMS = RMRO + 0x0018, 548 MTFFC = RMRO + 0x0020, 549 MTPFC = RMRO + 0x0024, 550 MTPFC2 = RMRO + 0x0028, 551 MTPFC30 = RMRO + 0x0030, 552 MTATC0 = RMRO + 0x0050, 553 MTIM = RMRO + 0x0060, 554 MRGC = RMRO + 0x0080, 555 MRMAC0 = RMRO + 0x0084, 556 MRMAC1 = RMRO + 0x0088, 557 MRAFC = RMRO + 0x008c, 558 MRSCE = RMRO + 0x0090, 559 MRSCP = RMRO + 0x0094, 560 MRSCC = RMRO + 0x0098, 561 MRFSCE = RMRO + 0x009c, 562 MRFSCP = RMRO + 0x00a0, 563 MTRC = RMRO + 0x00a4, 564 MRIM = RMRO + 0x00a8, 565 MRPFM = RMRO + 0x00ac, 566 MPFC0 = RMRO + 0x0100, 567 MLVC = RMRO + 0x0180, 568 MEEEC = RMRO + 0x0184, 569 MLBC = RMRO + 0x0188, 570 MXGMIIC = RMRO + 0x0190, 571 MPCH = RMRO + 0x0194, 572 MANC = RMRO + 0x0198, 573 MANM = RMRO + 0x019c, 574 MPLCA1 = RMRO + 0x01a0, 575 MPLCA2 = RMRO + 0x01a4, 576 MPLCA3 = RMRO + 0x01a8, 577 MPLCA4 = RMRO + 0x01ac, 578 MPLCAM = RMRO + 0x01b0, 579 MHDC1 = RMRO + 0x01c0, 580 MHDC2 = RMRO + 0x01c4, 581 MEIS = RMRO + 0x0200, 582 MEIE = RMRO + 0x0204, 583 MEID = RMRO + 0x0208, 584 MMIS0 = RMRO + 0x0210, 585 MMIE0 = RMRO + 0x0214, 586 MMID0 = RMRO + 0x0218, 587 MMIS1 = RMRO + 0x0220, 588 MMIE1 = RMRO + 0x0224, 589 MMID1 = RMRO + 0x0228, 590 MMIS2 = RMRO + 0x0230, 591 MMIE2 = RMRO + 0x0234, 592 MMID2 = RMRO + 0x0238, 593 MMPFTCT = RMRO + 0x0300, 594 MAPFTCT = RMRO + 0x0304, 595 MPFRCT = RMRO + 0x0308, 596 MFCICT = RMRO + 0x030c, 597 MEEECT = RMRO + 0x0310, 598 MMPCFTCT0 = RMRO + 0x0320, 599 MAPCFTCT0 = RMRO + 0x0330, 600 MPCFRCT0 = RMRO + 0x0340, 601 MHDCC = RMRO + 0x0350, 602 MROVFC = RMRO + 0x0354, 603 MRHCRCEC = RMRO + 0x0358, 604 MRXBCE = RMRO + 0x0400, 605 MRXBCP = RMRO + 0x0404, 606 MRGFCE = RMRO + 0x0408, 607 MRGFCP = RMRO + 0x040c, 608 MRBFC = RMRO + 0x0410, 609 MRMFC = RMRO + 0x0414, 610 MRUFC = RMRO + 0x0418, 611 MRPEFC = RMRO + 0x041c, 612 MRNEFC = RMRO + 0x0420, 613 MRFMEFC = RMRO + 0x0424, 614 MRFFMEFC = RMRO + 0x0428, 615 MRCFCEFC = RMRO + 0x042c, 616 MRFCEFC = RMRO + 0x0430, 617 MRRCFEFC = RMRO + 0x0434, 618 MRUEFC = RMRO + 0x043c, 619 MROEFC = RMRO + 0x0440, 620 MRBOEC = RMRO + 0x0444, 621 MTXBCE = RMRO + 0x0500, 622 MTXBCP = RMRO + 0x0504, 623 MTGFCE = RMRO + 0x0508, 624 MTGFCP = RMRO + 0x050c, 625 MTBFC = RMRO + 0x0510, 626 MTMFC = RMRO + 0x0514, 627 MTUFC = RMRO + 0x0518, 628 MTEFC = RMRO + 0x051c, 629 630 GWMC = GWRO + 0x0000, 631 GWMS = GWRO + 0x0004, 632 GWIRC = GWRO + 0x0010, 633 GWRDQSC = GWRO + 0x0014, 634 GWRDQC = GWRO + 0x0018, 635 GWRDQAC = GWRO + 0x001c, 636 GWRGC = GWRO + 0x0020, 637 GWRMFSC0 = GWRO + 0x0040, 638 GWRDQDC0 = GWRO + 0x0060, 639 GWRDQM0 = GWRO + 0x0080, 640 GWRDQMLM0 = GWRO + 0x00a0, 641 GWMTIRM = GWRO + 0x0100, 642 GWMSTLS = GWRO + 0x0104, 643 GWMSTLR = GWRO + 0x0108, 644 GWMSTSS = GWRO + 0x010c, 645 GWMSTSR = GWRO + 0x0110, 646 GWMAC0 = GWRO + 0x0120, 647 GWMAC1 = GWRO + 0x0124, 648 GWVCC = GWRO + 0x0130, 649 GWVTC = GWRO + 0x0134, 650 GWTTFC = GWRO + 0x0138, 651 GWTDCAC00 = GWRO + 0x0140, 652 GWTDCAC10 = GWRO + 0x0144, 653 GWTSDCC0 = GWRO + 0x0160, 654 GWTNM = GWRO + 0x0180, 655 GWTMNM = GWRO + 0x0184, 656 GWAC = GWRO + 0x0190, 657 GWDCBAC0 = GWRO + 0x0194, 658 GWDCBAC1 = GWRO + 0x0198, 659 GWIICBSC = GWRO + 0x019c, 660 GWMDNC = GWRO + 0x01a0, 661 GWTRC0 = GWRO + 0x0200, 662 GWTPC0 = GWRO + 0x0300, 663 GWARIRM = GWRO + 0x0380, 664 GWDCC0 = GWRO + 0x0400, 665 GWAARSS = GWRO + 0x0800, 666 GWAARSR0 = GWRO + 0x0804, 667 GWAARSR1 = GWRO + 0x0808, 668 GWIDAUAS0 = GWRO + 0x0840, 669 GWIDASM0 = GWRO + 0x0880, 670 GWIDASAM00 = GWRO + 0x0900, 671 GWIDASAM10 = GWRO + 0x0904, 672 GWIDACAM00 = GWRO + 0x0980, 673 GWIDACAM10 = GWRO + 0x0984, 674 GWGRLC = GWRO + 0x0a00, 675 GWGRLULC = GWRO + 0x0a04, 676 GWRLIVC0 = GWRO + 0x0a80, 677 GWRLULC0 = GWRO + 0x0a84, 678 GWIDPC = GWRO + 0x0b00, 679 GWIDC0 = GWRO + 0x0c00, 680 GWDIS0 = GWRO + 0x1100, 681 GWDIE0 = GWRO + 0x1104, 682 GWDID0 = GWRO + 0x1108, 683 GWTSDIS = GWRO + 0x1180, 684 GWTSDIE = GWRO + 0x1184, 685 GWTSDID = GWRO + 0x1188, 686 GWEIS0 = GWRO + 0x1190, 687 GWEIE0 = GWRO + 0x1194, 688 GWEID0 = GWRO + 0x1198, 689 GWEIS1 = GWRO + 0x11a0, 690 GWEIE1 = GWRO + 0x11a4, 691 GWEID1 = GWRO + 0x11a8, 692 GWEIS20 = GWRO + 0x1200, 693 GWEIE20 = GWRO + 0x1204, 694 GWEID20 = GWRO + 0x1208, 695 GWEIS3 = GWRO + 0x1280, 696 GWEIE3 = GWRO + 0x1284, 697 GWEID3 = GWRO + 0x1288, 698 GWEIS4 = GWRO + 0x1290, 699 GWEIE4 = GWRO + 0x1294, 700 GWEID4 = GWRO + 0x1298, 701 GWEIS5 = GWRO + 0x12a0, 702 GWEIE5 = GWRO + 0x12a4, 703 GWEID5 = GWRO + 0x12a8, 704 GWSCR0 = GWRO + 0x1800, 705 GWSCR1 = GWRO + 0x1900, 706 }; 707 708 /* ETHA/RMAC */ 709 enum rswitch_etha_mode { 710 EAMC_OPC_RESET, 711 EAMC_OPC_DISABLE, 712 EAMC_OPC_CONFIG, 713 EAMC_OPC_OPERATION, 714 }; 715 716 #define EAMS_OPS_MASK EAMC_OPC_OPERATION 717 718 #define EAVCC_VEM_SC_TAG (0x3 << 16) 719 720 #define MPIC_PIS_MII 0x00 721 #define MPIC_PIS_GMII 0x02 722 #define MPIC_PIS_XGMII 0x04 723 #define MPIC_LSC_SHIFT 3 724 #define MPIC_LSC_100M (1 << MPIC_LSC_SHIFT) 725 #define MPIC_LSC_1G (2 << MPIC_LSC_SHIFT) 726 #define MPIC_LSC_2_5G (3 << MPIC_LSC_SHIFT) 727 728 #define MDIO_READ_C45 0x03 729 #define MDIO_WRITE_C45 0x01 730 731 #define MPSM_PSME BIT(0) 732 #define MPSM_MFF_C45 BIT(2) 733 #define MPSM_PRD_SHIFT 16 734 #define MPSM_PRD_MASK GENMASK(31, MPSM_PRD_SHIFT) 735 736 /* Completion flags */ 737 #define MMIS1_PAACS BIT(2) /* Address */ 738 #define MMIS1_PWACS BIT(1) /* Write */ 739 #define MMIS1_PRACS BIT(0) /* Read */ 740 #define MMIS1_CLEAR_FLAGS 0xf 741 742 #define MPIC_PSMCS_SHIFT 16 743 #define MPIC_PSMCS_MASK GENMASK(22, MPIC_PSMCS_SHIFT) 744 #define MPIC_PSMCS(val) ((val) << MPIC_PSMCS_SHIFT) 745 746 #define MPIC_PSMHT_SHIFT 24 747 #define MPIC_PSMHT_MASK GENMASK(26, MPIC_PSMHT_SHIFT) 748 #define MPIC_PSMHT(val) ((val) << MPIC_PSMHT_SHIFT) 749 750 #define MLVC_PLV BIT(16) 751 752 /* GWCA */ 753 enum rswitch_gwca_mode { 754 GWMC_OPC_RESET, 755 GWMC_OPC_DISABLE, 756 GWMC_OPC_CONFIG, 757 GWMC_OPC_OPERATION, 758 }; 759 760 #define GWMS_OPS_MASK GWMC_OPC_OPERATION 761 762 #define GWMTIRM_MTIOG BIT(0) 763 #define GWMTIRM_MTR BIT(1) 764 765 #define GWVCC_VEM_SC_TAG (0x3 << 16) 766 767 #define GWARIRM_ARIOG BIT(0) 768 #define GWARIRM_ARR BIT(1) 769 770 #define GWDCC_BALR BIT(24) 771 #define GWDCC_DQT BIT(11) 772 #define GWDCC_ETS BIT(9) 773 #define GWDCC_EDE BIT(8) 774 775 #define GWTRC(queue) (GWTRC0 + (queue) / 32 * 4) 776 #define GWDCC_OFFS(queue) (GWDCC0 + (queue) * 4) 777 778 #define GWDIS(i) (GWDIS0 + (i) * 0x10) 779 #define GWDIE(i) (GWDIE0 + (i) * 0x10) 780 #define GWDID(i) (GWDID0 + (i) * 0x10) 781 782 /* COMA */ 783 #define RRC_RR BIT(0) 784 #define RRC_RR_CLR 0 785 #define RCEC_ACE_DEFAULT (BIT(0) | BIT(AGENT_INDEX_GWCA)) 786 #define RCEC_RCE BIT(16) 787 #define RCDC_RCD BIT(16) 788 789 #define CABPIRM_BPIOG BIT(0) 790 #define CABPIRM_BPR BIT(1) 791 792 /* MFWD */ 793 #define FWPC0_LTHTA BIT(0) 794 #define FWPC0_IP4UE BIT(3) 795 #define FWPC0_IP4TE BIT(4) 796 #define FWPC0_IP4OE BIT(5) 797 #define FWPC0_L2SE BIT(9) 798 #define FWPC0_IP4EA BIT(10) 799 #define FWPC0_IPDSA BIT(12) 800 #define FWPC0_IPHLA BIT(18) 801 #define FWPC0_MACSDA BIT(20) 802 #define FWPC0_MACHLA BIT(26) 803 #define FWPC0_MACHMA BIT(27) 804 #define FWPC0_VLANSA BIT(28) 805 806 #define FWPC0(i) (FWPC00 + (i) * 0x10) 807 #define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \ 808 FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \ 809 FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \ 810 FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA) 811 #define FWPC1(i) (FWPC10 + (i) * 0x10) 812 #define FWPC1_DDE BIT(0) 813 814 #define FWPBFC(i) (FWPBFC0 + (i) * 0x10) 815 816 #define FWPBFCSDC(j, i) (FWPBFCSDC00 + (i) * 0x10 + (j) * 0x04) 817 818 /* TOP */ 819 #define TPEMIMC7(queue) (TPEMIMC70 + (queue) * 4) 820 821 /* Descriptors */ 822 enum RX_DS_CC_BIT { 823 RX_DS = 0x0fff, /* Data size */ 824 RX_TR = 0x1000, /* Truncation indication */ 825 RX_EI = 0x2000, /* Error indication */ 826 RX_PS = 0xc000, /* Padding selection */ 827 }; 828 829 enum TX_DS_TAGL_BIT { 830 TX_DS = 0x0fff, /* Data size */ 831 TX_TAGL = 0xf000, /* Frame tag LSBs */ 832 }; 833 834 enum DIE_DT { 835 /* Frame data */ 836 DT_FSINGLE = 0x80, 837 DT_FSTART = 0x90, 838 DT_FMID = 0xa0, 839 DT_FEND = 0xb0, 840 841 /* Chain control */ 842 DT_LEMPTY = 0xc0, 843 DT_EEMPTY = 0xd0, 844 DT_LINKFIX = 0x00, 845 DT_LINK = 0xe0, 846 DT_EOS = 0xf0, 847 /* HW/SW arbitration */ 848 DT_FEMPTY = 0x40, 849 DT_FEMPTY_IS = 0x10, 850 DT_FEMPTY_IC = 0x20, 851 DT_FEMPTY_ND = 0x30, 852 DT_FEMPTY_START = 0x50, 853 DT_FEMPTY_MID = 0x60, 854 DT_FEMPTY_END = 0x70, 855 856 DT_MASK = 0xf0, 857 DIE = 0x08, /* Descriptor Interrupt Enable */ 858 }; 859 860 /* Both transmission and reception */ 861 #define INFO1_FMT BIT(2) 862 #define INFO1_TXC BIT(3) 863 864 /* For transmission */ 865 #define INFO1_TSUN(val) ((u64)(val) << 8ULL) 866 #define INFO1_CSD0(index) ((u64)(index) << 32ULL) 867 #define INFO1_CSD1(index) ((u64)(index) << 40ULL) 868 #define INFO1_DV(port_vector) ((u64)(port_vector) << 48ULL) 869 870 /* For reception */ 871 #define INFO1_SPN(port) ((u64)(port) << 36ULL) 872 873 /* For timestamp descriptor in dptrl (Byte 4 to 7) */ 874 #define TS_DESC_TSUN(dptrl) ((dptrl) & GENMASK(7, 0)) 875 #define TS_DESC_SPN(dptrl) (((dptrl) & GENMASK(10, 8)) >> 8) 876 #define TS_DESC_DPN(dptrl) (((dptrl) & GENMASK(17, 16)) >> 16) 877 #define TS_DESC_TN(dptrl) ((dptrl) & BIT(24)) 878 879 struct rswitch_desc { 880 __le16 info_ds; /* Descriptor size */ 881 u8 die_dt; /* Descriptor interrupt enable and type */ 882 __u8 dptrh; /* Descriptor pointer MSB */ 883 __le32 dptrl; /* Descriptor pointer LSW */ 884 } __packed; 885 886 struct rswitch_ts_desc { 887 struct rswitch_desc desc; 888 __le32 ts_nsec; 889 __le32 ts_sec; 890 } __packed; 891 892 struct rswitch_ext_desc { 893 struct rswitch_desc desc; 894 __le64 info1; 895 } __packed; 896 897 struct rswitch_ext_ts_desc { 898 struct rswitch_desc desc; 899 __le64 info1; 900 __le32 ts_nsec; 901 __le32 ts_sec; 902 } __packed; 903 904 struct rswitch_etha { 905 int index; 906 void __iomem *addr; 907 void __iomem *coma_addr; 908 bool external_phy; 909 struct mii_bus *mii; 910 phy_interface_t phy_interface; 911 u8 mac_addr[MAX_ADDR_LEN]; 912 int link; 913 int speed; 914 915 /* This hardware could not be initialized twice so that marked 916 * this flag to avoid multiple initialization. 917 */ 918 bool operated; 919 }; 920 921 /* The datasheet said descriptor "chain" and/or "queue". For consistency of 922 * name, this driver calls "queue". 923 */ 924 struct rswitch_gwca_queue { 925 union { 926 struct rswitch_ext_desc *tx_ring; 927 struct rswitch_ext_ts_desc *rx_ring; 928 struct rswitch_ts_desc *ts_ring; 929 }; 930 931 /* Common */ 932 dma_addr_t ring_dma; 933 int ring_size; 934 int cur; 935 int dirty; 936 937 /* For [rt]_ring */ 938 int index; 939 bool dir_tx; 940 struct sk_buff **skbs; 941 struct net_device *ndev; /* queue to ndev for irq */ 942 }; 943 944 struct rswitch_gwca_ts_info { 945 struct sk_buff *skb; 946 struct list_head list; 947 948 int port; 949 u8 tag; 950 }; 951 952 #define RSWITCH_NUM_IRQ_REGS (RSWITCH_MAX_NUM_QUEUES / BITS_PER_TYPE(u32)) 953 struct rswitch_gwca { 954 int index; 955 struct rswitch_desc *linkfix_table; 956 dma_addr_t linkfix_table_dma; 957 u32 linkfix_table_size; 958 struct rswitch_gwca_queue *queues; 959 int num_queues; 960 struct rswitch_gwca_queue ts_queue; 961 struct list_head ts_info_list; 962 DECLARE_BITMAP(used, RSWITCH_MAX_NUM_QUEUES); 963 u32 tx_irq_bits[RSWITCH_NUM_IRQ_REGS]; 964 u32 rx_irq_bits[RSWITCH_NUM_IRQ_REGS]; 965 int speed; 966 }; 967 968 #define NUM_QUEUES_PER_NDEV 2 969 struct rswitch_device { 970 struct rswitch_private *priv; 971 struct net_device *ndev; 972 struct napi_struct napi; 973 void __iomem *addr; 974 struct rswitch_gwca_queue *tx_queue; 975 struct rswitch_gwca_queue *rx_queue; 976 u8 ts_tag; 977 bool disabled; 978 979 int port; 980 struct rswitch_etha *etha; 981 struct device_node *np_port; 982 struct phy *serdes; 983 }; 984 985 struct rswitch_mfwd_mac_table_entry { 986 int queue_index; 987 unsigned char addr[MAX_ADDR_LEN]; 988 }; 989 990 struct rswitch_mfwd { 991 struct rswitch_mac_table_entry *mac_table_entries; 992 int num_mac_table_entries; 993 }; 994 995 struct rswitch_private { 996 struct platform_device *pdev; 997 void __iomem *addr; 998 struct rcar_gen4_ptp_private *ptp_priv; 999 1000 struct rswitch_device *rdev[RSWITCH_NUM_PORTS]; 1001 DECLARE_BITMAP(opened_ports, RSWITCH_NUM_PORTS); 1002 1003 struct rswitch_gwca gwca; 1004 struct rswitch_etha etha[RSWITCH_NUM_PORTS]; 1005 struct rswitch_mfwd mfwd; 1006 1007 bool gwca_halt; 1008 }; 1009 1010 #endif /* #ifndef __RSWITCH_H__ */ 1011