1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet Switch device driver 3 * 4 * Copyright (C) 2022 Renesas Electronics Corporation 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/etherdevice.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/of.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/rtnetlink.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 #include <linux/sys_soc.h> 25 26 #include "rswitch.h" 27 28 static int rswitch_reg_wait(void __iomem *addr, u32 offs, u32 mask, u32 expected) 29 { 30 u32 val; 31 32 return readl_poll_timeout_atomic(addr + offs, val, (val & mask) == expected, 33 1, RSWITCH_TIMEOUT_US); 34 } 35 36 static void rswitch_modify(void __iomem *addr, enum rswitch_reg reg, u32 clear, u32 set) 37 { 38 iowrite32((ioread32(addr + reg) & ~clear) | set, addr + reg); 39 } 40 41 /* Common Agent block (COMA) */ 42 static void rswitch_reset(struct rswitch_private *priv) 43 { 44 iowrite32(RRC_RR, priv->addr + RRC); 45 iowrite32(RRC_RR_CLR, priv->addr + RRC); 46 } 47 48 static void rswitch_clock_enable(struct rswitch_private *priv) 49 { 50 iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC); 51 } 52 53 static void rswitch_clock_disable(struct rswitch_private *priv) 54 { 55 iowrite32(RCDC_RCD, priv->addr + RCDC); 56 } 57 58 static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr, 59 unsigned int port) 60 { 61 u32 val = ioread32(coma_addr + RCEC); 62 63 if (val & RCEC_RCE) 64 return (val & BIT(port)) ? true : false; 65 else 66 return false; 67 } 68 69 static void rswitch_agent_clock_ctrl(void __iomem *coma_addr, unsigned int port, 70 int enable) 71 { 72 u32 val; 73 74 if (enable) { 75 val = ioread32(coma_addr + RCEC); 76 iowrite32(val | RCEC_RCE | BIT(port), coma_addr + RCEC); 77 } else { 78 val = ioread32(coma_addr + RCDC); 79 iowrite32(val | BIT(port), coma_addr + RCDC); 80 } 81 } 82 83 static int rswitch_bpool_config(struct rswitch_private *priv) 84 { 85 u32 val; 86 87 val = ioread32(priv->addr + CABPIRM); 88 if (val & CABPIRM_BPR) 89 return 0; 90 91 iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM); 92 93 return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR); 94 } 95 96 static void rswitch_coma_init(struct rswitch_private *priv) 97 { 98 iowrite32(CABPPFLC_INIT_VALUE, priv->addr + CABPPFLC0); 99 } 100 101 /* R-Switch-2 block (TOP) */ 102 static void rswitch_top_init(struct rswitch_private *priv) 103 { 104 unsigned int i; 105 106 for (i = 0; i < RSWITCH_MAX_NUM_QUEUES; i++) 107 iowrite32((i / 16) << (GWCA_INDEX * 8), priv->addr + TPEMIMC7(i)); 108 } 109 110 /* Forwarding engine block (MFWD) */ 111 static void rswitch_fwd_init(struct rswitch_private *priv) 112 { 113 unsigned int i; 114 115 /* For ETHA */ 116 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 117 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(i)); 118 iowrite32(0, priv->addr + FWPBFC(i)); 119 } 120 121 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 122 iowrite32(priv->rdev[i]->rx_queue->index, 123 priv->addr + FWPBFCSDC(GWCA_INDEX, i)); 124 iowrite32(BIT(priv->gwca.index), priv->addr + FWPBFC(i)); 125 } 126 127 /* For GWCA */ 128 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(priv->gwca.index)); 129 iowrite32(FWPC1_DDE, priv->addr + FWPC1(priv->gwca.index)); 130 iowrite32(0, priv->addr + FWPBFC(priv->gwca.index)); 131 iowrite32(GENMASK(RSWITCH_NUM_PORTS - 1, 0), priv->addr + FWPBFC(priv->gwca.index)); 132 } 133 134 /* Gateway CPU agent block (GWCA) */ 135 static int rswitch_gwca_change_mode(struct rswitch_private *priv, 136 enum rswitch_gwca_mode mode) 137 { 138 int ret; 139 140 if (!rswitch_agent_clock_is_enabled(priv->addr, priv->gwca.index)) 141 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 1); 142 143 iowrite32(mode, priv->addr + GWMC); 144 145 ret = rswitch_reg_wait(priv->addr, GWMS, GWMS_OPS_MASK, mode); 146 147 if (mode == GWMC_OPC_DISABLE) 148 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 0); 149 150 return ret; 151 } 152 153 static int rswitch_gwca_mcast_table_reset(struct rswitch_private *priv) 154 { 155 iowrite32(GWMTIRM_MTIOG, priv->addr + GWMTIRM); 156 157 return rswitch_reg_wait(priv->addr, GWMTIRM, GWMTIRM_MTR, GWMTIRM_MTR); 158 } 159 160 static int rswitch_gwca_axi_ram_reset(struct rswitch_private *priv) 161 { 162 iowrite32(GWARIRM_ARIOG, priv->addr + GWARIRM); 163 164 return rswitch_reg_wait(priv->addr, GWARIRM, GWARIRM_ARR, GWARIRM_ARR); 165 } 166 167 static bool rswitch_is_any_data_irq(struct rswitch_private *priv, u32 *dis, bool tx) 168 { 169 u32 *mask = tx ? priv->gwca.tx_irq_bits : priv->gwca.rx_irq_bits; 170 unsigned int i; 171 172 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 173 if (dis[i] & mask[i]) 174 return true; 175 } 176 177 return false; 178 } 179 180 static void rswitch_get_data_irq_status(struct rswitch_private *priv, u32 *dis) 181 { 182 unsigned int i; 183 184 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 185 dis[i] = ioread32(priv->addr + GWDIS(i)); 186 dis[i] &= ioread32(priv->addr + GWDIE(i)); 187 } 188 } 189 190 static void rswitch_enadis_data_irq(struct rswitch_private *priv, 191 unsigned int index, bool enable) 192 { 193 u32 offs = enable ? GWDIE(index / 32) : GWDID(index / 32); 194 195 iowrite32(BIT(index % 32), priv->addr + offs); 196 } 197 198 static void rswitch_ack_data_irq(struct rswitch_private *priv, 199 unsigned int index) 200 { 201 u32 offs = GWDIS(index / 32); 202 203 iowrite32(BIT(index % 32), priv->addr + offs); 204 } 205 206 static unsigned int rswitch_next_queue_index(struct rswitch_gwca_queue *gq, 207 bool cur, unsigned int num) 208 { 209 unsigned int index = cur ? gq->cur : gq->dirty; 210 211 if (index + num >= gq->ring_size) 212 index = (index + num) % gq->ring_size; 213 else 214 index += num; 215 216 return index; 217 } 218 219 static unsigned int rswitch_get_num_cur_queues(struct rswitch_gwca_queue *gq) 220 { 221 if (gq->cur >= gq->dirty) 222 return gq->cur - gq->dirty; 223 else 224 return gq->ring_size - gq->dirty + gq->cur; 225 } 226 227 static bool rswitch_is_queue_rxed(struct rswitch_gwca_queue *gq) 228 { 229 struct rswitch_ext_ts_desc *desc = &gq->rx_ring[gq->dirty]; 230 231 if ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) 232 return true; 233 234 return false; 235 } 236 237 static int rswitch_gwca_queue_alloc_rx_buf(struct rswitch_gwca_queue *gq, 238 unsigned int start_index, 239 unsigned int num) 240 { 241 unsigned int i, index; 242 243 for (i = 0; i < num; i++) { 244 index = (i + start_index) % gq->ring_size; 245 if (gq->rx_bufs[index]) 246 continue; 247 gq->rx_bufs[index] = netdev_alloc_frag(RSWITCH_BUF_SIZE); 248 if (!gq->rx_bufs[index]) 249 goto err; 250 } 251 252 return 0; 253 254 err: 255 for (; i-- > 0; ) { 256 index = (i + start_index) % gq->ring_size; 257 skb_free_frag(gq->rx_bufs[index]); 258 gq->rx_bufs[index] = NULL; 259 } 260 261 return -ENOMEM; 262 } 263 264 static void rswitch_gwca_queue_free(struct net_device *ndev, 265 struct rswitch_gwca_queue *gq) 266 { 267 unsigned int i; 268 269 if (!gq->dir_tx) { 270 dma_free_coherent(ndev->dev.parent, 271 sizeof(struct rswitch_ext_ts_desc) * 272 (gq->ring_size + 1), gq->rx_ring, gq->ring_dma); 273 gq->rx_ring = NULL; 274 275 for (i = 0; i < gq->ring_size; i++) 276 skb_free_frag(gq->rx_bufs[i]); 277 kfree(gq->rx_bufs); 278 gq->rx_bufs = NULL; 279 } else { 280 dma_free_coherent(ndev->dev.parent, 281 sizeof(struct rswitch_ext_desc) * 282 (gq->ring_size + 1), gq->tx_ring, gq->ring_dma); 283 gq->tx_ring = NULL; 284 kfree(gq->skbs); 285 gq->skbs = NULL; 286 kfree(gq->unmap_addrs); 287 gq->unmap_addrs = NULL; 288 } 289 } 290 291 static void rswitch_gwca_ts_queue_free(struct rswitch_private *priv) 292 { 293 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 294 295 dma_free_coherent(&priv->pdev->dev, 296 sizeof(struct rswitch_ts_desc) * (gq->ring_size + 1), 297 gq->ts_ring, gq->ring_dma); 298 gq->ts_ring = NULL; 299 } 300 301 static int rswitch_gwca_queue_alloc(struct net_device *ndev, 302 struct rswitch_private *priv, 303 struct rswitch_gwca_queue *gq, 304 bool dir_tx, unsigned int ring_size) 305 { 306 unsigned int i, bit; 307 308 gq->dir_tx = dir_tx; 309 gq->ring_size = ring_size; 310 gq->ndev = ndev; 311 312 if (!dir_tx) { 313 gq->rx_bufs = kcalloc(gq->ring_size, sizeof(*gq->rx_bufs), GFP_KERNEL); 314 if (!gq->rx_bufs) 315 return -ENOMEM; 316 if (rswitch_gwca_queue_alloc_rx_buf(gq, 0, gq->ring_size) < 0) 317 goto out; 318 319 gq->rx_ring = dma_alloc_coherent(ndev->dev.parent, 320 sizeof(struct rswitch_ext_ts_desc) * 321 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 322 } else { 323 gq->skbs = kcalloc(gq->ring_size, sizeof(*gq->skbs), GFP_KERNEL); 324 if (!gq->skbs) 325 return -ENOMEM; 326 gq->unmap_addrs = kcalloc(gq->ring_size, sizeof(*gq->unmap_addrs), GFP_KERNEL); 327 if (!gq->unmap_addrs) 328 goto out; 329 gq->tx_ring = dma_alloc_coherent(ndev->dev.parent, 330 sizeof(struct rswitch_ext_desc) * 331 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 332 } 333 334 if (!gq->rx_ring && !gq->tx_ring) 335 goto out; 336 337 i = gq->index / 32; 338 bit = BIT(gq->index % 32); 339 if (dir_tx) 340 priv->gwca.tx_irq_bits[i] |= bit; 341 else 342 priv->gwca.rx_irq_bits[i] |= bit; 343 344 return 0; 345 346 out: 347 rswitch_gwca_queue_free(ndev, gq); 348 349 return -ENOMEM; 350 } 351 352 static void rswitch_desc_set_dptr(struct rswitch_desc *desc, dma_addr_t addr) 353 { 354 desc->dptrl = cpu_to_le32(lower_32_bits(addr)); 355 desc->dptrh = upper_32_bits(addr) & 0xff; 356 } 357 358 static dma_addr_t rswitch_desc_get_dptr(const struct rswitch_desc *desc) 359 { 360 return __le32_to_cpu(desc->dptrl) | (u64)(desc->dptrh) << 32; 361 } 362 363 static int rswitch_gwca_queue_format(struct net_device *ndev, 364 struct rswitch_private *priv, 365 struct rswitch_gwca_queue *gq) 366 { 367 unsigned int ring_size = sizeof(struct rswitch_ext_desc) * gq->ring_size; 368 struct rswitch_ext_desc *desc; 369 struct rswitch_desc *linkfix; 370 dma_addr_t dma_addr; 371 unsigned int i; 372 373 memset(gq->tx_ring, 0, ring_size); 374 for (i = 0, desc = gq->tx_ring; i < gq->ring_size; i++, desc++) { 375 if (!gq->dir_tx) { 376 dma_addr = dma_map_single(ndev->dev.parent, 377 gq->rx_bufs[i] + RSWITCH_HEADROOM, 378 RSWITCH_MAP_BUF_SIZE, 379 DMA_FROM_DEVICE); 380 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 381 goto err; 382 383 desc->desc.info_ds = cpu_to_le16(RSWITCH_DESC_BUF_SIZE); 384 rswitch_desc_set_dptr(&desc->desc, dma_addr); 385 desc->desc.die_dt = DT_FEMPTY | DIE; 386 } else { 387 desc->desc.die_dt = DT_EEMPTY | DIE; 388 } 389 } 390 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 391 desc->desc.die_dt = DT_LINKFIX; 392 393 linkfix = &priv->gwca.linkfix_table[gq->index]; 394 linkfix->die_dt = DT_LINKFIX; 395 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 396 397 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DCP(GWCA_IPV_NUM) | GWDCC_DQT : 0) | GWDCC_EDE, 398 priv->addr + GWDCC_OFFS(gq->index)); 399 400 return 0; 401 402 err: 403 if (!gq->dir_tx) { 404 for (desc = gq->tx_ring; i-- > 0; desc++) { 405 dma_addr = rswitch_desc_get_dptr(&desc->desc); 406 dma_unmap_single(ndev->dev.parent, dma_addr, 407 RSWITCH_MAP_BUF_SIZE, DMA_FROM_DEVICE); 408 } 409 } 410 411 return -ENOMEM; 412 } 413 414 static void rswitch_gwca_ts_queue_fill(struct rswitch_private *priv, 415 unsigned int start_index, 416 unsigned int num) 417 { 418 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 419 struct rswitch_ts_desc *desc; 420 unsigned int i, index; 421 422 for (i = 0; i < num; i++) { 423 index = (i + start_index) % gq->ring_size; 424 desc = &gq->ts_ring[index]; 425 desc->desc.die_dt = DT_FEMPTY_ND | DIE; 426 } 427 } 428 429 static int rswitch_gwca_queue_ext_ts_fill(struct net_device *ndev, 430 struct rswitch_gwca_queue *gq, 431 unsigned int start_index, 432 unsigned int num) 433 { 434 struct rswitch_device *rdev = netdev_priv(ndev); 435 struct rswitch_ext_ts_desc *desc; 436 unsigned int i, index; 437 dma_addr_t dma_addr; 438 439 for (i = 0; i < num; i++) { 440 index = (i + start_index) % gq->ring_size; 441 desc = &gq->rx_ring[index]; 442 if (!gq->dir_tx) { 443 dma_addr = dma_map_single(ndev->dev.parent, 444 gq->rx_bufs[index] + RSWITCH_HEADROOM, 445 RSWITCH_MAP_BUF_SIZE, 446 DMA_FROM_DEVICE); 447 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 448 goto err; 449 450 desc->desc.info_ds = cpu_to_le16(RSWITCH_DESC_BUF_SIZE); 451 rswitch_desc_set_dptr(&desc->desc, dma_addr); 452 dma_wmb(); 453 desc->desc.die_dt = DT_FEMPTY | DIE; 454 desc->info1 = cpu_to_le64(INFO1_SPN(rdev->etha->index)); 455 } else { 456 desc->desc.die_dt = DT_EEMPTY | DIE; 457 } 458 } 459 460 return 0; 461 462 err: 463 if (!gq->dir_tx) { 464 for (; i-- > 0; ) { 465 index = (i + start_index) % gq->ring_size; 466 desc = &gq->rx_ring[index]; 467 dma_addr = rswitch_desc_get_dptr(&desc->desc); 468 dma_unmap_single(ndev->dev.parent, dma_addr, 469 RSWITCH_MAP_BUF_SIZE, DMA_FROM_DEVICE); 470 } 471 } 472 473 return -ENOMEM; 474 } 475 476 static int rswitch_gwca_queue_ext_ts_format(struct net_device *ndev, 477 struct rswitch_private *priv, 478 struct rswitch_gwca_queue *gq) 479 { 480 unsigned int ring_size = sizeof(struct rswitch_ext_ts_desc) * gq->ring_size; 481 struct rswitch_ext_ts_desc *desc; 482 struct rswitch_desc *linkfix; 483 int err; 484 485 memset(gq->rx_ring, 0, ring_size); 486 err = rswitch_gwca_queue_ext_ts_fill(ndev, gq, 0, gq->ring_size); 487 if (err < 0) 488 return err; 489 490 desc = &gq->rx_ring[gq->ring_size]; /* Last */ 491 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 492 desc->desc.die_dt = DT_LINKFIX; 493 494 linkfix = &priv->gwca.linkfix_table[gq->index]; 495 linkfix->die_dt = DT_LINKFIX; 496 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 497 498 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DCP(GWCA_IPV_NUM) | GWDCC_DQT : 0) | 499 GWDCC_ETS | GWDCC_EDE, 500 priv->addr + GWDCC_OFFS(gq->index)); 501 502 return 0; 503 } 504 505 static int rswitch_gwca_linkfix_alloc(struct rswitch_private *priv) 506 { 507 unsigned int i, num_queues = priv->gwca.num_queues; 508 struct rswitch_gwca *gwca = &priv->gwca; 509 struct device *dev = &priv->pdev->dev; 510 511 gwca->linkfix_table_size = sizeof(struct rswitch_desc) * num_queues; 512 gwca->linkfix_table = dma_alloc_coherent(dev, gwca->linkfix_table_size, 513 &gwca->linkfix_table_dma, GFP_KERNEL); 514 if (!gwca->linkfix_table) 515 return -ENOMEM; 516 for (i = 0; i < num_queues; i++) 517 gwca->linkfix_table[i].die_dt = DT_EOS; 518 519 return 0; 520 } 521 522 static void rswitch_gwca_linkfix_free(struct rswitch_private *priv) 523 { 524 struct rswitch_gwca *gwca = &priv->gwca; 525 526 if (gwca->linkfix_table) 527 dma_free_coherent(&priv->pdev->dev, gwca->linkfix_table_size, 528 gwca->linkfix_table, gwca->linkfix_table_dma); 529 gwca->linkfix_table = NULL; 530 } 531 532 static int rswitch_gwca_ts_queue_alloc(struct rswitch_private *priv) 533 { 534 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 535 struct rswitch_ts_desc *desc; 536 537 gq->ring_size = TS_RING_SIZE; 538 gq->ts_ring = dma_alloc_coherent(&priv->pdev->dev, 539 sizeof(struct rswitch_ts_desc) * 540 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 541 542 if (!gq->ts_ring) 543 return -ENOMEM; 544 545 rswitch_gwca_ts_queue_fill(priv, 0, TS_RING_SIZE); 546 desc = &gq->ts_ring[gq->ring_size]; 547 desc->desc.die_dt = DT_LINKFIX; 548 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 549 INIT_LIST_HEAD(&priv->gwca.ts_info_list); 550 551 return 0; 552 } 553 554 static struct rswitch_gwca_queue *rswitch_gwca_get(struct rswitch_private *priv) 555 { 556 struct rswitch_gwca_queue *gq; 557 unsigned int index; 558 559 index = find_first_zero_bit(priv->gwca.used, priv->gwca.num_queues); 560 if (index >= priv->gwca.num_queues) 561 return NULL; 562 set_bit(index, priv->gwca.used); 563 gq = &priv->gwca.queues[index]; 564 memset(gq, 0, sizeof(*gq)); 565 gq->index = index; 566 567 return gq; 568 } 569 570 static void rswitch_gwca_put(struct rswitch_private *priv, 571 struct rswitch_gwca_queue *gq) 572 { 573 clear_bit(gq->index, priv->gwca.used); 574 } 575 576 static int rswitch_txdmac_alloc(struct net_device *ndev) 577 { 578 struct rswitch_device *rdev = netdev_priv(ndev); 579 struct rswitch_private *priv = rdev->priv; 580 int err; 581 582 rdev->tx_queue = rswitch_gwca_get(priv); 583 if (!rdev->tx_queue) 584 return -EBUSY; 585 586 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->tx_queue, true, TX_RING_SIZE); 587 if (err < 0) { 588 rswitch_gwca_put(priv, rdev->tx_queue); 589 return err; 590 } 591 592 return 0; 593 } 594 595 static void rswitch_txdmac_free(struct net_device *ndev) 596 { 597 struct rswitch_device *rdev = netdev_priv(ndev); 598 599 rswitch_gwca_queue_free(ndev, rdev->tx_queue); 600 rswitch_gwca_put(rdev->priv, rdev->tx_queue); 601 } 602 603 static int rswitch_txdmac_init(struct rswitch_private *priv, unsigned int index) 604 { 605 struct rswitch_device *rdev = priv->rdev[index]; 606 607 return rswitch_gwca_queue_format(rdev->ndev, priv, rdev->tx_queue); 608 } 609 610 static int rswitch_rxdmac_alloc(struct net_device *ndev) 611 { 612 struct rswitch_device *rdev = netdev_priv(ndev); 613 struct rswitch_private *priv = rdev->priv; 614 int err; 615 616 rdev->rx_queue = rswitch_gwca_get(priv); 617 if (!rdev->rx_queue) 618 return -EBUSY; 619 620 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->rx_queue, false, RX_RING_SIZE); 621 if (err < 0) { 622 rswitch_gwca_put(priv, rdev->rx_queue); 623 return err; 624 } 625 626 return 0; 627 } 628 629 static void rswitch_rxdmac_free(struct net_device *ndev) 630 { 631 struct rswitch_device *rdev = netdev_priv(ndev); 632 633 rswitch_gwca_queue_free(ndev, rdev->rx_queue); 634 rswitch_gwca_put(rdev->priv, rdev->rx_queue); 635 } 636 637 static int rswitch_rxdmac_init(struct rswitch_private *priv, unsigned int index) 638 { 639 struct rswitch_device *rdev = priv->rdev[index]; 640 struct net_device *ndev = rdev->ndev; 641 642 return rswitch_gwca_queue_ext_ts_format(ndev, priv, rdev->rx_queue); 643 } 644 645 static int rswitch_gwca_hw_init(struct rswitch_private *priv) 646 { 647 unsigned int i; 648 int err; 649 650 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 651 if (err < 0) 652 return err; 653 err = rswitch_gwca_change_mode(priv, GWMC_OPC_CONFIG); 654 if (err < 0) 655 return err; 656 657 err = rswitch_gwca_mcast_table_reset(priv); 658 if (err < 0) 659 return err; 660 err = rswitch_gwca_axi_ram_reset(priv); 661 if (err < 0) 662 return err; 663 664 iowrite32(GWVCC_VEM_SC_TAG, priv->addr + GWVCC); 665 iowrite32(0, priv->addr + GWTTFC); 666 iowrite32(lower_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC1); 667 iowrite32(upper_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC0); 668 iowrite32(lower_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC10); 669 iowrite32(upper_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC00); 670 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDCC0); 671 672 iowrite32(GWTPC_PPPL(GWCA_IPV_NUM), priv->addr + GWTPC0); 673 674 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 675 err = rswitch_rxdmac_init(priv, i); 676 if (err < 0) 677 return err; 678 err = rswitch_txdmac_init(priv, i); 679 if (err < 0) 680 return err; 681 } 682 683 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 684 if (err < 0) 685 return err; 686 return rswitch_gwca_change_mode(priv, GWMC_OPC_OPERATION); 687 } 688 689 static int rswitch_gwca_hw_deinit(struct rswitch_private *priv) 690 { 691 int err; 692 693 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 694 if (err < 0) 695 return err; 696 err = rswitch_gwca_change_mode(priv, GWMC_OPC_RESET); 697 if (err < 0) 698 return err; 699 700 return rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 701 } 702 703 static int rswitch_gwca_halt(struct rswitch_private *priv) 704 { 705 int err; 706 707 priv->gwca_halt = true; 708 err = rswitch_gwca_hw_deinit(priv); 709 dev_err(&priv->pdev->dev, "halted (%d)\n", err); 710 711 return err; 712 } 713 714 static bool rswitch_rx(struct net_device *ndev, int *quota) 715 { 716 struct rswitch_device *rdev = netdev_priv(ndev); 717 struct rswitch_gwca_queue *gq = rdev->rx_queue; 718 struct rswitch_ext_ts_desc *desc; 719 int limit, boguscnt, ret; 720 struct sk_buff *skb; 721 dma_addr_t dma_addr; 722 unsigned int num; 723 u16 pkt_len; 724 u32 get_ts; 725 726 if (*quota <= 0) 727 return true; 728 729 boguscnt = min_t(int, gq->ring_size, *quota); 730 limit = boguscnt; 731 732 desc = &gq->rx_ring[gq->cur]; 733 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) { 734 dma_rmb(); 735 pkt_len = le16_to_cpu(desc->desc.info_ds) & RX_DS; 736 dma_addr = rswitch_desc_get_dptr(&desc->desc); 737 dma_unmap_single(ndev->dev.parent, dma_addr, 738 RSWITCH_MAP_BUF_SIZE, DMA_FROM_DEVICE); 739 skb = build_skb(gq->rx_bufs[gq->cur], RSWITCH_BUF_SIZE); 740 if (!skb) 741 goto out; 742 skb_reserve(skb, RSWITCH_HEADROOM); 743 skb_put(skb, pkt_len); 744 745 get_ts = rdev->priv->ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 746 if (get_ts) { 747 struct skb_shared_hwtstamps *shhwtstamps; 748 struct timespec64 ts; 749 750 shhwtstamps = skb_hwtstamps(skb); 751 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 752 ts.tv_sec = __le32_to_cpu(desc->ts_sec); 753 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); 754 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 755 } 756 skb->protocol = eth_type_trans(skb, ndev); 757 napi_gro_receive(&rdev->napi, skb); 758 rdev->ndev->stats.rx_packets++; 759 rdev->ndev->stats.rx_bytes += pkt_len; 760 761 out: 762 gq->rx_bufs[gq->cur] = NULL; 763 gq->cur = rswitch_next_queue_index(gq, true, 1); 764 desc = &gq->rx_ring[gq->cur]; 765 766 if (--boguscnt <= 0) 767 break; 768 } 769 770 num = rswitch_get_num_cur_queues(gq); 771 ret = rswitch_gwca_queue_alloc_rx_buf(gq, gq->dirty, num); 772 if (ret < 0) 773 goto err; 774 ret = rswitch_gwca_queue_ext_ts_fill(ndev, gq, gq->dirty, num); 775 if (ret < 0) 776 goto err; 777 gq->dirty = rswitch_next_queue_index(gq, false, num); 778 779 *quota -= limit - boguscnt; 780 781 return boguscnt <= 0; 782 783 err: 784 rswitch_gwca_halt(rdev->priv); 785 786 return 0; 787 } 788 789 static void rswitch_tx_free(struct net_device *ndev) 790 { 791 struct rswitch_device *rdev = netdev_priv(ndev); 792 struct rswitch_gwca_queue *gq = rdev->tx_queue; 793 struct rswitch_ext_desc *desc; 794 struct sk_buff *skb; 795 796 desc = &gq->tx_ring[gq->dirty]; 797 while ((desc->desc.die_dt & DT_MASK) == DT_FEMPTY) { 798 dma_rmb(); 799 800 skb = gq->skbs[gq->dirty]; 801 if (skb) { 802 rdev->ndev->stats.tx_packets++; 803 rdev->ndev->stats.tx_bytes += skb->len; 804 dma_unmap_single(ndev->dev.parent, 805 gq->unmap_addrs[gq->dirty], 806 skb->len, DMA_TO_DEVICE); 807 dev_kfree_skb_any(gq->skbs[gq->dirty]); 808 gq->skbs[gq->dirty] = NULL; 809 } 810 811 desc->desc.die_dt = DT_EEMPTY; 812 gq->dirty = rswitch_next_queue_index(gq, false, 1); 813 desc = &gq->tx_ring[gq->dirty]; 814 } 815 } 816 817 static int rswitch_poll(struct napi_struct *napi, int budget) 818 { 819 struct net_device *ndev = napi->dev; 820 struct rswitch_private *priv; 821 struct rswitch_device *rdev; 822 unsigned long flags; 823 int quota = budget; 824 825 rdev = netdev_priv(ndev); 826 priv = rdev->priv; 827 828 retry: 829 rswitch_tx_free(ndev); 830 831 if (rswitch_rx(ndev, "a)) 832 goto out; 833 else if (rdev->priv->gwca_halt) 834 goto err; 835 else if (rswitch_is_queue_rxed(rdev->rx_queue)) 836 goto retry; 837 838 netif_wake_subqueue(ndev, 0); 839 840 if (napi_complete_done(napi, budget - quota)) { 841 spin_lock_irqsave(&priv->lock, flags); 842 if (test_bit(rdev->port, priv->opened_ports)) { 843 rswitch_enadis_data_irq(priv, rdev->tx_queue->index, true); 844 rswitch_enadis_data_irq(priv, rdev->rx_queue->index, true); 845 } 846 spin_unlock_irqrestore(&priv->lock, flags); 847 } 848 849 out: 850 return budget - quota; 851 852 err: 853 napi_complete(napi); 854 855 return 0; 856 } 857 858 static void rswitch_queue_interrupt(struct net_device *ndev) 859 { 860 struct rswitch_device *rdev = netdev_priv(ndev); 861 862 if (napi_schedule_prep(&rdev->napi)) { 863 spin_lock(&rdev->priv->lock); 864 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 865 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 866 spin_unlock(&rdev->priv->lock); 867 __napi_schedule(&rdev->napi); 868 } 869 } 870 871 static irqreturn_t rswitch_data_irq(struct rswitch_private *priv, u32 *dis) 872 { 873 struct rswitch_gwca_queue *gq; 874 unsigned int i, index, bit; 875 876 for (i = 0; i < priv->gwca.num_queues; i++) { 877 gq = &priv->gwca.queues[i]; 878 index = gq->index / 32; 879 bit = BIT(gq->index % 32); 880 if (!(dis[index] & bit)) 881 continue; 882 883 rswitch_ack_data_irq(priv, gq->index); 884 rswitch_queue_interrupt(gq->ndev); 885 } 886 887 return IRQ_HANDLED; 888 } 889 890 static irqreturn_t rswitch_gwca_irq(int irq, void *dev_id) 891 { 892 struct rswitch_private *priv = dev_id; 893 u32 dis[RSWITCH_NUM_IRQ_REGS]; 894 irqreturn_t ret = IRQ_NONE; 895 896 rswitch_get_data_irq_status(priv, dis); 897 898 if (rswitch_is_any_data_irq(priv, dis, true) || 899 rswitch_is_any_data_irq(priv, dis, false)) 900 ret = rswitch_data_irq(priv, dis); 901 902 return ret; 903 } 904 905 static int rswitch_gwca_request_irqs(struct rswitch_private *priv) 906 { 907 char *resource_name, *irq_name; 908 int i, ret, irq; 909 910 for (i = 0; i < GWCA_NUM_IRQS; i++) { 911 resource_name = kasprintf(GFP_KERNEL, GWCA_IRQ_RESOURCE_NAME, i); 912 if (!resource_name) 913 return -ENOMEM; 914 915 irq = platform_get_irq_byname(priv->pdev, resource_name); 916 kfree(resource_name); 917 if (irq < 0) 918 return irq; 919 920 irq_name = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL, 921 GWCA_IRQ_NAME, i); 922 if (!irq_name) 923 return -ENOMEM; 924 925 ret = devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_irq, 926 0, irq_name, priv); 927 if (ret < 0) 928 return ret; 929 } 930 931 return 0; 932 } 933 934 static void rswitch_ts(struct rswitch_private *priv) 935 { 936 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 937 struct rswitch_gwca_ts_info *ts_info, *ts_info2; 938 struct skb_shared_hwtstamps shhwtstamps; 939 struct rswitch_ts_desc *desc; 940 struct timespec64 ts; 941 unsigned int num; 942 u32 tag, port; 943 944 desc = &gq->ts_ring[gq->cur]; 945 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY_ND) { 946 dma_rmb(); 947 948 port = TS_DESC_DPN(__le32_to_cpu(desc->desc.dptrl)); 949 tag = TS_DESC_TSUN(__le32_to_cpu(desc->desc.dptrl)); 950 951 list_for_each_entry_safe(ts_info, ts_info2, &priv->gwca.ts_info_list, list) { 952 if (!(ts_info->port == port && ts_info->tag == tag)) 953 continue; 954 955 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 956 ts.tv_sec = __le32_to_cpu(desc->ts_sec); 957 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); 958 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 959 skb_tstamp_tx(ts_info->skb, &shhwtstamps); 960 dev_consume_skb_irq(ts_info->skb); 961 list_del(&ts_info->list); 962 kfree(ts_info); 963 break; 964 } 965 966 gq->cur = rswitch_next_queue_index(gq, true, 1); 967 desc = &gq->ts_ring[gq->cur]; 968 } 969 970 num = rswitch_get_num_cur_queues(gq); 971 rswitch_gwca_ts_queue_fill(priv, gq->dirty, num); 972 gq->dirty = rswitch_next_queue_index(gq, false, num); 973 } 974 975 static irqreturn_t rswitch_gwca_ts_irq(int irq, void *dev_id) 976 { 977 struct rswitch_private *priv = dev_id; 978 979 if (ioread32(priv->addr + GWTSDIS) & GWCA_TS_IRQ_BIT) { 980 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDIS); 981 rswitch_ts(priv); 982 983 return IRQ_HANDLED; 984 } 985 986 return IRQ_NONE; 987 } 988 989 static int rswitch_gwca_ts_request_irqs(struct rswitch_private *priv) 990 { 991 int irq; 992 993 irq = platform_get_irq_byname(priv->pdev, GWCA_TS_IRQ_RESOURCE_NAME); 994 if (irq < 0) 995 return irq; 996 997 return devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_ts_irq, 998 0, GWCA_TS_IRQ_NAME, priv); 999 } 1000 1001 /* Ethernet TSN Agent block (ETHA) and Ethernet MAC IP block (RMAC) */ 1002 static int rswitch_etha_change_mode(struct rswitch_etha *etha, 1003 enum rswitch_etha_mode mode) 1004 { 1005 int ret; 1006 1007 if (!rswitch_agent_clock_is_enabled(etha->coma_addr, etha->index)) 1008 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 1); 1009 1010 iowrite32(mode, etha->addr + EAMC); 1011 1012 ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode); 1013 1014 if (mode == EAMC_OPC_DISABLE) 1015 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 0); 1016 1017 return ret; 1018 } 1019 1020 static void rswitch_etha_read_mac_address(struct rswitch_etha *etha) 1021 { 1022 u32 mrmac0 = ioread32(etha->addr + MRMAC0); 1023 u32 mrmac1 = ioread32(etha->addr + MRMAC1); 1024 u8 *mac = ða->mac_addr[0]; 1025 1026 mac[0] = (mrmac0 >> 8) & 0xFF; 1027 mac[1] = (mrmac0 >> 0) & 0xFF; 1028 mac[2] = (mrmac1 >> 24) & 0xFF; 1029 mac[3] = (mrmac1 >> 16) & 0xFF; 1030 mac[4] = (mrmac1 >> 8) & 0xFF; 1031 mac[5] = (mrmac1 >> 0) & 0xFF; 1032 } 1033 1034 static void rswitch_etha_write_mac_address(struct rswitch_etha *etha, const u8 *mac) 1035 { 1036 iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0); 1037 iowrite32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], 1038 etha->addr + MRMAC1); 1039 } 1040 1041 static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha) 1042 { 1043 iowrite32(MLVC_PLV, etha->addr + MLVC); 1044 1045 return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0); 1046 } 1047 1048 static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac) 1049 { 1050 u32 pis, lsc; 1051 1052 rswitch_etha_write_mac_address(etha, mac); 1053 1054 switch (etha->phy_interface) { 1055 case PHY_INTERFACE_MODE_SGMII: 1056 pis = MPIC_PIS_GMII; 1057 break; 1058 case PHY_INTERFACE_MODE_USXGMII: 1059 case PHY_INTERFACE_MODE_5GBASER: 1060 pis = MPIC_PIS_XGMII; 1061 break; 1062 default: 1063 pis = FIELD_GET(MPIC_PIS, ioread32(etha->addr + MPIC)); 1064 break; 1065 } 1066 1067 switch (etha->speed) { 1068 case 100: 1069 lsc = MPIC_LSC_100M; 1070 break; 1071 case 1000: 1072 lsc = MPIC_LSC_1G; 1073 break; 1074 case 2500: 1075 lsc = MPIC_LSC_2_5G; 1076 break; 1077 default: 1078 lsc = FIELD_GET(MPIC_LSC, ioread32(etha->addr + MPIC)); 1079 break; 1080 } 1081 1082 rswitch_modify(etha->addr, MPIC, MPIC_PIS | MPIC_LSC, 1083 FIELD_PREP(MPIC_PIS, pis) | FIELD_PREP(MPIC_LSC, lsc)); 1084 } 1085 1086 static void rswitch_etha_enable_mii(struct rswitch_etha *etha) 1087 { 1088 rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, 1089 MPIC_PSMCS(etha->psmcs) | MPIC_PSMHT(0x06)); 1090 rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45); 1091 } 1092 1093 static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac) 1094 { 1095 int err; 1096 1097 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 1098 if (err < 0) 1099 return err; 1100 err = rswitch_etha_change_mode(etha, EAMC_OPC_CONFIG); 1101 if (err < 0) 1102 return err; 1103 1104 iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC); 1105 rswitch_rmac_setting(etha, mac); 1106 rswitch_etha_enable_mii(etha); 1107 1108 err = rswitch_etha_wait_link_verification(etha); 1109 if (err < 0) 1110 return err; 1111 1112 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 1113 if (err < 0) 1114 return err; 1115 1116 return rswitch_etha_change_mode(etha, EAMC_OPC_OPERATION); 1117 } 1118 1119 static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read, 1120 int phyad, int devad, int regad, int data) 1121 { 1122 int pop = read ? MDIO_READ_C45 : MDIO_WRITE_C45; 1123 u32 val; 1124 int ret; 1125 1126 if (devad == 0xffffffff) 1127 return -ENODEV; 1128 1129 writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); 1130 1131 val = MPSM_PSME | MPSM_MFF_C45; 1132 iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 1133 1134 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1135 if (ret) 1136 return ret; 1137 1138 rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1139 1140 if (read) { 1141 writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 1142 1143 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1144 if (ret) 1145 return ret; 1146 1147 ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; 1148 1149 rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1150 } else { 1151 iowrite32((data << 16) | (pop << 13) | (devad << 8) | (phyad << 3) | val, 1152 etha->addr + MPSM); 1153 1154 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS); 1155 } 1156 1157 return ret; 1158 } 1159 1160 static int rswitch_etha_mii_read_c45(struct mii_bus *bus, int addr, int devad, 1161 int regad) 1162 { 1163 struct rswitch_etha *etha = bus->priv; 1164 1165 return rswitch_etha_set_access(etha, true, addr, devad, regad, 0); 1166 } 1167 1168 static int rswitch_etha_mii_write_c45(struct mii_bus *bus, int addr, int devad, 1169 int regad, u16 val) 1170 { 1171 struct rswitch_etha *etha = bus->priv; 1172 1173 return rswitch_etha_set_access(etha, false, addr, devad, regad, val); 1174 } 1175 1176 /* Call of_node_put(port) after done */ 1177 static struct device_node *rswitch_get_port_node(struct rswitch_device *rdev) 1178 { 1179 struct device_node *ports, *port; 1180 int err = 0; 1181 u32 index; 1182 1183 ports = of_get_child_by_name(rdev->ndev->dev.parent->of_node, 1184 "ethernet-ports"); 1185 if (!ports) 1186 return NULL; 1187 1188 for_each_child_of_node(ports, port) { 1189 err = of_property_read_u32(port, "reg", &index); 1190 if (err < 0) { 1191 port = NULL; 1192 goto out; 1193 } 1194 if (index == rdev->etha->index) { 1195 if (!of_device_is_available(port)) 1196 port = NULL; 1197 break; 1198 } 1199 } 1200 1201 out: 1202 of_node_put(ports); 1203 1204 return port; 1205 } 1206 1207 static int rswitch_etha_get_params(struct rswitch_device *rdev) 1208 { 1209 u32 max_speed; 1210 int err; 1211 1212 if (!rdev->np_port) 1213 return 0; /* ignored */ 1214 1215 err = of_get_phy_mode(rdev->np_port, &rdev->etha->phy_interface); 1216 if (err) 1217 return err; 1218 1219 err = of_property_read_u32(rdev->np_port, "max-speed", &max_speed); 1220 if (!err) { 1221 rdev->etha->speed = max_speed; 1222 return 0; 1223 } 1224 1225 /* if no "max-speed" property, let's use default speed */ 1226 switch (rdev->etha->phy_interface) { 1227 case PHY_INTERFACE_MODE_MII: 1228 rdev->etha->speed = SPEED_100; 1229 break; 1230 case PHY_INTERFACE_MODE_SGMII: 1231 rdev->etha->speed = SPEED_1000; 1232 break; 1233 case PHY_INTERFACE_MODE_USXGMII: 1234 rdev->etha->speed = SPEED_2500; 1235 break; 1236 default: 1237 return -EINVAL; 1238 } 1239 1240 return 0; 1241 } 1242 1243 static int rswitch_mii_register(struct rswitch_device *rdev) 1244 { 1245 struct device_node *mdio_np; 1246 struct mii_bus *mii_bus; 1247 int err; 1248 1249 mii_bus = mdiobus_alloc(); 1250 if (!mii_bus) 1251 return -ENOMEM; 1252 1253 mii_bus->name = "rswitch_mii"; 1254 sprintf(mii_bus->id, "etha%d", rdev->etha->index); 1255 mii_bus->priv = rdev->etha; 1256 mii_bus->read_c45 = rswitch_etha_mii_read_c45; 1257 mii_bus->write_c45 = rswitch_etha_mii_write_c45; 1258 mii_bus->parent = &rdev->priv->pdev->dev; 1259 1260 mdio_np = of_get_child_by_name(rdev->np_port, "mdio"); 1261 err = of_mdiobus_register(mii_bus, mdio_np); 1262 if (err < 0) { 1263 mdiobus_free(mii_bus); 1264 goto out; 1265 } 1266 1267 rdev->etha->mii = mii_bus; 1268 1269 out: 1270 of_node_put(mdio_np); 1271 1272 return err; 1273 } 1274 1275 static void rswitch_mii_unregister(struct rswitch_device *rdev) 1276 { 1277 if (rdev->etha->mii) { 1278 mdiobus_unregister(rdev->etha->mii); 1279 mdiobus_free(rdev->etha->mii); 1280 rdev->etha->mii = NULL; 1281 } 1282 } 1283 1284 static void rswitch_adjust_link(struct net_device *ndev) 1285 { 1286 struct rswitch_device *rdev = netdev_priv(ndev); 1287 struct phy_device *phydev = ndev->phydev; 1288 1289 if (phydev->link != rdev->etha->link) { 1290 phy_print_status(phydev); 1291 if (phydev->link) 1292 phy_power_on(rdev->serdes); 1293 else if (rdev->serdes->power_count) 1294 phy_power_off(rdev->serdes); 1295 1296 rdev->etha->link = phydev->link; 1297 1298 if (!rdev->priv->etha_no_runtime_change && 1299 phydev->speed != rdev->etha->speed) { 1300 rdev->etha->speed = phydev->speed; 1301 1302 rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr); 1303 phy_set_speed(rdev->serdes, rdev->etha->speed); 1304 } 1305 } 1306 } 1307 1308 static void rswitch_phy_remove_link_mode(struct rswitch_device *rdev, 1309 struct phy_device *phydev) 1310 { 1311 if (!rdev->priv->etha_no_runtime_change) 1312 return; 1313 1314 switch (rdev->etha->speed) { 1315 case SPEED_2500: 1316 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1317 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1318 break; 1319 case SPEED_1000: 1320 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1321 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1322 break; 1323 case SPEED_100: 1324 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1325 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1326 break; 1327 default: 1328 break; 1329 } 1330 1331 phy_set_max_speed(phydev, rdev->etha->speed); 1332 } 1333 1334 static int rswitch_phy_device_init(struct rswitch_device *rdev) 1335 { 1336 struct phy_device *phydev; 1337 struct device_node *phy; 1338 int err = -ENOENT; 1339 1340 if (!rdev->np_port) 1341 return -ENODEV; 1342 1343 phy = of_parse_phandle(rdev->np_port, "phy-handle", 0); 1344 if (!phy) 1345 return -ENODEV; 1346 1347 /* Set phydev->host_interfaces before calling of_phy_connect() to 1348 * configure the PHY with the information of host_interfaces. 1349 */ 1350 phydev = of_phy_find_device(phy); 1351 if (!phydev) 1352 goto out; 1353 __set_bit(rdev->etha->phy_interface, phydev->host_interfaces); 1354 1355 phydev = of_phy_connect(rdev->ndev, phy, rswitch_adjust_link, 0, 1356 rdev->etha->phy_interface); 1357 if (!phydev) 1358 goto out; 1359 1360 phy_set_max_speed(phydev, SPEED_2500); 1361 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1362 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1363 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1364 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1365 rswitch_phy_remove_link_mode(rdev, phydev); 1366 1367 phy_attached_info(phydev); 1368 1369 err = 0; 1370 out: 1371 of_node_put(phy); 1372 1373 return err; 1374 } 1375 1376 static void rswitch_phy_device_deinit(struct rswitch_device *rdev) 1377 { 1378 if (rdev->ndev->phydev) 1379 phy_disconnect(rdev->ndev->phydev); 1380 } 1381 1382 static int rswitch_serdes_set_params(struct rswitch_device *rdev) 1383 { 1384 int err; 1385 1386 err = phy_set_mode_ext(rdev->serdes, PHY_MODE_ETHERNET, 1387 rdev->etha->phy_interface); 1388 if (err < 0) 1389 return err; 1390 1391 return phy_set_speed(rdev->serdes, rdev->etha->speed); 1392 } 1393 1394 static int rswitch_ether_port_init_one(struct rswitch_device *rdev) 1395 { 1396 int err; 1397 1398 if (!rdev->etha->operated) { 1399 err = rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr); 1400 if (err < 0) 1401 return err; 1402 if (rdev->priv->etha_no_runtime_change) 1403 rdev->etha->operated = true; 1404 } 1405 1406 err = rswitch_mii_register(rdev); 1407 if (err < 0) 1408 return err; 1409 1410 err = rswitch_phy_device_init(rdev); 1411 if (err < 0) 1412 goto err_phy_device_init; 1413 1414 rdev->serdes = devm_of_phy_get(&rdev->priv->pdev->dev, rdev->np_port, NULL); 1415 if (IS_ERR(rdev->serdes)) { 1416 err = PTR_ERR(rdev->serdes); 1417 goto err_serdes_phy_get; 1418 } 1419 1420 err = rswitch_serdes_set_params(rdev); 1421 if (err < 0) 1422 goto err_serdes_set_params; 1423 1424 return 0; 1425 1426 err_serdes_set_params: 1427 err_serdes_phy_get: 1428 rswitch_phy_device_deinit(rdev); 1429 1430 err_phy_device_init: 1431 rswitch_mii_unregister(rdev); 1432 1433 return err; 1434 } 1435 1436 static void rswitch_ether_port_deinit_one(struct rswitch_device *rdev) 1437 { 1438 rswitch_phy_device_deinit(rdev); 1439 rswitch_mii_unregister(rdev); 1440 } 1441 1442 static int rswitch_ether_port_init_all(struct rswitch_private *priv) 1443 { 1444 int i, err; 1445 1446 rswitch_for_each_enabled_port(priv, i) { 1447 err = rswitch_ether_port_init_one(priv->rdev[i]); 1448 if (err) 1449 goto err_init_one; 1450 } 1451 1452 rswitch_for_each_enabled_port(priv, i) { 1453 err = phy_init(priv->rdev[i]->serdes); 1454 if (err) 1455 goto err_serdes; 1456 } 1457 1458 return 0; 1459 1460 err_serdes: 1461 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1462 phy_exit(priv->rdev[i]->serdes); 1463 i = RSWITCH_NUM_PORTS; 1464 1465 err_init_one: 1466 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1467 rswitch_ether_port_deinit_one(priv->rdev[i]); 1468 1469 return err; 1470 } 1471 1472 static void rswitch_ether_port_deinit_all(struct rswitch_private *priv) 1473 { 1474 unsigned int i; 1475 1476 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1477 phy_exit(priv->rdev[i]->serdes); 1478 rswitch_ether_port_deinit_one(priv->rdev[i]); 1479 } 1480 } 1481 1482 static int rswitch_open(struct net_device *ndev) 1483 { 1484 struct rswitch_device *rdev = netdev_priv(ndev); 1485 unsigned long flags; 1486 1487 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) 1488 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDIE); 1489 1490 napi_enable(&rdev->napi); 1491 1492 spin_lock_irqsave(&rdev->priv->lock, flags); 1493 bitmap_set(rdev->priv->opened_ports, rdev->port, 1); 1494 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, true); 1495 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, true); 1496 spin_unlock_irqrestore(&rdev->priv->lock, flags); 1497 1498 phy_start(ndev->phydev); 1499 1500 netif_start_queue(ndev); 1501 1502 return 0; 1503 }; 1504 1505 static int rswitch_stop(struct net_device *ndev) 1506 { 1507 struct rswitch_device *rdev = netdev_priv(ndev); 1508 struct rswitch_gwca_ts_info *ts_info, *ts_info2; 1509 unsigned long flags; 1510 1511 netif_tx_stop_all_queues(ndev); 1512 1513 phy_stop(ndev->phydev); 1514 1515 spin_lock_irqsave(&rdev->priv->lock, flags); 1516 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 1517 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 1518 bitmap_clear(rdev->priv->opened_ports, rdev->port, 1); 1519 spin_unlock_irqrestore(&rdev->priv->lock, flags); 1520 1521 napi_disable(&rdev->napi); 1522 1523 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) 1524 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDID); 1525 1526 list_for_each_entry_safe(ts_info, ts_info2, &rdev->priv->gwca.ts_info_list, list) { 1527 if (ts_info->port != rdev->port) 1528 continue; 1529 dev_kfree_skb_irq(ts_info->skb); 1530 list_del(&ts_info->list); 1531 kfree(ts_info); 1532 } 1533 1534 return 0; 1535 }; 1536 1537 static bool rswitch_ext_desc_set_info1(struct rswitch_device *rdev, 1538 struct sk_buff *skb, 1539 struct rswitch_ext_desc *desc) 1540 { 1541 desc->info1 = cpu_to_le64(INFO1_DV(BIT(rdev->etha->index)) | 1542 INFO1_IPV(GWCA_IPV_NUM) | INFO1_FMT); 1543 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 1544 struct rswitch_gwca_ts_info *ts_info; 1545 1546 ts_info = kzalloc(sizeof(*ts_info), GFP_ATOMIC); 1547 if (!ts_info) 1548 return false; 1549 1550 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1551 rdev->ts_tag++; 1552 desc->info1 |= cpu_to_le64(INFO1_TSUN(rdev->ts_tag) | INFO1_TXC); 1553 1554 ts_info->skb = skb_get(skb); 1555 ts_info->port = rdev->port; 1556 ts_info->tag = rdev->ts_tag; 1557 list_add_tail(&ts_info->list, &rdev->priv->gwca.ts_info_list); 1558 1559 skb_tx_timestamp(skb); 1560 } 1561 1562 return true; 1563 } 1564 1565 static bool rswitch_ext_desc_set(struct rswitch_device *rdev, 1566 struct sk_buff *skb, 1567 struct rswitch_ext_desc *desc, 1568 dma_addr_t dma_addr, u16 len, u8 die_dt) 1569 { 1570 rswitch_desc_set_dptr(&desc->desc, dma_addr); 1571 desc->desc.info_ds = cpu_to_le16(len); 1572 if (!rswitch_ext_desc_set_info1(rdev, skb, desc)) 1573 return false; 1574 1575 dma_wmb(); 1576 1577 desc->desc.die_dt = die_dt; 1578 1579 return true; 1580 } 1581 1582 static u8 rswitch_ext_desc_get_die_dt(unsigned int nr_desc, unsigned int index) 1583 { 1584 if (nr_desc == 1) 1585 return DT_FSINGLE | DIE; 1586 if (index == 0) 1587 return DT_FSTART; 1588 if (nr_desc - 1 == index) 1589 return DT_FEND | DIE; 1590 return DT_FMID; 1591 } 1592 1593 static u16 rswitch_ext_desc_get_len(u8 die_dt, unsigned int orig_len) 1594 { 1595 switch (die_dt & DT_MASK) { 1596 case DT_FSINGLE: 1597 case DT_FEND: 1598 return (orig_len % RSWITCH_DESC_BUF_SIZE) ?: RSWITCH_DESC_BUF_SIZE; 1599 case DT_FSTART: 1600 case DT_FMID: 1601 return RSWITCH_DESC_BUF_SIZE; 1602 default: 1603 return 0; 1604 } 1605 } 1606 1607 static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1608 { 1609 struct rswitch_device *rdev = netdev_priv(ndev); 1610 struct rswitch_gwca_queue *gq = rdev->tx_queue; 1611 dma_addr_t dma_addr, dma_addr_orig; 1612 netdev_tx_t ret = NETDEV_TX_OK; 1613 struct rswitch_ext_desc *desc; 1614 unsigned int i, nr_desc; 1615 u8 die_dt; 1616 u16 len; 1617 1618 nr_desc = (skb->len - 1) / RSWITCH_DESC_BUF_SIZE + 1; 1619 if (rswitch_get_num_cur_queues(gq) >= gq->ring_size - nr_desc) { 1620 netif_stop_subqueue(ndev, 0); 1621 return NETDEV_TX_BUSY; 1622 } 1623 1624 if (skb_put_padto(skb, ETH_ZLEN)) 1625 return ret; 1626 1627 dma_addr_orig = dma_map_single(ndev->dev.parent, skb->data, skb->len, DMA_TO_DEVICE); 1628 if (dma_mapping_error(ndev->dev.parent, dma_addr_orig)) 1629 goto err_kfree; 1630 1631 gq->skbs[gq->cur] = skb; 1632 gq->unmap_addrs[gq->cur] = dma_addr_orig; 1633 1634 dma_wmb(); 1635 1636 /* DT_FSTART should be set at last. So, this is reverse order. */ 1637 for (i = nr_desc; i-- > 0; ) { 1638 desc = &gq->tx_ring[rswitch_next_queue_index(gq, true, i)]; 1639 die_dt = rswitch_ext_desc_get_die_dt(nr_desc, i); 1640 dma_addr = dma_addr_orig + i * RSWITCH_DESC_BUF_SIZE; 1641 len = rswitch_ext_desc_get_len(die_dt, skb->len); 1642 if (!rswitch_ext_desc_set(rdev, skb, desc, dma_addr, len, die_dt)) 1643 goto err_unmap; 1644 } 1645 1646 gq->cur = rswitch_next_queue_index(gq, true, nr_desc); 1647 rswitch_modify(rdev->addr, GWTRC(gq->index), 0, BIT(gq->index % 32)); 1648 1649 return ret; 1650 1651 err_unmap: 1652 gq->skbs[(gq->cur + nr_desc - 1) % gq->ring_size] = NULL; 1653 dma_unmap_single(ndev->dev.parent, dma_addr_orig, skb->len, DMA_TO_DEVICE); 1654 1655 err_kfree: 1656 dev_kfree_skb_any(skb); 1657 1658 return ret; 1659 } 1660 1661 static struct net_device_stats *rswitch_get_stats(struct net_device *ndev) 1662 { 1663 return &ndev->stats; 1664 } 1665 1666 static int rswitch_hwstamp_get(struct net_device *ndev, struct ifreq *req) 1667 { 1668 struct rswitch_device *rdev = netdev_priv(ndev); 1669 struct rcar_gen4_ptp_private *ptp_priv; 1670 struct hwtstamp_config config; 1671 1672 ptp_priv = rdev->priv->ptp_priv; 1673 1674 config.flags = 0; 1675 config.tx_type = ptp_priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1676 HWTSTAMP_TX_OFF; 1677 switch (ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE) { 1678 case RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT: 1679 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1680 break; 1681 case RCAR_GEN4_RXTSTAMP_TYPE_ALL: 1682 config.rx_filter = HWTSTAMP_FILTER_ALL; 1683 break; 1684 default: 1685 config.rx_filter = HWTSTAMP_FILTER_NONE; 1686 break; 1687 } 1688 1689 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1690 } 1691 1692 static int rswitch_hwstamp_set(struct net_device *ndev, struct ifreq *req) 1693 { 1694 struct rswitch_device *rdev = netdev_priv(ndev); 1695 u32 tstamp_rx_ctrl = RCAR_GEN4_RXTSTAMP_ENABLED; 1696 struct hwtstamp_config config; 1697 u32 tstamp_tx_ctrl; 1698 1699 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1700 return -EFAULT; 1701 1702 if (config.flags) 1703 return -EINVAL; 1704 1705 switch (config.tx_type) { 1706 case HWTSTAMP_TX_OFF: 1707 tstamp_tx_ctrl = 0; 1708 break; 1709 case HWTSTAMP_TX_ON: 1710 tstamp_tx_ctrl = RCAR_GEN4_TXTSTAMP_ENABLED; 1711 break; 1712 default: 1713 return -ERANGE; 1714 } 1715 1716 switch (config.rx_filter) { 1717 case HWTSTAMP_FILTER_NONE: 1718 tstamp_rx_ctrl = 0; 1719 break; 1720 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1721 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 1722 break; 1723 default: 1724 config.rx_filter = HWTSTAMP_FILTER_ALL; 1725 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_ALL; 1726 break; 1727 } 1728 1729 rdev->priv->ptp_priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1730 rdev->priv->ptp_priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1731 1732 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1733 } 1734 1735 static int rswitch_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1736 { 1737 if (!netif_running(ndev)) 1738 return -EINVAL; 1739 1740 switch (cmd) { 1741 case SIOCGHWTSTAMP: 1742 return rswitch_hwstamp_get(ndev, req); 1743 case SIOCSHWTSTAMP: 1744 return rswitch_hwstamp_set(ndev, req); 1745 default: 1746 return phy_mii_ioctl(ndev->phydev, req, cmd); 1747 } 1748 } 1749 1750 static const struct net_device_ops rswitch_netdev_ops = { 1751 .ndo_open = rswitch_open, 1752 .ndo_stop = rswitch_stop, 1753 .ndo_start_xmit = rswitch_start_xmit, 1754 .ndo_get_stats = rswitch_get_stats, 1755 .ndo_eth_ioctl = rswitch_eth_ioctl, 1756 .ndo_validate_addr = eth_validate_addr, 1757 .ndo_set_mac_address = eth_mac_addr, 1758 }; 1759 1760 static int rswitch_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) 1761 { 1762 struct rswitch_device *rdev = netdev_priv(ndev); 1763 1764 info->phc_index = ptp_clock_index(rdev->priv->ptp_priv->clock); 1765 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1766 SOF_TIMESTAMPING_RX_SOFTWARE | 1767 SOF_TIMESTAMPING_SOFTWARE | 1768 SOF_TIMESTAMPING_TX_HARDWARE | 1769 SOF_TIMESTAMPING_RX_HARDWARE | 1770 SOF_TIMESTAMPING_RAW_HARDWARE; 1771 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); 1772 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1773 1774 return 0; 1775 } 1776 1777 static const struct ethtool_ops rswitch_ethtool_ops = { 1778 .get_ts_info = rswitch_get_ts_info, 1779 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1780 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1781 }; 1782 1783 static const struct of_device_id renesas_eth_sw_of_table[] = { 1784 { .compatible = "renesas,r8a779f0-ether-switch", }, 1785 { } 1786 }; 1787 MODULE_DEVICE_TABLE(of, renesas_eth_sw_of_table); 1788 1789 static void rswitch_etha_init(struct rswitch_private *priv, unsigned int index) 1790 { 1791 struct rswitch_etha *etha = &priv->etha[index]; 1792 1793 memset(etha, 0, sizeof(*etha)); 1794 etha->index = index; 1795 etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE; 1796 etha->coma_addr = priv->addr; 1797 1798 /* MPIC.PSMCS = (clk [MHz] / (MDC frequency [MHz] * 2) - 1. 1799 * Calculating PSMCS value as MDC frequency = 2.5MHz. So, multiply 1800 * both the numerator and the denominator by 10. 1801 */ 1802 etha->psmcs = clk_get_rate(priv->clk) / 100000 / (25 * 2) - 1; 1803 } 1804 1805 static int rswitch_device_alloc(struct rswitch_private *priv, unsigned int index) 1806 { 1807 struct platform_device *pdev = priv->pdev; 1808 struct rswitch_device *rdev; 1809 struct net_device *ndev; 1810 int err; 1811 1812 if (index >= RSWITCH_NUM_PORTS) 1813 return -EINVAL; 1814 1815 ndev = alloc_etherdev_mqs(sizeof(struct rswitch_device), 1, 1); 1816 if (!ndev) 1817 return -ENOMEM; 1818 1819 SET_NETDEV_DEV(ndev, &pdev->dev); 1820 ether_setup(ndev); 1821 1822 rdev = netdev_priv(ndev); 1823 rdev->ndev = ndev; 1824 rdev->priv = priv; 1825 priv->rdev[index] = rdev; 1826 rdev->port = index; 1827 rdev->etha = &priv->etha[index]; 1828 rdev->addr = priv->addr; 1829 1830 ndev->base_addr = (unsigned long)rdev->addr; 1831 snprintf(ndev->name, IFNAMSIZ, "tsn%d", index); 1832 ndev->netdev_ops = &rswitch_netdev_ops; 1833 ndev->ethtool_ops = &rswitch_ethtool_ops; 1834 1835 netif_napi_add(ndev, &rdev->napi, rswitch_poll); 1836 1837 rdev->np_port = rswitch_get_port_node(rdev); 1838 rdev->disabled = !rdev->np_port; 1839 err = of_get_ethdev_address(rdev->np_port, ndev); 1840 if (err) { 1841 if (is_valid_ether_addr(rdev->etha->mac_addr)) 1842 eth_hw_addr_set(ndev, rdev->etha->mac_addr); 1843 else 1844 eth_hw_addr_random(ndev); 1845 } 1846 1847 err = rswitch_etha_get_params(rdev); 1848 if (err < 0) 1849 goto out_get_params; 1850 1851 if (rdev->priv->gwca.speed < rdev->etha->speed) 1852 rdev->priv->gwca.speed = rdev->etha->speed; 1853 1854 err = rswitch_rxdmac_alloc(ndev); 1855 if (err < 0) 1856 goto out_rxdmac; 1857 1858 err = rswitch_txdmac_alloc(ndev); 1859 if (err < 0) 1860 goto out_txdmac; 1861 1862 return 0; 1863 1864 out_txdmac: 1865 rswitch_rxdmac_free(ndev); 1866 1867 out_rxdmac: 1868 out_get_params: 1869 of_node_put(rdev->np_port); 1870 netif_napi_del(&rdev->napi); 1871 free_netdev(ndev); 1872 1873 return err; 1874 } 1875 1876 static void rswitch_device_free(struct rswitch_private *priv, unsigned int index) 1877 { 1878 struct rswitch_device *rdev = priv->rdev[index]; 1879 struct net_device *ndev = rdev->ndev; 1880 1881 rswitch_txdmac_free(ndev); 1882 rswitch_rxdmac_free(ndev); 1883 of_node_put(rdev->np_port); 1884 netif_napi_del(&rdev->napi); 1885 free_netdev(ndev); 1886 } 1887 1888 static int rswitch_init(struct rswitch_private *priv) 1889 { 1890 int i, err; 1891 1892 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1893 rswitch_etha_init(priv, i); 1894 1895 rswitch_clock_enable(priv); 1896 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1897 rswitch_etha_read_mac_address(&priv->etha[i]); 1898 1899 rswitch_reset(priv); 1900 1901 rswitch_clock_enable(priv); 1902 rswitch_top_init(priv); 1903 err = rswitch_bpool_config(priv); 1904 if (err < 0) 1905 return err; 1906 1907 rswitch_coma_init(priv); 1908 1909 err = rswitch_gwca_linkfix_alloc(priv); 1910 if (err < 0) 1911 return -ENOMEM; 1912 1913 err = rswitch_gwca_ts_queue_alloc(priv); 1914 if (err < 0) 1915 goto err_ts_queue_alloc; 1916 1917 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1918 err = rswitch_device_alloc(priv, i); 1919 if (err < 0) { 1920 for (i--; i >= 0; i--) 1921 rswitch_device_free(priv, i); 1922 goto err_device_alloc; 1923 } 1924 } 1925 1926 rswitch_fwd_init(priv); 1927 1928 err = rcar_gen4_ptp_register(priv->ptp_priv, RCAR_GEN4_PTP_REG_LAYOUT_S4, 1929 RCAR_GEN4_PTP_CLOCK_S4); 1930 if (err < 0) 1931 goto err_ptp_register; 1932 1933 err = rswitch_gwca_request_irqs(priv); 1934 if (err < 0) 1935 goto err_gwca_request_irq; 1936 1937 err = rswitch_gwca_ts_request_irqs(priv); 1938 if (err < 0) 1939 goto err_gwca_ts_request_irq; 1940 1941 err = rswitch_gwca_hw_init(priv); 1942 if (err < 0) 1943 goto err_gwca_hw_init; 1944 1945 err = rswitch_ether_port_init_all(priv); 1946 if (err) 1947 goto err_ether_port_init_all; 1948 1949 rswitch_for_each_enabled_port(priv, i) { 1950 err = register_netdev(priv->rdev[i]->ndev); 1951 if (err) { 1952 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1953 unregister_netdev(priv->rdev[i]->ndev); 1954 goto err_register_netdev; 1955 } 1956 } 1957 1958 rswitch_for_each_enabled_port(priv, i) 1959 netdev_info(priv->rdev[i]->ndev, "MAC address %pM\n", 1960 priv->rdev[i]->ndev->dev_addr); 1961 1962 return 0; 1963 1964 err_register_netdev: 1965 rswitch_ether_port_deinit_all(priv); 1966 1967 err_ether_port_init_all: 1968 rswitch_gwca_hw_deinit(priv); 1969 1970 err_gwca_hw_init: 1971 err_gwca_ts_request_irq: 1972 err_gwca_request_irq: 1973 rcar_gen4_ptp_unregister(priv->ptp_priv); 1974 1975 err_ptp_register: 1976 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1977 rswitch_device_free(priv, i); 1978 1979 err_device_alloc: 1980 rswitch_gwca_ts_queue_free(priv); 1981 1982 err_ts_queue_alloc: 1983 rswitch_gwca_linkfix_free(priv); 1984 1985 return err; 1986 } 1987 1988 static const struct soc_device_attribute rswitch_soc_no_speed_change[] = { 1989 { .soc_id = "r8a779f0", .revision = "ES1.0" }, 1990 { /* Sentinel */ } 1991 }; 1992 1993 static int renesas_eth_sw_probe(struct platform_device *pdev) 1994 { 1995 const struct soc_device_attribute *attr; 1996 struct rswitch_private *priv; 1997 struct resource *res; 1998 int ret; 1999 2000 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "secure_base"); 2001 if (!res) { 2002 dev_err(&pdev->dev, "invalid resource\n"); 2003 return -EINVAL; 2004 } 2005 2006 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2007 if (!priv) 2008 return -ENOMEM; 2009 spin_lock_init(&priv->lock); 2010 2011 priv->clk = devm_clk_get(&pdev->dev, NULL); 2012 if (IS_ERR(priv->clk)) 2013 return PTR_ERR(priv->clk); 2014 2015 attr = soc_device_match(rswitch_soc_no_speed_change); 2016 if (attr) 2017 priv->etha_no_runtime_change = true; 2018 2019 priv->ptp_priv = rcar_gen4_ptp_alloc(pdev); 2020 if (!priv->ptp_priv) 2021 return -ENOMEM; 2022 2023 platform_set_drvdata(pdev, priv); 2024 priv->pdev = pdev; 2025 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2026 if (IS_ERR(priv->addr)) 2027 return PTR_ERR(priv->addr); 2028 2029 priv->ptp_priv->addr = priv->addr + RCAR_GEN4_GPTP_OFFSET_S4; 2030 2031 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 2032 if (ret < 0) { 2033 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2034 if (ret < 0) 2035 return ret; 2036 } 2037 2038 priv->gwca.index = AGENT_INDEX_GWCA; 2039 priv->gwca.num_queues = min(RSWITCH_NUM_PORTS * NUM_QUEUES_PER_NDEV, 2040 RSWITCH_MAX_NUM_QUEUES); 2041 priv->gwca.queues = devm_kcalloc(&pdev->dev, priv->gwca.num_queues, 2042 sizeof(*priv->gwca.queues), GFP_KERNEL); 2043 if (!priv->gwca.queues) 2044 return -ENOMEM; 2045 2046 pm_runtime_enable(&pdev->dev); 2047 pm_runtime_get_sync(&pdev->dev); 2048 2049 ret = rswitch_init(priv); 2050 if (ret < 0) { 2051 pm_runtime_put(&pdev->dev); 2052 pm_runtime_disable(&pdev->dev); 2053 return ret; 2054 } 2055 2056 device_set_wakeup_capable(&pdev->dev, 1); 2057 2058 return ret; 2059 } 2060 2061 static void rswitch_deinit(struct rswitch_private *priv) 2062 { 2063 int i; 2064 2065 rswitch_gwca_hw_deinit(priv); 2066 rcar_gen4_ptp_unregister(priv->ptp_priv); 2067 2068 rswitch_for_each_enabled_port(priv, i) { 2069 struct rswitch_device *rdev = priv->rdev[i]; 2070 2071 unregister_netdev(rdev->ndev); 2072 rswitch_ether_port_deinit_one(rdev); 2073 phy_exit(priv->rdev[i]->serdes); 2074 } 2075 2076 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 2077 rswitch_device_free(priv, i); 2078 2079 rswitch_gwca_ts_queue_free(priv); 2080 rswitch_gwca_linkfix_free(priv); 2081 2082 rswitch_clock_disable(priv); 2083 } 2084 2085 static int renesas_eth_sw_remove(struct platform_device *pdev) 2086 { 2087 struct rswitch_private *priv = platform_get_drvdata(pdev); 2088 2089 rswitch_deinit(priv); 2090 2091 pm_runtime_put(&pdev->dev); 2092 pm_runtime_disable(&pdev->dev); 2093 2094 platform_set_drvdata(pdev, NULL); 2095 2096 return 0; 2097 } 2098 2099 static struct platform_driver renesas_eth_sw_driver_platform = { 2100 .probe = renesas_eth_sw_probe, 2101 .remove = renesas_eth_sw_remove, 2102 .driver = { 2103 .name = "renesas_eth_sw", 2104 .of_match_table = renesas_eth_sw_of_table, 2105 } 2106 }; 2107 module_platform_driver(renesas_eth_sw_driver_platform); 2108 MODULE_AUTHOR("Yoshihiro Shimoda"); 2109 MODULE_DESCRIPTION("Renesas Ethernet Switch device driver"); 2110 MODULE_LICENSE("GPL"); 2111