1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet Switch device driver 3 * 4 * Copyright (C) 2022 Renesas Electronics Corporation 5 */ 6 7 #include <linux/dma-mapping.h> 8 #include <linux/err.h> 9 #include <linux/etherdevice.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 #include <linux/phy/phy.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/rtnetlink.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 25 #include "rswitch.h" 26 27 static int rswitch_reg_wait(void __iomem *addr, u32 offs, u32 mask, u32 expected) 28 { 29 u32 val; 30 31 return readl_poll_timeout_atomic(addr + offs, val, (val & mask) == expected, 32 1, RSWITCH_TIMEOUT_US); 33 } 34 35 static void rswitch_modify(void __iomem *addr, enum rswitch_reg reg, u32 clear, u32 set) 36 { 37 iowrite32((ioread32(addr + reg) & ~clear) | set, addr + reg); 38 } 39 40 /* Common Agent block (COMA) */ 41 static void rswitch_reset(struct rswitch_private *priv) 42 { 43 iowrite32(RRC_RR, priv->addr + RRC); 44 iowrite32(RRC_RR_CLR, priv->addr + RRC); 45 } 46 47 static void rswitch_clock_enable(struct rswitch_private *priv) 48 { 49 iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC); 50 } 51 52 static void rswitch_clock_disable(struct rswitch_private *priv) 53 { 54 iowrite32(RCDC_RCD, priv->addr + RCDC); 55 } 56 57 static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr, int port) 58 { 59 u32 val = ioread32(coma_addr + RCEC); 60 61 if (val & RCEC_RCE) 62 return (val & BIT(port)) ? true : false; 63 else 64 return false; 65 } 66 67 static void rswitch_agent_clock_ctrl(void __iomem *coma_addr, int port, int enable) 68 { 69 u32 val; 70 71 if (enable) { 72 val = ioread32(coma_addr + RCEC); 73 iowrite32(val | RCEC_RCE | BIT(port), coma_addr + RCEC); 74 } else { 75 val = ioread32(coma_addr + RCDC); 76 iowrite32(val | BIT(port), coma_addr + RCDC); 77 } 78 } 79 80 static int rswitch_bpool_config(struct rswitch_private *priv) 81 { 82 u32 val; 83 84 val = ioread32(priv->addr + CABPIRM); 85 if (val & CABPIRM_BPR) 86 return 0; 87 88 iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM); 89 90 return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR); 91 } 92 93 /* R-Switch-2 block (TOP) */ 94 static void rswitch_top_init(struct rswitch_private *priv) 95 { 96 int i; 97 98 for (i = 0; i < RSWITCH_MAX_NUM_QUEUES; i++) 99 iowrite32((i / 16) << (GWCA_INDEX * 8), priv->addr + TPEMIMC7(i)); 100 } 101 102 /* Forwarding engine block (MFWD) */ 103 static void rswitch_fwd_init(struct rswitch_private *priv) 104 { 105 int i; 106 107 /* For ETHA */ 108 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 109 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(i)); 110 iowrite32(0, priv->addr + FWPBFC(i)); 111 } 112 113 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 114 iowrite32(priv->rdev[i]->rx_queue->index, 115 priv->addr + FWPBFCSDC(GWCA_INDEX, i)); 116 iowrite32(BIT(priv->gwca.index), priv->addr + FWPBFC(i)); 117 } 118 119 /* For GWCA */ 120 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(priv->gwca.index)); 121 iowrite32(FWPC1_DDE, priv->addr + FWPC1(priv->gwca.index)); 122 iowrite32(0, priv->addr + FWPBFC(priv->gwca.index)); 123 iowrite32(GENMASK(RSWITCH_NUM_PORTS - 1, 0), priv->addr + FWPBFC(priv->gwca.index)); 124 } 125 126 /* Gateway CPU agent block (GWCA) */ 127 static int rswitch_gwca_change_mode(struct rswitch_private *priv, 128 enum rswitch_gwca_mode mode) 129 { 130 int ret; 131 132 if (!rswitch_agent_clock_is_enabled(priv->addr, priv->gwca.index)) 133 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 1); 134 135 iowrite32(mode, priv->addr + GWMC); 136 137 ret = rswitch_reg_wait(priv->addr, GWMS, GWMS_OPS_MASK, mode); 138 139 if (mode == GWMC_OPC_DISABLE) 140 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 0); 141 142 return ret; 143 } 144 145 static int rswitch_gwca_mcast_table_reset(struct rswitch_private *priv) 146 { 147 iowrite32(GWMTIRM_MTIOG, priv->addr + GWMTIRM); 148 149 return rswitch_reg_wait(priv->addr, GWMTIRM, GWMTIRM_MTR, GWMTIRM_MTR); 150 } 151 152 static int rswitch_gwca_axi_ram_reset(struct rswitch_private *priv) 153 { 154 iowrite32(GWARIRM_ARIOG, priv->addr + GWARIRM); 155 156 return rswitch_reg_wait(priv->addr, GWARIRM, GWARIRM_ARR, GWARIRM_ARR); 157 } 158 159 static void rswitch_gwca_set_rate_limit(struct rswitch_private *priv, int rate) 160 { 161 u32 gwgrlulc, gwgrlc; 162 163 switch (rate) { 164 case 1000: 165 gwgrlulc = 0x0000005f; 166 gwgrlc = 0x00010260; 167 break; 168 default: 169 dev_err(&priv->pdev->dev, "%s: This rate is not supported (%d)\n", __func__, rate); 170 return; 171 } 172 173 iowrite32(gwgrlulc, priv->addr + GWGRLULC); 174 iowrite32(gwgrlc, priv->addr + GWGRLC); 175 } 176 177 static bool rswitch_is_any_data_irq(struct rswitch_private *priv, u32 *dis, bool tx) 178 { 179 u32 *mask = tx ? priv->gwca.tx_irq_bits : priv->gwca.rx_irq_bits; 180 int i; 181 182 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 183 if (dis[i] & mask[i]) 184 return true; 185 } 186 187 return false; 188 } 189 190 static void rswitch_get_data_irq_status(struct rswitch_private *priv, u32 *dis) 191 { 192 int i; 193 194 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 195 dis[i] = ioread32(priv->addr + GWDIS(i)); 196 dis[i] &= ioread32(priv->addr + GWDIE(i)); 197 } 198 } 199 200 static void rswitch_enadis_data_irq(struct rswitch_private *priv, int index, bool enable) 201 { 202 u32 offs = enable ? GWDIE(index / 32) : GWDID(index / 32); 203 204 iowrite32(BIT(index % 32), priv->addr + offs); 205 } 206 207 static void rswitch_ack_data_irq(struct rswitch_private *priv, int index) 208 { 209 u32 offs = GWDIS(index / 32); 210 211 iowrite32(BIT(index % 32), priv->addr + offs); 212 } 213 214 static int rswitch_next_queue_index(struct rswitch_gwca_queue *gq, bool cur, int num) 215 { 216 int index = cur ? gq->cur : gq->dirty; 217 218 if (index + num >= gq->ring_size) 219 index = (index + num) % gq->ring_size; 220 else 221 index += num; 222 223 return index; 224 } 225 226 static int rswitch_get_num_cur_queues(struct rswitch_gwca_queue *gq) 227 { 228 if (gq->cur >= gq->dirty) 229 return gq->cur - gq->dirty; 230 else 231 return gq->ring_size - gq->dirty + gq->cur; 232 } 233 234 static bool rswitch_is_queue_rxed(struct rswitch_gwca_queue *gq) 235 { 236 struct rswitch_ext_ts_desc *desc = &gq->rx_ring[gq->dirty]; 237 238 if ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) 239 return true; 240 241 return false; 242 } 243 244 static int rswitch_gwca_queue_alloc_skb(struct rswitch_gwca_queue *gq, 245 int start_index, int num) 246 { 247 int i, index; 248 249 for (i = 0; i < num; i++) { 250 index = (i + start_index) % gq->ring_size; 251 if (gq->skbs[index]) 252 continue; 253 gq->skbs[index] = netdev_alloc_skb_ip_align(gq->ndev, 254 PKT_BUF_SZ + RSWITCH_ALIGN - 1); 255 if (!gq->skbs[index]) 256 goto err; 257 } 258 259 return 0; 260 261 err: 262 for (i--; i >= 0; i--) { 263 index = (i + start_index) % gq->ring_size; 264 dev_kfree_skb(gq->skbs[index]); 265 gq->skbs[index] = NULL; 266 } 267 268 return -ENOMEM; 269 } 270 271 static void rswitch_gwca_queue_free(struct net_device *ndev, 272 struct rswitch_gwca_queue *gq) 273 { 274 int i; 275 276 if (!gq->dir_tx) { 277 dma_free_coherent(ndev->dev.parent, 278 sizeof(struct rswitch_ext_ts_desc) * 279 (gq->ring_size + 1), gq->rx_ring, gq->ring_dma); 280 gq->rx_ring = NULL; 281 282 for (i = 0; i < gq->ring_size; i++) 283 dev_kfree_skb(gq->skbs[i]); 284 } else { 285 dma_free_coherent(ndev->dev.parent, 286 sizeof(struct rswitch_ext_desc) * 287 (gq->ring_size + 1), gq->tx_ring, gq->ring_dma); 288 gq->tx_ring = NULL; 289 } 290 291 kfree(gq->skbs); 292 gq->skbs = NULL; 293 } 294 295 static void rswitch_gwca_ts_queue_free(struct rswitch_private *priv) 296 { 297 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 298 299 dma_free_coherent(&priv->pdev->dev, 300 sizeof(struct rswitch_ts_desc) * (gq->ring_size + 1), 301 gq->ts_ring, gq->ring_dma); 302 gq->ts_ring = NULL; 303 } 304 305 static int rswitch_gwca_queue_alloc(struct net_device *ndev, 306 struct rswitch_private *priv, 307 struct rswitch_gwca_queue *gq, 308 bool dir_tx, int ring_size) 309 { 310 int i, bit; 311 312 gq->dir_tx = dir_tx; 313 gq->ring_size = ring_size; 314 gq->ndev = ndev; 315 316 gq->skbs = kcalloc(gq->ring_size, sizeof(*gq->skbs), GFP_KERNEL); 317 if (!gq->skbs) 318 return -ENOMEM; 319 320 if (!dir_tx) { 321 rswitch_gwca_queue_alloc_skb(gq, 0, gq->ring_size); 322 323 gq->rx_ring = dma_alloc_coherent(ndev->dev.parent, 324 sizeof(struct rswitch_ext_ts_desc) * 325 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 326 } else { 327 gq->tx_ring = dma_alloc_coherent(ndev->dev.parent, 328 sizeof(struct rswitch_ext_desc) * 329 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 330 } 331 332 if (!gq->rx_ring && !gq->tx_ring) 333 goto out; 334 335 i = gq->index / 32; 336 bit = BIT(gq->index % 32); 337 if (dir_tx) 338 priv->gwca.tx_irq_bits[i] |= bit; 339 else 340 priv->gwca.rx_irq_bits[i] |= bit; 341 342 return 0; 343 344 out: 345 rswitch_gwca_queue_free(ndev, gq); 346 347 return -ENOMEM; 348 } 349 350 static int rswitch_gwca_ts_queue_alloc(struct rswitch_private *priv) 351 { 352 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 353 354 gq->ring_size = TS_RING_SIZE; 355 gq->ts_ring = dma_alloc_coherent(&priv->pdev->dev, 356 sizeof(struct rswitch_ts_desc) * 357 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 358 return !gq->ts_ring ? -ENOMEM : 0; 359 } 360 361 static void rswitch_desc_set_dptr(struct rswitch_desc *desc, dma_addr_t addr) 362 { 363 desc->dptrl = cpu_to_le32(lower_32_bits(addr)); 364 desc->dptrh = upper_32_bits(addr) & 0xff; 365 } 366 367 static dma_addr_t rswitch_desc_get_dptr(const struct rswitch_desc *desc) 368 { 369 return __le32_to_cpu(desc->dptrl) | (u64)(desc->dptrh) << 32; 370 } 371 372 static int rswitch_gwca_queue_format(struct net_device *ndev, 373 struct rswitch_private *priv, 374 struct rswitch_gwca_queue *gq) 375 { 376 int ring_size = sizeof(struct rswitch_ext_desc) * gq->ring_size; 377 struct rswitch_ext_desc *desc; 378 struct rswitch_desc *linkfix; 379 dma_addr_t dma_addr; 380 int i; 381 382 memset(gq->tx_ring, 0, ring_size); 383 for (i = 0, desc = gq->tx_ring; i < gq->ring_size; i++, desc++) { 384 if (!gq->dir_tx) { 385 dma_addr = dma_map_single(ndev->dev.parent, 386 gq->skbs[i]->data, PKT_BUF_SZ, 387 DMA_FROM_DEVICE); 388 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 389 goto err; 390 391 desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ); 392 rswitch_desc_set_dptr(&desc->desc, dma_addr); 393 desc->desc.die_dt = DT_FEMPTY | DIE; 394 } else { 395 desc->desc.die_dt = DT_EEMPTY | DIE; 396 } 397 } 398 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 399 desc->desc.die_dt = DT_LINKFIX; 400 401 linkfix = &priv->gwca.linkfix_table[gq->index]; 402 linkfix->die_dt = DT_LINKFIX; 403 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 404 405 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DQT : 0) | GWDCC_EDE, 406 priv->addr + GWDCC_OFFS(gq->index)); 407 408 return 0; 409 410 err: 411 if (!gq->dir_tx) { 412 for (i--, desc = gq->tx_ring; i >= 0; i--, desc++) { 413 dma_addr = rswitch_desc_get_dptr(&desc->desc); 414 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, 415 DMA_FROM_DEVICE); 416 } 417 } 418 419 return -ENOMEM; 420 } 421 422 static void rswitch_gwca_ts_queue_fill(struct rswitch_private *priv, 423 int start_index, int num) 424 { 425 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 426 struct rswitch_ts_desc *desc; 427 int i, index; 428 429 for (i = 0; i < num; i++) { 430 index = (i + start_index) % gq->ring_size; 431 desc = &gq->ts_ring[index]; 432 desc->desc.die_dt = DT_FEMPTY_ND | DIE; 433 } 434 } 435 436 static int rswitch_gwca_queue_ext_ts_fill(struct net_device *ndev, 437 struct rswitch_gwca_queue *gq, 438 int start_index, int num) 439 { 440 struct rswitch_device *rdev = netdev_priv(ndev); 441 struct rswitch_ext_ts_desc *desc; 442 dma_addr_t dma_addr; 443 int i, index; 444 445 for (i = 0; i < num; i++) { 446 index = (i + start_index) % gq->ring_size; 447 desc = &gq->rx_ring[index]; 448 if (!gq->dir_tx) { 449 dma_addr = dma_map_single(ndev->dev.parent, 450 gq->skbs[index]->data, PKT_BUF_SZ, 451 DMA_FROM_DEVICE); 452 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 453 goto err; 454 455 desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ); 456 rswitch_desc_set_dptr(&desc->desc, dma_addr); 457 dma_wmb(); 458 desc->desc.die_dt = DT_FEMPTY | DIE; 459 desc->info1 = cpu_to_le64(INFO1_SPN(rdev->etha->index)); 460 } else { 461 desc->desc.die_dt = DT_EEMPTY | DIE; 462 } 463 } 464 465 return 0; 466 467 err: 468 if (!gq->dir_tx) { 469 for (i--; i >= 0; i--) { 470 index = (i + start_index) % gq->ring_size; 471 desc = &gq->rx_ring[index]; 472 dma_addr = rswitch_desc_get_dptr(&desc->desc); 473 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, 474 DMA_FROM_DEVICE); 475 } 476 } 477 478 return -ENOMEM; 479 } 480 481 static int rswitch_gwca_queue_ext_ts_format(struct net_device *ndev, 482 struct rswitch_private *priv, 483 struct rswitch_gwca_queue *gq) 484 { 485 int ring_size = sizeof(struct rswitch_ext_ts_desc) * gq->ring_size; 486 struct rswitch_ext_ts_desc *desc; 487 struct rswitch_desc *linkfix; 488 int err; 489 490 memset(gq->rx_ring, 0, ring_size); 491 err = rswitch_gwca_queue_ext_ts_fill(ndev, gq, 0, gq->ring_size); 492 if (err < 0) 493 return err; 494 495 desc = &gq->rx_ring[gq->ring_size]; /* Last */ 496 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 497 desc->desc.die_dt = DT_LINKFIX; 498 499 linkfix = &priv->gwca.linkfix_table[gq->index]; 500 linkfix->die_dt = DT_LINKFIX; 501 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 502 503 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DQT : 0) | GWDCC_ETS | GWDCC_EDE, 504 priv->addr + GWDCC_OFFS(gq->index)); 505 506 return 0; 507 } 508 509 static int rswitch_gwca_linkfix_alloc(struct rswitch_private *priv) 510 { 511 int i, num_queues = priv->gwca.num_queues; 512 struct rswitch_gwca *gwca = &priv->gwca; 513 struct device *dev = &priv->pdev->dev; 514 515 gwca->linkfix_table_size = sizeof(struct rswitch_desc) * num_queues; 516 gwca->linkfix_table = dma_alloc_coherent(dev, gwca->linkfix_table_size, 517 &gwca->linkfix_table_dma, GFP_KERNEL); 518 if (!gwca->linkfix_table) 519 return -ENOMEM; 520 for (i = 0; i < num_queues; i++) 521 gwca->linkfix_table[i].die_dt = DT_EOS; 522 523 return 0; 524 } 525 526 static void rswitch_gwca_linkfix_free(struct rswitch_private *priv) 527 { 528 struct rswitch_gwca *gwca = &priv->gwca; 529 530 if (gwca->linkfix_table) 531 dma_free_coherent(&priv->pdev->dev, gwca->linkfix_table_size, 532 gwca->linkfix_table, gwca->linkfix_table_dma); 533 gwca->linkfix_table = NULL; 534 } 535 536 static struct rswitch_gwca_queue *rswitch_gwca_get(struct rswitch_private *priv) 537 { 538 struct rswitch_gwca_queue *gq; 539 int index; 540 541 index = find_first_zero_bit(priv->gwca.used, priv->gwca.num_queues); 542 if (index >= priv->gwca.num_queues) 543 return NULL; 544 set_bit(index, priv->gwca.used); 545 gq = &priv->gwca.queues[index]; 546 memset(gq, 0, sizeof(*gq)); 547 gq->index = index; 548 549 return gq; 550 } 551 552 static void rswitch_gwca_put(struct rswitch_private *priv, 553 struct rswitch_gwca_queue *gq) 554 { 555 clear_bit(gq->index, priv->gwca.used); 556 } 557 558 static int rswitch_txdmac_alloc(struct net_device *ndev) 559 { 560 struct rswitch_device *rdev = netdev_priv(ndev); 561 struct rswitch_private *priv = rdev->priv; 562 int err; 563 564 rdev->tx_queue = rswitch_gwca_get(priv); 565 if (!rdev->tx_queue) 566 return -EBUSY; 567 568 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->tx_queue, true, TX_RING_SIZE); 569 if (err < 0) { 570 rswitch_gwca_put(priv, rdev->tx_queue); 571 return err; 572 } 573 574 return 0; 575 } 576 577 static void rswitch_txdmac_free(struct net_device *ndev) 578 { 579 struct rswitch_device *rdev = netdev_priv(ndev); 580 581 rswitch_gwca_queue_free(ndev, rdev->tx_queue); 582 rswitch_gwca_put(rdev->priv, rdev->tx_queue); 583 } 584 585 static int rswitch_txdmac_init(struct rswitch_private *priv, int index) 586 { 587 struct rswitch_device *rdev = priv->rdev[index]; 588 589 return rswitch_gwca_queue_format(rdev->ndev, priv, rdev->tx_queue); 590 } 591 592 static int rswitch_rxdmac_alloc(struct net_device *ndev) 593 { 594 struct rswitch_device *rdev = netdev_priv(ndev); 595 struct rswitch_private *priv = rdev->priv; 596 int err; 597 598 rdev->rx_queue = rswitch_gwca_get(priv); 599 if (!rdev->rx_queue) 600 return -EBUSY; 601 602 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->rx_queue, false, RX_RING_SIZE); 603 if (err < 0) { 604 rswitch_gwca_put(priv, rdev->rx_queue); 605 return err; 606 } 607 608 return 0; 609 } 610 611 static void rswitch_rxdmac_free(struct net_device *ndev) 612 { 613 struct rswitch_device *rdev = netdev_priv(ndev); 614 615 rswitch_gwca_queue_free(ndev, rdev->rx_queue); 616 rswitch_gwca_put(rdev->priv, rdev->rx_queue); 617 } 618 619 static int rswitch_rxdmac_init(struct rswitch_private *priv, int index) 620 { 621 struct rswitch_device *rdev = priv->rdev[index]; 622 struct net_device *ndev = rdev->ndev; 623 624 return rswitch_gwca_queue_ext_ts_format(ndev, priv, rdev->rx_queue); 625 } 626 627 static int rswitch_gwca_hw_init(struct rswitch_private *priv) 628 { 629 int i, err; 630 631 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 632 if (err < 0) 633 return err; 634 err = rswitch_gwca_change_mode(priv, GWMC_OPC_CONFIG); 635 if (err < 0) 636 return err; 637 638 err = rswitch_gwca_mcast_table_reset(priv); 639 if (err < 0) 640 return err; 641 err = rswitch_gwca_axi_ram_reset(priv); 642 if (err < 0) 643 return err; 644 645 iowrite32(GWVCC_VEM_SC_TAG, priv->addr + GWVCC); 646 iowrite32(0, priv->addr + GWTTFC); 647 iowrite32(lower_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC1); 648 iowrite32(upper_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC0); 649 iowrite32(lower_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC10); 650 iowrite32(upper_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC00); 651 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDCC0); 652 rswitch_gwca_set_rate_limit(priv, priv->gwca.speed); 653 654 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 655 err = rswitch_rxdmac_init(priv, i); 656 if (err < 0) 657 return err; 658 err = rswitch_txdmac_init(priv, i); 659 if (err < 0) 660 return err; 661 } 662 663 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 664 if (err < 0) 665 return err; 666 return rswitch_gwca_change_mode(priv, GWMC_OPC_OPERATION); 667 } 668 669 static int rswitch_gwca_hw_deinit(struct rswitch_private *priv) 670 { 671 int err; 672 673 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 674 if (err < 0) 675 return err; 676 err = rswitch_gwca_change_mode(priv, GWMC_OPC_RESET); 677 if (err < 0) 678 return err; 679 680 return rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 681 } 682 683 static int rswitch_gwca_halt(struct rswitch_private *priv) 684 { 685 int err; 686 687 priv->gwca_halt = true; 688 err = rswitch_gwca_hw_deinit(priv); 689 dev_err(&priv->pdev->dev, "halted (%d)\n", err); 690 691 return err; 692 } 693 694 static bool rswitch_rx(struct net_device *ndev, int *quota) 695 { 696 struct rswitch_device *rdev = netdev_priv(ndev); 697 struct rswitch_gwca_queue *gq = rdev->rx_queue; 698 struct rswitch_ext_ts_desc *desc; 699 int limit, boguscnt, num, ret; 700 struct sk_buff *skb; 701 dma_addr_t dma_addr; 702 u16 pkt_len; 703 u32 get_ts; 704 705 if (*quota <= 0) 706 return true; 707 708 boguscnt = min_t(int, gq->ring_size, *quota); 709 limit = boguscnt; 710 711 desc = &gq->rx_ring[gq->cur]; 712 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) { 713 dma_rmb(); 714 pkt_len = le16_to_cpu(desc->desc.info_ds) & RX_DS; 715 skb = gq->skbs[gq->cur]; 716 gq->skbs[gq->cur] = NULL; 717 dma_addr = rswitch_desc_get_dptr(&desc->desc); 718 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, DMA_FROM_DEVICE); 719 get_ts = rdev->priv->ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 720 if (get_ts) { 721 struct skb_shared_hwtstamps *shhwtstamps; 722 struct timespec64 ts; 723 724 shhwtstamps = skb_hwtstamps(skb); 725 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 726 ts.tv_sec = __le32_to_cpu(desc->ts_sec); 727 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); 728 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 729 } 730 skb_put(skb, pkt_len); 731 skb->protocol = eth_type_trans(skb, ndev); 732 netif_receive_skb(skb); 733 rdev->ndev->stats.rx_packets++; 734 rdev->ndev->stats.rx_bytes += pkt_len; 735 736 gq->cur = rswitch_next_queue_index(gq, true, 1); 737 desc = &gq->rx_ring[gq->cur]; 738 739 if (--boguscnt <= 0) 740 break; 741 } 742 743 num = rswitch_get_num_cur_queues(gq); 744 ret = rswitch_gwca_queue_alloc_skb(gq, gq->dirty, num); 745 if (ret < 0) 746 goto err; 747 ret = rswitch_gwca_queue_ext_ts_fill(ndev, gq, gq->dirty, num); 748 if (ret < 0) 749 goto err; 750 gq->dirty = rswitch_next_queue_index(gq, false, num); 751 752 *quota -= limit - boguscnt; 753 754 return boguscnt <= 0; 755 756 err: 757 rswitch_gwca_halt(rdev->priv); 758 759 return 0; 760 } 761 762 static int rswitch_tx_free(struct net_device *ndev, bool free_txed_only) 763 { 764 struct rswitch_device *rdev = netdev_priv(ndev); 765 struct rswitch_gwca_queue *gq = rdev->tx_queue; 766 struct rswitch_ext_desc *desc; 767 dma_addr_t dma_addr; 768 struct sk_buff *skb; 769 int free_num = 0; 770 int size; 771 772 for (; rswitch_get_num_cur_queues(gq) > 0; 773 gq->dirty = rswitch_next_queue_index(gq, false, 1)) { 774 desc = &gq->tx_ring[gq->dirty]; 775 if (free_txed_only && (desc->desc.die_dt & DT_MASK) != DT_FEMPTY) 776 break; 777 778 dma_rmb(); 779 size = le16_to_cpu(desc->desc.info_ds) & TX_DS; 780 skb = gq->skbs[gq->dirty]; 781 if (skb) { 782 dma_addr = rswitch_desc_get_dptr(&desc->desc); 783 dma_unmap_single(ndev->dev.parent, dma_addr, 784 size, DMA_TO_DEVICE); 785 dev_kfree_skb_any(gq->skbs[gq->dirty]); 786 gq->skbs[gq->dirty] = NULL; 787 free_num++; 788 } 789 desc->desc.die_dt = DT_EEMPTY; 790 rdev->ndev->stats.tx_packets++; 791 rdev->ndev->stats.tx_bytes += size; 792 } 793 794 return free_num; 795 } 796 797 static int rswitch_poll(struct napi_struct *napi, int budget) 798 { 799 struct net_device *ndev = napi->dev; 800 struct rswitch_private *priv; 801 struct rswitch_device *rdev; 802 int quota = budget; 803 804 rdev = netdev_priv(ndev); 805 priv = rdev->priv; 806 807 retry: 808 rswitch_tx_free(ndev, true); 809 810 if (rswitch_rx(ndev, "a)) 811 goto out; 812 else if (rdev->priv->gwca_halt) 813 goto err; 814 else if (rswitch_is_queue_rxed(rdev->rx_queue)) 815 goto retry; 816 817 netif_wake_subqueue(ndev, 0); 818 819 napi_complete(napi); 820 821 rswitch_enadis_data_irq(priv, rdev->tx_queue->index, true); 822 rswitch_enadis_data_irq(priv, rdev->rx_queue->index, true); 823 824 out: 825 return budget - quota; 826 827 err: 828 napi_complete(napi); 829 830 return 0; 831 } 832 833 static void rswitch_queue_interrupt(struct net_device *ndev) 834 { 835 struct rswitch_device *rdev = netdev_priv(ndev); 836 837 if (napi_schedule_prep(&rdev->napi)) { 838 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 839 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 840 __napi_schedule(&rdev->napi); 841 } 842 } 843 844 static irqreturn_t rswitch_data_irq(struct rswitch_private *priv, u32 *dis) 845 { 846 struct rswitch_gwca_queue *gq; 847 int i, index, bit; 848 849 for (i = 0; i < priv->gwca.num_queues; i++) { 850 gq = &priv->gwca.queues[i]; 851 index = gq->index / 32; 852 bit = BIT(gq->index % 32); 853 if (!(dis[index] & bit)) 854 continue; 855 856 rswitch_ack_data_irq(priv, gq->index); 857 rswitch_queue_interrupt(gq->ndev); 858 } 859 860 return IRQ_HANDLED; 861 } 862 863 static irqreturn_t rswitch_gwca_irq(int irq, void *dev_id) 864 { 865 struct rswitch_private *priv = dev_id; 866 u32 dis[RSWITCH_NUM_IRQ_REGS]; 867 irqreturn_t ret = IRQ_NONE; 868 869 rswitch_get_data_irq_status(priv, dis); 870 871 if (rswitch_is_any_data_irq(priv, dis, true) || 872 rswitch_is_any_data_irq(priv, dis, false)) 873 ret = rswitch_data_irq(priv, dis); 874 875 return ret; 876 } 877 878 static int rswitch_gwca_request_irqs(struct rswitch_private *priv) 879 { 880 char *resource_name, *irq_name; 881 int i, ret, irq; 882 883 for (i = 0; i < GWCA_NUM_IRQS; i++) { 884 resource_name = kasprintf(GFP_KERNEL, GWCA_IRQ_RESOURCE_NAME, i); 885 if (!resource_name) 886 return -ENOMEM; 887 888 irq = platform_get_irq_byname(priv->pdev, resource_name); 889 kfree(resource_name); 890 if (irq < 0) 891 return irq; 892 893 irq_name = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL, 894 GWCA_IRQ_NAME, i); 895 if (!irq_name) 896 return -ENOMEM; 897 898 ret = devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_irq, 899 0, irq_name, priv); 900 if (ret < 0) 901 return ret; 902 } 903 904 return 0; 905 } 906 907 static void rswitch_ts(struct rswitch_private *priv) 908 { 909 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 910 struct rswitch_gwca_ts_info *ts_info, *ts_info2; 911 struct skb_shared_hwtstamps shhwtstamps; 912 struct rswitch_ts_desc *desc; 913 struct timespec64 ts; 914 u32 tag, port; 915 int num; 916 917 desc = &gq->ts_ring[gq->cur]; 918 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY_ND) { 919 dma_rmb(); 920 921 port = TS_DESC_DPN(__le32_to_cpu(desc->desc.dptrl)); 922 tag = TS_DESC_TSUN(__le32_to_cpu(desc->desc.dptrl)); 923 924 list_for_each_entry_safe(ts_info, ts_info2, &priv->gwca.ts_info_list, list) { 925 if (!(ts_info->port == port && ts_info->tag == tag)) 926 continue; 927 928 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 929 ts.tv_sec = __le32_to_cpu(desc->ts_sec); 930 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); 931 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 932 skb_tstamp_tx(ts_info->skb, &shhwtstamps); 933 dev_consume_skb_irq(ts_info->skb); 934 list_del(&ts_info->list); 935 kfree(ts_info); 936 break; 937 } 938 939 gq->cur = rswitch_next_queue_index(gq, true, 1); 940 desc = &gq->ts_ring[gq->cur]; 941 } 942 943 num = rswitch_get_num_cur_queues(gq); 944 rswitch_gwca_ts_queue_fill(priv, gq->dirty, num); 945 gq->dirty = rswitch_next_queue_index(gq, false, num); 946 } 947 948 static irqreturn_t rswitch_gwca_ts_irq(int irq, void *dev_id) 949 { 950 struct rswitch_private *priv = dev_id; 951 952 if (ioread32(priv->addr + GWTSDIS) & GWCA_TS_IRQ_BIT) { 953 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDIS); 954 rswitch_ts(priv); 955 956 return IRQ_HANDLED; 957 } 958 959 return IRQ_NONE; 960 } 961 962 static int rswitch_gwca_ts_request_irqs(struct rswitch_private *priv) 963 { 964 int irq; 965 966 irq = platform_get_irq_byname(priv->pdev, GWCA_TS_IRQ_RESOURCE_NAME); 967 if (irq < 0) 968 return irq; 969 970 return devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_ts_irq, 971 0, GWCA_TS_IRQ_NAME, priv); 972 } 973 974 /* Ethernet TSN Agent block (ETHA) and Ethernet MAC IP block (RMAC) */ 975 static int rswitch_etha_change_mode(struct rswitch_etha *etha, 976 enum rswitch_etha_mode mode) 977 { 978 int ret; 979 980 if (!rswitch_agent_clock_is_enabled(etha->coma_addr, etha->index)) 981 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 1); 982 983 iowrite32(mode, etha->addr + EAMC); 984 985 ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode); 986 987 if (mode == EAMC_OPC_DISABLE) 988 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 0); 989 990 return ret; 991 } 992 993 static void rswitch_etha_read_mac_address(struct rswitch_etha *etha) 994 { 995 u32 mrmac0 = ioread32(etha->addr + MRMAC0); 996 u32 mrmac1 = ioread32(etha->addr + MRMAC1); 997 u8 *mac = ða->mac_addr[0]; 998 999 mac[0] = (mrmac0 >> 8) & 0xFF; 1000 mac[1] = (mrmac0 >> 0) & 0xFF; 1001 mac[2] = (mrmac1 >> 24) & 0xFF; 1002 mac[3] = (mrmac1 >> 16) & 0xFF; 1003 mac[4] = (mrmac1 >> 8) & 0xFF; 1004 mac[5] = (mrmac1 >> 0) & 0xFF; 1005 } 1006 1007 static void rswitch_etha_write_mac_address(struct rswitch_etha *etha, const u8 *mac) 1008 { 1009 iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0); 1010 iowrite32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], 1011 etha->addr + MRMAC1); 1012 } 1013 1014 static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha) 1015 { 1016 iowrite32(MLVC_PLV, etha->addr + MLVC); 1017 1018 return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0); 1019 } 1020 1021 static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac) 1022 { 1023 u32 val; 1024 1025 rswitch_etha_write_mac_address(etha, mac); 1026 1027 switch (etha->speed) { 1028 case 100: 1029 val = MPIC_LSC_100M; 1030 break; 1031 case 1000: 1032 val = MPIC_LSC_1G; 1033 break; 1034 case 2500: 1035 val = MPIC_LSC_2_5G; 1036 break; 1037 default: 1038 return; 1039 } 1040 1041 iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC); 1042 } 1043 1044 static void rswitch_etha_enable_mii(struct rswitch_etha *etha) 1045 { 1046 rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, 1047 MPIC_PSMCS(0x05) | MPIC_PSMHT(0x06)); 1048 rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45); 1049 } 1050 1051 static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac) 1052 { 1053 int err; 1054 1055 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 1056 if (err < 0) 1057 return err; 1058 err = rswitch_etha_change_mode(etha, EAMC_OPC_CONFIG); 1059 if (err < 0) 1060 return err; 1061 1062 iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC); 1063 rswitch_rmac_setting(etha, mac); 1064 rswitch_etha_enable_mii(etha); 1065 1066 err = rswitch_etha_wait_link_verification(etha); 1067 if (err < 0) 1068 return err; 1069 1070 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 1071 if (err < 0) 1072 return err; 1073 1074 return rswitch_etha_change_mode(etha, EAMC_OPC_OPERATION); 1075 } 1076 1077 static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read, 1078 int phyad, int devad, int regad, int data) 1079 { 1080 int pop = read ? MDIO_READ_C45 : MDIO_WRITE_C45; 1081 u32 val; 1082 int ret; 1083 1084 if (devad == 0xffffffff) 1085 return -ENODEV; 1086 1087 writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); 1088 1089 val = MPSM_PSME | MPSM_MFF_C45; 1090 iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 1091 1092 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1093 if (ret) 1094 return ret; 1095 1096 rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1097 1098 if (read) { 1099 writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 1100 1101 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1102 if (ret) 1103 return ret; 1104 1105 ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; 1106 1107 rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1108 } else { 1109 iowrite32((data << 16) | (pop << 13) | (devad << 8) | (phyad << 3) | val, 1110 etha->addr + MPSM); 1111 1112 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS); 1113 } 1114 1115 return ret; 1116 } 1117 1118 static int rswitch_etha_mii_read_c45(struct mii_bus *bus, int addr, int devad, 1119 int regad) 1120 { 1121 struct rswitch_etha *etha = bus->priv; 1122 1123 return rswitch_etha_set_access(etha, true, addr, devad, regad, 0); 1124 } 1125 1126 static int rswitch_etha_mii_write_c45(struct mii_bus *bus, int addr, int devad, 1127 int regad, u16 val) 1128 { 1129 struct rswitch_etha *etha = bus->priv; 1130 1131 return rswitch_etha_set_access(etha, false, addr, devad, regad, val); 1132 } 1133 1134 /* Call of_node_put(port) after done */ 1135 static struct device_node *rswitch_get_port_node(struct rswitch_device *rdev) 1136 { 1137 struct device_node *ports, *port; 1138 int err = 0; 1139 u32 index; 1140 1141 ports = of_get_child_by_name(rdev->ndev->dev.parent->of_node, 1142 "ethernet-ports"); 1143 if (!ports) 1144 return NULL; 1145 1146 for_each_child_of_node(ports, port) { 1147 err = of_property_read_u32(port, "reg", &index); 1148 if (err < 0) { 1149 port = NULL; 1150 goto out; 1151 } 1152 if (index == rdev->etha->index) { 1153 if (!of_device_is_available(port)) 1154 port = NULL; 1155 break; 1156 } 1157 } 1158 1159 out: 1160 of_node_put(ports); 1161 1162 return port; 1163 } 1164 1165 static int rswitch_etha_get_params(struct rswitch_device *rdev) 1166 { 1167 u32 max_speed; 1168 int err; 1169 1170 if (!rdev->np_port) 1171 return 0; /* ignored */ 1172 1173 err = of_get_phy_mode(rdev->np_port, &rdev->etha->phy_interface); 1174 if (err) 1175 return err; 1176 1177 err = of_property_read_u32(rdev->np_port, "max-speed", &max_speed); 1178 if (!err) { 1179 rdev->etha->speed = max_speed; 1180 return 0; 1181 } 1182 1183 /* if no "max-speed" property, let's use default speed */ 1184 switch (rdev->etha->phy_interface) { 1185 case PHY_INTERFACE_MODE_MII: 1186 rdev->etha->speed = SPEED_100; 1187 break; 1188 case PHY_INTERFACE_MODE_SGMII: 1189 rdev->etha->speed = SPEED_1000; 1190 break; 1191 case PHY_INTERFACE_MODE_USXGMII: 1192 rdev->etha->speed = SPEED_2500; 1193 break; 1194 default: 1195 return -EINVAL; 1196 } 1197 1198 return 0; 1199 } 1200 1201 static int rswitch_mii_register(struct rswitch_device *rdev) 1202 { 1203 struct device_node *mdio_np; 1204 struct mii_bus *mii_bus; 1205 int err; 1206 1207 mii_bus = mdiobus_alloc(); 1208 if (!mii_bus) 1209 return -ENOMEM; 1210 1211 mii_bus->name = "rswitch_mii"; 1212 sprintf(mii_bus->id, "etha%d", rdev->etha->index); 1213 mii_bus->priv = rdev->etha; 1214 mii_bus->read_c45 = rswitch_etha_mii_read_c45; 1215 mii_bus->write_c45 = rswitch_etha_mii_write_c45; 1216 mii_bus->parent = &rdev->priv->pdev->dev; 1217 1218 mdio_np = of_get_child_by_name(rdev->np_port, "mdio"); 1219 err = of_mdiobus_register(mii_bus, mdio_np); 1220 if (err < 0) { 1221 mdiobus_free(mii_bus); 1222 goto out; 1223 } 1224 1225 rdev->etha->mii = mii_bus; 1226 1227 out: 1228 of_node_put(mdio_np); 1229 1230 return err; 1231 } 1232 1233 static void rswitch_mii_unregister(struct rswitch_device *rdev) 1234 { 1235 if (rdev->etha->mii) { 1236 mdiobus_unregister(rdev->etha->mii); 1237 mdiobus_free(rdev->etha->mii); 1238 rdev->etha->mii = NULL; 1239 } 1240 } 1241 1242 static void rswitch_adjust_link(struct net_device *ndev) 1243 { 1244 struct rswitch_device *rdev = netdev_priv(ndev); 1245 struct phy_device *phydev = ndev->phydev; 1246 1247 /* Current hardware has a restriction not to change speed at runtime */ 1248 if (phydev->link != rdev->etha->link) { 1249 phy_print_status(phydev); 1250 if (phydev->link) 1251 phy_power_on(rdev->serdes); 1252 else 1253 phy_power_off(rdev->serdes); 1254 1255 rdev->etha->link = phydev->link; 1256 } 1257 } 1258 1259 static void rswitch_phy_remove_link_mode(struct rswitch_device *rdev, 1260 struct phy_device *phydev) 1261 { 1262 /* Current hardware has a restriction not to change speed at runtime */ 1263 switch (rdev->etha->speed) { 1264 case SPEED_2500: 1265 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1266 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1267 break; 1268 case SPEED_1000: 1269 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1270 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1271 break; 1272 case SPEED_100: 1273 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1274 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1275 break; 1276 default: 1277 break; 1278 } 1279 1280 phy_set_max_speed(phydev, rdev->etha->speed); 1281 } 1282 1283 static int rswitch_phy_device_init(struct rswitch_device *rdev) 1284 { 1285 struct phy_device *phydev; 1286 struct device_node *phy; 1287 int err = -ENOENT; 1288 1289 if (!rdev->np_port) 1290 return -ENODEV; 1291 1292 phy = of_parse_phandle(rdev->np_port, "phy-handle", 0); 1293 if (!phy) 1294 return -ENODEV; 1295 1296 /* Set phydev->host_interfaces before calling of_phy_connect() to 1297 * configure the PHY with the information of host_interfaces. 1298 */ 1299 phydev = of_phy_find_device(phy); 1300 if (!phydev) 1301 goto out; 1302 __set_bit(rdev->etha->phy_interface, phydev->host_interfaces); 1303 1304 phydev = of_phy_connect(rdev->ndev, phy, rswitch_adjust_link, 0, 1305 rdev->etha->phy_interface); 1306 if (!phydev) 1307 goto out; 1308 1309 phy_set_max_speed(phydev, SPEED_2500); 1310 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1311 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1312 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1313 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1314 rswitch_phy_remove_link_mode(rdev, phydev); 1315 1316 phy_attached_info(phydev); 1317 1318 err = 0; 1319 out: 1320 of_node_put(phy); 1321 1322 return err; 1323 } 1324 1325 static void rswitch_phy_device_deinit(struct rswitch_device *rdev) 1326 { 1327 if (rdev->ndev->phydev) 1328 phy_disconnect(rdev->ndev->phydev); 1329 } 1330 1331 static int rswitch_serdes_set_params(struct rswitch_device *rdev) 1332 { 1333 int err; 1334 1335 err = phy_set_mode_ext(rdev->serdes, PHY_MODE_ETHERNET, 1336 rdev->etha->phy_interface); 1337 if (err < 0) 1338 return err; 1339 1340 return phy_set_speed(rdev->serdes, rdev->etha->speed); 1341 } 1342 1343 static int rswitch_ether_port_init_one(struct rswitch_device *rdev) 1344 { 1345 int err; 1346 1347 if (!rdev->etha->operated) { 1348 err = rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr); 1349 if (err < 0) 1350 return err; 1351 rdev->etha->operated = true; 1352 } 1353 1354 err = rswitch_mii_register(rdev); 1355 if (err < 0) 1356 return err; 1357 1358 err = rswitch_phy_device_init(rdev); 1359 if (err < 0) 1360 goto err_phy_device_init; 1361 1362 rdev->serdes = devm_of_phy_get(&rdev->priv->pdev->dev, rdev->np_port, NULL); 1363 if (IS_ERR(rdev->serdes)) { 1364 err = PTR_ERR(rdev->serdes); 1365 goto err_serdes_phy_get; 1366 } 1367 1368 err = rswitch_serdes_set_params(rdev); 1369 if (err < 0) 1370 goto err_serdes_set_params; 1371 1372 return 0; 1373 1374 err_serdes_set_params: 1375 err_serdes_phy_get: 1376 rswitch_phy_device_deinit(rdev); 1377 1378 err_phy_device_init: 1379 rswitch_mii_unregister(rdev); 1380 1381 return err; 1382 } 1383 1384 static void rswitch_ether_port_deinit_one(struct rswitch_device *rdev) 1385 { 1386 rswitch_phy_device_deinit(rdev); 1387 rswitch_mii_unregister(rdev); 1388 } 1389 1390 static int rswitch_ether_port_init_all(struct rswitch_private *priv) 1391 { 1392 int i, err; 1393 1394 rswitch_for_each_enabled_port(priv, i) { 1395 err = rswitch_ether_port_init_one(priv->rdev[i]); 1396 if (err) 1397 goto err_init_one; 1398 } 1399 1400 rswitch_for_each_enabled_port(priv, i) { 1401 err = phy_init(priv->rdev[i]->serdes); 1402 if (err) 1403 goto err_serdes; 1404 } 1405 1406 return 0; 1407 1408 err_serdes: 1409 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1410 phy_exit(priv->rdev[i]->serdes); 1411 i = RSWITCH_NUM_PORTS; 1412 1413 err_init_one: 1414 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1415 rswitch_ether_port_deinit_one(priv->rdev[i]); 1416 1417 return err; 1418 } 1419 1420 static void rswitch_ether_port_deinit_all(struct rswitch_private *priv) 1421 { 1422 int i; 1423 1424 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1425 phy_exit(priv->rdev[i]->serdes); 1426 rswitch_ether_port_deinit_one(priv->rdev[i]); 1427 } 1428 } 1429 1430 static int rswitch_open(struct net_device *ndev) 1431 { 1432 struct rswitch_device *rdev = netdev_priv(ndev); 1433 1434 phy_start(ndev->phydev); 1435 1436 napi_enable(&rdev->napi); 1437 netif_start_queue(ndev); 1438 1439 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, true); 1440 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, true); 1441 1442 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) 1443 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDIE); 1444 1445 bitmap_set(rdev->priv->opened_ports, rdev->port, 1); 1446 1447 return 0; 1448 }; 1449 1450 static int rswitch_stop(struct net_device *ndev) 1451 { 1452 struct rswitch_device *rdev = netdev_priv(ndev); 1453 struct rswitch_gwca_ts_info *ts_info, *ts_info2; 1454 1455 netif_tx_stop_all_queues(ndev); 1456 bitmap_clear(rdev->priv->opened_ports, rdev->port, 1); 1457 1458 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) 1459 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDID); 1460 1461 list_for_each_entry_safe(ts_info, ts_info2, &rdev->priv->gwca.ts_info_list, list) { 1462 if (ts_info->port != rdev->port) 1463 continue; 1464 dev_kfree_skb_irq(ts_info->skb); 1465 list_del(&ts_info->list); 1466 kfree(ts_info); 1467 } 1468 1469 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 1470 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 1471 1472 phy_stop(ndev->phydev); 1473 napi_disable(&rdev->napi); 1474 1475 return 0; 1476 }; 1477 1478 static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1479 { 1480 struct rswitch_device *rdev = netdev_priv(ndev); 1481 struct rswitch_gwca_queue *gq = rdev->tx_queue; 1482 struct rswitch_ext_desc *desc; 1483 int ret = NETDEV_TX_OK; 1484 dma_addr_t dma_addr; 1485 1486 if (rswitch_get_num_cur_queues(gq) >= gq->ring_size - 1) { 1487 netif_stop_subqueue(ndev, 0); 1488 return ret; 1489 } 1490 1491 if (skb_put_padto(skb, ETH_ZLEN)) 1492 return ret; 1493 1494 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, DMA_TO_DEVICE); 1495 if (dma_mapping_error(ndev->dev.parent, dma_addr)) { 1496 dev_kfree_skb_any(skb); 1497 return ret; 1498 } 1499 1500 gq->skbs[gq->cur] = skb; 1501 desc = &gq->tx_ring[gq->cur]; 1502 rswitch_desc_set_dptr(&desc->desc, dma_addr); 1503 desc->desc.info_ds = cpu_to_le16(skb->len); 1504 1505 desc->info1 = cpu_to_le64(INFO1_DV(BIT(rdev->etha->index)) | INFO1_FMT); 1506 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 1507 struct rswitch_gwca_ts_info *ts_info; 1508 1509 ts_info = kzalloc(sizeof(*ts_info), GFP_ATOMIC); 1510 if (!ts_info) { 1511 dma_unmap_single(ndev->dev.parent, dma_addr, skb->len, DMA_TO_DEVICE); 1512 return -ENOMEM; 1513 } 1514 1515 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1516 rdev->ts_tag++; 1517 desc->info1 |= cpu_to_le64(INFO1_TSUN(rdev->ts_tag) | INFO1_TXC); 1518 1519 ts_info->skb = skb_get(skb); 1520 ts_info->port = rdev->port; 1521 ts_info->tag = rdev->ts_tag; 1522 list_add_tail(&ts_info->list, &rdev->priv->gwca.ts_info_list); 1523 1524 skb_tx_timestamp(skb); 1525 } 1526 1527 dma_wmb(); 1528 1529 desc->desc.die_dt = DT_FSINGLE | DIE; 1530 wmb(); /* gq->cur must be incremented after die_dt was set */ 1531 1532 gq->cur = rswitch_next_queue_index(gq, true, 1); 1533 rswitch_modify(rdev->addr, GWTRC(gq->index), 0, BIT(gq->index % 32)); 1534 1535 return ret; 1536 } 1537 1538 static struct net_device_stats *rswitch_get_stats(struct net_device *ndev) 1539 { 1540 return &ndev->stats; 1541 } 1542 1543 static int rswitch_hwstamp_get(struct net_device *ndev, struct ifreq *req) 1544 { 1545 struct rswitch_device *rdev = netdev_priv(ndev); 1546 struct rcar_gen4_ptp_private *ptp_priv; 1547 struct hwtstamp_config config; 1548 1549 ptp_priv = rdev->priv->ptp_priv; 1550 1551 config.flags = 0; 1552 config.tx_type = ptp_priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1553 HWTSTAMP_TX_OFF; 1554 switch (ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE) { 1555 case RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT: 1556 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1557 break; 1558 case RCAR_GEN4_RXTSTAMP_TYPE_ALL: 1559 config.rx_filter = HWTSTAMP_FILTER_ALL; 1560 break; 1561 default: 1562 config.rx_filter = HWTSTAMP_FILTER_NONE; 1563 break; 1564 } 1565 1566 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1567 } 1568 1569 static int rswitch_hwstamp_set(struct net_device *ndev, struct ifreq *req) 1570 { 1571 struct rswitch_device *rdev = netdev_priv(ndev); 1572 u32 tstamp_rx_ctrl = RCAR_GEN4_RXTSTAMP_ENABLED; 1573 struct hwtstamp_config config; 1574 u32 tstamp_tx_ctrl; 1575 1576 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1577 return -EFAULT; 1578 1579 if (config.flags) 1580 return -EINVAL; 1581 1582 switch (config.tx_type) { 1583 case HWTSTAMP_TX_OFF: 1584 tstamp_tx_ctrl = 0; 1585 break; 1586 case HWTSTAMP_TX_ON: 1587 tstamp_tx_ctrl = RCAR_GEN4_TXTSTAMP_ENABLED; 1588 break; 1589 default: 1590 return -ERANGE; 1591 } 1592 1593 switch (config.rx_filter) { 1594 case HWTSTAMP_FILTER_NONE: 1595 tstamp_rx_ctrl = 0; 1596 break; 1597 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1598 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 1599 break; 1600 default: 1601 config.rx_filter = HWTSTAMP_FILTER_ALL; 1602 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_ALL; 1603 break; 1604 } 1605 1606 rdev->priv->ptp_priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1607 rdev->priv->ptp_priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1608 1609 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1610 } 1611 1612 static int rswitch_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1613 { 1614 if (!netif_running(ndev)) 1615 return -EINVAL; 1616 1617 switch (cmd) { 1618 case SIOCGHWTSTAMP: 1619 return rswitch_hwstamp_get(ndev, req); 1620 case SIOCSHWTSTAMP: 1621 return rswitch_hwstamp_set(ndev, req); 1622 default: 1623 return phy_mii_ioctl(ndev->phydev, req, cmd); 1624 } 1625 } 1626 1627 static const struct net_device_ops rswitch_netdev_ops = { 1628 .ndo_open = rswitch_open, 1629 .ndo_stop = rswitch_stop, 1630 .ndo_start_xmit = rswitch_start_xmit, 1631 .ndo_get_stats = rswitch_get_stats, 1632 .ndo_eth_ioctl = rswitch_eth_ioctl, 1633 .ndo_validate_addr = eth_validate_addr, 1634 .ndo_set_mac_address = eth_mac_addr, 1635 }; 1636 1637 static int rswitch_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) 1638 { 1639 struct rswitch_device *rdev = netdev_priv(ndev); 1640 1641 info->phc_index = ptp_clock_index(rdev->priv->ptp_priv->clock); 1642 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1643 SOF_TIMESTAMPING_RX_SOFTWARE | 1644 SOF_TIMESTAMPING_SOFTWARE | 1645 SOF_TIMESTAMPING_TX_HARDWARE | 1646 SOF_TIMESTAMPING_RX_HARDWARE | 1647 SOF_TIMESTAMPING_RAW_HARDWARE; 1648 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); 1649 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1650 1651 return 0; 1652 } 1653 1654 static const struct ethtool_ops rswitch_ethtool_ops = { 1655 .get_ts_info = rswitch_get_ts_info, 1656 }; 1657 1658 static const struct of_device_id renesas_eth_sw_of_table[] = { 1659 { .compatible = "renesas,r8a779f0-ether-switch", }, 1660 { } 1661 }; 1662 MODULE_DEVICE_TABLE(of, renesas_eth_sw_of_table); 1663 1664 static void rswitch_etha_init(struct rswitch_private *priv, int index) 1665 { 1666 struct rswitch_etha *etha = &priv->etha[index]; 1667 1668 memset(etha, 0, sizeof(*etha)); 1669 etha->index = index; 1670 etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE; 1671 etha->coma_addr = priv->addr; 1672 } 1673 1674 static int rswitch_device_alloc(struct rswitch_private *priv, int index) 1675 { 1676 struct platform_device *pdev = priv->pdev; 1677 struct rswitch_device *rdev; 1678 struct net_device *ndev; 1679 int err; 1680 1681 if (index >= RSWITCH_NUM_PORTS) 1682 return -EINVAL; 1683 1684 ndev = alloc_etherdev_mqs(sizeof(struct rswitch_device), 1, 1); 1685 if (!ndev) 1686 return -ENOMEM; 1687 1688 SET_NETDEV_DEV(ndev, &pdev->dev); 1689 ether_setup(ndev); 1690 1691 rdev = netdev_priv(ndev); 1692 rdev->ndev = ndev; 1693 rdev->priv = priv; 1694 priv->rdev[index] = rdev; 1695 rdev->port = index; 1696 rdev->etha = &priv->etha[index]; 1697 rdev->addr = priv->addr; 1698 1699 ndev->base_addr = (unsigned long)rdev->addr; 1700 snprintf(ndev->name, IFNAMSIZ, "tsn%d", index); 1701 ndev->netdev_ops = &rswitch_netdev_ops; 1702 ndev->ethtool_ops = &rswitch_ethtool_ops; 1703 1704 netif_napi_add(ndev, &rdev->napi, rswitch_poll); 1705 1706 rdev->np_port = rswitch_get_port_node(rdev); 1707 rdev->disabled = !rdev->np_port; 1708 err = of_get_ethdev_address(rdev->np_port, ndev); 1709 of_node_put(rdev->np_port); 1710 if (err) { 1711 if (is_valid_ether_addr(rdev->etha->mac_addr)) 1712 eth_hw_addr_set(ndev, rdev->etha->mac_addr); 1713 else 1714 eth_hw_addr_random(ndev); 1715 } 1716 1717 err = rswitch_etha_get_params(rdev); 1718 if (err < 0) 1719 goto out_get_params; 1720 1721 if (rdev->priv->gwca.speed < rdev->etha->speed) 1722 rdev->priv->gwca.speed = rdev->etha->speed; 1723 1724 err = rswitch_rxdmac_alloc(ndev); 1725 if (err < 0) 1726 goto out_rxdmac; 1727 1728 err = rswitch_txdmac_alloc(ndev); 1729 if (err < 0) 1730 goto out_txdmac; 1731 1732 return 0; 1733 1734 out_txdmac: 1735 rswitch_rxdmac_free(ndev); 1736 1737 out_rxdmac: 1738 out_get_params: 1739 netif_napi_del(&rdev->napi); 1740 free_netdev(ndev); 1741 1742 return err; 1743 } 1744 1745 static void rswitch_device_free(struct rswitch_private *priv, int index) 1746 { 1747 struct rswitch_device *rdev = priv->rdev[index]; 1748 struct net_device *ndev = rdev->ndev; 1749 1750 rswitch_txdmac_free(ndev); 1751 rswitch_rxdmac_free(ndev); 1752 netif_napi_del(&rdev->napi); 1753 free_netdev(ndev); 1754 } 1755 1756 static int rswitch_init(struct rswitch_private *priv) 1757 { 1758 int i, err; 1759 1760 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1761 rswitch_etha_init(priv, i); 1762 1763 rswitch_clock_enable(priv); 1764 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1765 rswitch_etha_read_mac_address(&priv->etha[i]); 1766 1767 rswitch_reset(priv); 1768 1769 rswitch_clock_enable(priv); 1770 rswitch_top_init(priv); 1771 err = rswitch_bpool_config(priv); 1772 if (err < 0) 1773 return err; 1774 1775 err = rswitch_gwca_linkfix_alloc(priv); 1776 if (err < 0) 1777 return -ENOMEM; 1778 1779 err = rswitch_gwca_ts_queue_alloc(priv); 1780 if (err < 0) 1781 goto err_ts_queue_alloc; 1782 1783 rswitch_gwca_ts_queue_fill(priv, 0, TS_RING_SIZE); 1784 INIT_LIST_HEAD(&priv->gwca.ts_info_list); 1785 1786 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1787 err = rswitch_device_alloc(priv, i); 1788 if (err < 0) { 1789 for (i--; i >= 0; i--) 1790 rswitch_device_free(priv, i); 1791 goto err_device_alloc; 1792 } 1793 } 1794 1795 rswitch_fwd_init(priv); 1796 1797 err = rcar_gen4_ptp_register(priv->ptp_priv, RCAR_GEN4_PTP_REG_LAYOUT_S4, 1798 RCAR_GEN4_PTP_CLOCK_S4); 1799 if (err < 0) 1800 goto err_ptp_register; 1801 1802 err = rswitch_gwca_request_irqs(priv); 1803 if (err < 0) 1804 goto err_gwca_request_irq; 1805 1806 err = rswitch_gwca_ts_request_irqs(priv); 1807 if (err < 0) 1808 goto err_gwca_ts_request_irq; 1809 1810 err = rswitch_gwca_hw_init(priv); 1811 if (err < 0) 1812 goto err_gwca_hw_init; 1813 1814 err = rswitch_ether_port_init_all(priv); 1815 if (err) 1816 goto err_ether_port_init_all; 1817 1818 rswitch_for_each_enabled_port(priv, i) { 1819 err = register_netdev(priv->rdev[i]->ndev); 1820 if (err) { 1821 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1822 unregister_netdev(priv->rdev[i]->ndev); 1823 goto err_register_netdev; 1824 } 1825 } 1826 1827 rswitch_for_each_enabled_port(priv, i) 1828 netdev_info(priv->rdev[i]->ndev, "MAC address %pM\n", 1829 priv->rdev[i]->ndev->dev_addr); 1830 1831 return 0; 1832 1833 err_register_netdev: 1834 rswitch_ether_port_deinit_all(priv); 1835 1836 err_ether_port_init_all: 1837 rswitch_gwca_hw_deinit(priv); 1838 1839 err_gwca_hw_init: 1840 err_gwca_ts_request_irq: 1841 err_gwca_request_irq: 1842 rcar_gen4_ptp_unregister(priv->ptp_priv); 1843 1844 err_ptp_register: 1845 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1846 rswitch_device_free(priv, i); 1847 1848 err_device_alloc: 1849 rswitch_gwca_ts_queue_free(priv); 1850 1851 err_ts_queue_alloc: 1852 rswitch_gwca_linkfix_free(priv); 1853 1854 return err; 1855 } 1856 1857 static int renesas_eth_sw_probe(struct platform_device *pdev) 1858 { 1859 struct rswitch_private *priv; 1860 struct resource *res; 1861 int ret; 1862 1863 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "secure_base"); 1864 if (!res) { 1865 dev_err(&pdev->dev, "invalid resource\n"); 1866 return -EINVAL; 1867 } 1868 1869 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1870 if (!priv) 1871 return -ENOMEM; 1872 1873 priv->ptp_priv = rcar_gen4_ptp_alloc(pdev); 1874 if (!priv->ptp_priv) 1875 return -ENOMEM; 1876 1877 platform_set_drvdata(pdev, priv); 1878 priv->pdev = pdev; 1879 priv->addr = devm_ioremap_resource(&pdev->dev, res); 1880 if (IS_ERR(priv->addr)) 1881 return PTR_ERR(priv->addr); 1882 1883 priv->ptp_priv->addr = priv->addr + RCAR_GEN4_GPTP_OFFSET_S4; 1884 1885 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 1886 if (ret < 0) { 1887 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1888 if (ret < 0) 1889 return ret; 1890 } 1891 1892 priv->gwca.index = AGENT_INDEX_GWCA; 1893 priv->gwca.num_queues = min(RSWITCH_NUM_PORTS * NUM_QUEUES_PER_NDEV, 1894 RSWITCH_MAX_NUM_QUEUES); 1895 priv->gwca.queues = devm_kcalloc(&pdev->dev, priv->gwca.num_queues, 1896 sizeof(*priv->gwca.queues), GFP_KERNEL); 1897 if (!priv->gwca.queues) 1898 return -ENOMEM; 1899 1900 pm_runtime_enable(&pdev->dev); 1901 pm_runtime_get_sync(&pdev->dev); 1902 1903 ret = rswitch_init(priv); 1904 if (ret < 0) { 1905 pm_runtime_put(&pdev->dev); 1906 pm_runtime_disable(&pdev->dev); 1907 return ret; 1908 } 1909 1910 device_set_wakeup_capable(&pdev->dev, 1); 1911 1912 return ret; 1913 } 1914 1915 static void rswitch_deinit(struct rswitch_private *priv) 1916 { 1917 int i; 1918 1919 rswitch_gwca_hw_deinit(priv); 1920 rcar_gen4_ptp_unregister(priv->ptp_priv); 1921 1922 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1923 struct rswitch_device *rdev = priv->rdev[i]; 1924 1925 phy_exit(priv->rdev[i]->serdes); 1926 rswitch_ether_port_deinit_one(rdev); 1927 unregister_netdev(rdev->ndev); 1928 rswitch_device_free(priv, i); 1929 } 1930 1931 rswitch_gwca_ts_queue_free(priv); 1932 rswitch_gwca_linkfix_free(priv); 1933 1934 rswitch_clock_disable(priv); 1935 } 1936 1937 static int renesas_eth_sw_remove(struct platform_device *pdev) 1938 { 1939 struct rswitch_private *priv = platform_get_drvdata(pdev); 1940 1941 rswitch_deinit(priv); 1942 1943 pm_runtime_put(&pdev->dev); 1944 pm_runtime_disable(&pdev->dev); 1945 1946 platform_set_drvdata(pdev, NULL); 1947 1948 return 0; 1949 } 1950 1951 static struct platform_driver renesas_eth_sw_driver_platform = { 1952 .probe = renesas_eth_sw_probe, 1953 .remove = renesas_eth_sw_remove, 1954 .driver = { 1955 .name = "renesas_eth_sw", 1956 .of_match_table = renesas_eth_sw_of_table, 1957 } 1958 }; 1959 module_platform_driver(renesas_eth_sw_driver_platform); 1960 MODULE_AUTHOR("Yoshihiro Shimoda"); 1961 MODULE_DESCRIPTION("Renesas Ethernet Switch device driver"); 1962 MODULE_LICENSE("GPL"); 1963