1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet Switch device driver 3 * 4 * Copyright (C) 2022 Renesas Electronics Corporation 5 */ 6 7 #include <linux/dma-mapping.h> 8 #include <linux/err.h> 9 #include <linux/etherdevice.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 #include <linux/phy/phy.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/rtnetlink.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 25 #include "rswitch.h" 26 27 static int rswitch_reg_wait(void __iomem *addr, u32 offs, u32 mask, u32 expected) 28 { 29 u32 val; 30 31 return readl_poll_timeout_atomic(addr + offs, val, (val & mask) == expected, 32 1, RSWITCH_TIMEOUT_US); 33 } 34 35 static void rswitch_modify(void __iomem *addr, enum rswitch_reg reg, u32 clear, u32 set) 36 { 37 iowrite32((ioread32(addr + reg) & ~clear) | set, addr + reg); 38 } 39 40 /* Common Agent block (COMA) */ 41 static void rswitch_reset(struct rswitch_private *priv) 42 { 43 iowrite32(RRC_RR, priv->addr + RRC); 44 iowrite32(RRC_RR_CLR, priv->addr + RRC); 45 } 46 47 static void rswitch_clock_enable(struct rswitch_private *priv) 48 { 49 iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC); 50 } 51 52 static void rswitch_clock_disable(struct rswitch_private *priv) 53 { 54 iowrite32(RCDC_RCD, priv->addr + RCDC); 55 } 56 57 static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr, int port) 58 { 59 u32 val = ioread32(coma_addr + RCEC); 60 61 if (val & RCEC_RCE) 62 return (val & BIT(port)) ? true : false; 63 else 64 return false; 65 } 66 67 static void rswitch_agent_clock_ctrl(void __iomem *coma_addr, int port, int enable) 68 { 69 u32 val; 70 71 if (enable) { 72 val = ioread32(coma_addr + RCEC); 73 iowrite32(val | RCEC_RCE | BIT(port), coma_addr + RCEC); 74 } else { 75 val = ioread32(coma_addr + RCDC); 76 iowrite32(val | BIT(port), coma_addr + RCDC); 77 } 78 } 79 80 static int rswitch_bpool_config(struct rswitch_private *priv) 81 { 82 u32 val; 83 84 val = ioread32(priv->addr + CABPIRM); 85 if (val & CABPIRM_BPR) 86 return 0; 87 88 iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM); 89 90 return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR); 91 } 92 93 /* R-Switch-2 block (TOP) */ 94 static void rswitch_top_init(struct rswitch_private *priv) 95 { 96 int i; 97 98 for (i = 0; i < RSWITCH_MAX_NUM_QUEUES; i++) 99 iowrite32((i / 16) << (GWCA_INDEX * 8), priv->addr + TPEMIMC7(i)); 100 } 101 102 /* Forwarding engine block (MFWD) */ 103 static void rswitch_fwd_init(struct rswitch_private *priv) 104 { 105 int i; 106 107 /* For ETHA */ 108 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 109 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(i)); 110 iowrite32(0, priv->addr + FWPBFC(i)); 111 } 112 113 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 114 iowrite32(priv->rdev[i]->rx_queue->index, 115 priv->addr + FWPBFCSDC(GWCA_INDEX, i)); 116 iowrite32(BIT(priv->gwca.index), priv->addr + FWPBFC(i)); 117 } 118 119 /* For GWCA */ 120 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(priv->gwca.index)); 121 iowrite32(FWPC1_DDE, priv->addr + FWPC1(priv->gwca.index)); 122 iowrite32(0, priv->addr + FWPBFC(priv->gwca.index)); 123 iowrite32(GENMASK(RSWITCH_NUM_PORTS - 1, 0), priv->addr + FWPBFC(priv->gwca.index)); 124 } 125 126 /* Gateway CPU agent block (GWCA) */ 127 static int rswitch_gwca_change_mode(struct rswitch_private *priv, 128 enum rswitch_gwca_mode mode) 129 { 130 int ret; 131 132 if (!rswitch_agent_clock_is_enabled(priv->addr, priv->gwca.index)) 133 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 1); 134 135 iowrite32(mode, priv->addr + GWMC); 136 137 ret = rswitch_reg_wait(priv->addr, GWMS, GWMS_OPS_MASK, mode); 138 139 if (mode == GWMC_OPC_DISABLE) 140 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 0); 141 142 return ret; 143 } 144 145 static int rswitch_gwca_mcast_table_reset(struct rswitch_private *priv) 146 { 147 iowrite32(GWMTIRM_MTIOG, priv->addr + GWMTIRM); 148 149 return rswitch_reg_wait(priv->addr, GWMTIRM, GWMTIRM_MTR, GWMTIRM_MTR); 150 } 151 152 static int rswitch_gwca_axi_ram_reset(struct rswitch_private *priv) 153 { 154 iowrite32(GWARIRM_ARIOG, priv->addr + GWARIRM); 155 156 return rswitch_reg_wait(priv->addr, GWARIRM, GWARIRM_ARR, GWARIRM_ARR); 157 } 158 159 static void rswitch_gwca_set_rate_limit(struct rswitch_private *priv, int rate) 160 { 161 u32 gwgrlulc, gwgrlc; 162 163 switch (rate) { 164 case 1000: 165 gwgrlulc = 0x0000005f; 166 gwgrlc = 0x00010260; 167 break; 168 default: 169 dev_err(&priv->pdev->dev, "%s: This rate is not supported (%d)\n", __func__, rate); 170 return; 171 } 172 173 iowrite32(gwgrlulc, priv->addr + GWGRLULC); 174 iowrite32(gwgrlc, priv->addr + GWGRLC); 175 } 176 177 static bool rswitch_is_any_data_irq(struct rswitch_private *priv, u32 *dis, bool tx) 178 { 179 u32 *mask = tx ? priv->gwca.tx_irq_bits : priv->gwca.rx_irq_bits; 180 int i; 181 182 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 183 if (dis[i] & mask[i]) 184 return true; 185 } 186 187 return false; 188 } 189 190 static void rswitch_get_data_irq_status(struct rswitch_private *priv, u32 *dis) 191 { 192 int i; 193 194 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 195 dis[i] = ioread32(priv->addr + GWDIS(i)); 196 dis[i] &= ioread32(priv->addr + GWDIE(i)); 197 } 198 } 199 200 static void rswitch_enadis_data_irq(struct rswitch_private *priv, int index, bool enable) 201 { 202 u32 offs = enable ? GWDIE(index / 32) : GWDID(index / 32); 203 204 iowrite32(BIT(index % 32), priv->addr + offs); 205 } 206 207 static void rswitch_ack_data_irq(struct rswitch_private *priv, int index) 208 { 209 u32 offs = GWDIS(index / 32); 210 211 iowrite32(BIT(index % 32), priv->addr + offs); 212 } 213 214 static int rswitch_next_queue_index(struct rswitch_gwca_queue *gq, bool cur, int num) 215 { 216 int index = cur ? gq->cur : gq->dirty; 217 218 if (index + num >= gq->ring_size) 219 index = (index + num) % gq->ring_size; 220 else 221 index += num; 222 223 return index; 224 } 225 226 static int rswitch_get_num_cur_queues(struct rswitch_gwca_queue *gq) 227 { 228 if (gq->cur >= gq->dirty) 229 return gq->cur - gq->dirty; 230 else 231 return gq->ring_size - gq->dirty + gq->cur; 232 } 233 234 static bool rswitch_is_queue_rxed(struct rswitch_gwca_queue *gq) 235 { 236 struct rswitch_ext_ts_desc *desc = &gq->rx_ring[gq->dirty]; 237 238 if ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) 239 return true; 240 241 return false; 242 } 243 244 static int rswitch_gwca_queue_alloc_skb(struct rswitch_gwca_queue *gq, 245 int start_index, int num) 246 { 247 int i, index; 248 249 for (i = 0; i < num; i++) { 250 index = (i + start_index) % gq->ring_size; 251 if (gq->skbs[index]) 252 continue; 253 gq->skbs[index] = netdev_alloc_skb_ip_align(gq->ndev, 254 PKT_BUF_SZ + RSWITCH_ALIGN - 1); 255 if (!gq->skbs[index]) 256 goto err; 257 } 258 259 return 0; 260 261 err: 262 for (i--; i >= 0; i--) { 263 index = (i + start_index) % gq->ring_size; 264 dev_kfree_skb(gq->skbs[index]); 265 gq->skbs[index] = NULL; 266 } 267 268 return -ENOMEM; 269 } 270 271 static void rswitch_gwca_queue_free(struct net_device *ndev, 272 struct rswitch_gwca_queue *gq) 273 { 274 int i; 275 276 if (!gq->dir_tx) { 277 dma_free_coherent(ndev->dev.parent, 278 sizeof(struct rswitch_ext_ts_desc) * 279 (gq->ring_size + 1), gq->rx_ring, gq->ring_dma); 280 gq->rx_ring = NULL; 281 282 for (i = 0; i < gq->ring_size; i++) 283 dev_kfree_skb(gq->skbs[i]); 284 } else { 285 dma_free_coherent(ndev->dev.parent, 286 sizeof(struct rswitch_ext_desc) * 287 (gq->ring_size + 1), gq->tx_ring, gq->ring_dma); 288 gq->tx_ring = NULL; 289 } 290 291 kfree(gq->skbs); 292 gq->skbs = NULL; 293 } 294 295 static void rswitch_gwca_ts_queue_free(struct rswitch_private *priv) 296 { 297 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 298 299 dma_free_coherent(&priv->pdev->dev, 300 sizeof(struct rswitch_ts_desc) * (gq->ring_size + 1), 301 gq->ts_ring, gq->ring_dma); 302 gq->ts_ring = NULL; 303 } 304 305 static int rswitch_gwca_queue_alloc(struct net_device *ndev, 306 struct rswitch_private *priv, 307 struct rswitch_gwca_queue *gq, 308 bool dir_tx, int ring_size) 309 { 310 int i, bit; 311 312 gq->dir_tx = dir_tx; 313 gq->ring_size = ring_size; 314 gq->ndev = ndev; 315 316 gq->skbs = kcalloc(gq->ring_size, sizeof(*gq->skbs), GFP_KERNEL); 317 if (!gq->skbs) 318 return -ENOMEM; 319 320 if (!dir_tx) { 321 rswitch_gwca_queue_alloc_skb(gq, 0, gq->ring_size); 322 323 gq->rx_ring = dma_alloc_coherent(ndev->dev.parent, 324 sizeof(struct rswitch_ext_ts_desc) * 325 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 326 } else { 327 gq->tx_ring = dma_alloc_coherent(ndev->dev.parent, 328 sizeof(struct rswitch_ext_desc) * 329 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 330 } 331 332 if (!gq->rx_ring && !gq->tx_ring) 333 goto out; 334 335 i = gq->index / 32; 336 bit = BIT(gq->index % 32); 337 if (dir_tx) 338 priv->gwca.tx_irq_bits[i] |= bit; 339 else 340 priv->gwca.rx_irq_bits[i] |= bit; 341 342 return 0; 343 344 out: 345 rswitch_gwca_queue_free(ndev, gq); 346 347 return -ENOMEM; 348 } 349 350 static void rswitch_desc_set_dptr(struct rswitch_desc *desc, dma_addr_t addr) 351 { 352 desc->dptrl = cpu_to_le32(lower_32_bits(addr)); 353 desc->dptrh = upper_32_bits(addr) & 0xff; 354 } 355 356 static dma_addr_t rswitch_desc_get_dptr(const struct rswitch_desc *desc) 357 { 358 return __le32_to_cpu(desc->dptrl) | (u64)(desc->dptrh) << 32; 359 } 360 361 static int rswitch_gwca_queue_format(struct net_device *ndev, 362 struct rswitch_private *priv, 363 struct rswitch_gwca_queue *gq) 364 { 365 int ring_size = sizeof(struct rswitch_ext_desc) * gq->ring_size; 366 struct rswitch_ext_desc *desc; 367 struct rswitch_desc *linkfix; 368 dma_addr_t dma_addr; 369 int i; 370 371 memset(gq->tx_ring, 0, ring_size); 372 for (i = 0, desc = gq->tx_ring; i < gq->ring_size; i++, desc++) { 373 if (!gq->dir_tx) { 374 dma_addr = dma_map_single(ndev->dev.parent, 375 gq->skbs[i]->data, PKT_BUF_SZ, 376 DMA_FROM_DEVICE); 377 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 378 goto err; 379 380 desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ); 381 rswitch_desc_set_dptr(&desc->desc, dma_addr); 382 desc->desc.die_dt = DT_FEMPTY | DIE; 383 } else { 384 desc->desc.die_dt = DT_EEMPTY | DIE; 385 } 386 } 387 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 388 desc->desc.die_dt = DT_LINKFIX; 389 390 linkfix = &priv->gwca.linkfix_table[gq->index]; 391 linkfix->die_dt = DT_LINKFIX; 392 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 393 394 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DQT : 0) | GWDCC_EDE, 395 priv->addr + GWDCC_OFFS(gq->index)); 396 397 return 0; 398 399 err: 400 if (!gq->dir_tx) { 401 for (i--, desc = gq->tx_ring; i >= 0; i--, desc++) { 402 dma_addr = rswitch_desc_get_dptr(&desc->desc); 403 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, 404 DMA_FROM_DEVICE); 405 } 406 } 407 408 return -ENOMEM; 409 } 410 411 static void rswitch_gwca_ts_queue_fill(struct rswitch_private *priv, 412 int start_index, int num) 413 { 414 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 415 struct rswitch_ts_desc *desc; 416 int i, index; 417 418 for (i = 0; i < num; i++) { 419 index = (i + start_index) % gq->ring_size; 420 desc = &gq->ts_ring[index]; 421 desc->desc.die_dt = DT_FEMPTY_ND | DIE; 422 } 423 } 424 425 static int rswitch_gwca_queue_ext_ts_fill(struct net_device *ndev, 426 struct rswitch_gwca_queue *gq, 427 int start_index, int num) 428 { 429 struct rswitch_device *rdev = netdev_priv(ndev); 430 struct rswitch_ext_ts_desc *desc; 431 dma_addr_t dma_addr; 432 int i, index; 433 434 for (i = 0; i < num; i++) { 435 index = (i + start_index) % gq->ring_size; 436 desc = &gq->rx_ring[index]; 437 if (!gq->dir_tx) { 438 dma_addr = dma_map_single(ndev->dev.parent, 439 gq->skbs[index]->data, PKT_BUF_SZ, 440 DMA_FROM_DEVICE); 441 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 442 goto err; 443 444 desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ); 445 rswitch_desc_set_dptr(&desc->desc, dma_addr); 446 dma_wmb(); 447 desc->desc.die_dt = DT_FEMPTY | DIE; 448 desc->info1 = cpu_to_le64(INFO1_SPN(rdev->etha->index)); 449 } else { 450 desc->desc.die_dt = DT_EEMPTY | DIE; 451 } 452 } 453 454 return 0; 455 456 err: 457 if (!gq->dir_tx) { 458 for (i--; i >= 0; i--) { 459 index = (i + start_index) % gq->ring_size; 460 desc = &gq->rx_ring[index]; 461 dma_addr = rswitch_desc_get_dptr(&desc->desc); 462 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, 463 DMA_FROM_DEVICE); 464 } 465 } 466 467 return -ENOMEM; 468 } 469 470 static int rswitch_gwca_queue_ext_ts_format(struct net_device *ndev, 471 struct rswitch_private *priv, 472 struct rswitch_gwca_queue *gq) 473 { 474 int ring_size = sizeof(struct rswitch_ext_ts_desc) * gq->ring_size; 475 struct rswitch_ext_ts_desc *desc; 476 struct rswitch_desc *linkfix; 477 int err; 478 479 memset(gq->rx_ring, 0, ring_size); 480 err = rswitch_gwca_queue_ext_ts_fill(ndev, gq, 0, gq->ring_size); 481 if (err < 0) 482 return err; 483 484 desc = &gq->rx_ring[gq->ring_size]; /* Last */ 485 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 486 desc->desc.die_dt = DT_LINKFIX; 487 488 linkfix = &priv->gwca.linkfix_table[gq->index]; 489 linkfix->die_dt = DT_LINKFIX; 490 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 491 492 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DQT : 0) | GWDCC_ETS | GWDCC_EDE, 493 priv->addr + GWDCC_OFFS(gq->index)); 494 495 return 0; 496 } 497 498 static int rswitch_gwca_linkfix_alloc(struct rswitch_private *priv) 499 { 500 int i, num_queues = priv->gwca.num_queues; 501 struct rswitch_gwca *gwca = &priv->gwca; 502 struct device *dev = &priv->pdev->dev; 503 504 gwca->linkfix_table_size = sizeof(struct rswitch_desc) * num_queues; 505 gwca->linkfix_table = dma_alloc_coherent(dev, gwca->linkfix_table_size, 506 &gwca->linkfix_table_dma, GFP_KERNEL); 507 if (!gwca->linkfix_table) 508 return -ENOMEM; 509 for (i = 0; i < num_queues; i++) 510 gwca->linkfix_table[i].die_dt = DT_EOS; 511 512 return 0; 513 } 514 515 static void rswitch_gwca_linkfix_free(struct rswitch_private *priv) 516 { 517 struct rswitch_gwca *gwca = &priv->gwca; 518 519 if (gwca->linkfix_table) 520 dma_free_coherent(&priv->pdev->dev, gwca->linkfix_table_size, 521 gwca->linkfix_table, gwca->linkfix_table_dma); 522 gwca->linkfix_table = NULL; 523 } 524 525 static int rswitch_gwca_ts_queue_alloc(struct rswitch_private *priv) 526 { 527 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 528 struct rswitch_ts_desc *desc; 529 530 gq->ring_size = TS_RING_SIZE; 531 gq->ts_ring = dma_alloc_coherent(&priv->pdev->dev, 532 sizeof(struct rswitch_ts_desc) * 533 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 534 535 if (!gq->ts_ring) 536 return -ENOMEM; 537 538 rswitch_gwca_ts_queue_fill(priv, 0, TS_RING_SIZE); 539 desc = &gq->ts_ring[gq->ring_size]; 540 desc->desc.die_dt = DT_LINKFIX; 541 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 542 INIT_LIST_HEAD(&priv->gwca.ts_info_list); 543 544 return 0; 545 } 546 547 static struct rswitch_gwca_queue *rswitch_gwca_get(struct rswitch_private *priv) 548 { 549 struct rswitch_gwca_queue *gq; 550 int index; 551 552 index = find_first_zero_bit(priv->gwca.used, priv->gwca.num_queues); 553 if (index >= priv->gwca.num_queues) 554 return NULL; 555 set_bit(index, priv->gwca.used); 556 gq = &priv->gwca.queues[index]; 557 memset(gq, 0, sizeof(*gq)); 558 gq->index = index; 559 560 return gq; 561 } 562 563 static void rswitch_gwca_put(struct rswitch_private *priv, 564 struct rswitch_gwca_queue *gq) 565 { 566 clear_bit(gq->index, priv->gwca.used); 567 } 568 569 static int rswitch_txdmac_alloc(struct net_device *ndev) 570 { 571 struct rswitch_device *rdev = netdev_priv(ndev); 572 struct rswitch_private *priv = rdev->priv; 573 int err; 574 575 rdev->tx_queue = rswitch_gwca_get(priv); 576 if (!rdev->tx_queue) 577 return -EBUSY; 578 579 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->tx_queue, true, TX_RING_SIZE); 580 if (err < 0) { 581 rswitch_gwca_put(priv, rdev->tx_queue); 582 return err; 583 } 584 585 return 0; 586 } 587 588 static void rswitch_txdmac_free(struct net_device *ndev) 589 { 590 struct rswitch_device *rdev = netdev_priv(ndev); 591 592 rswitch_gwca_queue_free(ndev, rdev->tx_queue); 593 rswitch_gwca_put(rdev->priv, rdev->tx_queue); 594 } 595 596 static int rswitch_txdmac_init(struct rswitch_private *priv, int index) 597 { 598 struct rswitch_device *rdev = priv->rdev[index]; 599 600 return rswitch_gwca_queue_format(rdev->ndev, priv, rdev->tx_queue); 601 } 602 603 static int rswitch_rxdmac_alloc(struct net_device *ndev) 604 { 605 struct rswitch_device *rdev = netdev_priv(ndev); 606 struct rswitch_private *priv = rdev->priv; 607 int err; 608 609 rdev->rx_queue = rswitch_gwca_get(priv); 610 if (!rdev->rx_queue) 611 return -EBUSY; 612 613 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->rx_queue, false, RX_RING_SIZE); 614 if (err < 0) { 615 rswitch_gwca_put(priv, rdev->rx_queue); 616 return err; 617 } 618 619 return 0; 620 } 621 622 static void rswitch_rxdmac_free(struct net_device *ndev) 623 { 624 struct rswitch_device *rdev = netdev_priv(ndev); 625 626 rswitch_gwca_queue_free(ndev, rdev->rx_queue); 627 rswitch_gwca_put(rdev->priv, rdev->rx_queue); 628 } 629 630 static int rswitch_rxdmac_init(struct rswitch_private *priv, int index) 631 { 632 struct rswitch_device *rdev = priv->rdev[index]; 633 struct net_device *ndev = rdev->ndev; 634 635 return rswitch_gwca_queue_ext_ts_format(ndev, priv, rdev->rx_queue); 636 } 637 638 static int rswitch_gwca_hw_init(struct rswitch_private *priv) 639 { 640 int i, err; 641 642 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 643 if (err < 0) 644 return err; 645 err = rswitch_gwca_change_mode(priv, GWMC_OPC_CONFIG); 646 if (err < 0) 647 return err; 648 649 err = rswitch_gwca_mcast_table_reset(priv); 650 if (err < 0) 651 return err; 652 err = rswitch_gwca_axi_ram_reset(priv); 653 if (err < 0) 654 return err; 655 656 iowrite32(GWVCC_VEM_SC_TAG, priv->addr + GWVCC); 657 iowrite32(0, priv->addr + GWTTFC); 658 iowrite32(lower_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC1); 659 iowrite32(upper_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC0); 660 iowrite32(lower_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC10); 661 iowrite32(upper_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC00); 662 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDCC0); 663 rswitch_gwca_set_rate_limit(priv, priv->gwca.speed); 664 665 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 666 err = rswitch_rxdmac_init(priv, i); 667 if (err < 0) 668 return err; 669 err = rswitch_txdmac_init(priv, i); 670 if (err < 0) 671 return err; 672 } 673 674 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 675 if (err < 0) 676 return err; 677 return rswitch_gwca_change_mode(priv, GWMC_OPC_OPERATION); 678 } 679 680 static int rswitch_gwca_hw_deinit(struct rswitch_private *priv) 681 { 682 int err; 683 684 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 685 if (err < 0) 686 return err; 687 err = rswitch_gwca_change_mode(priv, GWMC_OPC_RESET); 688 if (err < 0) 689 return err; 690 691 return rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 692 } 693 694 static int rswitch_gwca_halt(struct rswitch_private *priv) 695 { 696 int err; 697 698 priv->gwca_halt = true; 699 err = rswitch_gwca_hw_deinit(priv); 700 dev_err(&priv->pdev->dev, "halted (%d)\n", err); 701 702 return err; 703 } 704 705 static bool rswitch_rx(struct net_device *ndev, int *quota) 706 { 707 struct rswitch_device *rdev = netdev_priv(ndev); 708 struct rswitch_gwca_queue *gq = rdev->rx_queue; 709 struct rswitch_ext_ts_desc *desc; 710 int limit, boguscnt, num, ret; 711 struct sk_buff *skb; 712 dma_addr_t dma_addr; 713 u16 pkt_len; 714 u32 get_ts; 715 716 if (*quota <= 0) 717 return true; 718 719 boguscnt = min_t(int, gq->ring_size, *quota); 720 limit = boguscnt; 721 722 desc = &gq->rx_ring[gq->cur]; 723 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) { 724 dma_rmb(); 725 pkt_len = le16_to_cpu(desc->desc.info_ds) & RX_DS; 726 skb = gq->skbs[gq->cur]; 727 gq->skbs[gq->cur] = NULL; 728 dma_addr = rswitch_desc_get_dptr(&desc->desc); 729 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, DMA_FROM_DEVICE); 730 get_ts = rdev->priv->ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 731 if (get_ts) { 732 struct skb_shared_hwtstamps *shhwtstamps; 733 struct timespec64 ts; 734 735 shhwtstamps = skb_hwtstamps(skb); 736 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 737 ts.tv_sec = __le32_to_cpu(desc->ts_sec); 738 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); 739 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 740 } 741 skb_put(skb, pkt_len); 742 skb->protocol = eth_type_trans(skb, ndev); 743 netif_receive_skb(skb); 744 rdev->ndev->stats.rx_packets++; 745 rdev->ndev->stats.rx_bytes += pkt_len; 746 747 gq->cur = rswitch_next_queue_index(gq, true, 1); 748 desc = &gq->rx_ring[gq->cur]; 749 750 if (--boguscnt <= 0) 751 break; 752 } 753 754 num = rswitch_get_num_cur_queues(gq); 755 ret = rswitch_gwca_queue_alloc_skb(gq, gq->dirty, num); 756 if (ret < 0) 757 goto err; 758 ret = rswitch_gwca_queue_ext_ts_fill(ndev, gq, gq->dirty, num); 759 if (ret < 0) 760 goto err; 761 gq->dirty = rswitch_next_queue_index(gq, false, num); 762 763 *quota -= limit - boguscnt; 764 765 return boguscnt <= 0; 766 767 err: 768 rswitch_gwca_halt(rdev->priv); 769 770 return 0; 771 } 772 773 static int rswitch_tx_free(struct net_device *ndev, bool free_txed_only) 774 { 775 struct rswitch_device *rdev = netdev_priv(ndev); 776 struct rswitch_gwca_queue *gq = rdev->tx_queue; 777 struct rswitch_ext_desc *desc; 778 dma_addr_t dma_addr; 779 struct sk_buff *skb; 780 int free_num = 0; 781 int size; 782 783 for (; rswitch_get_num_cur_queues(gq) > 0; 784 gq->dirty = rswitch_next_queue_index(gq, false, 1)) { 785 desc = &gq->tx_ring[gq->dirty]; 786 if (free_txed_only && (desc->desc.die_dt & DT_MASK) != DT_FEMPTY) 787 break; 788 789 dma_rmb(); 790 size = le16_to_cpu(desc->desc.info_ds) & TX_DS; 791 skb = gq->skbs[gq->dirty]; 792 if (skb) { 793 dma_addr = rswitch_desc_get_dptr(&desc->desc); 794 dma_unmap_single(ndev->dev.parent, dma_addr, 795 size, DMA_TO_DEVICE); 796 dev_kfree_skb_any(gq->skbs[gq->dirty]); 797 gq->skbs[gq->dirty] = NULL; 798 free_num++; 799 } 800 desc->desc.die_dt = DT_EEMPTY; 801 rdev->ndev->stats.tx_packets++; 802 rdev->ndev->stats.tx_bytes += size; 803 } 804 805 return free_num; 806 } 807 808 static int rswitch_poll(struct napi_struct *napi, int budget) 809 { 810 struct net_device *ndev = napi->dev; 811 struct rswitch_private *priv; 812 struct rswitch_device *rdev; 813 int quota = budget; 814 815 rdev = netdev_priv(ndev); 816 priv = rdev->priv; 817 818 retry: 819 rswitch_tx_free(ndev, true); 820 821 if (rswitch_rx(ndev, "a)) 822 goto out; 823 else if (rdev->priv->gwca_halt) 824 goto err; 825 else if (rswitch_is_queue_rxed(rdev->rx_queue)) 826 goto retry; 827 828 netif_wake_subqueue(ndev, 0); 829 830 napi_complete(napi); 831 832 rswitch_enadis_data_irq(priv, rdev->tx_queue->index, true); 833 rswitch_enadis_data_irq(priv, rdev->rx_queue->index, true); 834 835 out: 836 return budget - quota; 837 838 err: 839 napi_complete(napi); 840 841 return 0; 842 } 843 844 static void rswitch_queue_interrupt(struct net_device *ndev) 845 { 846 struct rswitch_device *rdev = netdev_priv(ndev); 847 848 if (napi_schedule_prep(&rdev->napi)) { 849 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 850 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 851 __napi_schedule(&rdev->napi); 852 } 853 } 854 855 static irqreturn_t rswitch_data_irq(struct rswitch_private *priv, u32 *dis) 856 { 857 struct rswitch_gwca_queue *gq; 858 int i, index, bit; 859 860 for (i = 0; i < priv->gwca.num_queues; i++) { 861 gq = &priv->gwca.queues[i]; 862 index = gq->index / 32; 863 bit = BIT(gq->index % 32); 864 if (!(dis[index] & bit)) 865 continue; 866 867 rswitch_ack_data_irq(priv, gq->index); 868 rswitch_queue_interrupt(gq->ndev); 869 } 870 871 return IRQ_HANDLED; 872 } 873 874 static irqreturn_t rswitch_gwca_irq(int irq, void *dev_id) 875 { 876 struct rswitch_private *priv = dev_id; 877 u32 dis[RSWITCH_NUM_IRQ_REGS]; 878 irqreturn_t ret = IRQ_NONE; 879 880 rswitch_get_data_irq_status(priv, dis); 881 882 if (rswitch_is_any_data_irq(priv, dis, true) || 883 rswitch_is_any_data_irq(priv, dis, false)) 884 ret = rswitch_data_irq(priv, dis); 885 886 return ret; 887 } 888 889 static int rswitch_gwca_request_irqs(struct rswitch_private *priv) 890 { 891 char *resource_name, *irq_name; 892 int i, ret, irq; 893 894 for (i = 0; i < GWCA_NUM_IRQS; i++) { 895 resource_name = kasprintf(GFP_KERNEL, GWCA_IRQ_RESOURCE_NAME, i); 896 if (!resource_name) 897 return -ENOMEM; 898 899 irq = platform_get_irq_byname(priv->pdev, resource_name); 900 kfree(resource_name); 901 if (irq < 0) 902 return irq; 903 904 irq_name = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL, 905 GWCA_IRQ_NAME, i); 906 if (!irq_name) 907 return -ENOMEM; 908 909 ret = devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_irq, 910 0, irq_name, priv); 911 if (ret < 0) 912 return ret; 913 } 914 915 return 0; 916 } 917 918 static void rswitch_ts(struct rswitch_private *priv) 919 { 920 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 921 struct rswitch_gwca_ts_info *ts_info, *ts_info2; 922 struct skb_shared_hwtstamps shhwtstamps; 923 struct rswitch_ts_desc *desc; 924 struct timespec64 ts; 925 u32 tag, port; 926 int num; 927 928 desc = &gq->ts_ring[gq->cur]; 929 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY_ND) { 930 dma_rmb(); 931 932 port = TS_DESC_DPN(__le32_to_cpu(desc->desc.dptrl)); 933 tag = TS_DESC_TSUN(__le32_to_cpu(desc->desc.dptrl)); 934 935 list_for_each_entry_safe(ts_info, ts_info2, &priv->gwca.ts_info_list, list) { 936 if (!(ts_info->port == port && ts_info->tag == tag)) 937 continue; 938 939 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 940 ts.tv_sec = __le32_to_cpu(desc->ts_sec); 941 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); 942 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 943 skb_tstamp_tx(ts_info->skb, &shhwtstamps); 944 dev_consume_skb_irq(ts_info->skb); 945 list_del(&ts_info->list); 946 kfree(ts_info); 947 break; 948 } 949 950 gq->cur = rswitch_next_queue_index(gq, true, 1); 951 desc = &gq->ts_ring[gq->cur]; 952 } 953 954 num = rswitch_get_num_cur_queues(gq); 955 rswitch_gwca_ts_queue_fill(priv, gq->dirty, num); 956 gq->dirty = rswitch_next_queue_index(gq, false, num); 957 } 958 959 static irqreturn_t rswitch_gwca_ts_irq(int irq, void *dev_id) 960 { 961 struct rswitch_private *priv = dev_id; 962 963 if (ioread32(priv->addr + GWTSDIS) & GWCA_TS_IRQ_BIT) { 964 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDIS); 965 rswitch_ts(priv); 966 967 return IRQ_HANDLED; 968 } 969 970 return IRQ_NONE; 971 } 972 973 static int rswitch_gwca_ts_request_irqs(struct rswitch_private *priv) 974 { 975 int irq; 976 977 irq = platform_get_irq_byname(priv->pdev, GWCA_TS_IRQ_RESOURCE_NAME); 978 if (irq < 0) 979 return irq; 980 981 return devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_ts_irq, 982 0, GWCA_TS_IRQ_NAME, priv); 983 } 984 985 /* Ethernet TSN Agent block (ETHA) and Ethernet MAC IP block (RMAC) */ 986 static int rswitch_etha_change_mode(struct rswitch_etha *etha, 987 enum rswitch_etha_mode mode) 988 { 989 int ret; 990 991 if (!rswitch_agent_clock_is_enabled(etha->coma_addr, etha->index)) 992 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 1); 993 994 iowrite32(mode, etha->addr + EAMC); 995 996 ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode); 997 998 if (mode == EAMC_OPC_DISABLE) 999 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 0); 1000 1001 return ret; 1002 } 1003 1004 static void rswitch_etha_read_mac_address(struct rswitch_etha *etha) 1005 { 1006 u32 mrmac0 = ioread32(etha->addr + MRMAC0); 1007 u32 mrmac1 = ioread32(etha->addr + MRMAC1); 1008 u8 *mac = ða->mac_addr[0]; 1009 1010 mac[0] = (mrmac0 >> 8) & 0xFF; 1011 mac[1] = (mrmac0 >> 0) & 0xFF; 1012 mac[2] = (mrmac1 >> 24) & 0xFF; 1013 mac[3] = (mrmac1 >> 16) & 0xFF; 1014 mac[4] = (mrmac1 >> 8) & 0xFF; 1015 mac[5] = (mrmac1 >> 0) & 0xFF; 1016 } 1017 1018 static void rswitch_etha_write_mac_address(struct rswitch_etha *etha, const u8 *mac) 1019 { 1020 iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0); 1021 iowrite32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], 1022 etha->addr + MRMAC1); 1023 } 1024 1025 static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha) 1026 { 1027 iowrite32(MLVC_PLV, etha->addr + MLVC); 1028 1029 return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0); 1030 } 1031 1032 static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac) 1033 { 1034 u32 val; 1035 1036 rswitch_etha_write_mac_address(etha, mac); 1037 1038 switch (etha->speed) { 1039 case 100: 1040 val = MPIC_LSC_100M; 1041 break; 1042 case 1000: 1043 val = MPIC_LSC_1G; 1044 break; 1045 case 2500: 1046 val = MPIC_LSC_2_5G; 1047 break; 1048 default: 1049 return; 1050 } 1051 1052 iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC); 1053 } 1054 1055 static void rswitch_etha_enable_mii(struct rswitch_etha *etha) 1056 { 1057 rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, 1058 MPIC_PSMCS(0x05) | MPIC_PSMHT(0x06)); 1059 rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45); 1060 } 1061 1062 static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac) 1063 { 1064 int err; 1065 1066 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 1067 if (err < 0) 1068 return err; 1069 err = rswitch_etha_change_mode(etha, EAMC_OPC_CONFIG); 1070 if (err < 0) 1071 return err; 1072 1073 iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC); 1074 rswitch_rmac_setting(etha, mac); 1075 rswitch_etha_enable_mii(etha); 1076 1077 err = rswitch_etha_wait_link_verification(etha); 1078 if (err < 0) 1079 return err; 1080 1081 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 1082 if (err < 0) 1083 return err; 1084 1085 return rswitch_etha_change_mode(etha, EAMC_OPC_OPERATION); 1086 } 1087 1088 static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read, 1089 int phyad, int devad, int regad, int data) 1090 { 1091 int pop = read ? MDIO_READ_C45 : MDIO_WRITE_C45; 1092 u32 val; 1093 int ret; 1094 1095 if (devad == 0xffffffff) 1096 return -ENODEV; 1097 1098 writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); 1099 1100 val = MPSM_PSME | MPSM_MFF_C45; 1101 iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 1102 1103 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1104 if (ret) 1105 return ret; 1106 1107 rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1108 1109 if (read) { 1110 writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 1111 1112 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1113 if (ret) 1114 return ret; 1115 1116 ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; 1117 1118 rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1119 } else { 1120 iowrite32((data << 16) | (pop << 13) | (devad << 8) | (phyad << 3) | val, 1121 etha->addr + MPSM); 1122 1123 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS); 1124 } 1125 1126 return ret; 1127 } 1128 1129 static int rswitch_etha_mii_read_c45(struct mii_bus *bus, int addr, int devad, 1130 int regad) 1131 { 1132 struct rswitch_etha *etha = bus->priv; 1133 1134 return rswitch_etha_set_access(etha, true, addr, devad, regad, 0); 1135 } 1136 1137 static int rswitch_etha_mii_write_c45(struct mii_bus *bus, int addr, int devad, 1138 int regad, u16 val) 1139 { 1140 struct rswitch_etha *etha = bus->priv; 1141 1142 return rswitch_etha_set_access(etha, false, addr, devad, regad, val); 1143 } 1144 1145 /* Call of_node_put(port) after done */ 1146 static struct device_node *rswitch_get_port_node(struct rswitch_device *rdev) 1147 { 1148 struct device_node *ports, *port; 1149 int err = 0; 1150 u32 index; 1151 1152 ports = of_get_child_by_name(rdev->ndev->dev.parent->of_node, 1153 "ethernet-ports"); 1154 if (!ports) 1155 return NULL; 1156 1157 for_each_child_of_node(ports, port) { 1158 err = of_property_read_u32(port, "reg", &index); 1159 if (err < 0) { 1160 port = NULL; 1161 goto out; 1162 } 1163 if (index == rdev->etha->index) { 1164 if (!of_device_is_available(port)) 1165 port = NULL; 1166 break; 1167 } 1168 } 1169 1170 out: 1171 of_node_put(ports); 1172 1173 return port; 1174 } 1175 1176 static int rswitch_etha_get_params(struct rswitch_device *rdev) 1177 { 1178 u32 max_speed; 1179 int err; 1180 1181 if (!rdev->np_port) 1182 return 0; /* ignored */ 1183 1184 err = of_get_phy_mode(rdev->np_port, &rdev->etha->phy_interface); 1185 if (err) 1186 return err; 1187 1188 err = of_property_read_u32(rdev->np_port, "max-speed", &max_speed); 1189 if (!err) { 1190 rdev->etha->speed = max_speed; 1191 return 0; 1192 } 1193 1194 /* if no "max-speed" property, let's use default speed */ 1195 switch (rdev->etha->phy_interface) { 1196 case PHY_INTERFACE_MODE_MII: 1197 rdev->etha->speed = SPEED_100; 1198 break; 1199 case PHY_INTERFACE_MODE_SGMII: 1200 rdev->etha->speed = SPEED_1000; 1201 break; 1202 case PHY_INTERFACE_MODE_USXGMII: 1203 rdev->etha->speed = SPEED_2500; 1204 break; 1205 default: 1206 return -EINVAL; 1207 } 1208 1209 return 0; 1210 } 1211 1212 static int rswitch_mii_register(struct rswitch_device *rdev) 1213 { 1214 struct device_node *mdio_np; 1215 struct mii_bus *mii_bus; 1216 int err; 1217 1218 mii_bus = mdiobus_alloc(); 1219 if (!mii_bus) 1220 return -ENOMEM; 1221 1222 mii_bus->name = "rswitch_mii"; 1223 sprintf(mii_bus->id, "etha%d", rdev->etha->index); 1224 mii_bus->priv = rdev->etha; 1225 mii_bus->read_c45 = rswitch_etha_mii_read_c45; 1226 mii_bus->write_c45 = rswitch_etha_mii_write_c45; 1227 mii_bus->parent = &rdev->priv->pdev->dev; 1228 1229 mdio_np = of_get_child_by_name(rdev->np_port, "mdio"); 1230 err = of_mdiobus_register(mii_bus, mdio_np); 1231 if (err < 0) { 1232 mdiobus_free(mii_bus); 1233 goto out; 1234 } 1235 1236 rdev->etha->mii = mii_bus; 1237 1238 out: 1239 of_node_put(mdio_np); 1240 1241 return err; 1242 } 1243 1244 static void rswitch_mii_unregister(struct rswitch_device *rdev) 1245 { 1246 if (rdev->etha->mii) { 1247 mdiobus_unregister(rdev->etha->mii); 1248 mdiobus_free(rdev->etha->mii); 1249 rdev->etha->mii = NULL; 1250 } 1251 } 1252 1253 static void rswitch_adjust_link(struct net_device *ndev) 1254 { 1255 struct rswitch_device *rdev = netdev_priv(ndev); 1256 struct phy_device *phydev = ndev->phydev; 1257 1258 /* Current hardware has a restriction not to change speed at runtime */ 1259 if (phydev->link != rdev->etha->link) { 1260 phy_print_status(phydev); 1261 if (phydev->link) 1262 phy_power_on(rdev->serdes); 1263 else 1264 phy_power_off(rdev->serdes); 1265 1266 rdev->etha->link = phydev->link; 1267 } 1268 } 1269 1270 static void rswitch_phy_remove_link_mode(struct rswitch_device *rdev, 1271 struct phy_device *phydev) 1272 { 1273 /* Current hardware has a restriction not to change speed at runtime */ 1274 switch (rdev->etha->speed) { 1275 case SPEED_2500: 1276 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1277 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1278 break; 1279 case SPEED_1000: 1280 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1281 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1282 break; 1283 case SPEED_100: 1284 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1285 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1286 break; 1287 default: 1288 break; 1289 } 1290 1291 phy_set_max_speed(phydev, rdev->etha->speed); 1292 } 1293 1294 static int rswitch_phy_device_init(struct rswitch_device *rdev) 1295 { 1296 struct phy_device *phydev; 1297 struct device_node *phy; 1298 int err = -ENOENT; 1299 1300 if (!rdev->np_port) 1301 return -ENODEV; 1302 1303 phy = of_parse_phandle(rdev->np_port, "phy-handle", 0); 1304 if (!phy) 1305 return -ENODEV; 1306 1307 /* Set phydev->host_interfaces before calling of_phy_connect() to 1308 * configure the PHY with the information of host_interfaces. 1309 */ 1310 phydev = of_phy_find_device(phy); 1311 if (!phydev) 1312 goto out; 1313 __set_bit(rdev->etha->phy_interface, phydev->host_interfaces); 1314 1315 phydev = of_phy_connect(rdev->ndev, phy, rswitch_adjust_link, 0, 1316 rdev->etha->phy_interface); 1317 if (!phydev) 1318 goto out; 1319 1320 phy_set_max_speed(phydev, SPEED_2500); 1321 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1322 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1323 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1324 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1325 rswitch_phy_remove_link_mode(rdev, phydev); 1326 1327 phy_attached_info(phydev); 1328 1329 err = 0; 1330 out: 1331 of_node_put(phy); 1332 1333 return err; 1334 } 1335 1336 static void rswitch_phy_device_deinit(struct rswitch_device *rdev) 1337 { 1338 if (rdev->ndev->phydev) 1339 phy_disconnect(rdev->ndev->phydev); 1340 } 1341 1342 static int rswitch_serdes_set_params(struct rswitch_device *rdev) 1343 { 1344 int err; 1345 1346 err = phy_set_mode_ext(rdev->serdes, PHY_MODE_ETHERNET, 1347 rdev->etha->phy_interface); 1348 if (err < 0) 1349 return err; 1350 1351 return phy_set_speed(rdev->serdes, rdev->etha->speed); 1352 } 1353 1354 static int rswitch_ether_port_init_one(struct rswitch_device *rdev) 1355 { 1356 int err; 1357 1358 if (!rdev->etha->operated) { 1359 err = rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr); 1360 if (err < 0) 1361 return err; 1362 rdev->etha->operated = true; 1363 } 1364 1365 err = rswitch_mii_register(rdev); 1366 if (err < 0) 1367 return err; 1368 1369 err = rswitch_phy_device_init(rdev); 1370 if (err < 0) 1371 goto err_phy_device_init; 1372 1373 rdev->serdes = devm_of_phy_get(&rdev->priv->pdev->dev, rdev->np_port, NULL); 1374 if (IS_ERR(rdev->serdes)) { 1375 err = PTR_ERR(rdev->serdes); 1376 goto err_serdes_phy_get; 1377 } 1378 1379 err = rswitch_serdes_set_params(rdev); 1380 if (err < 0) 1381 goto err_serdes_set_params; 1382 1383 return 0; 1384 1385 err_serdes_set_params: 1386 err_serdes_phy_get: 1387 rswitch_phy_device_deinit(rdev); 1388 1389 err_phy_device_init: 1390 rswitch_mii_unregister(rdev); 1391 1392 return err; 1393 } 1394 1395 static void rswitch_ether_port_deinit_one(struct rswitch_device *rdev) 1396 { 1397 rswitch_phy_device_deinit(rdev); 1398 rswitch_mii_unregister(rdev); 1399 } 1400 1401 static int rswitch_ether_port_init_all(struct rswitch_private *priv) 1402 { 1403 int i, err; 1404 1405 rswitch_for_each_enabled_port(priv, i) { 1406 err = rswitch_ether_port_init_one(priv->rdev[i]); 1407 if (err) 1408 goto err_init_one; 1409 } 1410 1411 rswitch_for_each_enabled_port(priv, i) { 1412 err = phy_init(priv->rdev[i]->serdes); 1413 if (err) 1414 goto err_serdes; 1415 } 1416 1417 return 0; 1418 1419 err_serdes: 1420 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1421 phy_exit(priv->rdev[i]->serdes); 1422 i = RSWITCH_NUM_PORTS; 1423 1424 err_init_one: 1425 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1426 rswitch_ether_port_deinit_one(priv->rdev[i]); 1427 1428 return err; 1429 } 1430 1431 static void rswitch_ether_port_deinit_all(struct rswitch_private *priv) 1432 { 1433 int i; 1434 1435 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1436 phy_exit(priv->rdev[i]->serdes); 1437 rswitch_ether_port_deinit_one(priv->rdev[i]); 1438 } 1439 } 1440 1441 static int rswitch_open(struct net_device *ndev) 1442 { 1443 struct rswitch_device *rdev = netdev_priv(ndev); 1444 1445 phy_start(ndev->phydev); 1446 1447 napi_enable(&rdev->napi); 1448 netif_start_queue(ndev); 1449 1450 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, true); 1451 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, true); 1452 1453 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) 1454 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDIE); 1455 1456 bitmap_set(rdev->priv->opened_ports, rdev->port, 1); 1457 1458 return 0; 1459 }; 1460 1461 static int rswitch_stop(struct net_device *ndev) 1462 { 1463 struct rswitch_device *rdev = netdev_priv(ndev); 1464 struct rswitch_gwca_ts_info *ts_info, *ts_info2; 1465 1466 netif_tx_stop_all_queues(ndev); 1467 bitmap_clear(rdev->priv->opened_ports, rdev->port, 1); 1468 1469 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) 1470 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDID); 1471 1472 list_for_each_entry_safe(ts_info, ts_info2, &rdev->priv->gwca.ts_info_list, list) { 1473 if (ts_info->port != rdev->port) 1474 continue; 1475 dev_kfree_skb_irq(ts_info->skb); 1476 list_del(&ts_info->list); 1477 kfree(ts_info); 1478 } 1479 1480 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 1481 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 1482 1483 phy_stop(ndev->phydev); 1484 napi_disable(&rdev->napi); 1485 1486 return 0; 1487 }; 1488 1489 static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1490 { 1491 struct rswitch_device *rdev = netdev_priv(ndev); 1492 struct rswitch_gwca_queue *gq = rdev->tx_queue; 1493 struct rswitch_ext_desc *desc; 1494 int ret = NETDEV_TX_OK; 1495 dma_addr_t dma_addr; 1496 1497 if (rswitch_get_num_cur_queues(gq) >= gq->ring_size - 1) { 1498 netif_stop_subqueue(ndev, 0); 1499 return NETDEV_TX_BUSY; 1500 } 1501 1502 if (skb_put_padto(skb, ETH_ZLEN)) 1503 return ret; 1504 1505 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, DMA_TO_DEVICE); 1506 if (dma_mapping_error(ndev->dev.parent, dma_addr)) { 1507 dev_kfree_skb_any(skb); 1508 return ret; 1509 } 1510 1511 gq->skbs[gq->cur] = skb; 1512 desc = &gq->tx_ring[gq->cur]; 1513 rswitch_desc_set_dptr(&desc->desc, dma_addr); 1514 desc->desc.info_ds = cpu_to_le16(skb->len); 1515 1516 desc->info1 = cpu_to_le64(INFO1_DV(BIT(rdev->etha->index)) | INFO1_FMT); 1517 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 1518 struct rswitch_gwca_ts_info *ts_info; 1519 1520 ts_info = kzalloc(sizeof(*ts_info), GFP_ATOMIC); 1521 if (!ts_info) { 1522 dma_unmap_single(ndev->dev.parent, dma_addr, skb->len, DMA_TO_DEVICE); 1523 return -ENOMEM; 1524 } 1525 1526 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1527 rdev->ts_tag++; 1528 desc->info1 |= cpu_to_le64(INFO1_TSUN(rdev->ts_tag) | INFO1_TXC); 1529 1530 ts_info->skb = skb_get(skb); 1531 ts_info->port = rdev->port; 1532 ts_info->tag = rdev->ts_tag; 1533 list_add_tail(&ts_info->list, &rdev->priv->gwca.ts_info_list); 1534 1535 skb_tx_timestamp(skb); 1536 } 1537 1538 dma_wmb(); 1539 1540 desc->desc.die_dt = DT_FSINGLE | DIE; 1541 wmb(); /* gq->cur must be incremented after die_dt was set */ 1542 1543 gq->cur = rswitch_next_queue_index(gq, true, 1); 1544 rswitch_modify(rdev->addr, GWTRC(gq->index), 0, BIT(gq->index % 32)); 1545 1546 return ret; 1547 } 1548 1549 static struct net_device_stats *rswitch_get_stats(struct net_device *ndev) 1550 { 1551 return &ndev->stats; 1552 } 1553 1554 static int rswitch_hwstamp_get(struct net_device *ndev, struct ifreq *req) 1555 { 1556 struct rswitch_device *rdev = netdev_priv(ndev); 1557 struct rcar_gen4_ptp_private *ptp_priv; 1558 struct hwtstamp_config config; 1559 1560 ptp_priv = rdev->priv->ptp_priv; 1561 1562 config.flags = 0; 1563 config.tx_type = ptp_priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1564 HWTSTAMP_TX_OFF; 1565 switch (ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE) { 1566 case RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT: 1567 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1568 break; 1569 case RCAR_GEN4_RXTSTAMP_TYPE_ALL: 1570 config.rx_filter = HWTSTAMP_FILTER_ALL; 1571 break; 1572 default: 1573 config.rx_filter = HWTSTAMP_FILTER_NONE; 1574 break; 1575 } 1576 1577 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1578 } 1579 1580 static int rswitch_hwstamp_set(struct net_device *ndev, struct ifreq *req) 1581 { 1582 struct rswitch_device *rdev = netdev_priv(ndev); 1583 u32 tstamp_rx_ctrl = RCAR_GEN4_RXTSTAMP_ENABLED; 1584 struct hwtstamp_config config; 1585 u32 tstamp_tx_ctrl; 1586 1587 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1588 return -EFAULT; 1589 1590 if (config.flags) 1591 return -EINVAL; 1592 1593 switch (config.tx_type) { 1594 case HWTSTAMP_TX_OFF: 1595 tstamp_tx_ctrl = 0; 1596 break; 1597 case HWTSTAMP_TX_ON: 1598 tstamp_tx_ctrl = RCAR_GEN4_TXTSTAMP_ENABLED; 1599 break; 1600 default: 1601 return -ERANGE; 1602 } 1603 1604 switch (config.rx_filter) { 1605 case HWTSTAMP_FILTER_NONE: 1606 tstamp_rx_ctrl = 0; 1607 break; 1608 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1609 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 1610 break; 1611 default: 1612 config.rx_filter = HWTSTAMP_FILTER_ALL; 1613 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_ALL; 1614 break; 1615 } 1616 1617 rdev->priv->ptp_priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1618 rdev->priv->ptp_priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1619 1620 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1621 } 1622 1623 static int rswitch_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1624 { 1625 if (!netif_running(ndev)) 1626 return -EINVAL; 1627 1628 switch (cmd) { 1629 case SIOCGHWTSTAMP: 1630 return rswitch_hwstamp_get(ndev, req); 1631 case SIOCSHWTSTAMP: 1632 return rswitch_hwstamp_set(ndev, req); 1633 default: 1634 return phy_mii_ioctl(ndev->phydev, req, cmd); 1635 } 1636 } 1637 1638 static const struct net_device_ops rswitch_netdev_ops = { 1639 .ndo_open = rswitch_open, 1640 .ndo_stop = rswitch_stop, 1641 .ndo_start_xmit = rswitch_start_xmit, 1642 .ndo_get_stats = rswitch_get_stats, 1643 .ndo_eth_ioctl = rswitch_eth_ioctl, 1644 .ndo_validate_addr = eth_validate_addr, 1645 .ndo_set_mac_address = eth_mac_addr, 1646 }; 1647 1648 static int rswitch_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) 1649 { 1650 struct rswitch_device *rdev = netdev_priv(ndev); 1651 1652 info->phc_index = ptp_clock_index(rdev->priv->ptp_priv->clock); 1653 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1654 SOF_TIMESTAMPING_RX_SOFTWARE | 1655 SOF_TIMESTAMPING_SOFTWARE | 1656 SOF_TIMESTAMPING_TX_HARDWARE | 1657 SOF_TIMESTAMPING_RX_HARDWARE | 1658 SOF_TIMESTAMPING_RAW_HARDWARE; 1659 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); 1660 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1661 1662 return 0; 1663 } 1664 1665 static const struct ethtool_ops rswitch_ethtool_ops = { 1666 .get_ts_info = rswitch_get_ts_info, 1667 }; 1668 1669 static const struct of_device_id renesas_eth_sw_of_table[] = { 1670 { .compatible = "renesas,r8a779f0-ether-switch", }, 1671 { } 1672 }; 1673 MODULE_DEVICE_TABLE(of, renesas_eth_sw_of_table); 1674 1675 static void rswitch_etha_init(struct rswitch_private *priv, int index) 1676 { 1677 struct rswitch_etha *etha = &priv->etha[index]; 1678 1679 memset(etha, 0, sizeof(*etha)); 1680 etha->index = index; 1681 etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE; 1682 etha->coma_addr = priv->addr; 1683 } 1684 1685 static int rswitch_device_alloc(struct rswitch_private *priv, int index) 1686 { 1687 struct platform_device *pdev = priv->pdev; 1688 struct rswitch_device *rdev; 1689 struct net_device *ndev; 1690 int err; 1691 1692 if (index >= RSWITCH_NUM_PORTS) 1693 return -EINVAL; 1694 1695 ndev = alloc_etherdev_mqs(sizeof(struct rswitch_device), 1, 1); 1696 if (!ndev) 1697 return -ENOMEM; 1698 1699 SET_NETDEV_DEV(ndev, &pdev->dev); 1700 ether_setup(ndev); 1701 1702 rdev = netdev_priv(ndev); 1703 rdev->ndev = ndev; 1704 rdev->priv = priv; 1705 priv->rdev[index] = rdev; 1706 rdev->port = index; 1707 rdev->etha = &priv->etha[index]; 1708 rdev->addr = priv->addr; 1709 1710 ndev->base_addr = (unsigned long)rdev->addr; 1711 snprintf(ndev->name, IFNAMSIZ, "tsn%d", index); 1712 ndev->netdev_ops = &rswitch_netdev_ops; 1713 ndev->ethtool_ops = &rswitch_ethtool_ops; 1714 1715 netif_napi_add(ndev, &rdev->napi, rswitch_poll); 1716 1717 rdev->np_port = rswitch_get_port_node(rdev); 1718 rdev->disabled = !rdev->np_port; 1719 err = of_get_ethdev_address(rdev->np_port, ndev); 1720 of_node_put(rdev->np_port); 1721 if (err) { 1722 if (is_valid_ether_addr(rdev->etha->mac_addr)) 1723 eth_hw_addr_set(ndev, rdev->etha->mac_addr); 1724 else 1725 eth_hw_addr_random(ndev); 1726 } 1727 1728 err = rswitch_etha_get_params(rdev); 1729 if (err < 0) 1730 goto out_get_params; 1731 1732 if (rdev->priv->gwca.speed < rdev->etha->speed) 1733 rdev->priv->gwca.speed = rdev->etha->speed; 1734 1735 err = rswitch_rxdmac_alloc(ndev); 1736 if (err < 0) 1737 goto out_rxdmac; 1738 1739 err = rswitch_txdmac_alloc(ndev); 1740 if (err < 0) 1741 goto out_txdmac; 1742 1743 return 0; 1744 1745 out_txdmac: 1746 rswitch_rxdmac_free(ndev); 1747 1748 out_rxdmac: 1749 out_get_params: 1750 netif_napi_del(&rdev->napi); 1751 free_netdev(ndev); 1752 1753 return err; 1754 } 1755 1756 static void rswitch_device_free(struct rswitch_private *priv, int index) 1757 { 1758 struct rswitch_device *rdev = priv->rdev[index]; 1759 struct net_device *ndev = rdev->ndev; 1760 1761 rswitch_txdmac_free(ndev); 1762 rswitch_rxdmac_free(ndev); 1763 netif_napi_del(&rdev->napi); 1764 free_netdev(ndev); 1765 } 1766 1767 static int rswitch_init(struct rswitch_private *priv) 1768 { 1769 int i, err; 1770 1771 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1772 rswitch_etha_init(priv, i); 1773 1774 rswitch_clock_enable(priv); 1775 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1776 rswitch_etha_read_mac_address(&priv->etha[i]); 1777 1778 rswitch_reset(priv); 1779 1780 rswitch_clock_enable(priv); 1781 rswitch_top_init(priv); 1782 err = rswitch_bpool_config(priv); 1783 if (err < 0) 1784 return err; 1785 1786 err = rswitch_gwca_linkfix_alloc(priv); 1787 if (err < 0) 1788 return -ENOMEM; 1789 1790 err = rswitch_gwca_ts_queue_alloc(priv); 1791 if (err < 0) 1792 goto err_ts_queue_alloc; 1793 1794 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1795 err = rswitch_device_alloc(priv, i); 1796 if (err < 0) { 1797 for (i--; i >= 0; i--) 1798 rswitch_device_free(priv, i); 1799 goto err_device_alloc; 1800 } 1801 } 1802 1803 rswitch_fwd_init(priv); 1804 1805 err = rcar_gen4_ptp_register(priv->ptp_priv, RCAR_GEN4_PTP_REG_LAYOUT_S4, 1806 RCAR_GEN4_PTP_CLOCK_S4); 1807 if (err < 0) 1808 goto err_ptp_register; 1809 1810 err = rswitch_gwca_request_irqs(priv); 1811 if (err < 0) 1812 goto err_gwca_request_irq; 1813 1814 err = rswitch_gwca_ts_request_irqs(priv); 1815 if (err < 0) 1816 goto err_gwca_ts_request_irq; 1817 1818 err = rswitch_gwca_hw_init(priv); 1819 if (err < 0) 1820 goto err_gwca_hw_init; 1821 1822 err = rswitch_ether_port_init_all(priv); 1823 if (err) 1824 goto err_ether_port_init_all; 1825 1826 rswitch_for_each_enabled_port(priv, i) { 1827 err = register_netdev(priv->rdev[i]->ndev); 1828 if (err) { 1829 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1830 unregister_netdev(priv->rdev[i]->ndev); 1831 goto err_register_netdev; 1832 } 1833 } 1834 1835 rswitch_for_each_enabled_port(priv, i) 1836 netdev_info(priv->rdev[i]->ndev, "MAC address %pM\n", 1837 priv->rdev[i]->ndev->dev_addr); 1838 1839 return 0; 1840 1841 err_register_netdev: 1842 rswitch_ether_port_deinit_all(priv); 1843 1844 err_ether_port_init_all: 1845 rswitch_gwca_hw_deinit(priv); 1846 1847 err_gwca_hw_init: 1848 err_gwca_ts_request_irq: 1849 err_gwca_request_irq: 1850 rcar_gen4_ptp_unregister(priv->ptp_priv); 1851 1852 err_ptp_register: 1853 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1854 rswitch_device_free(priv, i); 1855 1856 err_device_alloc: 1857 rswitch_gwca_ts_queue_free(priv); 1858 1859 err_ts_queue_alloc: 1860 rswitch_gwca_linkfix_free(priv); 1861 1862 return err; 1863 } 1864 1865 static int renesas_eth_sw_probe(struct platform_device *pdev) 1866 { 1867 struct rswitch_private *priv; 1868 struct resource *res; 1869 int ret; 1870 1871 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "secure_base"); 1872 if (!res) { 1873 dev_err(&pdev->dev, "invalid resource\n"); 1874 return -EINVAL; 1875 } 1876 1877 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1878 if (!priv) 1879 return -ENOMEM; 1880 1881 priv->ptp_priv = rcar_gen4_ptp_alloc(pdev); 1882 if (!priv->ptp_priv) 1883 return -ENOMEM; 1884 1885 platform_set_drvdata(pdev, priv); 1886 priv->pdev = pdev; 1887 priv->addr = devm_ioremap_resource(&pdev->dev, res); 1888 if (IS_ERR(priv->addr)) 1889 return PTR_ERR(priv->addr); 1890 1891 priv->ptp_priv->addr = priv->addr + RCAR_GEN4_GPTP_OFFSET_S4; 1892 1893 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 1894 if (ret < 0) { 1895 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1896 if (ret < 0) 1897 return ret; 1898 } 1899 1900 priv->gwca.index = AGENT_INDEX_GWCA; 1901 priv->gwca.num_queues = min(RSWITCH_NUM_PORTS * NUM_QUEUES_PER_NDEV, 1902 RSWITCH_MAX_NUM_QUEUES); 1903 priv->gwca.queues = devm_kcalloc(&pdev->dev, priv->gwca.num_queues, 1904 sizeof(*priv->gwca.queues), GFP_KERNEL); 1905 if (!priv->gwca.queues) 1906 return -ENOMEM; 1907 1908 pm_runtime_enable(&pdev->dev); 1909 pm_runtime_get_sync(&pdev->dev); 1910 1911 ret = rswitch_init(priv); 1912 if (ret < 0) { 1913 pm_runtime_put(&pdev->dev); 1914 pm_runtime_disable(&pdev->dev); 1915 return ret; 1916 } 1917 1918 device_set_wakeup_capable(&pdev->dev, 1); 1919 1920 return ret; 1921 } 1922 1923 static void rswitch_deinit(struct rswitch_private *priv) 1924 { 1925 int i; 1926 1927 rswitch_gwca_hw_deinit(priv); 1928 rcar_gen4_ptp_unregister(priv->ptp_priv); 1929 1930 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1931 struct rswitch_device *rdev = priv->rdev[i]; 1932 1933 phy_exit(priv->rdev[i]->serdes); 1934 rswitch_ether_port_deinit_one(rdev); 1935 unregister_netdev(rdev->ndev); 1936 rswitch_device_free(priv, i); 1937 } 1938 1939 rswitch_gwca_ts_queue_free(priv); 1940 rswitch_gwca_linkfix_free(priv); 1941 1942 rswitch_clock_disable(priv); 1943 } 1944 1945 static int renesas_eth_sw_remove(struct platform_device *pdev) 1946 { 1947 struct rswitch_private *priv = platform_get_drvdata(pdev); 1948 1949 rswitch_deinit(priv); 1950 1951 pm_runtime_put(&pdev->dev); 1952 pm_runtime_disable(&pdev->dev); 1953 1954 platform_set_drvdata(pdev, NULL); 1955 1956 return 0; 1957 } 1958 1959 static struct platform_driver renesas_eth_sw_driver_platform = { 1960 .probe = renesas_eth_sw_probe, 1961 .remove = renesas_eth_sw_remove, 1962 .driver = { 1963 .name = "renesas_eth_sw", 1964 .of_match_table = renesas_eth_sw_of_table, 1965 } 1966 }; 1967 module_platform_driver(renesas_eth_sw_driver_platform); 1968 MODULE_AUTHOR("Yoshihiro Shimoda"); 1969 MODULE_DESCRIPTION("Renesas Ethernet Switch device driver"); 1970 MODULE_LICENSE("GPL"); 1971