1 /* Renesas Ethernet AVB device driver 2 * 3 * Copyright (C) 2014-2015 Renesas Electronics Corporation 4 * Copyright (C) 2015 Renesas Solutions Corp. 5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 6 * 7 * Based on the SuperH Ethernet driver 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License version 2, 11 * as published by the Free Software Foundation. 12 */ 13 14 #include <linux/cache.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/err.h> 19 #include <linux/etherdevice.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/kernel.h> 23 #include <linux/list.h> 24 #include <linux/module.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_mdio.h> 30 #include <linux/of_net.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/slab.h> 33 #include <linux/spinlock.h> 34 #include <linux/sys_soc.h> 35 36 #include <asm/div64.h> 37 38 #include "ravb.h" 39 40 #define RAVB_DEF_MSG_ENABLE \ 41 (NETIF_MSG_LINK | \ 42 NETIF_MSG_TIMER | \ 43 NETIF_MSG_RX_ERR | \ 44 NETIF_MSG_TX_ERR) 45 46 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 47 "ch0", /* RAVB_BE */ 48 "ch1", /* RAVB_NC */ 49 }; 50 51 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 52 "ch18", /* RAVB_BE */ 53 "ch19", /* RAVB_NC */ 54 }; 55 56 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 57 u32 set) 58 { 59 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 60 } 61 62 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 63 { 64 int i; 65 66 for (i = 0; i < 10000; i++) { 67 if ((ravb_read(ndev, reg) & mask) == value) 68 return 0; 69 udelay(10); 70 } 71 return -ETIMEDOUT; 72 } 73 74 static int ravb_config(struct net_device *ndev) 75 { 76 int error; 77 78 /* Set config mode */ 79 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 80 /* Check if the operating mode is changed to the config mode */ 81 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 82 if (error) 83 netdev_err(ndev, "failed to switch device to config mode\n"); 84 85 return error; 86 } 87 88 static void ravb_set_duplex(struct net_device *ndev) 89 { 90 struct ravb_private *priv = netdev_priv(ndev); 91 92 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0); 93 } 94 95 static void ravb_set_rate(struct net_device *ndev) 96 { 97 struct ravb_private *priv = netdev_priv(ndev); 98 99 switch (priv->speed) { 100 case 100: /* 100BASE */ 101 ravb_write(ndev, GECMR_SPEED_100, GECMR); 102 break; 103 case 1000: /* 1000BASE */ 104 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 105 break; 106 } 107 } 108 109 static void ravb_set_buffer_align(struct sk_buff *skb) 110 { 111 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 112 113 if (reserve) 114 skb_reserve(skb, RAVB_ALIGN - reserve); 115 } 116 117 /* Get MAC address from the MAC address registers 118 * 119 * Ethernet AVB device doesn't have ROM for MAC address. 120 * This function gets the MAC address that was used by a bootloader. 121 */ 122 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 123 { 124 if (mac) { 125 ether_addr_copy(ndev->dev_addr, mac); 126 } else { 127 u32 mahr = ravb_read(ndev, MAHR); 128 u32 malr = ravb_read(ndev, MALR); 129 130 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 131 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 132 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 133 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 134 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 135 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 136 } 137 } 138 139 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 140 { 141 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 142 mdiobb); 143 144 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 145 } 146 147 /* MDC pin control */ 148 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 149 { 150 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 151 } 152 153 /* Data I/O pin control */ 154 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 155 { 156 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 157 } 158 159 /* Set data bit */ 160 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 161 { 162 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 163 } 164 165 /* Get data bit */ 166 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 167 { 168 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 169 mdiobb); 170 171 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 172 } 173 174 /* MDIO bus control struct */ 175 static struct mdiobb_ops bb_ops = { 176 .owner = THIS_MODULE, 177 .set_mdc = ravb_set_mdc, 178 .set_mdio_dir = ravb_set_mdio_dir, 179 .set_mdio_data = ravb_set_mdio_data, 180 .get_mdio_data = ravb_get_mdio_data, 181 }; 182 183 /* Free TX skb function for AVB-IP */ 184 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 185 { 186 struct ravb_private *priv = netdev_priv(ndev); 187 struct net_device_stats *stats = &priv->stats[q]; 188 struct ravb_tx_desc *desc; 189 int free_num = 0; 190 int entry; 191 u32 size; 192 193 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 194 bool txed; 195 196 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 197 NUM_TX_DESC); 198 desc = &priv->tx_ring[q][entry]; 199 txed = desc->die_dt == DT_FEMPTY; 200 if (free_txed_only && !txed) 201 break; 202 /* Descriptor type must be checked before all other reads */ 203 dma_rmb(); 204 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 205 /* Free the original skb. */ 206 if (priv->tx_skb[q][entry / NUM_TX_DESC]) { 207 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 208 size, DMA_TO_DEVICE); 209 /* Last packet descriptor? */ 210 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { 211 entry /= NUM_TX_DESC; 212 dev_kfree_skb_any(priv->tx_skb[q][entry]); 213 priv->tx_skb[q][entry] = NULL; 214 if (txed) 215 stats->tx_packets++; 216 } 217 free_num++; 218 } 219 if (txed) 220 stats->tx_bytes += size; 221 desc->die_dt = DT_EEMPTY; 222 } 223 return free_num; 224 } 225 226 /* Free skb's and DMA buffers for Ethernet AVB */ 227 static void ravb_ring_free(struct net_device *ndev, int q) 228 { 229 struct ravb_private *priv = netdev_priv(ndev); 230 int ring_size; 231 int i; 232 233 if (priv->rx_ring[q]) { 234 for (i = 0; i < priv->num_rx_ring[q]; i++) { 235 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 236 237 if (!dma_mapping_error(ndev->dev.parent, 238 le32_to_cpu(desc->dptr))) 239 dma_unmap_single(ndev->dev.parent, 240 le32_to_cpu(desc->dptr), 241 priv->rx_buf_sz, 242 DMA_FROM_DEVICE); 243 } 244 ring_size = sizeof(struct ravb_ex_rx_desc) * 245 (priv->num_rx_ring[q] + 1); 246 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 247 priv->rx_desc_dma[q]); 248 priv->rx_ring[q] = NULL; 249 } 250 251 if (priv->tx_ring[q]) { 252 ravb_tx_free(ndev, q, false); 253 254 ring_size = sizeof(struct ravb_tx_desc) * 255 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 256 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 257 priv->tx_desc_dma[q]); 258 priv->tx_ring[q] = NULL; 259 } 260 261 /* Free RX skb ringbuffer */ 262 if (priv->rx_skb[q]) { 263 for (i = 0; i < priv->num_rx_ring[q]; i++) 264 dev_kfree_skb(priv->rx_skb[q][i]); 265 } 266 kfree(priv->rx_skb[q]); 267 priv->rx_skb[q] = NULL; 268 269 /* Free aligned TX buffers */ 270 kfree(priv->tx_align[q]); 271 priv->tx_align[q] = NULL; 272 273 /* Free TX skb ringbuffer. 274 * SKBs are freed by ravb_tx_free() call above. 275 */ 276 kfree(priv->tx_skb[q]); 277 priv->tx_skb[q] = NULL; 278 } 279 280 /* Format skb and descriptor buffer for Ethernet AVB */ 281 static void ravb_ring_format(struct net_device *ndev, int q) 282 { 283 struct ravb_private *priv = netdev_priv(ndev); 284 struct ravb_ex_rx_desc *rx_desc; 285 struct ravb_tx_desc *tx_desc; 286 struct ravb_desc *desc; 287 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 288 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 289 NUM_TX_DESC; 290 dma_addr_t dma_addr; 291 int i; 292 293 priv->cur_rx[q] = 0; 294 priv->cur_tx[q] = 0; 295 priv->dirty_rx[q] = 0; 296 priv->dirty_tx[q] = 0; 297 298 memset(priv->rx_ring[q], 0, rx_ring_size); 299 /* Build RX ring buffer */ 300 for (i = 0; i < priv->num_rx_ring[q]; i++) { 301 /* RX descriptor */ 302 rx_desc = &priv->rx_ring[q][i]; 303 rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 304 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 305 priv->rx_buf_sz, 306 DMA_FROM_DEVICE); 307 /* We just set the data size to 0 for a failed mapping which 308 * should prevent DMA from happening... 309 */ 310 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 311 rx_desc->ds_cc = cpu_to_le16(0); 312 rx_desc->dptr = cpu_to_le32(dma_addr); 313 rx_desc->die_dt = DT_FEMPTY; 314 } 315 rx_desc = &priv->rx_ring[q][i]; 316 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 317 rx_desc->die_dt = DT_LINKFIX; /* type */ 318 319 memset(priv->tx_ring[q], 0, tx_ring_size); 320 /* Build TX ring buffer */ 321 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 322 i++, tx_desc++) { 323 tx_desc->die_dt = DT_EEMPTY; 324 tx_desc++; 325 tx_desc->die_dt = DT_EEMPTY; 326 } 327 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 328 tx_desc->die_dt = DT_LINKFIX; /* type */ 329 330 /* RX descriptor base address for best effort */ 331 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 332 desc->die_dt = DT_LINKFIX; /* type */ 333 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 334 335 /* TX descriptor base address for best effort */ 336 desc = &priv->desc_bat[q]; 337 desc->die_dt = DT_LINKFIX; /* type */ 338 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 339 } 340 341 /* Init skb and descriptor buffer for Ethernet AVB */ 342 static int ravb_ring_init(struct net_device *ndev, int q) 343 { 344 struct ravb_private *priv = netdev_priv(ndev); 345 struct sk_buff *skb; 346 int ring_size; 347 int i; 348 349 priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) + 350 ETH_HLEN + VLAN_HLEN; 351 352 /* Allocate RX and TX skb rings */ 353 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 354 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 355 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 356 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 357 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 358 goto error; 359 360 for (i = 0; i < priv->num_rx_ring[q]; i++) { 361 skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1); 362 if (!skb) 363 goto error; 364 ravb_set_buffer_align(skb); 365 priv->rx_skb[q][i] = skb; 366 } 367 368 /* Allocate rings for the aligned buffers */ 369 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 370 DPTR_ALIGN - 1, GFP_KERNEL); 371 if (!priv->tx_align[q]) 372 goto error; 373 374 /* Allocate all RX descriptors. */ 375 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 376 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 377 &priv->rx_desc_dma[q], 378 GFP_KERNEL); 379 if (!priv->rx_ring[q]) 380 goto error; 381 382 priv->dirty_rx[q] = 0; 383 384 /* Allocate all TX descriptors. */ 385 ring_size = sizeof(struct ravb_tx_desc) * 386 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 387 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 388 &priv->tx_desc_dma[q], 389 GFP_KERNEL); 390 if (!priv->tx_ring[q]) 391 goto error; 392 393 return 0; 394 395 error: 396 ravb_ring_free(ndev, q); 397 398 return -ENOMEM; 399 } 400 401 /* E-MAC init function */ 402 static void ravb_emac_init(struct net_device *ndev) 403 { 404 struct ravb_private *priv = netdev_priv(ndev); 405 406 /* Receive frame limit set register */ 407 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 408 409 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 410 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | 411 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 412 ECMR_TE | ECMR_RE, ECMR); 413 414 ravb_set_rate(ndev); 415 416 /* Set MAC address */ 417 ravb_write(ndev, 418 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 419 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 420 ravb_write(ndev, 421 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 422 423 /* E-MAC status register clear */ 424 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 425 426 /* E-MAC interrupt enable register */ 427 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 428 } 429 430 /* Device init function for Ethernet AVB */ 431 static int ravb_dmac_init(struct net_device *ndev) 432 { 433 struct ravb_private *priv = netdev_priv(ndev); 434 int error; 435 436 /* Set CONFIG mode */ 437 error = ravb_config(ndev); 438 if (error) 439 return error; 440 441 error = ravb_ring_init(ndev, RAVB_BE); 442 if (error) 443 return error; 444 error = ravb_ring_init(ndev, RAVB_NC); 445 if (error) { 446 ravb_ring_free(ndev, RAVB_BE); 447 return error; 448 } 449 450 /* Descriptor format */ 451 ravb_ring_format(ndev, RAVB_BE); 452 ravb_ring_format(ndev, RAVB_NC); 453 454 #if defined(__LITTLE_ENDIAN) 455 ravb_modify(ndev, CCC, CCC_BOC, 0); 456 #else 457 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 458 #endif 459 460 /* Set AVB RX */ 461 ravb_write(ndev, 462 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 463 464 /* Set FIFO size */ 465 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 466 467 /* Timestamp enable */ 468 ravb_write(ndev, TCCR_TFEN, TCCR); 469 470 /* Interrupt init: */ 471 if (priv->chip_id == RCAR_GEN3) { 472 /* Clear DIL.DPLx */ 473 ravb_write(ndev, 0, DIL); 474 /* Set queue specific interrupt */ 475 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 476 } 477 /* Frame receive */ 478 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 479 /* Disable FIFO full warning */ 480 ravb_write(ndev, 0, RIC1); 481 /* Receive FIFO full error, descriptor empty */ 482 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 483 /* Frame transmitted, timestamp FIFO updated */ 484 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 485 486 /* Setting the control will start the AVB-DMAC process. */ 487 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 488 489 return 0; 490 } 491 492 static void ravb_get_tx_tstamp(struct net_device *ndev) 493 { 494 struct ravb_private *priv = netdev_priv(ndev); 495 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 496 struct skb_shared_hwtstamps shhwtstamps; 497 struct sk_buff *skb; 498 struct timespec64 ts; 499 u16 tag, tfa_tag; 500 int count; 501 u32 tfa2; 502 503 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 504 while (count--) { 505 tfa2 = ravb_read(ndev, TFA2); 506 tfa_tag = (tfa2 & TFA2_TST) >> 16; 507 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 508 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 509 ravb_read(ndev, TFA1); 510 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 511 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 512 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 513 list) { 514 skb = ts_skb->skb; 515 tag = ts_skb->tag; 516 list_del(&ts_skb->list); 517 kfree(ts_skb); 518 if (tag == tfa_tag) { 519 skb_tstamp_tx(skb, &shhwtstamps); 520 break; 521 } 522 } 523 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 524 } 525 } 526 527 static void ravb_rx_csum(struct sk_buff *skb) 528 { 529 u8 *hw_csum; 530 531 /* The hardware checksum is 2 bytes appended to packet data */ 532 if (unlikely(skb->len < 2)) 533 return; 534 hw_csum = skb_tail_pointer(skb) - 2; 535 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 536 skb->ip_summed = CHECKSUM_COMPLETE; 537 skb_trim(skb, skb->len - 2); 538 } 539 540 /* Packet receive function for Ethernet AVB */ 541 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 542 { 543 struct ravb_private *priv = netdev_priv(ndev); 544 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 545 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 546 priv->cur_rx[q]; 547 struct net_device_stats *stats = &priv->stats[q]; 548 struct ravb_ex_rx_desc *desc; 549 struct sk_buff *skb; 550 dma_addr_t dma_addr; 551 struct timespec64 ts; 552 u8 desc_status; 553 u16 pkt_len; 554 int limit; 555 556 boguscnt = min(boguscnt, *quota); 557 limit = boguscnt; 558 desc = &priv->rx_ring[q][entry]; 559 while (desc->die_dt != DT_FEMPTY) { 560 /* Descriptor type must be checked before all other reads */ 561 dma_rmb(); 562 desc_status = desc->msc; 563 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 564 565 if (--boguscnt < 0) 566 break; 567 568 /* We use 0-byte descriptors to mark the DMA mapping errors */ 569 if (!pkt_len) 570 continue; 571 572 if (desc_status & MSC_MC) 573 stats->multicast++; 574 575 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 576 MSC_CEEF)) { 577 stats->rx_errors++; 578 if (desc_status & MSC_CRC) 579 stats->rx_crc_errors++; 580 if (desc_status & MSC_RFE) 581 stats->rx_frame_errors++; 582 if (desc_status & (MSC_RTLF | MSC_RTSF)) 583 stats->rx_length_errors++; 584 if (desc_status & MSC_CEEF) 585 stats->rx_missed_errors++; 586 } else { 587 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 588 589 skb = priv->rx_skb[q][entry]; 590 priv->rx_skb[q][entry] = NULL; 591 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 592 priv->rx_buf_sz, 593 DMA_FROM_DEVICE); 594 get_ts &= (q == RAVB_NC) ? 595 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 596 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 597 if (get_ts) { 598 struct skb_shared_hwtstamps *shhwtstamps; 599 600 shhwtstamps = skb_hwtstamps(skb); 601 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 602 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 603 32) | le32_to_cpu(desc->ts_sl); 604 ts.tv_nsec = le32_to_cpu(desc->ts_n); 605 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 606 } 607 608 skb_put(skb, pkt_len); 609 skb->protocol = eth_type_trans(skb, ndev); 610 if (ndev->features & NETIF_F_RXCSUM) 611 ravb_rx_csum(skb); 612 napi_gro_receive(&priv->napi[q], skb); 613 stats->rx_packets++; 614 stats->rx_bytes += pkt_len; 615 } 616 617 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 618 desc = &priv->rx_ring[q][entry]; 619 } 620 621 /* Refill the RX ring buffers. */ 622 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 623 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 624 desc = &priv->rx_ring[q][entry]; 625 desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 626 627 if (!priv->rx_skb[q][entry]) { 628 skb = netdev_alloc_skb(ndev, 629 priv->rx_buf_sz + 630 RAVB_ALIGN - 1); 631 if (!skb) 632 break; /* Better luck next round. */ 633 ravb_set_buffer_align(skb); 634 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 635 le16_to_cpu(desc->ds_cc), 636 DMA_FROM_DEVICE); 637 skb_checksum_none_assert(skb); 638 /* We just set the data size to 0 for a failed mapping 639 * which should prevent DMA from happening... 640 */ 641 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 642 desc->ds_cc = cpu_to_le16(0); 643 desc->dptr = cpu_to_le32(dma_addr); 644 priv->rx_skb[q][entry] = skb; 645 } 646 /* Descriptor type must be set after all the above writes */ 647 dma_wmb(); 648 desc->die_dt = DT_FEMPTY; 649 } 650 651 *quota -= limit - (++boguscnt); 652 653 return boguscnt <= 0; 654 } 655 656 static void ravb_rcv_snd_disable(struct net_device *ndev) 657 { 658 /* Disable TX and RX */ 659 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 660 } 661 662 static void ravb_rcv_snd_enable(struct net_device *ndev) 663 { 664 /* Enable TX and RX */ 665 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 666 } 667 668 /* function for waiting dma process finished */ 669 static int ravb_stop_dma(struct net_device *ndev) 670 { 671 int error; 672 673 /* Wait for stopping the hardware TX process */ 674 error = ravb_wait(ndev, TCCR, 675 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 676 if (error) 677 return error; 678 679 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 680 0); 681 if (error) 682 return error; 683 684 /* Stop the E-MAC's RX/TX processes. */ 685 ravb_rcv_snd_disable(ndev); 686 687 /* Wait for stopping the RX DMA process */ 688 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 689 if (error) 690 return error; 691 692 /* Stop AVB-DMAC process */ 693 return ravb_config(ndev); 694 } 695 696 /* E-MAC interrupt handler */ 697 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 698 { 699 struct ravb_private *priv = netdev_priv(ndev); 700 u32 ecsr, psr; 701 702 ecsr = ravb_read(ndev, ECSR); 703 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 704 705 if (ecsr & ECSR_MPD) 706 pm_wakeup_event(&priv->pdev->dev, 0); 707 if (ecsr & ECSR_ICD) 708 ndev->stats.tx_carrier_errors++; 709 if (ecsr & ECSR_LCHNG) { 710 /* Link changed */ 711 if (priv->no_avb_link) 712 return; 713 psr = ravb_read(ndev, PSR); 714 if (priv->avb_link_active_low) 715 psr ^= PSR_LMON; 716 if (!(psr & PSR_LMON)) { 717 /* DIsable RX and TX */ 718 ravb_rcv_snd_disable(ndev); 719 } else { 720 /* Enable RX and TX */ 721 ravb_rcv_snd_enable(ndev); 722 } 723 } 724 } 725 726 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 727 { 728 struct net_device *ndev = dev_id; 729 struct ravb_private *priv = netdev_priv(ndev); 730 731 spin_lock(&priv->lock); 732 ravb_emac_interrupt_unlocked(ndev); 733 mmiowb(); 734 spin_unlock(&priv->lock); 735 return IRQ_HANDLED; 736 } 737 738 /* Error interrupt handler */ 739 static void ravb_error_interrupt(struct net_device *ndev) 740 { 741 struct ravb_private *priv = netdev_priv(ndev); 742 u32 eis, ris2; 743 744 eis = ravb_read(ndev, EIS); 745 ravb_write(ndev, ~EIS_QFS, EIS); 746 if (eis & EIS_QFS) { 747 ris2 = ravb_read(ndev, RIS2); 748 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); 749 750 /* Receive Descriptor Empty int */ 751 if (ris2 & RIS2_QFF0) 752 priv->stats[RAVB_BE].rx_over_errors++; 753 754 /* Receive Descriptor Empty int */ 755 if (ris2 & RIS2_QFF1) 756 priv->stats[RAVB_NC].rx_over_errors++; 757 758 /* Receive FIFO Overflow int */ 759 if (ris2 & RIS2_RFFF) 760 priv->rx_fifo_errors++; 761 } 762 } 763 764 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 765 { 766 struct ravb_private *priv = netdev_priv(ndev); 767 u32 ris0 = ravb_read(ndev, RIS0); 768 u32 ric0 = ravb_read(ndev, RIC0); 769 u32 tis = ravb_read(ndev, TIS); 770 u32 tic = ravb_read(ndev, TIC); 771 772 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 773 if (napi_schedule_prep(&priv->napi[q])) { 774 /* Mask RX and TX interrupts */ 775 if (priv->chip_id == RCAR_GEN2) { 776 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 777 ravb_write(ndev, tic & ~BIT(q), TIC); 778 } else { 779 ravb_write(ndev, BIT(q), RID0); 780 ravb_write(ndev, BIT(q), TID); 781 } 782 __napi_schedule(&priv->napi[q]); 783 } else { 784 netdev_warn(ndev, 785 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 786 ris0, ric0); 787 netdev_warn(ndev, 788 " tx status 0x%08x, tx mask 0x%08x.\n", 789 tis, tic); 790 } 791 return true; 792 } 793 return false; 794 } 795 796 static bool ravb_timestamp_interrupt(struct net_device *ndev) 797 { 798 u32 tis = ravb_read(ndev, TIS); 799 800 if (tis & TIS_TFUF) { 801 ravb_write(ndev, ~TIS_TFUF, TIS); 802 ravb_get_tx_tstamp(ndev); 803 return true; 804 } 805 return false; 806 } 807 808 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 809 { 810 struct net_device *ndev = dev_id; 811 struct ravb_private *priv = netdev_priv(ndev); 812 irqreturn_t result = IRQ_NONE; 813 u32 iss; 814 815 spin_lock(&priv->lock); 816 /* Get interrupt status */ 817 iss = ravb_read(ndev, ISS); 818 819 /* Received and transmitted interrupts */ 820 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 821 int q; 822 823 /* Timestamp updated */ 824 if (ravb_timestamp_interrupt(ndev)) 825 result = IRQ_HANDLED; 826 827 /* Network control and best effort queue RX/TX */ 828 for (q = RAVB_NC; q >= RAVB_BE; q--) { 829 if (ravb_queue_interrupt(ndev, q)) 830 result = IRQ_HANDLED; 831 } 832 } 833 834 /* E-MAC status summary */ 835 if (iss & ISS_MS) { 836 ravb_emac_interrupt_unlocked(ndev); 837 result = IRQ_HANDLED; 838 } 839 840 /* Error status summary */ 841 if (iss & ISS_ES) { 842 ravb_error_interrupt(ndev); 843 result = IRQ_HANDLED; 844 } 845 846 /* gPTP interrupt status summary */ 847 if (iss & ISS_CGIS) { 848 ravb_ptp_interrupt(ndev); 849 result = IRQ_HANDLED; 850 } 851 852 mmiowb(); 853 spin_unlock(&priv->lock); 854 return result; 855 } 856 857 /* Timestamp/Error/gPTP interrupt handler */ 858 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 859 { 860 struct net_device *ndev = dev_id; 861 struct ravb_private *priv = netdev_priv(ndev); 862 irqreturn_t result = IRQ_NONE; 863 u32 iss; 864 865 spin_lock(&priv->lock); 866 /* Get interrupt status */ 867 iss = ravb_read(ndev, ISS); 868 869 /* Timestamp updated */ 870 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 871 result = IRQ_HANDLED; 872 873 /* Error status summary */ 874 if (iss & ISS_ES) { 875 ravb_error_interrupt(ndev); 876 result = IRQ_HANDLED; 877 } 878 879 /* gPTP interrupt status summary */ 880 if (iss & ISS_CGIS) { 881 ravb_ptp_interrupt(ndev); 882 result = IRQ_HANDLED; 883 } 884 885 mmiowb(); 886 spin_unlock(&priv->lock); 887 return result; 888 } 889 890 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 891 { 892 struct net_device *ndev = dev_id; 893 struct ravb_private *priv = netdev_priv(ndev); 894 irqreturn_t result = IRQ_NONE; 895 896 spin_lock(&priv->lock); 897 898 /* Network control/Best effort queue RX/TX */ 899 if (ravb_queue_interrupt(ndev, q)) 900 result = IRQ_HANDLED; 901 902 mmiowb(); 903 spin_unlock(&priv->lock); 904 return result; 905 } 906 907 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 908 { 909 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 910 } 911 912 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 913 { 914 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 915 } 916 917 static int ravb_poll(struct napi_struct *napi, int budget) 918 { 919 struct net_device *ndev = napi->dev; 920 struct ravb_private *priv = netdev_priv(ndev); 921 unsigned long flags; 922 int q = napi - priv->napi; 923 int mask = BIT(q); 924 int quota = budget; 925 u32 ris0, tis; 926 927 for (;;) { 928 tis = ravb_read(ndev, TIS); 929 ris0 = ravb_read(ndev, RIS0); 930 if (!((ris0 & mask) || (tis & mask))) 931 break; 932 933 /* Processing RX Descriptor Ring */ 934 if (ris0 & mask) { 935 /* Clear RX interrupt */ 936 ravb_write(ndev, ~mask, RIS0); 937 if (ravb_rx(ndev, "a, q)) 938 goto out; 939 } 940 /* Processing TX Descriptor Ring */ 941 if (tis & mask) { 942 spin_lock_irqsave(&priv->lock, flags); 943 /* Clear TX interrupt */ 944 ravb_write(ndev, ~mask, TIS); 945 ravb_tx_free(ndev, q, true); 946 netif_wake_subqueue(ndev, q); 947 mmiowb(); 948 spin_unlock_irqrestore(&priv->lock, flags); 949 } 950 } 951 952 napi_complete(napi); 953 954 /* Re-enable RX/TX interrupts */ 955 spin_lock_irqsave(&priv->lock, flags); 956 if (priv->chip_id == RCAR_GEN2) { 957 ravb_modify(ndev, RIC0, mask, mask); 958 ravb_modify(ndev, TIC, mask, mask); 959 } else { 960 ravb_write(ndev, mask, RIE0); 961 ravb_write(ndev, mask, TIE); 962 } 963 mmiowb(); 964 spin_unlock_irqrestore(&priv->lock, flags); 965 966 /* Receive error message handling */ 967 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 968 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 969 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 970 ndev->stats.rx_over_errors = priv->rx_over_errors; 971 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 972 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 973 out: 974 return budget - quota; 975 } 976 977 /* PHY state control function */ 978 static void ravb_adjust_link(struct net_device *ndev) 979 { 980 struct ravb_private *priv = netdev_priv(ndev); 981 struct phy_device *phydev = ndev->phydev; 982 bool new_state = false; 983 unsigned long flags; 984 985 spin_lock_irqsave(&priv->lock, flags); 986 987 /* Disable TX and RX right over here, if E-MAC change is ignored */ 988 if (priv->no_avb_link) 989 ravb_rcv_snd_disable(ndev); 990 991 if (phydev->link) { 992 if (phydev->duplex != priv->duplex) { 993 new_state = true; 994 priv->duplex = phydev->duplex; 995 ravb_set_duplex(ndev); 996 } 997 998 if (phydev->speed != priv->speed) { 999 new_state = true; 1000 priv->speed = phydev->speed; 1001 ravb_set_rate(ndev); 1002 } 1003 if (!priv->link) { 1004 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1005 new_state = true; 1006 priv->link = phydev->link; 1007 } 1008 } else if (priv->link) { 1009 new_state = true; 1010 priv->link = 0; 1011 priv->speed = 0; 1012 priv->duplex = -1; 1013 } 1014 1015 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1016 if (priv->no_avb_link && phydev->link) 1017 ravb_rcv_snd_enable(ndev); 1018 1019 mmiowb(); 1020 spin_unlock_irqrestore(&priv->lock, flags); 1021 1022 if (new_state && netif_msg_link(priv)) 1023 phy_print_status(phydev); 1024 } 1025 1026 static const struct soc_device_attribute r8a7795es10[] = { 1027 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1028 { /* sentinel */ } 1029 }; 1030 1031 /* PHY init function */ 1032 static int ravb_phy_init(struct net_device *ndev) 1033 { 1034 struct device_node *np = ndev->dev.parent->of_node; 1035 struct ravb_private *priv = netdev_priv(ndev); 1036 struct phy_device *phydev; 1037 struct device_node *pn; 1038 int err; 1039 1040 priv->link = 0; 1041 priv->speed = 0; 1042 priv->duplex = -1; 1043 1044 /* Try connecting to PHY */ 1045 pn = of_parse_phandle(np, "phy-handle", 0); 1046 if (!pn) { 1047 /* In the case of a fixed PHY, the DT node associated 1048 * to the PHY is the Ethernet MAC DT node. 1049 */ 1050 if (of_phy_is_fixed_link(np)) { 1051 err = of_phy_register_fixed_link(np); 1052 if (err) 1053 return err; 1054 } 1055 pn = of_node_get(np); 1056 } 1057 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1058 priv->phy_interface); 1059 of_node_put(pn); 1060 if (!phydev) { 1061 netdev_err(ndev, "failed to connect PHY\n"); 1062 err = -ENOENT; 1063 goto err_deregister_fixed_link; 1064 } 1065 1066 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1067 * at this time. 1068 */ 1069 if (soc_device_match(r8a7795es10)) { 1070 err = phy_set_max_speed(phydev, SPEED_100); 1071 if (err) { 1072 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1073 goto err_phy_disconnect; 1074 } 1075 1076 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1077 } 1078 1079 /* 10BASE is not supported */ 1080 phydev->supported &= ~PHY_10BT_FEATURES; 1081 1082 phy_attached_info(phydev); 1083 1084 return 0; 1085 1086 err_phy_disconnect: 1087 phy_disconnect(phydev); 1088 err_deregister_fixed_link: 1089 if (of_phy_is_fixed_link(np)) 1090 of_phy_deregister_fixed_link(np); 1091 1092 return err; 1093 } 1094 1095 /* PHY control start function */ 1096 static int ravb_phy_start(struct net_device *ndev) 1097 { 1098 int error; 1099 1100 error = ravb_phy_init(ndev); 1101 if (error) 1102 return error; 1103 1104 phy_start(ndev->phydev); 1105 1106 return 0; 1107 } 1108 1109 static u32 ravb_get_msglevel(struct net_device *ndev) 1110 { 1111 struct ravb_private *priv = netdev_priv(ndev); 1112 1113 return priv->msg_enable; 1114 } 1115 1116 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1117 { 1118 struct ravb_private *priv = netdev_priv(ndev); 1119 1120 priv->msg_enable = value; 1121 } 1122 1123 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1124 "rx_queue_0_current", 1125 "tx_queue_0_current", 1126 "rx_queue_0_dirty", 1127 "tx_queue_0_dirty", 1128 "rx_queue_0_packets", 1129 "tx_queue_0_packets", 1130 "rx_queue_0_bytes", 1131 "tx_queue_0_bytes", 1132 "rx_queue_0_mcast_packets", 1133 "rx_queue_0_errors", 1134 "rx_queue_0_crc_errors", 1135 "rx_queue_0_frame_errors", 1136 "rx_queue_0_length_errors", 1137 "rx_queue_0_missed_errors", 1138 "rx_queue_0_over_errors", 1139 1140 "rx_queue_1_current", 1141 "tx_queue_1_current", 1142 "rx_queue_1_dirty", 1143 "tx_queue_1_dirty", 1144 "rx_queue_1_packets", 1145 "tx_queue_1_packets", 1146 "rx_queue_1_bytes", 1147 "tx_queue_1_bytes", 1148 "rx_queue_1_mcast_packets", 1149 "rx_queue_1_errors", 1150 "rx_queue_1_crc_errors", 1151 "rx_queue_1_frame_errors", 1152 "rx_queue_1_length_errors", 1153 "rx_queue_1_missed_errors", 1154 "rx_queue_1_over_errors", 1155 }; 1156 1157 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1158 1159 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1160 { 1161 switch (sset) { 1162 case ETH_SS_STATS: 1163 return RAVB_STATS_LEN; 1164 default: 1165 return -EOPNOTSUPP; 1166 } 1167 } 1168 1169 static void ravb_get_ethtool_stats(struct net_device *ndev, 1170 struct ethtool_stats *estats, u64 *data) 1171 { 1172 struct ravb_private *priv = netdev_priv(ndev); 1173 int i = 0; 1174 int q; 1175 1176 /* Device-specific stats */ 1177 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1178 struct net_device_stats *stats = &priv->stats[q]; 1179 1180 data[i++] = priv->cur_rx[q]; 1181 data[i++] = priv->cur_tx[q]; 1182 data[i++] = priv->dirty_rx[q]; 1183 data[i++] = priv->dirty_tx[q]; 1184 data[i++] = stats->rx_packets; 1185 data[i++] = stats->tx_packets; 1186 data[i++] = stats->rx_bytes; 1187 data[i++] = stats->tx_bytes; 1188 data[i++] = stats->multicast; 1189 data[i++] = stats->rx_errors; 1190 data[i++] = stats->rx_crc_errors; 1191 data[i++] = stats->rx_frame_errors; 1192 data[i++] = stats->rx_length_errors; 1193 data[i++] = stats->rx_missed_errors; 1194 data[i++] = stats->rx_over_errors; 1195 } 1196 } 1197 1198 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1199 { 1200 switch (stringset) { 1201 case ETH_SS_STATS: 1202 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1203 break; 1204 } 1205 } 1206 1207 static void ravb_get_ringparam(struct net_device *ndev, 1208 struct ethtool_ringparam *ring) 1209 { 1210 struct ravb_private *priv = netdev_priv(ndev); 1211 1212 ring->rx_max_pending = BE_RX_RING_MAX; 1213 ring->tx_max_pending = BE_TX_RING_MAX; 1214 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1215 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1216 } 1217 1218 static int ravb_set_ringparam(struct net_device *ndev, 1219 struct ethtool_ringparam *ring) 1220 { 1221 struct ravb_private *priv = netdev_priv(ndev); 1222 int error; 1223 1224 if (ring->tx_pending > BE_TX_RING_MAX || 1225 ring->rx_pending > BE_RX_RING_MAX || 1226 ring->tx_pending < BE_TX_RING_MIN || 1227 ring->rx_pending < BE_RX_RING_MIN) 1228 return -EINVAL; 1229 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1230 return -EINVAL; 1231 1232 if (netif_running(ndev)) { 1233 netif_device_detach(ndev); 1234 /* Stop PTP Clock driver */ 1235 if (priv->chip_id == RCAR_GEN2) 1236 ravb_ptp_stop(ndev); 1237 /* Wait for DMA stopping */ 1238 error = ravb_stop_dma(ndev); 1239 if (error) { 1240 netdev_err(ndev, 1241 "cannot set ringparam! Any AVB processes are still running?\n"); 1242 return error; 1243 } 1244 synchronize_irq(ndev->irq); 1245 1246 /* Free all the skb's in the RX queue and the DMA buffers. */ 1247 ravb_ring_free(ndev, RAVB_BE); 1248 ravb_ring_free(ndev, RAVB_NC); 1249 } 1250 1251 /* Set new parameters */ 1252 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1253 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1254 1255 if (netif_running(ndev)) { 1256 error = ravb_dmac_init(ndev); 1257 if (error) { 1258 netdev_err(ndev, 1259 "%s: ravb_dmac_init() failed, error %d\n", 1260 __func__, error); 1261 return error; 1262 } 1263 1264 ravb_emac_init(ndev); 1265 1266 /* Initialise PTP Clock driver */ 1267 if (priv->chip_id == RCAR_GEN2) 1268 ravb_ptp_init(ndev, priv->pdev); 1269 1270 netif_device_attach(ndev); 1271 } 1272 1273 return 0; 1274 } 1275 1276 static int ravb_get_ts_info(struct net_device *ndev, 1277 struct ethtool_ts_info *info) 1278 { 1279 struct ravb_private *priv = netdev_priv(ndev); 1280 1281 info->so_timestamping = 1282 SOF_TIMESTAMPING_TX_SOFTWARE | 1283 SOF_TIMESTAMPING_RX_SOFTWARE | 1284 SOF_TIMESTAMPING_SOFTWARE | 1285 SOF_TIMESTAMPING_TX_HARDWARE | 1286 SOF_TIMESTAMPING_RX_HARDWARE | 1287 SOF_TIMESTAMPING_RAW_HARDWARE; 1288 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1289 info->rx_filters = 1290 (1 << HWTSTAMP_FILTER_NONE) | 1291 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1292 (1 << HWTSTAMP_FILTER_ALL); 1293 info->phc_index = ptp_clock_index(priv->ptp.clock); 1294 1295 return 0; 1296 } 1297 1298 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1299 { 1300 struct ravb_private *priv = netdev_priv(ndev); 1301 1302 wol->supported = WAKE_MAGIC; 1303 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1304 } 1305 1306 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1307 { 1308 struct ravb_private *priv = netdev_priv(ndev); 1309 1310 if (wol->wolopts & ~WAKE_MAGIC) 1311 return -EOPNOTSUPP; 1312 1313 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1314 1315 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1316 1317 return 0; 1318 } 1319 1320 static const struct ethtool_ops ravb_ethtool_ops = { 1321 .nway_reset = phy_ethtool_nway_reset, 1322 .get_msglevel = ravb_get_msglevel, 1323 .set_msglevel = ravb_set_msglevel, 1324 .get_link = ethtool_op_get_link, 1325 .get_strings = ravb_get_strings, 1326 .get_ethtool_stats = ravb_get_ethtool_stats, 1327 .get_sset_count = ravb_get_sset_count, 1328 .get_ringparam = ravb_get_ringparam, 1329 .set_ringparam = ravb_set_ringparam, 1330 .get_ts_info = ravb_get_ts_info, 1331 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1332 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1333 .get_wol = ravb_get_wol, 1334 .set_wol = ravb_set_wol, 1335 }; 1336 1337 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1338 struct net_device *ndev, struct device *dev, 1339 const char *ch) 1340 { 1341 char *name; 1342 int error; 1343 1344 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1345 if (!name) 1346 return -ENOMEM; 1347 error = request_irq(irq, handler, 0, name, ndev); 1348 if (error) 1349 netdev_err(ndev, "cannot request IRQ %s\n", name); 1350 1351 return error; 1352 } 1353 1354 /* Network device open function for Ethernet AVB */ 1355 static int ravb_open(struct net_device *ndev) 1356 { 1357 struct ravb_private *priv = netdev_priv(ndev); 1358 struct platform_device *pdev = priv->pdev; 1359 struct device *dev = &pdev->dev; 1360 int error; 1361 1362 napi_enable(&priv->napi[RAVB_BE]); 1363 napi_enable(&priv->napi[RAVB_NC]); 1364 1365 if (priv->chip_id == RCAR_GEN2) { 1366 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1367 ndev->name, ndev); 1368 if (error) { 1369 netdev_err(ndev, "cannot request IRQ\n"); 1370 goto out_napi_off; 1371 } 1372 } else { 1373 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1374 dev, "ch22:multi"); 1375 if (error) 1376 goto out_napi_off; 1377 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1378 dev, "ch24:emac"); 1379 if (error) 1380 goto out_free_irq; 1381 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1382 ndev, dev, "ch0:rx_be"); 1383 if (error) 1384 goto out_free_irq_emac; 1385 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1386 ndev, dev, "ch18:tx_be"); 1387 if (error) 1388 goto out_free_irq_be_rx; 1389 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1390 ndev, dev, "ch1:rx_nc"); 1391 if (error) 1392 goto out_free_irq_be_tx; 1393 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1394 ndev, dev, "ch19:tx_nc"); 1395 if (error) 1396 goto out_free_irq_nc_rx; 1397 } 1398 1399 /* Device init */ 1400 error = ravb_dmac_init(ndev); 1401 if (error) 1402 goto out_free_irq_nc_tx; 1403 ravb_emac_init(ndev); 1404 1405 /* Initialise PTP Clock driver */ 1406 if (priv->chip_id == RCAR_GEN2) 1407 ravb_ptp_init(ndev, priv->pdev); 1408 1409 netif_tx_start_all_queues(ndev); 1410 1411 /* PHY control start */ 1412 error = ravb_phy_start(ndev); 1413 if (error) 1414 goto out_ptp_stop; 1415 1416 return 0; 1417 1418 out_ptp_stop: 1419 /* Stop PTP Clock driver */ 1420 if (priv->chip_id == RCAR_GEN2) 1421 ravb_ptp_stop(ndev); 1422 out_free_irq_nc_tx: 1423 if (priv->chip_id == RCAR_GEN2) 1424 goto out_free_irq; 1425 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1426 out_free_irq_nc_rx: 1427 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1428 out_free_irq_be_tx: 1429 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1430 out_free_irq_be_rx: 1431 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1432 out_free_irq_emac: 1433 free_irq(priv->emac_irq, ndev); 1434 out_free_irq: 1435 free_irq(ndev->irq, ndev); 1436 out_napi_off: 1437 napi_disable(&priv->napi[RAVB_NC]); 1438 napi_disable(&priv->napi[RAVB_BE]); 1439 return error; 1440 } 1441 1442 /* Timeout function for Ethernet AVB */ 1443 static void ravb_tx_timeout(struct net_device *ndev) 1444 { 1445 struct ravb_private *priv = netdev_priv(ndev); 1446 1447 netif_err(priv, tx_err, ndev, 1448 "transmit timed out, status %08x, resetting...\n", 1449 ravb_read(ndev, ISS)); 1450 1451 /* tx_errors count up */ 1452 ndev->stats.tx_errors++; 1453 1454 schedule_work(&priv->work); 1455 } 1456 1457 static void ravb_tx_timeout_work(struct work_struct *work) 1458 { 1459 struct ravb_private *priv = container_of(work, struct ravb_private, 1460 work); 1461 struct net_device *ndev = priv->ndev; 1462 1463 netif_tx_stop_all_queues(ndev); 1464 1465 /* Stop PTP Clock driver */ 1466 if (priv->chip_id == RCAR_GEN2) 1467 ravb_ptp_stop(ndev); 1468 1469 /* Wait for DMA stopping */ 1470 ravb_stop_dma(ndev); 1471 1472 ravb_ring_free(ndev, RAVB_BE); 1473 ravb_ring_free(ndev, RAVB_NC); 1474 1475 /* Device init */ 1476 ravb_dmac_init(ndev); 1477 ravb_emac_init(ndev); 1478 1479 /* Initialise PTP Clock driver */ 1480 if (priv->chip_id == RCAR_GEN2) 1481 ravb_ptp_init(ndev, priv->pdev); 1482 1483 netif_tx_start_all_queues(ndev); 1484 } 1485 1486 /* Packet transmit function for Ethernet AVB */ 1487 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1488 { 1489 struct ravb_private *priv = netdev_priv(ndev); 1490 u16 q = skb_get_queue_mapping(skb); 1491 struct ravb_tstamp_skb *ts_skb; 1492 struct ravb_tx_desc *desc; 1493 unsigned long flags; 1494 u32 dma_addr; 1495 void *buffer; 1496 u32 entry; 1497 u32 len; 1498 1499 spin_lock_irqsave(&priv->lock, flags); 1500 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1501 NUM_TX_DESC) { 1502 netif_err(priv, tx_queued, ndev, 1503 "still transmitting with the full ring!\n"); 1504 netif_stop_subqueue(ndev, q); 1505 spin_unlock_irqrestore(&priv->lock, flags); 1506 return NETDEV_TX_BUSY; 1507 } 1508 1509 if (skb_put_padto(skb, ETH_ZLEN)) 1510 goto exit; 1511 1512 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); 1513 priv->tx_skb[q][entry / NUM_TX_DESC] = skb; 1514 1515 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1516 entry / NUM_TX_DESC * DPTR_ALIGN; 1517 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1518 /* Zero length DMA descriptors are problematic as they seem to 1519 * terminate DMA transfers. Avoid them by simply using a length of 1520 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN. 1521 * 1522 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of 1523 * data by the call to skb_put_padto() above this is safe with 1524 * respect to both the length of the first DMA descriptor (len) 1525 * overflowing the available data and the length of the second DMA 1526 * descriptor (skb->len - len) being negative. 1527 */ 1528 if (len == 0) 1529 len = DPTR_ALIGN; 1530 1531 memcpy(buffer, skb->data, len); 1532 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1533 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1534 goto drop; 1535 1536 desc = &priv->tx_ring[q][entry]; 1537 desc->ds_tagl = cpu_to_le16(len); 1538 desc->dptr = cpu_to_le32(dma_addr); 1539 1540 buffer = skb->data + len; 1541 len = skb->len - len; 1542 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1543 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1544 goto unmap; 1545 1546 desc++; 1547 desc->ds_tagl = cpu_to_le16(len); 1548 desc->dptr = cpu_to_le32(dma_addr); 1549 1550 /* TX timestamp required */ 1551 if (q == RAVB_NC) { 1552 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1553 if (!ts_skb) { 1554 desc--; 1555 dma_unmap_single(ndev->dev.parent, dma_addr, len, 1556 DMA_TO_DEVICE); 1557 goto unmap; 1558 } 1559 ts_skb->skb = skb; 1560 ts_skb->tag = priv->ts_skb_tag++; 1561 priv->ts_skb_tag &= 0x3ff; 1562 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1563 1564 /* TAG and timestamp required flag */ 1565 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1566 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1567 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1568 } 1569 1570 skb_tx_timestamp(skb); 1571 /* Descriptor type must be set after all the above writes */ 1572 dma_wmb(); 1573 desc->die_dt = DT_FEND; 1574 desc--; 1575 desc->die_dt = DT_FSTART; 1576 1577 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1578 1579 priv->cur_tx[q] += NUM_TX_DESC; 1580 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1581 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && 1582 !ravb_tx_free(ndev, q, true)) 1583 netif_stop_subqueue(ndev, q); 1584 1585 exit: 1586 mmiowb(); 1587 spin_unlock_irqrestore(&priv->lock, flags); 1588 return NETDEV_TX_OK; 1589 1590 unmap: 1591 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1592 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1593 drop: 1594 dev_kfree_skb_any(skb); 1595 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; 1596 goto exit; 1597 } 1598 1599 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1600 struct net_device *sb_dev, 1601 select_queue_fallback_t fallback) 1602 { 1603 /* If skb needs TX timestamp, it is handled in network control queue */ 1604 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1605 RAVB_BE; 1606 1607 } 1608 1609 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1610 { 1611 struct ravb_private *priv = netdev_priv(ndev); 1612 struct net_device_stats *nstats, *stats0, *stats1; 1613 1614 nstats = &ndev->stats; 1615 stats0 = &priv->stats[RAVB_BE]; 1616 stats1 = &priv->stats[RAVB_NC]; 1617 1618 nstats->tx_dropped += ravb_read(ndev, TROCR); 1619 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1620 nstats->collisions += ravb_read(ndev, CDCR); 1621 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1622 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1623 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1624 1625 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1626 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1627 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1628 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1629 1630 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1631 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1632 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1633 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1634 nstats->multicast = stats0->multicast + stats1->multicast; 1635 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1636 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1637 nstats->rx_frame_errors = 1638 stats0->rx_frame_errors + stats1->rx_frame_errors; 1639 nstats->rx_length_errors = 1640 stats0->rx_length_errors + stats1->rx_length_errors; 1641 nstats->rx_missed_errors = 1642 stats0->rx_missed_errors + stats1->rx_missed_errors; 1643 nstats->rx_over_errors = 1644 stats0->rx_over_errors + stats1->rx_over_errors; 1645 1646 return nstats; 1647 } 1648 1649 /* Update promiscuous bit */ 1650 static void ravb_set_rx_mode(struct net_device *ndev) 1651 { 1652 struct ravb_private *priv = netdev_priv(ndev); 1653 unsigned long flags; 1654 1655 spin_lock_irqsave(&priv->lock, flags); 1656 ravb_modify(ndev, ECMR, ECMR_PRM, 1657 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1658 mmiowb(); 1659 spin_unlock_irqrestore(&priv->lock, flags); 1660 } 1661 1662 /* Device close function for Ethernet AVB */ 1663 static int ravb_close(struct net_device *ndev) 1664 { 1665 struct device_node *np = ndev->dev.parent->of_node; 1666 struct ravb_private *priv = netdev_priv(ndev); 1667 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1668 1669 netif_tx_stop_all_queues(ndev); 1670 1671 /* Disable interrupts by clearing the interrupt masks. */ 1672 ravb_write(ndev, 0, RIC0); 1673 ravb_write(ndev, 0, RIC2); 1674 ravb_write(ndev, 0, TIC); 1675 1676 /* Stop PTP Clock driver */ 1677 if (priv->chip_id == RCAR_GEN2) 1678 ravb_ptp_stop(ndev); 1679 1680 /* Set the config mode to stop the AVB-DMAC's processes */ 1681 if (ravb_stop_dma(ndev) < 0) 1682 netdev_err(ndev, 1683 "device will be stopped after h/w processes are done.\n"); 1684 1685 /* Clear the timestamp list */ 1686 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1687 list_del(&ts_skb->list); 1688 kfree(ts_skb); 1689 } 1690 1691 /* PHY disconnect */ 1692 if (ndev->phydev) { 1693 phy_stop(ndev->phydev); 1694 phy_disconnect(ndev->phydev); 1695 if (of_phy_is_fixed_link(np)) 1696 of_phy_deregister_fixed_link(np); 1697 } 1698 1699 if (priv->chip_id != RCAR_GEN2) { 1700 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1701 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1702 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1703 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1704 free_irq(priv->emac_irq, ndev); 1705 } 1706 free_irq(ndev->irq, ndev); 1707 1708 napi_disable(&priv->napi[RAVB_NC]); 1709 napi_disable(&priv->napi[RAVB_BE]); 1710 1711 /* Free all the skb's in the RX queue and the DMA buffers. */ 1712 ravb_ring_free(ndev, RAVB_BE); 1713 ravb_ring_free(ndev, RAVB_NC); 1714 1715 return 0; 1716 } 1717 1718 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1719 { 1720 struct ravb_private *priv = netdev_priv(ndev); 1721 struct hwtstamp_config config; 1722 1723 config.flags = 0; 1724 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1725 HWTSTAMP_TX_OFF; 1726 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1727 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1728 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1729 config.rx_filter = HWTSTAMP_FILTER_ALL; 1730 else 1731 config.rx_filter = HWTSTAMP_FILTER_NONE; 1732 1733 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1734 -EFAULT : 0; 1735 } 1736 1737 /* Control hardware time stamping */ 1738 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1739 { 1740 struct ravb_private *priv = netdev_priv(ndev); 1741 struct hwtstamp_config config; 1742 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1743 u32 tstamp_tx_ctrl; 1744 1745 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1746 return -EFAULT; 1747 1748 /* Reserved for future extensions */ 1749 if (config.flags) 1750 return -EINVAL; 1751 1752 switch (config.tx_type) { 1753 case HWTSTAMP_TX_OFF: 1754 tstamp_tx_ctrl = 0; 1755 break; 1756 case HWTSTAMP_TX_ON: 1757 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1758 break; 1759 default: 1760 return -ERANGE; 1761 } 1762 1763 switch (config.rx_filter) { 1764 case HWTSTAMP_FILTER_NONE: 1765 tstamp_rx_ctrl = 0; 1766 break; 1767 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1768 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1769 break; 1770 default: 1771 config.rx_filter = HWTSTAMP_FILTER_ALL; 1772 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1773 } 1774 1775 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1776 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1777 1778 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1779 -EFAULT : 0; 1780 } 1781 1782 /* ioctl to device function */ 1783 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1784 { 1785 struct phy_device *phydev = ndev->phydev; 1786 1787 if (!netif_running(ndev)) 1788 return -EINVAL; 1789 1790 if (!phydev) 1791 return -ENODEV; 1792 1793 switch (cmd) { 1794 case SIOCGHWTSTAMP: 1795 return ravb_hwtstamp_get(ndev, req); 1796 case SIOCSHWTSTAMP: 1797 return ravb_hwtstamp_set(ndev, req); 1798 } 1799 1800 return phy_mii_ioctl(phydev, req, cmd); 1801 } 1802 1803 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 1804 { 1805 if (netif_running(ndev)) 1806 return -EBUSY; 1807 1808 ndev->mtu = new_mtu; 1809 netdev_update_features(ndev); 1810 1811 return 0; 1812 } 1813 1814 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1815 { 1816 struct ravb_private *priv = netdev_priv(ndev); 1817 unsigned long flags; 1818 1819 spin_lock_irqsave(&priv->lock, flags); 1820 1821 /* Disable TX and RX */ 1822 ravb_rcv_snd_disable(ndev); 1823 1824 /* Modify RX Checksum setting */ 1825 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1826 1827 /* Enable TX and RX */ 1828 ravb_rcv_snd_enable(ndev); 1829 1830 spin_unlock_irqrestore(&priv->lock, flags); 1831 } 1832 1833 static int ravb_set_features(struct net_device *ndev, 1834 netdev_features_t features) 1835 { 1836 netdev_features_t changed = ndev->features ^ features; 1837 1838 if (changed & NETIF_F_RXCSUM) 1839 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1840 1841 ndev->features = features; 1842 1843 return 0; 1844 } 1845 1846 static const struct net_device_ops ravb_netdev_ops = { 1847 .ndo_open = ravb_open, 1848 .ndo_stop = ravb_close, 1849 .ndo_start_xmit = ravb_start_xmit, 1850 .ndo_select_queue = ravb_select_queue, 1851 .ndo_get_stats = ravb_get_stats, 1852 .ndo_set_rx_mode = ravb_set_rx_mode, 1853 .ndo_tx_timeout = ravb_tx_timeout, 1854 .ndo_do_ioctl = ravb_do_ioctl, 1855 .ndo_change_mtu = ravb_change_mtu, 1856 .ndo_validate_addr = eth_validate_addr, 1857 .ndo_set_mac_address = eth_mac_addr, 1858 .ndo_set_features = ravb_set_features, 1859 }; 1860 1861 /* MDIO bus init function */ 1862 static int ravb_mdio_init(struct ravb_private *priv) 1863 { 1864 struct platform_device *pdev = priv->pdev; 1865 struct device *dev = &pdev->dev; 1866 int error; 1867 1868 /* Bitbang init */ 1869 priv->mdiobb.ops = &bb_ops; 1870 1871 /* MII controller setting */ 1872 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1873 if (!priv->mii_bus) 1874 return -ENOMEM; 1875 1876 /* Hook up MII support for ethtool */ 1877 priv->mii_bus->name = "ravb_mii"; 1878 priv->mii_bus->parent = dev; 1879 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1880 pdev->name, pdev->id); 1881 1882 /* Register MDIO bus */ 1883 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1884 if (error) 1885 goto out_free_bus; 1886 1887 return 0; 1888 1889 out_free_bus: 1890 free_mdio_bitbang(priv->mii_bus); 1891 return error; 1892 } 1893 1894 /* MDIO bus release function */ 1895 static int ravb_mdio_release(struct ravb_private *priv) 1896 { 1897 /* Unregister mdio bus */ 1898 mdiobus_unregister(priv->mii_bus); 1899 1900 /* Free bitbang info */ 1901 free_mdio_bitbang(priv->mii_bus); 1902 1903 return 0; 1904 } 1905 1906 static const struct of_device_id ravb_match_table[] = { 1907 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1908 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1909 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1910 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1911 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1912 { } 1913 }; 1914 MODULE_DEVICE_TABLE(of, ravb_match_table); 1915 1916 static int ravb_set_gti(struct net_device *ndev) 1917 { 1918 struct ravb_private *priv = netdev_priv(ndev); 1919 struct device *dev = ndev->dev.parent; 1920 unsigned long rate; 1921 uint64_t inc; 1922 1923 rate = clk_get_rate(priv->clk); 1924 if (!rate) 1925 return -EINVAL; 1926 1927 inc = 1000000000ULL << 20; 1928 do_div(inc, rate); 1929 1930 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1931 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1932 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1933 return -EINVAL; 1934 } 1935 1936 ravb_write(ndev, inc, GTI); 1937 1938 return 0; 1939 } 1940 1941 static void ravb_set_config_mode(struct net_device *ndev) 1942 { 1943 struct ravb_private *priv = netdev_priv(ndev); 1944 1945 if (priv->chip_id == RCAR_GEN2) { 1946 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1947 /* Set CSEL value */ 1948 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1949 } else { 1950 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1951 CCC_GAC | CCC_CSEL_HPB); 1952 } 1953 } 1954 1955 /* Set tx and rx clock internal delay modes */ 1956 static void ravb_set_delay_mode(struct net_device *ndev) 1957 { 1958 struct ravb_private *priv = netdev_priv(ndev); 1959 int set = 0; 1960 1961 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1962 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1963 set |= APSR_DM_RDM; 1964 1965 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1966 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1967 set |= APSR_DM_TDM; 1968 1969 ravb_modify(ndev, APSR, APSR_DM, set); 1970 } 1971 1972 static int ravb_probe(struct platform_device *pdev) 1973 { 1974 struct device_node *np = pdev->dev.of_node; 1975 struct ravb_private *priv; 1976 enum ravb_chip_id chip_id; 1977 struct net_device *ndev; 1978 int error, irq, q; 1979 struct resource *res; 1980 int i; 1981 1982 if (!np) { 1983 dev_err(&pdev->dev, 1984 "this driver is required to be instantiated from device tree\n"); 1985 return -EINVAL; 1986 } 1987 1988 /* Get base address */ 1989 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1990 if (!res) { 1991 dev_err(&pdev->dev, "invalid resource\n"); 1992 return -EINVAL; 1993 } 1994 1995 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 1996 NUM_TX_QUEUE, NUM_RX_QUEUE); 1997 if (!ndev) 1998 return -ENOMEM; 1999 2000 ndev->features = NETIF_F_RXCSUM; 2001 ndev->hw_features = NETIF_F_RXCSUM; 2002 2003 pm_runtime_enable(&pdev->dev); 2004 pm_runtime_get_sync(&pdev->dev); 2005 2006 /* The Ether-specific entries in the device structure. */ 2007 ndev->base_addr = res->start; 2008 2009 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2010 2011 if (chip_id == RCAR_GEN3) 2012 irq = platform_get_irq_byname(pdev, "ch22"); 2013 else 2014 irq = platform_get_irq(pdev, 0); 2015 if (irq < 0) { 2016 error = irq; 2017 goto out_release; 2018 } 2019 ndev->irq = irq; 2020 2021 SET_NETDEV_DEV(ndev, &pdev->dev); 2022 2023 priv = netdev_priv(ndev); 2024 priv->ndev = ndev; 2025 priv->pdev = pdev; 2026 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2027 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2028 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2029 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2030 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2031 if (IS_ERR(priv->addr)) { 2032 error = PTR_ERR(priv->addr); 2033 goto out_release; 2034 } 2035 2036 spin_lock_init(&priv->lock); 2037 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2038 2039 priv->phy_interface = of_get_phy_mode(np); 2040 2041 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2042 priv->avb_link_active_low = 2043 of_property_read_bool(np, "renesas,ether-link-active-low"); 2044 2045 if (chip_id == RCAR_GEN3) { 2046 irq = platform_get_irq_byname(pdev, "ch24"); 2047 if (irq < 0) { 2048 error = irq; 2049 goto out_release; 2050 } 2051 priv->emac_irq = irq; 2052 for (i = 0; i < NUM_RX_QUEUE; i++) { 2053 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2054 if (irq < 0) { 2055 error = irq; 2056 goto out_release; 2057 } 2058 priv->rx_irqs[i] = irq; 2059 } 2060 for (i = 0; i < NUM_TX_QUEUE; i++) { 2061 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2062 if (irq < 0) { 2063 error = irq; 2064 goto out_release; 2065 } 2066 priv->tx_irqs[i] = irq; 2067 } 2068 } 2069 2070 priv->chip_id = chip_id; 2071 2072 priv->clk = devm_clk_get(&pdev->dev, NULL); 2073 if (IS_ERR(priv->clk)) { 2074 error = PTR_ERR(priv->clk); 2075 goto out_release; 2076 } 2077 2078 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2079 ndev->min_mtu = ETH_MIN_MTU; 2080 2081 /* Set function */ 2082 ndev->netdev_ops = &ravb_netdev_ops; 2083 ndev->ethtool_ops = &ravb_ethtool_ops; 2084 2085 /* Set AVB config mode */ 2086 ravb_set_config_mode(ndev); 2087 2088 /* Set GTI value */ 2089 error = ravb_set_gti(ndev); 2090 if (error) 2091 goto out_release; 2092 2093 /* Request GTI loading */ 2094 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2095 2096 if (priv->chip_id != RCAR_GEN2) 2097 ravb_set_delay_mode(ndev); 2098 2099 /* Allocate descriptor base address table */ 2100 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2101 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2102 &priv->desc_bat_dma, GFP_KERNEL); 2103 if (!priv->desc_bat) { 2104 dev_err(&pdev->dev, 2105 "Cannot allocate desc base address table (size %d bytes)\n", 2106 priv->desc_bat_size); 2107 error = -ENOMEM; 2108 goto out_release; 2109 } 2110 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2111 priv->desc_bat[q].die_dt = DT_EOS; 2112 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2113 2114 /* Initialise HW timestamp list */ 2115 INIT_LIST_HEAD(&priv->ts_skb_list); 2116 2117 /* Initialise PTP Clock driver */ 2118 if (chip_id != RCAR_GEN2) 2119 ravb_ptp_init(ndev, pdev); 2120 2121 /* Debug message level */ 2122 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2123 2124 /* Read and set MAC address */ 2125 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2126 if (!is_valid_ether_addr(ndev->dev_addr)) { 2127 dev_warn(&pdev->dev, 2128 "no valid MAC address supplied, using a random one\n"); 2129 eth_hw_addr_random(ndev); 2130 } 2131 2132 /* MDIO bus init */ 2133 error = ravb_mdio_init(priv); 2134 if (error) { 2135 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2136 goto out_dma_free; 2137 } 2138 2139 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2140 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2141 2142 /* Network device register */ 2143 error = register_netdev(ndev); 2144 if (error) 2145 goto out_napi_del; 2146 2147 device_set_wakeup_capable(&pdev->dev, 1); 2148 2149 /* Print device information */ 2150 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2151 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2152 2153 platform_set_drvdata(pdev, ndev); 2154 2155 return 0; 2156 2157 out_napi_del: 2158 netif_napi_del(&priv->napi[RAVB_NC]); 2159 netif_napi_del(&priv->napi[RAVB_BE]); 2160 ravb_mdio_release(priv); 2161 out_dma_free: 2162 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2163 priv->desc_bat_dma); 2164 2165 /* Stop PTP Clock driver */ 2166 if (chip_id != RCAR_GEN2) 2167 ravb_ptp_stop(ndev); 2168 out_release: 2169 free_netdev(ndev); 2170 2171 pm_runtime_put(&pdev->dev); 2172 pm_runtime_disable(&pdev->dev); 2173 return error; 2174 } 2175 2176 static int ravb_remove(struct platform_device *pdev) 2177 { 2178 struct net_device *ndev = platform_get_drvdata(pdev); 2179 struct ravb_private *priv = netdev_priv(ndev); 2180 2181 /* Stop PTP Clock driver */ 2182 if (priv->chip_id != RCAR_GEN2) 2183 ravb_ptp_stop(ndev); 2184 2185 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2186 priv->desc_bat_dma); 2187 /* Set reset mode */ 2188 ravb_write(ndev, CCC_OPC_RESET, CCC); 2189 pm_runtime_put_sync(&pdev->dev); 2190 unregister_netdev(ndev); 2191 netif_napi_del(&priv->napi[RAVB_NC]); 2192 netif_napi_del(&priv->napi[RAVB_BE]); 2193 ravb_mdio_release(priv); 2194 pm_runtime_disable(&pdev->dev); 2195 free_netdev(ndev); 2196 platform_set_drvdata(pdev, NULL); 2197 2198 return 0; 2199 } 2200 2201 static int ravb_wol_setup(struct net_device *ndev) 2202 { 2203 struct ravb_private *priv = netdev_priv(ndev); 2204 2205 /* Disable interrupts by clearing the interrupt masks. */ 2206 ravb_write(ndev, 0, RIC0); 2207 ravb_write(ndev, 0, RIC2); 2208 ravb_write(ndev, 0, TIC); 2209 2210 /* Only allow ECI interrupts */ 2211 synchronize_irq(priv->emac_irq); 2212 napi_disable(&priv->napi[RAVB_NC]); 2213 napi_disable(&priv->napi[RAVB_BE]); 2214 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2215 2216 /* Enable MagicPacket */ 2217 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2218 2219 return enable_irq_wake(priv->emac_irq); 2220 } 2221 2222 static int ravb_wol_restore(struct net_device *ndev) 2223 { 2224 struct ravb_private *priv = netdev_priv(ndev); 2225 int ret; 2226 2227 napi_enable(&priv->napi[RAVB_NC]); 2228 napi_enable(&priv->napi[RAVB_BE]); 2229 2230 /* Disable MagicPacket */ 2231 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2232 2233 ret = ravb_close(ndev); 2234 if (ret < 0) 2235 return ret; 2236 2237 return disable_irq_wake(priv->emac_irq); 2238 } 2239 2240 static int __maybe_unused ravb_suspend(struct device *dev) 2241 { 2242 struct net_device *ndev = dev_get_drvdata(dev); 2243 struct ravb_private *priv = netdev_priv(ndev); 2244 int ret; 2245 2246 if (!netif_running(ndev)) 2247 return 0; 2248 2249 netif_device_detach(ndev); 2250 2251 if (priv->wol_enabled) 2252 ret = ravb_wol_setup(ndev); 2253 else 2254 ret = ravb_close(ndev); 2255 2256 return ret; 2257 } 2258 2259 static int __maybe_unused ravb_resume(struct device *dev) 2260 { 2261 struct net_device *ndev = dev_get_drvdata(dev); 2262 struct ravb_private *priv = netdev_priv(ndev); 2263 int ret = 0; 2264 2265 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2266 if (priv->wol_enabled) 2267 ravb_write(ndev, CCC_OPC_RESET, CCC); 2268 2269 /* All register have been reset to default values. 2270 * Restore all registers which where setup at probe time and 2271 * reopen device if it was running before system suspended. 2272 */ 2273 2274 /* Set AVB config mode */ 2275 ravb_set_config_mode(ndev); 2276 2277 /* Set GTI value */ 2278 ret = ravb_set_gti(ndev); 2279 if (ret) 2280 return ret; 2281 2282 /* Request GTI loading */ 2283 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2284 2285 if (priv->chip_id != RCAR_GEN2) 2286 ravb_set_delay_mode(ndev); 2287 2288 /* Restore descriptor base address table */ 2289 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2290 2291 if (netif_running(ndev)) { 2292 if (priv->wol_enabled) { 2293 ret = ravb_wol_restore(ndev); 2294 if (ret) 2295 return ret; 2296 } 2297 ret = ravb_open(ndev); 2298 if (ret < 0) 2299 return ret; 2300 netif_device_attach(ndev); 2301 } 2302 2303 return ret; 2304 } 2305 2306 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2307 { 2308 /* Runtime PM callback shared between ->runtime_suspend() 2309 * and ->runtime_resume(). Simply returns success. 2310 * 2311 * This driver re-initializes all registers after 2312 * pm_runtime_get_sync() anyway so there is no need 2313 * to save and restore registers here. 2314 */ 2315 return 0; 2316 } 2317 2318 static const struct dev_pm_ops ravb_dev_pm_ops = { 2319 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2320 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2321 }; 2322 2323 static struct platform_driver ravb_driver = { 2324 .probe = ravb_probe, 2325 .remove = ravb_remove, 2326 .driver = { 2327 .name = "ravb", 2328 .pm = &ravb_dev_pm_ops, 2329 .of_match_table = ravb_match_table, 2330 }, 2331 }; 2332 2333 module_platform_driver(ravb_driver); 2334 2335 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2336 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2337 MODULE_LICENSE("GPL v2"); 2338