1 /* Renesas Ethernet AVB device driver 2 * 3 * Copyright (C) 2014-2015 Renesas Electronics Corporation 4 * Copyright (C) 2015 Renesas Solutions Corp. 5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 6 * 7 * Based on the SuperH Ethernet driver 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License version 2, 11 * as published by the Free Software Foundation. 12 */ 13 14 #include <linux/cache.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/err.h> 19 #include <linux/etherdevice.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/kernel.h> 23 #include <linux/list.h> 24 #include <linux/module.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_mdio.h> 30 #include <linux/of_net.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/slab.h> 33 #include <linux/spinlock.h> 34 35 #include <asm/div64.h> 36 37 #include "ravb.h" 38 39 #define RAVB_DEF_MSG_ENABLE \ 40 (NETIF_MSG_LINK | \ 41 NETIF_MSG_TIMER | \ 42 NETIF_MSG_RX_ERR | \ 43 NETIF_MSG_TX_ERR) 44 45 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 46 "ch0", /* RAVB_BE */ 47 "ch1", /* RAVB_NC */ 48 }; 49 50 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 51 "ch18", /* RAVB_BE */ 52 "ch19", /* RAVB_NC */ 53 }; 54 55 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 56 u32 set) 57 { 58 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 59 } 60 61 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 62 { 63 int i; 64 65 for (i = 0; i < 10000; i++) { 66 if ((ravb_read(ndev, reg) & mask) == value) 67 return 0; 68 udelay(10); 69 } 70 return -ETIMEDOUT; 71 } 72 73 static int ravb_config(struct net_device *ndev) 74 { 75 int error; 76 77 /* Set config mode */ 78 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 79 /* Check if the operating mode is changed to the config mode */ 80 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 81 if (error) 82 netdev_err(ndev, "failed to switch device to config mode\n"); 83 84 return error; 85 } 86 87 static void ravb_set_duplex(struct net_device *ndev) 88 { 89 struct ravb_private *priv = netdev_priv(ndev); 90 91 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0); 92 } 93 94 static void ravb_set_rate(struct net_device *ndev) 95 { 96 struct ravb_private *priv = netdev_priv(ndev); 97 98 switch (priv->speed) { 99 case 100: /* 100BASE */ 100 ravb_write(ndev, GECMR_SPEED_100, GECMR); 101 break; 102 case 1000: /* 1000BASE */ 103 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 104 break; 105 } 106 } 107 108 static void ravb_set_buffer_align(struct sk_buff *skb) 109 { 110 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 111 112 if (reserve) 113 skb_reserve(skb, RAVB_ALIGN - reserve); 114 } 115 116 /* Get MAC address from the MAC address registers 117 * 118 * Ethernet AVB device doesn't have ROM for MAC address. 119 * This function gets the MAC address that was used by a bootloader. 120 */ 121 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 122 { 123 if (mac) { 124 ether_addr_copy(ndev->dev_addr, mac); 125 } else { 126 u32 mahr = ravb_read(ndev, MAHR); 127 u32 malr = ravb_read(ndev, MALR); 128 129 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 130 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 131 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 132 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 133 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 134 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 135 } 136 } 137 138 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 139 { 140 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 141 mdiobb); 142 143 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 144 } 145 146 /* MDC pin control */ 147 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 148 { 149 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 150 } 151 152 /* Data I/O pin control */ 153 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 154 { 155 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 156 } 157 158 /* Set data bit */ 159 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 160 { 161 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 162 } 163 164 /* Get data bit */ 165 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 166 { 167 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 168 mdiobb); 169 170 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 171 } 172 173 /* MDIO bus control struct */ 174 static struct mdiobb_ops bb_ops = { 175 .owner = THIS_MODULE, 176 .set_mdc = ravb_set_mdc, 177 .set_mdio_dir = ravb_set_mdio_dir, 178 .set_mdio_data = ravb_set_mdio_data, 179 .get_mdio_data = ravb_get_mdio_data, 180 }; 181 182 /* Free skb's and DMA buffers for Ethernet AVB */ 183 static void ravb_ring_free(struct net_device *ndev, int q) 184 { 185 struct ravb_private *priv = netdev_priv(ndev); 186 int ring_size; 187 int i; 188 189 /* Free RX skb ringbuffer */ 190 if (priv->rx_skb[q]) { 191 for (i = 0; i < priv->num_rx_ring[q]; i++) 192 dev_kfree_skb(priv->rx_skb[q][i]); 193 } 194 kfree(priv->rx_skb[q]); 195 priv->rx_skb[q] = NULL; 196 197 /* Free TX skb ringbuffer */ 198 if (priv->tx_skb[q]) { 199 for (i = 0; i < priv->num_tx_ring[q]; i++) 200 dev_kfree_skb(priv->tx_skb[q][i]); 201 } 202 kfree(priv->tx_skb[q]); 203 priv->tx_skb[q] = NULL; 204 205 /* Free aligned TX buffers */ 206 kfree(priv->tx_align[q]); 207 priv->tx_align[q] = NULL; 208 209 if (priv->rx_ring[q]) { 210 ring_size = sizeof(struct ravb_ex_rx_desc) * 211 (priv->num_rx_ring[q] + 1); 212 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 213 priv->rx_desc_dma[q]); 214 priv->rx_ring[q] = NULL; 215 } 216 217 if (priv->tx_ring[q]) { 218 ring_size = sizeof(struct ravb_tx_desc) * 219 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 220 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 221 priv->tx_desc_dma[q]); 222 priv->tx_ring[q] = NULL; 223 } 224 } 225 226 /* Format skb and descriptor buffer for Ethernet AVB */ 227 static void ravb_ring_format(struct net_device *ndev, int q) 228 { 229 struct ravb_private *priv = netdev_priv(ndev); 230 struct ravb_ex_rx_desc *rx_desc; 231 struct ravb_tx_desc *tx_desc; 232 struct ravb_desc *desc; 233 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 234 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 235 NUM_TX_DESC; 236 dma_addr_t dma_addr; 237 int i; 238 239 priv->cur_rx[q] = 0; 240 priv->cur_tx[q] = 0; 241 priv->dirty_rx[q] = 0; 242 priv->dirty_tx[q] = 0; 243 244 memset(priv->rx_ring[q], 0, rx_ring_size); 245 /* Build RX ring buffer */ 246 for (i = 0; i < priv->num_rx_ring[q]; i++) { 247 /* RX descriptor */ 248 rx_desc = &priv->rx_ring[q][i]; 249 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ); 250 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 251 PKT_BUF_SZ, 252 DMA_FROM_DEVICE); 253 /* We just set the data size to 0 for a failed mapping which 254 * should prevent DMA from happening... 255 */ 256 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 257 rx_desc->ds_cc = cpu_to_le16(0); 258 rx_desc->dptr = cpu_to_le32(dma_addr); 259 rx_desc->die_dt = DT_FEMPTY; 260 } 261 rx_desc = &priv->rx_ring[q][i]; 262 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 263 rx_desc->die_dt = DT_LINKFIX; /* type */ 264 265 memset(priv->tx_ring[q], 0, tx_ring_size); 266 /* Build TX ring buffer */ 267 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 268 i++, tx_desc++) { 269 tx_desc->die_dt = DT_EEMPTY; 270 tx_desc++; 271 tx_desc->die_dt = DT_EEMPTY; 272 } 273 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 274 tx_desc->die_dt = DT_LINKFIX; /* type */ 275 276 /* RX descriptor base address for best effort */ 277 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 278 desc->die_dt = DT_LINKFIX; /* type */ 279 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 280 281 /* TX descriptor base address for best effort */ 282 desc = &priv->desc_bat[q]; 283 desc->die_dt = DT_LINKFIX; /* type */ 284 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 285 } 286 287 /* Init skb and descriptor buffer for Ethernet AVB */ 288 static int ravb_ring_init(struct net_device *ndev, int q) 289 { 290 struct ravb_private *priv = netdev_priv(ndev); 291 struct sk_buff *skb; 292 int ring_size; 293 int i; 294 295 /* Allocate RX and TX skb rings */ 296 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 297 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 298 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 299 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 300 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 301 goto error; 302 303 for (i = 0; i < priv->num_rx_ring[q]; i++) { 304 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1); 305 if (!skb) 306 goto error; 307 ravb_set_buffer_align(skb); 308 priv->rx_skb[q][i] = skb; 309 } 310 311 /* Allocate rings for the aligned buffers */ 312 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 313 DPTR_ALIGN - 1, GFP_KERNEL); 314 if (!priv->tx_align[q]) 315 goto error; 316 317 /* Allocate all RX descriptors. */ 318 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 319 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 320 &priv->rx_desc_dma[q], 321 GFP_KERNEL); 322 if (!priv->rx_ring[q]) 323 goto error; 324 325 priv->dirty_rx[q] = 0; 326 327 /* Allocate all TX descriptors. */ 328 ring_size = sizeof(struct ravb_tx_desc) * 329 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 330 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 331 &priv->tx_desc_dma[q], 332 GFP_KERNEL); 333 if (!priv->tx_ring[q]) 334 goto error; 335 336 return 0; 337 338 error: 339 ravb_ring_free(ndev, q); 340 341 return -ENOMEM; 342 } 343 344 /* E-MAC init function */ 345 static void ravb_emac_init(struct net_device *ndev) 346 { 347 struct ravb_private *priv = netdev_priv(ndev); 348 349 /* Receive frame limit set register */ 350 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 351 352 /* PAUSE prohibition */ 353 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | 354 ECMR_TE | ECMR_RE, ECMR); 355 356 ravb_set_rate(ndev); 357 358 /* Set MAC address */ 359 ravb_write(ndev, 360 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 361 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 362 ravb_write(ndev, 363 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 364 365 /* E-MAC status register clear */ 366 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 367 368 /* E-MAC interrupt enable register */ 369 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 370 } 371 372 /* Device init function for Ethernet AVB */ 373 static int ravb_dmac_init(struct net_device *ndev) 374 { 375 struct ravb_private *priv = netdev_priv(ndev); 376 int error; 377 378 /* Set CONFIG mode */ 379 error = ravb_config(ndev); 380 if (error) 381 return error; 382 383 error = ravb_ring_init(ndev, RAVB_BE); 384 if (error) 385 return error; 386 error = ravb_ring_init(ndev, RAVB_NC); 387 if (error) { 388 ravb_ring_free(ndev, RAVB_BE); 389 return error; 390 } 391 392 /* Descriptor format */ 393 ravb_ring_format(ndev, RAVB_BE); 394 ravb_ring_format(ndev, RAVB_NC); 395 396 #if defined(__LITTLE_ENDIAN) 397 ravb_modify(ndev, CCC, CCC_BOC, 0); 398 #else 399 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 400 #endif 401 402 /* Set AVB RX */ 403 ravb_write(ndev, 404 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 405 406 /* Set FIFO size */ 407 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 408 409 /* Timestamp enable */ 410 ravb_write(ndev, TCCR_TFEN, TCCR); 411 412 /* Interrupt init: */ 413 if (priv->chip_id == RCAR_GEN3) { 414 /* Clear DIL.DPLx */ 415 ravb_write(ndev, 0, DIL); 416 /* Set queue specific interrupt */ 417 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 418 } 419 /* Frame receive */ 420 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 421 /* Disable FIFO full warning */ 422 ravb_write(ndev, 0, RIC1); 423 /* Receive FIFO full error, descriptor empty */ 424 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 425 /* Frame transmitted, timestamp FIFO updated */ 426 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 427 428 /* Setting the control will start the AVB-DMAC process. */ 429 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 430 431 return 0; 432 } 433 434 /* Free TX skb function for AVB-IP */ 435 static int ravb_tx_free(struct net_device *ndev, int q) 436 { 437 struct ravb_private *priv = netdev_priv(ndev); 438 struct net_device_stats *stats = &priv->stats[q]; 439 struct ravb_tx_desc *desc; 440 int free_num = 0; 441 int entry; 442 u32 size; 443 444 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 445 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 446 NUM_TX_DESC); 447 desc = &priv->tx_ring[q][entry]; 448 if (desc->die_dt != DT_FEMPTY) 449 break; 450 /* Descriptor type must be checked before all other reads */ 451 dma_rmb(); 452 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 453 /* Free the original skb. */ 454 if (priv->tx_skb[q][entry / NUM_TX_DESC]) { 455 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 456 size, DMA_TO_DEVICE); 457 /* Last packet descriptor? */ 458 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { 459 entry /= NUM_TX_DESC; 460 dev_kfree_skb_any(priv->tx_skb[q][entry]); 461 priv->tx_skb[q][entry] = NULL; 462 stats->tx_packets++; 463 } 464 free_num++; 465 } 466 stats->tx_bytes += size; 467 desc->die_dt = DT_EEMPTY; 468 } 469 return free_num; 470 } 471 472 static void ravb_get_tx_tstamp(struct net_device *ndev) 473 { 474 struct ravb_private *priv = netdev_priv(ndev); 475 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 476 struct skb_shared_hwtstamps shhwtstamps; 477 struct sk_buff *skb; 478 struct timespec64 ts; 479 u16 tag, tfa_tag; 480 int count; 481 u32 tfa2; 482 483 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 484 while (count--) { 485 tfa2 = ravb_read(ndev, TFA2); 486 tfa_tag = (tfa2 & TFA2_TST) >> 16; 487 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 488 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 489 ravb_read(ndev, TFA1); 490 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 491 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 492 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 493 list) { 494 skb = ts_skb->skb; 495 tag = ts_skb->tag; 496 list_del(&ts_skb->list); 497 kfree(ts_skb); 498 if (tag == tfa_tag) { 499 skb_tstamp_tx(skb, &shhwtstamps); 500 break; 501 } 502 } 503 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 504 } 505 } 506 507 /* Packet receive function for Ethernet AVB */ 508 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 509 { 510 struct ravb_private *priv = netdev_priv(ndev); 511 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 512 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 513 priv->cur_rx[q]; 514 struct net_device_stats *stats = &priv->stats[q]; 515 struct ravb_ex_rx_desc *desc; 516 struct sk_buff *skb; 517 dma_addr_t dma_addr; 518 struct timespec64 ts; 519 u8 desc_status; 520 u16 pkt_len; 521 int limit; 522 523 boguscnt = min(boguscnt, *quota); 524 limit = boguscnt; 525 desc = &priv->rx_ring[q][entry]; 526 while (desc->die_dt != DT_FEMPTY) { 527 /* Descriptor type must be checked before all other reads */ 528 dma_rmb(); 529 desc_status = desc->msc; 530 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 531 532 if (--boguscnt < 0) 533 break; 534 535 /* We use 0-byte descriptors to mark the DMA mapping errors */ 536 if (!pkt_len) 537 continue; 538 539 if (desc_status & MSC_MC) 540 stats->multicast++; 541 542 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 543 MSC_CEEF)) { 544 stats->rx_errors++; 545 if (desc_status & MSC_CRC) 546 stats->rx_crc_errors++; 547 if (desc_status & MSC_RFE) 548 stats->rx_frame_errors++; 549 if (desc_status & (MSC_RTLF | MSC_RTSF)) 550 stats->rx_length_errors++; 551 if (desc_status & MSC_CEEF) 552 stats->rx_missed_errors++; 553 } else { 554 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 555 556 skb = priv->rx_skb[q][entry]; 557 priv->rx_skb[q][entry] = NULL; 558 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 559 PKT_BUF_SZ, 560 DMA_FROM_DEVICE); 561 get_ts &= (q == RAVB_NC) ? 562 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 563 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 564 if (get_ts) { 565 struct skb_shared_hwtstamps *shhwtstamps; 566 567 shhwtstamps = skb_hwtstamps(skb); 568 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 569 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 570 32) | le32_to_cpu(desc->ts_sl); 571 ts.tv_nsec = le32_to_cpu(desc->ts_n); 572 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 573 } 574 skb_put(skb, pkt_len); 575 skb->protocol = eth_type_trans(skb, ndev); 576 napi_gro_receive(&priv->napi[q], skb); 577 stats->rx_packets++; 578 stats->rx_bytes += pkt_len; 579 } 580 581 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 582 desc = &priv->rx_ring[q][entry]; 583 } 584 585 /* Refill the RX ring buffers. */ 586 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 587 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 588 desc = &priv->rx_ring[q][entry]; 589 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ); 590 591 if (!priv->rx_skb[q][entry]) { 592 skb = netdev_alloc_skb(ndev, 593 PKT_BUF_SZ + RAVB_ALIGN - 1); 594 if (!skb) 595 break; /* Better luck next round. */ 596 ravb_set_buffer_align(skb); 597 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 598 le16_to_cpu(desc->ds_cc), 599 DMA_FROM_DEVICE); 600 skb_checksum_none_assert(skb); 601 /* We just set the data size to 0 for a failed mapping 602 * which should prevent DMA from happening... 603 */ 604 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 605 desc->ds_cc = cpu_to_le16(0); 606 desc->dptr = cpu_to_le32(dma_addr); 607 priv->rx_skb[q][entry] = skb; 608 } 609 /* Descriptor type must be set after all the above writes */ 610 dma_wmb(); 611 desc->die_dt = DT_FEMPTY; 612 } 613 614 *quota -= limit - (++boguscnt); 615 616 return boguscnt <= 0; 617 } 618 619 static void ravb_rcv_snd_disable(struct net_device *ndev) 620 { 621 /* Disable TX and RX */ 622 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 623 } 624 625 static void ravb_rcv_snd_enable(struct net_device *ndev) 626 { 627 /* Enable TX and RX */ 628 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 629 } 630 631 /* function for waiting dma process finished */ 632 static int ravb_stop_dma(struct net_device *ndev) 633 { 634 int error; 635 636 /* Wait for stopping the hardware TX process */ 637 error = ravb_wait(ndev, TCCR, 638 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 639 if (error) 640 return error; 641 642 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 643 0); 644 if (error) 645 return error; 646 647 /* Stop the E-MAC's RX/TX processes. */ 648 ravb_rcv_snd_disable(ndev); 649 650 /* Wait for stopping the RX DMA process */ 651 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 652 if (error) 653 return error; 654 655 /* Stop AVB-DMAC process */ 656 return ravb_config(ndev); 657 } 658 659 /* E-MAC interrupt handler */ 660 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 661 { 662 struct ravb_private *priv = netdev_priv(ndev); 663 u32 ecsr, psr; 664 665 ecsr = ravb_read(ndev, ECSR); 666 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 667 if (ecsr & ECSR_ICD) 668 ndev->stats.tx_carrier_errors++; 669 if (ecsr & ECSR_LCHNG) { 670 /* Link changed */ 671 if (priv->no_avb_link) 672 return; 673 psr = ravb_read(ndev, PSR); 674 if (priv->avb_link_active_low) 675 psr ^= PSR_LMON; 676 if (!(psr & PSR_LMON)) { 677 /* DIsable RX and TX */ 678 ravb_rcv_snd_disable(ndev); 679 } else { 680 /* Enable RX and TX */ 681 ravb_rcv_snd_enable(ndev); 682 } 683 } 684 } 685 686 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 687 { 688 struct net_device *ndev = dev_id; 689 struct ravb_private *priv = netdev_priv(ndev); 690 691 spin_lock(&priv->lock); 692 ravb_emac_interrupt_unlocked(ndev); 693 mmiowb(); 694 spin_unlock(&priv->lock); 695 return IRQ_HANDLED; 696 } 697 698 /* Error interrupt handler */ 699 static void ravb_error_interrupt(struct net_device *ndev) 700 { 701 struct ravb_private *priv = netdev_priv(ndev); 702 u32 eis, ris2; 703 704 eis = ravb_read(ndev, EIS); 705 ravb_write(ndev, ~EIS_QFS, EIS); 706 if (eis & EIS_QFS) { 707 ris2 = ravb_read(ndev, RIS2); 708 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); 709 710 /* Receive Descriptor Empty int */ 711 if (ris2 & RIS2_QFF0) 712 priv->stats[RAVB_BE].rx_over_errors++; 713 714 /* Receive Descriptor Empty int */ 715 if (ris2 & RIS2_QFF1) 716 priv->stats[RAVB_NC].rx_over_errors++; 717 718 /* Receive FIFO Overflow int */ 719 if (ris2 & RIS2_RFFF) 720 priv->rx_fifo_errors++; 721 } 722 } 723 724 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 725 { 726 struct ravb_private *priv = netdev_priv(ndev); 727 u32 ris0 = ravb_read(ndev, RIS0); 728 u32 ric0 = ravb_read(ndev, RIC0); 729 u32 tis = ravb_read(ndev, TIS); 730 u32 tic = ravb_read(ndev, TIC); 731 732 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 733 if (napi_schedule_prep(&priv->napi[q])) { 734 /* Mask RX and TX interrupts */ 735 if (priv->chip_id == RCAR_GEN2) { 736 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 737 ravb_write(ndev, tic & ~BIT(q), TIC); 738 } else { 739 ravb_write(ndev, BIT(q), RID0); 740 ravb_write(ndev, BIT(q), TID); 741 } 742 __napi_schedule(&priv->napi[q]); 743 } else { 744 netdev_warn(ndev, 745 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 746 ris0, ric0); 747 netdev_warn(ndev, 748 " tx status 0x%08x, tx mask 0x%08x.\n", 749 tis, tic); 750 } 751 return true; 752 } 753 return false; 754 } 755 756 static bool ravb_timestamp_interrupt(struct net_device *ndev) 757 { 758 u32 tis = ravb_read(ndev, TIS); 759 760 if (tis & TIS_TFUF) { 761 ravb_write(ndev, ~TIS_TFUF, TIS); 762 ravb_get_tx_tstamp(ndev); 763 return true; 764 } 765 return false; 766 } 767 768 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 769 { 770 struct net_device *ndev = dev_id; 771 struct ravb_private *priv = netdev_priv(ndev); 772 irqreturn_t result = IRQ_NONE; 773 u32 iss; 774 775 spin_lock(&priv->lock); 776 /* Get interrupt status */ 777 iss = ravb_read(ndev, ISS); 778 779 /* Received and transmitted interrupts */ 780 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 781 int q; 782 783 /* Timestamp updated */ 784 if (ravb_timestamp_interrupt(ndev)) 785 result = IRQ_HANDLED; 786 787 /* Network control and best effort queue RX/TX */ 788 for (q = RAVB_NC; q >= RAVB_BE; q--) { 789 if (ravb_queue_interrupt(ndev, q)) 790 result = IRQ_HANDLED; 791 } 792 } 793 794 /* E-MAC status summary */ 795 if (iss & ISS_MS) { 796 ravb_emac_interrupt_unlocked(ndev); 797 result = IRQ_HANDLED; 798 } 799 800 /* Error status summary */ 801 if (iss & ISS_ES) { 802 ravb_error_interrupt(ndev); 803 result = IRQ_HANDLED; 804 } 805 806 /* gPTP interrupt status summary */ 807 if (iss & ISS_CGIS) { 808 ravb_ptp_interrupt(ndev); 809 result = IRQ_HANDLED; 810 } 811 812 mmiowb(); 813 spin_unlock(&priv->lock); 814 return result; 815 } 816 817 /* Timestamp/Error/gPTP interrupt handler */ 818 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 819 { 820 struct net_device *ndev = dev_id; 821 struct ravb_private *priv = netdev_priv(ndev); 822 irqreturn_t result = IRQ_NONE; 823 u32 iss; 824 825 spin_lock(&priv->lock); 826 /* Get interrupt status */ 827 iss = ravb_read(ndev, ISS); 828 829 /* Timestamp updated */ 830 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 831 result = IRQ_HANDLED; 832 833 /* Error status summary */ 834 if (iss & ISS_ES) { 835 ravb_error_interrupt(ndev); 836 result = IRQ_HANDLED; 837 } 838 839 /* gPTP interrupt status summary */ 840 if (iss & ISS_CGIS) { 841 ravb_ptp_interrupt(ndev); 842 result = IRQ_HANDLED; 843 } 844 845 mmiowb(); 846 spin_unlock(&priv->lock); 847 return result; 848 } 849 850 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 851 { 852 struct net_device *ndev = dev_id; 853 struct ravb_private *priv = netdev_priv(ndev); 854 irqreturn_t result = IRQ_NONE; 855 856 spin_lock(&priv->lock); 857 858 /* Network control/Best effort queue RX/TX */ 859 if (ravb_queue_interrupt(ndev, q)) 860 result = IRQ_HANDLED; 861 862 mmiowb(); 863 spin_unlock(&priv->lock); 864 return result; 865 } 866 867 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 868 { 869 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 870 } 871 872 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 873 { 874 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 875 } 876 877 static int ravb_poll(struct napi_struct *napi, int budget) 878 { 879 struct net_device *ndev = napi->dev; 880 struct ravb_private *priv = netdev_priv(ndev); 881 unsigned long flags; 882 int q = napi - priv->napi; 883 int mask = BIT(q); 884 int quota = budget; 885 u32 ris0, tis; 886 887 for (;;) { 888 tis = ravb_read(ndev, TIS); 889 ris0 = ravb_read(ndev, RIS0); 890 if (!((ris0 & mask) || (tis & mask))) 891 break; 892 893 /* Processing RX Descriptor Ring */ 894 if (ris0 & mask) { 895 /* Clear RX interrupt */ 896 ravb_write(ndev, ~mask, RIS0); 897 if (ravb_rx(ndev, "a, q)) 898 goto out; 899 } 900 /* Processing TX Descriptor Ring */ 901 if (tis & mask) { 902 spin_lock_irqsave(&priv->lock, flags); 903 /* Clear TX interrupt */ 904 ravb_write(ndev, ~mask, TIS); 905 ravb_tx_free(ndev, q); 906 netif_wake_subqueue(ndev, q); 907 mmiowb(); 908 spin_unlock_irqrestore(&priv->lock, flags); 909 } 910 } 911 912 napi_complete(napi); 913 914 /* Re-enable RX/TX interrupts */ 915 spin_lock_irqsave(&priv->lock, flags); 916 if (priv->chip_id == RCAR_GEN2) { 917 ravb_modify(ndev, RIC0, mask, mask); 918 ravb_modify(ndev, TIC, mask, mask); 919 } else { 920 ravb_write(ndev, mask, RIE0); 921 ravb_write(ndev, mask, TIE); 922 } 923 mmiowb(); 924 spin_unlock_irqrestore(&priv->lock, flags); 925 926 /* Receive error message handling */ 927 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 928 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 929 if (priv->rx_over_errors != ndev->stats.rx_over_errors) { 930 ndev->stats.rx_over_errors = priv->rx_over_errors; 931 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n"); 932 } 933 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) { 934 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 935 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n"); 936 } 937 out: 938 return budget - quota; 939 } 940 941 /* PHY state control function */ 942 static void ravb_adjust_link(struct net_device *ndev) 943 { 944 struct ravb_private *priv = netdev_priv(ndev); 945 struct phy_device *phydev = ndev->phydev; 946 bool new_state = false; 947 948 if (phydev->link) { 949 if (phydev->duplex != priv->duplex) { 950 new_state = true; 951 priv->duplex = phydev->duplex; 952 ravb_set_duplex(ndev); 953 } 954 955 if (phydev->speed != priv->speed) { 956 new_state = true; 957 priv->speed = phydev->speed; 958 ravb_set_rate(ndev); 959 } 960 if (!priv->link) { 961 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 962 new_state = true; 963 priv->link = phydev->link; 964 if (priv->no_avb_link) 965 ravb_rcv_snd_enable(ndev); 966 } 967 } else if (priv->link) { 968 new_state = true; 969 priv->link = 0; 970 priv->speed = 0; 971 priv->duplex = -1; 972 if (priv->no_avb_link) 973 ravb_rcv_snd_disable(ndev); 974 } 975 976 if (new_state && netif_msg_link(priv)) 977 phy_print_status(phydev); 978 } 979 980 /* PHY init function */ 981 static int ravb_phy_init(struct net_device *ndev) 982 { 983 struct device_node *np = ndev->dev.parent->of_node; 984 struct ravb_private *priv = netdev_priv(ndev); 985 struct phy_device *phydev; 986 struct device_node *pn; 987 int err; 988 989 priv->link = 0; 990 priv->speed = 0; 991 priv->duplex = -1; 992 993 /* Try connecting to PHY */ 994 pn = of_parse_phandle(np, "phy-handle", 0); 995 if (!pn) { 996 /* In the case of a fixed PHY, the DT node associated 997 * to the PHY is the Ethernet MAC DT node. 998 */ 999 if (of_phy_is_fixed_link(np)) { 1000 err = of_phy_register_fixed_link(np); 1001 if (err) 1002 return err; 1003 } 1004 pn = of_node_get(np); 1005 } 1006 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1007 priv->phy_interface); 1008 of_node_put(pn); 1009 if (!phydev) { 1010 netdev_err(ndev, "failed to connect PHY\n"); 1011 return -ENOENT; 1012 } 1013 1014 /* This driver only support 10/100Mbit speeds on Gen3 1015 * at this time. 1016 */ 1017 if (priv->chip_id == RCAR_GEN3) { 1018 int err; 1019 1020 err = phy_set_max_speed(phydev, SPEED_100); 1021 if (err) { 1022 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1023 phy_disconnect(phydev); 1024 return err; 1025 } 1026 1027 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1028 } 1029 1030 /* 10BASE is not supported */ 1031 phydev->supported &= ~PHY_10BT_FEATURES; 1032 1033 phy_attached_info(phydev); 1034 1035 return 0; 1036 } 1037 1038 /* PHY control start function */ 1039 static int ravb_phy_start(struct net_device *ndev) 1040 { 1041 int error; 1042 1043 error = ravb_phy_init(ndev); 1044 if (error) 1045 return error; 1046 1047 phy_start(ndev->phydev); 1048 1049 return 0; 1050 } 1051 1052 static int ravb_get_link_ksettings(struct net_device *ndev, 1053 struct ethtool_link_ksettings *cmd) 1054 { 1055 struct ravb_private *priv = netdev_priv(ndev); 1056 int error = -ENODEV; 1057 unsigned long flags; 1058 1059 if (ndev->phydev) { 1060 spin_lock_irqsave(&priv->lock, flags); 1061 error = phy_ethtool_ksettings_get(ndev->phydev, cmd); 1062 spin_unlock_irqrestore(&priv->lock, flags); 1063 } 1064 1065 return error; 1066 } 1067 1068 static int ravb_set_link_ksettings(struct net_device *ndev, 1069 const struct ethtool_link_ksettings *cmd) 1070 { 1071 struct ravb_private *priv = netdev_priv(ndev); 1072 unsigned long flags; 1073 int error; 1074 1075 if (!ndev->phydev) 1076 return -ENODEV; 1077 1078 spin_lock_irqsave(&priv->lock, flags); 1079 1080 /* Disable TX and RX */ 1081 ravb_rcv_snd_disable(ndev); 1082 1083 error = phy_ethtool_ksettings_set(ndev->phydev, cmd); 1084 if (error) 1085 goto error_exit; 1086 1087 if (cmd->base.duplex == DUPLEX_FULL) 1088 priv->duplex = 1; 1089 else 1090 priv->duplex = 0; 1091 1092 ravb_set_duplex(ndev); 1093 1094 error_exit: 1095 mdelay(1); 1096 1097 /* Enable TX and RX */ 1098 ravb_rcv_snd_enable(ndev); 1099 1100 mmiowb(); 1101 spin_unlock_irqrestore(&priv->lock, flags); 1102 1103 return error; 1104 } 1105 1106 static int ravb_nway_reset(struct net_device *ndev) 1107 { 1108 struct ravb_private *priv = netdev_priv(ndev); 1109 int error = -ENODEV; 1110 unsigned long flags; 1111 1112 if (ndev->phydev) { 1113 spin_lock_irqsave(&priv->lock, flags); 1114 error = phy_start_aneg(ndev->phydev); 1115 spin_unlock_irqrestore(&priv->lock, flags); 1116 } 1117 1118 return error; 1119 } 1120 1121 static u32 ravb_get_msglevel(struct net_device *ndev) 1122 { 1123 struct ravb_private *priv = netdev_priv(ndev); 1124 1125 return priv->msg_enable; 1126 } 1127 1128 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1129 { 1130 struct ravb_private *priv = netdev_priv(ndev); 1131 1132 priv->msg_enable = value; 1133 } 1134 1135 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1136 "rx_queue_0_current", 1137 "tx_queue_0_current", 1138 "rx_queue_0_dirty", 1139 "tx_queue_0_dirty", 1140 "rx_queue_0_packets", 1141 "tx_queue_0_packets", 1142 "rx_queue_0_bytes", 1143 "tx_queue_0_bytes", 1144 "rx_queue_0_mcast_packets", 1145 "rx_queue_0_errors", 1146 "rx_queue_0_crc_errors", 1147 "rx_queue_0_frame_errors", 1148 "rx_queue_0_length_errors", 1149 "rx_queue_0_missed_errors", 1150 "rx_queue_0_over_errors", 1151 1152 "rx_queue_1_current", 1153 "tx_queue_1_current", 1154 "rx_queue_1_dirty", 1155 "tx_queue_1_dirty", 1156 "rx_queue_1_packets", 1157 "tx_queue_1_packets", 1158 "rx_queue_1_bytes", 1159 "tx_queue_1_bytes", 1160 "rx_queue_1_mcast_packets", 1161 "rx_queue_1_errors", 1162 "rx_queue_1_crc_errors", 1163 "rx_queue_1_frame_errors", 1164 "rx_queue_1_length_errors", 1165 "rx_queue_1_missed_errors", 1166 "rx_queue_1_over_errors", 1167 }; 1168 1169 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1170 1171 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1172 { 1173 switch (sset) { 1174 case ETH_SS_STATS: 1175 return RAVB_STATS_LEN; 1176 default: 1177 return -EOPNOTSUPP; 1178 } 1179 } 1180 1181 static void ravb_get_ethtool_stats(struct net_device *ndev, 1182 struct ethtool_stats *stats, u64 *data) 1183 { 1184 struct ravb_private *priv = netdev_priv(ndev); 1185 int i = 0; 1186 int q; 1187 1188 /* Device-specific stats */ 1189 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1190 struct net_device_stats *stats = &priv->stats[q]; 1191 1192 data[i++] = priv->cur_rx[q]; 1193 data[i++] = priv->cur_tx[q]; 1194 data[i++] = priv->dirty_rx[q]; 1195 data[i++] = priv->dirty_tx[q]; 1196 data[i++] = stats->rx_packets; 1197 data[i++] = stats->tx_packets; 1198 data[i++] = stats->rx_bytes; 1199 data[i++] = stats->tx_bytes; 1200 data[i++] = stats->multicast; 1201 data[i++] = stats->rx_errors; 1202 data[i++] = stats->rx_crc_errors; 1203 data[i++] = stats->rx_frame_errors; 1204 data[i++] = stats->rx_length_errors; 1205 data[i++] = stats->rx_missed_errors; 1206 data[i++] = stats->rx_over_errors; 1207 } 1208 } 1209 1210 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1211 { 1212 switch (stringset) { 1213 case ETH_SS_STATS: 1214 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1215 break; 1216 } 1217 } 1218 1219 static void ravb_get_ringparam(struct net_device *ndev, 1220 struct ethtool_ringparam *ring) 1221 { 1222 struct ravb_private *priv = netdev_priv(ndev); 1223 1224 ring->rx_max_pending = BE_RX_RING_MAX; 1225 ring->tx_max_pending = BE_TX_RING_MAX; 1226 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1227 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1228 } 1229 1230 static int ravb_set_ringparam(struct net_device *ndev, 1231 struct ethtool_ringparam *ring) 1232 { 1233 struct ravb_private *priv = netdev_priv(ndev); 1234 int error; 1235 1236 if (ring->tx_pending > BE_TX_RING_MAX || 1237 ring->rx_pending > BE_RX_RING_MAX || 1238 ring->tx_pending < BE_TX_RING_MIN || 1239 ring->rx_pending < BE_RX_RING_MIN) 1240 return -EINVAL; 1241 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1242 return -EINVAL; 1243 1244 if (netif_running(ndev)) { 1245 netif_device_detach(ndev); 1246 /* Stop PTP Clock driver */ 1247 if (priv->chip_id == RCAR_GEN2) 1248 ravb_ptp_stop(ndev); 1249 /* Wait for DMA stopping */ 1250 error = ravb_stop_dma(ndev); 1251 if (error) { 1252 netdev_err(ndev, 1253 "cannot set ringparam! Any AVB processes are still running?\n"); 1254 return error; 1255 } 1256 synchronize_irq(ndev->irq); 1257 1258 /* Free all the skb's in the RX queue and the DMA buffers. */ 1259 ravb_ring_free(ndev, RAVB_BE); 1260 ravb_ring_free(ndev, RAVB_NC); 1261 } 1262 1263 /* Set new parameters */ 1264 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1265 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1266 1267 if (netif_running(ndev)) { 1268 error = ravb_dmac_init(ndev); 1269 if (error) { 1270 netdev_err(ndev, 1271 "%s: ravb_dmac_init() failed, error %d\n", 1272 __func__, error); 1273 return error; 1274 } 1275 1276 ravb_emac_init(ndev); 1277 1278 /* Initialise PTP Clock driver */ 1279 if (priv->chip_id == RCAR_GEN2) 1280 ravb_ptp_init(ndev, priv->pdev); 1281 1282 netif_device_attach(ndev); 1283 } 1284 1285 return 0; 1286 } 1287 1288 static int ravb_get_ts_info(struct net_device *ndev, 1289 struct ethtool_ts_info *info) 1290 { 1291 struct ravb_private *priv = netdev_priv(ndev); 1292 1293 info->so_timestamping = 1294 SOF_TIMESTAMPING_TX_SOFTWARE | 1295 SOF_TIMESTAMPING_RX_SOFTWARE | 1296 SOF_TIMESTAMPING_SOFTWARE | 1297 SOF_TIMESTAMPING_TX_HARDWARE | 1298 SOF_TIMESTAMPING_RX_HARDWARE | 1299 SOF_TIMESTAMPING_RAW_HARDWARE; 1300 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1301 info->rx_filters = 1302 (1 << HWTSTAMP_FILTER_NONE) | 1303 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1304 (1 << HWTSTAMP_FILTER_ALL); 1305 info->phc_index = ptp_clock_index(priv->ptp.clock); 1306 1307 return 0; 1308 } 1309 1310 static const struct ethtool_ops ravb_ethtool_ops = { 1311 .nway_reset = ravb_nway_reset, 1312 .get_msglevel = ravb_get_msglevel, 1313 .set_msglevel = ravb_set_msglevel, 1314 .get_link = ethtool_op_get_link, 1315 .get_strings = ravb_get_strings, 1316 .get_ethtool_stats = ravb_get_ethtool_stats, 1317 .get_sset_count = ravb_get_sset_count, 1318 .get_ringparam = ravb_get_ringparam, 1319 .set_ringparam = ravb_set_ringparam, 1320 .get_ts_info = ravb_get_ts_info, 1321 .get_link_ksettings = ravb_get_link_ksettings, 1322 .set_link_ksettings = ravb_set_link_ksettings, 1323 }; 1324 1325 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1326 struct net_device *ndev, struct device *dev, 1327 const char *ch) 1328 { 1329 char *name; 1330 int error; 1331 1332 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1333 if (!name) 1334 return -ENOMEM; 1335 error = request_irq(irq, handler, 0, name, ndev); 1336 if (error) 1337 netdev_err(ndev, "cannot request IRQ %s\n", name); 1338 1339 return error; 1340 } 1341 1342 /* Network device open function for Ethernet AVB */ 1343 static int ravb_open(struct net_device *ndev) 1344 { 1345 struct ravb_private *priv = netdev_priv(ndev); 1346 struct platform_device *pdev = priv->pdev; 1347 struct device *dev = &pdev->dev; 1348 int error; 1349 1350 napi_enable(&priv->napi[RAVB_BE]); 1351 napi_enable(&priv->napi[RAVB_NC]); 1352 1353 if (priv->chip_id == RCAR_GEN2) { 1354 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1355 ndev->name, ndev); 1356 if (error) { 1357 netdev_err(ndev, "cannot request IRQ\n"); 1358 goto out_napi_off; 1359 } 1360 } else { 1361 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1362 dev, "ch22:multi"); 1363 if (error) 1364 goto out_napi_off; 1365 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1366 dev, "ch24:emac"); 1367 if (error) 1368 goto out_free_irq; 1369 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1370 ndev, dev, "ch0:rx_be"); 1371 if (error) 1372 goto out_free_irq_emac; 1373 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1374 ndev, dev, "ch18:tx_be"); 1375 if (error) 1376 goto out_free_irq_be_rx; 1377 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1378 ndev, dev, "ch1:rx_nc"); 1379 if (error) 1380 goto out_free_irq_be_tx; 1381 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1382 ndev, dev, "ch19:tx_nc"); 1383 if (error) 1384 goto out_free_irq_nc_rx; 1385 } 1386 1387 /* Device init */ 1388 error = ravb_dmac_init(ndev); 1389 if (error) 1390 goto out_free_irq_nc_tx; 1391 ravb_emac_init(ndev); 1392 1393 /* Initialise PTP Clock driver */ 1394 if (priv->chip_id == RCAR_GEN2) 1395 ravb_ptp_init(ndev, priv->pdev); 1396 1397 netif_tx_start_all_queues(ndev); 1398 1399 /* PHY control start */ 1400 error = ravb_phy_start(ndev); 1401 if (error) 1402 goto out_ptp_stop; 1403 1404 return 0; 1405 1406 out_ptp_stop: 1407 /* Stop PTP Clock driver */ 1408 if (priv->chip_id == RCAR_GEN2) 1409 ravb_ptp_stop(ndev); 1410 out_free_irq_nc_tx: 1411 if (priv->chip_id == RCAR_GEN2) 1412 goto out_free_irq; 1413 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1414 out_free_irq_nc_rx: 1415 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1416 out_free_irq_be_tx: 1417 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1418 out_free_irq_be_rx: 1419 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1420 out_free_irq_emac: 1421 free_irq(priv->emac_irq, ndev); 1422 out_free_irq: 1423 free_irq(ndev->irq, ndev); 1424 out_napi_off: 1425 napi_disable(&priv->napi[RAVB_NC]); 1426 napi_disable(&priv->napi[RAVB_BE]); 1427 return error; 1428 } 1429 1430 /* Timeout function for Ethernet AVB */ 1431 static void ravb_tx_timeout(struct net_device *ndev) 1432 { 1433 struct ravb_private *priv = netdev_priv(ndev); 1434 1435 netif_err(priv, tx_err, ndev, 1436 "transmit timed out, status %08x, resetting...\n", 1437 ravb_read(ndev, ISS)); 1438 1439 /* tx_errors count up */ 1440 ndev->stats.tx_errors++; 1441 1442 schedule_work(&priv->work); 1443 } 1444 1445 static void ravb_tx_timeout_work(struct work_struct *work) 1446 { 1447 struct ravb_private *priv = container_of(work, struct ravb_private, 1448 work); 1449 struct net_device *ndev = priv->ndev; 1450 1451 netif_tx_stop_all_queues(ndev); 1452 1453 /* Stop PTP Clock driver */ 1454 if (priv->chip_id == RCAR_GEN2) 1455 ravb_ptp_stop(ndev); 1456 1457 /* Wait for DMA stopping */ 1458 ravb_stop_dma(ndev); 1459 1460 ravb_ring_free(ndev, RAVB_BE); 1461 ravb_ring_free(ndev, RAVB_NC); 1462 1463 /* Device init */ 1464 ravb_dmac_init(ndev); 1465 ravb_emac_init(ndev); 1466 1467 /* Initialise PTP Clock driver */ 1468 if (priv->chip_id == RCAR_GEN2) 1469 ravb_ptp_init(ndev, priv->pdev); 1470 1471 netif_tx_start_all_queues(ndev); 1472 } 1473 1474 /* Packet transmit function for Ethernet AVB */ 1475 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1476 { 1477 struct ravb_private *priv = netdev_priv(ndev); 1478 u16 q = skb_get_queue_mapping(skb); 1479 struct ravb_tstamp_skb *ts_skb; 1480 struct ravb_tx_desc *desc; 1481 unsigned long flags; 1482 u32 dma_addr; 1483 void *buffer; 1484 u32 entry; 1485 u32 len; 1486 1487 spin_lock_irqsave(&priv->lock, flags); 1488 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1489 NUM_TX_DESC) { 1490 netif_err(priv, tx_queued, ndev, 1491 "still transmitting with the full ring!\n"); 1492 netif_stop_subqueue(ndev, q); 1493 spin_unlock_irqrestore(&priv->lock, flags); 1494 return NETDEV_TX_BUSY; 1495 } 1496 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); 1497 priv->tx_skb[q][entry / NUM_TX_DESC] = skb; 1498 1499 if (skb_put_padto(skb, ETH_ZLEN)) 1500 goto drop; 1501 1502 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1503 entry / NUM_TX_DESC * DPTR_ALIGN; 1504 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1505 memcpy(buffer, skb->data, len); 1506 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1507 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1508 goto drop; 1509 1510 desc = &priv->tx_ring[q][entry]; 1511 desc->ds_tagl = cpu_to_le16(len); 1512 desc->dptr = cpu_to_le32(dma_addr); 1513 1514 buffer = skb->data + len; 1515 len = skb->len - len; 1516 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1517 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1518 goto unmap; 1519 1520 desc++; 1521 desc->ds_tagl = cpu_to_le16(len); 1522 desc->dptr = cpu_to_le32(dma_addr); 1523 1524 /* TX timestamp required */ 1525 if (q == RAVB_NC) { 1526 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1527 if (!ts_skb) { 1528 desc--; 1529 dma_unmap_single(ndev->dev.parent, dma_addr, len, 1530 DMA_TO_DEVICE); 1531 goto unmap; 1532 } 1533 ts_skb->skb = skb; 1534 ts_skb->tag = priv->ts_skb_tag++; 1535 priv->ts_skb_tag &= 0x3ff; 1536 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1537 1538 /* TAG and timestamp required flag */ 1539 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1540 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1541 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12); 1542 } 1543 1544 skb_tx_timestamp(skb); 1545 /* Descriptor type must be set after all the above writes */ 1546 dma_wmb(); 1547 desc->die_dt = DT_FEND; 1548 desc--; 1549 desc->die_dt = DT_FSTART; 1550 1551 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1552 1553 priv->cur_tx[q] += NUM_TX_DESC; 1554 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1555 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q)) 1556 netif_stop_subqueue(ndev, q); 1557 1558 exit: 1559 mmiowb(); 1560 spin_unlock_irqrestore(&priv->lock, flags); 1561 return NETDEV_TX_OK; 1562 1563 unmap: 1564 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1565 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1566 drop: 1567 dev_kfree_skb_any(skb); 1568 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; 1569 goto exit; 1570 } 1571 1572 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1573 void *accel_priv, select_queue_fallback_t fallback) 1574 { 1575 /* If skb needs TX timestamp, it is handled in network control queue */ 1576 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1577 RAVB_BE; 1578 1579 } 1580 1581 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1582 { 1583 struct ravb_private *priv = netdev_priv(ndev); 1584 struct net_device_stats *nstats, *stats0, *stats1; 1585 1586 nstats = &ndev->stats; 1587 stats0 = &priv->stats[RAVB_BE]; 1588 stats1 = &priv->stats[RAVB_NC]; 1589 1590 nstats->tx_dropped += ravb_read(ndev, TROCR); 1591 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1592 nstats->collisions += ravb_read(ndev, CDCR); 1593 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1594 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1595 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1596 1597 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1598 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1599 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1600 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1601 1602 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1603 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1604 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1605 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1606 nstats->multicast = stats0->multicast + stats1->multicast; 1607 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1608 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1609 nstats->rx_frame_errors = 1610 stats0->rx_frame_errors + stats1->rx_frame_errors; 1611 nstats->rx_length_errors = 1612 stats0->rx_length_errors + stats1->rx_length_errors; 1613 nstats->rx_missed_errors = 1614 stats0->rx_missed_errors + stats1->rx_missed_errors; 1615 nstats->rx_over_errors = 1616 stats0->rx_over_errors + stats1->rx_over_errors; 1617 1618 return nstats; 1619 } 1620 1621 /* Update promiscuous bit */ 1622 static void ravb_set_rx_mode(struct net_device *ndev) 1623 { 1624 struct ravb_private *priv = netdev_priv(ndev); 1625 unsigned long flags; 1626 1627 spin_lock_irqsave(&priv->lock, flags); 1628 ravb_modify(ndev, ECMR, ECMR_PRM, 1629 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1630 mmiowb(); 1631 spin_unlock_irqrestore(&priv->lock, flags); 1632 } 1633 1634 /* Device close function for Ethernet AVB */ 1635 static int ravb_close(struct net_device *ndev) 1636 { 1637 struct ravb_private *priv = netdev_priv(ndev); 1638 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1639 1640 netif_tx_stop_all_queues(ndev); 1641 1642 /* Disable interrupts by clearing the interrupt masks. */ 1643 ravb_write(ndev, 0, RIC0); 1644 ravb_write(ndev, 0, RIC2); 1645 ravb_write(ndev, 0, TIC); 1646 1647 /* Stop PTP Clock driver */ 1648 if (priv->chip_id == RCAR_GEN2) 1649 ravb_ptp_stop(ndev); 1650 1651 /* Set the config mode to stop the AVB-DMAC's processes */ 1652 if (ravb_stop_dma(ndev) < 0) 1653 netdev_err(ndev, 1654 "device will be stopped after h/w processes are done.\n"); 1655 1656 /* Clear the timestamp list */ 1657 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1658 list_del(&ts_skb->list); 1659 kfree(ts_skb); 1660 } 1661 1662 /* PHY disconnect */ 1663 if (ndev->phydev) { 1664 phy_stop(ndev->phydev); 1665 phy_disconnect(ndev->phydev); 1666 } 1667 1668 if (priv->chip_id != RCAR_GEN2) { 1669 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1670 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1671 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1672 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1673 free_irq(priv->emac_irq, ndev); 1674 } 1675 free_irq(ndev->irq, ndev); 1676 1677 napi_disable(&priv->napi[RAVB_NC]); 1678 napi_disable(&priv->napi[RAVB_BE]); 1679 1680 /* Free all the skb's in the RX queue and the DMA buffers. */ 1681 ravb_ring_free(ndev, RAVB_BE); 1682 ravb_ring_free(ndev, RAVB_NC); 1683 1684 return 0; 1685 } 1686 1687 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1688 { 1689 struct ravb_private *priv = netdev_priv(ndev); 1690 struct hwtstamp_config config; 1691 1692 config.flags = 0; 1693 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1694 HWTSTAMP_TX_OFF; 1695 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1696 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1697 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1698 config.rx_filter = HWTSTAMP_FILTER_ALL; 1699 else 1700 config.rx_filter = HWTSTAMP_FILTER_NONE; 1701 1702 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1703 -EFAULT : 0; 1704 } 1705 1706 /* Control hardware time stamping */ 1707 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1708 { 1709 struct ravb_private *priv = netdev_priv(ndev); 1710 struct hwtstamp_config config; 1711 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1712 u32 tstamp_tx_ctrl; 1713 1714 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1715 return -EFAULT; 1716 1717 /* Reserved for future extensions */ 1718 if (config.flags) 1719 return -EINVAL; 1720 1721 switch (config.tx_type) { 1722 case HWTSTAMP_TX_OFF: 1723 tstamp_tx_ctrl = 0; 1724 break; 1725 case HWTSTAMP_TX_ON: 1726 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1727 break; 1728 default: 1729 return -ERANGE; 1730 } 1731 1732 switch (config.rx_filter) { 1733 case HWTSTAMP_FILTER_NONE: 1734 tstamp_rx_ctrl = 0; 1735 break; 1736 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1737 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1738 break; 1739 default: 1740 config.rx_filter = HWTSTAMP_FILTER_ALL; 1741 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1742 } 1743 1744 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1745 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1746 1747 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1748 -EFAULT : 0; 1749 } 1750 1751 /* ioctl to device function */ 1752 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1753 { 1754 struct phy_device *phydev = ndev->phydev; 1755 1756 if (!netif_running(ndev)) 1757 return -EINVAL; 1758 1759 if (!phydev) 1760 return -ENODEV; 1761 1762 switch (cmd) { 1763 case SIOCGHWTSTAMP: 1764 return ravb_hwtstamp_get(ndev, req); 1765 case SIOCSHWTSTAMP: 1766 return ravb_hwtstamp_set(ndev, req); 1767 } 1768 1769 return phy_mii_ioctl(phydev, req, cmd); 1770 } 1771 1772 static const struct net_device_ops ravb_netdev_ops = { 1773 .ndo_open = ravb_open, 1774 .ndo_stop = ravb_close, 1775 .ndo_start_xmit = ravb_start_xmit, 1776 .ndo_select_queue = ravb_select_queue, 1777 .ndo_get_stats = ravb_get_stats, 1778 .ndo_set_rx_mode = ravb_set_rx_mode, 1779 .ndo_tx_timeout = ravb_tx_timeout, 1780 .ndo_do_ioctl = ravb_do_ioctl, 1781 .ndo_validate_addr = eth_validate_addr, 1782 .ndo_set_mac_address = eth_mac_addr, 1783 .ndo_change_mtu = eth_change_mtu, 1784 }; 1785 1786 /* MDIO bus init function */ 1787 static int ravb_mdio_init(struct ravb_private *priv) 1788 { 1789 struct platform_device *pdev = priv->pdev; 1790 struct device *dev = &pdev->dev; 1791 int error; 1792 1793 /* Bitbang init */ 1794 priv->mdiobb.ops = &bb_ops; 1795 1796 /* MII controller setting */ 1797 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1798 if (!priv->mii_bus) 1799 return -ENOMEM; 1800 1801 /* Hook up MII support for ethtool */ 1802 priv->mii_bus->name = "ravb_mii"; 1803 priv->mii_bus->parent = dev; 1804 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1805 pdev->name, pdev->id); 1806 1807 /* Register MDIO bus */ 1808 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1809 if (error) 1810 goto out_free_bus; 1811 1812 return 0; 1813 1814 out_free_bus: 1815 free_mdio_bitbang(priv->mii_bus); 1816 return error; 1817 } 1818 1819 /* MDIO bus release function */ 1820 static int ravb_mdio_release(struct ravb_private *priv) 1821 { 1822 /* Unregister mdio bus */ 1823 mdiobus_unregister(priv->mii_bus); 1824 1825 /* Free bitbang info */ 1826 free_mdio_bitbang(priv->mii_bus); 1827 1828 return 0; 1829 } 1830 1831 static const struct of_device_id ravb_match_table[] = { 1832 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1833 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1834 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1835 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1836 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1837 { } 1838 }; 1839 MODULE_DEVICE_TABLE(of, ravb_match_table); 1840 1841 static int ravb_set_gti(struct net_device *ndev) 1842 { 1843 1844 struct device *dev = ndev->dev.parent; 1845 struct device_node *np = dev->of_node; 1846 unsigned long rate; 1847 struct clk *clk; 1848 uint64_t inc; 1849 1850 clk = of_clk_get(np, 0); 1851 if (IS_ERR(clk)) { 1852 dev_err(dev, "could not get clock\n"); 1853 return PTR_ERR(clk); 1854 } 1855 1856 rate = clk_get_rate(clk); 1857 clk_put(clk); 1858 1859 if (!rate) 1860 return -EINVAL; 1861 1862 inc = 1000000000ULL << 20; 1863 do_div(inc, rate); 1864 1865 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1866 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1867 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1868 return -EINVAL; 1869 } 1870 1871 ravb_write(ndev, inc, GTI); 1872 1873 return 0; 1874 } 1875 1876 static void ravb_set_config_mode(struct net_device *ndev) 1877 { 1878 struct ravb_private *priv = netdev_priv(ndev); 1879 1880 if (priv->chip_id == RCAR_GEN2) { 1881 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1882 /* Set CSEL value */ 1883 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1884 } else { 1885 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1886 CCC_GAC | CCC_CSEL_HPB); 1887 } 1888 } 1889 1890 static int ravb_probe(struct platform_device *pdev) 1891 { 1892 struct device_node *np = pdev->dev.of_node; 1893 struct ravb_private *priv; 1894 enum ravb_chip_id chip_id; 1895 struct net_device *ndev; 1896 int error, irq, q; 1897 struct resource *res; 1898 int i; 1899 1900 if (!np) { 1901 dev_err(&pdev->dev, 1902 "this driver is required to be instantiated from device tree\n"); 1903 return -EINVAL; 1904 } 1905 1906 /* Get base address */ 1907 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1908 if (!res) { 1909 dev_err(&pdev->dev, "invalid resource\n"); 1910 return -EINVAL; 1911 } 1912 1913 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 1914 NUM_TX_QUEUE, NUM_RX_QUEUE); 1915 if (!ndev) 1916 return -ENOMEM; 1917 1918 pm_runtime_enable(&pdev->dev); 1919 pm_runtime_get_sync(&pdev->dev); 1920 1921 /* The Ether-specific entries in the device structure. */ 1922 ndev->base_addr = res->start; 1923 1924 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 1925 1926 if (chip_id == RCAR_GEN3) 1927 irq = platform_get_irq_byname(pdev, "ch22"); 1928 else 1929 irq = platform_get_irq(pdev, 0); 1930 if (irq < 0) { 1931 error = irq; 1932 goto out_release; 1933 } 1934 ndev->irq = irq; 1935 1936 SET_NETDEV_DEV(ndev, &pdev->dev); 1937 1938 priv = netdev_priv(ndev); 1939 priv->ndev = ndev; 1940 priv->pdev = pdev; 1941 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 1942 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 1943 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 1944 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 1945 priv->addr = devm_ioremap_resource(&pdev->dev, res); 1946 if (IS_ERR(priv->addr)) { 1947 error = PTR_ERR(priv->addr); 1948 goto out_release; 1949 } 1950 1951 spin_lock_init(&priv->lock); 1952 INIT_WORK(&priv->work, ravb_tx_timeout_work); 1953 1954 priv->phy_interface = of_get_phy_mode(np); 1955 1956 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 1957 priv->avb_link_active_low = 1958 of_property_read_bool(np, "renesas,ether-link-active-low"); 1959 1960 if (chip_id == RCAR_GEN3) { 1961 irq = platform_get_irq_byname(pdev, "ch24"); 1962 if (irq < 0) { 1963 error = irq; 1964 goto out_release; 1965 } 1966 priv->emac_irq = irq; 1967 for (i = 0; i < NUM_RX_QUEUE; i++) { 1968 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 1969 if (irq < 0) { 1970 error = irq; 1971 goto out_release; 1972 } 1973 priv->rx_irqs[i] = irq; 1974 } 1975 for (i = 0; i < NUM_TX_QUEUE; i++) { 1976 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 1977 if (irq < 0) { 1978 error = irq; 1979 goto out_release; 1980 } 1981 priv->tx_irqs[i] = irq; 1982 } 1983 } 1984 1985 priv->chip_id = chip_id; 1986 1987 /* Set function */ 1988 ndev->netdev_ops = &ravb_netdev_ops; 1989 ndev->ethtool_ops = &ravb_ethtool_ops; 1990 1991 /* Set AVB config mode */ 1992 ravb_set_config_mode(ndev); 1993 1994 /* Set GTI value */ 1995 error = ravb_set_gti(ndev); 1996 if (error) 1997 goto out_release; 1998 1999 /* Request GTI loading */ 2000 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2001 2002 /* Allocate descriptor base address table */ 2003 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2004 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2005 &priv->desc_bat_dma, GFP_KERNEL); 2006 if (!priv->desc_bat) { 2007 dev_err(&pdev->dev, 2008 "Cannot allocate desc base address table (size %d bytes)\n", 2009 priv->desc_bat_size); 2010 error = -ENOMEM; 2011 goto out_release; 2012 } 2013 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2014 priv->desc_bat[q].die_dt = DT_EOS; 2015 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2016 2017 /* Initialise HW timestamp list */ 2018 INIT_LIST_HEAD(&priv->ts_skb_list); 2019 2020 /* Initialise PTP Clock driver */ 2021 if (chip_id != RCAR_GEN2) 2022 ravb_ptp_init(ndev, pdev); 2023 2024 /* Debug message level */ 2025 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2026 2027 /* Read and set MAC address */ 2028 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2029 if (!is_valid_ether_addr(ndev->dev_addr)) { 2030 dev_warn(&pdev->dev, 2031 "no valid MAC address supplied, using a random one\n"); 2032 eth_hw_addr_random(ndev); 2033 } 2034 2035 /* MDIO bus init */ 2036 error = ravb_mdio_init(priv); 2037 if (error) { 2038 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2039 goto out_dma_free; 2040 } 2041 2042 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2043 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2044 2045 /* Network device register */ 2046 error = register_netdev(ndev); 2047 if (error) 2048 goto out_napi_del; 2049 2050 /* Print device information */ 2051 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2052 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2053 2054 platform_set_drvdata(pdev, ndev); 2055 2056 return 0; 2057 2058 out_napi_del: 2059 netif_napi_del(&priv->napi[RAVB_NC]); 2060 netif_napi_del(&priv->napi[RAVB_BE]); 2061 ravb_mdio_release(priv); 2062 out_dma_free: 2063 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2064 priv->desc_bat_dma); 2065 2066 /* Stop PTP Clock driver */ 2067 if (chip_id != RCAR_GEN2) 2068 ravb_ptp_stop(ndev); 2069 out_release: 2070 if (ndev) 2071 free_netdev(ndev); 2072 2073 pm_runtime_put(&pdev->dev); 2074 pm_runtime_disable(&pdev->dev); 2075 return error; 2076 } 2077 2078 static int ravb_remove(struct platform_device *pdev) 2079 { 2080 struct net_device *ndev = platform_get_drvdata(pdev); 2081 struct ravb_private *priv = netdev_priv(ndev); 2082 2083 /* Stop PTP Clock driver */ 2084 if (priv->chip_id != RCAR_GEN2) 2085 ravb_ptp_stop(ndev); 2086 2087 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2088 priv->desc_bat_dma); 2089 /* Set reset mode */ 2090 ravb_write(ndev, CCC_OPC_RESET, CCC); 2091 pm_runtime_put_sync(&pdev->dev); 2092 unregister_netdev(ndev); 2093 netif_napi_del(&priv->napi[RAVB_NC]); 2094 netif_napi_del(&priv->napi[RAVB_BE]); 2095 ravb_mdio_release(priv); 2096 pm_runtime_disable(&pdev->dev); 2097 free_netdev(ndev); 2098 platform_set_drvdata(pdev, NULL); 2099 2100 return 0; 2101 } 2102 2103 static int __maybe_unused ravb_suspend(struct device *dev) 2104 { 2105 struct net_device *ndev = dev_get_drvdata(dev); 2106 int ret = 0; 2107 2108 if (netif_running(ndev)) { 2109 netif_device_detach(ndev); 2110 ret = ravb_close(ndev); 2111 } 2112 2113 return ret; 2114 } 2115 2116 static int __maybe_unused ravb_resume(struct device *dev) 2117 { 2118 struct net_device *ndev = dev_get_drvdata(dev); 2119 struct ravb_private *priv = netdev_priv(ndev); 2120 int ret = 0; 2121 2122 /* All register have been reset to default values. 2123 * Restore all registers which where setup at probe time and 2124 * reopen device if it was running before system suspended. 2125 */ 2126 2127 /* Set AVB config mode */ 2128 ravb_set_config_mode(ndev); 2129 2130 /* Set GTI value */ 2131 ret = ravb_set_gti(ndev); 2132 if (ret) 2133 return ret; 2134 2135 /* Request GTI loading */ 2136 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2137 2138 /* Restore descriptor base address table */ 2139 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2140 2141 if (netif_running(ndev)) { 2142 ret = ravb_open(ndev); 2143 if (ret < 0) 2144 return ret; 2145 netif_device_attach(ndev); 2146 } 2147 2148 return ret; 2149 } 2150 2151 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2152 { 2153 /* Runtime PM callback shared between ->runtime_suspend() 2154 * and ->runtime_resume(). Simply returns success. 2155 * 2156 * This driver re-initializes all registers after 2157 * pm_runtime_get_sync() anyway so there is no need 2158 * to save and restore registers here. 2159 */ 2160 return 0; 2161 } 2162 2163 static const struct dev_pm_ops ravb_dev_pm_ops = { 2164 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2165 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2166 }; 2167 2168 static struct platform_driver ravb_driver = { 2169 .probe = ravb_probe, 2170 .remove = ravb_remove, 2171 .driver = { 2172 .name = "ravb", 2173 .pm = &ravb_dev_pm_ops, 2174 .of_match_table = ravb_match_table, 2175 }, 2176 }; 2177 2178 module_platform_driver(ravb_driver); 2179 2180 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2181 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2182 MODULE_LICENSE("GPL v2"); 2183