1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 33 #include <asm/div64.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 44 "ch0", /* RAVB_BE */ 45 "ch1", /* RAVB_NC */ 46 }; 47 48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 49 "ch18", /* RAVB_BE */ 50 "ch19", /* RAVB_NC */ 51 }; 52 53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 54 u32 set) 55 { 56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 57 } 58 59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 60 { 61 int i; 62 63 for (i = 0; i < 10000; i++) { 64 if ((ravb_read(ndev, reg) & mask) == value) 65 return 0; 66 udelay(10); 67 } 68 return -ETIMEDOUT; 69 } 70 71 static int ravb_config(struct net_device *ndev) 72 { 73 int error; 74 75 /* Set config mode */ 76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 77 /* Check if the operating mode is changed to the config mode */ 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 79 if (error) 80 netdev_err(ndev, "failed to switch device to config mode\n"); 81 82 return error; 83 } 84 85 static void ravb_set_rate(struct net_device *ndev) 86 { 87 struct ravb_private *priv = netdev_priv(ndev); 88 89 switch (priv->speed) { 90 case 100: /* 100BASE */ 91 ravb_write(ndev, GECMR_SPEED_100, GECMR); 92 break; 93 case 1000: /* 1000BASE */ 94 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 95 break; 96 } 97 } 98 99 static void ravb_set_buffer_align(struct sk_buff *skb) 100 { 101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 102 103 if (reserve) 104 skb_reserve(skb, RAVB_ALIGN - reserve); 105 } 106 107 /* Get MAC address from the MAC address registers 108 * 109 * Ethernet AVB device doesn't have ROM for MAC address. 110 * This function gets the MAC address that was used by a bootloader. 111 */ 112 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 113 { 114 if (!IS_ERR(mac)) { 115 ether_addr_copy(ndev->dev_addr, mac); 116 } else { 117 u32 mahr = ravb_read(ndev, MAHR); 118 u32 malr = ravb_read(ndev, MALR); 119 120 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 121 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 122 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 123 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 124 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 125 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 126 } 127 } 128 129 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 130 { 131 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 132 mdiobb); 133 134 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 135 } 136 137 /* MDC pin control */ 138 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 139 { 140 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 141 } 142 143 /* Data I/O pin control */ 144 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 145 { 146 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 147 } 148 149 /* Set data bit */ 150 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 151 { 152 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 153 } 154 155 /* Get data bit */ 156 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 157 { 158 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 159 mdiobb); 160 161 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 162 } 163 164 /* MDIO bus control struct */ 165 static struct mdiobb_ops bb_ops = { 166 .owner = THIS_MODULE, 167 .set_mdc = ravb_set_mdc, 168 .set_mdio_dir = ravb_set_mdio_dir, 169 .set_mdio_data = ravb_set_mdio_data, 170 .get_mdio_data = ravb_get_mdio_data, 171 }; 172 173 /* Free TX skb function for AVB-IP */ 174 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 175 { 176 struct ravb_private *priv = netdev_priv(ndev); 177 struct net_device_stats *stats = &priv->stats[q]; 178 int num_tx_desc = priv->num_tx_desc; 179 struct ravb_tx_desc *desc; 180 int free_num = 0; 181 int entry; 182 u32 size; 183 184 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 185 bool txed; 186 187 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 188 num_tx_desc); 189 desc = &priv->tx_ring[q][entry]; 190 txed = desc->die_dt == DT_FEMPTY; 191 if (free_txed_only && !txed) 192 break; 193 /* Descriptor type must be checked before all other reads */ 194 dma_rmb(); 195 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 196 /* Free the original skb. */ 197 if (priv->tx_skb[q][entry / num_tx_desc]) { 198 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 199 size, DMA_TO_DEVICE); 200 /* Last packet descriptor? */ 201 if (entry % num_tx_desc == num_tx_desc - 1) { 202 entry /= num_tx_desc; 203 dev_kfree_skb_any(priv->tx_skb[q][entry]); 204 priv->tx_skb[q][entry] = NULL; 205 if (txed) 206 stats->tx_packets++; 207 } 208 free_num++; 209 } 210 if (txed) 211 stats->tx_bytes += size; 212 desc->die_dt = DT_EEMPTY; 213 } 214 return free_num; 215 } 216 217 /* Free skb's and DMA buffers for Ethernet AVB */ 218 static void ravb_ring_free(struct net_device *ndev, int q) 219 { 220 struct ravb_private *priv = netdev_priv(ndev); 221 int num_tx_desc = priv->num_tx_desc; 222 int ring_size; 223 int i; 224 225 if (priv->rx_ring[q]) { 226 for (i = 0; i < priv->num_rx_ring[q]; i++) { 227 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 228 229 if (!dma_mapping_error(ndev->dev.parent, 230 le32_to_cpu(desc->dptr))) 231 dma_unmap_single(ndev->dev.parent, 232 le32_to_cpu(desc->dptr), 233 priv->rx_buf_sz, 234 DMA_FROM_DEVICE); 235 } 236 ring_size = sizeof(struct ravb_ex_rx_desc) * 237 (priv->num_rx_ring[q] + 1); 238 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 239 priv->rx_desc_dma[q]); 240 priv->rx_ring[q] = NULL; 241 } 242 243 if (priv->tx_ring[q]) { 244 ravb_tx_free(ndev, q, false); 245 246 ring_size = sizeof(struct ravb_tx_desc) * 247 (priv->num_tx_ring[q] * num_tx_desc + 1); 248 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 249 priv->tx_desc_dma[q]); 250 priv->tx_ring[q] = NULL; 251 } 252 253 /* Free RX skb ringbuffer */ 254 if (priv->rx_skb[q]) { 255 for (i = 0; i < priv->num_rx_ring[q]; i++) 256 dev_kfree_skb(priv->rx_skb[q][i]); 257 } 258 kfree(priv->rx_skb[q]); 259 priv->rx_skb[q] = NULL; 260 261 /* Free aligned TX buffers */ 262 kfree(priv->tx_align[q]); 263 priv->tx_align[q] = NULL; 264 265 /* Free TX skb ringbuffer. 266 * SKBs are freed by ravb_tx_free() call above. 267 */ 268 kfree(priv->tx_skb[q]); 269 priv->tx_skb[q] = NULL; 270 } 271 272 /* Format skb and descriptor buffer for Ethernet AVB */ 273 static void ravb_ring_format(struct net_device *ndev, int q) 274 { 275 struct ravb_private *priv = netdev_priv(ndev); 276 int num_tx_desc = priv->num_tx_desc; 277 struct ravb_ex_rx_desc *rx_desc; 278 struct ravb_tx_desc *tx_desc; 279 struct ravb_desc *desc; 280 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 281 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 282 num_tx_desc; 283 dma_addr_t dma_addr; 284 int i; 285 286 priv->cur_rx[q] = 0; 287 priv->cur_tx[q] = 0; 288 priv->dirty_rx[q] = 0; 289 priv->dirty_tx[q] = 0; 290 291 memset(priv->rx_ring[q], 0, rx_ring_size); 292 /* Build RX ring buffer */ 293 for (i = 0; i < priv->num_rx_ring[q]; i++) { 294 /* RX descriptor */ 295 rx_desc = &priv->rx_ring[q][i]; 296 rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 297 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 298 priv->rx_buf_sz, 299 DMA_FROM_DEVICE); 300 /* We just set the data size to 0 for a failed mapping which 301 * should prevent DMA from happening... 302 */ 303 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 304 rx_desc->ds_cc = cpu_to_le16(0); 305 rx_desc->dptr = cpu_to_le32(dma_addr); 306 rx_desc->die_dt = DT_FEMPTY; 307 } 308 rx_desc = &priv->rx_ring[q][i]; 309 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 310 rx_desc->die_dt = DT_LINKFIX; /* type */ 311 312 memset(priv->tx_ring[q], 0, tx_ring_size); 313 /* Build TX ring buffer */ 314 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 315 i++, tx_desc++) { 316 tx_desc->die_dt = DT_EEMPTY; 317 if (num_tx_desc > 1) { 318 tx_desc++; 319 tx_desc->die_dt = DT_EEMPTY; 320 } 321 } 322 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 323 tx_desc->die_dt = DT_LINKFIX; /* type */ 324 325 /* RX descriptor base address for best effort */ 326 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 327 desc->die_dt = DT_LINKFIX; /* type */ 328 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 329 330 /* TX descriptor base address for best effort */ 331 desc = &priv->desc_bat[q]; 332 desc->die_dt = DT_LINKFIX; /* type */ 333 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 334 } 335 336 /* Init skb and descriptor buffer for Ethernet AVB */ 337 static int ravb_ring_init(struct net_device *ndev, int q) 338 { 339 struct ravb_private *priv = netdev_priv(ndev); 340 int num_tx_desc = priv->num_tx_desc; 341 struct sk_buff *skb; 342 int ring_size; 343 int i; 344 345 priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) + 346 ETH_HLEN + VLAN_HLEN + sizeof(__sum16); 347 348 /* Allocate RX and TX skb rings */ 349 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 350 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 351 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 352 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 353 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 354 goto error; 355 356 for (i = 0; i < priv->num_rx_ring[q]; i++) { 357 skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1); 358 if (!skb) 359 goto error; 360 ravb_set_buffer_align(skb); 361 priv->rx_skb[q][i] = skb; 362 } 363 364 if (num_tx_desc > 1) { 365 /* Allocate rings for the aligned buffers */ 366 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 367 DPTR_ALIGN - 1, GFP_KERNEL); 368 if (!priv->tx_align[q]) 369 goto error; 370 } 371 372 /* Allocate all RX descriptors. */ 373 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 374 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 375 &priv->rx_desc_dma[q], 376 GFP_KERNEL); 377 if (!priv->rx_ring[q]) 378 goto error; 379 380 priv->dirty_rx[q] = 0; 381 382 /* Allocate all TX descriptors. */ 383 ring_size = sizeof(struct ravb_tx_desc) * 384 (priv->num_tx_ring[q] * num_tx_desc + 1); 385 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 386 &priv->tx_desc_dma[q], 387 GFP_KERNEL); 388 if (!priv->tx_ring[q]) 389 goto error; 390 391 return 0; 392 393 error: 394 ravb_ring_free(ndev, q); 395 396 return -ENOMEM; 397 } 398 399 /* E-MAC init function */ 400 static void ravb_emac_init(struct net_device *ndev) 401 { 402 /* Receive frame limit set register */ 403 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 404 405 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 406 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 407 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 408 ECMR_TE | ECMR_RE, ECMR); 409 410 ravb_set_rate(ndev); 411 412 /* Set MAC address */ 413 ravb_write(ndev, 414 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 415 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 416 ravb_write(ndev, 417 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 418 419 /* E-MAC status register clear */ 420 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 421 422 /* E-MAC interrupt enable register */ 423 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 424 } 425 426 /* Device init function for Ethernet AVB */ 427 static int ravb_dmac_init(struct net_device *ndev) 428 { 429 struct ravb_private *priv = netdev_priv(ndev); 430 int error; 431 432 /* Set CONFIG mode */ 433 error = ravb_config(ndev); 434 if (error) 435 return error; 436 437 error = ravb_ring_init(ndev, RAVB_BE); 438 if (error) 439 return error; 440 error = ravb_ring_init(ndev, RAVB_NC); 441 if (error) { 442 ravb_ring_free(ndev, RAVB_BE); 443 return error; 444 } 445 446 /* Descriptor format */ 447 ravb_ring_format(ndev, RAVB_BE); 448 ravb_ring_format(ndev, RAVB_NC); 449 450 #if defined(__LITTLE_ENDIAN) 451 ravb_modify(ndev, CCC, CCC_BOC, 0); 452 #else 453 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 454 #endif 455 456 /* Set AVB RX */ 457 ravb_write(ndev, 458 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 459 460 /* Set FIFO size */ 461 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 462 463 /* Timestamp enable */ 464 ravb_write(ndev, TCCR_TFEN, TCCR); 465 466 /* Interrupt init: */ 467 if (priv->chip_id == RCAR_GEN3) { 468 /* Clear DIL.DPLx */ 469 ravb_write(ndev, 0, DIL); 470 /* Set queue specific interrupt */ 471 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 472 } 473 /* Frame receive */ 474 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 475 /* Disable FIFO full warning */ 476 ravb_write(ndev, 0, RIC1); 477 /* Receive FIFO full error, descriptor empty */ 478 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 479 /* Frame transmitted, timestamp FIFO updated */ 480 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 481 482 /* Setting the control will start the AVB-DMAC process. */ 483 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 484 485 return 0; 486 } 487 488 static void ravb_get_tx_tstamp(struct net_device *ndev) 489 { 490 struct ravb_private *priv = netdev_priv(ndev); 491 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 492 struct skb_shared_hwtstamps shhwtstamps; 493 struct sk_buff *skb; 494 struct timespec64 ts; 495 u16 tag, tfa_tag; 496 int count; 497 u32 tfa2; 498 499 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 500 while (count--) { 501 tfa2 = ravb_read(ndev, TFA2); 502 tfa_tag = (tfa2 & TFA2_TST) >> 16; 503 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 504 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 505 ravb_read(ndev, TFA1); 506 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 507 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 508 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 509 list) { 510 skb = ts_skb->skb; 511 tag = ts_skb->tag; 512 list_del(&ts_skb->list); 513 kfree(ts_skb); 514 if (tag == tfa_tag) { 515 skb_tstamp_tx(skb, &shhwtstamps); 516 dev_consume_skb_any(skb); 517 break; 518 } else { 519 dev_kfree_skb_any(skb); 520 } 521 } 522 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 523 } 524 } 525 526 static void ravb_rx_csum(struct sk_buff *skb) 527 { 528 u8 *hw_csum; 529 530 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 531 * appended to packet data 532 */ 533 if (unlikely(skb->len < sizeof(__sum16))) 534 return; 535 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 536 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 537 skb->ip_summed = CHECKSUM_COMPLETE; 538 skb_trim(skb, skb->len - sizeof(__sum16)); 539 } 540 541 /* Packet receive function for Ethernet AVB */ 542 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 543 { 544 struct ravb_private *priv = netdev_priv(ndev); 545 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 546 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 547 priv->cur_rx[q]; 548 struct net_device_stats *stats = &priv->stats[q]; 549 struct ravb_ex_rx_desc *desc; 550 struct sk_buff *skb; 551 dma_addr_t dma_addr; 552 struct timespec64 ts; 553 u8 desc_status; 554 u16 pkt_len; 555 int limit; 556 557 boguscnt = min(boguscnt, *quota); 558 limit = boguscnt; 559 desc = &priv->rx_ring[q][entry]; 560 while (desc->die_dt != DT_FEMPTY) { 561 /* Descriptor type must be checked before all other reads */ 562 dma_rmb(); 563 desc_status = desc->msc; 564 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 565 566 if (--boguscnt < 0) 567 break; 568 569 /* We use 0-byte descriptors to mark the DMA mapping errors */ 570 if (!pkt_len) 571 continue; 572 573 if (desc_status & MSC_MC) 574 stats->multicast++; 575 576 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 577 MSC_CEEF)) { 578 stats->rx_errors++; 579 if (desc_status & MSC_CRC) 580 stats->rx_crc_errors++; 581 if (desc_status & MSC_RFE) 582 stats->rx_frame_errors++; 583 if (desc_status & (MSC_RTLF | MSC_RTSF)) 584 stats->rx_length_errors++; 585 if (desc_status & MSC_CEEF) 586 stats->rx_missed_errors++; 587 } else { 588 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 589 590 skb = priv->rx_skb[q][entry]; 591 priv->rx_skb[q][entry] = NULL; 592 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 593 priv->rx_buf_sz, 594 DMA_FROM_DEVICE); 595 get_ts &= (q == RAVB_NC) ? 596 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 597 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 598 if (get_ts) { 599 struct skb_shared_hwtstamps *shhwtstamps; 600 601 shhwtstamps = skb_hwtstamps(skb); 602 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 603 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 604 32) | le32_to_cpu(desc->ts_sl); 605 ts.tv_nsec = le32_to_cpu(desc->ts_n); 606 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 607 } 608 609 skb_put(skb, pkt_len); 610 skb->protocol = eth_type_trans(skb, ndev); 611 if (ndev->features & NETIF_F_RXCSUM) 612 ravb_rx_csum(skb); 613 napi_gro_receive(&priv->napi[q], skb); 614 stats->rx_packets++; 615 stats->rx_bytes += pkt_len; 616 } 617 618 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 619 desc = &priv->rx_ring[q][entry]; 620 } 621 622 /* Refill the RX ring buffers. */ 623 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 624 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 625 desc = &priv->rx_ring[q][entry]; 626 desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 627 628 if (!priv->rx_skb[q][entry]) { 629 skb = netdev_alloc_skb(ndev, 630 priv->rx_buf_sz + 631 RAVB_ALIGN - 1); 632 if (!skb) 633 break; /* Better luck next round. */ 634 ravb_set_buffer_align(skb); 635 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 636 le16_to_cpu(desc->ds_cc), 637 DMA_FROM_DEVICE); 638 skb_checksum_none_assert(skb); 639 /* We just set the data size to 0 for a failed mapping 640 * which should prevent DMA from happening... 641 */ 642 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 643 desc->ds_cc = cpu_to_le16(0); 644 desc->dptr = cpu_to_le32(dma_addr); 645 priv->rx_skb[q][entry] = skb; 646 } 647 /* Descriptor type must be set after all the above writes */ 648 dma_wmb(); 649 desc->die_dt = DT_FEMPTY; 650 } 651 652 *quota -= limit - (++boguscnt); 653 654 return boguscnt <= 0; 655 } 656 657 static void ravb_rcv_snd_disable(struct net_device *ndev) 658 { 659 /* Disable TX and RX */ 660 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 661 } 662 663 static void ravb_rcv_snd_enable(struct net_device *ndev) 664 { 665 /* Enable TX and RX */ 666 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 667 } 668 669 /* function for waiting dma process finished */ 670 static int ravb_stop_dma(struct net_device *ndev) 671 { 672 int error; 673 674 /* Wait for stopping the hardware TX process */ 675 error = ravb_wait(ndev, TCCR, 676 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 677 if (error) 678 return error; 679 680 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 681 0); 682 if (error) 683 return error; 684 685 /* Stop the E-MAC's RX/TX processes. */ 686 ravb_rcv_snd_disable(ndev); 687 688 /* Wait for stopping the RX DMA process */ 689 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 690 if (error) 691 return error; 692 693 /* Stop AVB-DMAC process */ 694 return ravb_config(ndev); 695 } 696 697 /* E-MAC interrupt handler */ 698 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 699 { 700 struct ravb_private *priv = netdev_priv(ndev); 701 u32 ecsr, psr; 702 703 ecsr = ravb_read(ndev, ECSR); 704 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 705 706 if (ecsr & ECSR_MPD) 707 pm_wakeup_event(&priv->pdev->dev, 0); 708 if (ecsr & ECSR_ICD) 709 ndev->stats.tx_carrier_errors++; 710 if (ecsr & ECSR_LCHNG) { 711 /* Link changed */ 712 if (priv->no_avb_link) 713 return; 714 psr = ravb_read(ndev, PSR); 715 if (priv->avb_link_active_low) 716 psr ^= PSR_LMON; 717 if (!(psr & PSR_LMON)) { 718 /* DIsable RX and TX */ 719 ravb_rcv_snd_disable(ndev); 720 } else { 721 /* Enable RX and TX */ 722 ravb_rcv_snd_enable(ndev); 723 } 724 } 725 } 726 727 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 728 { 729 struct net_device *ndev = dev_id; 730 struct ravb_private *priv = netdev_priv(ndev); 731 732 spin_lock(&priv->lock); 733 ravb_emac_interrupt_unlocked(ndev); 734 spin_unlock(&priv->lock); 735 return IRQ_HANDLED; 736 } 737 738 /* Error interrupt handler */ 739 static void ravb_error_interrupt(struct net_device *ndev) 740 { 741 struct ravb_private *priv = netdev_priv(ndev); 742 u32 eis, ris2; 743 744 eis = ravb_read(ndev, EIS); 745 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 746 if (eis & EIS_QFS) { 747 ris2 = ravb_read(ndev, RIS2); 748 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED), 749 RIS2); 750 751 /* Receive Descriptor Empty int */ 752 if (ris2 & RIS2_QFF0) 753 priv->stats[RAVB_BE].rx_over_errors++; 754 755 /* Receive Descriptor Empty int */ 756 if (ris2 & RIS2_QFF1) 757 priv->stats[RAVB_NC].rx_over_errors++; 758 759 /* Receive FIFO Overflow int */ 760 if (ris2 & RIS2_RFFF) 761 priv->rx_fifo_errors++; 762 } 763 } 764 765 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 766 { 767 struct ravb_private *priv = netdev_priv(ndev); 768 u32 ris0 = ravb_read(ndev, RIS0); 769 u32 ric0 = ravb_read(ndev, RIC0); 770 u32 tis = ravb_read(ndev, TIS); 771 u32 tic = ravb_read(ndev, TIC); 772 773 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 774 if (napi_schedule_prep(&priv->napi[q])) { 775 /* Mask RX and TX interrupts */ 776 if (priv->chip_id == RCAR_GEN2) { 777 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 778 ravb_write(ndev, tic & ~BIT(q), TIC); 779 } else { 780 ravb_write(ndev, BIT(q), RID0); 781 ravb_write(ndev, BIT(q), TID); 782 } 783 __napi_schedule(&priv->napi[q]); 784 } else { 785 netdev_warn(ndev, 786 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 787 ris0, ric0); 788 netdev_warn(ndev, 789 " tx status 0x%08x, tx mask 0x%08x.\n", 790 tis, tic); 791 } 792 return true; 793 } 794 return false; 795 } 796 797 static bool ravb_timestamp_interrupt(struct net_device *ndev) 798 { 799 u32 tis = ravb_read(ndev, TIS); 800 801 if (tis & TIS_TFUF) { 802 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 803 ravb_get_tx_tstamp(ndev); 804 return true; 805 } 806 return false; 807 } 808 809 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 810 { 811 struct net_device *ndev = dev_id; 812 struct ravb_private *priv = netdev_priv(ndev); 813 irqreturn_t result = IRQ_NONE; 814 u32 iss; 815 816 spin_lock(&priv->lock); 817 /* Get interrupt status */ 818 iss = ravb_read(ndev, ISS); 819 820 /* Received and transmitted interrupts */ 821 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 822 int q; 823 824 /* Timestamp updated */ 825 if (ravb_timestamp_interrupt(ndev)) 826 result = IRQ_HANDLED; 827 828 /* Network control and best effort queue RX/TX */ 829 for (q = RAVB_NC; q >= RAVB_BE; q--) { 830 if (ravb_queue_interrupt(ndev, q)) 831 result = IRQ_HANDLED; 832 } 833 } 834 835 /* E-MAC status summary */ 836 if (iss & ISS_MS) { 837 ravb_emac_interrupt_unlocked(ndev); 838 result = IRQ_HANDLED; 839 } 840 841 /* Error status summary */ 842 if (iss & ISS_ES) { 843 ravb_error_interrupt(ndev); 844 result = IRQ_HANDLED; 845 } 846 847 /* gPTP interrupt status summary */ 848 if (iss & ISS_CGIS) { 849 ravb_ptp_interrupt(ndev); 850 result = IRQ_HANDLED; 851 } 852 853 spin_unlock(&priv->lock); 854 return result; 855 } 856 857 /* Timestamp/Error/gPTP interrupt handler */ 858 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 859 { 860 struct net_device *ndev = dev_id; 861 struct ravb_private *priv = netdev_priv(ndev); 862 irqreturn_t result = IRQ_NONE; 863 u32 iss; 864 865 spin_lock(&priv->lock); 866 /* Get interrupt status */ 867 iss = ravb_read(ndev, ISS); 868 869 /* Timestamp updated */ 870 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 871 result = IRQ_HANDLED; 872 873 /* Error status summary */ 874 if (iss & ISS_ES) { 875 ravb_error_interrupt(ndev); 876 result = IRQ_HANDLED; 877 } 878 879 /* gPTP interrupt status summary */ 880 if (iss & ISS_CGIS) { 881 ravb_ptp_interrupt(ndev); 882 result = IRQ_HANDLED; 883 } 884 885 spin_unlock(&priv->lock); 886 return result; 887 } 888 889 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 890 { 891 struct net_device *ndev = dev_id; 892 struct ravb_private *priv = netdev_priv(ndev); 893 irqreturn_t result = IRQ_NONE; 894 895 spin_lock(&priv->lock); 896 897 /* Network control/Best effort queue RX/TX */ 898 if (ravb_queue_interrupt(ndev, q)) 899 result = IRQ_HANDLED; 900 901 spin_unlock(&priv->lock); 902 return result; 903 } 904 905 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 906 { 907 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 908 } 909 910 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 911 { 912 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 913 } 914 915 static int ravb_poll(struct napi_struct *napi, int budget) 916 { 917 struct net_device *ndev = napi->dev; 918 struct ravb_private *priv = netdev_priv(ndev); 919 unsigned long flags; 920 int q = napi - priv->napi; 921 int mask = BIT(q); 922 int quota = budget; 923 u32 ris0, tis; 924 925 for (;;) { 926 tis = ravb_read(ndev, TIS); 927 ris0 = ravb_read(ndev, RIS0); 928 if (!((ris0 & mask) || (tis & mask))) 929 break; 930 931 /* Processing RX Descriptor Ring */ 932 if (ris0 & mask) { 933 /* Clear RX interrupt */ 934 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 935 if (ravb_rx(ndev, "a, q)) 936 goto out; 937 } 938 /* Processing TX Descriptor Ring */ 939 if (tis & mask) { 940 spin_lock_irqsave(&priv->lock, flags); 941 /* Clear TX interrupt */ 942 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 943 ravb_tx_free(ndev, q, true); 944 netif_wake_subqueue(ndev, q); 945 spin_unlock_irqrestore(&priv->lock, flags); 946 } 947 } 948 949 napi_complete(napi); 950 951 /* Re-enable RX/TX interrupts */ 952 spin_lock_irqsave(&priv->lock, flags); 953 if (priv->chip_id == RCAR_GEN2) { 954 ravb_modify(ndev, RIC0, mask, mask); 955 ravb_modify(ndev, TIC, mask, mask); 956 } else { 957 ravb_write(ndev, mask, RIE0); 958 ravb_write(ndev, mask, TIE); 959 } 960 spin_unlock_irqrestore(&priv->lock, flags); 961 962 /* Receive error message handling */ 963 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 964 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 965 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 966 ndev->stats.rx_over_errors = priv->rx_over_errors; 967 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 968 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 969 out: 970 return budget - quota; 971 } 972 973 /* PHY state control function */ 974 static void ravb_adjust_link(struct net_device *ndev) 975 { 976 struct ravb_private *priv = netdev_priv(ndev); 977 struct phy_device *phydev = ndev->phydev; 978 bool new_state = false; 979 unsigned long flags; 980 981 spin_lock_irqsave(&priv->lock, flags); 982 983 /* Disable TX and RX right over here, if E-MAC change is ignored */ 984 if (priv->no_avb_link) 985 ravb_rcv_snd_disable(ndev); 986 987 if (phydev->link) { 988 if (phydev->speed != priv->speed) { 989 new_state = true; 990 priv->speed = phydev->speed; 991 ravb_set_rate(ndev); 992 } 993 if (!priv->link) { 994 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 995 new_state = true; 996 priv->link = phydev->link; 997 } 998 } else if (priv->link) { 999 new_state = true; 1000 priv->link = 0; 1001 priv->speed = 0; 1002 } 1003 1004 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1005 if (priv->no_avb_link && phydev->link) 1006 ravb_rcv_snd_enable(ndev); 1007 1008 spin_unlock_irqrestore(&priv->lock, flags); 1009 1010 if (new_state && netif_msg_link(priv)) 1011 phy_print_status(phydev); 1012 } 1013 1014 static const struct soc_device_attribute r8a7795es10[] = { 1015 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1016 { /* sentinel */ } 1017 }; 1018 1019 /* PHY init function */ 1020 static int ravb_phy_init(struct net_device *ndev) 1021 { 1022 struct device_node *np = ndev->dev.parent->of_node; 1023 struct ravb_private *priv = netdev_priv(ndev); 1024 struct phy_device *phydev; 1025 struct device_node *pn; 1026 int err; 1027 1028 priv->link = 0; 1029 priv->speed = 0; 1030 1031 /* Try connecting to PHY */ 1032 pn = of_parse_phandle(np, "phy-handle", 0); 1033 if (!pn) { 1034 /* In the case of a fixed PHY, the DT node associated 1035 * to the PHY is the Ethernet MAC DT node. 1036 */ 1037 if (of_phy_is_fixed_link(np)) { 1038 err = of_phy_register_fixed_link(np); 1039 if (err) 1040 return err; 1041 } 1042 pn = of_node_get(np); 1043 } 1044 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1045 priv->phy_interface); 1046 of_node_put(pn); 1047 if (!phydev) { 1048 netdev_err(ndev, "failed to connect PHY\n"); 1049 err = -ENOENT; 1050 goto err_deregister_fixed_link; 1051 } 1052 1053 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1054 * at this time. 1055 */ 1056 if (soc_device_match(r8a7795es10)) { 1057 err = phy_set_max_speed(phydev, SPEED_100); 1058 if (err) { 1059 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1060 goto err_phy_disconnect; 1061 } 1062 1063 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1064 } 1065 1066 /* 10BASE, Pause and Asym Pause is not supported */ 1067 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1068 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1069 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1070 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1071 1072 /* Half Duplex is not supported */ 1073 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1074 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1075 1076 phy_attached_info(phydev); 1077 1078 return 0; 1079 1080 err_phy_disconnect: 1081 phy_disconnect(phydev); 1082 err_deregister_fixed_link: 1083 if (of_phy_is_fixed_link(np)) 1084 of_phy_deregister_fixed_link(np); 1085 1086 return err; 1087 } 1088 1089 /* PHY control start function */ 1090 static int ravb_phy_start(struct net_device *ndev) 1091 { 1092 int error; 1093 1094 error = ravb_phy_init(ndev); 1095 if (error) 1096 return error; 1097 1098 phy_start(ndev->phydev); 1099 1100 return 0; 1101 } 1102 1103 static u32 ravb_get_msglevel(struct net_device *ndev) 1104 { 1105 struct ravb_private *priv = netdev_priv(ndev); 1106 1107 return priv->msg_enable; 1108 } 1109 1110 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1111 { 1112 struct ravb_private *priv = netdev_priv(ndev); 1113 1114 priv->msg_enable = value; 1115 } 1116 1117 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1118 "rx_queue_0_current", 1119 "tx_queue_0_current", 1120 "rx_queue_0_dirty", 1121 "tx_queue_0_dirty", 1122 "rx_queue_0_packets", 1123 "tx_queue_0_packets", 1124 "rx_queue_0_bytes", 1125 "tx_queue_0_bytes", 1126 "rx_queue_0_mcast_packets", 1127 "rx_queue_0_errors", 1128 "rx_queue_0_crc_errors", 1129 "rx_queue_0_frame_errors", 1130 "rx_queue_0_length_errors", 1131 "rx_queue_0_missed_errors", 1132 "rx_queue_0_over_errors", 1133 1134 "rx_queue_1_current", 1135 "tx_queue_1_current", 1136 "rx_queue_1_dirty", 1137 "tx_queue_1_dirty", 1138 "rx_queue_1_packets", 1139 "tx_queue_1_packets", 1140 "rx_queue_1_bytes", 1141 "tx_queue_1_bytes", 1142 "rx_queue_1_mcast_packets", 1143 "rx_queue_1_errors", 1144 "rx_queue_1_crc_errors", 1145 "rx_queue_1_frame_errors", 1146 "rx_queue_1_length_errors", 1147 "rx_queue_1_missed_errors", 1148 "rx_queue_1_over_errors", 1149 }; 1150 1151 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1152 1153 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1154 { 1155 switch (sset) { 1156 case ETH_SS_STATS: 1157 return RAVB_STATS_LEN; 1158 default: 1159 return -EOPNOTSUPP; 1160 } 1161 } 1162 1163 static void ravb_get_ethtool_stats(struct net_device *ndev, 1164 struct ethtool_stats *estats, u64 *data) 1165 { 1166 struct ravb_private *priv = netdev_priv(ndev); 1167 int i = 0; 1168 int q; 1169 1170 /* Device-specific stats */ 1171 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1172 struct net_device_stats *stats = &priv->stats[q]; 1173 1174 data[i++] = priv->cur_rx[q]; 1175 data[i++] = priv->cur_tx[q]; 1176 data[i++] = priv->dirty_rx[q]; 1177 data[i++] = priv->dirty_tx[q]; 1178 data[i++] = stats->rx_packets; 1179 data[i++] = stats->tx_packets; 1180 data[i++] = stats->rx_bytes; 1181 data[i++] = stats->tx_bytes; 1182 data[i++] = stats->multicast; 1183 data[i++] = stats->rx_errors; 1184 data[i++] = stats->rx_crc_errors; 1185 data[i++] = stats->rx_frame_errors; 1186 data[i++] = stats->rx_length_errors; 1187 data[i++] = stats->rx_missed_errors; 1188 data[i++] = stats->rx_over_errors; 1189 } 1190 } 1191 1192 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1193 { 1194 switch (stringset) { 1195 case ETH_SS_STATS: 1196 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1197 break; 1198 } 1199 } 1200 1201 static void ravb_get_ringparam(struct net_device *ndev, 1202 struct ethtool_ringparam *ring) 1203 { 1204 struct ravb_private *priv = netdev_priv(ndev); 1205 1206 ring->rx_max_pending = BE_RX_RING_MAX; 1207 ring->tx_max_pending = BE_TX_RING_MAX; 1208 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1209 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1210 } 1211 1212 static int ravb_set_ringparam(struct net_device *ndev, 1213 struct ethtool_ringparam *ring) 1214 { 1215 struct ravb_private *priv = netdev_priv(ndev); 1216 int error; 1217 1218 if (ring->tx_pending > BE_TX_RING_MAX || 1219 ring->rx_pending > BE_RX_RING_MAX || 1220 ring->tx_pending < BE_TX_RING_MIN || 1221 ring->rx_pending < BE_RX_RING_MIN) 1222 return -EINVAL; 1223 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1224 return -EINVAL; 1225 1226 if (netif_running(ndev)) { 1227 netif_device_detach(ndev); 1228 /* Stop PTP Clock driver */ 1229 if (priv->chip_id == RCAR_GEN2) 1230 ravb_ptp_stop(ndev); 1231 /* Wait for DMA stopping */ 1232 error = ravb_stop_dma(ndev); 1233 if (error) { 1234 netdev_err(ndev, 1235 "cannot set ringparam! Any AVB processes are still running?\n"); 1236 return error; 1237 } 1238 synchronize_irq(ndev->irq); 1239 1240 /* Free all the skb's in the RX queue and the DMA buffers. */ 1241 ravb_ring_free(ndev, RAVB_BE); 1242 ravb_ring_free(ndev, RAVB_NC); 1243 } 1244 1245 /* Set new parameters */ 1246 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1247 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1248 1249 if (netif_running(ndev)) { 1250 error = ravb_dmac_init(ndev); 1251 if (error) { 1252 netdev_err(ndev, 1253 "%s: ravb_dmac_init() failed, error %d\n", 1254 __func__, error); 1255 return error; 1256 } 1257 1258 ravb_emac_init(ndev); 1259 1260 /* Initialise PTP Clock driver */ 1261 if (priv->chip_id == RCAR_GEN2) 1262 ravb_ptp_init(ndev, priv->pdev); 1263 1264 netif_device_attach(ndev); 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int ravb_get_ts_info(struct net_device *ndev, 1271 struct ethtool_ts_info *info) 1272 { 1273 struct ravb_private *priv = netdev_priv(ndev); 1274 1275 info->so_timestamping = 1276 SOF_TIMESTAMPING_TX_SOFTWARE | 1277 SOF_TIMESTAMPING_RX_SOFTWARE | 1278 SOF_TIMESTAMPING_SOFTWARE | 1279 SOF_TIMESTAMPING_TX_HARDWARE | 1280 SOF_TIMESTAMPING_RX_HARDWARE | 1281 SOF_TIMESTAMPING_RAW_HARDWARE; 1282 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1283 info->rx_filters = 1284 (1 << HWTSTAMP_FILTER_NONE) | 1285 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1286 (1 << HWTSTAMP_FILTER_ALL); 1287 info->phc_index = ptp_clock_index(priv->ptp.clock); 1288 1289 return 0; 1290 } 1291 1292 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1293 { 1294 struct ravb_private *priv = netdev_priv(ndev); 1295 1296 wol->supported = WAKE_MAGIC; 1297 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1298 } 1299 1300 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1301 { 1302 struct ravb_private *priv = netdev_priv(ndev); 1303 1304 if (wol->wolopts & ~WAKE_MAGIC) 1305 return -EOPNOTSUPP; 1306 1307 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1308 1309 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1310 1311 return 0; 1312 } 1313 1314 static const struct ethtool_ops ravb_ethtool_ops = { 1315 .nway_reset = phy_ethtool_nway_reset, 1316 .get_msglevel = ravb_get_msglevel, 1317 .set_msglevel = ravb_set_msglevel, 1318 .get_link = ethtool_op_get_link, 1319 .get_strings = ravb_get_strings, 1320 .get_ethtool_stats = ravb_get_ethtool_stats, 1321 .get_sset_count = ravb_get_sset_count, 1322 .get_ringparam = ravb_get_ringparam, 1323 .set_ringparam = ravb_set_ringparam, 1324 .get_ts_info = ravb_get_ts_info, 1325 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1326 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1327 .get_wol = ravb_get_wol, 1328 .set_wol = ravb_set_wol, 1329 }; 1330 1331 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1332 struct net_device *ndev, struct device *dev, 1333 const char *ch) 1334 { 1335 char *name; 1336 int error; 1337 1338 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1339 if (!name) 1340 return -ENOMEM; 1341 error = request_irq(irq, handler, 0, name, ndev); 1342 if (error) 1343 netdev_err(ndev, "cannot request IRQ %s\n", name); 1344 1345 return error; 1346 } 1347 1348 /* Network device open function for Ethernet AVB */ 1349 static int ravb_open(struct net_device *ndev) 1350 { 1351 struct ravb_private *priv = netdev_priv(ndev); 1352 struct platform_device *pdev = priv->pdev; 1353 struct device *dev = &pdev->dev; 1354 int error; 1355 1356 napi_enable(&priv->napi[RAVB_BE]); 1357 napi_enable(&priv->napi[RAVB_NC]); 1358 1359 if (priv->chip_id == RCAR_GEN2) { 1360 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1361 ndev->name, ndev); 1362 if (error) { 1363 netdev_err(ndev, "cannot request IRQ\n"); 1364 goto out_napi_off; 1365 } 1366 } else { 1367 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1368 dev, "ch22:multi"); 1369 if (error) 1370 goto out_napi_off; 1371 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1372 dev, "ch24:emac"); 1373 if (error) 1374 goto out_free_irq; 1375 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1376 ndev, dev, "ch0:rx_be"); 1377 if (error) 1378 goto out_free_irq_emac; 1379 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1380 ndev, dev, "ch18:tx_be"); 1381 if (error) 1382 goto out_free_irq_be_rx; 1383 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1384 ndev, dev, "ch1:rx_nc"); 1385 if (error) 1386 goto out_free_irq_be_tx; 1387 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1388 ndev, dev, "ch19:tx_nc"); 1389 if (error) 1390 goto out_free_irq_nc_rx; 1391 } 1392 1393 /* Device init */ 1394 error = ravb_dmac_init(ndev); 1395 if (error) 1396 goto out_free_irq_nc_tx; 1397 ravb_emac_init(ndev); 1398 1399 /* Initialise PTP Clock driver */ 1400 if (priv->chip_id == RCAR_GEN2) 1401 ravb_ptp_init(ndev, priv->pdev); 1402 1403 netif_tx_start_all_queues(ndev); 1404 1405 /* PHY control start */ 1406 error = ravb_phy_start(ndev); 1407 if (error) 1408 goto out_ptp_stop; 1409 1410 return 0; 1411 1412 out_ptp_stop: 1413 /* Stop PTP Clock driver */ 1414 if (priv->chip_id == RCAR_GEN2) 1415 ravb_ptp_stop(ndev); 1416 out_free_irq_nc_tx: 1417 if (priv->chip_id == RCAR_GEN2) 1418 goto out_free_irq; 1419 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1420 out_free_irq_nc_rx: 1421 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1422 out_free_irq_be_tx: 1423 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1424 out_free_irq_be_rx: 1425 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1426 out_free_irq_emac: 1427 free_irq(priv->emac_irq, ndev); 1428 out_free_irq: 1429 free_irq(ndev->irq, ndev); 1430 out_napi_off: 1431 napi_disable(&priv->napi[RAVB_NC]); 1432 napi_disable(&priv->napi[RAVB_BE]); 1433 return error; 1434 } 1435 1436 /* Timeout function for Ethernet AVB */ 1437 static void ravb_tx_timeout(struct net_device *ndev) 1438 { 1439 struct ravb_private *priv = netdev_priv(ndev); 1440 1441 netif_err(priv, tx_err, ndev, 1442 "transmit timed out, status %08x, resetting...\n", 1443 ravb_read(ndev, ISS)); 1444 1445 /* tx_errors count up */ 1446 ndev->stats.tx_errors++; 1447 1448 schedule_work(&priv->work); 1449 } 1450 1451 static void ravb_tx_timeout_work(struct work_struct *work) 1452 { 1453 struct ravb_private *priv = container_of(work, struct ravb_private, 1454 work); 1455 struct net_device *ndev = priv->ndev; 1456 1457 netif_tx_stop_all_queues(ndev); 1458 1459 /* Stop PTP Clock driver */ 1460 if (priv->chip_id == RCAR_GEN2) 1461 ravb_ptp_stop(ndev); 1462 1463 /* Wait for DMA stopping */ 1464 ravb_stop_dma(ndev); 1465 1466 ravb_ring_free(ndev, RAVB_BE); 1467 ravb_ring_free(ndev, RAVB_NC); 1468 1469 /* Device init */ 1470 ravb_dmac_init(ndev); 1471 ravb_emac_init(ndev); 1472 1473 /* Initialise PTP Clock driver */ 1474 if (priv->chip_id == RCAR_GEN2) 1475 ravb_ptp_init(ndev, priv->pdev); 1476 1477 netif_tx_start_all_queues(ndev); 1478 } 1479 1480 /* Packet transmit function for Ethernet AVB */ 1481 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1482 { 1483 struct ravb_private *priv = netdev_priv(ndev); 1484 int num_tx_desc = priv->num_tx_desc; 1485 u16 q = skb_get_queue_mapping(skb); 1486 struct ravb_tstamp_skb *ts_skb; 1487 struct ravb_tx_desc *desc; 1488 unsigned long flags; 1489 u32 dma_addr; 1490 void *buffer; 1491 u32 entry; 1492 u32 len; 1493 1494 spin_lock_irqsave(&priv->lock, flags); 1495 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1496 num_tx_desc) { 1497 netif_err(priv, tx_queued, ndev, 1498 "still transmitting with the full ring!\n"); 1499 netif_stop_subqueue(ndev, q); 1500 spin_unlock_irqrestore(&priv->lock, flags); 1501 return NETDEV_TX_BUSY; 1502 } 1503 1504 if (skb_put_padto(skb, ETH_ZLEN)) 1505 goto exit; 1506 1507 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1508 priv->tx_skb[q][entry / num_tx_desc] = skb; 1509 1510 if (num_tx_desc > 1) { 1511 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1512 entry / num_tx_desc * DPTR_ALIGN; 1513 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1514 1515 /* Zero length DMA descriptors are problematic as they seem 1516 * to terminate DMA transfers. Avoid them by simply using a 1517 * length of DPTR_ALIGN (4) when skb data is aligned to 1518 * DPTR_ALIGN. 1519 * 1520 * As skb is guaranteed to have at least ETH_ZLEN (60) 1521 * bytes of data by the call to skb_put_padto() above this 1522 * is safe with respect to both the length of the first DMA 1523 * descriptor (len) overflowing the available data and the 1524 * length of the second DMA descriptor (skb->len - len) 1525 * being negative. 1526 */ 1527 if (len == 0) 1528 len = DPTR_ALIGN; 1529 1530 memcpy(buffer, skb->data, len); 1531 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1532 DMA_TO_DEVICE); 1533 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1534 goto drop; 1535 1536 desc = &priv->tx_ring[q][entry]; 1537 desc->ds_tagl = cpu_to_le16(len); 1538 desc->dptr = cpu_to_le32(dma_addr); 1539 1540 buffer = skb->data + len; 1541 len = skb->len - len; 1542 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1543 DMA_TO_DEVICE); 1544 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1545 goto unmap; 1546 1547 desc++; 1548 } else { 1549 desc = &priv->tx_ring[q][entry]; 1550 len = skb->len; 1551 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1552 DMA_TO_DEVICE); 1553 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1554 goto drop; 1555 } 1556 desc->ds_tagl = cpu_to_le16(len); 1557 desc->dptr = cpu_to_le32(dma_addr); 1558 1559 /* TX timestamp required */ 1560 if (q == RAVB_NC) { 1561 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1562 if (!ts_skb) { 1563 if (num_tx_desc > 1) { 1564 desc--; 1565 dma_unmap_single(ndev->dev.parent, dma_addr, 1566 len, DMA_TO_DEVICE); 1567 } 1568 goto unmap; 1569 } 1570 ts_skb->skb = skb_get(skb); 1571 ts_skb->tag = priv->ts_skb_tag++; 1572 priv->ts_skb_tag &= 0x3ff; 1573 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1574 1575 /* TAG and timestamp required flag */ 1576 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1577 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1578 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1579 } 1580 1581 skb_tx_timestamp(skb); 1582 /* Descriptor type must be set after all the above writes */ 1583 dma_wmb(); 1584 if (num_tx_desc > 1) { 1585 desc->die_dt = DT_FEND; 1586 desc--; 1587 desc->die_dt = DT_FSTART; 1588 } else { 1589 desc->die_dt = DT_FSINGLE; 1590 } 1591 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1592 1593 priv->cur_tx[q] += num_tx_desc; 1594 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1595 (priv->num_tx_ring[q] - 1) * num_tx_desc && 1596 !ravb_tx_free(ndev, q, true)) 1597 netif_stop_subqueue(ndev, q); 1598 1599 exit: 1600 spin_unlock_irqrestore(&priv->lock, flags); 1601 return NETDEV_TX_OK; 1602 1603 unmap: 1604 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1605 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1606 drop: 1607 dev_kfree_skb_any(skb); 1608 priv->tx_skb[q][entry / num_tx_desc] = NULL; 1609 goto exit; 1610 } 1611 1612 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1613 struct net_device *sb_dev) 1614 { 1615 /* If skb needs TX timestamp, it is handled in network control queue */ 1616 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1617 RAVB_BE; 1618 1619 } 1620 1621 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1622 { 1623 struct ravb_private *priv = netdev_priv(ndev); 1624 struct net_device_stats *nstats, *stats0, *stats1; 1625 1626 nstats = &ndev->stats; 1627 stats0 = &priv->stats[RAVB_BE]; 1628 stats1 = &priv->stats[RAVB_NC]; 1629 1630 nstats->tx_dropped += ravb_read(ndev, TROCR); 1631 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1632 nstats->collisions += ravb_read(ndev, CDCR); 1633 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1634 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1635 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1636 1637 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1638 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1639 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1640 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1641 1642 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1643 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1644 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1645 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1646 nstats->multicast = stats0->multicast + stats1->multicast; 1647 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1648 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1649 nstats->rx_frame_errors = 1650 stats0->rx_frame_errors + stats1->rx_frame_errors; 1651 nstats->rx_length_errors = 1652 stats0->rx_length_errors + stats1->rx_length_errors; 1653 nstats->rx_missed_errors = 1654 stats0->rx_missed_errors + stats1->rx_missed_errors; 1655 nstats->rx_over_errors = 1656 stats0->rx_over_errors + stats1->rx_over_errors; 1657 1658 return nstats; 1659 } 1660 1661 /* Update promiscuous bit */ 1662 static void ravb_set_rx_mode(struct net_device *ndev) 1663 { 1664 struct ravb_private *priv = netdev_priv(ndev); 1665 unsigned long flags; 1666 1667 spin_lock_irqsave(&priv->lock, flags); 1668 ravb_modify(ndev, ECMR, ECMR_PRM, 1669 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1670 spin_unlock_irqrestore(&priv->lock, flags); 1671 } 1672 1673 /* Device close function for Ethernet AVB */ 1674 static int ravb_close(struct net_device *ndev) 1675 { 1676 struct device_node *np = ndev->dev.parent->of_node; 1677 struct ravb_private *priv = netdev_priv(ndev); 1678 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1679 1680 netif_tx_stop_all_queues(ndev); 1681 1682 /* Disable interrupts by clearing the interrupt masks. */ 1683 ravb_write(ndev, 0, RIC0); 1684 ravb_write(ndev, 0, RIC2); 1685 ravb_write(ndev, 0, TIC); 1686 1687 /* Stop PTP Clock driver */ 1688 if (priv->chip_id == RCAR_GEN2) 1689 ravb_ptp_stop(ndev); 1690 1691 /* Set the config mode to stop the AVB-DMAC's processes */ 1692 if (ravb_stop_dma(ndev) < 0) 1693 netdev_err(ndev, 1694 "device will be stopped after h/w processes are done.\n"); 1695 1696 /* Clear the timestamp list */ 1697 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1698 list_del(&ts_skb->list); 1699 kfree_skb(ts_skb->skb); 1700 kfree(ts_skb); 1701 } 1702 1703 /* PHY disconnect */ 1704 if (ndev->phydev) { 1705 phy_stop(ndev->phydev); 1706 phy_disconnect(ndev->phydev); 1707 if (of_phy_is_fixed_link(np)) 1708 of_phy_deregister_fixed_link(np); 1709 } 1710 1711 if (priv->chip_id != RCAR_GEN2) { 1712 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1713 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1714 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1715 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1716 free_irq(priv->emac_irq, ndev); 1717 } 1718 free_irq(ndev->irq, ndev); 1719 1720 napi_disable(&priv->napi[RAVB_NC]); 1721 napi_disable(&priv->napi[RAVB_BE]); 1722 1723 /* Free all the skb's in the RX queue and the DMA buffers. */ 1724 ravb_ring_free(ndev, RAVB_BE); 1725 ravb_ring_free(ndev, RAVB_NC); 1726 1727 return 0; 1728 } 1729 1730 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1731 { 1732 struct ravb_private *priv = netdev_priv(ndev); 1733 struct hwtstamp_config config; 1734 1735 config.flags = 0; 1736 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1737 HWTSTAMP_TX_OFF; 1738 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1739 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1740 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1741 config.rx_filter = HWTSTAMP_FILTER_ALL; 1742 else 1743 config.rx_filter = HWTSTAMP_FILTER_NONE; 1744 1745 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1746 -EFAULT : 0; 1747 } 1748 1749 /* Control hardware time stamping */ 1750 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1751 { 1752 struct ravb_private *priv = netdev_priv(ndev); 1753 struct hwtstamp_config config; 1754 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1755 u32 tstamp_tx_ctrl; 1756 1757 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1758 return -EFAULT; 1759 1760 /* Reserved for future extensions */ 1761 if (config.flags) 1762 return -EINVAL; 1763 1764 switch (config.tx_type) { 1765 case HWTSTAMP_TX_OFF: 1766 tstamp_tx_ctrl = 0; 1767 break; 1768 case HWTSTAMP_TX_ON: 1769 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1770 break; 1771 default: 1772 return -ERANGE; 1773 } 1774 1775 switch (config.rx_filter) { 1776 case HWTSTAMP_FILTER_NONE: 1777 tstamp_rx_ctrl = 0; 1778 break; 1779 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1780 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1781 break; 1782 default: 1783 config.rx_filter = HWTSTAMP_FILTER_ALL; 1784 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1785 } 1786 1787 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1788 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1789 1790 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1791 -EFAULT : 0; 1792 } 1793 1794 /* ioctl to device function */ 1795 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1796 { 1797 struct phy_device *phydev = ndev->phydev; 1798 1799 if (!netif_running(ndev)) 1800 return -EINVAL; 1801 1802 if (!phydev) 1803 return -ENODEV; 1804 1805 switch (cmd) { 1806 case SIOCGHWTSTAMP: 1807 return ravb_hwtstamp_get(ndev, req); 1808 case SIOCSHWTSTAMP: 1809 return ravb_hwtstamp_set(ndev, req); 1810 } 1811 1812 return phy_mii_ioctl(phydev, req, cmd); 1813 } 1814 1815 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 1816 { 1817 if (netif_running(ndev)) 1818 return -EBUSY; 1819 1820 ndev->mtu = new_mtu; 1821 netdev_update_features(ndev); 1822 1823 return 0; 1824 } 1825 1826 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1827 { 1828 struct ravb_private *priv = netdev_priv(ndev); 1829 unsigned long flags; 1830 1831 spin_lock_irqsave(&priv->lock, flags); 1832 1833 /* Disable TX and RX */ 1834 ravb_rcv_snd_disable(ndev); 1835 1836 /* Modify RX Checksum setting */ 1837 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1838 1839 /* Enable TX and RX */ 1840 ravb_rcv_snd_enable(ndev); 1841 1842 spin_unlock_irqrestore(&priv->lock, flags); 1843 } 1844 1845 static int ravb_set_features(struct net_device *ndev, 1846 netdev_features_t features) 1847 { 1848 netdev_features_t changed = ndev->features ^ features; 1849 1850 if (changed & NETIF_F_RXCSUM) 1851 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1852 1853 ndev->features = features; 1854 1855 return 0; 1856 } 1857 1858 static const struct net_device_ops ravb_netdev_ops = { 1859 .ndo_open = ravb_open, 1860 .ndo_stop = ravb_close, 1861 .ndo_start_xmit = ravb_start_xmit, 1862 .ndo_select_queue = ravb_select_queue, 1863 .ndo_get_stats = ravb_get_stats, 1864 .ndo_set_rx_mode = ravb_set_rx_mode, 1865 .ndo_tx_timeout = ravb_tx_timeout, 1866 .ndo_do_ioctl = ravb_do_ioctl, 1867 .ndo_change_mtu = ravb_change_mtu, 1868 .ndo_validate_addr = eth_validate_addr, 1869 .ndo_set_mac_address = eth_mac_addr, 1870 .ndo_set_features = ravb_set_features, 1871 }; 1872 1873 /* MDIO bus init function */ 1874 static int ravb_mdio_init(struct ravb_private *priv) 1875 { 1876 struct platform_device *pdev = priv->pdev; 1877 struct device *dev = &pdev->dev; 1878 int error; 1879 1880 /* Bitbang init */ 1881 priv->mdiobb.ops = &bb_ops; 1882 1883 /* MII controller setting */ 1884 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1885 if (!priv->mii_bus) 1886 return -ENOMEM; 1887 1888 /* Hook up MII support for ethtool */ 1889 priv->mii_bus->name = "ravb_mii"; 1890 priv->mii_bus->parent = dev; 1891 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1892 pdev->name, pdev->id); 1893 1894 /* Register MDIO bus */ 1895 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1896 if (error) 1897 goto out_free_bus; 1898 1899 return 0; 1900 1901 out_free_bus: 1902 free_mdio_bitbang(priv->mii_bus); 1903 return error; 1904 } 1905 1906 /* MDIO bus release function */ 1907 static int ravb_mdio_release(struct ravb_private *priv) 1908 { 1909 /* Unregister mdio bus */ 1910 mdiobus_unregister(priv->mii_bus); 1911 1912 /* Free bitbang info */ 1913 free_mdio_bitbang(priv->mii_bus); 1914 1915 return 0; 1916 } 1917 1918 static const struct of_device_id ravb_match_table[] = { 1919 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1920 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1921 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1922 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1923 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1924 { } 1925 }; 1926 MODULE_DEVICE_TABLE(of, ravb_match_table); 1927 1928 static int ravb_set_gti(struct net_device *ndev) 1929 { 1930 struct ravb_private *priv = netdev_priv(ndev); 1931 struct device *dev = ndev->dev.parent; 1932 unsigned long rate; 1933 uint64_t inc; 1934 1935 rate = clk_get_rate(priv->clk); 1936 if (!rate) 1937 return -EINVAL; 1938 1939 inc = 1000000000ULL << 20; 1940 do_div(inc, rate); 1941 1942 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1943 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1944 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1945 return -EINVAL; 1946 } 1947 1948 ravb_write(ndev, inc, GTI); 1949 1950 return 0; 1951 } 1952 1953 static void ravb_set_config_mode(struct net_device *ndev) 1954 { 1955 struct ravb_private *priv = netdev_priv(ndev); 1956 1957 if (priv->chip_id == RCAR_GEN2) { 1958 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1959 /* Set CSEL value */ 1960 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1961 } else { 1962 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1963 CCC_GAC | CCC_CSEL_HPB); 1964 } 1965 } 1966 1967 static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = { 1968 { .soc_id = "r8a774c0" }, 1969 { .soc_id = "r8a77990" }, 1970 { .soc_id = "r8a77995" }, 1971 { /* sentinel */ } 1972 }; 1973 1974 /* Set tx and rx clock internal delay modes */ 1975 static void ravb_set_delay_mode(struct net_device *ndev) 1976 { 1977 struct ravb_private *priv = netdev_priv(ndev); 1978 int set = 0; 1979 1980 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1981 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1982 set |= APSR_DM_RDM; 1983 1984 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1985 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 1986 if (!WARN(soc_device_match(ravb_delay_mode_quirk_match), 1987 "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree", 1988 phy_modes(priv->phy_interface))) 1989 set |= APSR_DM_TDM; 1990 } 1991 1992 ravb_modify(ndev, APSR, APSR_DM, set); 1993 } 1994 1995 static int ravb_probe(struct platform_device *pdev) 1996 { 1997 struct device_node *np = pdev->dev.of_node; 1998 struct ravb_private *priv; 1999 enum ravb_chip_id chip_id; 2000 struct net_device *ndev; 2001 int error, irq, q; 2002 struct resource *res; 2003 int i; 2004 2005 if (!np) { 2006 dev_err(&pdev->dev, 2007 "this driver is required to be instantiated from device tree\n"); 2008 return -EINVAL; 2009 } 2010 2011 /* Get base address */ 2012 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2013 if (!res) { 2014 dev_err(&pdev->dev, "invalid resource\n"); 2015 return -EINVAL; 2016 } 2017 2018 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2019 NUM_TX_QUEUE, NUM_RX_QUEUE); 2020 if (!ndev) 2021 return -ENOMEM; 2022 2023 ndev->features = NETIF_F_RXCSUM; 2024 ndev->hw_features = NETIF_F_RXCSUM; 2025 2026 pm_runtime_enable(&pdev->dev); 2027 pm_runtime_get_sync(&pdev->dev); 2028 2029 /* The Ether-specific entries in the device structure. */ 2030 ndev->base_addr = res->start; 2031 2032 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2033 2034 if (chip_id == RCAR_GEN3) 2035 irq = platform_get_irq_byname(pdev, "ch22"); 2036 else 2037 irq = platform_get_irq(pdev, 0); 2038 if (irq < 0) { 2039 error = irq; 2040 goto out_release; 2041 } 2042 ndev->irq = irq; 2043 2044 SET_NETDEV_DEV(ndev, &pdev->dev); 2045 2046 priv = netdev_priv(ndev); 2047 priv->ndev = ndev; 2048 priv->pdev = pdev; 2049 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2050 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2051 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2052 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2053 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2054 if (IS_ERR(priv->addr)) { 2055 error = PTR_ERR(priv->addr); 2056 goto out_release; 2057 } 2058 2059 spin_lock_init(&priv->lock); 2060 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2061 2062 priv->phy_interface = of_get_phy_mode(np); 2063 2064 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2065 priv->avb_link_active_low = 2066 of_property_read_bool(np, "renesas,ether-link-active-low"); 2067 2068 if (chip_id == RCAR_GEN3) { 2069 irq = platform_get_irq_byname(pdev, "ch24"); 2070 if (irq < 0) { 2071 error = irq; 2072 goto out_release; 2073 } 2074 priv->emac_irq = irq; 2075 for (i = 0; i < NUM_RX_QUEUE; i++) { 2076 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2077 if (irq < 0) { 2078 error = irq; 2079 goto out_release; 2080 } 2081 priv->rx_irqs[i] = irq; 2082 } 2083 for (i = 0; i < NUM_TX_QUEUE; i++) { 2084 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2085 if (irq < 0) { 2086 error = irq; 2087 goto out_release; 2088 } 2089 priv->tx_irqs[i] = irq; 2090 } 2091 } 2092 2093 priv->chip_id = chip_id; 2094 2095 priv->clk = devm_clk_get(&pdev->dev, NULL); 2096 if (IS_ERR(priv->clk)) { 2097 error = PTR_ERR(priv->clk); 2098 goto out_release; 2099 } 2100 2101 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2102 ndev->min_mtu = ETH_MIN_MTU; 2103 2104 priv->num_tx_desc = chip_id == RCAR_GEN2 ? 2105 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3; 2106 2107 /* Set function */ 2108 ndev->netdev_ops = &ravb_netdev_ops; 2109 ndev->ethtool_ops = &ravb_ethtool_ops; 2110 2111 /* Set AVB config mode */ 2112 ravb_set_config_mode(ndev); 2113 2114 /* Set GTI value */ 2115 error = ravb_set_gti(ndev); 2116 if (error) 2117 goto out_release; 2118 2119 /* Request GTI loading */ 2120 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2121 2122 if (priv->chip_id != RCAR_GEN2) 2123 ravb_set_delay_mode(ndev); 2124 2125 /* Allocate descriptor base address table */ 2126 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2127 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2128 &priv->desc_bat_dma, GFP_KERNEL); 2129 if (!priv->desc_bat) { 2130 dev_err(&pdev->dev, 2131 "Cannot allocate desc base address table (size %d bytes)\n", 2132 priv->desc_bat_size); 2133 error = -ENOMEM; 2134 goto out_release; 2135 } 2136 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2137 priv->desc_bat[q].die_dt = DT_EOS; 2138 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2139 2140 /* Initialise HW timestamp list */ 2141 INIT_LIST_HEAD(&priv->ts_skb_list); 2142 2143 /* Initialise PTP Clock driver */ 2144 if (chip_id != RCAR_GEN2) 2145 ravb_ptp_init(ndev, pdev); 2146 2147 /* Debug message level */ 2148 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2149 2150 /* Read and set MAC address */ 2151 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2152 if (!is_valid_ether_addr(ndev->dev_addr)) { 2153 dev_warn(&pdev->dev, 2154 "no valid MAC address supplied, using a random one\n"); 2155 eth_hw_addr_random(ndev); 2156 } 2157 2158 /* MDIO bus init */ 2159 error = ravb_mdio_init(priv); 2160 if (error) { 2161 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2162 goto out_dma_free; 2163 } 2164 2165 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2166 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2167 2168 /* Network device register */ 2169 error = register_netdev(ndev); 2170 if (error) 2171 goto out_napi_del; 2172 2173 device_set_wakeup_capable(&pdev->dev, 1); 2174 2175 /* Print device information */ 2176 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2177 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2178 2179 platform_set_drvdata(pdev, ndev); 2180 2181 return 0; 2182 2183 out_napi_del: 2184 netif_napi_del(&priv->napi[RAVB_NC]); 2185 netif_napi_del(&priv->napi[RAVB_BE]); 2186 ravb_mdio_release(priv); 2187 out_dma_free: 2188 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2189 priv->desc_bat_dma); 2190 2191 /* Stop PTP Clock driver */ 2192 if (chip_id != RCAR_GEN2) 2193 ravb_ptp_stop(ndev); 2194 out_release: 2195 free_netdev(ndev); 2196 2197 pm_runtime_put(&pdev->dev); 2198 pm_runtime_disable(&pdev->dev); 2199 return error; 2200 } 2201 2202 static int ravb_remove(struct platform_device *pdev) 2203 { 2204 struct net_device *ndev = platform_get_drvdata(pdev); 2205 struct ravb_private *priv = netdev_priv(ndev); 2206 2207 /* Stop PTP Clock driver */ 2208 if (priv->chip_id != RCAR_GEN2) 2209 ravb_ptp_stop(ndev); 2210 2211 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2212 priv->desc_bat_dma); 2213 /* Set reset mode */ 2214 ravb_write(ndev, CCC_OPC_RESET, CCC); 2215 pm_runtime_put_sync(&pdev->dev); 2216 unregister_netdev(ndev); 2217 netif_napi_del(&priv->napi[RAVB_NC]); 2218 netif_napi_del(&priv->napi[RAVB_BE]); 2219 ravb_mdio_release(priv); 2220 pm_runtime_disable(&pdev->dev); 2221 free_netdev(ndev); 2222 platform_set_drvdata(pdev, NULL); 2223 2224 return 0; 2225 } 2226 2227 static int ravb_wol_setup(struct net_device *ndev) 2228 { 2229 struct ravb_private *priv = netdev_priv(ndev); 2230 2231 /* Disable interrupts by clearing the interrupt masks. */ 2232 ravb_write(ndev, 0, RIC0); 2233 ravb_write(ndev, 0, RIC2); 2234 ravb_write(ndev, 0, TIC); 2235 2236 /* Only allow ECI interrupts */ 2237 synchronize_irq(priv->emac_irq); 2238 napi_disable(&priv->napi[RAVB_NC]); 2239 napi_disable(&priv->napi[RAVB_BE]); 2240 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2241 2242 /* Enable MagicPacket */ 2243 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2244 2245 return enable_irq_wake(priv->emac_irq); 2246 } 2247 2248 static int ravb_wol_restore(struct net_device *ndev) 2249 { 2250 struct ravb_private *priv = netdev_priv(ndev); 2251 int ret; 2252 2253 napi_enable(&priv->napi[RAVB_NC]); 2254 napi_enable(&priv->napi[RAVB_BE]); 2255 2256 /* Disable MagicPacket */ 2257 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2258 2259 ret = ravb_close(ndev); 2260 if (ret < 0) 2261 return ret; 2262 2263 return disable_irq_wake(priv->emac_irq); 2264 } 2265 2266 static int __maybe_unused ravb_suspend(struct device *dev) 2267 { 2268 struct net_device *ndev = dev_get_drvdata(dev); 2269 struct ravb_private *priv = netdev_priv(ndev); 2270 int ret; 2271 2272 if (!netif_running(ndev)) 2273 return 0; 2274 2275 netif_device_detach(ndev); 2276 2277 if (priv->wol_enabled) 2278 ret = ravb_wol_setup(ndev); 2279 else 2280 ret = ravb_close(ndev); 2281 2282 return ret; 2283 } 2284 2285 static int __maybe_unused ravb_resume(struct device *dev) 2286 { 2287 struct net_device *ndev = dev_get_drvdata(dev); 2288 struct ravb_private *priv = netdev_priv(ndev); 2289 int ret = 0; 2290 2291 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2292 if (priv->wol_enabled) 2293 ravb_write(ndev, CCC_OPC_RESET, CCC); 2294 2295 /* All register have been reset to default values. 2296 * Restore all registers which where setup at probe time and 2297 * reopen device if it was running before system suspended. 2298 */ 2299 2300 /* Set AVB config mode */ 2301 ravb_set_config_mode(ndev); 2302 2303 /* Set GTI value */ 2304 ret = ravb_set_gti(ndev); 2305 if (ret) 2306 return ret; 2307 2308 /* Request GTI loading */ 2309 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2310 2311 if (priv->chip_id != RCAR_GEN2) 2312 ravb_set_delay_mode(ndev); 2313 2314 /* Restore descriptor base address table */ 2315 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2316 2317 if (netif_running(ndev)) { 2318 if (priv->wol_enabled) { 2319 ret = ravb_wol_restore(ndev); 2320 if (ret) 2321 return ret; 2322 } 2323 ret = ravb_open(ndev); 2324 if (ret < 0) 2325 return ret; 2326 netif_device_attach(ndev); 2327 } 2328 2329 return ret; 2330 } 2331 2332 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2333 { 2334 /* Runtime PM callback shared between ->runtime_suspend() 2335 * and ->runtime_resume(). Simply returns success. 2336 * 2337 * This driver re-initializes all registers after 2338 * pm_runtime_get_sync() anyway so there is no need 2339 * to save and restore registers here. 2340 */ 2341 return 0; 2342 } 2343 2344 static const struct dev_pm_ops ravb_dev_pm_ops = { 2345 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2346 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2347 }; 2348 2349 static struct platform_driver ravb_driver = { 2350 .probe = ravb_probe, 2351 .remove = ravb_remove, 2352 .driver = { 2353 .name = "ravb", 2354 .pm = &ravb_dev_pm_ops, 2355 .of_match_table = ravb_match_table, 2356 }, 2357 }; 2358 2359 module_platform_driver(ravb_driver); 2360 2361 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2362 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2363 MODULE_LICENSE("GPL v2"); 2364