1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/reset.h> 31 #include <linux/math64.h> 32 33 #include "ravb.h" 34 35 #define RAVB_DEF_MSG_ENABLE \ 36 (NETIF_MSG_LINK | \ 37 NETIF_MSG_TIMER | \ 38 NETIF_MSG_RX_ERR | \ 39 NETIF_MSG_TX_ERR) 40 41 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 42 "ch0", /* RAVB_BE */ 43 "ch1", /* RAVB_NC */ 44 }; 45 46 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 47 "ch18", /* RAVB_BE */ 48 "ch19", /* RAVB_NC */ 49 }; 50 51 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 52 u32 set) 53 { 54 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 55 } 56 57 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 58 { 59 int i; 60 61 for (i = 0; i < 10000; i++) { 62 if ((ravb_read(ndev, reg) & mask) == value) 63 return 0; 64 udelay(10); 65 } 66 return -ETIMEDOUT; 67 } 68 69 static int ravb_config(struct net_device *ndev) 70 { 71 int error; 72 73 /* Set config mode */ 74 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 75 /* Check if the operating mode is changed to the config mode */ 76 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 77 if (error) 78 netdev_err(ndev, "failed to switch device to config mode\n"); 79 80 return error; 81 } 82 83 static void ravb_set_rate_gbeth(struct net_device *ndev) 84 { 85 struct ravb_private *priv = netdev_priv(ndev); 86 87 switch (priv->speed) { 88 case 10: /* 10BASE */ 89 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 90 break; 91 case 100: /* 100BASE */ 92 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 93 break; 94 case 1000: /* 1000BASE */ 95 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 96 break; 97 } 98 } 99 100 static void ravb_set_rate_rcar(struct net_device *ndev) 101 { 102 struct ravb_private *priv = netdev_priv(ndev); 103 104 switch (priv->speed) { 105 case 100: /* 100BASE */ 106 ravb_write(ndev, GECMR_SPEED_100, GECMR); 107 break; 108 case 1000: /* 1000BASE */ 109 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 110 break; 111 } 112 } 113 114 static void ravb_set_buffer_align(struct sk_buff *skb) 115 { 116 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 117 118 if (reserve) 119 skb_reserve(skb, RAVB_ALIGN - reserve); 120 } 121 122 /* Get MAC address from the MAC address registers 123 * 124 * Ethernet AVB device doesn't have ROM for MAC address. 125 * This function gets the MAC address that was used by a bootloader. 126 */ 127 static void ravb_read_mac_address(struct device_node *np, 128 struct net_device *ndev) 129 { 130 int ret; 131 132 ret = of_get_ethdev_address(np, ndev); 133 if (ret) { 134 u32 mahr = ravb_read(ndev, MAHR); 135 u32 malr = ravb_read(ndev, MALR); 136 u8 addr[ETH_ALEN]; 137 138 addr[0] = (mahr >> 24) & 0xFF; 139 addr[1] = (mahr >> 16) & 0xFF; 140 addr[2] = (mahr >> 8) & 0xFF; 141 addr[3] = (mahr >> 0) & 0xFF; 142 addr[4] = (malr >> 8) & 0xFF; 143 addr[5] = (malr >> 0) & 0xFF; 144 eth_hw_addr_set(ndev, addr); 145 } 146 } 147 148 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 149 { 150 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 151 mdiobb); 152 153 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 154 } 155 156 /* MDC pin control */ 157 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 158 { 159 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 160 } 161 162 /* Data I/O pin control */ 163 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 164 { 165 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 166 } 167 168 /* Set data bit */ 169 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 170 { 171 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 172 } 173 174 /* Get data bit */ 175 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 176 { 177 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 178 mdiobb); 179 180 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 181 } 182 183 /* MDIO bus control struct */ 184 static const struct mdiobb_ops bb_ops = { 185 .owner = THIS_MODULE, 186 .set_mdc = ravb_set_mdc, 187 .set_mdio_dir = ravb_set_mdio_dir, 188 .set_mdio_data = ravb_set_mdio_data, 189 .get_mdio_data = ravb_get_mdio_data, 190 }; 191 192 /* Free TX skb function for AVB-IP */ 193 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 194 { 195 struct ravb_private *priv = netdev_priv(ndev); 196 struct net_device_stats *stats = &priv->stats[q]; 197 unsigned int num_tx_desc = priv->num_tx_desc; 198 struct ravb_tx_desc *desc; 199 unsigned int entry; 200 int free_num = 0; 201 u32 size; 202 203 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 204 bool txed; 205 206 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 207 num_tx_desc); 208 desc = &priv->tx_ring[q][entry]; 209 txed = desc->die_dt == DT_FEMPTY; 210 if (free_txed_only && !txed) 211 break; 212 /* Descriptor type must be checked before all other reads */ 213 dma_rmb(); 214 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 215 /* Free the original skb. */ 216 if (priv->tx_skb[q][entry / num_tx_desc]) { 217 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 218 size, DMA_TO_DEVICE); 219 /* Last packet descriptor? */ 220 if (entry % num_tx_desc == num_tx_desc - 1) { 221 entry /= num_tx_desc; 222 dev_kfree_skb_any(priv->tx_skb[q][entry]); 223 priv->tx_skb[q][entry] = NULL; 224 if (txed) 225 stats->tx_packets++; 226 } 227 free_num++; 228 } 229 if (txed) 230 stats->tx_bytes += size; 231 desc->die_dt = DT_EEMPTY; 232 } 233 return free_num; 234 } 235 236 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q) 237 { 238 struct ravb_private *priv = netdev_priv(ndev); 239 unsigned int ring_size; 240 unsigned int i; 241 242 if (!priv->gbeth_rx_ring) 243 return; 244 245 for (i = 0; i < priv->num_rx_ring[q]; i++) { 246 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i]; 247 248 if (!dma_mapping_error(ndev->dev.parent, 249 le32_to_cpu(desc->dptr))) 250 dma_unmap_single(ndev->dev.parent, 251 le32_to_cpu(desc->dptr), 252 GBETH_RX_BUFF_MAX, 253 DMA_FROM_DEVICE); 254 } 255 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 256 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring, 257 priv->rx_desc_dma[q]); 258 priv->gbeth_rx_ring = NULL; 259 } 260 261 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q) 262 { 263 struct ravb_private *priv = netdev_priv(ndev); 264 unsigned int ring_size; 265 unsigned int i; 266 267 if (!priv->rx_ring[q]) 268 return; 269 270 for (i = 0; i < priv->num_rx_ring[q]; i++) { 271 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 272 273 if (!dma_mapping_error(ndev->dev.parent, 274 le32_to_cpu(desc->dptr))) 275 dma_unmap_single(ndev->dev.parent, 276 le32_to_cpu(desc->dptr), 277 RX_BUF_SZ, 278 DMA_FROM_DEVICE); 279 } 280 ring_size = sizeof(struct ravb_ex_rx_desc) * 281 (priv->num_rx_ring[q] + 1); 282 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 283 priv->rx_desc_dma[q]); 284 priv->rx_ring[q] = NULL; 285 } 286 287 /* Free skb's and DMA buffers for Ethernet AVB */ 288 static void ravb_ring_free(struct net_device *ndev, int q) 289 { 290 struct ravb_private *priv = netdev_priv(ndev); 291 const struct ravb_hw_info *info = priv->info; 292 unsigned int num_tx_desc = priv->num_tx_desc; 293 unsigned int ring_size; 294 unsigned int i; 295 296 info->rx_ring_free(ndev, q); 297 298 if (priv->tx_ring[q]) { 299 ravb_tx_free(ndev, q, false); 300 301 ring_size = sizeof(struct ravb_tx_desc) * 302 (priv->num_tx_ring[q] * num_tx_desc + 1); 303 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 304 priv->tx_desc_dma[q]); 305 priv->tx_ring[q] = NULL; 306 } 307 308 /* Free RX skb ringbuffer */ 309 if (priv->rx_skb[q]) { 310 for (i = 0; i < priv->num_rx_ring[q]; i++) 311 dev_kfree_skb(priv->rx_skb[q][i]); 312 } 313 kfree(priv->rx_skb[q]); 314 priv->rx_skb[q] = NULL; 315 316 /* Free aligned TX buffers */ 317 kfree(priv->tx_align[q]); 318 priv->tx_align[q] = NULL; 319 320 /* Free TX skb ringbuffer. 321 * SKBs are freed by ravb_tx_free() call above. 322 */ 323 kfree(priv->tx_skb[q]); 324 priv->tx_skb[q] = NULL; 325 } 326 327 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q) 328 { 329 struct ravb_private *priv = netdev_priv(ndev); 330 struct ravb_rx_desc *rx_desc; 331 unsigned int rx_ring_size; 332 dma_addr_t dma_addr; 333 unsigned int i; 334 335 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 336 memset(priv->gbeth_rx_ring, 0, rx_ring_size); 337 /* Build RX ring buffer */ 338 for (i = 0; i < priv->num_rx_ring[q]; i++) { 339 /* RX descriptor */ 340 rx_desc = &priv->gbeth_rx_ring[i]; 341 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 342 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 343 GBETH_RX_BUFF_MAX, 344 DMA_FROM_DEVICE); 345 /* We just set the data size to 0 for a failed mapping which 346 * should prevent DMA from happening... 347 */ 348 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 349 rx_desc->ds_cc = cpu_to_le16(0); 350 rx_desc->dptr = cpu_to_le32(dma_addr); 351 rx_desc->die_dt = DT_FEMPTY; 352 } 353 rx_desc = &priv->gbeth_rx_ring[i]; 354 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 355 rx_desc->die_dt = DT_LINKFIX; /* type */ 356 } 357 358 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q) 359 { 360 struct ravb_private *priv = netdev_priv(ndev); 361 struct ravb_ex_rx_desc *rx_desc; 362 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 363 dma_addr_t dma_addr; 364 unsigned int i; 365 366 memset(priv->rx_ring[q], 0, rx_ring_size); 367 /* Build RX ring buffer */ 368 for (i = 0; i < priv->num_rx_ring[q]; i++) { 369 /* RX descriptor */ 370 rx_desc = &priv->rx_ring[q][i]; 371 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 372 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 373 RX_BUF_SZ, 374 DMA_FROM_DEVICE); 375 /* We just set the data size to 0 for a failed mapping which 376 * should prevent DMA from happening... 377 */ 378 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 379 rx_desc->ds_cc = cpu_to_le16(0); 380 rx_desc->dptr = cpu_to_le32(dma_addr); 381 rx_desc->die_dt = DT_FEMPTY; 382 } 383 rx_desc = &priv->rx_ring[q][i]; 384 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 385 rx_desc->die_dt = DT_LINKFIX; /* type */ 386 } 387 388 /* Format skb and descriptor buffer for Ethernet AVB */ 389 static void ravb_ring_format(struct net_device *ndev, int q) 390 { 391 struct ravb_private *priv = netdev_priv(ndev); 392 const struct ravb_hw_info *info = priv->info; 393 unsigned int num_tx_desc = priv->num_tx_desc; 394 struct ravb_tx_desc *tx_desc; 395 struct ravb_desc *desc; 396 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 397 num_tx_desc; 398 unsigned int i; 399 400 priv->cur_rx[q] = 0; 401 priv->cur_tx[q] = 0; 402 priv->dirty_rx[q] = 0; 403 priv->dirty_tx[q] = 0; 404 405 info->rx_ring_format(ndev, q); 406 407 memset(priv->tx_ring[q], 0, tx_ring_size); 408 /* Build TX ring buffer */ 409 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 410 i++, tx_desc++) { 411 tx_desc->die_dt = DT_EEMPTY; 412 if (num_tx_desc > 1) { 413 tx_desc++; 414 tx_desc->die_dt = DT_EEMPTY; 415 } 416 } 417 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 418 tx_desc->die_dt = DT_LINKFIX; /* type */ 419 420 /* RX descriptor base address for best effort */ 421 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 422 desc->die_dt = DT_LINKFIX; /* type */ 423 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 424 425 /* TX descriptor base address for best effort */ 426 desc = &priv->desc_bat[q]; 427 desc->die_dt = DT_LINKFIX; /* type */ 428 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 429 } 430 431 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q) 432 { 433 struct ravb_private *priv = netdev_priv(ndev); 434 unsigned int ring_size; 435 436 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 437 438 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size, 439 &priv->rx_desc_dma[q], 440 GFP_KERNEL); 441 return priv->gbeth_rx_ring; 442 } 443 444 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q) 445 { 446 struct ravb_private *priv = netdev_priv(ndev); 447 unsigned int ring_size; 448 449 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 450 451 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 452 &priv->rx_desc_dma[q], 453 GFP_KERNEL); 454 return priv->rx_ring[q]; 455 } 456 457 /* Init skb and descriptor buffer for Ethernet AVB */ 458 static int ravb_ring_init(struct net_device *ndev, int q) 459 { 460 struct ravb_private *priv = netdev_priv(ndev); 461 const struct ravb_hw_info *info = priv->info; 462 unsigned int num_tx_desc = priv->num_tx_desc; 463 unsigned int ring_size; 464 struct sk_buff *skb; 465 unsigned int i; 466 467 /* Allocate RX and TX skb rings */ 468 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 469 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 470 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 471 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 472 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 473 goto error; 474 475 for (i = 0; i < priv->num_rx_ring[q]; i++) { 476 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL); 477 if (!skb) 478 goto error; 479 ravb_set_buffer_align(skb); 480 priv->rx_skb[q][i] = skb; 481 } 482 483 if (num_tx_desc > 1) { 484 /* Allocate rings for the aligned buffers */ 485 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 486 DPTR_ALIGN - 1, GFP_KERNEL); 487 if (!priv->tx_align[q]) 488 goto error; 489 } 490 491 /* Allocate all RX descriptors. */ 492 if (!info->alloc_rx_desc(ndev, q)) 493 goto error; 494 495 priv->dirty_rx[q] = 0; 496 497 /* Allocate all TX descriptors. */ 498 ring_size = sizeof(struct ravb_tx_desc) * 499 (priv->num_tx_ring[q] * num_tx_desc + 1); 500 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 501 &priv->tx_desc_dma[q], 502 GFP_KERNEL); 503 if (!priv->tx_ring[q]) 504 goto error; 505 506 return 0; 507 508 error: 509 ravb_ring_free(ndev, q); 510 511 return -ENOMEM; 512 } 513 514 static void ravb_emac_init_gbeth(struct net_device *ndev) 515 { 516 struct ravb_private *priv = netdev_priv(ndev); 517 518 /* Receive frame limit set register */ 519 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); 520 521 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 522 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 523 ECMR_TE | ECMR_RE | ECMR_RCPT | 524 ECMR_TXF | ECMR_RXF, ECMR); 525 526 ravb_set_rate_gbeth(ndev); 527 528 /* Set MAC address */ 529 ravb_write(ndev, 530 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 531 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 532 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 533 534 /* E-MAC status register clear */ 535 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 536 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 537 538 /* E-MAC interrupt enable register */ 539 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 540 541 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 542 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 543 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 544 } else { 545 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 546 CXR31_SEL_LINK0); 547 } 548 } 549 550 static void ravb_emac_init_rcar(struct net_device *ndev) 551 { 552 /* Receive frame limit set register */ 553 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 554 555 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 556 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 557 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 558 ECMR_TE | ECMR_RE, ECMR); 559 560 ravb_set_rate_rcar(ndev); 561 562 /* Set MAC address */ 563 ravb_write(ndev, 564 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 565 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 566 ravb_write(ndev, 567 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 568 569 /* E-MAC status register clear */ 570 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 571 572 /* E-MAC interrupt enable register */ 573 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 574 } 575 576 /* E-MAC init function */ 577 static void ravb_emac_init(struct net_device *ndev) 578 { 579 struct ravb_private *priv = netdev_priv(ndev); 580 const struct ravb_hw_info *info = priv->info; 581 582 info->emac_init(ndev); 583 } 584 585 static int ravb_dmac_init_gbeth(struct net_device *ndev) 586 { 587 int error; 588 589 error = ravb_ring_init(ndev, RAVB_BE); 590 if (error) 591 return error; 592 593 /* Descriptor format */ 594 ravb_ring_format(ndev, RAVB_BE); 595 596 /* Set DMAC RX */ 597 ravb_write(ndev, 0x60000000, RCR); 598 599 /* Set Max Frame Length (RTC) */ 600 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC); 601 602 /* Set FIFO size */ 603 ravb_write(ndev, 0x00222200, TGC); 604 605 ravb_write(ndev, 0, TCCR); 606 607 /* Frame receive */ 608 ravb_write(ndev, RIC0_FRE0, RIC0); 609 /* Disable FIFO full warning */ 610 ravb_write(ndev, 0x0, RIC1); 611 /* Receive FIFO full error, descriptor empty */ 612 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 613 614 ravb_write(ndev, TIC_FTE0, TIC); 615 616 return 0; 617 } 618 619 static int ravb_dmac_init_rcar(struct net_device *ndev) 620 { 621 struct ravb_private *priv = netdev_priv(ndev); 622 const struct ravb_hw_info *info = priv->info; 623 int error; 624 625 error = ravb_ring_init(ndev, RAVB_BE); 626 if (error) 627 return error; 628 error = ravb_ring_init(ndev, RAVB_NC); 629 if (error) { 630 ravb_ring_free(ndev, RAVB_BE); 631 return error; 632 } 633 634 /* Descriptor format */ 635 ravb_ring_format(ndev, RAVB_BE); 636 ravb_ring_format(ndev, RAVB_NC); 637 638 /* Set AVB RX */ 639 ravb_write(ndev, 640 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 641 642 /* Set FIFO size */ 643 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 644 645 /* Timestamp enable */ 646 ravb_write(ndev, TCCR_TFEN, TCCR); 647 648 /* Interrupt init: */ 649 if (info->multi_irqs) { 650 /* Clear DIL.DPLx */ 651 ravb_write(ndev, 0, DIL); 652 /* Set queue specific interrupt */ 653 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 654 } 655 /* Frame receive */ 656 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 657 /* Disable FIFO full warning */ 658 ravb_write(ndev, 0, RIC1); 659 /* Receive FIFO full error, descriptor empty */ 660 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 661 /* Frame transmitted, timestamp FIFO updated */ 662 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 663 664 return 0; 665 } 666 667 /* Device init function for Ethernet AVB */ 668 static int ravb_dmac_init(struct net_device *ndev) 669 { 670 struct ravb_private *priv = netdev_priv(ndev); 671 const struct ravb_hw_info *info = priv->info; 672 int error; 673 674 /* Set CONFIG mode */ 675 error = ravb_config(ndev); 676 if (error) 677 return error; 678 679 error = info->dmac_init(ndev); 680 if (error) 681 return error; 682 683 /* Setting the control will start the AVB-DMAC process. */ 684 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 685 686 return 0; 687 } 688 689 static void ravb_get_tx_tstamp(struct net_device *ndev) 690 { 691 struct ravb_private *priv = netdev_priv(ndev); 692 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 693 struct skb_shared_hwtstamps shhwtstamps; 694 struct sk_buff *skb; 695 struct timespec64 ts; 696 u16 tag, tfa_tag; 697 int count; 698 u32 tfa2; 699 700 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 701 while (count--) { 702 tfa2 = ravb_read(ndev, TFA2); 703 tfa_tag = (tfa2 & TFA2_TST) >> 16; 704 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 705 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 706 ravb_read(ndev, TFA1); 707 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 708 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 709 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 710 list) { 711 skb = ts_skb->skb; 712 tag = ts_skb->tag; 713 list_del(&ts_skb->list); 714 kfree(ts_skb); 715 if (tag == tfa_tag) { 716 skb_tstamp_tx(skb, &shhwtstamps); 717 dev_consume_skb_any(skb); 718 break; 719 } else { 720 dev_kfree_skb_any(skb); 721 } 722 } 723 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 724 } 725 } 726 727 static void ravb_rx_csum(struct sk_buff *skb) 728 { 729 u8 *hw_csum; 730 731 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 732 * appended to packet data 733 */ 734 if (unlikely(skb->len < sizeof(__sum16))) 735 return; 736 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 737 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 738 skb->ip_summed = CHECKSUM_COMPLETE; 739 skb_trim(skb, skb->len - sizeof(__sum16)); 740 } 741 742 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry, 743 struct ravb_rx_desc *desc) 744 { 745 struct ravb_private *priv = netdev_priv(ndev); 746 struct sk_buff *skb; 747 748 skb = priv->rx_skb[RAVB_BE][entry]; 749 priv->rx_skb[RAVB_BE][entry] = NULL; 750 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 751 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE); 752 753 return skb; 754 } 755 756 /* Packet receive function for Gigabit Ethernet */ 757 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) 758 { 759 struct ravb_private *priv = netdev_priv(ndev); 760 const struct ravb_hw_info *info = priv->info; 761 struct net_device_stats *stats; 762 struct ravb_rx_desc *desc; 763 struct sk_buff *skb; 764 dma_addr_t dma_addr; 765 u8 desc_status; 766 int boguscnt; 767 u16 pkt_len; 768 u8 die_dt; 769 int entry; 770 int limit; 771 772 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 773 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 774 stats = &priv->stats[q]; 775 776 boguscnt = min(boguscnt, *quota); 777 limit = boguscnt; 778 desc = &priv->gbeth_rx_ring[entry]; 779 while (desc->die_dt != DT_FEMPTY) { 780 /* Descriptor type must be checked before all other reads */ 781 dma_rmb(); 782 desc_status = desc->msc; 783 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 784 785 if (--boguscnt < 0) 786 break; 787 788 /* We use 0-byte descriptors to mark the DMA mapping errors */ 789 if (!pkt_len) 790 continue; 791 792 if (desc_status & MSC_MC) 793 stats->multicast++; 794 795 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 796 stats->rx_errors++; 797 if (desc_status & MSC_CRC) 798 stats->rx_crc_errors++; 799 if (desc_status & MSC_RFE) 800 stats->rx_frame_errors++; 801 if (desc_status & (MSC_RTLF | MSC_RTSF)) 802 stats->rx_length_errors++; 803 if (desc_status & MSC_CEEF) 804 stats->rx_missed_errors++; 805 } else { 806 die_dt = desc->die_dt & 0xF0; 807 switch (die_dt) { 808 case DT_FSINGLE: 809 skb = ravb_get_skb_gbeth(ndev, entry, desc); 810 skb_put(skb, pkt_len); 811 skb->protocol = eth_type_trans(skb, ndev); 812 napi_gro_receive(&priv->napi[q], skb); 813 stats->rx_packets++; 814 stats->rx_bytes += pkt_len; 815 break; 816 case DT_FSTART: 817 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc); 818 skb_put(priv->rx_1st_skb, pkt_len); 819 break; 820 case DT_FMID: 821 skb = ravb_get_skb_gbeth(ndev, entry, desc); 822 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 823 priv->rx_1st_skb->len, 824 skb->data, 825 pkt_len); 826 skb_put(priv->rx_1st_skb, pkt_len); 827 dev_kfree_skb(skb); 828 break; 829 case DT_FEND: 830 skb = ravb_get_skb_gbeth(ndev, entry, desc); 831 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 832 priv->rx_1st_skb->len, 833 skb->data, 834 pkt_len); 835 skb_put(priv->rx_1st_skb, pkt_len); 836 dev_kfree_skb(skb); 837 priv->rx_1st_skb->protocol = 838 eth_type_trans(priv->rx_1st_skb, ndev); 839 napi_gro_receive(&priv->napi[q], 840 priv->rx_1st_skb); 841 stats->rx_packets++; 842 stats->rx_bytes += pkt_len; 843 break; 844 } 845 } 846 847 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 848 desc = &priv->gbeth_rx_ring[entry]; 849 } 850 851 /* Refill the RX ring buffers. */ 852 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 853 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 854 desc = &priv->gbeth_rx_ring[entry]; 855 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 856 857 if (!priv->rx_skb[q][entry]) { 858 skb = netdev_alloc_skb(ndev, info->max_rx_len); 859 if (!skb) 860 break; 861 ravb_set_buffer_align(skb); 862 dma_addr = dma_map_single(ndev->dev.parent, 863 skb->data, 864 GBETH_RX_BUFF_MAX, 865 DMA_FROM_DEVICE); 866 skb_checksum_none_assert(skb); 867 /* We just set the data size to 0 for a failed mapping 868 * which should prevent DMA from happening... 869 */ 870 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 871 desc->ds_cc = cpu_to_le16(0); 872 desc->dptr = cpu_to_le32(dma_addr); 873 priv->rx_skb[q][entry] = skb; 874 } 875 /* Descriptor type must be set after all the above writes */ 876 dma_wmb(); 877 desc->die_dt = DT_FEMPTY; 878 } 879 880 *quota -= limit - (++boguscnt); 881 882 return boguscnt <= 0; 883 } 884 885 /* Packet receive function for Ethernet AVB */ 886 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q) 887 { 888 struct ravb_private *priv = netdev_priv(ndev); 889 const struct ravb_hw_info *info = priv->info; 890 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 891 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 892 priv->cur_rx[q]; 893 struct net_device_stats *stats = &priv->stats[q]; 894 struct ravb_ex_rx_desc *desc; 895 struct sk_buff *skb; 896 dma_addr_t dma_addr; 897 struct timespec64 ts; 898 u8 desc_status; 899 u16 pkt_len; 900 int limit; 901 902 boguscnt = min(boguscnt, *quota); 903 limit = boguscnt; 904 desc = &priv->rx_ring[q][entry]; 905 while (desc->die_dt != DT_FEMPTY) { 906 /* Descriptor type must be checked before all other reads */ 907 dma_rmb(); 908 desc_status = desc->msc; 909 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 910 911 if (--boguscnt < 0) 912 break; 913 914 /* We use 0-byte descriptors to mark the DMA mapping errors */ 915 if (!pkt_len) 916 continue; 917 918 if (desc_status & MSC_MC) 919 stats->multicast++; 920 921 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 922 MSC_CEEF)) { 923 stats->rx_errors++; 924 if (desc_status & MSC_CRC) 925 stats->rx_crc_errors++; 926 if (desc_status & MSC_RFE) 927 stats->rx_frame_errors++; 928 if (desc_status & (MSC_RTLF | MSC_RTSF)) 929 stats->rx_length_errors++; 930 if (desc_status & MSC_CEEF) 931 stats->rx_missed_errors++; 932 } else { 933 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 934 935 skb = priv->rx_skb[q][entry]; 936 priv->rx_skb[q][entry] = NULL; 937 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 938 RX_BUF_SZ, 939 DMA_FROM_DEVICE); 940 get_ts &= (q == RAVB_NC) ? 941 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 942 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 943 if (get_ts) { 944 struct skb_shared_hwtstamps *shhwtstamps; 945 946 shhwtstamps = skb_hwtstamps(skb); 947 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 948 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 949 32) | le32_to_cpu(desc->ts_sl); 950 ts.tv_nsec = le32_to_cpu(desc->ts_n); 951 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 952 } 953 954 skb_put(skb, pkt_len); 955 skb->protocol = eth_type_trans(skb, ndev); 956 if (ndev->features & NETIF_F_RXCSUM) 957 ravb_rx_csum(skb); 958 napi_gro_receive(&priv->napi[q], skb); 959 stats->rx_packets++; 960 stats->rx_bytes += pkt_len; 961 } 962 963 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 964 desc = &priv->rx_ring[q][entry]; 965 } 966 967 /* Refill the RX ring buffers. */ 968 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 969 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 970 desc = &priv->rx_ring[q][entry]; 971 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 972 973 if (!priv->rx_skb[q][entry]) { 974 skb = netdev_alloc_skb(ndev, info->max_rx_len); 975 if (!skb) 976 break; /* Better luck next round. */ 977 ravb_set_buffer_align(skb); 978 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 979 le16_to_cpu(desc->ds_cc), 980 DMA_FROM_DEVICE); 981 skb_checksum_none_assert(skb); 982 /* We just set the data size to 0 for a failed mapping 983 * which should prevent DMA from happening... 984 */ 985 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 986 desc->ds_cc = cpu_to_le16(0); 987 desc->dptr = cpu_to_le32(dma_addr); 988 priv->rx_skb[q][entry] = skb; 989 } 990 /* Descriptor type must be set after all the above writes */ 991 dma_wmb(); 992 desc->die_dt = DT_FEMPTY; 993 } 994 995 *quota -= limit - (++boguscnt); 996 997 return boguscnt <= 0; 998 } 999 1000 /* Packet receive function for Ethernet AVB */ 1001 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 1002 { 1003 struct ravb_private *priv = netdev_priv(ndev); 1004 const struct ravb_hw_info *info = priv->info; 1005 1006 return info->receive(ndev, quota, q); 1007 } 1008 1009 static void ravb_rcv_snd_disable(struct net_device *ndev) 1010 { 1011 /* Disable TX and RX */ 1012 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1013 } 1014 1015 static void ravb_rcv_snd_enable(struct net_device *ndev) 1016 { 1017 /* Enable TX and RX */ 1018 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1019 } 1020 1021 /* function for waiting dma process finished */ 1022 static int ravb_stop_dma(struct net_device *ndev) 1023 { 1024 struct ravb_private *priv = netdev_priv(ndev); 1025 const struct ravb_hw_info *info = priv->info; 1026 int error; 1027 1028 /* Wait for stopping the hardware TX process */ 1029 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1030 1031 if (error) 1032 return error; 1033 1034 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1035 0); 1036 if (error) 1037 return error; 1038 1039 /* Stop the E-MAC's RX/TX processes. */ 1040 ravb_rcv_snd_disable(ndev); 1041 1042 /* Wait for stopping the RX DMA process */ 1043 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1044 if (error) 1045 return error; 1046 1047 /* Stop AVB-DMAC process */ 1048 return ravb_config(ndev); 1049 } 1050 1051 /* E-MAC interrupt handler */ 1052 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1053 { 1054 struct ravb_private *priv = netdev_priv(ndev); 1055 u32 ecsr, psr; 1056 1057 ecsr = ravb_read(ndev, ECSR); 1058 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1059 1060 if (ecsr & ECSR_MPD) 1061 pm_wakeup_event(&priv->pdev->dev, 0); 1062 if (ecsr & ECSR_ICD) 1063 ndev->stats.tx_carrier_errors++; 1064 if (ecsr & ECSR_LCHNG) { 1065 /* Link changed */ 1066 if (priv->no_avb_link) 1067 return; 1068 psr = ravb_read(ndev, PSR); 1069 if (priv->avb_link_active_low) 1070 psr ^= PSR_LMON; 1071 if (!(psr & PSR_LMON)) { 1072 /* DIsable RX and TX */ 1073 ravb_rcv_snd_disable(ndev); 1074 } else { 1075 /* Enable RX and TX */ 1076 ravb_rcv_snd_enable(ndev); 1077 } 1078 } 1079 } 1080 1081 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1082 { 1083 struct net_device *ndev = dev_id; 1084 struct ravb_private *priv = netdev_priv(ndev); 1085 1086 spin_lock(&priv->lock); 1087 ravb_emac_interrupt_unlocked(ndev); 1088 spin_unlock(&priv->lock); 1089 return IRQ_HANDLED; 1090 } 1091 1092 /* Error interrupt handler */ 1093 static void ravb_error_interrupt(struct net_device *ndev) 1094 { 1095 struct ravb_private *priv = netdev_priv(ndev); 1096 u32 eis, ris2; 1097 1098 eis = ravb_read(ndev, EIS); 1099 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1100 if (eis & EIS_QFS) { 1101 ris2 = ravb_read(ndev, RIS2); 1102 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1103 RIS2); 1104 1105 /* Receive Descriptor Empty int */ 1106 if (ris2 & RIS2_QFF0) 1107 priv->stats[RAVB_BE].rx_over_errors++; 1108 1109 /* Receive Descriptor Empty int */ 1110 if (ris2 & RIS2_QFF1) 1111 priv->stats[RAVB_NC].rx_over_errors++; 1112 1113 /* Receive FIFO Overflow int */ 1114 if (ris2 & RIS2_RFFF) 1115 priv->rx_fifo_errors++; 1116 } 1117 } 1118 1119 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1120 { 1121 struct ravb_private *priv = netdev_priv(ndev); 1122 const struct ravb_hw_info *info = priv->info; 1123 u32 ris0 = ravb_read(ndev, RIS0); 1124 u32 ric0 = ravb_read(ndev, RIC0); 1125 u32 tis = ravb_read(ndev, TIS); 1126 u32 tic = ravb_read(ndev, TIC); 1127 1128 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1129 if (napi_schedule_prep(&priv->napi[q])) { 1130 /* Mask RX and TX interrupts */ 1131 if (!info->irq_en_dis) { 1132 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1133 ravb_write(ndev, tic & ~BIT(q), TIC); 1134 } else { 1135 ravb_write(ndev, BIT(q), RID0); 1136 ravb_write(ndev, BIT(q), TID); 1137 } 1138 __napi_schedule(&priv->napi[q]); 1139 } else { 1140 netdev_warn(ndev, 1141 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1142 ris0, ric0); 1143 netdev_warn(ndev, 1144 " tx status 0x%08x, tx mask 0x%08x.\n", 1145 tis, tic); 1146 } 1147 return true; 1148 } 1149 return false; 1150 } 1151 1152 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1153 { 1154 u32 tis = ravb_read(ndev, TIS); 1155 1156 if (tis & TIS_TFUF) { 1157 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1158 ravb_get_tx_tstamp(ndev); 1159 return true; 1160 } 1161 return false; 1162 } 1163 1164 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1165 { 1166 struct net_device *ndev = dev_id; 1167 struct ravb_private *priv = netdev_priv(ndev); 1168 const struct ravb_hw_info *info = priv->info; 1169 irqreturn_t result = IRQ_NONE; 1170 u32 iss; 1171 1172 spin_lock(&priv->lock); 1173 /* Get interrupt status */ 1174 iss = ravb_read(ndev, ISS); 1175 1176 /* Received and transmitted interrupts */ 1177 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1178 int q; 1179 1180 /* Timestamp updated */ 1181 if (ravb_timestamp_interrupt(ndev)) 1182 result = IRQ_HANDLED; 1183 1184 /* Network control and best effort queue RX/TX */ 1185 if (info->nc_queues) { 1186 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1187 if (ravb_queue_interrupt(ndev, q)) 1188 result = IRQ_HANDLED; 1189 } 1190 } else { 1191 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1192 result = IRQ_HANDLED; 1193 } 1194 } 1195 1196 /* E-MAC status summary */ 1197 if (iss & ISS_MS) { 1198 ravb_emac_interrupt_unlocked(ndev); 1199 result = IRQ_HANDLED; 1200 } 1201 1202 /* Error status summary */ 1203 if (iss & ISS_ES) { 1204 ravb_error_interrupt(ndev); 1205 result = IRQ_HANDLED; 1206 } 1207 1208 /* gPTP interrupt status summary */ 1209 if (iss & ISS_CGIS) { 1210 ravb_ptp_interrupt(ndev); 1211 result = IRQ_HANDLED; 1212 } 1213 1214 spin_unlock(&priv->lock); 1215 return result; 1216 } 1217 1218 /* Timestamp/Error/gPTP interrupt handler */ 1219 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1220 { 1221 struct net_device *ndev = dev_id; 1222 struct ravb_private *priv = netdev_priv(ndev); 1223 irqreturn_t result = IRQ_NONE; 1224 u32 iss; 1225 1226 spin_lock(&priv->lock); 1227 /* Get interrupt status */ 1228 iss = ravb_read(ndev, ISS); 1229 1230 /* Timestamp updated */ 1231 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1232 result = IRQ_HANDLED; 1233 1234 /* Error status summary */ 1235 if (iss & ISS_ES) { 1236 ravb_error_interrupt(ndev); 1237 result = IRQ_HANDLED; 1238 } 1239 1240 /* gPTP interrupt status summary */ 1241 if (iss & ISS_CGIS) { 1242 ravb_ptp_interrupt(ndev); 1243 result = IRQ_HANDLED; 1244 } 1245 1246 spin_unlock(&priv->lock); 1247 return result; 1248 } 1249 1250 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1251 { 1252 struct net_device *ndev = dev_id; 1253 struct ravb_private *priv = netdev_priv(ndev); 1254 irqreturn_t result = IRQ_NONE; 1255 1256 spin_lock(&priv->lock); 1257 1258 /* Network control/Best effort queue RX/TX */ 1259 if (ravb_queue_interrupt(ndev, q)) 1260 result = IRQ_HANDLED; 1261 1262 spin_unlock(&priv->lock); 1263 return result; 1264 } 1265 1266 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1267 { 1268 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1269 } 1270 1271 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1272 { 1273 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1274 } 1275 1276 static int ravb_poll(struct napi_struct *napi, int budget) 1277 { 1278 struct net_device *ndev = napi->dev; 1279 struct ravb_private *priv = netdev_priv(ndev); 1280 const struct ravb_hw_info *info = priv->info; 1281 bool gptp = info->gptp || info->ccc_gac; 1282 struct ravb_rx_desc *desc; 1283 unsigned long flags; 1284 int q = napi - priv->napi; 1285 int mask = BIT(q); 1286 int quota = budget; 1287 unsigned int entry; 1288 1289 if (!gptp) { 1290 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 1291 desc = &priv->gbeth_rx_ring[entry]; 1292 } 1293 /* Processing RX Descriptor Ring */ 1294 /* Clear RX interrupt */ 1295 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1296 if (gptp || desc->die_dt != DT_FEMPTY) { 1297 if (ravb_rx(ndev, "a, q)) 1298 goto out; 1299 } 1300 1301 /* Processing TX Descriptor Ring */ 1302 spin_lock_irqsave(&priv->lock, flags); 1303 /* Clear TX interrupt */ 1304 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1305 ravb_tx_free(ndev, q, true); 1306 netif_wake_subqueue(ndev, q); 1307 spin_unlock_irqrestore(&priv->lock, flags); 1308 1309 napi_complete(napi); 1310 1311 /* Re-enable RX/TX interrupts */ 1312 spin_lock_irqsave(&priv->lock, flags); 1313 if (!info->irq_en_dis) { 1314 ravb_modify(ndev, RIC0, mask, mask); 1315 ravb_modify(ndev, TIC, mask, mask); 1316 } else { 1317 ravb_write(ndev, mask, RIE0); 1318 ravb_write(ndev, mask, TIE); 1319 } 1320 spin_unlock_irqrestore(&priv->lock, flags); 1321 1322 /* Receive error message handling */ 1323 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1324 if (info->nc_queues) 1325 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1326 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1327 ndev->stats.rx_over_errors = priv->rx_over_errors; 1328 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1329 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1330 out: 1331 return budget - quota; 1332 } 1333 1334 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1335 { 1336 struct ravb_private *priv = netdev_priv(ndev); 1337 1338 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1339 } 1340 1341 /* PHY state control function */ 1342 static void ravb_adjust_link(struct net_device *ndev) 1343 { 1344 struct ravb_private *priv = netdev_priv(ndev); 1345 const struct ravb_hw_info *info = priv->info; 1346 struct phy_device *phydev = ndev->phydev; 1347 bool new_state = false; 1348 unsigned long flags; 1349 1350 spin_lock_irqsave(&priv->lock, flags); 1351 1352 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1353 if (priv->no_avb_link) 1354 ravb_rcv_snd_disable(ndev); 1355 1356 if (phydev->link) { 1357 if (info->half_duplex && phydev->duplex != priv->duplex) { 1358 new_state = true; 1359 priv->duplex = phydev->duplex; 1360 ravb_set_duplex_gbeth(ndev); 1361 } 1362 1363 if (phydev->speed != priv->speed) { 1364 new_state = true; 1365 priv->speed = phydev->speed; 1366 info->set_rate(ndev); 1367 } 1368 if (!priv->link) { 1369 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1370 new_state = true; 1371 priv->link = phydev->link; 1372 } 1373 } else if (priv->link) { 1374 new_state = true; 1375 priv->link = 0; 1376 priv->speed = 0; 1377 if (info->half_duplex) 1378 priv->duplex = -1; 1379 } 1380 1381 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1382 if (priv->no_avb_link && phydev->link) 1383 ravb_rcv_snd_enable(ndev); 1384 1385 spin_unlock_irqrestore(&priv->lock, flags); 1386 1387 if (new_state && netif_msg_link(priv)) 1388 phy_print_status(phydev); 1389 } 1390 1391 /* PHY init function */ 1392 static int ravb_phy_init(struct net_device *ndev) 1393 { 1394 struct device_node *np = ndev->dev.parent->of_node; 1395 struct ravb_private *priv = netdev_priv(ndev); 1396 const struct ravb_hw_info *info = priv->info; 1397 struct phy_device *phydev; 1398 struct device_node *pn; 1399 phy_interface_t iface; 1400 int err; 1401 1402 priv->link = 0; 1403 priv->speed = 0; 1404 priv->duplex = -1; 1405 1406 /* Try connecting to PHY */ 1407 pn = of_parse_phandle(np, "phy-handle", 0); 1408 if (!pn) { 1409 /* In the case of a fixed PHY, the DT node associated 1410 * to the PHY is the Ethernet MAC DT node. 1411 */ 1412 if (of_phy_is_fixed_link(np)) { 1413 err = of_phy_register_fixed_link(np); 1414 if (err) 1415 return err; 1416 } 1417 pn = of_node_get(np); 1418 } 1419 1420 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1421 : priv->phy_interface; 1422 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1423 of_node_put(pn); 1424 if (!phydev) { 1425 netdev_err(ndev, "failed to connect PHY\n"); 1426 err = -ENOENT; 1427 goto err_deregister_fixed_link; 1428 } 1429 1430 if (!info->half_duplex) { 1431 /* 10BASE, Pause and Asym Pause is not supported */ 1432 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1433 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1434 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1435 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1436 1437 /* Half Duplex is not supported */ 1438 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1439 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1440 } 1441 1442 phy_attached_info(phydev); 1443 1444 return 0; 1445 1446 err_deregister_fixed_link: 1447 if (of_phy_is_fixed_link(np)) 1448 of_phy_deregister_fixed_link(np); 1449 1450 return err; 1451 } 1452 1453 /* PHY control start function */ 1454 static int ravb_phy_start(struct net_device *ndev) 1455 { 1456 int error; 1457 1458 error = ravb_phy_init(ndev); 1459 if (error) 1460 return error; 1461 1462 phy_start(ndev->phydev); 1463 1464 return 0; 1465 } 1466 1467 static u32 ravb_get_msglevel(struct net_device *ndev) 1468 { 1469 struct ravb_private *priv = netdev_priv(ndev); 1470 1471 return priv->msg_enable; 1472 } 1473 1474 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1475 { 1476 struct ravb_private *priv = netdev_priv(ndev); 1477 1478 priv->msg_enable = value; 1479 } 1480 1481 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1482 "rx_queue_0_current", 1483 "tx_queue_0_current", 1484 "rx_queue_0_dirty", 1485 "tx_queue_0_dirty", 1486 "rx_queue_0_packets", 1487 "tx_queue_0_packets", 1488 "rx_queue_0_bytes", 1489 "tx_queue_0_bytes", 1490 "rx_queue_0_mcast_packets", 1491 "rx_queue_0_errors", 1492 "rx_queue_0_crc_errors", 1493 "rx_queue_0_frame_errors", 1494 "rx_queue_0_length_errors", 1495 "rx_queue_0_csum_offload_errors", 1496 "rx_queue_0_over_errors", 1497 }; 1498 1499 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1500 "rx_queue_0_current", 1501 "tx_queue_0_current", 1502 "rx_queue_0_dirty", 1503 "tx_queue_0_dirty", 1504 "rx_queue_0_packets", 1505 "tx_queue_0_packets", 1506 "rx_queue_0_bytes", 1507 "tx_queue_0_bytes", 1508 "rx_queue_0_mcast_packets", 1509 "rx_queue_0_errors", 1510 "rx_queue_0_crc_errors", 1511 "rx_queue_0_frame_errors", 1512 "rx_queue_0_length_errors", 1513 "rx_queue_0_missed_errors", 1514 "rx_queue_0_over_errors", 1515 1516 "rx_queue_1_current", 1517 "tx_queue_1_current", 1518 "rx_queue_1_dirty", 1519 "tx_queue_1_dirty", 1520 "rx_queue_1_packets", 1521 "tx_queue_1_packets", 1522 "rx_queue_1_bytes", 1523 "tx_queue_1_bytes", 1524 "rx_queue_1_mcast_packets", 1525 "rx_queue_1_errors", 1526 "rx_queue_1_crc_errors", 1527 "rx_queue_1_frame_errors", 1528 "rx_queue_1_length_errors", 1529 "rx_queue_1_missed_errors", 1530 "rx_queue_1_over_errors", 1531 }; 1532 1533 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1534 { 1535 struct ravb_private *priv = netdev_priv(netdev); 1536 const struct ravb_hw_info *info = priv->info; 1537 1538 switch (sset) { 1539 case ETH_SS_STATS: 1540 return info->stats_len; 1541 default: 1542 return -EOPNOTSUPP; 1543 } 1544 } 1545 1546 static void ravb_get_ethtool_stats(struct net_device *ndev, 1547 struct ethtool_stats *estats, u64 *data) 1548 { 1549 struct ravb_private *priv = netdev_priv(ndev); 1550 const struct ravb_hw_info *info = priv->info; 1551 int num_rx_q; 1552 int i = 0; 1553 int q; 1554 1555 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1556 /* Device-specific stats */ 1557 for (q = RAVB_BE; q < num_rx_q; q++) { 1558 struct net_device_stats *stats = &priv->stats[q]; 1559 1560 data[i++] = priv->cur_rx[q]; 1561 data[i++] = priv->cur_tx[q]; 1562 data[i++] = priv->dirty_rx[q]; 1563 data[i++] = priv->dirty_tx[q]; 1564 data[i++] = stats->rx_packets; 1565 data[i++] = stats->tx_packets; 1566 data[i++] = stats->rx_bytes; 1567 data[i++] = stats->tx_bytes; 1568 data[i++] = stats->multicast; 1569 data[i++] = stats->rx_errors; 1570 data[i++] = stats->rx_crc_errors; 1571 data[i++] = stats->rx_frame_errors; 1572 data[i++] = stats->rx_length_errors; 1573 data[i++] = stats->rx_missed_errors; 1574 data[i++] = stats->rx_over_errors; 1575 } 1576 } 1577 1578 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1579 { 1580 struct ravb_private *priv = netdev_priv(ndev); 1581 const struct ravb_hw_info *info = priv->info; 1582 1583 switch (stringset) { 1584 case ETH_SS_STATS: 1585 memcpy(data, info->gstrings_stats, info->gstrings_size); 1586 break; 1587 } 1588 } 1589 1590 static void ravb_get_ringparam(struct net_device *ndev, 1591 struct ethtool_ringparam *ring, 1592 struct kernel_ethtool_ringparam *kernel_ring, 1593 struct netlink_ext_ack *extack) 1594 { 1595 struct ravb_private *priv = netdev_priv(ndev); 1596 1597 ring->rx_max_pending = BE_RX_RING_MAX; 1598 ring->tx_max_pending = BE_TX_RING_MAX; 1599 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1600 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1601 } 1602 1603 static int ravb_set_ringparam(struct net_device *ndev, 1604 struct ethtool_ringparam *ring, 1605 struct kernel_ethtool_ringparam *kernel_ring, 1606 struct netlink_ext_ack *extack) 1607 { 1608 struct ravb_private *priv = netdev_priv(ndev); 1609 const struct ravb_hw_info *info = priv->info; 1610 int error; 1611 1612 if (ring->tx_pending > BE_TX_RING_MAX || 1613 ring->rx_pending > BE_RX_RING_MAX || 1614 ring->tx_pending < BE_TX_RING_MIN || 1615 ring->rx_pending < BE_RX_RING_MIN) 1616 return -EINVAL; 1617 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1618 return -EINVAL; 1619 1620 if (netif_running(ndev)) { 1621 netif_device_detach(ndev); 1622 /* Stop PTP Clock driver */ 1623 if (info->gptp) 1624 ravb_ptp_stop(ndev); 1625 /* Wait for DMA stopping */ 1626 error = ravb_stop_dma(ndev); 1627 if (error) { 1628 netdev_err(ndev, 1629 "cannot set ringparam! Any AVB processes are still running?\n"); 1630 return error; 1631 } 1632 synchronize_irq(ndev->irq); 1633 1634 /* Free all the skb's in the RX queue and the DMA buffers. */ 1635 ravb_ring_free(ndev, RAVB_BE); 1636 if (info->nc_queues) 1637 ravb_ring_free(ndev, RAVB_NC); 1638 } 1639 1640 /* Set new parameters */ 1641 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1642 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1643 1644 if (netif_running(ndev)) { 1645 error = ravb_dmac_init(ndev); 1646 if (error) { 1647 netdev_err(ndev, 1648 "%s: ravb_dmac_init() failed, error %d\n", 1649 __func__, error); 1650 return error; 1651 } 1652 1653 ravb_emac_init(ndev); 1654 1655 /* Initialise PTP Clock driver */ 1656 if (info->gptp) 1657 ravb_ptp_init(ndev, priv->pdev); 1658 1659 netif_device_attach(ndev); 1660 } 1661 1662 return 0; 1663 } 1664 1665 static int ravb_get_ts_info(struct net_device *ndev, 1666 struct ethtool_ts_info *info) 1667 { 1668 struct ravb_private *priv = netdev_priv(ndev); 1669 const struct ravb_hw_info *hw_info = priv->info; 1670 1671 info->so_timestamping = 1672 SOF_TIMESTAMPING_TX_SOFTWARE | 1673 SOF_TIMESTAMPING_RX_SOFTWARE | 1674 SOF_TIMESTAMPING_SOFTWARE | 1675 SOF_TIMESTAMPING_TX_HARDWARE | 1676 SOF_TIMESTAMPING_RX_HARDWARE | 1677 SOF_TIMESTAMPING_RAW_HARDWARE; 1678 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1679 info->rx_filters = 1680 (1 << HWTSTAMP_FILTER_NONE) | 1681 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1682 (1 << HWTSTAMP_FILTER_ALL); 1683 if (hw_info->gptp || hw_info->ccc_gac) 1684 info->phc_index = ptp_clock_index(priv->ptp.clock); 1685 1686 return 0; 1687 } 1688 1689 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1690 { 1691 struct ravb_private *priv = netdev_priv(ndev); 1692 1693 wol->supported = WAKE_MAGIC; 1694 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1695 } 1696 1697 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1698 { 1699 struct ravb_private *priv = netdev_priv(ndev); 1700 const struct ravb_hw_info *info = priv->info; 1701 1702 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1703 return -EOPNOTSUPP; 1704 1705 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1706 1707 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1708 1709 return 0; 1710 } 1711 1712 static const struct ethtool_ops ravb_ethtool_ops = { 1713 .nway_reset = phy_ethtool_nway_reset, 1714 .get_msglevel = ravb_get_msglevel, 1715 .set_msglevel = ravb_set_msglevel, 1716 .get_link = ethtool_op_get_link, 1717 .get_strings = ravb_get_strings, 1718 .get_ethtool_stats = ravb_get_ethtool_stats, 1719 .get_sset_count = ravb_get_sset_count, 1720 .get_ringparam = ravb_get_ringparam, 1721 .set_ringparam = ravb_set_ringparam, 1722 .get_ts_info = ravb_get_ts_info, 1723 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1724 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1725 .get_wol = ravb_get_wol, 1726 .set_wol = ravb_set_wol, 1727 }; 1728 1729 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1730 struct net_device *ndev, struct device *dev, 1731 const char *ch) 1732 { 1733 char *name; 1734 int error; 1735 1736 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1737 if (!name) 1738 return -ENOMEM; 1739 error = request_irq(irq, handler, 0, name, ndev); 1740 if (error) 1741 netdev_err(ndev, "cannot request IRQ %s\n", name); 1742 1743 return error; 1744 } 1745 1746 /* Network device open function for Ethernet AVB */ 1747 static int ravb_open(struct net_device *ndev) 1748 { 1749 struct ravb_private *priv = netdev_priv(ndev); 1750 const struct ravb_hw_info *info = priv->info; 1751 struct platform_device *pdev = priv->pdev; 1752 struct device *dev = &pdev->dev; 1753 int error; 1754 1755 napi_enable(&priv->napi[RAVB_BE]); 1756 if (info->nc_queues) 1757 napi_enable(&priv->napi[RAVB_NC]); 1758 1759 if (!info->multi_irqs) { 1760 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1761 ndev->name, ndev); 1762 if (error) { 1763 netdev_err(ndev, "cannot request IRQ\n"); 1764 goto out_napi_off; 1765 } 1766 } else { 1767 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1768 dev, "ch22:multi"); 1769 if (error) 1770 goto out_napi_off; 1771 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1772 dev, "ch24:emac"); 1773 if (error) 1774 goto out_free_irq; 1775 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1776 ndev, dev, "ch0:rx_be"); 1777 if (error) 1778 goto out_free_irq_emac; 1779 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1780 ndev, dev, "ch18:tx_be"); 1781 if (error) 1782 goto out_free_irq_be_rx; 1783 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1784 ndev, dev, "ch1:rx_nc"); 1785 if (error) 1786 goto out_free_irq_be_tx; 1787 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1788 ndev, dev, "ch19:tx_nc"); 1789 if (error) 1790 goto out_free_irq_nc_rx; 1791 1792 if (info->err_mgmt_irqs) { 1793 error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt, 1794 ndev, dev, "err_a"); 1795 if (error) 1796 goto out_free_irq_nc_tx; 1797 error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt, 1798 ndev, dev, "mgmt_a"); 1799 if (error) 1800 goto out_free_irq_erra; 1801 } 1802 } 1803 1804 /* Device init */ 1805 error = ravb_dmac_init(ndev); 1806 if (error) 1807 goto out_free_irq_mgmta; 1808 ravb_emac_init(ndev); 1809 1810 /* Initialise PTP Clock driver */ 1811 if (info->gptp) 1812 ravb_ptp_init(ndev, priv->pdev); 1813 1814 netif_tx_start_all_queues(ndev); 1815 1816 /* PHY control start */ 1817 error = ravb_phy_start(ndev); 1818 if (error) 1819 goto out_ptp_stop; 1820 1821 return 0; 1822 1823 out_ptp_stop: 1824 /* Stop PTP Clock driver */ 1825 if (info->gptp) 1826 ravb_ptp_stop(ndev); 1827 out_free_irq_mgmta: 1828 if (!info->multi_irqs) 1829 goto out_free_irq; 1830 if (info->err_mgmt_irqs) 1831 free_irq(priv->mgmta_irq, ndev); 1832 out_free_irq_erra: 1833 if (info->err_mgmt_irqs) 1834 free_irq(priv->erra_irq, ndev); 1835 out_free_irq_nc_tx: 1836 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1837 out_free_irq_nc_rx: 1838 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1839 out_free_irq_be_tx: 1840 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1841 out_free_irq_be_rx: 1842 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1843 out_free_irq_emac: 1844 free_irq(priv->emac_irq, ndev); 1845 out_free_irq: 1846 free_irq(ndev->irq, ndev); 1847 out_napi_off: 1848 if (info->nc_queues) 1849 napi_disable(&priv->napi[RAVB_NC]); 1850 napi_disable(&priv->napi[RAVB_BE]); 1851 return error; 1852 } 1853 1854 /* Timeout function for Ethernet AVB */ 1855 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1856 { 1857 struct ravb_private *priv = netdev_priv(ndev); 1858 1859 netif_err(priv, tx_err, ndev, 1860 "transmit timed out, status %08x, resetting...\n", 1861 ravb_read(ndev, ISS)); 1862 1863 /* tx_errors count up */ 1864 ndev->stats.tx_errors++; 1865 1866 schedule_work(&priv->work); 1867 } 1868 1869 static void ravb_tx_timeout_work(struct work_struct *work) 1870 { 1871 struct ravb_private *priv = container_of(work, struct ravb_private, 1872 work); 1873 const struct ravb_hw_info *info = priv->info; 1874 struct net_device *ndev = priv->ndev; 1875 int error; 1876 1877 netif_tx_stop_all_queues(ndev); 1878 1879 /* Stop PTP Clock driver */ 1880 if (info->gptp) 1881 ravb_ptp_stop(ndev); 1882 1883 /* Wait for DMA stopping */ 1884 if (ravb_stop_dma(ndev)) { 1885 /* If ravb_stop_dma() fails, the hardware is still operating 1886 * for TX and/or RX. So, this should not call the following 1887 * functions because ravb_dmac_init() is possible to fail too. 1888 * Also, this should not retry ravb_stop_dma() again and again 1889 * here because it's possible to wait forever. So, this just 1890 * re-enables the TX and RX and skip the following 1891 * re-initialization procedure. 1892 */ 1893 ravb_rcv_snd_enable(ndev); 1894 goto out; 1895 } 1896 1897 ravb_ring_free(ndev, RAVB_BE); 1898 if (info->nc_queues) 1899 ravb_ring_free(ndev, RAVB_NC); 1900 1901 /* Device init */ 1902 error = ravb_dmac_init(ndev); 1903 if (error) { 1904 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1905 * should return here to avoid re-enabling the TX and RX in 1906 * ravb_emac_init(). 1907 */ 1908 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1909 __func__, error); 1910 return; 1911 } 1912 ravb_emac_init(ndev); 1913 1914 out: 1915 /* Initialise PTP Clock driver */ 1916 if (info->gptp) 1917 ravb_ptp_init(ndev, priv->pdev); 1918 1919 netif_tx_start_all_queues(ndev); 1920 } 1921 1922 /* Packet transmit function for Ethernet AVB */ 1923 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1924 { 1925 struct ravb_private *priv = netdev_priv(ndev); 1926 const struct ravb_hw_info *info = priv->info; 1927 unsigned int num_tx_desc = priv->num_tx_desc; 1928 u16 q = skb_get_queue_mapping(skb); 1929 struct ravb_tstamp_skb *ts_skb; 1930 struct ravb_tx_desc *desc; 1931 unsigned long flags; 1932 u32 dma_addr; 1933 void *buffer; 1934 u32 entry; 1935 u32 len; 1936 1937 spin_lock_irqsave(&priv->lock, flags); 1938 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1939 num_tx_desc) { 1940 netif_err(priv, tx_queued, ndev, 1941 "still transmitting with the full ring!\n"); 1942 netif_stop_subqueue(ndev, q); 1943 spin_unlock_irqrestore(&priv->lock, flags); 1944 return NETDEV_TX_BUSY; 1945 } 1946 1947 if (skb_put_padto(skb, ETH_ZLEN)) 1948 goto exit; 1949 1950 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1951 priv->tx_skb[q][entry / num_tx_desc] = skb; 1952 1953 if (num_tx_desc > 1) { 1954 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1955 entry / num_tx_desc * DPTR_ALIGN; 1956 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1957 1958 /* Zero length DMA descriptors are problematic as they seem 1959 * to terminate DMA transfers. Avoid them by simply using a 1960 * length of DPTR_ALIGN (4) when skb data is aligned to 1961 * DPTR_ALIGN. 1962 * 1963 * As skb is guaranteed to have at least ETH_ZLEN (60) 1964 * bytes of data by the call to skb_put_padto() above this 1965 * is safe with respect to both the length of the first DMA 1966 * descriptor (len) overflowing the available data and the 1967 * length of the second DMA descriptor (skb->len - len) 1968 * being negative. 1969 */ 1970 if (len == 0) 1971 len = DPTR_ALIGN; 1972 1973 memcpy(buffer, skb->data, len); 1974 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1975 DMA_TO_DEVICE); 1976 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1977 goto drop; 1978 1979 desc = &priv->tx_ring[q][entry]; 1980 desc->ds_tagl = cpu_to_le16(len); 1981 desc->dptr = cpu_to_le32(dma_addr); 1982 1983 buffer = skb->data + len; 1984 len = skb->len - len; 1985 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1986 DMA_TO_DEVICE); 1987 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1988 goto unmap; 1989 1990 desc++; 1991 } else { 1992 desc = &priv->tx_ring[q][entry]; 1993 len = skb->len; 1994 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1995 DMA_TO_DEVICE); 1996 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1997 goto drop; 1998 } 1999 desc->ds_tagl = cpu_to_le16(len); 2000 desc->dptr = cpu_to_le32(dma_addr); 2001 2002 /* TX timestamp required */ 2003 if (info->gptp || info->ccc_gac) { 2004 if (q == RAVB_NC) { 2005 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2006 if (!ts_skb) { 2007 if (num_tx_desc > 1) { 2008 desc--; 2009 dma_unmap_single(ndev->dev.parent, dma_addr, 2010 len, DMA_TO_DEVICE); 2011 } 2012 goto unmap; 2013 } 2014 ts_skb->skb = skb_get(skb); 2015 ts_skb->tag = priv->ts_skb_tag++; 2016 priv->ts_skb_tag &= 0x3ff; 2017 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2018 2019 /* TAG and timestamp required flag */ 2020 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2021 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2022 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2023 } 2024 2025 skb_tx_timestamp(skb); 2026 } 2027 /* Descriptor type must be set after all the above writes */ 2028 dma_wmb(); 2029 if (num_tx_desc > 1) { 2030 desc->die_dt = DT_FEND; 2031 desc--; 2032 desc->die_dt = DT_FSTART; 2033 } else { 2034 desc->die_dt = DT_FSINGLE; 2035 } 2036 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2037 2038 priv->cur_tx[q] += num_tx_desc; 2039 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2040 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2041 !ravb_tx_free(ndev, q, true)) 2042 netif_stop_subqueue(ndev, q); 2043 2044 exit: 2045 spin_unlock_irqrestore(&priv->lock, flags); 2046 return NETDEV_TX_OK; 2047 2048 unmap: 2049 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2050 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2051 drop: 2052 dev_kfree_skb_any(skb); 2053 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2054 goto exit; 2055 } 2056 2057 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2058 struct net_device *sb_dev) 2059 { 2060 /* If skb needs TX timestamp, it is handled in network control queue */ 2061 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2062 RAVB_BE; 2063 2064 } 2065 2066 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2067 { 2068 struct ravb_private *priv = netdev_priv(ndev); 2069 const struct ravb_hw_info *info = priv->info; 2070 struct net_device_stats *nstats, *stats0, *stats1; 2071 2072 nstats = &ndev->stats; 2073 stats0 = &priv->stats[RAVB_BE]; 2074 2075 if (info->tx_counters) { 2076 nstats->tx_dropped += ravb_read(ndev, TROCR); 2077 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2078 } 2079 2080 if (info->carrier_counters) { 2081 nstats->collisions += ravb_read(ndev, CXR41); 2082 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2083 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2084 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2085 } 2086 2087 nstats->rx_packets = stats0->rx_packets; 2088 nstats->tx_packets = stats0->tx_packets; 2089 nstats->rx_bytes = stats0->rx_bytes; 2090 nstats->tx_bytes = stats0->tx_bytes; 2091 nstats->multicast = stats0->multicast; 2092 nstats->rx_errors = stats0->rx_errors; 2093 nstats->rx_crc_errors = stats0->rx_crc_errors; 2094 nstats->rx_frame_errors = stats0->rx_frame_errors; 2095 nstats->rx_length_errors = stats0->rx_length_errors; 2096 nstats->rx_missed_errors = stats0->rx_missed_errors; 2097 nstats->rx_over_errors = stats0->rx_over_errors; 2098 if (info->nc_queues) { 2099 stats1 = &priv->stats[RAVB_NC]; 2100 2101 nstats->rx_packets += stats1->rx_packets; 2102 nstats->tx_packets += stats1->tx_packets; 2103 nstats->rx_bytes += stats1->rx_bytes; 2104 nstats->tx_bytes += stats1->tx_bytes; 2105 nstats->multicast += stats1->multicast; 2106 nstats->rx_errors += stats1->rx_errors; 2107 nstats->rx_crc_errors += stats1->rx_crc_errors; 2108 nstats->rx_frame_errors += stats1->rx_frame_errors; 2109 nstats->rx_length_errors += stats1->rx_length_errors; 2110 nstats->rx_missed_errors += stats1->rx_missed_errors; 2111 nstats->rx_over_errors += stats1->rx_over_errors; 2112 } 2113 2114 return nstats; 2115 } 2116 2117 /* Update promiscuous bit */ 2118 static void ravb_set_rx_mode(struct net_device *ndev) 2119 { 2120 struct ravb_private *priv = netdev_priv(ndev); 2121 unsigned long flags; 2122 2123 spin_lock_irqsave(&priv->lock, flags); 2124 ravb_modify(ndev, ECMR, ECMR_PRM, 2125 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2126 spin_unlock_irqrestore(&priv->lock, flags); 2127 } 2128 2129 /* Device close function for Ethernet AVB */ 2130 static int ravb_close(struct net_device *ndev) 2131 { 2132 struct device_node *np = ndev->dev.parent->of_node; 2133 struct ravb_private *priv = netdev_priv(ndev); 2134 const struct ravb_hw_info *info = priv->info; 2135 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2136 2137 netif_tx_stop_all_queues(ndev); 2138 2139 /* Disable interrupts by clearing the interrupt masks. */ 2140 ravb_write(ndev, 0, RIC0); 2141 ravb_write(ndev, 0, RIC2); 2142 ravb_write(ndev, 0, TIC); 2143 2144 /* Stop PTP Clock driver */ 2145 if (info->gptp) 2146 ravb_ptp_stop(ndev); 2147 2148 /* Set the config mode to stop the AVB-DMAC's processes */ 2149 if (ravb_stop_dma(ndev) < 0) 2150 netdev_err(ndev, 2151 "device will be stopped after h/w processes are done.\n"); 2152 2153 /* Clear the timestamp list */ 2154 if (info->gptp || info->ccc_gac) { 2155 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2156 list_del(&ts_skb->list); 2157 kfree_skb(ts_skb->skb); 2158 kfree(ts_skb); 2159 } 2160 } 2161 2162 /* PHY disconnect */ 2163 if (ndev->phydev) { 2164 phy_stop(ndev->phydev); 2165 phy_disconnect(ndev->phydev); 2166 if (of_phy_is_fixed_link(np)) 2167 of_phy_deregister_fixed_link(np); 2168 } 2169 2170 if (info->multi_irqs) { 2171 free_irq(priv->tx_irqs[RAVB_NC], ndev); 2172 free_irq(priv->rx_irqs[RAVB_NC], ndev); 2173 free_irq(priv->tx_irqs[RAVB_BE], ndev); 2174 free_irq(priv->rx_irqs[RAVB_BE], ndev); 2175 free_irq(priv->emac_irq, ndev); 2176 if (info->err_mgmt_irqs) { 2177 free_irq(priv->erra_irq, ndev); 2178 free_irq(priv->mgmta_irq, ndev); 2179 } 2180 } 2181 free_irq(ndev->irq, ndev); 2182 2183 if (info->nc_queues) 2184 napi_disable(&priv->napi[RAVB_NC]); 2185 napi_disable(&priv->napi[RAVB_BE]); 2186 2187 /* Free all the skb's in the RX queue and the DMA buffers. */ 2188 ravb_ring_free(ndev, RAVB_BE); 2189 if (info->nc_queues) 2190 ravb_ring_free(ndev, RAVB_NC); 2191 2192 return 0; 2193 } 2194 2195 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2196 { 2197 struct ravb_private *priv = netdev_priv(ndev); 2198 struct hwtstamp_config config; 2199 2200 config.flags = 0; 2201 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2202 HWTSTAMP_TX_OFF; 2203 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2204 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2205 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2206 break; 2207 case RAVB_RXTSTAMP_TYPE_ALL: 2208 config.rx_filter = HWTSTAMP_FILTER_ALL; 2209 break; 2210 default: 2211 config.rx_filter = HWTSTAMP_FILTER_NONE; 2212 } 2213 2214 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2215 -EFAULT : 0; 2216 } 2217 2218 /* Control hardware time stamping */ 2219 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2220 { 2221 struct ravb_private *priv = netdev_priv(ndev); 2222 struct hwtstamp_config config; 2223 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2224 u32 tstamp_tx_ctrl; 2225 2226 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2227 return -EFAULT; 2228 2229 switch (config.tx_type) { 2230 case HWTSTAMP_TX_OFF: 2231 tstamp_tx_ctrl = 0; 2232 break; 2233 case HWTSTAMP_TX_ON: 2234 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2235 break; 2236 default: 2237 return -ERANGE; 2238 } 2239 2240 switch (config.rx_filter) { 2241 case HWTSTAMP_FILTER_NONE: 2242 tstamp_rx_ctrl = 0; 2243 break; 2244 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2245 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2246 break; 2247 default: 2248 config.rx_filter = HWTSTAMP_FILTER_ALL; 2249 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2250 } 2251 2252 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2253 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2254 2255 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2256 -EFAULT : 0; 2257 } 2258 2259 /* ioctl to device function */ 2260 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2261 { 2262 struct phy_device *phydev = ndev->phydev; 2263 2264 if (!netif_running(ndev)) 2265 return -EINVAL; 2266 2267 if (!phydev) 2268 return -ENODEV; 2269 2270 switch (cmd) { 2271 case SIOCGHWTSTAMP: 2272 return ravb_hwtstamp_get(ndev, req); 2273 case SIOCSHWTSTAMP: 2274 return ravb_hwtstamp_set(ndev, req); 2275 } 2276 2277 return phy_mii_ioctl(phydev, req, cmd); 2278 } 2279 2280 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2281 { 2282 struct ravb_private *priv = netdev_priv(ndev); 2283 2284 ndev->mtu = new_mtu; 2285 2286 if (netif_running(ndev)) { 2287 synchronize_irq(priv->emac_irq); 2288 ravb_emac_init(ndev); 2289 } 2290 2291 netdev_update_features(ndev); 2292 2293 return 0; 2294 } 2295 2296 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2297 { 2298 struct ravb_private *priv = netdev_priv(ndev); 2299 unsigned long flags; 2300 2301 spin_lock_irqsave(&priv->lock, flags); 2302 2303 /* Disable TX and RX */ 2304 ravb_rcv_snd_disable(ndev); 2305 2306 /* Modify RX Checksum setting */ 2307 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2308 2309 /* Enable TX and RX */ 2310 ravb_rcv_snd_enable(ndev); 2311 2312 spin_unlock_irqrestore(&priv->lock, flags); 2313 } 2314 2315 static int ravb_set_features_gbeth(struct net_device *ndev, 2316 netdev_features_t features) 2317 { 2318 /* Place holder */ 2319 return 0; 2320 } 2321 2322 static int ravb_set_features_rcar(struct net_device *ndev, 2323 netdev_features_t features) 2324 { 2325 netdev_features_t changed = ndev->features ^ features; 2326 2327 if (changed & NETIF_F_RXCSUM) 2328 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2329 2330 ndev->features = features; 2331 2332 return 0; 2333 } 2334 2335 static int ravb_set_features(struct net_device *ndev, 2336 netdev_features_t features) 2337 { 2338 struct ravb_private *priv = netdev_priv(ndev); 2339 const struct ravb_hw_info *info = priv->info; 2340 2341 return info->set_feature(ndev, features); 2342 } 2343 2344 static const struct net_device_ops ravb_netdev_ops = { 2345 .ndo_open = ravb_open, 2346 .ndo_stop = ravb_close, 2347 .ndo_start_xmit = ravb_start_xmit, 2348 .ndo_select_queue = ravb_select_queue, 2349 .ndo_get_stats = ravb_get_stats, 2350 .ndo_set_rx_mode = ravb_set_rx_mode, 2351 .ndo_tx_timeout = ravb_tx_timeout, 2352 .ndo_eth_ioctl = ravb_do_ioctl, 2353 .ndo_change_mtu = ravb_change_mtu, 2354 .ndo_validate_addr = eth_validate_addr, 2355 .ndo_set_mac_address = eth_mac_addr, 2356 .ndo_set_features = ravb_set_features, 2357 }; 2358 2359 /* MDIO bus init function */ 2360 static int ravb_mdio_init(struct ravb_private *priv) 2361 { 2362 struct platform_device *pdev = priv->pdev; 2363 struct device *dev = &pdev->dev; 2364 struct phy_device *phydev; 2365 struct device_node *pn; 2366 int error; 2367 2368 /* Bitbang init */ 2369 priv->mdiobb.ops = &bb_ops; 2370 2371 /* MII controller setting */ 2372 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2373 if (!priv->mii_bus) 2374 return -ENOMEM; 2375 2376 /* Hook up MII support for ethtool */ 2377 priv->mii_bus->name = "ravb_mii"; 2378 priv->mii_bus->parent = dev; 2379 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2380 pdev->name, pdev->id); 2381 2382 /* Register MDIO bus */ 2383 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 2384 if (error) 2385 goto out_free_bus; 2386 2387 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2388 phydev = of_phy_find_device(pn); 2389 if (phydev) { 2390 phydev->mac_managed_pm = true; 2391 put_device(&phydev->mdio.dev); 2392 } 2393 of_node_put(pn); 2394 2395 return 0; 2396 2397 out_free_bus: 2398 free_mdio_bitbang(priv->mii_bus); 2399 return error; 2400 } 2401 2402 /* MDIO bus release function */ 2403 static int ravb_mdio_release(struct ravb_private *priv) 2404 { 2405 /* Unregister mdio bus */ 2406 mdiobus_unregister(priv->mii_bus); 2407 2408 /* Free bitbang info */ 2409 free_mdio_bitbang(priv->mii_bus); 2410 2411 return 0; 2412 } 2413 2414 static const struct ravb_hw_info ravb_gen3_hw_info = { 2415 .rx_ring_free = ravb_rx_ring_free_rcar, 2416 .rx_ring_format = ravb_rx_ring_format_rcar, 2417 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2418 .receive = ravb_rx_rcar, 2419 .set_rate = ravb_set_rate_rcar, 2420 .set_feature = ravb_set_features_rcar, 2421 .dmac_init = ravb_dmac_init_rcar, 2422 .emac_init = ravb_emac_init_rcar, 2423 .gstrings_stats = ravb_gstrings_stats, 2424 .gstrings_size = sizeof(ravb_gstrings_stats), 2425 .net_hw_features = NETIF_F_RXCSUM, 2426 .net_features = NETIF_F_RXCSUM, 2427 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2428 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2429 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2430 .rx_max_buf_size = SZ_2K, 2431 .internal_delay = 1, 2432 .tx_counters = 1, 2433 .multi_irqs = 1, 2434 .irq_en_dis = 1, 2435 .ccc_gac = 1, 2436 .nc_queues = 1, 2437 .magic_pkt = 1, 2438 }; 2439 2440 static const struct ravb_hw_info ravb_gen2_hw_info = { 2441 .rx_ring_free = ravb_rx_ring_free_rcar, 2442 .rx_ring_format = ravb_rx_ring_format_rcar, 2443 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2444 .receive = ravb_rx_rcar, 2445 .set_rate = ravb_set_rate_rcar, 2446 .set_feature = ravb_set_features_rcar, 2447 .dmac_init = ravb_dmac_init_rcar, 2448 .emac_init = ravb_emac_init_rcar, 2449 .gstrings_stats = ravb_gstrings_stats, 2450 .gstrings_size = sizeof(ravb_gstrings_stats), 2451 .net_hw_features = NETIF_F_RXCSUM, 2452 .net_features = NETIF_F_RXCSUM, 2453 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2454 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2455 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2456 .rx_max_buf_size = SZ_2K, 2457 .aligned_tx = 1, 2458 .gptp = 1, 2459 .nc_queues = 1, 2460 .magic_pkt = 1, 2461 }; 2462 2463 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2464 .rx_ring_free = ravb_rx_ring_free_rcar, 2465 .rx_ring_format = ravb_rx_ring_format_rcar, 2466 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2467 .receive = ravb_rx_rcar, 2468 .set_rate = ravb_set_rate_rcar, 2469 .set_feature = ravb_set_features_rcar, 2470 .dmac_init = ravb_dmac_init_rcar, 2471 .emac_init = ravb_emac_init_rcar, 2472 .gstrings_stats = ravb_gstrings_stats, 2473 .gstrings_size = sizeof(ravb_gstrings_stats), 2474 .net_hw_features = NETIF_F_RXCSUM, 2475 .net_features = NETIF_F_RXCSUM, 2476 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2477 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2478 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2479 .rx_max_buf_size = SZ_2K, 2480 .multi_irqs = 1, 2481 .err_mgmt_irqs = 1, 2482 .gptp = 1, 2483 .gptp_ref_clk = 1, 2484 .nc_queues = 1, 2485 .magic_pkt = 1, 2486 }; 2487 2488 static const struct ravb_hw_info gbeth_hw_info = { 2489 .rx_ring_free = ravb_rx_ring_free_gbeth, 2490 .rx_ring_format = ravb_rx_ring_format_gbeth, 2491 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth, 2492 .receive = ravb_rx_gbeth, 2493 .set_rate = ravb_set_rate_gbeth, 2494 .set_feature = ravb_set_features_gbeth, 2495 .dmac_init = ravb_dmac_init_gbeth, 2496 .emac_init = ravb_emac_init_gbeth, 2497 .gstrings_stats = ravb_gstrings_stats_gbeth, 2498 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2499 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2500 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), 2501 .tccr_mask = TCCR_TSRQ0, 2502 .rx_max_buf_size = SZ_8K, 2503 .aligned_tx = 1, 2504 .tx_counters = 1, 2505 .carrier_counters = 1, 2506 .half_duplex = 1, 2507 }; 2508 2509 static const struct of_device_id ravb_match_table[] = { 2510 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2511 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2512 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2513 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2514 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2515 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info }, 2516 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2517 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2518 { } 2519 }; 2520 MODULE_DEVICE_TABLE(of, ravb_match_table); 2521 2522 static int ravb_set_gti(struct net_device *ndev) 2523 { 2524 struct ravb_private *priv = netdev_priv(ndev); 2525 const struct ravb_hw_info *info = priv->info; 2526 struct device *dev = ndev->dev.parent; 2527 unsigned long rate; 2528 uint64_t inc; 2529 2530 if (info->gptp_ref_clk) 2531 rate = clk_get_rate(priv->gptp_clk); 2532 else 2533 rate = clk_get_rate(priv->clk); 2534 if (!rate) 2535 return -EINVAL; 2536 2537 inc = div64_ul(1000000000ULL << 20, rate); 2538 2539 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 2540 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 2541 inc, GTI_TIV_MIN, GTI_TIV_MAX); 2542 return -EINVAL; 2543 } 2544 2545 ravb_write(ndev, inc, GTI); 2546 2547 return 0; 2548 } 2549 2550 static void ravb_set_config_mode(struct net_device *ndev) 2551 { 2552 struct ravb_private *priv = netdev_priv(ndev); 2553 const struct ravb_hw_info *info = priv->info; 2554 2555 if (info->gptp) { 2556 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2557 /* Set CSEL value */ 2558 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 2559 } else if (info->ccc_gac) { 2560 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 2561 CCC_GAC | CCC_CSEL_HPB); 2562 } else { 2563 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2564 } 2565 } 2566 2567 /* Set tx and rx clock internal delay modes */ 2568 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 2569 { 2570 struct ravb_private *priv = netdev_priv(ndev); 2571 bool explicit_delay = false; 2572 u32 delay; 2573 2574 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2575 /* Valid values are 0 and 1800, according to DT bindings */ 2576 priv->rxcidm = !!delay; 2577 explicit_delay = true; 2578 } 2579 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2580 /* Valid values are 0 and 2000, according to DT bindings */ 2581 priv->txcidm = !!delay; 2582 explicit_delay = true; 2583 } 2584 2585 if (explicit_delay) 2586 return; 2587 2588 /* Fall back to legacy rgmii-*id behavior */ 2589 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2590 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2591 priv->rxcidm = 1; 2592 priv->rgmii_override = 1; 2593 } 2594 2595 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2596 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2597 priv->txcidm = 1; 2598 priv->rgmii_override = 1; 2599 } 2600 } 2601 2602 static void ravb_set_delay_mode(struct net_device *ndev) 2603 { 2604 struct ravb_private *priv = netdev_priv(ndev); 2605 u32 set = 0; 2606 2607 if (priv->rxcidm) 2608 set |= APSR_RDM; 2609 if (priv->txcidm) 2610 set |= APSR_TDM; 2611 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 2612 } 2613 2614 static int ravb_probe(struct platform_device *pdev) 2615 { 2616 struct device_node *np = pdev->dev.of_node; 2617 const struct ravb_hw_info *info; 2618 struct reset_control *rstc; 2619 struct ravb_private *priv; 2620 struct net_device *ndev; 2621 int error, irq, q; 2622 struct resource *res; 2623 int i; 2624 2625 if (!np) { 2626 dev_err(&pdev->dev, 2627 "this driver is required to be instantiated from device tree\n"); 2628 return -EINVAL; 2629 } 2630 2631 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 2632 if (IS_ERR(rstc)) 2633 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2634 "failed to get cpg reset\n"); 2635 2636 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2637 NUM_TX_QUEUE, NUM_RX_QUEUE); 2638 if (!ndev) 2639 return -ENOMEM; 2640 2641 info = of_device_get_match_data(&pdev->dev); 2642 2643 ndev->features = info->net_features; 2644 ndev->hw_features = info->net_hw_features; 2645 2646 reset_control_deassert(rstc); 2647 pm_runtime_enable(&pdev->dev); 2648 pm_runtime_get_sync(&pdev->dev); 2649 2650 if (info->multi_irqs) { 2651 if (info->err_mgmt_irqs) 2652 irq = platform_get_irq_byname(pdev, "dia"); 2653 else 2654 irq = platform_get_irq_byname(pdev, "ch22"); 2655 } else { 2656 irq = platform_get_irq(pdev, 0); 2657 } 2658 if (irq < 0) { 2659 error = irq; 2660 goto out_release; 2661 } 2662 ndev->irq = irq; 2663 2664 SET_NETDEV_DEV(ndev, &pdev->dev); 2665 2666 priv = netdev_priv(ndev); 2667 priv->info = info; 2668 priv->rstc = rstc; 2669 priv->ndev = ndev; 2670 priv->pdev = pdev; 2671 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2672 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2673 if (info->nc_queues) { 2674 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2675 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2676 } 2677 2678 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2679 if (IS_ERR(priv->addr)) { 2680 error = PTR_ERR(priv->addr); 2681 goto out_release; 2682 } 2683 2684 /* The Ether-specific entries in the device structure. */ 2685 ndev->base_addr = res->start; 2686 2687 spin_lock_init(&priv->lock); 2688 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2689 2690 error = of_get_phy_mode(np, &priv->phy_interface); 2691 if (error && error != -ENODEV) 2692 goto out_release; 2693 2694 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2695 priv->avb_link_active_low = 2696 of_property_read_bool(np, "renesas,ether-link-active-low"); 2697 2698 if (info->multi_irqs) { 2699 if (info->err_mgmt_irqs) 2700 irq = platform_get_irq_byname(pdev, "line3"); 2701 else 2702 irq = platform_get_irq_byname(pdev, "ch24"); 2703 if (irq < 0) { 2704 error = irq; 2705 goto out_release; 2706 } 2707 priv->emac_irq = irq; 2708 for (i = 0; i < NUM_RX_QUEUE; i++) { 2709 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2710 if (irq < 0) { 2711 error = irq; 2712 goto out_release; 2713 } 2714 priv->rx_irqs[i] = irq; 2715 } 2716 for (i = 0; i < NUM_TX_QUEUE; i++) { 2717 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2718 if (irq < 0) { 2719 error = irq; 2720 goto out_release; 2721 } 2722 priv->tx_irqs[i] = irq; 2723 } 2724 2725 if (info->err_mgmt_irqs) { 2726 irq = platform_get_irq_byname(pdev, "err_a"); 2727 if (irq < 0) { 2728 error = irq; 2729 goto out_release; 2730 } 2731 priv->erra_irq = irq; 2732 2733 irq = platform_get_irq_byname(pdev, "mgmt_a"); 2734 if (irq < 0) { 2735 error = irq; 2736 goto out_release; 2737 } 2738 priv->mgmta_irq = irq; 2739 } 2740 } 2741 2742 priv->clk = devm_clk_get(&pdev->dev, NULL); 2743 if (IS_ERR(priv->clk)) { 2744 error = PTR_ERR(priv->clk); 2745 goto out_release; 2746 } 2747 2748 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2749 if (IS_ERR(priv->refclk)) { 2750 error = PTR_ERR(priv->refclk); 2751 goto out_release; 2752 } 2753 clk_prepare_enable(priv->refclk); 2754 2755 if (info->gptp_ref_clk) { 2756 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2757 if (IS_ERR(priv->gptp_clk)) { 2758 error = PTR_ERR(priv->gptp_clk); 2759 goto out_disable_refclk; 2760 } 2761 clk_prepare_enable(priv->gptp_clk); 2762 } 2763 2764 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2765 ndev->min_mtu = ETH_MIN_MTU; 2766 2767 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2768 * Use two descriptor to handle such situation. First descriptor to 2769 * handle aligned data buffer and second descriptor to handle the 2770 * overflow data because of alignment. 2771 */ 2772 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2773 2774 /* Set function */ 2775 ndev->netdev_ops = &ravb_netdev_ops; 2776 ndev->ethtool_ops = &ravb_ethtool_ops; 2777 2778 /* Set AVB config mode */ 2779 ravb_set_config_mode(ndev); 2780 2781 if (info->gptp || info->ccc_gac) { 2782 /* Set GTI value */ 2783 error = ravb_set_gti(ndev); 2784 if (error) 2785 goto out_disable_gptp_clk; 2786 2787 /* Request GTI loading */ 2788 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2789 } 2790 2791 if (info->internal_delay) { 2792 ravb_parse_delay_mode(np, ndev); 2793 ravb_set_delay_mode(ndev); 2794 } 2795 2796 /* Allocate descriptor base address table */ 2797 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2798 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2799 &priv->desc_bat_dma, GFP_KERNEL); 2800 if (!priv->desc_bat) { 2801 dev_err(&pdev->dev, 2802 "Cannot allocate desc base address table (size %d bytes)\n", 2803 priv->desc_bat_size); 2804 error = -ENOMEM; 2805 goto out_disable_gptp_clk; 2806 } 2807 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2808 priv->desc_bat[q].die_dt = DT_EOS; 2809 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2810 2811 /* Initialise HW timestamp list */ 2812 INIT_LIST_HEAD(&priv->ts_skb_list); 2813 2814 /* Initialise PTP Clock driver */ 2815 if (info->ccc_gac) 2816 ravb_ptp_init(ndev, pdev); 2817 2818 /* Debug message level */ 2819 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2820 2821 /* Read and set MAC address */ 2822 ravb_read_mac_address(np, ndev); 2823 if (!is_valid_ether_addr(ndev->dev_addr)) { 2824 dev_warn(&pdev->dev, 2825 "no valid MAC address supplied, using a random one\n"); 2826 eth_hw_addr_random(ndev); 2827 } 2828 2829 /* MDIO bus init */ 2830 error = ravb_mdio_init(priv); 2831 if (error) { 2832 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2833 goto out_dma_free; 2834 } 2835 2836 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 2837 if (info->nc_queues) 2838 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 2839 2840 /* Network device register */ 2841 error = register_netdev(ndev); 2842 if (error) 2843 goto out_napi_del; 2844 2845 device_set_wakeup_capable(&pdev->dev, 1); 2846 2847 /* Print device information */ 2848 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2849 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2850 2851 platform_set_drvdata(pdev, ndev); 2852 2853 return 0; 2854 2855 out_napi_del: 2856 if (info->nc_queues) 2857 netif_napi_del(&priv->napi[RAVB_NC]); 2858 2859 netif_napi_del(&priv->napi[RAVB_BE]); 2860 ravb_mdio_release(priv); 2861 out_dma_free: 2862 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2863 priv->desc_bat_dma); 2864 2865 /* Stop PTP Clock driver */ 2866 if (info->ccc_gac) 2867 ravb_ptp_stop(ndev); 2868 out_disable_gptp_clk: 2869 clk_disable_unprepare(priv->gptp_clk); 2870 out_disable_refclk: 2871 clk_disable_unprepare(priv->refclk); 2872 out_release: 2873 free_netdev(ndev); 2874 2875 pm_runtime_put(&pdev->dev); 2876 pm_runtime_disable(&pdev->dev); 2877 reset_control_assert(rstc); 2878 return error; 2879 } 2880 2881 static int ravb_remove(struct platform_device *pdev) 2882 { 2883 struct net_device *ndev = platform_get_drvdata(pdev); 2884 struct ravb_private *priv = netdev_priv(ndev); 2885 const struct ravb_hw_info *info = priv->info; 2886 2887 /* Stop PTP Clock driver */ 2888 if (info->ccc_gac) 2889 ravb_ptp_stop(ndev); 2890 2891 clk_disable_unprepare(priv->gptp_clk); 2892 clk_disable_unprepare(priv->refclk); 2893 2894 /* Set reset mode */ 2895 ravb_write(ndev, CCC_OPC_RESET, CCC); 2896 unregister_netdev(ndev); 2897 if (info->nc_queues) 2898 netif_napi_del(&priv->napi[RAVB_NC]); 2899 netif_napi_del(&priv->napi[RAVB_BE]); 2900 ravb_mdio_release(priv); 2901 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2902 priv->desc_bat_dma); 2903 pm_runtime_put_sync(&pdev->dev); 2904 pm_runtime_disable(&pdev->dev); 2905 reset_control_assert(priv->rstc); 2906 free_netdev(ndev); 2907 platform_set_drvdata(pdev, NULL); 2908 2909 return 0; 2910 } 2911 2912 static int ravb_wol_setup(struct net_device *ndev) 2913 { 2914 struct ravb_private *priv = netdev_priv(ndev); 2915 const struct ravb_hw_info *info = priv->info; 2916 2917 /* Disable interrupts by clearing the interrupt masks. */ 2918 ravb_write(ndev, 0, RIC0); 2919 ravb_write(ndev, 0, RIC2); 2920 ravb_write(ndev, 0, TIC); 2921 2922 /* Only allow ECI interrupts */ 2923 synchronize_irq(priv->emac_irq); 2924 if (info->nc_queues) 2925 napi_disable(&priv->napi[RAVB_NC]); 2926 napi_disable(&priv->napi[RAVB_BE]); 2927 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2928 2929 /* Enable MagicPacket */ 2930 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2931 2932 return enable_irq_wake(priv->emac_irq); 2933 } 2934 2935 static int ravb_wol_restore(struct net_device *ndev) 2936 { 2937 struct ravb_private *priv = netdev_priv(ndev); 2938 const struct ravb_hw_info *info = priv->info; 2939 2940 if (info->nc_queues) 2941 napi_enable(&priv->napi[RAVB_NC]); 2942 napi_enable(&priv->napi[RAVB_BE]); 2943 2944 /* Disable MagicPacket */ 2945 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2946 2947 ravb_close(ndev); 2948 2949 return disable_irq_wake(priv->emac_irq); 2950 } 2951 2952 static int __maybe_unused ravb_suspend(struct device *dev) 2953 { 2954 struct net_device *ndev = dev_get_drvdata(dev); 2955 struct ravb_private *priv = netdev_priv(ndev); 2956 int ret; 2957 2958 if (!netif_running(ndev)) 2959 return 0; 2960 2961 netif_device_detach(ndev); 2962 2963 if (priv->wol_enabled) 2964 ret = ravb_wol_setup(ndev); 2965 else 2966 ret = ravb_close(ndev); 2967 2968 if (priv->info->ccc_gac) 2969 ravb_ptp_stop(ndev); 2970 2971 return ret; 2972 } 2973 2974 static int __maybe_unused ravb_resume(struct device *dev) 2975 { 2976 struct net_device *ndev = dev_get_drvdata(dev); 2977 struct ravb_private *priv = netdev_priv(ndev); 2978 const struct ravb_hw_info *info = priv->info; 2979 int ret = 0; 2980 2981 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2982 if (priv->wol_enabled) 2983 ravb_write(ndev, CCC_OPC_RESET, CCC); 2984 2985 /* All register have been reset to default values. 2986 * Restore all registers which where setup at probe time and 2987 * reopen device if it was running before system suspended. 2988 */ 2989 2990 /* Set AVB config mode */ 2991 ravb_set_config_mode(ndev); 2992 2993 if (info->gptp || info->ccc_gac) { 2994 /* Set GTI value */ 2995 ret = ravb_set_gti(ndev); 2996 if (ret) 2997 return ret; 2998 2999 /* Request GTI loading */ 3000 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 3001 } 3002 3003 if (info->internal_delay) 3004 ravb_set_delay_mode(ndev); 3005 3006 /* Restore descriptor base address table */ 3007 ravb_write(ndev, priv->desc_bat_dma, DBAT); 3008 3009 if (priv->info->ccc_gac) 3010 ravb_ptp_init(ndev, priv->pdev); 3011 3012 if (netif_running(ndev)) { 3013 if (priv->wol_enabled) { 3014 ret = ravb_wol_restore(ndev); 3015 if (ret) 3016 return ret; 3017 } 3018 ret = ravb_open(ndev); 3019 if (ret < 0) 3020 return ret; 3021 ravb_set_rx_mode(ndev); 3022 netif_device_attach(ndev); 3023 } 3024 3025 return ret; 3026 } 3027 3028 static int __maybe_unused ravb_runtime_nop(struct device *dev) 3029 { 3030 /* Runtime PM callback shared between ->runtime_suspend() 3031 * and ->runtime_resume(). Simply returns success. 3032 * 3033 * This driver re-initializes all registers after 3034 * pm_runtime_get_sync() anyway so there is no need 3035 * to save and restore registers here. 3036 */ 3037 return 0; 3038 } 3039 3040 static const struct dev_pm_ops ravb_dev_pm_ops = { 3041 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3042 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 3043 }; 3044 3045 static struct platform_driver ravb_driver = { 3046 .probe = ravb_probe, 3047 .remove = ravb_remove, 3048 .driver = { 3049 .name = "ravb", 3050 .pm = &ravb_dev_pm_ops, 3051 .of_match_table = ravb_match_table, 3052 }, 3053 }; 3054 3055 module_platform_driver(ravb_driver); 3056 3057 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3058 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3059 MODULE_LICENSE("GPL v2"); 3060