1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 #include <linux/reset.h> 33 34 #include <asm/div64.h> 35 36 #include "ravb.h" 37 38 #define RAVB_DEF_MSG_ENABLE \ 39 (NETIF_MSG_LINK | \ 40 NETIF_MSG_TIMER | \ 41 NETIF_MSG_RX_ERR | \ 42 NETIF_MSG_TX_ERR) 43 44 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 45 "ch0", /* RAVB_BE */ 46 "ch1", /* RAVB_NC */ 47 }; 48 49 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 50 "ch18", /* RAVB_BE */ 51 "ch19", /* RAVB_NC */ 52 }; 53 54 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 55 u32 set) 56 { 57 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 58 } 59 60 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 61 { 62 int i; 63 64 for (i = 0; i < 10000; i++) { 65 if ((ravb_read(ndev, reg) & mask) == value) 66 return 0; 67 udelay(10); 68 } 69 return -ETIMEDOUT; 70 } 71 72 static int ravb_config(struct net_device *ndev) 73 { 74 int error; 75 76 /* Set config mode */ 77 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 78 /* Check if the operating mode is changed to the config mode */ 79 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 80 if (error) 81 netdev_err(ndev, "failed to switch device to config mode\n"); 82 83 return error; 84 } 85 86 static void ravb_set_rate_gbeth(struct net_device *ndev) 87 { 88 struct ravb_private *priv = netdev_priv(ndev); 89 90 switch (priv->speed) { 91 case 10: /* 10BASE */ 92 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 93 break; 94 case 100: /* 100BASE */ 95 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 96 break; 97 case 1000: /* 1000BASE */ 98 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 99 break; 100 } 101 } 102 103 static void ravb_set_rate_rcar(struct net_device *ndev) 104 { 105 struct ravb_private *priv = netdev_priv(ndev); 106 107 switch (priv->speed) { 108 case 100: /* 100BASE */ 109 ravb_write(ndev, GECMR_SPEED_100, GECMR); 110 break; 111 case 1000: /* 1000BASE */ 112 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 113 break; 114 } 115 } 116 117 static void ravb_set_buffer_align(struct sk_buff *skb) 118 { 119 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 120 121 if (reserve) 122 skb_reserve(skb, RAVB_ALIGN - reserve); 123 } 124 125 /* Get MAC address from the MAC address registers 126 * 127 * Ethernet AVB device doesn't have ROM for MAC address. 128 * This function gets the MAC address that was used by a bootloader. 129 */ 130 static void ravb_read_mac_address(struct device_node *np, 131 struct net_device *ndev) 132 { 133 int ret; 134 135 ret = of_get_mac_address(np, ndev->dev_addr); 136 if (ret) { 137 u32 mahr = ravb_read(ndev, MAHR); 138 u32 malr = ravb_read(ndev, MALR); 139 140 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 141 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 142 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 143 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 144 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 145 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 146 } 147 } 148 149 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 150 { 151 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 152 mdiobb); 153 154 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 155 } 156 157 /* MDC pin control */ 158 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 159 { 160 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 161 } 162 163 /* Data I/O pin control */ 164 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 165 { 166 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 167 } 168 169 /* Set data bit */ 170 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 171 { 172 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 173 } 174 175 /* Get data bit */ 176 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 177 { 178 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 179 mdiobb); 180 181 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 182 } 183 184 /* MDIO bus control struct */ 185 static const struct mdiobb_ops bb_ops = { 186 .owner = THIS_MODULE, 187 .set_mdc = ravb_set_mdc, 188 .set_mdio_dir = ravb_set_mdio_dir, 189 .set_mdio_data = ravb_set_mdio_data, 190 .get_mdio_data = ravb_get_mdio_data, 191 }; 192 193 /* Free TX skb function for AVB-IP */ 194 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 195 { 196 struct ravb_private *priv = netdev_priv(ndev); 197 struct net_device_stats *stats = &priv->stats[q]; 198 unsigned int num_tx_desc = priv->num_tx_desc; 199 struct ravb_tx_desc *desc; 200 unsigned int entry; 201 int free_num = 0; 202 u32 size; 203 204 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 205 bool txed; 206 207 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 208 num_tx_desc); 209 desc = &priv->tx_ring[q][entry]; 210 txed = desc->die_dt == DT_FEMPTY; 211 if (free_txed_only && !txed) 212 break; 213 /* Descriptor type must be checked before all other reads */ 214 dma_rmb(); 215 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 216 /* Free the original skb. */ 217 if (priv->tx_skb[q][entry / num_tx_desc]) { 218 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 219 size, DMA_TO_DEVICE); 220 /* Last packet descriptor? */ 221 if (entry % num_tx_desc == num_tx_desc - 1) { 222 entry /= num_tx_desc; 223 dev_kfree_skb_any(priv->tx_skb[q][entry]); 224 priv->tx_skb[q][entry] = NULL; 225 if (txed) 226 stats->tx_packets++; 227 } 228 free_num++; 229 } 230 if (txed) 231 stats->tx_bytes += size; 232 desc->die_dt = DT_EEMPTY; 233 } 234 return free_num; 235 } 236 237 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q) 238 { 239 /* Place holder */ 240 } 241 242 static void ravb_rx_ring_free(struct net_device *ndev, int q) 243 { 244 struct ravb_private *priv = netdev_priv(ndev); 245 unsigned int ring_size; 246 unsigned int i; 247 248 if (!priv->rx_ring[q]) 249 return; 250 251 for (i = 0; i < priv->num_rx_ring[q]; i++) { 252 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 253 254 if (!dma_mapping_error(ndev->dev.parent, 255 le32_to_cpu(desc->dptr))) 256 dma_unmap_single(ndev->dev.parent, 257 le32_to_cpu(desc->dptr), 258 RX_BUF_SZ, 259 DMA_FROM_DEVICE); 260 } 261 ring_size = sizeof(struct ravb_ex_rx_desc) * 262 (priv->num_rx_ring[q] + 1); 263 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 264 priv->rx_desc_dma[q]); 265 priv->rx_ring[q] = NULL; 266 } 267 268 /* Free skb's and DMA buffers for Ethernet AVB */ 269 static void ravb_ring_free(struct net_device *ndev, int q) 270 { 271 struct ravb_private *priv = netdev_priv(ndev); 272 const struct ravb_hw_info *info = priv->info; 273 unsigned int num_tx_desc = priv->num_tx_desc; 274 unsigned int ring_size; 275 unsigned int i; 276 277 info->rx_ring_free(ndev, q); 278 279 if (priv->tx_ring[q]) { 280 ravb_tx_free(ndev, q, false); 281 282 ring_size = sizeof(struct ravb_tx_desc) * 283 (priv->num_tx_ring[q] * num_tx_desc + 1); 284 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 285 priv->tx_desc_dma[q]); 286 priv->tx_ring[q] = NULL; 287 } 288 289 /* Free RX skb ringbuffer */ 290 if (priv->rx_skb[q]) { 291 for (i = 0; i < priv->num_rx_ring[q]; i++) 292 dev_kfree_skb(priv->rx_skb[q][i]); 293 } 294 kfree(priv->rx_skb[q]); 295 priv->rx_skb[q] = NULL; 296 297 /* Free aligned TX buffers */ 298 kfree(priv->tx_align[q]); 299 priv->tx_align[q] = NULL; 300 301 /* Free TX skb ringbuffer. 302 * SKBs are freed by ravb_tx_free() call above. 303 */ 304 kfree(priv->tx_skb[q]); 305 priv->tx_skb[q] = NULL; 306 } 307 308 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q) 309 { 310 /* Place holder */ 311 } 312 313 static void ravb_rx_ring_format(struct net_device *ndev, int q) 314 { 315 struct ravb_private *priv = netdev_priv(ndev); 316 struct ravb_ex_rx_desc *rx_desc; 317 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 318 dma_addr_t dma_addr; 319 unsigned int i; 320 321 memset(priv->rx_ring[q], 0, rx_ring_size); 322 /* Build RX ring buffer */ 323 for (i = 0; i < priv->num_rx_ring[q]; i++) { 324 /* RX descriptor */ 325 rx_desc = &priv->rx_ring[q][i]; 326 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 327 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 328 RX_BUF_SZ, 329 DMA_FROM_DEVICE); 330 /* We just set the data size to 0 for a failed mapping which 331 * should prevent DMA from happening... 332 */ 333 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 334 rx_desc->ds_cc = cpu_to_le16(0); 335 rx_desc->dptr = cpu_to_le32(dma_addr); 336 rx_desc->die_dt = DT_FEMPTY; 337 } 338 rx_desc = &priv->rx_ring[q][i]; 339 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 340 rx_desc->die_dt = DT_LINKFIX; /* type */ 341 } 342 343 /* Format skb and descriptor buffer for Ethernet AVB */ 344 static void ravb_ring_format(struct net_device *ndev, int q) 345 { 346 struct ravb_private *priv = netdev_priv(ndev); 347 const struct ravb_hw_info *info = priv->info; 348 unsigned int num_tx_desc = priv->num_tx_desc; 349 struct ravb_tx_desc *tx_desc; 350 struct ravb_desc *desc; 351 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 352 num_tx_desc; 353 unsigned int i; 354 355 priv->cur_rx[q] = 0; 356 priv->cur_tx[q] = 0; 357 priv->dirty_rx[q] = 0; 358 priv->dirty_tx[q] = 0; 359 360 info->rx_ring_format(ndev, q); 361 362 memset(priv->tx_ring[q], 0, tx_ring_size); 363 /* Build TX ring buffer */ 364 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 365 i++, tx_desc++) { 366 tx_desc->die_dt = DT_EEMPTY; 367 if (num_tx_desc > 1) { 368 tx_desc++; 369 tx_desc->die_dt = DT_EEMPTY; 370 } 371 } 372 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 373 tx_desc->die_dt = DT_LINKFIX; /* type */ 374 375 /* RX descriptor base address for best effort */ 376 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 377 desc->die_dt = DT_LINKFIX; /* type */ 378 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 379 380 /* TX descriptor base address for best effort */ 381 desc = &priv->desc_bat[q]; 382 desc->die_dt = DT_LINKFIX; /* type */ 383 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 384 } 385 386 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q) 387 { 388 /* Place holder */ 389 return NULL; 390 } 391 392 static void *ravb_alloc_rx_desc(struct net_device *ndev, int q) 393 { 394 struct ravb_private *priv = netdev_priv(ndev); 395 unsigned int ring_size; 396 397 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 398 399 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 400 &priv->rx_desc_dma[q], 401 GFP_KERNEL); 402 return priv->rx_ring[q]; 403 } 404 405 /* Init skb and descriptor buffer for Ethernet AVB */ 406 static int ravb_ring_init(struct net_device *ndev, int q) 407 { 408 struct ravb_private *priv = netdev_priv(ndev); 409 const struct ravb_hw_info *info = priv->info; 410 unsigned int num_tx_desc = priv->num_tx_desc; 411 unsigned int ring_size; 412 struct sk_buff *skb; 413 unsigned int i; 414 415 /* Allocate RX and TX skb rings */ 416 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 417 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 418 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 419 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 420 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 421 goto error; 422 423 for (i = 0; i < priv->num_rx_ring[q]; i++) { 424 skb = netdev_alloc_skb(ndev, info->max_rx_len); 425 if (!skb) 426 goto error; 427 ravb_set_buffer_align(skb); 428 priv->rx_skb[q][i] = skb; 429 } 430 431 if (num_tx_desc > 1) { 432 /* Allocate rings for the aligned buffers */ 433 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 434 DPTR_ALIGN - 1, GFP_KERNEL); 435 if (!priv->tx_align[q]) 436 goto error; 437 } 438 439 /* Allocate all RX descriptors. */ 440 if (!info->alloc_rx_desc(ndev, q)) 441 goto error; 442 443 priv->dirty_rx[q] = 0; 444 445 /* Allocate all TX descriptors. */ 446 ring_size = sizeof(struct ravb_tx_desc) * 447 (priv->num_tx_ring[q] * num_tx_desc + 1); 448 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 449 &priv->tx_desc_dma[q], 450 GFP_KERNEL); 451 if (!priv->tx_ring[q]) 452 goto error; 453 454 return 0; 455 456 error: 457 ravb_ring_free(ndev, q); 458 459 return -ENOMEM; 460 } 461 462 static void ravb_emac_init_gbeth(struct net_device *ndev) 463 { 464 struct ravb_private *priv = netdev_priv(ndev); 465 466 /* Receive frame limit set register */ 467 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); 468 469 /* PAUSE prohibition */ 470 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 471 ECMR_TE | ECMR_RE | ECMR_RCPT | 472 ECMR_TXF | ECMR_RXF | ECMR_PRM, ECMR); 473 474 ravb_set_rate_gbeth(ndev); 475 476 /* Set MAC address */ 477 ravb_write(ndev, 478 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 479 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 480 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 481 482 /* E-MAC status register clear */ 483 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 484 485 /* E-MAC interrupt enable register */ 486 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 487 488 ravb_modify(ndev, CXR31, CXR31_SEL_LINK1, 0); 489 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0, CXR31_SEL_LINK0); 490 } 491 492 static void ravb_emac_init_rcar(struct net_device *ndev) 493 { 494 /* Receive frame limit set register */ 495 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 496 497 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 498 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 499 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 500 ECMR_TE | ECMR_RE, ECMR); 501 502 ravb_set_rate_rcar(ndev); 503 504 /* Set MAC address */ 505 ravb_write(ndev, 506 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 507 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 508 ravb_write(ndev, 509 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 510 511 /* E-MAC status register clear */ 512 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 513 514 /* E-MAC interrupt enable register */ 515 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 516 } 517 518 /* E-MAC init function */ 519 static void ravb_emac_init(struct net_device *ndev) 520 { 521 struct ravb_private *priv = netdev_priv(ndev); 522 const struct ravb_hw_info *info = priv->info; 523 524 info->emac_init(ndev); 525 } 526 527 static int ravb_dmac_init_gbeth(struct net_device *ndev) 528 { 529 int error; 530 531 error = ravb_ring_init(ndev, RAVB_BE); 532 if (error) 533 return error; 534 535 /* Descriptor format */ 536 ravb_ring_format(ndev, RAVB_BE); 537 538 /* Set AVB RX */ 539 ravb_write(ndev, 0x60000000, RCR); 540 541 /* Set Max Frame Length (RTC) */ 542 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC); 543 544 /* Set FIFO size */ 545 ravb_write(ndev, 0x00222200, TGC); 546 547 ravb_write(ndev, 0, TCCR); 548 549 /* Frame receive */ 550 ravb_write(ndev, RIC0_FRE0, RIC0); 551 /* Disable FIFO full warning */ 552 ravb_write(ndev, 0x0, RIC1); 553 /* Receive FIFO full error, descriptor empty */ 554 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 555 556 ravb_write(ndev, TIC_FTE0, TIC); 557 558 return 0; 559 } 560 561 static int ravb_dmac_init_rcar(struct net_device *ndev) 562 { 563 struct ravb_private *priv = netdev_priv(ndev); 564 const struct ravb_hw_info *info = priv->info; 565 int error; 566 567 error = ravb_ring_init(ndev, RAVB_BE); 568 if (error) 569 return error; 570 error = ravb_ring_init(ndev, RAVB_NC); 571 if (error) { 572 ravb_ring_free(ndev, RAVB_BE); 573 return error; 574 } 575 576 /* Descriptor format */ 577 ravb_ring_format(ndev, RAVB_BE); 578 ravb_ring_format(ndev, RAVB_NC); 579 580 /* Set AVB RX */ 581 ravb_write(ndev, 582 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 583 584 /* Set FIFO size */ 585 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 586 587 /* Timestamp enable */ 588 ravb_write(ndev, TCCR_TFEN, TCCR); 589 590 /* Interrupt init: */ 591 if (info->multi_irqs) { 592 /* Clear DIL.DPLx */ 593 ravb_write(ndev, 0, DIL); 594 /* Set queue specific interrupt */ 595 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 596 } 597 /* Frame receive */ 598 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 599 /* Disable FIFO full warning */ 600 ravb_write(ndev, 0, RIC1); 601 /* Receive FIFO full error, descriptor empty */ 602 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 603 /* Frame transmitted, timestamp FIFO updated */ 604 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 605 606 return 0; 607 } 608 609 /* Device init function for Ethernet AVB */ 610 static int ravb_dmac_init(struct net_device *ndev) 611 { 612 struct ravb_private *priv = netdev_priv(ndev); 613 const struct ravb_hw_info *info = priv->info; 614 int error; 615 616 /* Set CONFIG mode */ 617 error = ravb_config(ndev); 618 if (error) 619 return error; 620 621 error = info->dmac_init(ndev); 622 if (error) 623 return error; 624 625 /* Setting the control will start the AVB-DMAC process. */ 626 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 627 628 return 0; 629 } 630 631 static void ravb_get_tx_tstamp(struct net_device *ndev) 632 { 633 struct ravb_private *priv = netdev_priv(ndev); 634 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 635 struct skb_shared_hwtstamps shhwtstamps; 636 struct sk_buff *skb; 637 struct timespec64 ts; 638 u16 tag, tfa_tag; 639 int count; 640 u32 tfa2; 641 642 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 643 while (count--) { 644 tfa2 = ravb_read(ndev, TFA2); 645 tfa_tag = (tfa2 & TFA2_TST) >> 16; 646 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 647 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 648 ravb_read(ndev, TFA1); 649 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 650 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 651 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 652 list) { 653 skb = ts_skb->skb; 654 tag = ts_skb->tag; 655 list_del(&ts_skb->list); 656 kfree(ts_skb); 657 if (tag == tfa_tag) { 658 skb_tstamp_tx(skb, &shhwtstamps); 659 dev_consume_skb_any(skb); 660 break; 661 } else { 662 dev_kfree_skb_any(skb); 663 } 664 } 665 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 666 } 667 } 668 669 static void ravb_rx_csum(struct sk_buff *skb) 670 { 671 u8 *hw_csum; 672 673 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 674 * appended to packet data 675 */ 676 if (unlikely(skb->len < sizeof(__sum16))) 677 return; 678 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 679 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 680 skb->ip_summed = CHECKSUM_COMPLETE; 681 skb_trim(skb, skb->len - sizeof(__sum16)); 682 } 683 684 /* Packet receive function for Gigabit Ethernet */ 685 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) 686 { 687 /* Place holder */ 688 return true; 689 } 690 691 /* Packet receive function for Ethernet AVB */ 692 static bool ravb_rcar_rx(struct net_device *ndev, int *quota, int q) 693 { 694 struct ravb_private *priv = netdev_priv(ndev); 695 const struct ravb_hw_info *info = priv->info; 696 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 697 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 698 priv->cur_rx[q]; 699 struct net_device_stats *stats = &priv->stats[q]; 700 struct ravb_ex_rx_desc *desc; 701 struct sk_buff *skb; 702 dma_addr_t dma_addr; 703 struct timespec64 ts; 704 u8 desc_status; 705 u16 pkt_len; 706 int limit; 707 708 boguscnt = min(boguscnt, *quota); 709 limit = boguscnt; 710 desc = &priv->rx_ring[q][entry]; 711 while (desc->die_dt != DT_FEMPTY) { 712 /* Descriptor type must be checked before all other reads */ 713 dma_rmb(); 714 desc_status = desc->msc; 715 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 716 717 if (--boguscnt < 0) 718 break; 719 720 /* We use 0-byte descriptors to mark the DMA mapping errors */ 721 if (!pkt_len) 722 continue; 723 724 if (desc_status & MSC_MC) 725 stats->multicast++; 726 727 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 728 MSC_CEEF)) { 729 stats->rx_errors++; 730 if (desc_status & MSC_CRC) 731 stats->rx_crc_errors++; 732 if (desc_status & MSC_RFE) 733 stats->rx_frame_errors++; 734 if (desc_status & (MSC_RTLF | MSC_RTSF)) 735 stats->rx_length_errors++; 736 if (desc_status & MSC_CEEF) 737 stats->rx_missed_errors++; 738 } else { 739 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 740 741 skb = priv->rx_skb[q][entry]; 742 priv->rx_skb[q][entry] = NULL; 743 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 744 RX_BUF_SZ, 745 DMA_FROM_DEVICE); 746 get_ts &= (q == RAVB_NC) ? 747 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 748 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 749 if (get_ts) { 750 struct skb_shared_hwtstamps *shhwtstamps; 751 752 shhwtstamps = skb_hwtstamps(skb); 753 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 754 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 755 32) | le32_to_cpu(desc->ts_sl); 756 ts.tv_nsec = le32_to_cpu(desc->ts_n); 757 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 758 } 759 760 skb_put(skb, pkt_len); 761 skb->protocol = eth_type_trans(skb, ndev); 762 if (ndev->features & NETIF_F_RXCSUM) 763 ravb_rx_csum(skb); 764 napi_gro_receive(&priv->napi[q], skb); 765 stats->rx_packets++; 766 stats->rx_bytes += pkt_len; 767 } 768 769 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 770 desc = &priv->rx_ring[q][entry]; 771 } 772 773 /* Refill the RX ring buffers. */ 774 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 775 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 776 desc = &priv->rx_ring[q][entry]; 777 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 778 779 if (!priv->rx_skb[q][entry]) { 780 skb = netdev_alloc_skb(ndev, info->max_rx_len); 781 if (!skb) 782 break; /* Better luck next round. */ 783 ravb_set_buffer_align(skb); 784 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 785 le16_to_cpu(desc->ds_cc), 786 DMA_FROM_DEVICE); 787 skb_checksum_none_assert(skb); 788 /* We just set the data size to 0 for a failed mapping 789 * which should prevent DMA from happening... 790 */ 791 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 792 desc->ds_cc = cpu_to_le16(0); 793 desc->dptr = cpu_to_le32(dma_addr); 794 priv->rx_skb[q][entry] = skb; 795 } 796 /* Descriptor type must be set after all the above writes */ 797 dma_wmb(); 798 desc->die_dt = DT_FEMPTY; 799 } 800 801 *quota -= limit - (++boguscnt); 802 803 return boguscnt <= 0; 804 } 805 806 /* Packet receive function for Ethernet AVB */ 807 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 808 { 809 struct ravb_private *priv = netdev_priv(ndev); 810 const struct ravb_hw_info *info = priv->info; 811 812 return info->receive(ndev, quota, q); 813 } 814 815 static void ravb_rcv_snd_disable(struct net_device *ndev) 816 { 817 /* Disable TX and RX */ 818 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 819 } 820 821 static void ravb_rcv_snd_enable(struct net_device *ndev) 822 { 823 /* Enable TX and RX */ 824 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 825 } 826 827 /* function for waiting dma process finished */ 828 static int ravb_stop_dma(struct net_device *ndev) 829 { 830 struct ravb_private *priv = netdev_priv(ndev); 831 const struct ravb_hw_info *info = priv->info; 832 int error; 833 834 /* Wait for stopping the hardware TX process */ 835 error = ravb_wait(ndev, TCCR, info->tsrq, 0); 836 837 if (error) 838 return error; 839 840 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 841 0); 842 if (error) 843 return error; 844 845 /* Stop the E-MAC's RX/TX processes. */ 846 ravb_rcv_snd_disable(ndev); 847 848 /* Wait for stopping the RX DMA process */ 849 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 850 if (error) 851 return error; 852 853 /* Stop AVB-DMAC process */ 854 return ravb_config(ndev); 855 } 856 857 /* E-MAC interrupt handler */ 858 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 859 { 860 struct ravb_private *priv = netdev_priv(ndev); 861 u32 ecsr, psr; 862 863 ecsr = ravb_read(ndev, ECSR); 864 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 865 866 if (ecsr & ECSR_MPD) 867 pm_wakeup_event(&priv->pdev->dev, 0); 868 if (ecsr & ECSR_ICD) 869 ndev->stats.tx_carrier_errors++; 870 if (ecsr & ECSR_LCHNG) { 871 /* Link changed */ 872 if (priv->no_avb_link) 873 return; 874 psr = ravb_read(ndev, PSR); 875 if (priv->avb_link_active_low) 876 psr ^= PSR_LMON; 877 if (!(psr & PSR_LMON)) { 878 /* DIsable RX and TX */ 879 ravb_rcv_snd_disable(ndev); 880 } else { 881 /* Enable RX and TX */ 882 ravb_rcv_snd_enable(ndev); 883 } 884 } 885 } 886 887 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 888 { 889 struct net_device *ndev = dev_id; 890 struct ravb_private *priv = netdev_priv(ndev); 891 892 spin_lock(&priv->lock); 893 ravb_emac_interrupt_unlocked(ndev); 894 spin_unlock(&priv->lock); 895 return IRQ_HANDLED; 896 } 897 898 /* Error interrupt handler */ 899 static void ravb_error_interrupt(struct net_device *ndev) 900 { 901 struct ravb_private *priv = netdev_priv(ndev); 902 u32 eis, ris2; 903 904 eis = ravb_read(ndev, EIS); 905 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 906 if (eis & EIS_QFS) { 907 ris2 = ravb_read(ndev, RIS2); 908 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED), 909 RIS2); 910 911 /* Receive Descriptor Empty int */ 912 if (ris2 & RIS2_QFF0) 913 priv->stats[RAVB_BE].rx_over_errors++; 914 915 /* Receive Descriptor Empty int */ 916 if (ris2 & RIS2_QFF1) 917 priv->stats[RAVB_NC].rx_over_errors++; 918 919 /* Receive FIFO Overflow int */ 920 if (ris2 & RIS2_RFFF) 921 priv->rx_fifo_errors++; 922 } 923 } 924 925 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 926 { 927 struct ravb_private *priv = netdev_priv(ndev); 928 const struct ravb_hw_info *info = priv->info; 929 u32 ris0 = ravb_read(ndev, RIS0); 930 u32 ric0 = ravb_read(ndev, RIC0); 931 u32 tis = ravb_read(ndev, TIS); 932 u32 tic = ravb_read(ndev, TIC); 933 934 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 935 if (napi_schedule_prep(&priv->napi[q])) { 936 /* Mask RX and TX interrupts */ 937 if (!info->multi_irqs) { 938 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 939 ravb_write(ndev, tic & ~BIT(q), TIC); 940 } else { 941 ravb_write(ndev, BIT(q), RID0); 942 ravb_write(ndev, BIT(q), TID); 943 } 944 __napi_schedule(&priv->napi[q]); 945 } else { 946 netdev_warn(ndev, 947 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 948 ris0, ric0); 949 netdev_warn(ndev, 950 " tx status 0x%08x, tx mask 0x%08x.\n", 951 tis, tic); 952 } 953 return true; 954 } 955 return false; 956 } 957 958 static bool ravb_timestamp_interrupt(struct net_device *ndev) 959 { 960 u32 tis = ravb_read(ndev, TIS); 961 962 if (tis & TIS_TFUF) { 963 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 964 ravb_get_tx_tstamp(ndev); 965 return true; 966 } 967 return false; 968 } 969 970 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 971 { 972 struct net_device *ndev = dev_id; 973 struct ravb_private *priv = netdev_priv(ndev); 974 const struct ravb_hw_info *info = priv->info; 975 irqreturn_t result = IRQ_NONE; 976 u32 iss; 977 978 spin_lock(&priv->lock); 979 /* Get interrupt status */ 980 iss = ravb_read(ndev, ISS); 981 982 /* Received and transmitted interrupts */ 983 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 984 int q; 985 986 /* Timestamp updated */ 987 if (ravb_timestamp_interrupt(ndev)) 988 result = IRQ_HANDLED; 989 990 /* Network control and best effort queue RX/TX */ 991 if (info->nc_queue) { 992 for (q = RAVB_NC; q >= RAVB_BE; q--) { 993 if (ravb_queue_interrupt(ndev, q)) 994 result = IRQ_HANDLED; 995 } 996 } else { 997 if (ravb_queue_interrupt(ndev, RAVB_BE)) 998 result = IRQ_HANDLED; 999 } 1000 } 1001 1002 /* E-MAC status summary */ 1003 if (iss & ISS_MS) { 1004 ravb_emac_interrupt_unlocked(ndev); 1005 result = IRQ_HANDLED; 1006 } 1007 1008 /* Error status summary */ 1009 if (iss & ISS_ES) { 1010 ravb_error_interrupt(ndev); 1011 result = IRQ_HANDLED; 1012 } 1013 1014 /* gPTP interrupt status summary */ 1015 if (iss & ISS_CGIS) { 1016 ravb_ptp_interrupt(ndev); 1017 result = IRQ_HANDLED; 1018 } 1019 1020 spin_unlock(&priv->lock); 1021 return result; 1022 } 1023 1024 /* Timestamp/Error/gPTP interrupt handler */ 1025 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1026 { 1027 struct net_device *ndev = dev_id; 1028 struct ravb_private *priv = netdev_priv(ndev); 1029 irqreturn_t result = IRQ_NONE; 1030 u32 iss; 1031 1032 spin_lock(&priv->lock); 1033 /* Get interrupt status */ 1034 iss = ravb_read(ndev, ISS); 1035 1036 /* Timestamp updated */ 1037 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1038 result = IRQ_HANDLED; 1039 1040 /* Error status summary */ 1041 if (iss & ISS_ES) { 1042 ravb_error_interrupt(ndev); 1043 result = IRQ_HANDLED; 1044 } 1045 1046 /* gPTP interrupt status summary */ 1047 if (iss & ISS_CGIS) { 1048 ravb_ptp_interrupt(ndev); 1049 result = IRQ_HANDLED; 1050 } 1051 1052 spin_unlock(&priv->lock); 1053 return result; 1054 } 1055 1056 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1057 { 1058 struct net_device *ndev = dev_id; 1059 struct ravb_private *priv = netdev_priv(ndev); 1060 irqreturn_t result = IRQ_NONE; 1061 1062 spin_lock(&priv->lock); 1063 1064 /* Network control/Best effort queue RX/TX */ 1065 if (ravb_queue_interrupt(ndev, q)) 1066 result = IRQ_HANDLED; 1067 1068 spin_unlock(&priv->lock); 1069 return result; 1070 } 1071 1072 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1073 { 1074 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1075 } 1076 1077 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1078 { 1079 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1080 } 1081 1082 static int ravb_poll(struct napi_struct *napi, int budget) 1083 { 1084 struct net_device *ndev = napi->dev; 1085 struct ravb_private *priv = netdev_priv(ndev); 1086 const struct ravb_hw_info *info = priv->info; 1087 unsigned long flags; 1088 int q = napi - priv->napi; 1089 int mask = BIT(q); 1090 int quota = budget; 1091 1092 /* Processing RX Descriptor Ring */ 1093 /* Clear RX interrupt */ 1094 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1095 if (ravb_rx(ndev, "a, q)) 1096 goto out; 1097 1098 /* Processing TX Descriptor Ring */ 1099 spin_lock_irqsave(&priv->lock, flags); 1100 /* Clear TX interrupt */ 1101 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1102 ravb_tx_free(ndev, q, true); 1103 netif_wake_subqueue(ndev, q); 1104 spin_unlock_irqrestore(&priv->lock, flags); 1105 1106 napi_complete(napi); 1107 1108 /* Re-enable RX/TX interrupts */ 1109 spin_lock_irqsave(&priv->lock, flags); 1110 if (!info->multi_irqs) { 1111 ravb_modify(ndev, RIC0, mask, mask); 1112 ravb_modify(ndev, TIC, mask, mask); 1113 } else { 1114 ravb_write(ndev, mask, RIE0); 1115 ravb_write(ndev, mask, TIE); 1116 } 1117 spin_unlock_irqrestore(&priv->lock, flags); 1118 1119 /* Receive error message handling */ 1120 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1121 if (info->nc_queue) 1122 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1123 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1124 ndev->stats.rx_over_errors = priv->rx_over_errors; 1125 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1126 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1127 out: 1128 return budget - quota; 1129 } 1130 1131 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1132 { 1133 struct ravb_private *priv = netdev_priv(ndev); 1134 1135 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1136 } 1137 1138 /* PHY state control function */ 1139 static void ravb_adjust_link(struct net_device *ndev) 1140 { 1141 struct ravb_private *priv = netdev_priv(ndev); 1142 const struct ravb_hw_info *info = priv->info; 1143 struct phy_device *phydev = ndev->phydev; 1144 bool new_state = false; 1145 unsigned long flags; 1146 1147 spin_lock_irqsave(&priv->lock, flags); 1148 1149 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1150 if (priv->no_avb_link) 1151 ravb_rcv_snd_disable(ndev); 1152 1153 if (phydev->link) { 1154 if (info->half_duplex && phydev->duplex != priv->duplex) { 1155 new_state = true; 1156 priv->duplex = phydev->duplex; 1157 ravb_set_duplex_gbeth(ndev); 1158 } 1159 1160 if (phydev->speed != priv->speed) { 1161 new_state = true; 1162 priv->speed = phydev->speed; 1163 info->set_rate(ndev); 1164 } 1165 if (!priv->link) { 1166 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1167 new_state = true; 1168 priv->link = phydev->link; 1169 } 1170 } else if (priv->link) { 1171 new_state = true; 1172 priv->link = 0; 1173 priv->speed = 0; 1174 if (info->half_duplex) 1175 priv->duplex = -1; 1176 } 1177 1178 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1179 if (priv->no_avb_link && phydev->link) 1180 ravb_rcv_snd_enable(ndev); 1181 1182 spin_unlock_irqrestore(&priv->lock, flags); 1183 1184 if (new_state && netif_msg_link(priv)) 1185 phy_print_status(phydev); 1186 } 1187 1188 static const struct soc_device_attribute r8a7795es10[] = { 1189 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1190 { /* sentinel */ } 1191 }; 1192 1193 /* PHY init function */ 1194 static int ravb_phy_init(struct net_device *ndev) 1195 { 1196 struct device_node *np = ndev->dev.parent->of_node; 1197 struct ravb_private *priv = netdev_priv(ndev); 1198 const struct ravb_hw_info *info = priv->info; 1199 struct phy_device *phydev; 1200 struct device_node *pn; 1201 phy_interface_t iface; 1202 int err; 1203 1204 priv->link = 0; 1205 priv->speed = 0; 1206 priv->duplex = -1; 1207 1208 /* Try connecting to PHY */ 1209 pn = of_parse_phandle(np, "phy-handle", 0); 1210 if (!pn) { 1211 /* In the case of a fixed PHY, the DT node associated 1212 * to the PHY is the Ethernet MAC DT node. 1213 */ 1214 if (of_phy_is_fixed_link(np)) { 1215 err = of_phy_register_fixed_link(np); 1216 if (err) 1217 return err; 1218 } 1219 pn = of_node_get(np); 1220 } 1221 1222 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1223 : priv->phy_interface; 1224 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1225 of_node_put(pn); 1226 if (!phydev) { 1227 netdev_err(ndev, "failed to connect PHY\n"); 1228 err = -ENOENT; 1229 goto err_deregister_fixed_link; 1230 } 1231 1232 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1233 * at this time. 1234 */ 1235 if (soc_device_match(r8a7795es10)) { 1236 err = phy_set_max_speed(phydev, SPEED_100); 1237 if (err) { 1238 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1239 goto err_phy_disconnect; 1240 } 1241 1242 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1243 } 1244 1245 if (!info->half_duplex) { 1246 /* 10BASE, Pause and Asym Pause is not supported */ 1247 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1248 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1249 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1250 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1251 1252 /* Half Duplex is not supported */ 1253 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1254 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1255 } 1256 1257 phy_attached_info(phydev); 1258 1259 return 0; 1260 1261 err_phy_disconnect: 1262 phy_disconnect(phydev); 1263 err_deregister_fixed_link: 1264 if (of_phy_is_fixed_link(np)) 1265 of_phy_deregister_fixed_link(np); 1266 1267 return err; 1268 } 1269 1270 /* PHY control start function */ 1271 static int ravb_phy_start(struct net_device *ndev) 1272 { 1273 int error; 1274 1275 error = ravb_phy_init(ndev); 1276 if (error) 1277 return error; 1278 1279 phy_start(ndev->phydev); 1280 1281 return 0; 1282 } 1283 1284 static u32 ravb_get_msglevel(struct net_device *ndev) 1285 { 1286 struct ravb_private *priv = netdev_priv(ndev); 1287 1288 return priv->msg_enable; 1289 } 1290 1291 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1292 { 1293 struct ravb_private *priv = netdev_priv(ndev); 1294 1295 priv->msg_enable = value; 1296 } 1297 1298 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1299 "rx_queue_0_current", 1300 "tx_queue_0_current", 1301 "rx_queue_0_dirty", 1302 "tx_queue_0_dirty", 1303 "rx_queue_0_packets", 1304 "tx_queue_0_packets", 1305 "rx_queue_0_bytes", 1306 "tx_queue_0_bytes", 1307 "rx_queue_0_mcast_packets", 1308 "rx_queue_0_errors", 1309 "rx_queue_0_crc_errors", 1310 "rx_queue_0_frame_errors", 1311 "rx_queue_0_length_errors", 1312 "rx_queue_0_missed_errors", 1313 "rx_queue_0_over_errors", 1314 1315 "rx_queue_1_current", 1316 "tx_queue_1_current", 1317 "rx_queue_1_dirty", 1318 "tx_queue_1_dirty", 1319 "rx_queue_1_packets", 1320 "tx_queue_1_packets", 1321 "rx_queue_1_bytes", 1322 "tx_queue_1_bytes", 1323 "rx_queue_1_mcast_packets", 1324 "rx_queue_1_errors", 1325 "rx_queue_1_crc_errors", 1326 "rx_queue_1_frame_errors", 1327 "rx_queue_1_length_errors", 1328 "rx_queue_1_missed_errors", 1329 "rx_queue_1_over_errors", 1330 }; 1331 1332 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1333 { 1334 struct ravb_private *priv = netdev_priv(netdev); 1335 const struct ravb_hw_info *info = priv->info; 1336 1337 switch (sset) { 1338 case ETH_SS_STATS: 1339 return info->stats_len; 1340 default: 1341 return -EOPNOTSUPP; 1342 } 1343 } 1344 1345 static void ravb_get_ethtool_stats(struct net_device *ndev, 1346 struct ethtool_stats *estats, u64 *data) 1347 { 1348 struct ravb_private *priv = netdev_priv(ndev); 1349 const struct ravb_hw_info *info = priv->info; 1350 int num_rx_q; 1351 int i = 0; 1352 int q; 1353 1354 num_rx_q = info->nc_queue ? NUM_RX_QUEUE : 1; 1355 /* Device-specific stats */ 1356 for (q = RAVB_BE; q < num_rx_q; q++) { 1357 struct net_device_stats *stats = &priv->stats[q]; 1358 1359 data[i++] = priv->cur_rx[q]; 1360 data[i++] = priv->cur_tx[q]; 1361 data[i++] = priv->dirty_rx[q]; 1362 data[i++] = priv->dirty_tx[q]; 1363 data[i++] = stats->rx_packets; 1364 data[i++] = stats->tx_packets; 1365 data[i++] = stats->rx_bytes; 1366 data[i++] = stats->tx_bytes; 1367 data[i++] = stats->multicast; 1368 data[i++] = stats->rx_errors; 1369 data[i++] = stats->rx_crc_errors; 1370 data[i++] = stats->rx_frame_errors; 1371 data[i++] = stats->rx_length_errors; 1372 data[i++] = stats->rx_missed_errors; 1373 data[i++] = stats->rx_over_errors; 1374 } 1375 } 1376 1377 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1378 { 1379 struct ravb_private *priv = netdev_priv(ndev); 1380 const struct ravb_hw_info *info = priv->info; 1381 1382 switch (stringset) { 1383 case ETH_SS_STATS: 1384 memcpy(data, info->gstrings_stats, info->gstrings_size); 1385 break; 1386 } 1387 } 1388 1389 static void ravb_get_ringparam(struct net_device *ndev, 1390 struct ethtool_ringparam *ring) 1391 { 1392 struct ravb_private *priv = netdev_priv(ndev); 1393 1394 ring->rx_max_pending = BE_RX_RING_MAX; 1395 ring->tx_max_pending = BE_TX_RING_MAX; 1396 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1397 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1398 } 1399 1400 static int ravb_set_ringparam(struct net_device *ndev, 1401 struct ethtool_ringparam *ring) 1402 { 1403 struct ravb_private *priv = netdev_priv(ndev); 1404 const struct ravb_hw_info *info = priv->info; 1405 int error; 1406 1407 if (ring->tx_pending > BE_TX_RING_MAX || 1408 ring->rx_pending > BE_RX_RING_MAX || 1409 ring->tx_pending < BE_TX_RING_MIN || 1410 ring->rx_pending < BE_RX_RING_MIN) 1411 return -EINVAL; 1412 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1413 return -EINVAL; 1414 1415 if (netif_running(ndev)) { 1416 netif_device_detach(ndev); 1417 /* Stop PTP Clock driver */ 1418 if (info->gptp) 1419 ravb_ptp_stop(ndev); 1420 /* Wait for DMA stopping */ 1421 error = ravb_stop_dma(ndev); 1422 if (error) { 1423 netdev_err(ndev, 1424 "cannot set ringparam! Any AVB processes are still running?\n"); 1425 return error; 1426 } 1427 synchronize_irq(ndev->irq); 1428 1429 /* Free all the skb's in the RX queue and the DMA buffers. */ 1430 ravb_ring_free(ndev, RAVB_BE); 1431 if (info->nc_queue) 1432 ravb_ring_free(ndev, RAVB_NC); 1433 } 1434 1435 /* Set new parameters */ 1436 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1437 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1438 1439 if (netif_running(ndev)) { 1440 error = ravb_dmac_init(ndev); 1441 if (error) { 1442 netdev_err(ndev, 1443 "%s: ravb_dmac_init() failed, error %d\n", 1444 __func__, error); 1445 return error; 1446 } 1447 1448 ravb_emac_init(ndev); 1449 1450 /* Initialise PTP Clock driver */ 1451 if (info->gptp) 1452 ravb_ptp_init(ndev, priv->pdev); 1453 1454 netif_device_attach(ndev); 1455 } 1456 1457 return 0; 1458 } 1459 1460 static int ravb_get_ts_info(struct net_device *ndev, 1461 struct ethtool_ts_info *info) 1462 { 1463 struct ravb_private *priv = netdev_priv(ndev); 1464 const struct ravb_hw_info *hw_info = priv->info; 1465 1466 info->so_timestamping = 1467 SOF_TIMESTAMPING_TX_SOFTWARE | 1468 SOF_TIMESTAMPING_RX_SOFTWARE | 1469 SOF_TIMESTAMPING_SOFTWARE | 1470 SOF_TIMESTAMPING_TX_HARDWARE | 1471 SOF_TIMESTAMPING_RX_HARDWARE | 1472 SOF_TIMESTAMPING_RAW_HARDWARE; 1473 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1474 info->rx_filters = 1475 (1 << HWTSTAMP_FILTER_NONE) | 1476 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1477 (1 << HWTSTAMP_FILTER_ALL); 1478 if (hw_info->gptp || hw_info->ccc_gac) 1479 info->phc_index = ptp_clock_index(priv->ptp.clock); 1480 1481 return 0; 1482 } 1483 1484 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1485 { 1486 struct ravb_private *priv = netdev_priv(ndev); 1487 1488 wol->supported = WAKE_MAGIC; 1489 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1490 } 1491 1492 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1493 { 1494 struct ravb_private *priv = netdev_priv(ndev); 1495 const struct ravb_hw_info *info = priv->info; 1496 1497 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1498 return -EOPNOTSUPP; 1499 1500 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1501 1502 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1503 1504 return 0; 1505 } 1506 1507 static const struct ethtool_ops ravb_ethtool_ops = { 1508 .nway_reset = phy_ethtool_nway_reset, 1509 .get_msglevel = ravb_get_msglevel, 1510 .set_msglevel = ravb_set_msglevel, 1511 .get_link = ethtool_op_get_link, 1512 .get_strings = ravb_get_strings, 1513 .get_ethtool_stats = ravb_get_ethtool_stats, 1514 .get_sset_count = ravb_get_sset_count, 1515 .get_ringparam = ravb_get_ringparam, 1516 .set_ringparam = ravb_set_ringparam, 1517 .get_ts_info = ravb_get_ts_info, 1518 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1519 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1520 .get_wol = ravb_get_wol, 1521 .set_wol = ravb_set_wol, 1522 }; 1523 1524 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1525 struct net_device *ndev, struct device *dev, 1526 const char *ch) 1527 { 1528 char *name; 1529 int error; 1530 1531 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1532 if (!name) 1533 return -ENOMEM; 1534 error = request_irq(irq, handler, 0, name, ndev); 1535 if (error) 1536 netdev_err(ndev, "cannot request IRQ %s\n", name); 1537 1538 return error; 1539 } 1540 1541 /* Network device open function for Ethernet AVB */ 1542 static int ravb_open(struct net_device *ndev) 1543 { 1544 struct ravb_private *priv = netdev_priv(ndev); 1545 const struct ravb_hw_info *info = priv->info; 1546 struct platform_device *pdev = priv->pdev; 1547 struct device *dev = &pdev->dev; 1548 int error; 1549 1550 napi_enable(&priv->napi[RAVB_BE]); 1551 if (info->nc_queue) 1552 napi_enable(&priv->napi[RAVB_NC]); 1553 1554 if (!info->multi_irqs) { 1555 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1556 ndev->name, ndev); 1557 if (error) { 1558 netdev_err(ndev, "cannot request IRQ\n"); 1559 goto out_napi_off; 1560 } 1561 } else { 1562 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1563 dev, "ch22:multi"); 1564 if (error) 1565 goto out_napi_off; 1566 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1567 dev, "ch24:emac"); 1568 if (error) 1569 goto out_free_irq; 1570 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1571 ndev, dev, "ch0:rx_be"); 1572 if (error) 1573 goto out_free_irq_emac; 1574 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1575 ndev, dev, "ch18:tx_be"); 1576 if (error) 1577 goto out_free_irq_be_rx; 1578 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1579 ndev, dev, "ch1:rx_nc"); 1580 if (error) 1581 goto out_free_irq_be_tx; 1582 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1583 ndev, dev, "ch19:tx_nc"); 1584 if (error) 1585 goto out_free_irq_nc_rx; 1586 } 1587 1588 /* Device init */ 1589 error = ravb_dmac_init(ndev); 1590 if (error) 1591 goto out_free_irq_nc_tx; 1592 ravb_emac_init(ndev); 1593 1594 /* Initialise PTP Clock driver */ 1595 if (info->gptp) 1596 ravb_ptp_init(ndev, priv->pdev); 1597 1598 netif_tx_start_all_queues(ndev); 1599 1600 /* PHY control start */ 1601 error = ravb_phy_start(ndev); 1602 if (error) 1603 goto out_ptp_stop; 1604 1605 return 0; 1606 1607 out_ptp_stop: 1608 /* Stop PTP Clock driver */ 1609 if (info->gptp) 1610 ravb_ptp_stop(ndev); 1611 out_free_irq_nc_tx: 1612 if (!info->multi_irqs) 1613 goto out_free_irq; 1614 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1615 out_free_irq_nc_rx: 1616 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1617 out_free_irq_be_tx: 1618 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1619 out_free_irq_be_rx: 1620 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1621 out_free_irq_emac: 1622 free_irq(priv->emac_irq, ndev); 1623 out_free_irq: 1624 free_irq(ndev->irq, ndev); 1625 out_napi_off: 1626 if (info->nc_queue) 1627 napi_disable(&priv->napi[RAVB_NC]); 1628 napi_disable(&priv->napi[RAVB_BE]); 1629 return error; 1630 } 1631 1632 /* Timeout function for Ethernet AVB */ 1633 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1634 { 1635 struct ravb_private *priv = netdev_priv(ndev); 1636 1637 netif_err(priv, tx_err, ndev, 1638 "transmit timed out, status %08x, resetting...\n", 1639 ravb_read(ndev, ISS)); 1640 1641 /* tx_errors count up */ 1642 ndev->stats.tx_errors++; 1643 1644 schedule_work(&priv->work); 1645 } 1646 1647 static void ravb_tx_timeout_work(struct work_struct *work) 1648 { 1649 struct ravb_private *priv = container_of(work, struct ravb_private, 1650 work); 1651 const struct ravb_hw_info *info = priv->info; 1652 struct net_device *ndev = priv->ndev; 1653 int error; 1654 1655 netif_tx_stop_all_queues(ndev); 1656 1657 /* Stop PTP Clock driver */ 1658 if (info->gptp) 1659 ravb_ptp_stop(ndev); 1660 1661 /* Wait for DMA stopping */ 1662 if (ravb_stop_dma(ndev)) { 1663 /* If ravb_stop_dma() fails, the hardware is still operating 1664 * for TX and/or RX. So, this should not call the following 1665 * functions because ravb_dmac_init() is possible to fail too. 1666 * Also, this should not retry ravb_stop_dma() again and again 1667 * here because it's possible to wait forever. So, this just 1668 * re-enables the TX and RX and skip the following 1669 * re-initialization procedure. 1670 */ 1671 ravb_rcv_snd_enable(ndev); 1672 goto out; 1673 } 1674 1675 ravb_ring_free(ndev, RAVB_BE); 1676 if (info->nc_queue) 1677 ravb_ring_free(ndev, RAVB_NC); 1678 1679 /* Device init */ 1680 error = ravb_dmac_init(ndev); 1681 if (error) { 1682 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1683 * should return here to avoid re-enabling the TX and RX in 1684 * ravb_emac_init(). 1685 */ 1686 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1687 __func__, error); 1688 return; 1689 } 1690 ravb_emac_init(ndev); 1691 1692 out: 1693 /* Initialise PTP Clock driver */ 1694 if (info->gptp) 1695 ravb_ptp_init(ndev, priv->pdev); 1696 1697 netif_tx_start_all_queues(ndev); 1698 } 1699 1700 /* Packet transmit function for Ethernet AVB */ 1701 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1702 { 1703 struct ravb_private *priv = netdev_priv(ndev); 1704 const struct ravb_hw_info *info = priv->info; 1705 unsigned int num_tx_desc = priv->num_tx_desc; 1706 u16 q = skb_get_queue_mapping(skb); 1707 struct ravb_tstamp_skb *ts_skb; 1708 struct ravb_tx_desc *desc; 1709 unsigned long flags; 1710 u32 dma_addr; 1711 void *buffer; 1712 u32 entry; 1713 u32 len; 1714 1715 spin_lock_irqsave(&priv->lock, flags); 1716 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1717 num_tx_desc) { 1718 netif_err(priv, tx_queued, ndev, 1719 "still transmitting with the full ring!\n"); 1720 netif_stop_subqueue(ndev, q); 1721 spin_unlock_irqrestore(&priv->lock, flags); 1722 return NETDEV_TX_BUSY; 1723 } 1724 1725 if (skb_put_padto(skb, ETH_ZLEN)) 1726 goto exit; 1727 1728 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1729 priv->tx_skb[q][entry / num_tx_desc] = skb; 1730 1731 if (num_tx_desc > 1) { 1732 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1733 entry / num_tx_desc * DPTR_ALIGN; 1734 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1735 1736 /* Zero length DMA descriptors are problematic as they seem 1737 * to terminate DMA transfers. Avoid them by simply using a 1738 * length of DPTR_ALIGN (4) when skb data is aligned to 1739 * DPTR_ALIGN. 1740 * 1741 * As skb is guaranteed to have at least ETH_ZLEN (60) 1742 * bytes of data by the call to skb_put_padto() above this 1743 * is safe with respect to both the length of the first DMA 1744 * descriptor (len) overflowing the available data and the 1745 * length of the second DMA descriptor (skb->len - len) 1746 * being negative. 1747 */ 1748 if (len == 0) 1749 len = DPTR_ALIGN; 1750 1751 memcpy(buffer, skb->data, len); 1752 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1753 DMA_TO_DEVICE); 1754 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1755 goto drop; 1756 1757 desc = &priv->tx_ring[q][entry]; 1758 desc->ds_tagl = cpu_to_le16(len); 1759 desc->dptr = cpu_to_le32(dma_addr); 1760 1761 buffer = skb->data + len; 1762 len = skb->len - len; 1763 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1764 DMA_TO_DEVICE); 1765 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1766 goto unmap; 1767 1768 desc++; 1769 } else { 1770 desc = &priv->tx_ring[q][entry]; 1771 len = skb->len; 1772 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1773 DMA_TO_DEVICE); 1774 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1775 goto drop; 1776 } 1777 desc->ds_tagl = cpu_to_le16(len); 1778 desc->dptr = cpu_to_le32(dma_addr); 1779 1780 /* TX timestamp required */ 1781 if (info->gptp || info->ccc_gac) { 1782 if (q == RAVB_NC) { 1783 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1784 if (!ts_skb) { 1785 if (num_tx_desc > 1) { 1786 desc--; 1787 dma_unmap_single(ndev->dev.parent, dma_addr, 1788 len, DMA_TO_DEVICE); 1789 } 1790 goto unmap; 1791 } 1792 ts_skb->skb = skb_get(skb); 1793 ts_skb->tag = priv->ts_skb_tag++; 1794 priv->ts_skb_tag &= 0x3ff; 1795 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1796 1797 /* TAG and timestamp required flag */ 1798 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1799 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1800 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1801 } 1802 1803 skb_tx_timestamp(skb); 1804 } 1805 /* Descriptor type must be set after all the above writes */ 1806 dma_wmb(); 1807 if (num_tx_desc > 1) { 1808 desc->die_dt = DT_FEND; 1809 desc--; 1810 desc->die_dt = DT_FSTART; 1811 } else { 1812 desc->die_dt = DT_FSINGLE; 1813 } 1814 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1815 1816 priv->cur_tx[q] += num_tx_desc; 1817 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1818 (priv->num_tx_ring[q] - 1) * num_tx_desc && 1819 !ravb_tx_free(ndev, q, true)) 1820 netif_stop_subqueue(ndev, q); 1821 1822 exit: 1823 spin_unlock_irqrestore(&priv->lock, flags); 1824 return NETDEV_TX_OK; 1825 1826 unmap: 1827 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1828 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1829 drop: 1830 dev_kfree_skb_any(skb); 1831 priv->tx_skb[q][entry / num_tx_desc] = NULL; 1832 goto exit; 1833 } 1834 1835 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1836 struct net_device *sb_dev) 1837 { 1838 /* If skb needs TX timestamp, it is handled in network control queue */ 1839 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1840 RAVB_BE; 1841 1842 } 1843 1844 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1845 { 1846 struct ravb_private *priv = netdev_priv(ndev); 1847 const struct ravb_hw_info *info = priv->info; 1848 struct net_device_stats *nstats, *stats0, *stats1; 1849 1850 nstats = &ndev->stats; 1851 stats0 = &priv->stats[RAVB_BE]; 1852 1853 if (info->tx_counters) { 1854 nstats->tx_dropped += ravb_read(ndev, TROCR); 1855 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1856 } 1857 1858 nstats->rx_packets = stats0->rx_packets; 1859 nstats->tx_packets = stats0->tx_packets; 1860 nstats->rx_bytes = stats0->rx_bytes; 1861 nstats->tx_bytes = stats0->tx_bytes; 1862 nstats->multicast = stats0->multicast; 1863 nstats->rx_errors = stats0->rx_errors; 1864 nstats->rx_crc_errors = stats0->rx_crc_errors; 1865 nstats->rx_frame_errors = stats0->rx_frame_errors; 1866 nstats->rx_length_errors = stats0->rx_length_errors; 1867 nstats->rx_missed_errors = stats0->rx_missed_errors; 1868 nstats->rx_over_errors = stats0->rx_over_errors; 1869 if (info->nc_queue) { 1870 stats1 = &priv->stats[RAVB_NC]; 1871 1872 nstats->rx_packets += stats1->rx_packets; 1873 nstats->tx_packets += stats1->tx_packets; 1874 nstats->rx_bytes += stats1->rx_bytes; 1875 nstats->tx_bytes += stats1->tx_bytes; 1876 nstats->multicast += stats1->multicast; 1877 nstats->rx_errors += stats1->rx_errors; 1878 nstats->rx_crc_errors += stats1->rx_crc_errors; 1879 nstats->rx_frame_errors += stats1->rx_frame_errors; 1880 nstats->rx_length_errors += stats1->rx_length_errors; 1881 nstats->rx_missed_errors += stats1->rx_missed_errors; 1882 nstats->rx_over_errors += stats1->rx_over_errors; 1883 } 1884 1885 return nstats; 1886 } 1887 1888 /* Update promiscuous bit */ 1889 static void ravb_set_rx_mode(struct net_device *ndev) 1890 { 1891 struct ravb_private *priv = netdev_priv(ndev); 1892 unsigned long flags; 1893 1894 spin_lock_irqsave(&priv->lock, flags); 1895 ravb_modify(ndev, ECMR, ECMR_PRM, 1896 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1897 spin_unlock_irqrestore(&priv->lock, flags); 1898 } 1899 1900 /* Device close function for Ethernet AVB */ 1901 static int ravb_close(struct net_device *ndev) 1902 { 1903 struct device_node *np = ndev->dev.parent->of_node; 1904 struct ravb_private *priv = netdev_priv(ndev); 1905 const struct ravb_hw_info *info = priv->info; 1906 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1907 1908 netif_tx_stop_all_queues(ndev); 1909 1910 /* Disable interrupts by clearing the interrupt masks. */ 1911 ravb_write(ndev, 0, RIC0); 1912 ravb_write(ndev, 0, RIC2); 1913 ravb_write(ndev, 0, TIC); 1914 1915 /* Stop PTP Clock driver */ 1916 if (info->gptp) 1917 ravb_ptp_stop(ndev); 1918 1919 /* Set the config mode to stop the AVB-DMAC's processes */ 1920 if (ravb_stop_dma(ndev) < 0) 1921 netdev_err(ndev, 1922 "device will be stopped after h/w processes are done.\n"); 1923 1924 /* Clear the timestamp list */ 1925 if (info->gptp || info->ccc_gac) { 1926 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1927 list_del(&ts_skb->list); 1928 kfree_skb(ts_skb->skb); 1929 kfree(ts_skb); 1930 } 1931 } 1932 1933 /* PHY disconnect */ 1934 if (ndev->phydev) { 1935 phy_stop(ndev->phydev); 1936 phy_disconnect(ndev->phydev); 1937 if (of_phy_is_fixed_link(np)) 1938 of_phy_deregister_fixed_link(np); 1939 } 1940 1941 if (info->multi_irqs) { 1942 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1943 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1944 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1945 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1946 free_irq(priv->emac_irq, ndev); 1947 } 1948 free_irq(ndev->irq, ndev); 1949 1950 if (info->nc_queue) 1951 napi_disable(&priv->napi[RAVB_NC]); 1952 napi_disable(&priv->napi[RAVB_BE]); 1953 1954 /* Free all the skb's in the RX queue and the DMA buffers. */ 1955 ravb_ring_free(ndev, RAVB_BE); 1956 if (info->nc_queue) 1957 ravb_ring_free(ndev, RAVB_NC); 1958 1959 return 0; 1960 } 1961 1962 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1963 { 1964 struct ravb_private *priv = netdev_priv(ndev); 1965 struct hwtstamp_config config; 1966 1967 config.flags = 0; 1968 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1969 HWTSTAMP_TX_OFF; 1970 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 1971 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 1972 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1973 break; 1974 case RAVB_RXTSTAMP_TYPE_ALL: 1975 config.rx_filter = HWTSTAMP_FILTER_ALL; 1976 break; 1977 default: 1978 config.rx_filter = HWTSTAMP_FILTER_NONE; 1979 } 1980 1981 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1982 -EFAULT : 0; 1983 } 1984 1985 /* Control hardware time stamping */ 1986 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1987 { 1988 struct ravb_private *priv = netdev_priv(ndev); 1989 struct hwtstamp_config config; 1990 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1991 u32 tstamp_tx_ctrl; 1992 1993 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1994 return -EFAULT; 1995 1996 /* Reserved for future extensions */ 1997 if (config.flags) 1998 return -EINVAL; 1999 2000 switch (config.tx_type) { 2001 case HWTSTAMP_TX_OFF: 2002 tstamp_tx_ctrl = 0; 2003 break; 2004 case HWTSTAMP_TX_ON: 2005 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2006 break; 2007 default: 2008 return -ERANGE; 2009 } 2010 2011 switch (config.rx_filter) { 2012 case HWTSTAMP_FILTER_NONE: 2013 tstamp_rx_ctrl = 0; 2014 break; 2015 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2016 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2017 break; 2018 default: 2019 config.rx_filter = HWTSTAMP_FILTER_ALL; 2020 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2021 } 2022 2023 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2024 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2025 2026 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2027 -EFAULT : 0; 2028 } 2029 2030 /* ioctl to device function */ 2031 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2032 { 2033 struct phy_device *phydev = ndev->phydev; 2034 2035 if (!netif_running(ndev)) 2036 return -EINVAL; 2037 2038 if (!phydev) 2039 return -ENODEV; 2040 2041 switch (cmd) { 2042 case SIOCGHWTSTAMP: 2043 return ravb_hwtstamp_get(ndev, req); 2044 case SIOCSHWTSTAMP: 2045 return ravb_hwtstamp_set(ndev, req); 2046 } 2047 2048 return phy_mii_ioctl(phydev, req, cmd); 2049 } 2050 2051 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2052 { 2053 struct ravb_private *priv = netdev_priv(ndev); 2054 2055 ndev->mtu = new_mtu; 2056 2057 if (netif_running(ndev)) { 2058 synchronize_irq(priv->emac_irq); 2059 ravb_emac_init(ndev); 2060 } 2061 2062 netdev_update_features(ndev); 2063 2064 return 0; 2065 } 2066 2067 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2068 { 2069 struct ravb_private *priv = netdev_priv(ndev); 2070 unsigned long flags; 2071 2072 spin_lock_irqsave(&priv->lock, flags); 2073 2074 /* Disable TX and RX */ 2075 ravb_rcv_snd_disable(ndev); 2076 2077 /* Modify RX Checksum setting */ 2078 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2079 2080 /* Enable TX and RX */ 2081 ravb_rcv_snd_enable(ndev); 2082 2083 spin_unlock_irqrestore(&priv->lock, flags); 2084 } 2085 2086 static int ravb_set_features_gbeth(struct net_device *ndev, 2087 netdev_features_t features) 2088 { 2089 /* Place holder */ 2090 return 0; 2091 } 2092 2093 static int ravb_set_features_rcar(struct net_device *ndev, 2094 netdev_features_t features) 2095 { 2096 netdev_features_t changed = ndev->features ^ features; 2097 2098 if (changed & NETIF_F_RXCSUM) 2099 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2100 2101 ndev->features = features; 2102 2103 return 0; 2104 } 2105 2106 static int ravb_set_features(struct net_device *ndev, 2107 netdev_features_t features) 2108 { 2109 struct ravb_private *priv = netdev_priv(ndev); 2110 const struct ravb_hw_info *info = priv->info; 2111 2112 return info->set_feature(ndev, features); 2113 } 2114 2115 static const struct net_device_ops ravb_netdev_ops = { 2116 .ndo_open = ravb_open, 2117 .ndo_stop = ravb_close, 2118 .ndo_start_xmit = ravb_start_xmit, 2119 .ndo_select_queue = ravb_select_queue, 2120 .ndo_get_stats = ravb_get_stats, 2121 .ndo_set_rx_mode = ravb_set_rx_mode, 2122 .ndo_tx_timeout = ravb_tx_timeout, 2123 .ndo_eth_ioctl = ravb_do_ioctl, 2124 .ndo_change_mtu = ravb_change_mtu, 2125 .ndo_validate_addr = eth_validate_addr, 2126 .ndo_set_mac_address = eth_mac_addr, 2127 .ndo_set_features = ravb_set_features, 2128 }; 2129 2130 /* MDIO bus init function */ 2131 static int ravb_mdio_init(struct ravb_private *priv) 2132 { 2133 struct platform_device *pdev = priv->pdev; 2134 struct device *dev = &pdev->dev; 2135 int error; 2136 2137 /* Bitbang init */ 2138 priv->mdiobb.ops = &bb_ops; 2139 2140 /* MII controller setting */ 2141 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2142 if (!priv->mii_bus) 2143 return -ENOMEM; 2144 2145 /* Hook up MII support for ethtool */ 2146 priv->mii_bus->name = "ravb_mii"; 2147 priv->mii_bus->parent = dev; 2148 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2149 pdev->name, pdev->id); 2150 2151 /* Register MDIO bus */ 2152 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 2153 if (error) 2154 goto out_free_bus; 2155 2156 return 0; 2157 2158 out_free_bus: 2159 free_mdio_bitbang(priv->mii_bus); 2160 return error; 2161 } 2162 2163 /* MDIO bus release function */ 2164 static int ravb_mdio_release(struct ravb_private *priv) 2165 { 2166 /* Unregister mdio bus */ 2167 mdiobus_unregister(priv->mii_bus); 2168 2169 /* Free bitbang info */ 2170 free_mdio_bitbang(priv->mii_bus); 2171 2172 return 0; 2173 } 2174 2175 static const struct ravb_hw_info ravb_gen3_hw_info = { 2176 .rx_ring_free = ravb_rx_ring_free, 2177 .rx_ring_format = ravb_rx_ring_format, 2178 .alloc_rx_desc = ravb_alloc_rx_desc, 2179 .receive = ravb_rcar_rx, 2180 .set_rate = ravb_set_rate_rcar, 2181 .set_feature = ravb_set_features_rcar, 2182 .dmac_init = ravb_dmac_init_rcar, 2183 .emac_init = ravb_emac_init_rcar, 2184 .gstrings_stats = ravb_gstrings_stats, 2185 .gstrings_size = sizeof(ravb_gstrings_stats), 2186 .net_hw_features = NETIF_F_RXCSUM, 2187 .net_features = NETIF_F_RXCSUM, 2188 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2189 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2190 .tsrq = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2191 .internal_delay = 1, 2192 .tx_counters = 1, 2193 .multi_irqs = 1, 2194 .ccc_gac = 1, 2195 .nc_queue = 1, 2196 .magic_pkt = 1, 2197 }; 2198 2199 static const struct ravb_hw_info ravb_gen2_hw_info = { 2200 .rx_ring_free = ravb_rx_ring_free, 2201 .rx_ring_format = ravb_rx_ring_format, 2202 .alloc_rx_desc = ravb_alloc_rx_desc, 2203 .receive = ravb_rcar_rx, 2204 .set_rate = ravb_set_rate_rcar, 2205 .set_feature = ravb_set_features_rcar, 2206 .dmac_init = ravb_dmac_init_rcar, 2207 .emac_init = ravb_emac_init_rcar, 2208 .gstrings_stats = ravb_gstrings_stats, 2209 .gstrings_size = sizeof(ravb_gstrings_stats), 2210 .net_hw_features = NETIF_F_RXCSUM, 2211 .net_features = NETIF_F_RXCSUM, 2212 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2213 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2214 .tsrq = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2215 .aligned_tx = 1, 2216 .gptp = 1, 2217 .nc_queue = 1, 2218 .magic_pkt = 1, 2219 }; 2220 2221 static const struct ravb_hw_info gbeth_hw_info = { 2222 .rx_ring_free = ravb_rx_ring_free_gbeth, 2223 .rx_ring_format = ravb_rx_ring_format_gbeth, 2224 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth, 2225 .receive = ravb_rx_gbeth, 2226 .set_rate = ravb_set_rate_gbeth, 2227 .set_feature = ravb_set_features_gbeth, 2228 .dmac_init = ravb_dmac_init_gbeth, 2229 .emac_init = ravb_emac_init_gbeth, 2230 .max_rx_len = GBETH_RX_BUFF_MAX + RAVB_ALIGN - 1, 2231 .tsrq = TCCR_TSRQ0, 2232 .aligned_tx = 1, 2233 .tx_counters = 1, 2234 .half_duplex = 1, 2235 }; 2236 2237 static const struct of_device_id ravb_match_table[] = { 2238 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2239 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2240 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2241 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2242 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2243 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2244 { } 2245 }; 2246 MODULE_DEVICE_TABLE(of, ravb_match_table); 2247 2248 static int ravb_set_gti(struct net_device *ndev) 2249 { 2250 struct ravb_private *priv = netdev_priv(ndev); 2251 struct device *dev = ndev->dev.parent; 2252 unsigned long rate; 2253 uint64_t inc; 2254 2255 rate = clk_get_rate(priv->clk); 2256 if (!rate) 2257 return -EINVAL; 2258 2259 inc = 1000000000ULL << 20; 2260 do_div(inc, rate); 2261 2262 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 2263 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 2264 inc, GTI_TIV_MIN, GTI_TIV_MAX); 2265 return -EINVAL; 2266 } 2267 2268 ravb_write(ndev, inc, GTI); 2269 2270 return 0; 2271 } 2272 2273 static void ravb_set_config_mode(struct net_device *ndev) 2274 { 2275 struct ravb_private *priv = netdev_priv(ndev); 2276 const struct ravb_hw_info *info = priv->info; 2277 2278 if (info->gptp) { 2279 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2280 /* Set CSEL value */ 2281 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 2282 } else if (info->ccc_gac) { 2283 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 2284 CCC_GAC | CCC_CSEL_HPB); 2285 } else { 2286 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 2287 } 2288 } 2289 2290 /* Set tx and rx clock internal delay modes */ 2291 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 2292 { 2293 struct ravb_private *priv = netdev_priv(ndev); 2294 bool explicit_delay = false; 2295 u32 delay; 2296 2297 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2298 /* Valid values are 0 and 1800, according to DT bindings */ 2299 priv->rxcidm = !!delay; 2300 explicit_delay = true; 2301 } 2302 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2303 /* Valid values are 0 and 2000, according to DT bindings */ 2304 priv->txcidm = !!delay; 2305 explicit_delay = true; 2306 } 2307 2308 if (explicit_delay) 2309 return; 2310 2311 /* Fall back to legacy rgmii-*id behavior */ 2312 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2313 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2314 priv->rxcidm = 1; 2315 priv->rgmii_override = 1; 2316 } 2317 2318 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2319 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2320 priv->txcidm = 1; 2321 priv->rgmii_override = 1; 2322 } 2323 } 2324 2325 static void ravb_set_delay_mode(struct net_device *ndev) 2326 { 2327 struct ravb_private *priv = netdev_priv(ndev); 2328 u32 set = 0; 2329 2330 if (priv->rxcidm) 2331 set |= APSR_RDM; 2332 if (priv->txcidm) 2333 set |= APSR_TDM; 2334 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 2335 } 2336 2337 static int ravb_probe(struct platform_device *pdev) 2338 { 2339 struct device_node *np = pdev->dev.of_node; 2340 const struct ravb_hw_info *info; 2341 struct reset_control *rstc; 2342 struct ravb_private *priv; 2343 struct net_device *ndev; 2344 int error, irq, q; 2345 struct resource *res; 2346 int i; 2347 2348 if (!np) { 2349 dev_err(&pdev->dev, 2350 "this driver is required to be instantiated from device tree\n"); 2351 return -EINVAL; 2352 } 2353 2354 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 2355 if (IS_ERR(rstc)) 2356 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2357 "failed to get cpg reset\n"); 2358 2359 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2360 NUM_TX_QUEUE, NUM_RX_QUEUE); 2361 if (!ndev) 2362 return -ENOMEM; 2363 2364 info = of_device_get_match_data(&pdev->dev); 2365 2366 ndev->features = info->net_features; 2367 ndev->hw_features = info->net_hw_features; 2368 2369 reset_control_deassert(rstc); 2370 pm_runtime_enable(&pdev->dev); 2371 pm_runtime_get_sync(&pdev->dev); 2372 2373 if (info->multi_irqs) 2374 irq = platform_get_irq_byname(pdev, "ch22"); 2375 else 2376 irq = platform_get_irq(pdev, 0); 2377 if (irq < 0) { 2378 error = irq; 2379 goto out_release; 2380 } 2381 ndev->irq = irq; 2382 2383 SET_NETDEV_DEV(ndev, &pdev->dev); 2384 2385 priv = netdev_priv(ndev); 2386 priv->info = info; 2387 priv->rstc = rstc; 2388 priv->ndev = ndev; 2389 priv->pdev = pdev; 2390 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2391 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2392 if (info->nc_queue) { 2393 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2394 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2395 } 2396 2397 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2398 if (IS_ERR(priv->addr)) { 2399 error = PTR_ERR(priv->addr); 2400 goto out_release; 2401 } 2402 2403 /* The Ether-specific entries in the device structure. */ 2404 ndev->base_addr = res->start; 2405 2406 spin_lock_init(&priv->lock); 2407 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2408 2409 error = of_get_phy_mode(np, &priv->phy_interface); 2410 if (error && error != -ENODEV) 2411 goto out_release; 2412 2413 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2414 priv->avb_link_active_low = 2415 of_property_read_bool(np, "renesas,ether-link-active-low"); 2416 2417 if (info->multi_irqs) { 2418 irq = platform_get_irq_byname(pdev, "ch24"); 2419 if (irq < 0) { 2420 error = irq; 2421 goto out_release; 2422 } 2423 priv->emac_irq = irq; 2424 for (i = 0; i < NUM_RX_QUEUE; i++) { 2425 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2426 if (irq < 0) { 2427 error = irq; 2428 goto out_release; 2429 } 2430 priv->rx_irqs[i] = irq; 2431 } 2432 for (i = 0; i < NUM_TX_QUEUE; i++) { 2433 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2434 if (irq < 0) { 2435 error = irq; 2436 goto out_release; 2437 } 2438 priv->tx_irqs[i] = irq; 2439 } 2440 } 2441 2442 priv->clk = devm_clk_get(&pdev->dev, NULL); 2443 if (IS_ERR(priv->clk)) { 2444 error = PTR_ERR(priv->clk); 2445 goto out_release; 2446 } 2447 2448 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2449 if (IS_ERR(priv->refclk)) { 2450 error = PTR_ERR(priv->refclk); 2451 goto out_release; 2452 } 2453 clk_prepare_enable(priv->refclk); 2454 2455 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2456 ndev->min_mtu = ETH_MIN_MTU; 2457 2458 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2459 * Use two descriptor to handle such situation. First descriptor to 2460 * handle aligned data buffer and second descriptor to handle the 2461 * overflow data because of alignment. 2462 */ 2463 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2464 2465 /* Set function */ 2466 ndev->netdev_ops = &ravb_netdev_ops; 2467 ndev->ethtool_ops = &ravb_ethtool_ops; 2468 2469 /* Set AVB config mode */ 2470 ravb_set_config_mode(ndev); 2471 2472 if (info->gptp || info->ccc_gac) { 2473 /* Set GTI value */ 2474 error = ravb_set_gti(ndev); 2475 if (error) 2476 goto out_disable_refclk; 2477 2478 /* Request GTI loading */ 2479 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2480 } 2481 2482 if (info->internal_delay) { 2483 ravb_parse_delay_mode(np, ndev); 2484 ravb_set_delay_mode(ndev); 2485 } 2486 2487 /* Allocate descriptor base address table */ 2488 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2489 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2490 &priv->desc_bat_dma, GFP_KERNEL); 2491 if (!priv->desc_bat) { 2492 dev_err(&pdev->dev, 2493 "Cannot allocate desc base address table (size %d bytes)\n", 2494 priv->desc_bat_size); 2495 error = -ENOMEM; 2496 goto out_disable_refclk; 2497 } 2498 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2499 priv->desc_bat[q].die_dt = DT_EOS; 2500 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2501 2502 /* Initialise HW timestamp list */ 2503 INIT_LIST_HEAD(&priv->ts_skb_list); 2504 2505 /* Initialise PTP Clock driver */ 2506 if (info->ccc_gac) 2507 ravb_ptp_init(ndev, pdev); 2508 2509 /* Debug message level */ 2510 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2511 2512 /* Read and set MAC address */ 2513 ravb_read_mac_address(np, ndev); 2514 if (!is_valid_ether_addr(ndev->dev_addr)) { 2515 dev_warn(&pdev->dev, 2516 "no valid MAC address supplied, using a random one\n"); 2517 eth_hw_addr_random(ndev); 2518 } 2519 2520 /* MDIO bus init */ 2521 error = ravb_mdio_init(priv); 2522 if (error) { 2523 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2524 goto out_dma_free; 2525 } 2526 2527 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2528 if (info->nc_queue) 2529 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2530 2531 /* Network device register */ 2532 error = register_netdev(ndev); 2533 if (error) 2534 goto out_napi_del; 2535 2536 device_set_wakeup_capable(&pdev->dev, 1); 2537 2538 /* Print device information */ 2539 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2540 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2541 2542 platform_set_drvdata(pdev, ndev); 2543 2544 return 0; 2545 2546 out_napi_del: 2547 if (info->nc_queue) 2548 netif_napi_del(&priv->napi[RAVB_NC]); 2549 2550 netif_napi_del(&priv->napi[RAVB_BE]); 2551 ravb_mdio_release(priv); 2552 out_dma_free: 2553 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2554 priv->desc_bat_dma); 2555 2556 /* Stop PTP Clock driver */ 2557 if (info->ccc_gac) 2558 ravb_ptp_stop(ndev); 2559 out_disable_refclk: 2560 clk_disable_unprepare(priv->refclk); 2561 out_release: 2562 free_netdev(ndev); 2563 2564 pm_runtime_put(&pdev->dev); 2565 pm_runtime_disable(&pdev->dev); 2566 reset_control_assert(rstc); 2567 return error; 2568 } 2569 2570 static int ravb_remove(struct platform_device *pdev) 2571 { 2572 struct net_device *ndev = platform_get_drvdata(pdev); 2573 struct ravb_private *priv = netdev_priv(ndev); 2574 const struct ravb_hw_info *info = priv->info; 2575 2576 /* Stop PTP Clock driver */ 2577 if (info->ccc_gac) 2578 ravb_ptp_stop(ndev); 2579 2580 clk_disable_unprepare(priv->refclk); 2581 2582 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2583 priv->desc_bat_dma); 2584 /* Set reset mode */ 2585 ravb_write(ndev, CCC_OPC_RESET, CCC); 2586 pm_runtime_put_sync(&pdev->dev); 2587 unregister_netdev(ndev); 2588 if (info->nc_queue) 2589 netif_napi_del(&priv->napi[RAVB_NC]); 2590 netif_napi_del(&priv->napi[RAVB_BE]); 2591 ravb_mdio_release(priv); 2592 pm_runtime_disable(&pdev->dev); 2593 reset_control_assert(priv->rstc); 2594 free_netdev(ndev); 2595 platform_set_drvdata(pdev, NULL); 2596 2597 return 0; 2598 } 2599 2600 static int ravb_wol_setup(struct net_device *ndev) 2601 { 2602 struct ravb_private *priv = netdev_priv(ndev); 2603 const struct ravb_hw_info *info = priv->info; 2604 2605 /* Disable interrupts by clearing the interrupt masks. */ 2606 ravb_write(ndev, 0, RIC0); 2607 ravb_write(ndev, 0, RIC2); 2608 ravb_write(ndev, 0, TIC); 2609 2610 /* Only allow ECI interrupts */ 2611 synchronize_irq(priv->emac_irq); 2612 if (info->nc_queue) 2613 napi_disable(&priv->napi[RAVB_NC]); 2614 napi_disable(&priv->napi[RAVB_BE]); 2615 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2616 2617 /* Enable MagicPacket */ 2618 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2619 2620 return enable_irq_wake(priv->emac_irq); 2621 } 2622 2623 static int ravb_wol_restore(struct net_device *ndev) 2624 { 2625 struct ravb_private *priv = netdev_priv(ndev); 2626 const struct ravb_hw_info *info = priv->info; 2627 int ret; 2628 2629 if (info->nc_queue) 2630 napi_enable(&priv->napi[RAVB_NC]); 2631 napi_enable(&priv->napi[RAVB_BE]); 2632 2633 /* Disable MagicPacket */ 2634 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2635 2636 ret = ravb_close(ndev); 2637 if (ret < 0) 2638 return ret; 2639 2640 return disable_irq_wake(priv->emac_irq); 2641 } 2642 2643 static int __maybe_unused ravb_suspend(struct device *dev) 2644 { 2645 struct net_device *ndev = dev_get_drvdata(dev); 2646 struct ravb_private *priv = netdev_priv(ndev); 2647 int ret; 2648 2649 if (!netif_running(ndev)) 2650 return 0; 2651 2652 netif_device_detach(ndev); 2653 2654 if (priv->wol_enabled) 2655 ret = ravb_wol_setup(ndev); 2656 else 2657 ret = ravb_close(ndev); 2658 2659 return ret; 2660 } 2661 2662 static int __maybe_unused ravb_resume(struct device *dev) 2663 { 2664 struct net_device *ndev = dev_get_drvdata(dev); 2665 struct ravb_private *priv = netdev_priv(ndev); 2666 const struct ravb_hw_info *info = priv->info; 2667 int ret = 0; 2668 2669 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2670 if (priv->wol_enabled) 2671 ravb_write(ndev, CCC_OPC_RESET, CCC); 2672 2673 /* All register have been reset to default values. 2674 * Restore all registers which where setup at probe time and 2675 * reopen device if it was running before system suspended. 2676 */ 2677 2678 /* Set AVB config mode */ 2679 ravb_set_config_mode(ndev); 2680 2681 if (info->gptp || info->ccc_gac) { 2682 /* Set GTI value */ 2683 ret = ravb_set_gti(ndev); 2684 if (ret) 2685 return ret; 2686 2687 /* Request GTI loading */ 2688 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2689 } 2690 2691 if (info->internal_delay) 2692 ravb_set_delay_mode(ndev); 2693 2694 /* Restore descriptor base address table */ 2695 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2696 2697 if (netif_running(ndev)) { 2698 if (priv->wol_enabled) { 2699 ret = ravb_wol_restore(ndev); 2700 if (ret) 2701 return ret; 2702 } 2703 ret = ravb_open(ndev); 2704 if (ret < 0) 2705 return ret; 2706 netif_device_attach(ndev); 2707 } 2708 2709 return ret; 2710 } 2711 2712 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2713 { 2714 /* Runtime PM callback shared between ->runtime_suspend() 2715 * and ->runtime_resume(). Simply returns success. 2716 * 2717 * This driver re-initializes all registers after 2718 * pm_runtime_get_sync() anyway so there is no need 2719 * to save and restore registers here. 2720 */ 2721 return 0; 2722 } 2723 2724 static const struct dev_pm_ops ravb_dev_pm_ops = { 2725 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2726 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2727 }; 2728 2729 static struct platform_driver ravb_driver = { 2730 .probe = ravb_probe, 2731 .remove = ravb_remove, 2732 .driver = { 2733 .name = "ravb", 2734 .pm = &ravb_dev_pm_ops, 2735 .of_match_table = ravb_match_table, 2736 }, 2737 }; 2738 2739 module_platform_driver(ravb_driver); 2740 2741 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2742 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2743 MODULE_LICENSE("GPL v2"); 2744