1 /* Renesas Ethernet AVB device driver 2 * 3 * Copyright (C) 2014-2015 Renesas Electronics Corporation 4 * Copyright (C) 2015 Renesas Solutions Corp. 5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 6 * 7 * Based on the SuperH Ethernet driver 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License version 2, 11 * as published by the Free Software Foundation. 12 */ 13 14 #include <linux/cache.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/err.h> 19 #include <linux/etherdevice.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/kernel.h> 23 #include <linux/list.h> 24 #include <linux/module.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_mdio.h> 30 #include <linux/of_net.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/slab.h> 33 #include <linux/spinlock.h> 34 #include <linux/sys_soc.h> 35 36 #include <asm/div64.h> 37 38 #include "ravb.h" 39 40 #define RAVB_DEF_MSG_ENABLE \ 41 (NETIF_MSG_LINK | \ 42 NETIF_MSG_TIMER | \ 43 NETIF_MSG_RX_ERR | \ 44 NETIF_MSG_TX_ERR) 45 46 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 47 "ch0", /* RAVB_BE */ 48 "ch1", /* RAVB_NC */ 49 }; 50 51 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 52 "ch18", /* RAVB_BE */ 53 "ch19", /* RAVB_NC */ 54 }; 55 56 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 57 u32 set) 58 { 59 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 60 } 61 62 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 63 { 64 int i; 65 66 for (i = 0; i < 10000; i++) { 67 if ((ravb_read(ndev, reg) & mask) == value) 68 return 0; 69 udelay(10); 70 } 71 return -ETIMEDOUT; 72 } 73 74 static int ravb_config(struct net_device *ndev) 75 { 76 int error; 77 78 /* Set config mode */ 79 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 80 /* Check if the operating mode is changed to the config mode */ 81 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 82 if (error) 83 netdev_err(ndev, "failed to switch device to config mode\n"); 84 85 return error; 86 } 87 88 static void ravb_set_duplex(struct net_device *ndev) 89 { 90 struct ravb_private *priv = netdev_priv(ndev); 91 92 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0); 93 } 94 95 static void ravb_set_rate(struct net_device *ndev) 96 { 97 struct ravb_private *priv = netdev_priv(ndev); 98 99 switch (priv->speed) { 100 case 100: /* 100BASE */ 101 ravb_write(ndev, GECMR_SPEED_100, GECMR); 102 break; 103 case 1000: /* 1000BASE */ 104 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 105 break; 106 } 107 } 108 109 static void ravb_set_buffer_align(struct sk_buff *skb) 110 { 111 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 112 113 if (reserve) 114 skb_reserve(skb, RAVB_ALIGN - reserve); 115 } 116 117 /* Get MAC address from the MAC address registers 118 * 119 * Ethernet AVB device doesn't have ROM for MAC address. 120 * This function gets the MAC address that was used by a bootloader. 121 */ 122 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 123 { 124 if (mac) { 125 ether_addr_copy(ndev->dev_addr, mac); 126 } else { 127 u32 mahr = ravb_read(ndev, MAHR); 128 u32 malr = ravb_read(ndev, MALR); 129 130 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 131 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 132 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 133 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 134 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 135 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 136 } 137 } 138 139 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 140 { 141 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 142 mdiobb); 143 144 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 145 } 146 147 /* MDC pin control */ 148 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 149 { 150 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 151 } 152 153 /* Data I/O pin control */ 154 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 155 { 156 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 157 } 158 159 /* Set data bit */ 160 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 161 { 162 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 163 } 164 165 /* Get data bit */ 166 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 167 { 168 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 169 mdiobb); 170 171 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 172 } 173 174 /* MDIO bus control struct */ 175 static struct mdiobb_ops bb_ops = { 176 .owner = THIS_MODULE, 177 .set_mdc = ravb_set_mdc, 178 .set_mdio_dir = ravb_set_mdio_dir, 179 .set_mdio_data = ravb_set_mdio_data, 180 .get_mdio_data = ravb_get_mdio_data, 181 }; 182 183 /* Free TX skb function for AVB-IP */ 184 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 185 { 186 struct ravb_private *priv = netdev_priv(ndev); 187 struct net_device_stats *stats = &priv->stats[q]; 188 struct ravb_tx_desc *desc; 189 int free_num = 0; 190 int entry; 191 u32 size; 192 193 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 194 bool txed; 195 196 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 197 NUM_TX_DESC); 198 desc = &priv->tx_ring[q][entry]; 199 txed = desc->die_dt == DT_FEMPTY; 200 if (free_txed_only && !txed) 201 break; 202 /* Descriptor type must be checked before all other reads */ 203 dma_rmb(); 204 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 205 /* Free the original skb. */ 206 if (priv->tx_skb[q][entry / NUM_TX_DESC]) { 207 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 208 size, DMA_TO_DEVICE); 209 /* Last packet descriptor? */ 210 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { 211 entry /= NUM_TX_DESC; 212 dev_kfree_skb_any(priv->tx_skb[q][entry]); 213 priv->tx_skb[q][entry] = NULL; 214 if (txed) 215 stats->tx_packets++; 216 } 217 free_num++; 218 } 219 if (txed) 220 stats->tx_bytes += size; 221 desc->die_dt = DT_EEMPTY; 222 } 223 return free_num; 224 } 225 226 /* Free skb's and DMA buffers for Ethernet AVB */ 227 static void ravb_ring_free(struct net_device *ndev, int q) 228 { 229 struct ravb_private *priv = netdev_priv(ndev); 230 int ring_size; 231 int i; 232 233 if (priv->rx_ring[q]) { 234 for (i = 0; i < priv->num_rx_ring[q]; i++) { 235 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 236 237 if (!dma_mapping_error(ndev->dev.parent, 238 le32_to_cpu(desc->dptr))) 239 dma_unmap_single(ndev->dev.parent, 240 le32_to_cpu(desc->dptr), 241 PKT_BUF_SZ, 242 DMA_FROM_DEVICE); 243 } 244 ring_size = sizeof(struct ravb_ex_rx_desc) * 245 (priv->num_rx_ring[q] + 1); 246 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 247 priv->rx_desc_dma[q]); 248 priv->rx_ring[q] = NULL; 249 } 250 251 if (priv->tx_ring[q]) { 252 ravb_tx_free(ndev, q, false); 253 254 ring_size = sizeof(struct ravb_tx_desc) * 255 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 256 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 257 priv->tx_desc_dma[q]); 258 priv->tx_ring[q] = NULL; 259 } 260 261 /* Free RX skb ringbuffer */ 262 if (priv->rx_skb[q]) { 263 for (i = 0; i < priv->num_rx_ring[q]; i++) 264 dev_kfree_skb(priv->rx_skb[q][i]); 265 } 266 kfree(priv->rx_skb[q]); 267 priv->rx_skb[q] = NULL; 268 269 /* Free aligned TX buffers */ 270 kfree(priv->tx_align[q]); 271 priv->tx_align[q] = NULL; 272 273 /* Free TX skb ringbuffer. 274 * SKBs are freed by ravb_tx_free() call above. 275 */ 276 kfree(priv->tx_skb[q]); 277 priv->tx_skb[q] = NULL; 278 } 279 280 /* Format skb and descriptor buffer for Ethernet AVB */ 281 static void ravb_ring_format(struct net_device *ndev, int q) 282 { 283 struct ravb_private *priv = netdev_priv(ndev); 284 struct ravb_ex_rx_desc *rx_desc; 285 struct ravb_tx_desc *tx_desc; 286 struct ravb_desc *desc; 287 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 288 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 289 NUM_TX_DESC; 290 dma_addr_t dma_addr; 291 int i; 292 293 priv->cur_rx[q] = 0; 294 priv->cur_tx[q] = 0; 295 priv->dirty_rx[q] = 0; 296 priv->dirty_tx[q] = 0; 297 298 memset(priv->rx_ring[q], 0, rx_ring_size); 299 /* Build RX ring buffer */ 300 for (i = 0; i < priv->num_rx_ring[q]; i++) { 301 /* RX descriptor */ 302 rx_desc = &priv->rx_ring[q][i]; 303 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ); 304 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 305 PKT_BUF_SZ, 306 DMA_FROM_DEVICE); 307 /* We just set the data size to 0 for a failed mapping which 308 * should prevent DMA from happening... 309 */ 310 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 311 rx_desc->ds_cc = cpu_to_le16(0); 312 rx_desc->dptr = cpu_to_le32(dma_addr); 313 rx_desc->die_dt = DT_FEMPTY; 314 } 315 rx_desc = &priv->rx_ring[q][i]; 316 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 317 rx_desc->die_dt = DT_LINKFIX; /* type */ 318 319 memset(priv->tx_ring[q], 0, tx_ring_size); 320 /* Build TX ring buffer */ 321 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 322 i++, tx_desc++) { 323 tx_desc->die_dt = DT_EEMPTY; 324 tx_desc++; 325 tx_desc->die_dt = DT_EEMPTY; 326 } 327 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 328 tx_desc->die_dt = DT_LINKFIX; /* type */ 329 330 /* RX descriptor base address for best effort */ 331 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 332 desc->die_dt = DT_LINKFIX; /* type */ 333 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 334 335 /* TX descriptor base address for best effort */ 336 desc = &priv->desc_bat[q]; 337 desc->die_dt = DT_LINKFIX; /* type */ 338 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 339 } 340 341 /* Init skb and descriptor buffer for Ethernet AVB */ 342 static int ravb_ring_init(struct net_device *ndev, int q) 343 { 344 struct ravb_private *priv = netdev_priv(ndev); 345 struct sk_buff *skb; 346 int ring_size; 347 int i; 348 349 /* Allocate RX and TX skb rings */ 350 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 351 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 352 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 353 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 354 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 355 goto error; 356 357 for (i = 0; i < priv->num_rx_ring[q]; i++) { 358 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1); 359 if (!skb) 360 goto error; 361 ravb_set_buffer_align(skb); 362 priv->rx_skb[q][i] = skb; 363 } 364 365 /* Allocate rings for the aligned buffers */ 366 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 367 DPTR_ALIGN - 1, GFP_KERNEL); 368 if (!priv->tx_align[q]) 369 goto error; 370 371 /* Allocate all RX descriptors. */ 372 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 373 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 374 &priv->rx_desc_dma[q], 375 GFP_KERNEL); 376 if (!priv->rx_ring[q]) 377 goto error; 378 379 priv->dirty_rx[q] = 0; 380 381 /* Allocate all TX descriptors. */ 382 ring_size = sizeof(struct ravb_tx_desc) * 383 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 384 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 385 &priv->tx_desc_dma[q], 386 GFP_KERNEL); 387 if (!priv->tx_ring[q]) 388 goto error; 389 390 return 0; 391 392 error: 393 ravb_ring_free(ndev, q); 394 395 return -ENOMEM; 396 } 397 398 /* E-MAC init function */ 399 static void ravb_emac_init(struct net_device *ndev) 400 { 401 struct ravb_private *priv = netdev_priv(ndev); 402 403 /* Receive frame limit set register */ 404 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 405 406 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 407 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | 408 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 409 ECMR_TE | ECMR_RE, ECMR); 410 411 ravb_set_rate(ndev); 412 413 /* Set MAC address */ 414 ravb_write(ndev, 415 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 416 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 417 ravb_write(ndev, 418 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 419 420 /* E-MAC status register clear */ 421 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 422 423 /* E-MAC interrupt enable register */ 424 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 425 } 426 427 /* Device init function for Ethernet AVB */ 428 static int ravb_dmac_init(struct net_device *ndev) 429 { 430 struct ravb_private *priv = netdev_priv(ndev); 431 int error; 432 433 /* Set CONFIG mode */ 434 error = ravb_config(ndev); 435 if (error) 436 return error; 437 438 error = ravb_ring_init(ndev, RAVB_BE); 439 if (error) 440 return error; 441 error = ravb_ring_init(ndev, RAVB_NC); 442 if (error) { 443 ravb_ring_free(ndev, RAVB_BE); 444 return error; 445 } 446 447 /* Descriptor format */ 448 ravb_ring_format(ndev, RAVB_BE); 449 ravb_ring_format(ndev, RAVB_NC); 450 451 #if defined(__LITTLE_ENDIAN) 452 ravb_modify(ndev, CCC, CCC_BOC, 0); 453 #else 454 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 455 #endif 456 457 /* Set AVB RX */ 458 ravb_write(ndev, 459 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 460 461 /* Set FIFO size */ 462 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 463 464 /* Timestamp enable */ 465 ravb_write(ndev, TCCR_TFEN, TCCR); 466 467 /* Interrupt init: */ 468 if (priv->chip_id == RCAR_GEN3) { 469 /* Clear DIL.DPLx */ 470 ravb_write(ndev, 0, DIL); 471 /* Set queue specific interrupt */ 472 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 473 } 474 /* Frame receive */ 475 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 476 /* Disable FIFO full warning */ 477 ravb_write(ndev, 0, RIC1); 478 /* Receive FIFO full error, descriptor empty */ 479 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 480 /* Frame transmitted, timestamp FIFO updated */ 481 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 482 483 /* Setting the control will start the AVB-DMAC process. */ 484 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 485 486 return 0; 487 } 488 489 static void ravb_get_tx_tstamp(struct net_device *ndev) 490 { 491 struct ravb_private *priv = netdev_priv(ndev); 492 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 493 struct skb_shared_hwtstamps shhwtstamps; 494 struct sk_buff *skb; 495 struct timespec64 ts; 496 u16 tag, tfa_tag; 497 int count; 498 u32 tfa2; 499 500 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 501 while (count--) { 502 tfa2 = ravb_read(ndev, TFA2); 503 tfa_tag = (tfa2 & TFA2_TST) >> 16; 504 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 505 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 506 ravb_read(ndev, TFA1); 507 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 508 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 509 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 510 list) { 511 skb = ts_skb->skb; 512 tag = ts_skb->tag; 513 list_del(&ts_skb->list); 514 kfree(ts_skb); 515 if (tag == tfa_tag) { 516 skb_tstamp_tx(skb, &shhwtstamps); 517 break; 518 } 519 } 520 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 521 } 522 } 523 524 static void ravb_rx_csum(struct sk_buff *skb) 525 { 526 u8 *hw_csum; 527 528 /* The hardware checksum is 2 bytes appended to packet data */ 529 if (unlikely(skb->len < 2)) 530 return; 531 hw_csum = skb_tail_pointer(skb) - 2; 532 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 533 skb->ip_summed = CHECKSUM_COMPLETE; 534 skb_trim(skb, skb->len - 2); 535 } 536 537 /* Packet receive function for Ethernet AVB */ 538 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 539 { 540 struct ravb_private *priv = netdev_priv(ndev); 541 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 542 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 543 priv->cur_rx[q]; 544 struct net_device_stats *stats = &priv->stats[q]; 545 struct ravb_ex_rx_desc *desc; 546 struct sk_buff *skb; 547 dma_addr_t dma_addr; 548 struct timespec64 ts; 549 u8 desc_status; 550 u16 pkt_len; 551 int limit; 552 553 boguscnt = min(boguscnt, *quota); 554 limit = boguscnt; 555 desc = &priv->rx_ring[q][entry]; 556 while (desc->die_dt != DT_FEMPTY) { 557 /* Descriptor type must be checked before all other reads */ 558 dma_rmb(); 559 desc_status = desc->msc; 560 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 561 562 if (--boguscnt < 0) 563 break; 564 565 /* We use 0-byte descriptors to mark the DMA mapping errors */ 566 if (!pkt_len) 567 continue; 568 569 if (desc_status & MSC_MC) 570 stats->multicast++; 571 572 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 573 MSC_CEEF)) { 574 stats->rx_errors++; 575 if (desc_status & MSC_CRC) 576 stats->rx_crc_errors++; 577 if (desc_status & MSC_RFE) 578 stats->rx_frame_errors++; 579 if (desc_status & (MSC_RTLF | MSC_RTSF)) 580 stats->rx_length_errors++; 581 if (desc_status & MSC_CEEF) 582 stats->rx_missed_errors++; 583 } else { 584 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 585 586 skb = priv->rx_skb[q][entry]; 587 priv->rx_skb[q][entry] = NULL; 588 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 589 PKT_BUF_SZ, 590 DMA_FROM_DEVICE); 591 get_ts &= (q == RAVB_NC) ? 592 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 593 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 594 if (get_ts) { 595 struct skb_shared_hwtstamps *shhwtstamps; 596 597 shhwtstamps = skb_hwtstamps(skb); 598 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 599 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 600 32) | le32_to_cpu(desc->ts_sl); 601 ts.tv_nsec = le32_to_cpu(desc->ts_n); 602 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 603 } 604 605 skb_put(skb, pkt_len); 606 skb->protocol = eth_type_trans(skb, ndev); 607 if (ndev->features & NETIF_F_RXCSUM) 608 ravb_rx_csum(skb); 609 napi_gro_receive(&priv->napi[q], skb); 610 stats->rx_packets++; 611 stats->rx_bytes += pkt_len; 612 } 613 614 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 615 desc = &priv->rx_ring[q][entry]; 616 } 617 618 /* Refill the RX ring buffers. */ 619 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 620 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 621 desc = &priv->rx_ring[q][entry]; 622 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ); 623 624 if (!priv->rx_skb[q][entry]) { 625 skb = netdev_alloc_skb(ndev, 626 PKT_BUF_SZ + RAVB_ALIGN - 1); 627 if (!skb) 628 break; /* Better luck next round. */ 629 ravb_set_buffer_align(skb); 630 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 631 le16_to_cpu(desc->ds_cc), 632 DMA_FROM_DEVICE); 633 skb_checksum_none_assert(skb); 634 /* We just set the data size to 0 for a failed mapping 635 * which should prevent DMA from happening... 636 */ 637 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 638 desc->ds_cc = cpu_to_le16(0); 639 desc->dptr = cpu_to_le32(dma_addr); 640 priv->rx_skb[q][entry] = skb; 641 } 642 /* Descriptor type must be set after all the above writes */ 643 dma_wmb(); 644 desc->die_dt = DT_FEMPTY; 645 } 646 647 *quota -= limit - (++boguscnt); 648 649 return boguscnt <= 0; 650 } 651 652 static void ravb_rcv_snd_disable(struct net_device *ndev) 653 { 654 /* Disable TX and RX */ 655 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 656 } 657 658 static void ravb_rcv_snd_enable(struct net_device *ndev) 659 { 660 /* Enable TX and RX */ 661 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 662 } 663 664 /* function for waiting dma process finished */ 665 static int ravb_stop_dma(struct net_device *ndev) 666 { 667 int error; 668 669 /* Wait for stopping the hardware TX process */ 670 error = ravb_wait(ndev, TCCR, 671 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 672 if (error) 673 return error; 674 675 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 676 0); 677 if (error) 678 return error; 679 680 /* Stop the E-MAC's RX/TX processes. */ 681 ravb_rcv_snd_disable(ndev); 682 683 /* Wait for stopping the RX DMA process */ 684 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 685 if (error) 686 return error; 687 688 /* Stop AVB-DMAC process */ 689 return ravb_config(ndev); 690 } 691 692 /* E-MAC interrupt handler */ 693 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 694 { 695 struct ravb_private *priv = netdev_priv(ndev); 696 u32 ecsr, psr; 697 698 ecsr = ravb_read(ndev, ECSR); 699 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 700 701 if (ecsr & ECSR_MPD) 702 pm_wakeup_event(&priv->pdev->dev, 0); 703 if (ecsr & ECSR_ICD) 704 ndev->stats.tx_carrier_errors++; 705 if (ecsr & ECSR_LCHNG) { 706 /* Link changed */ 707 if (priv->no_avb_link) 708 return; 709 psr = ravb_read(ndev, PSR); 710 if (priv->avb_link_active_low) 711 psr ^= PSR_LMON; 712 if (!(psr & PSR_LMON)) { 713 /* DIsable RX and TX */ 714 ravb_rcv_snd_disable(ndev); 715 } else { 716 /* Enable RX and TX */ 717 ravb_rcv_snd_enable(ndev); 718 } 719 } 720 } 721 722 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 723 { 724 struct net_device *ndev = dev_id; 725 struct ravb_private *priv = netdev_priv(ndev); 726 727 spin_lock(&priv->lock); 728 ravb_emac_interrupt_unlocked(ndev); 729 mmiowb(); 730 spin_unlock(&priv->lock); 731 return IRQ_HANDLED; 732 } 733 734 /* Error interrupt handler */ 735 static void ravb_error_interrupt(struct net_device *ndev) 736 { 737 struct ravb_private *priv = netdev_priv(ndev); 738 u32 eis, ris2; 739 740 eis = ravb_read(ndev, EIS); 741 ravb_write(ndev, ~EIS_QFS, EIS); 742 if (eis & EIS_QFS) { 743 ris2 = ravb_read(ndev, RIS2); 744 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); 745 746 /* Receive Descriptor Empty int */ 747 if (ris2 & RIS2_QFF0) 748 priv->stats[RAVB_BE].rx_over_errors++; 749 750 /* Receive Descriptor Empty int */ 751 if (ris2 & RIS2_QFF1) 752 priv->stats[RAVB_NC].rx_over_errors++; 753 754 /* Receive FIFO Overflow int */ 755 if (ris2 & RIS2_RFFF) 756 priv->rx_fifo_errors++; 757 } 758 } 759 760 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 761 { 762 struct ravb_private *priv = netdev_priv(ndev); 763 u32 ris0 = ravb_read(ndev, RIS0); 764 u32 ric0 = ravb_read(ndev, RIC0); 765 u32 tis = ravb_read(ndev, TIS); 766 u32 tic = ravb_read(ndev, TIC); 767 768 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 769 if (napi_schedule_prep(&priv->napi[q])) { 770 /* Mask RX and TX interrupts */ 771 if (priv->chip_id == RCAR_GEN2) { 772 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 773 ravb_write(ndev, tic & ~BIT(q), TIC); 774 } else { 775 ravb_write(ndev, BIT(q), RID0); 776 ravb_write(ndev, BIT(q), TID); 777 } 778 __napi_schedule(&priv->napi[q]); 779 } else { 780 netdev_warn(ndev, 781 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 782 ris0, ric0); 783 netdev_warn(ndev, 784 " tx status 0x%08x, tx mask 0x%08x.\n", 785 tis, tic); 786 } 787 return true; 788 } 789 return false; 790 } 791 792 static bool ravb_timestamp_interrupt(struct net_device *ndev) 793 { 794 u32 tis = ravb_read(ndev, TIS); 795 796 if (tis & TIS_TFUF) { 797 ravb_write(ndev, ~TIS_TFUF, TIS); 798 ravb_get_tx_tstamp(ndev); 799 return true; 800 } 801 return false; 802 } 803 804 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 805 { 806 struct net_device *ndev = dev_id; 807 struct ravb_private *priv = netdev_priv(ndev); 808 irqreturn_t result = IRQ_NONE; 809 u32 iss; 810 811 spin_lock(&priv->lock); 812 /* Get interrupt status */ 813 iss = ravb_read(ndev, ISS); 814 815 /* Received and transmitted interrupts */ 816 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 817 int q; 818 819 /* Timestamp updated */ 820 if (ravb_timestamp_interrupt(ndev)) 821 result = IRQ_HANDLED; 822 823 /* Network control and best effort queue RX/TX */ 824 for (q = RAVB_NC; q >= RAVB_BE; q--) { 825 if (ravb_queue_interrupt(ndev, q)) 826 result = IRQ_HANDLED; 827 } 828 } 829 830 /* E-MAC status summary */ 831 if (iss & ISS_MS) { 832 ravb_emac_interrupt_unlocked(ndev); 833 result = IRQ_HANDLED; 834 } 835 836 /* Error status summary */ 837 if (iss & ISS_ES) { 838 ravb_error_interrupt(ndev); 839 result = IRQ_HANDLED; 840 } 841 842 /* gPTP interrupt status summary */ 843 if (iss & ISS_CGIS) { 844 ravb_ptp_interrupt(ndev); 845 result = IRQ_HANDLED; 846 } 847 848 mmiowb(); 849 spin_unlock(&priv->lock); 850 return result; 851 } 852 853 /* Timestamp/Error/gPTP interrupt handler */ 854 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 855 { 856 struct net_device *ndev = dev_id; 857 struct ravb_private *priv = netdev_priv(ndev); 858 irqreturn_t result = IRQ_NONE; 859 u32 iss; 860 861 spin_lock(&priv->lock); 862 /* Get interrupt status */ 863 iss = ravb_read(ndev, ISS); 864 865 /* Timestamp updated */ 866 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 867 result = IRQ_HANDLED; 868 869 /* Error status summary */ 870 if (iss & ISS_ES) { 871 ravb_error_interrupt(ndev); 872 result = IRQ_HANDLED; 873 } 874 875 /* gPTP interrupt status summary */ 876 if (iss & ISS_CGIS) { 877 ravb_ptp_interrupt(ndev); 878 result = IRQ_HANDLED; 879 } 880 881 mmiowb(); 882 spin_unlock(&priv->lock); 883 return result; 884 } 885 886 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 887 { 888 struct net_device *ndev = dev_id; 889 struct ravb_private *priv = netdev_priv(ndev); 890 irqreturn_t result = IRQ_NONE; 891 892 spin_lock(&priv->lock); 893 894 /* Network control/Best effort queue RX/TX */ 895 if (ravb_queue_interrupt(ndev, q)) 896 result = IRQ_HANDLED; 897 898 mmiowb(); 899 spin_unlock(&priv->lock); 900 return result; 901 } 902 903 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 904 { 905 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 906 } 907 908 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 909 { 910 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 911 } 912 913 static int ravb_poll(struct napi_struct *napi, int budget) 914 { 915 struct net_device *ndev = napi->dev; 916 struct ravb_private *priv = netdev_priv(ndev); 917 unsigned long flags; 918 int q = napi - priv->napi; 919 int mask = BIT(q); 920 int quota = budget; 921 u32 ris0, tis; 922 923 for (;;) { 924 tis = ravb_read(ndev, TIS); 925 ris0 = ravb_read(ndev, RIS0); 926 if (!((ris0 & mask) || (tis & mask))) 927 break; 928 929 /* Processing RX Descriptor Ring */ 930 if (ris0 & mask) { 931 /* Clear RX interrupt */ 932 ravb_write(ndev, ~mask, RIS0); 933 if (ravb_rx(ndev, "a, q)) 934 goto out; 935 } 936 /* Processing TX Descriptor Ring */ 937 if (tis & mask) { 938 spin_lock_irqsave(&priv->lock, flags); 939 /* Clear TX interrupt */ 940 ravb_write(ndev, ~mask, TIS); 941 ravb_tx_free(ndev, q, true); 942 netif_wake_subqueue(ndev, q); 943 mmiowb(); 944 spin_unlock_irqrestore(&priv->lock, flags); 945 } 946 } 947 948 napi_complete(napi); 949 950 /* Re-enable RX/TX interrupts */ 951 spin_lock_irqsave(&priv->lock, flags); 952 if (priv->chip_id == RCAR_GEN2) { 953 ravb_modify(ndev, RIC0, mask, mask); 954 ravb_modify(ndev, TIC, mask, mask); 955 } else { 956 ravb_write(ndev, mask, RIE0); 957 ravb_write(ndev, mask, TIE); 958 } 959 mmiowb(); 960 spin_unlock_irqrestore(&priv->lock, flags); 961 962 /* Receive error message handling */ 963 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 964 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 965 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 966 ndev->stats.rx_over_errors = priv->rx_over_errors; 967 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 968 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 969 out: 970 return budget - quota; 971 } 972 973 /* PHY state control function */ 974 static void ravb_adjust_link(struct net_device *ndev) 975 { 976 struct ravb_private *priv = netdev_priv(ndev); 977 struct phy_device *phydev = ndev->phydev; 978 bool new_state = false; 979 980 if (phydev->link) { 981 if (phydev->duplex != priv->duplex) { 982 new_state = true; 983 priv->duplex = phydev->duplex; 984 ravb_set_duplex(ndev); 985 } 986 987 if (phydev->speed != priv->speed) { 988 new_state = true; 989 priv->speed = phydev->speed; 990 ravb_set_rate(ndev); 991 } 992 if (!priv->link) { 993 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 994 new_state = true; 995 priv->link = phydev->link; 996 if (priv->no_avb_link) 997 ravb_rcv_snd_enable(ndev); 998 } 999 } else if (priv->link) { 1000 new_state = true; 1001 priv->link = 0; 1002 priv->speed = 0; 1003 priv->duplex = -1; 1004 if (priv->no_avb_link) 1005 ravb_rcv_snd_disable(ndev); 1006 } 1007 1008 if (new_state && netif_msg_link(priv)) 1009 phy_print_status(phydev); 1010 } 1011 1012 static const struct soc_device_attribute r8a7795es10[] = { 1013 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1014 { /* sentinel */ } 1015 }; 1016 1017 /* PHY init function */ 1018 static int ravb_phy_init(struct net_device *ndev) 1019 { 1020 struct device_node *np = ndev->dev.parent->of_node; 1021 struct ravb_private *priv = netdev_priv(ndev); 1022 struct phy_device *phydev; 1023 struct device_node *pn; 1024 int err; 1025 1026 priv->link = 0; 1027 priv->speed = 0; 1028 priv->duplex = -1; 1029 1030 /* Try connecting to PHY */ 1031 pn = of_parse_phandle(np, "phy-handle", 0); 1032 if (!pn) { 1033 /* In the case of a fixed PHY, the DT node associated 1034 * to the PHY is the Ethernet MAC DT node. 1035 */ 1036 if (of_phy_is_fixed_link(np)) { 1037 err = of_phy_register_fixed_link(np); 1038 if (err) 1039 return err; 1040 } 1041 pn = of_node_get(np); 1042 } 1043 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1044 priv->phy_interface); 1045 of_node_put(pn); 1046 if (!phydev) { 1047 netdev_err(ndev, "failed to connect PHY\n"); 1048 err = -ENOENT; 1049 goto err_deregister_fixed_link; 1050 } 1051 1052 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1053 * at this time. 1054 */ 1055 if (soc_device_match(r8a7795es10)) { 1056 err = phy_set_max_speed(phydev, SPEED_100); 1057 if (err) { 1058 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1059 goto err_phy_disconnect; 1060 } 1061 1062 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1063 } 1064 1065 /* 10BASE is not supported */ 1066 phydev->supported &= ~PHY_10BT_FEATURES; 1067 1068 phy_attached_info(phydev); 1069 1070 return 0; 1071 1072 err_phy_disconnect: 1073 phy_disconnect(phydev); 1074 err_deregister_fixed_link: 1075 if (of_phy_is_fixed_link(np)) 1076 of_phy_deregister_fixed_link(np); 1077 1078 return err; 1079 } 1080 1081 /* PHY control start function */ 1082 static int ravb_phy_start(struct net_device *ndev) 1083 { 1084 int error; 1085 1086 error = ravb_phy_init(ndev); 1087 if (error) 1088 return error; 1089 1090 phy_start(ndev->phydev); 1091 1092 return 0; 1093 } 1094 1095 static int ravb_get_link_ksettings(struct net_device *ndev, 1096 struct ethtool_link_ksettings *cmd) 1097 { 1098 struct ravb_private *priv = netdev_priv(ndev); 1099 unsigned long flags; 1100 1101 if (!ndev->phydev) 1102 return -ENODEV; 1103 1104 spin_lock_irqsave(&priv->lock, flags); 1105 phy_ethtool_ksettings_get(ndev->phydev, cmd); 1106 spin_unlock_irqrestore(&priv->lock, flags); 1107 1108 return 0; 1109 } 1110 1111 static int ravb_set_link_ksettings(struct net_device *ndev, 1112 const struct ethtool_link_ksettings *cmd) 1113 { 1114 struct ravb_private *priv = netdev_priv(ndev); 1115 unsigned long flags; 1116 int error; 1117 1118 if (!ndev->phydev) 1119 return -ENODEV; 1120 1121 spin_lock_irqsave(&priv->lock, flags); 1122 1123 /* Disable TX and RX */ 1124 ravb_rcv_snd_disable(ndev); 1125 1126 error = phy_ethtool_ksettings_set(ndev->phydev, cmd); 1127 if (error) 1128 goto error_exit; 1129 1130 if (cmd->base.duplex == DUPLEX_FULL) 1131 priv->duplex = 1; 1132 else 1133 priv->duplex = 0; 1134 1135 ravb_set_duplex(ndev); 1136 1137 error_exit: 1138 mdelay(1); 1139 1140 /* Enable TX and RX */ 1141 ravb_rcv_snd_enable(ndev); 1142 1143 mmiowb(); 1144 spin_unlock_irqrestore(&priv->lock, flags); 1145 1146 return error; 1147 } 1148 1149 static int ravb_nway_reset(struct net_device *ndev) 1150 { 1151 struct ravb_private *priv = netdev_priv(ndev); 1152 int error = -ENODEV; 1153 unsigned long flags; 1154 1155 if (ndev->phydev) { 1156 spin_lock_irqsave(&priv->lock, flags); 1157 error = phy_start_aneg(ndev->phydev); 1158 spin_unlock_irqrestore(&priv->lock, flags); 1159 } 1160 1161 return error; 1162 } 1163 1164 static u32 ravb_get_msglevel(struct net_device *ndev) 1165 { 1166 struct ravb_private *priv = netdev_priv(ndev); 1167 1168 return priv->msg_enable; 1169 } 1170 1171 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1172 { 1173 struct ravb_private *priv = netdev_priv(ndev); 1174 1175 priv->msg_enable = value; 1176 } 1177 1178 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1179 "rx_queue_0_current", 1180 "tx_queue_0_current", 1181 "rx_queue_0_dirty", 1182 "tx_queue_0_dirty", 1183 "rx_queue_0_packets", 1184 "tx_queue_0_packets", 1185 "rx_queue_0_bytes", 1186 "tx_queue_0_bytes", 1187 "rx_queue_0_mcast_packets", 1188 "rx_queue_0_errors", 1189 "rx_queue_0_crc_errors", 1190 "rx_queue_0_frame_errors", 1191 "rx_queue_0_length_errors", 1192 "rx_queue_0_missed_errors", 1193 "rx_queue_0_over_errors", 1194 1195 "rx_queue_1_current", 1196 "tx_queue_1_current", 1197 "rx_queue_1_dirty", 1198 "tx_queue_1_dirty", 1199 "rx_queue_1_packets", 1200 "tx_queue_1_packets", 1201 "rx_queue_1_bytes", 1202 "tx_queue_1_bytes", 1203 "rx_queue_1_mcast_packets", 1204 "rx_queue_1_errors", 1205 "rx_queue_1_crc_errors", 1206 "rx_queue_1_frame_errors", 1207 "rx_queue_1_length_errors", 1208 "rx_queue_1_missed_errors", 1209 "rx_queue_1_over_errors", 1210 }; 1211 1212 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1213 1214 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1215 { 1216 switch (sset) { 1217 case ETH_SS_STATS: 1218 return RAVB_STATS_LEN; 1219 default: 1220 return -EOPNOTSUPP; 1221 } 1222 } 1223 1224 static void ravb_get_ethtool_stats(struct net_device *ndev, 1225 struct ethtool_stats *stats, u64 *data) 1226 { 1227 struct ravb_private *priv = netdev_priv(ndev); 1228 int i = 0; 1229 int q; 1230 1231 /* Device-specific stats */ 1232 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1233 struct net_device_stats *stats = &priv->stats[q]; 1234 1235 data[i++] = priv->cur_rx[q]; 1236 data[i++] = priv->cur_tx[q]; 1237 data[i++] = priv->dirty_rx[q]; 1238 data[i++] = priv->dirty_tx[q]; 1239 data[i++] = stats->rx_packets; 1240 data[i++] = stats->tx_packets; 1241 data[i++] = stats->rx_bytes; 1242 data[i++] = stats->tx_bytes; 1243 data[i++] = stats->multicast; 1244 data[i++] = stats->rx_errors; 1245 data[i++] = stats->rx_crc_errors; 1246 data[i++] = stats->rx_frame_errors; 1247 data[i++] = stats->rx_length_errors; 1248 data[i++] = stats->rx_missed_errors; 1249 data[i++] = stats->rx_over_errors; 1250 } 1251 } 1252 1253 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1254 { 1255 switch (stringset) { 1256 case ETH_SS_STATS: 1257 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1258 break; 1259 } 1260 } 1261 1262 static void ravb_get_ringparam(struct net_device *ndev, 1263 struct ethtool_ringparam *ring) 1264 { 1265 struct ravb_private *priv = netdev_priv(ndev); 1266 1267 ring->rx_max_pending = BE_RX_RING_MAX; 1268 ring->tx_max_pending = BE_TX_RING_MAX; 1269 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1270 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1271 } 1272 1273 static int ravb_set_ringparam(struct net_device *ndev, 1274 struct ethtool_ringparam *ring) 1275 { 1276 struct ravb_private *priv = netdev_priv(ndev); 1277 int error; 1278 1279 if (ring->tx_pending > BE_TX_RING_MAX || 1280 ring->rx_pending > BE_RX_RING_MAX || 1281 ring->tx_pending < BE_TX_RING_MIN || 1282 ring->rx_pending < BE_RX_RING_MIN) 1283 return -EINVAL; 1284 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1285 return -EINVAL; 1286 1287 if (netif_running(ndev)) { 1288 netif_device_detach(ndev); 1289 /* Stop PTP Clock driver */ 1290 if (priv->chip_id == RCAR_GEN2) 1291 ravb_ptp_stop(ndev); 1292 /* Wait for DMA stopping */ 1293 error = ravb_stop_dma(ndev); 1294 if (error) { 1295 netdev_err(ndev, 1296 "cannot set ringparam! Any AVB processes are still running?\n"); 1297 return error; 1298 } 1299 synchronize_irq(ndev->irq); 1300 1301 /* Free all the skb's in the RX queue and the DMA buffers. */ 1302 ravb_ring_free(ndev, RAVB_BE); 1303 ravb_ring_free(ndev, RAVB_NC); 1304 } 1305 1306 /* Set new parameters */ 1307 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1308 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1309 1310 if (netif_running(ndev)) { 1311 error = ravb_dmac_init(ndev); 1312 if (error) { 1313 netdev_err(ndev, 1314 "%s: ravb_dmac_init() failed, error %d\n", 1315 __func__, error); 1316 return error; 1317 } 1318 1319 ravb_emac_init(ndev); 1320 1321 /* Initialise PTP Clock driver */ 1322 if (priv->chip_id == RCAR_GEN2) 1323 ravb_ptp_init(ndev, priv->pdev); 1324 1325 netif_device_attach(ndev); 1326 } 1327 1328 return 0; 1329 } 1330 1331 static int ravb_get_ts_info(struct net_device *ndev, 1332 struct ethtool_ts_info *info) 1333 { 1334 struct ravb_private *priv = netdev_priv(ndev); 1335 1336 info->so_timestamping = 1337 SOF_TIMESTAMPING_TX_SOFTWARE | 1338 SOF_TIMESTAMPING_RX_SOFTWARE | 1339 SOF_TIMESTAMPING_SOFTWARE | 1340 SOF_TIMESTAMPING_TX_HARDWARE | 1341 SOF_TIMESTAMPING_RX_HARDWARE | 1342 SOF_TIMESTAMPING_RAW_HARDWARE; 1343 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1344 info->rx_filters = 1345 (1 << HWTSTAMP_FILTER_NONE) | 1346 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1347 (1 << HWTSTAMP_FILTER_ALL); 1348 info->phc_index = ptp_clock_index(priv->ptp.clock); 1349 1350 return 0; 1351 } 1352 1353 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1354 { 1355 struct ravb_private *priv = netdev_priv(ndev); 1356 1357 wol->supported = WAKE_MAGIC; 1358 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1359 } 1360 1361 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1362 { 1363 struct ravb_private *priv = netdev_priv(ndev); 1364 1365 if (wol->wolopts & ~WAKE_MAGIC) 1366 return -EOPNOTSUPP; 1367 1368 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1369 1370 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1371 1372 return 0; 1373 } 1374 1375 static const struct ethtool_ops ravb_ethtool_ops = { 1376 .nway_reset = ravb_nway_reset, 1377 .get_msglevel = ravb_get_msglevel, 1378 .set_msglevel = ravb_set_msglevel, 1379 .get_link = ethtool_op_get_link, 1380 .get_strings = ravb_get_strings, 1381 .get_ethtool_stats = ravb_get_ethtool_stats, 1382 .get_sset_count = ravb_get_sset_count, 1383 .get_ringparam = ravb_get_ringparam, 1384 .set_ringparam = ravb_set_ringparam, 1385 .get_ts_info = ravb_get_ts_info, 1386 .get_link_ksettings = ravb_get_link_ksettings, 1387 .set_link_ksettings = ravb_set_link_ksettings, 1388 .get_wol = ravb_get_wol, 1389 .set_wol = ravb_set_wol, 1390 }; 1391 1392 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1393 struct net_device *ndev, struct device *dev, 1394 const char *ch) 1395 { 1396 char *name; 1397 int error; 1398 1399 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1400 if (!name) 1401 return -ENOMEM; 1402 error = request_irq(irq, handler, 0, name, ndev); 1403 if (error) 1404 netdev_err(ndev, "cannot request IRQ %s\n", name); 1405 1406 return error; 1407 } 1408 1409 /* Network device open function for Ethernet AVB */ 1410 static int ravb_open(struct net_device *ndev) 1411 { 1412 struct ravb_private *priv = netdev_priv(ndev); 1413 struct platform_device *pdev = priv->pdev; 1414 struct device *dev = &pdev->dev; 1415 int error; 1416 1417 napi_enable(&priv->napi[RAVB_BE]); 1418 napi_enable(&priv->napi[RAVB_NC]); 1419 1420 if (priv->chip_id == RCAR_GEN2) { 1421 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1422 ndev->name, ndev); 1423 if (error) { 1424 netdev_err(ndev, "cannot request IRQ\n"); 1425 goto out_napi_off; 1426 } 1427 } else { 1428 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1429 dev, "ch22:multi"); 1430 if (error) 1431 goto out_napi_off; 1432 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1433 dev, "ch24:emac"); 1434 if (error) 1435 goto out_free_irq; 1436 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1437 ndev, dev, "ch0:rx_be"); 1438 if (error) 1439 goto out_free_irq_emac; 1440 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1441 ndev, dev, "ch18:tx_be"); 1442 if (error) 1443 goto out_free_irq_be_rx; 1444 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1445 ndev, dev, "ch1:rx_nc"); 1446 if (error) 1447 goto out_free_irq_be_tx; 1448 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1449 ndev, dev, "ch19:tx_nc"); 1450 if (error) 1451 goto out_free_irq_nc_rx; 1452 } 1453 1454 /* Device init */ 1455 error = ravb_dmac_init(ndev); 1456 if (error) 1457 goto out_free_irq_nc_tx; 1458 ravb_emac_init(ndev); 1459 1460 /* Initialise PTP Clock driver */ 1461 if (priv->chip_id == RCAR_GEN2) 1462 ravb_ptp_init(ndev, priv->pdev); 1463 1464 netif_tx_start_all_queues(ndev); 1465 1466 /* PHY control start */ 1467 error = ravb_phy_start(ndev); 1468 if (error) 1469 goto out_ptp_stop; 1470 1471 return 0; 1472 1473 out_ptp_stop: 1474 /* Stop PTP Clock driver */ 1475 if (priv->chip_id == RCAR_GEN2) 1476 ravb_ptp_stop(ndev); 1477 out_free_irq_nc_tx: 1478 if (priv->chip_id == RCAR_GEN2) 1479 goto out_free_irq; 1480 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1481 out_free_irq_nc_rx: 1482 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1483 out_free_irq_be_tx: 1484 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1485 out_free_irq_be_rx: 1486 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1487 out_free_irq_emac: 1488 free_irq(priv->emac_irq, ndev); 1489 out_free_irq: 1490 free_irq(ndev->irq, ndev); 1491 out_napi_off: 1492 napi_disable(&priv->napi[RAVB_NC]); 1493 napi_disable(&priv->napi[RAVB_BE]); 1494 return error; 1495 } 1496 1497 /* Timeout function for Ethernet AVB */ 1498 static void ravb_tx_timeout(struct net_device *ndev) 1499 { 1500 struct ravb_private *priv = netdev_priv(ndev); 1501 1502 netif_err(priv, tx_err, ndev, 1503 "transmit timed out, status %08x, resetting...\n", 1504 ravb_read(ndev, ISS)); 1505 1506 /* tx_errors count up */ 1507 ndev->stats.tx_errors++; 1508 1509 schedule_work(&priv->work); 1510 } 1511 1512 static void ravb_tx_timeout_work(struct work_struct *work) 1513 { 1514 struct ravb_private *priv = container_of(work, struct ravb_private, 1515 work); 1516 struct net_device *ndev = priv->ndev; 1517 1518 netif_tx_stop_all_queues(ndev); 1519 1520 /* Stop PTP Clock driver */ 1521 if (priv->chip_id == RCAR_GEN2) 1522 ravb_ptp_stop(ndev); 1523 1524 /* Wait for DMA stopping */ 1525 ravb_stop_dma(ndev); 1526 1527 ravb_ring_free(ndev, RAVB_BE); 1528 ravb_ring_free(ndev, RAVB_NC); 1529 1530 /* Device init */ 1531 ravb_dmac_init(ndev); 1532 ravb_emac_init(ndev); 1533 1534 /* Initialise PTP Clock driver */ 1535 if (priv->chip_id == RCAR_GEN2) 1536 ravb_ptp_init(ndev, priv->pdev); 1537 1538 netif_tx_start_all_queues(ndev); 1539 } 1540 1541 /* Packet transmit function for Ethernet AVB */ 1542 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1543 { 1544 struct ravb_private *priv = netdev_priv(ndev); 1545 u16 q = skb_get_queue_mapping(skb); 1546 struct ravb_tstamp_skb *ts_skb; 1547 struct ravb_tx_desc *desc; 1548 unsigned long flags; 1549 u32 dma_addr; 1550 void *buffer; 1551 u32 entry; 1552 u32 len; 1553 1554 spin_lock_irqsave(&priv->lock, flags); 1555 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1556 NUM_TX_DESC) { 1557 netif_err(priv, tx_queued, ndev, 1558 "still transmitting with the full ring!\n"); 1559 netif_stop_subqueue(ndev, q); 1560 spin_unlock_irqrestore(&priv->lock, flags); 1561 return NETDEV_TX_BUSY; 1562 } 1563 1564 if (skb_put_padto(skb, ETH_ZLEN)) 1565 goto exit; 1566 1567 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); 1568 priv->tx_skb[q][entry / NUM_TX_DESC] = skb; 1569 1570 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1571 entry / NUM_TX_DESC * DPTR_ALIGN; 1572 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1573 /* Zero length DMA descriptors are problematic as they seem to 1574 * terminate DMA transfers. Avoid them by simply using a length of 1575 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN. 1576 * 1577 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of 1578 * data by the call to skb_put_padto() above this is safe with 1579 * respect to both the length of the first DMA descriptor (len) 1580 * overflowing the available data and the length of the second DMA 1581 * descriptor (skb->len - len) being negative. 1582 */ 1583 if (len == 0) 1584 len = DPTR_ALIGN; 1585 1586 memcpy(buffer, skb->data, len); 1587 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1588 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1589 goto drop; 1590 1591 desc = &priv->tx_ring[q][entry]; 1592 desc->ds_tagl = cpu_to_le16(len); 1593 desc->dptr = cpu_to_le32(dma_addr); 1594 1595 buffer = skb->data + len; 1596 len = skb->len - len; 1597 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1598 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1599 goto unmap; 1600 1601 desc++; 1602 desc->ds_tagl = cpu_to_le16(len); 1603 desc->dptr = cpu_to_le32(dma_addr); 1604 1605 /* TX timestamp required */ 1606 if (q == RAVB_NC) { 1607 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1608 if (!ts_skb) { 1609 desc--; 1610 dma_unmap_single(ndev->dev.parent, dma_addr, len, 1611 DMA_TO_DEVICE); 1612 goto unmap; 1613 } 1614 ts_skb->skb = skb; 1615 ts_skb->tag = priv->ts_skb_tag++; 1616 priv->ts_skb_tag &= 0x3ff; 1617 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1618 1619 /* TAG and timestamp required flag */ 1620 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1621 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1622 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12); 1623 } 1624 1625 skb_tx_timestamp(skb); 1626 /* Descriptor type must be set after all the above writes */ 1627 dma_wmb(); 1628 desc->die_dt = DT_FEND; 1629 desc--; 1630 desc->die_dt = DT_FSTART; 1631 1632 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1633 1634 priv->cur_tx[q] += NUM_TX_DESC; 1635 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1636 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && 1637 !ravb_tx_free(ndev, q, true)) 1638 netif_stop_subqueue(ndev, q); 1639 1640 exit: 1641 mmiowb(); 1642 spin_unlock_irqrestore(&priv->lock, flags); 1643 return NETDEV_TX_OK; 1644 1645 unmap: 1646 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1647 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1648 drop: 1649 dev_kfree_skb_any(skb); 1650 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; 1651 goto exit; 1652 } 1653 1654 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1655 void *accel_priv, select_queue_fallback_t fallback) 1656 { 1657 /* If skb needs TX timestamp, it is handled in network control queue */ 1658 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1659 RAVB_BE; 1660 1661 } 1662 1663 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1664 { 1665 struct ravb_private *priv = netdev_priv(ndev); 1666 struct net_device_stats *nstats, *stats0, *stats1; 1667 1668 nstats = &ndev->stats; 1669 stats0 = &priv->stats[RAVB_BE]; 1670 stats1 = &priv->stats[RAVB_NC]; 1671 1672 nstats->tx_dropped += ravb_read(ndev, TROCR); 1673 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1674 nstats->collisions += ravb_read(ndev, CDCR); 1675 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1676 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1677 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1678 1679 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1680 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1681 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1682 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1683 1684 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1685 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1686 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1687 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1688 nstats->multicast = stats0->multicast + stats1->multicast; 1689 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1690 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1691 nstats->rx_frame_errors = 1692 stats0->rx_frame_errors + stats1->rx_frame_errors; 1693 nstats->rx_length_errors = 1694 stats0->rx_length_errors + stats1->rx_length_errors; 1695 nstats->rx_missed_errors = 1696 stats0->rx_missed_errors + stats1->rx_missed_errors; 1697 nstats->rx_over_errors = 1698 stats0->rx_over_errors + stats1->rx_over_errors; 1699 1700 return nstats; 1701 } 1702 1703 /* Update promiscuous bit */ 1704 static void ravb_set_rx_mode(struct net_device *ndev) 1705 { 1706 struct ravb_private *priv = netdev_priv(ndev); 1707 unsigned long flags; 1708 1709 spin_lock_irqsave(&priv->lock, flags); 1710 ravb_modify(ndev, ECMR, ECMR_PRM, 1711 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1712 mmiowb(); 1713 spin_unlock_irqrestore(&priv->lock, flags); 1714 } 1715 1716 /* Device close function for Ethernet AVB */ 1717 static int ravb_close(struct net_device *ndev) 1718 { 1719 struct device_node *np = ndev->dev.parent->of_node; 1720 struct ravb_private *priv = netdev_priv(ndev); 1721 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1722 1723 netif_tx_stop_all_queues(ndev); 1724 1725 /* Disable interrupts by clearing the interrupt masks. */ 1726 ravb_write(ndev, 0, RIC0); 1727 ravb_write(ndev, 0, RIC2); 1728 ravb_write(ndev, 0, TIC); 1729 1730 /* Stop PTP Clock driver */ 1731 if (priv->chip_id == RCAR_GEN2) 1732 ravb_ptp_stop(ndev); 1733 1734 /* Set the config mode to stop the AVB-DMAC's processes */ 1735 if (ravb_stop_dma(ndev) < 0) 1736 netdev_err(ndev, 1737 "device will be stopped after h/w processes are done.\n"); 1738 1739 /* Clear the timestamp list */ 1740 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1741 list_del(&ts_skb->list); 1742 kfree(ts_skb); 1743 } 1744 1745 /* PHY disconnect */ 1746 if (ndev->phydev) { 1747 phy_stop(ndev->phydev); 1748 phy_disconnect(ndev->phydev); 1749 if (of_phy_is_fixed_link(np)) 1750 of_phy_deregister_fixed_link(np); 1751 } 1752 1753 if (priv->chip_id != RCAR_GEN2) { 1754 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1755 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1756 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1757 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1758 free_irq(priv->emac_irq, ndev); 1759 } 1760 free_irq(ndev->irq, ndev); 1761 1762 napi_disable(&priv->napi[RAVB_NC]); 1763 napi_disable(&priv->napi[RAVB_BE]); 1764 1765 /* Free all the skb's in the RX queue and the DMA buffers. */ 1766 ravb_ring_free(ndev, RAVB_BE); 1767 ravb_ring_free(ndev, RAVB_NC); 1768 1769 return 0; 1770 } 1771 1772 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1773 { 1774 struct ravb_private *priv = netdev_priv(ndev); 1775 struct hwtstamp_config config; 1776 1777 config.flags = 0; 1778 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1779 HWTSTAMP_TX_OFF; 1780 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1781 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1782 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1783 config.rx_filter = HWTSTAMP_FILTER_ALL; 1784 else 1785 config.rx_filter = HWTSTAMP_FILTER_NONE; 1786 1787 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1788 -EFAULT : 0; 1789 } 1790 1791 /* Control hardware time stamping */ 1792 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1793 { 1794 struct ravb_private *priv = netdev_priv(ndev); 1795 struct hwtstamp_config config; 1796 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1797 u32 tstamp_tx_ctrl; 1798 1799 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1800 return -EFAULT; 1801 1802 /* Reserved for future extensions */ 1803 if (config.flags) 1804 return -EINVAL; 1805 1806 switch (config.tx_type) { 1807 case HWTSTAMP_TX_OFF: 1808 tstamp_tx_ctrl = 0; 1809 break; 1810 case HWTSTAMP_TX_ON: 1811 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1812 break; 1813 default: 1814 return -ERANGE; 1815 } 1816 1817 switch (config.rx_filter) { 1818 case HWTSTAMP_FILTER_NONE: 1819 tstamp_rx_ctrl = 0; 1820 break; 1821 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1822 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1823 break; 1824 default: 1825 config.rx_filter = HWTSTAMP_FILTER_ALL; 1826 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1827 } 1828 1829 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1830 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1831 1832 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1833 -EFAULT : 0; 1834 } 1835 1836 /* ioctl to device function */ 1837 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1838 { 1839 struct phy_device *phydev = ndev->phydev; 1840 1841 if (!netif_running(ndev)) 1842 return -EINVAL; 1843 1844 if (!phydev) 1845 return -ENODEV; 1846 1847 switch (cmd) { 1848 case SIOCGHWTSTAMP: 1849 return ravb_hwtstamp_get(ndev, req); 1850 case SIOCSHWTSTAMP: 1851 return ravb_hwtstamp_set(ndev, req); 1852 } 1853 1854 return phy_mii_ioctl(phydev, req, cmd); 1855 } 1856 1857 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1858 { 1859 struct ravb_private *priv = netdev_priv(ndev); 1860 unsigned long flags; 1861 1862 spin_lock_irqsave(&priv->lock, flags); 1863 1864 /* Disable TX and RX */ 1865 ravb_rcv_snd_disable(ndev); 1866 1867 /* Modify RX Checksum setting */ 1868 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1869 1870 /* Enable TX and RX */ 1871 ravb_rcv_snd_enable(ndev); 1872 1873 spin_unlock_irqrestore(&priv->lock, flags); 1874 } 1875 1876 static int ravb_set_features(struct net_device *ndev, 1877 netdev_features_t features) 1878 { 1879 netdev_features_t changed = ndev->features ^ features; 1880 1881 if (changed & NETIF_F_RXCSUM) 1882 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1883 1884 ndev->features = features; 1885 1886 return 0; 1887 } 1888 1889 static const struct net_device_ops ravb_netdev_ops = { 1890 .ndo_open = ravb_open, 1891 .ndo_stop = ravb_close, 1892 .ndo_start_xmit = ravb_start_xmit, 1893 .ndo_select_queue = ravb_select_queue, 1894 .ndo_get_stats = ravb_get_stats, 1895 .ndo_set_rx_mode = ravb_set_rx_mode, 1896 .ndo_tx_timeout = ravb_tx_timeout, 1897 .ndo_do_ioctl = ravb_do_ioctl, 1898 .ndo_validate_addr = eth_validate_addr, 1899 .ndo_set_mac_address = eth_mac_addr, 1900 .ndo_set_features = ravb_set_features, 1901 }; 1902 1903 /* MDIO bus init function */ 1904 static int ravb_mdio_init(struct ravb_private *priv) 1905 { 1906 struct platform_device *pdev = priv->pdev; 1907 struct device *dev = &pdev->dev; 1908 int error; 1909 1910 /* Bitbang init */ 1911 priv->mdiobb.ops = &bb_ops; 1912 1913 /* MII controller setting */ 1914 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1915 if (!priv->mii_bus) 1916 return -ENOMEM; 1917 1918 /* Hook up MII support for ethtool */ 1919 priv->mii_bus->name = "ravb_mii"; 1920 priv->mii_bus->parent = dev; 1921 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1922 pdev->name, pdev->id); 1923 1924 /* Register MDIO bus */ 1925 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1926 if (error) 1927 goto out_free_bus; 1928 1929 return 0; 1930 1931 out_free_bus: 1932 free_mdio_bitbang(priv->mii_bus); 1933 return error; 1934 } 1935 1936 /* MDIO bus release function */ 1937 static int ravb_mdio_release(struct ravb_private *priv) 1938 { 1939 /* Unregister mdio bus */ 1940 mdiobus_unregister(priv->mii_bus); 1941 1942 /* Free bitbang info */ 1943 free_mdio_bitbang(priv->mii_bus); 1944 1945 return 0; 1946 } 1947 1948 static const struct of_device_id ravb_match_table[] = { 1949 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1950 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1951 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1952 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1953 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1954 { } 1955 }; 1956 MODULE_DEVICE_TABLE(of, ravb_match_table); 1957 1958 static int ravb_set_gti(struct net_device *ndev) 1959 { 1960 struct ravb_private *priv = netdev_priv(ndev); 1961 struct device *dev = ndev->dev.parent; 1962 unsigned long rate; 1963 uint64_t inc; 1964 1965 rate = clk_get_rate(priv->clk); 1966 if (!rate) 1967 return -EINVAL; 1968 1969 inc = 1000000000ULL << 20; 1970 do_div(inc, rate); 1971 1972 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1973 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1974 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1975 return -EINVAL; 1976 } 1977 1978 ravb_write(ndev, inc, GTI); 1979 1980 return 0; 1981 } 1982 1983 static void ravb_set_config_mode(struct net_device *ndev) 1984 { 1985 struct ravb_private *priv = netdev_priv(ndev); 1986 1987 if (priv->chip_id == RCAR_GEN2) { 1988 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1989 /* Set CSEL value */ 1990 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1991 } else { 1992 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1993 CCC_GAC | CCC_CSEL_HPB); 1994 } 1995 } 1996 1997 /* Set tx and rx clock internal delay modes */ 1998 static void ravb_set_delay_mode(struct net_device *ndev) 1999 { 2000 struct ravb_private *priv = netdev_priv(ndev); 2001 int set = 0; 2002 2003 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2004 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 2005 set |= APSR_DM_RDM; 2006 2007 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2008 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 2009 set |= APSR_DM_TDM; 2010 2011 ravb_modify(ndev, APSR, APSR_DM, set); 2012 } 2013 2014 static int ravb_probe(struct platform_device *pdev) 2015 { 2016 struct device_node *np = pdev->dev.of_node; 2017 struct ravb_private *priv; 2018 enum ravb_chip_id chip_id; 2019 struct net_device *ndev; 2020 int error, irq, q; 2021 struct resource *res; 2022 int i; 2023 2024 if (!np) { 2025 dev_err(&pdev->dev, 2026 "this driver is required to be instantiated from device tree\n"); 2027 return -EINVAL; 2028 } 2029 2030 /* Get base address */ 2031 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2032 if (!res) { 2033 dev_err(&pdev->dev, "invalid resource\n"); 2034 return -EINVAL; 2035 } 2036 2037 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2038 NUM_TX_QUEUE, NUM_RX_QUEUE); 2039 if (!ndev) 2040 return -ENOMEM; 2041 2042 ndev->features = NETIF_F_RXCSUM; 2043 ndev->hw_features = NETIF_F_RXCSUM; 2044 2045 pm_runtime_enable(&pdev->dev); 2046 pm_runtime_get_sync(&pdev->dev); 2047 2048 /* The Ether-specific entries in the device structure. */ 2049 ndev->base_addr = res->start; 2050 2051 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2052 2053 if (chip_id == RCAR_GEN3) 2054 irq = platform_get_irq_byname(pdev, "ch22"); 2055 else 2056 irq = platform_get_irq(pdev, 0); 2057 if (irq < 0) { 2058 error = irq; 2059 goto out_release; 2060 } 2061 ndev->irq = irq; 2062 2063 SET_NETDEV_DEV(ndev, &pdev->dev); 2064 2065 priv = netdev_priv(ndev); 2066 priv->ndev = ndev; 2067 priv->pdev = pdev; 2068 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2069 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2070 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2071 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2072 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2073 if (IS_ERR(priv->addr)) { 2074 error = PTR_ERR(priv->addr); 2075 goto out_release; 2076 } 2077 2078 spin_lock_init(&priv->lock); 2079 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2080 2081 priv->phy_interface = of_get_phy_mode(np); 2082 2083 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2084 priv->avb_link_active_low = 2085 of_property_read_bool(np, "renesas,ether-link-active-low"); 2086 2087 if (chip_id == RCAR_GEN3) { 2088 irq = platform_get_irq_byname(pdev, "ch24"); 2089 if (irq < 0) { 2090 error = irq; 2091 goto out_release; 2092 } 2093 priv->emac_irq = irq; 2094 for (i = 0; i < NUM_RX_QUEUE; i++) { 2095 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2096 if (irq < 0) { 2097 error = irq; 2098 goto out_release; 2099 } 2100 priv->rx_irqs[i] = irq; 2101 } 2102 for (i = 0; i < NUM_TX_QUEUE; i++) { 2103 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2104 if (irq < 0) { 2105 error = irq; 2106 goto out_release; 2107 } 2108 priv->tx_irqs[i] = irq; 2109 } 2110 } 2111 2112 priv->chip_id = chip_id; 2113 2114 priv->clk = devm_clk_get(&pdev->dev, NULL); 2115 if (IS_ERR(priv->clk)) { 2116 error = PTR_ERR(priv->clk); 2117 goto out_release; 2118 } 2119 2120 /* Set function */ 2121 ndev->netdev_ops = &ravb_netdev_ops; 2122 ndev->ethtool_ops = &ravb_ethtool_ops; 2123 2124 /* Set AVB config mode */ 2125 ravb_set_config_mode(ndev); 2126 2127 /* Set GTI value */ 2128 error = ravb_set_gti(ndev); 2129 if (error) 2130 goto out_release; 2131 2132 /* Request GTI loading */ 2133 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2134 2135 if (priv->chip_id != RCAR_GEN2) 2136 ravb_set_delay_mode(ndev); 2137 2138 /* Allocate descriptor base address table */ 2139 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2140 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2141 &priv->desc_bat_dma, GFP_KERNEL); 2142 if (!priv->desc_bat) { 2143 dev_err(&pdev->dev, 2144 "Cannot allocate desc base address table (size %d bytes)\n", 2145 priv->desc_bat_size); 2146 error = -ENOMEM; 2147 goto out_release; 2148 } 2149 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2150 priv->desc_bat[q].die_dt = DT_EOS; 2151 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2152 2153 /* Initialise HW timestamp list */ 2154 INIT_LIST_HEAD(&priv->ts_skb_list); 2155 2156 /* Initialise PTP Clock driver */ 2157 if (chip_id != RCAR_GEN2) 2158 ravb_ptp_init(ndev, pdev); 2159 2160 /* Debug message level */ 2161 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2162 2163 /* Read and set MAC address */ 2164 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2165 if (!is_valid_ether_addr(ndev->dev_addr)) { 2166 dev_warn(&pdev->dev, 2167 "no valid MAC address supplied, using a random one\n"); 2168 eth_hw_addr_random(ndev); 2169 } 2170 2171 /* MDIO bus init */ 2172 error = ravb_mdio_init(priv); 2173 if (error) { 2174 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2175 goto out_dma_free; 2176 } 2177 2178 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2179 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2180 2181 /* Network device register */ 2182 error = register_netdev(ndev); 2183 if (error) 2184 goto out_napi_del; 2185 2186 device_set_wakeup_capable(&pdev->dev, 1); 2187 2188 /* Print device information */ 2189 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2190 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2191 2192 platform_set_drvdata(pdev, ndev); 2193 2194 return 0; 2195 2196 out_napi_del: 2197 netif_napi_del(&priv->napi[RAVB_NC]); 2198 netif_napi_del(&priv->napi[RAVB_BE]); 2199 ravb_mdio_release(priv); 2200 out_dma_free: 2201 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2202 priv->desc_bat_dma); 2203 2204 /* Stop PTP Clock driver */ 2205 if (chip_id != RCAR_GEN2) 2206 ravb_ptp_stop(ndev); 2207 out_release: 2208 free_netdev(ndev); 2209 2210 pm_runtime_put(&pdev->dev); 2211 pm_runtime_disable(&pdev->dev); 2212 return error; 2213 } 2214 2215 static int ravb_remove(struct platform_device *pdev) 2216 { 2217 struct net_device *ndev = platform_get_drvdata(pdev); 2218 struct ravb_private *priv = netdev_priv(ndev); 2219 2220 /* Stop PTP Clock driver */ 2221 if (priv->chip_id != RCAR_GEN2) 2222 ravb_ptp_stop(ndev); 2223 2224 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2225 priv->desc_bat_dma); 2226 /* Set reset mode */ 2227 ravb_write(ndev, CCC_OPC_RESET, CCC); 2228 pm_runtime_put_sync(&pdev->dev); 2229 unregister_netdev(ndev); 2230 netif_napi_del(&priv->napi[RAVB_NC]); 2231 netif_napi_del(&priv->napi[RAVB_BE]); 2232 ravb_mdio_release(priv); 2233 pm_runtime_disable(&pdev->dev); 2234 free_netdev(ndev); 2235 platform_set_drvdata(pdev, NULL); 2236 2237 return 0; 2238 } 2239 2240 static int ravb_wol_setup(struct net_device *ndev) 2241 { 2242 struct ravb_private *priv = netdev_priv(ndev); 2243 2244 /* Disable interrupts by clearing the interrupt masks. */ 2245 ravb_write(ndev, 0, RIC0); 2246 ravb_write(ndev, 0, RIC2); 2247 ravb_write(ndev, 0, TIC); 2248 2249 /* Only allow ECI interrupts */ 2250 synchronize_irq(priv->emac_irq); 2251 napi_disable(&priv->napi[RAVB_NC]); 2252 napi_disable(&priv->napi[RAVB_BE]); 2253 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2254 2255 /* Enable MagicPacket */ 2256 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2257 2258 return enable_irq_wake(priv->emac_irq); 2259 } 2260 2261 static int ravb_wol_restore(struct net_device *ndev) 2262 { 2263 struct ravb_private *priv = netdev_priv(ndev); 2264 int ret; 2265 2266 napi_enable(&priv->napi[RAVB_NC]); 2267 napi_enable(&priv->napi[RAVB_BE]); 2268 2269 /* Disable MagicPacket */ 2270 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2271 2272 ret = ravb_close(ndev); 2273 if (ret < 0) 2274 return ret; 2275 2276 return disable_irq_wake(priv->emac_irq); 2277 } 2278 2279 static int __maybe_unused ravb_suspend(struct device *dev) 2280 { 2281 struct net_device *ndev = dev_get_drvdata(dev); 2282 struct ravb_private *priv = netdev_priv(ndev); 2283 int ret; 2284 2285 if (!netif_running(ndev)) 2286 return 0; 2287 2288 netif_device_detach(ndev); 2289 2290 if (priv->wol_enabled) 2291 ret = ravb_wol_setup(ndev); 2292 else 2293 ret = ravb_close(ndev); 2294 2295 return ret; 2296 } 2297 2298 static int __maybe_unused ravb_resume(struct device *dev) 2299 { 2300 struct net_device *ndev = dev_get_drvdata(dev); 2301 struct ravb_private *priv = netdev_priv(ndev); 2302 int ret = 0; 2303 2304 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2305 if (priv->wol_enabled) 2306 ravb_write(ndev, CCC_OPC_RESET, CCC); 2307 2308 /* All register have been reset to default values. 2309 * Restore all registers which where setup at probe time and 2310 * reopen device if it was running before system suspended. 2311 */ 2312 2313 /* Set AVB config mode */ 2314 ravb_set_config_mode(ndev); 2315 2316 /* Set GTI value */ 2317 ret = ravb_set_gti(ndev); 2318 if (ret) 2319 return ret; 2320 2321 /* Request GTI loading */ 2322 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2323 2324 if (priv->chip_id != RCAR_GEN2) 2325 ravb_set_delay_mode(ndev); 2326 2327 /* Restore descriptor base address table */ 2328 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2329 2330 if (netif_running(ndev)) { 2331 if (priv->wol_enabled) { 2332 ret = ravb_wol_restore(ndev); 2333 if (ret) 2334 return ret; 2335 } 2336 ret = ravb_open(ndev); 2337 if (ret < 0) 2338 return ret; 2339 netif_device_attach(ndev); 2340 } 2341 2342 return ret; 2343 } 2344 2345 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2346 { 2347 /* Runtime PM callback shared between ->runtime_suspend() 2348 * and ->runtime_resume(). Simply returns success. 2349 * 2350 * This driver re-initializes all registers after 2351 * pm_runtime_get_sync() anyway so there is no need 2352 * to save and restore registers here. 2353 */ 2354 return 0; 2355 } 2356 2357 static const struct dev_pm_ops ravb_dev_pm_ops = { 2358 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2359 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2360 }; 2361 2362 static struct platform_driver ravb_driver = { 2363 .probe = ravb_probe, 2364 .remove = ravb_remove, 2365 .driver = { 2366 .name = "ravb", 2367 .pm = &ravb_dev_pm_ops, 2368 .of_match_table = ravb_match_table, 2369 }, 2370 }; 2371 2372 module_platform_driver(ravb_driver); 2373 2374 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2375 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2376 MODULE_LICENSE("GPL v2"); 2377