1 /* Renesas Ethernet AVB device driver 2 * 3 * Copyright (C) 2014-2015 Renesas Electronics Corporation 4 * Copyright (C) 2015 Renesas Solutions Corp. 5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 6 * 7 * Based on the SuperH Ethernet driver 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License version 2, 11 * as published by the Free Software Foundation. 12 */ 13 14 #include <linux/cache.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/err.h> 19 #include <linux/etherdevice.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/kernel.h> 23 #include <linux/list.h> 24 #include <linux/module.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_mdio.h> 30 #include <linux/of_net.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/slab.h> 33 #include <linux/spinlock.h> 34 #include <linux/sys_soc.h> 35 36 #include <asm/div64.h> 37 38 #include "ravb.h" 39 40 #define RAVB_DEF_MSG_ENABLE \ 41 (NETIF_MSG_LINK | \ 42 NETIF_MSG_TIMER | \ 43 NETIF_MSG_RX_ERR | \ 44 NETIF_MSG_TX_ERR) 45 46 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 47 "ch0", /* RAVB_BE */ 48 "ch1", /* RAVB_NC */ 49 }; 50 51 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 52 "ch18", /* RAVB_BE */ 53 "ch19", /* RAVB_NC */ 54 }; 55 56 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 57 u32 set) 58 { 59 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 60 } 61 62 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 63 { 64 int i; 65 66 for (i = 0; i < 10000; i++) { 67 if ((ravb_read(ndev, reg) & mask) == value) 68 return 0; 69 udelay(10); 70 } 71 return -ETIMEDOUT; 72 } 73 74 static int ravb_config(struct net_device *ndev) 75 { 76 int error; 77 78 /* Set config mode */ 79 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 80 /* Check if the operating mode is changed to the config mode */ 81 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 82 if (error) 83 netdev_err(ndev, "failed to switch device to config mode\n"); 84 85 return error; 86 } 87 88 static void ravb_set_duplex(struct net_device *ndev) 89 { 90 struct ravb_private *priv = netdev_priv(ndev); 91 92 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0); 93 } 94 95 static void ravb_set_rate(struct net_device *ndev) 96 { 97 struct ravb_private *priv = netdev_priv(ndev); 98 99 switch (priv->speed) { 100 case 100: /* 100BASE */ 101 ravb_write(ndev, GECMR_SPEED_100, GECMR); 102 break; 103 case 1000: /* 1000BASE */ 104 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 105 break; 106 } 107 } 108 109 static void ravb_set_buffer_align(struct sk_buff *skb) 110 { 111 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 112 113 if (reserve) 114 skb_reserve(skb, RAVB_ALIGN - reserve); 115 } 116 117 /* Get MAC address from the MAC address registers 118 * 119 * Ethernet AVB device doesn't have ROM for MAC address. 120 * This function gets the MAC address that was used by a bootloader. 121 */ 122 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 123 { 124 if (mac) { 125 ether_addr_copy(ndev->dev_addr, mac); 126 } else { 127 u32 mahr = ravb_read(ndev, MAHR); 128 u32 malr = ravb_read(ndev, MALR); 129 130 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 131 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 132 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 133 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 134 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 135 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 136 } 137 } 138 139 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 140 { 141 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 142 mdiobb); 143 144 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 145 } 146 147 /* MDC pin control */ 148 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 149 { 150 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 151 } 152 153 /* Data I/O pin control */ 154 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 155 { 156 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 157 } 158 159 /* Set data bit */ 160 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 161 { 162 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 163 } 164 165 /* Get data bit */ 166 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 167 { 168 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 169 mdiobb); 170 171 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 172 } 173 174 /* MDIO bus control struct */ 175 static struct mdiobb_ops bb_ops = { 176 .owner = THIS_MODULE, 177 .set_mdc = ravb_set_mdc, 178 .set_mdio_dir = ravb_set_mdio_dir, 179 .set_mdio_data = ravb_set_mdio_data, 180 .get_mdio_data = ravb_get_mdio_data, 181 }; 182 183 /* Free TX skb function for AVB-IP */ 184 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 185 { 186 struct ravb_private *priv = netdev_priv(ndev); 187 struct net_device_stats *stats = &priv->stats[q]; 188 struct ravb_tx_desc *desc; 189 int free_num = 0; 190 int entry; 191 u32 size; 192 193 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 194 bool txed; 195 196 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 197 NUM_TX_DESC); 198 desc = &priv->tx_ring[q][entry]; 199 txed = desc->die_dt == DT_FEMPTY; 200 if (free_txed_only && !txed) 201 break; 202 /* Descriptor type must be checked before all other reads */ 203 dma_rmb(); 204 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 205 /* Free the original skb. */ 206 if (priv->tx_skb[q][entry / NUM_TX_DESC]) { 207 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 208 size, DMA_TO_DEVICE); 209 /* Last packet descriptor? */ 210 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { 211 entry /= NUM_TX_DESC; 212 dev_kfree_skb_any(priv->tx_skb[q][entry]); 213 priv->tx_skb[q][entry] = NULL; 214 if (txed) 215 stats->tx_packets++; 216 } 217 free_num++; 218 } 219 if (txed) 220 stats->tx_bytes += size; 221 desc->die_dt = DT_EEMPTY; 222 } 223 return free_num; 224 } 225 226 /* Free skb's and DMA buffers for Ethernet AVB */ 227 static void ravb_ring_free(struct net_device *ndev, int q) 228 { 229 struct ravb_private *priv = netdev_priv(ndev); 230 int ring_size; 231 int i; 232 233 if (priv->rx_ring[q]) { 234 for (i = 0; i < priv->num_rx_ring[q]; i++) { 235 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 236 237 if (!dma_mapping_error(ndev->dev.parent, 238 le32_to_cpu(desc->dptr))) 239 dma_unmap_single(ndev->dev.parent, 240 le32_to_cpu(desc->dptr), 241 PKT_BUF_SZ, 242 DMA_FROM_DEVICE); 243 } 244 ring_size = sizeof(struct ravb_ex_rx_desc) * 245 (priv->num_rx_ring[q] + 1); 246 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 247 priv->rx_desc_dma[q]); 248 priv->rx_ring[q] = NULL; 249 } 250 251 if (priv->tx_ring[q]) { 252 ravb_tx_free(ndev, q, false); 253 254 ring_size = sizeof(struct ravb_tx_desc) * 255 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 256 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 257 priv->tx_desc_dma[q]); 258 priv->tx_ring[q] = NULL; 259 } 260 261 /* Free RX skb ringbuffer */ 262 if (priv->rx_skb[q]) { 263 for (i = 0; i < priv->num_rx_ring[q]; i++) 264 dev_kfree_skb(priv->rx_skb[q][i]); 265 } 266 kfree(priv->rx_skb[q]); 267 priv->rx_skb[q] = NULL; 268 269 /* Free aligned TX buffers */ 270 kfree(priv->tx_align[q]); 271 priv->tx_align[q] = NULL; 272 273 /* Free TX skb ringbuffer. 274 * SKBs are freed by ravb_tx_free() call above. 275 */ 276 kfree(priv->tx_skb[q]); 277 priv->tx_skb[q] = NULL; 278 } 279 280 /* Format skb and descriptor buffer for Ethernet AVB */ 281 static void ravb_ring_format(struct net_device *ndev, int q) 282 { 283 struct ravb_private *priv = netdev_priv(ndev); 284 struct ravb_ex_rx_desc *rx_desc; 285 struct ravb_tx_desc *tx_desc; 286 struct ravb_desc *desc; 287 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 288 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 289 NUM_TX_DESC; 290 dma_addr_t dma_addr; 291 int i; 292 293 priv->cur_rx[q] = 0; 294 priv->cur_tx[q] = 0; 295 priv->dirty_rx[q] = 0; 296 priv->dirty_tx[q] = 0; 297 298 memset(priv->rx_ring[q], 0, rx_ring_size); 299 /* Build RX ring buffer */ 300 for (i = 0; i < priv->num_rx_ring[q]; i++) { 301 /* RX descriptor */ 302 rx_desc = &priv->rx_ring[q][i]; 303 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ); 304 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 305 PKT_BUF_SZ, 306 DMA_FROM_DEVICE); 307 /* We just set the data size to 0 for a failed mapping which 308 * should prevent DMA from happening... 309 */ 310 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 311 rx_desc->ds_cc = cpu_to_le16(0); 312 rx_desc->dptr = cpu_to_le32(dma_addr); 313 rx_desc->die_dt = DT_FEMPTY; 314 } 315 rx_desc = &priv->rx_ring[q][i]; 316 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 317 rx_desc->die_dt = DT_LINKFIX; /* type */ 318 319 memset(priv->tx_ring[q], 0, tx_ring_size); 320 /* Build TX ring buffer */ 321 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 322 i++, tx_desc++) { 323 tx_desc->die_dt = DT_EEMPTY; 324 tx_desc++; 325 tx_desc->die_dt = DT_EEMPTY; 326 } 327 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 328 tx_desc->die_dt = DT_LINKFIX; /* type */ 329 330 /* RX descriptor base address for best effort */ 331 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 332 desc->die_dt = DT_LINKFIX; /* type */ 333 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 334 335 /* TX descriptor base address for best effort */ 336 desc = &priv->desc_bat[q]; 337 desc->die_dt = DT_LINKFIX; /* type */ 338 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 339 } 340 341 /* Init skb and descriptor buffer for Ethernet AVB */ 342 static int ravb_ring_init(struct net_device *ndev, int q) 343 { 344 struct ravb_private *priv = netdev_priv(ndev); 345 struct sk_buff *skb; 346 int ring_size; 347 int i; 348 349 /* Allocate RX and TX skb rings */ 350 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 351 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 352 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 353 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 354 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 355 goto error; 356 357 for (i = 0; i < priv->num_rx_ring[q]; i++) { 358 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1); 359 if (!skb) 360 goto error; 361 ravb_set_buffer_align(skb); 362 priv->rx_skb[q][i] = skb; 363 } 364 365 /* Allocate rings for the aligned buffers */ 366 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 367 DPTR_ALIGN - 1, GFP_KERNEL); 368 if (!priv->tx_align[q]) 369 goto error; 370 371 /* Allocate all RX descriptors. */ 372 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 373 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 374 &priv->rx_desc_dma[q], 375 GFP_KERNEL); 376 if (!priv->rx_ring[q]) 377 goto error; 378 379 priv->dirty_rx[q] = 0; 380 381 /* Allocate all TX descriptors. */ 382 ring_size = sizeof(struct ravb_tx_desc) * 383 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 384 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 385 &priv->tx_desc_dma[q], 386 GFP_KERNEL); 387 if (!priv->tx_ring[q]) 388 goto error; 389 390 return 0; 391 392 error: 393 ravb_ring_free(ndev, q); 394 395 return -ENOMEM; 396 } 397 398 /* E-MAC init function */ 399 static void ravb_emac_init(struct net_device *ndev) 400 { 401 struct ravb_private *priv = netdev_priv(ndev); 402 403 /* Receive frame limit set register */ 404 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 405 406 /* PAUSE prohibition */ 407 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | 408 ECMR_TE | ECMR_RE, ECMR); 409 410 ravb_set_rate(ndev); 411 412 /* Set MAC address */ 413 ravb_write(ndev, 414 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 415 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 416 ravb_write(ndev, 417 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 418 419 /* E-MAC status register clear */ 420 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 421 422 /* E-MAC interrupt enable register */ 423 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 424 } 425 426 /* Device init function for Ethernet AVB */ 427 static int ravb_dmac_init(struct net_device *ndev) 428 { 429 struct ravb_private *priv = netdev_priv(ndev); 430 int error; 431 432 /* Set CONFIG mode */ 433 error = ravb_config(ndev); 434 if (error) 435 return error; 436 437 error = ravb_ring_init(ndev, RAVB_BE); 438 if (error) 439 return error; 440 error = ravb_ring_init(ndev, RAVB_NC); 441 if (error) { 442 ravb_ring_free(ndev, RAVB_BE); 443 return error; 444 } 445 446 /* Descriptor format */ 447 ravb_ring_format(ndev, RAVB_BE); 448 ravb_ring_format(ndev, RAVB_NC); 449 450 #if defined(__LITTLE_ENDIAN) 451 ravb_modify(ndev, CCC, CCC_BOC, 0); 452 #else 453 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 454 #endif 455 456 /* Set AVB RX */ 457 ravb_write(ndev, 458 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 459 460 /* Set FIFO size */ 461 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 462 463 /* Timestamp enable */ 464 ravb_write(ndev, TCCR_TFEN, TCCR); 465 466 /* Interrupt init: */ 467 if (priv->chip_id == RCAR_GEN3) { 468 /* Clear DIL.DPLx */ 469 ravb_write(ndev, 0, DIL); 470 /* Set queue specific interrupt */ 471 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 472 } 473 /* Frame receive */ 474 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 475 /* Disable FIFO full warning */ 476 ravb_write(ndev, 0, RIC1); 477 /* Receive FIFO full error, descriptor empty */ 478 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 479 /* Frame transmitted, timestamp FIFO updated */ 480 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 481 482 /* Setting the control will start the AVB-DMAC process. */ 483 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 484 485 return 0; 486 } 487 488 static void ravb_get_tx_tstamp(struct net_device *ndev) 489 { 490 struct ravb_private *priv = netdev_priv(ndev); 491 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 492 struct skb_shared_hwtstamps shhwtstamps; 493 struct sk_buff *skb; 494 struct timespec64 ts; 495 u16 tag, tfa_tag; 496 int count; 497 u32 tfa2; 498 499 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 500 while (count--) { 501 tfa2 = ravb_read(ndev, TFA2); 502 tfa_tag = (tfa2 & TFA2_TST) >> 16; 503 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 504 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 505 ravb_read(ndev, TFA1); 506 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 507 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 508 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 509 list) { 510 skb = ts_skb->skb; 511 tag = ts_skb->tag; 512 list_del(&ts_skb->list); 513 kfree(ts_skb); 514 if (tag == tfa_tag) { 515 skb_tstamp_tx(skb, &shhwtstamps); 516 break; 517 } 518 } 519 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 520 } 521 } 522 523 /* Packet receive function for Ethernet AVB */ 524 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 525 { 526 struct ravb_private *priv = netdev_priv(ndev); 527 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 528 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 529 priv->cur_rx[q]; 530 struct net_device_stats *stats = &priv->stats[q]; 531 struct ravb_ex_rx_desc *desc; 532 struct sk_buff *skb; 533 dma_addr_t dma_addr; 534 struct timespec64 ts; 535 u8 desc_status; 536 u16 pkt_len; 537 int limit; 538 539 boguscnt = min(boguscnt, *quota); 540 limit = boguscnt; 541 desc = &priv->rx_ring[q][entry]; 542 while (desc->die_dt != DT_FEMPTY) { 543 /* Descriptor type must be checked before all other reads */ 544 dma_rmb(); 545 desc_status = desc->msc; 546 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 547 548 if (--boguscnt < 0) 549 break; 550 551 /* We use 0-byte descriptors to mark the DMA mapping errors */ 552 if (!pkt_len) 553 continue; 554 555 if (desc_status & MSC_MC) 556 stats->multicast++; 557 558 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 559 MSC_CEEF)) { 560 stats->rx_errors++; 561 if (desc_status & MSC_CRC) 562 stats->rx_crc_errors++; 563 if (desc_status & MSC_RFE) 564 stats->rx_frame_errors++; 565 if (desc_status & (MSC_RTLF | MSC_RTSF)) 566 stats->rx_length_errors++; 567 if (desc_status & MSC_CEEF) 568 stats->rx_missed_errors++; 569 } else { 570 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 571 572 skb = priv->rx_skb[q][entry]; 573 priv->rx_skb[q][entry] = NULL; 574 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 575 PKT_BUF_SZ, 576 DMA_FROM_DEVICE); 577 get_ts &= (q == RAVB_NC) ? 578 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 579 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 580 if (get_ts) { 581 struct skb_shared_hwtstamps *shhwtstamps; 582 583 shhwtstamps = skb_hwtstamps(skb); 584 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 585 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 586 32) | le32_to_cpu(desc->ts_sl); 587 ts.tv_nsec = le32_to_cpu(desc->ts_n); 588 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 589 } 590 skb_put(skb, pkt_len); 591 skb->protocol = eth_type_trans(skb, ndev); 592 napi_gro_receive(&priv->napi[q], skb); 593 stats->rx_packets++; 594 stats->rx_bytes += pkt_len; 595 } 596 597 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 598 desc = &priv->rx_ring[q][entry]; 599 } 600 601 /* Refill the RX ring buffers. */ 602 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 603 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 604 desc = &priv->rx_ring[q][entry]; 605 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ); 606 607 if (!priv->rx_skb[q][entry]) { 608 skb = netdev_alloc_skb(ndev, 609 PKT_BUF_SZ + RAVB_ALIGN - 1); 610 if (!skb) 611 break; /* Better luck next round. */ 612 ravb_set_buffer_align(skb); 613 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 614 le16_to_cpu(desc->ds_cc), 615 DMA_FROM_DEVICE); 616 skb_checksum_none_assert(skb); 617 /* We just set the data size to 0 for a failed mapping 618 * which should prevent DMA from happening... 619 */ 620 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 621 desc->ds_cc = cpu_to_le16(0); 622 desc->dptr = cpu_to_le32(dma_addr); 623 priv->rx_skb[q][entry] = skb; 624 } 625 /* Descriptor type must be set after all the above writes */ 626 dma_wmb(); 627 desc->die_dt = DT_FEMPTY; 628 } 629 630 *quota -= limit - (++boguscnt); 631 632 return boguscnt <= 0; 633 } 634 635 static void ravb_rcv_snd_disable(struct net_device *ndev) 636 { 637 /* Disable TX and RX */ 638 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 639 } 640 641 static void ravb_rcv_snd_enable(struct net_device *ndev) 642 { 643 /* Enable TX and RX */ 644 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 645 } 646 647 /* function for waiting dma process finished */ 648 static int ravb_stop_dma(struct net_device *ndev) 649 { 650 int error; 651 652 /* Wait for stopping the hardware TX process */ 653 error = ravb_wait(ndev, TCCR, 654 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 655 if (error) 656 return error; 657 658 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 659 0); 660 if (error) 661 return error; 662 663 /* Stop the E-MAC's RX/TX processes. */ 664 ravb_rcv_snd_disable(ndev); 665 666 /* Wait for stopping the RX DMA process */ 667 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 668 if (error) 669 return error; 670 671 /* Stop AVB-DMAC process */ 672 return ravb_config(ndev); 673 } 674 675 /* E-MAC interrupt handler */ 676 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 677 { 678 struct ravb_private *priv = netdev_priv(ndev); 679 u32 ecsr, psr; 680 681 ecsr = ravb_read(ndev, ECSR); 682 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 683 684 if (ecsr & ECSR_MPD) 685 pm_wakeup_event(&priv->pdev->dev, 0); 686 if (ecsr & ECSR_ICD) 687 ndev->stats.tx_carrier_errors++; 688 if (ecsr & ECSR_LCHNG) { 689 /* Link changed */ 690 if (priv->no_avb_link) 691 return; 692 psr = ravb_read(ndev, PSR); 693 if (priv->avb_link_active_low) 694 psr ^= PSR_LMON; 695 if (!(psr & PSR_LMON)) { 696 /* DIsable RX and TX */ 697 ravb_rcv_snd_disable(ndev); 698 } else { 699 /* Enable RX and TX */ 700 ravb_rcv_snd_enable(ndev); 701 } 702 } 703 } 704 705 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 706 { 707 struct net_device *ndev = dev_id; 708 struct ravb_private *priv = netdev_priv(ndev); 709 710 spin_lock(&priv->lock); 711 ravb_emac_interrupt_unlocked(ndev); 712 mmiowb(); 713 spin_unlock(&priv->lock); 714 return IRQ_HANDLED; 715 } 716 717 /* Error interrupt handler */ 718 static void ravb_error_interrupt(struct net_device *ndev) 719 { 720 struct ravb_private *priv = netdev_priv(ndev); 721 u32 eis, ris2; 722 723 eis = ravb_read(ndev, EIS); 724 ravb_write(ndev, ~EIS_QFS, EIS); 725 if (eis & EIS_QFS) { 726 ris2 = ravb_read(ndev, RIS2); 727 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); 728 729 /* Receive Descriptor Empty int */ 730 if (ris2 & RIS2_QFF0) 731 priv->stats[RAVB_BE].rx_over_errors++; 732 733 /* Receive Descriptor Empty int */ 734 if (ris2 & RIS2_QFF1) 735 priv->stats[RAVB_NC].rx_over_errors++; 736 737 /* Receive FIFO Overflow int */ 738 if (ris2 & RIS2_RFFF) 739 priv->rx_fifo_errors++; 740 } 741 } 742 743 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 744 { 745 struct ravb_private *priv = netdev_priv(ndev); 746 u32 ris0 = ravb_read(ndev, RIS0); 747 u32 ric0 = ravb_read(ndev, RIC0); 748 u32 tis = ravb_read(ndev, TIS); 749 u32 tic = ravb_read(ndev, TIC); 750 751 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 752 if (napi_schedule_prep(&priv->napi[q])) { 753 /* Mask RX and TX interrupts */ 754 if (priv->chip_id == RCAR_GEN2) { 755 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 756 ravb_write(ndev, tic & ~BIT(q), TIC); 757 } else { 758 ravb_write(ndev, BIT(q), RID0); 759 ravb_write(ndev, BIT(q), TID); 760 } 761 __napi_schedule(&priv->napi[q]); 762 } else { 763 netdev_warn(ndev, 764 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 765 ris0, ric0); 766 netdev_warn(ndev, 767 " tx status 0x%08x, tx mask 0x%08x.\n", 768 tis, tic); 769 } 770 return true; 771 } 772 return false; 773 } 774 775 static bool ravb_timestamp_interrupt(struct net_device *ndev) 776 { 777 u32 tis = ravb_read(ndev, TIS); 778 779 if (tis & TIS_TFUF) { 780 ravb_write(ndev, ~TIS_TFUF, TIS); 781 ravb_get_tx_tstamp(ndev); 782 return true; 783 } 784 return false; 785 } 786 787 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 788 { 789 struct net_device *ndev = dev_id; 790 struct ravb_private *priv = netdev_priv(ndev); 791 irqreturn_t result = IRQ_NONE; 792 u32 iss; 793 794 spin_lock(&priv->lock); 795 /* Get interrupt status */ 796 iss = ravb_read(ndev, ISS); 797 798 /* Received and transmitted interrupts */ 799 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 800 int q; 801 802 /* Timestamp updated */ 803 if (ravb_timestamp_interrupt(ndev)) 804 result = IRQ_HANDLED; 805 806 /* Network control and best effort queue RX/TX */ 807 for (q = RAVB_NC; q >= RAVB_BE; q--) { 808 if (ravb_queue_interrupt(ndev, q)) 809 result = IRQ_HANDLED; 810 } 811 } 812 813 /* E-MAC status summary */ 814 if (iss & ISS_MS) { 815 ravb_emac_interrupt_unlocked(ndev); 816 result = IRQ_HANDLED; 817 } 818 819 /* Error status summary */ 820 if (iss & ISS_ES) { 821 ravb_error_interrupt(ndev); 822 result = IRQ_HANDLED; 823 } 824 825 /* gPTP interrupt status summary */ 826 if (iss & ISS_CGIS) { 827 ravb_ptp_interrupt(ndev); 828 result = IRQ_HANDLED; 829 } 830 831 mmiowb(); 832 spin_unlock(&priv->lock); 833 return result; 834 } 835 836 /* Timestamp/Error/gPTP interrupt handler */ 837 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 838 { 839 struct net_device *ndev = dev_id; 840 struct ravb_private *priv = netdev_priv(ndev); 841 irqreturn_t result = IRQ_NONE; 842 u32 iss; 843 844 spin_lock(&priv->lock); 845 /* Get interrupt status */ 846 iss = ravb_read(ndev, ISS); 847 848 /* Timestamp updated */ 849 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 850 result = IRQ_HANDLED; 851 852 /* Error status summary */ 853 if (iss & ISS_ES) { 854 ravb_error_interrupt(ndev); 855 result = IRQ_HANDLED; 856 } 857 858 /* gPTP interrupt status summary */ 859 if (iss & ISS_CGIS) { 860 ravb_ptp_interrupt(ndev); 861 result = IRQ_HANDLED; 862 } 863 864 mmiowb(); 865 spin_unlock(&priv->lock); 866 return result; 867 } 868 869 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 870 { 871 struct net_device *ndev = dev_id; 872 struct ravb_private *priv = netdev_priv(ndev); 873 irqreturn_t result = IRQ_NONE; 874 875 spin_lock(&priv->lock); 876 877 /* Network control/Best effort queue RX/TX */ 878 if (ravb_queue_interrupt(ndev, q)) 879 result = IRQ_HANDLED; 880 881 mmiowb(); 882 spin_unlock(&priv->lock); 883 return result; 884 } 885 886 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 887 { 888 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 889 } 890 891 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 892 { 893 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 894 } 895 896 static int ravb_poll(struct napi_struct *napi, int budget) 897 { 898 struct net_device *ndev = napi->dev; 899 struct ravb_private *priv = netdev_priv(ndev); 900 unsigned long flags; 901 int q = napi - priv->napi; 902 int mask = BIT(q); 903 int quota = budget; 904 u32 ris0, tis; 905 906 for (;;) { 907 tis = ravb_read(ndev, TIS); 908 ris0 = ravb_read(ndev, RIS0); 909 if (!((ris0 & mask) || (tis & mask))) 910 break; 911 912 /* Processing RX Descriptor Ring */ 913 if (ris0 & mask) { 914 /* Clear RX interrupt */ 915 ravb_write(ndev, ~mask, RIS0); 916 if (ravb_rx(ndev, "a, q)) 917 goto out; 918 } 919 /* Processing TX Descriptor Ring */ 920 if (tis & mask) { 921 spin_lock_irqsave(&priv->lock, flags); 922 /* Clear TX interrupt */ 923 ravb_write(ndev, ~mask, TIS); 924 ravb_tx_free(ndev, q, true); 925 netif_wake_subqueue(ndev, q); 926 mmiowb(); 927 spin_unlock_irqrestore(&priv->lock, flags); 928 } 929 } 930 931 napi_complete(napi); 932 933 /* Re-enable RX/TX interrupts */ 934 spin_lock_irqsave(&priv->lock, flags); 935 if (priv->chip_id == RCAR_GEN2) { 936 ravb_modify(ndev, RIC0, mask, mask); 937 ravb_modify(ndev, TIC, mask, mask); 938 } else { 939 ravb_write(ndev, mask, RIE0); 940 ravb_write(ndev, mask, TIE); 941 } 942 mmiowb(); 943 spin_unlock_irqrestore(&priv->lock, flags); 944 945 /* Receive error message handling */ 946 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 947 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 948 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 949 ndev->stats.rx_over_errors = priv->rx_over_errors; 950 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 951 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 952 out: 953 return budget - quota; 954 } 955 956 /* PHY state control function */ 957 static void ravb_adjust_link(struct net_device *ndev) 958 { 959 struct ravb_private *priv = netdev_priv(ndev); 960 struct phy_device *phydev = ndev->phydev; 961 bool new_state = false; 962 963 if (phydev->link) { 964 if (phydev->duplex != priv->duplex) { 965 new_state = true; 966 priv->duplex = phydev->duplex; 967 ravb_set_duplex(ndev); 968 } 969 970 if (phydev->speed != priv->speed) { 971 new_state = true; 972 priv->speed = phydev->speed; 973 ravb_set_rate(ndev); 974 } 975 if (!priv->link) { 976 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 977 new_state = true; 978 priv->link = phydev->link; 979 if (priv->no_avb_link) 980 ravb_rcv_snd_enable(ndev); 981 } 982 } else if (priv->link) { 983 new_state = true; 984 priv->link = 0; 985 priv->speed = 0; 986 priv->duplex = -1; 987 if (priv->no_avb_link) 988 ravb_rcv_snd_disable(ndev); 989 } 990 991 if (new_state && netif_msg_link(priv)) 992 phy_print_status(phydev); 993 } 994 995 static const struct soc_device_attribute r8a7795es10[] = { 996 { .soc_id = "r8a7795", .revision = "ES1.0", }, 997 { /* sentinel */ } 998 }; 999 1000 /* PHY init function */ 1001 static int ravb_phy_init(struct net_device *ndev) 1002 { 1003 struct device_node *np = ndev->dev.parent->of_node; 1004 struct ravb_private *priv = netdev_priv(ndev); 1005 struct phy_device *phydev; 1006 struct device_node *pn; 1007 int err; 1008 1009 priv->link = 0; 1010 priv->speed = 0; 1011 priv->duplex = -1; 1012 1013 /* Try connecting to PHY */ 1014 pn = of_parse_phandle(np, "phy-handle", 0); 1015 if (!pn) { 1016 /* In the case of a fixed PHY, the DT node associated 1017 * to the PHY is the Ethernet MAC DT node. 1018 */ 1019 if (of_phy_is_fixed_link(np)) { 1020 err = of_phy_register_fixed_link(np); 1021 if (err) 1022 return err; 1023 } 1024 pn = of_node_get(np); 1025 } 1026 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1027 priv->phy_interface); 1028 of_node_put(pn); 1029 if (!phydev) { 1030 netdev_err(ndev, "failed to connect PHY\n"); 1031 err = -ENOENT; 1032 goto err_deregister_fixed_link; 1033 } 1034 1035 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1036 * at this time. 1037 */ 1038 if (soc_device_match(r8a7795es10)) { 1039 err = phy_set_max_speed(phydev, SPEED_100); 1040 if (err) { 1041 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1042 goto err_phy_disconnect; 1043 } 1044 1045 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1046 } 1047 1048 /* 10BASE is not supported */ 1049 phydev->supported &= ~PHY_10BT_FEATURES; 1050 1051 phy_attached_info(phydev); 1052 1053 return 0; 1054 1055 err_phy_disconnect: 1056 phy_disconnect(phydev); 1057 err_deregister_fixed_link: 1058 if (of_phy_is_fixed_link(np)) 1059 of_phy_deregister_fixed_link(np); 1060 1061 return err; 1062 } 1063 1064 /* PHY control start function */ 1065 static int ravb_phy_start(struct net_device *ndev) 1066 { 1067 int error; 1068 1069 error = ravb_phy_init(ndev); 1070 if (error) 1071 return error; 1072 1073 phy_start(ndev->phydev); 1074 1075 return 0; 1076 } 1077 1078 static int ravb_get_link_ksettings(struct net_device *ndev, 1079 struct ethtool_link_ksettings *cmd) 1080 { 1081 struct ravb_private *priv = netdev_priv(ndev); 1082 unsigned long flags; 1083 1084 if (!ndev->phydev) 1085 return -ENODEV; 1086 1087 spin_lock_irqsave(&priv->lock, flags); 1088 phy_ethtool_ksettings_get(ndev->phydev, cmd); 1089 spin_unlock_irqrestore(&priv->lock, flags); 1090 1091 return 0; 1092 } 1093 1094 static int ravb_set_link_ksettings(struct net_device *ndev, 1095 const struct ethtool_link_ksettings *cmd) 1096 { 1097 struct ravb_private *priv = netdev_priv(ndev); 1098 unsigned long flags; 1099 int error; 1100 1101 if (!ndev->phydev) 1102 return -ENODEV; 1103 1104 spin_lock_irqsave(&priv->lock, flags); 1105 1106 /* Disable TX and RX */ 1107 ravb_rcv_snd_disable(ndev); 1108 1109 error = phy_ethtool_ksettings_set(ndev->phydev, cmd); 1110 if (error) 1111 goto error_exit; 1112 1113 if (cmd->base.duplex == DUPLEX_FULL) 1114 priv->duplex = 1; 1115 else 1116 priv->duplex = 0; 1117 1118 ravb_set_duplex(ndev); 1119 1120 error_exit: 1121 mdelay(1); 1122 1123 /* Enable TX and RX */ 1124 ravb_rcv_snd_enable(ndev); 1125 1126 mmiowb(); 1127 spin_unlock_irqrestore(&priv->lock, flags); 1128 1129 return error; 1130 } 1131 1132 static int ravb_nway_reset(struct net_device *ndev) 1133 { 1134 struct ravb_private *priv = netdev_priv(ndev); 1135 int error = -ENODEV; 1136 unsigned long flags; 1137 1138 if (ndev->phydev) { 1139 spin_lock_irqsave(&priv->lock, flags); 1140 error = phy_start_aneg(ndev->phydev); 1141 spin_unlock_irqrestore(&priv->lock, flags); 1142 } 1143 1144 return error; 1145 } 1146 1147 static u32 ravb_get_msglevel(struct net_device *ndev) 1148 { 1149 struct ravb_private *priv = netdev_priv(ndev); 1150 1151 return priv->msg_enable; 1152 } 1153 1154 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1155 { 1156 struct ravb_private *priv = netdev_priv(ndev); 1157 1158 priv->msg_enable = value; 1159 } 1160 1161 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1162 "rx_queue_0_current", 1163 "tx_queue_0_current", 1164 "rx_queue_0_dirty", 1165 "tx_queue_0_dirty", 1166 "rx_queue_0_packets", 1167 "tx_queue_0_packets", 1168 "rx_queue_0_bytes", 1169 "tx_queue_0_bytes", 1170 "rx_queue_0_mcast_packets", 1171 "rx_queue_0_errors", 1172 "rx_queue_0_crc_errors", 1173 "rx_queue_0_frame_errors", 1174 "rx_queue_0_length_errors", 1175 "rx_queue_0_missed_errors", 1176 "rx_queue_0_over_errors", 1177 1178 "rx_queue_1_current", 1179 "tx_queue_1_current", 1180 "rx_queue_1_dirty", 1181 "tx_queue_1_dirty", 1182 "rx_queue_1_packets", 1183 "tx_queue_1_packets", 1184 "rx_queue_1_bytes", 1185 "tx_queue_1_bytes", 1186 "rx_queue_1_mcast_packets", 1187 "rx_queue_1_errors", 1188 "rx_queue_1_crc_errors", 1189 "rx_queue_1_frame_errors", 1190 "rx_queue_1_length_errors", 1191 "rx_queue_1_missed_errors", 1192 "rx_queue_1_over_errors", 1193 }; 1194 1195 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1196 1197 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1198 { 1199 switch (sset) { 1200 case ETH_SS_STATS: 1201 return RAVB_STATS_LEN; 1202 default: 1203 return -EOPNOTSUPP; 1204 } 1205 } 1206 1207 static void ravb_get_ethtool_stats(struct net_device *ndev, 1208 struct ethtool_stats *stats, u64 *data) 1209 { 1210 struct ravb_private *priv = netdev_priv(ndev); 1211 int i = 0; 1212 int q; 1213 1214 /* Device-specific stats */ 1215 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1216 struct net_device_stats *stats = &priv->stats[q]; 1217 1218 data[i++] = priv->cur_rx[q]; 1219 data[i++] = priv->cur_tx[q]; 1220 data[i++] = priv->dirty_rx[q]; 1221 data[i++] = priv->dirty_tx[q]; 1222 data[i++] = stats->rx_packets; 1223 data[i++] = stats->tx_packets; 1224 data[i++] = stats->rx_bytes; 1225 data[i++] = stats->tx_bytes; 1226 data[i++] = stats->multicast; 1227 data[i++] = stats->rx_errors; 1228 data[i++] = stats->rx_crc_errors; 1229 data[i++] = stats->rx_frame_errors; 1230 data[i++] = stats->rx_length_errors; 1231 data[i++] = stats->rx_missed_errors; 1232 data[i++] = stats->rx_over_errors; 1233 } 1234 } 1235 1236 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1237 { 1238 switch (stringset) { 1239 case ETH_SS_STATS: 1240 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1241 break; 1242 } 1243 } 1244 1245 static void ravb_get_ringparam(struct net_device *ndev, 1246 struct ethtool_ringparam *ring) 1247 { 1248 struct ravb_private *priv = netdev_priv(ndev); 1249 1250 ring->rx_max_pending = BE_RX_RING_MAX; 1251 ring->tx_max_pending = BE_TX_RING_MAX; 1252 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1253 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1254 } 1255 1256 static int ravb_set_ringparam(struct net_device *ndev, 1257 struct ethtool_ringparam *ring) 1258 { 1259 struct ravb_private *priv = netdev_priv(ndev); 1260 int error; 1261 1262 if (ring->tx_pending > BE_TX_RING_MAX || 1263 ring->rx_pending > BE_RX_RING_MAX || 1264 ring->tx_pending < BE_TX_RING_MIN || 1265 ring->rx_pending < BE_RX_RING_MIN) 1266 return -EINVAL; 1267 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1268 return -EINVAL; 1269 1270 if (netif_running(ndev)) { 1271 netif_device_detach(ndev); 1272 /* Stop PTP Clock driver */ 1273 if (priv->chip_id == RCAR_GEN2) 1274 ravb_ptp_stop(ndev); 1275 /* Wait for DMA stopping */ 1276 error = ravb_stop_dma(ndev); 1277 if (error) { 1278 netdev_err(ndev, 1279 "cannot set ringparam! Any AVB processes are still running?\n"); 1280 return error; 1281 } 1282 synchronize_irq(ndev->irq); 1283 1284 /* Free all the skb's in the RX queue and the DMA buffers. */ 1285 ravb_ring_free(ndev, RAVB_BE); 1286 ravb_ring_free(ndev, RAVB_NC); 1287 } 1288 1289 /* Set new parameters */ 1290 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1291 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1292 1293 if (netif_running(ndev)) { 1294 error = ravb_dmac_init(ndev); 1295 if (error) { 1296 netdev_err(ndev, 1297 "%s: ravb_dmac_init() failed, error %d\n", 1298 __func__, error); 1299 return error; 1300 } 1301 1302 ravb_emac_init(ndev); 1303 1304 /* Initialise PTP Clock driver */ 1305 if (priv->chip_id == RCAR_GEN2) 1306 ravb_ptp_init(ndev, priv->pdev); 1307 1308 netif_device_attach(ndev); 1309 } 1310 1311 return 0; 1312 } 1313 1314 static int ravb_get_ts_info(struct net_device *ndev, 1315 struct ethtool_ts_info *info) 1316 { 1317 struct ravb_private *priv = netdev_priv(ndev); 1318 1319 info->so_timestamping = 1320 SOF_TIMESTAMPING_TX_SOFTWARE | 1321 SOF_TIMESTAMPING_RX_SOFTWARE | 1322 SOF_TIMESTAMPING_SOFTWARE | 1323 SOF_TIMESTAMPING_TX_HARDWARE | 1324 SOF_TIMESTAMPING_RX_HARDWARE | 1325 SOF_TIMESTAMPING_RAW_HARDWARE; 1326 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1327 info->rx_filters = 1328 (1 << HWTSTAMP_FILTER_NONE) | 1329 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1330 (1 << HWTSTAMP_FILTER_ALL); 1331 info->phc_index = ptp_clock_index(priv->ptp.clock); 1332 1333 return 0; 1334 } 1335 1336 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1337 { 1338 struct ravb_private *priv = netdev_priv(ndev); 1339 1340 wol->supported = 0; 1341 wol->wolopts = 0; 1342 1343 if (priv->clk) { 1344 wol->supported = WAKE_MAGIC; 1345 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1346 } 1347 } 1348 1349 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1350 { 1351 struct ravb_private *priv = netdev_priv(ndev); 1352 1353 if (!priv->clk || wol->wolopts & ~WAKE_MAGIC) 1354 return -EOPNOTSUPP; 1355 1356 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1357 1358 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1359 1360 return 0; 1361 } 1362 1363 static const struct ethtool_ops ravb_ethtool_ops = { 1364 .nway_reset = ravb_nway_reset, 1365 .get_msglevel = ravb_get_msglevel, 1366 .set_msglevel = ravb_set_msglevel, 1367 .get_link = ethtool_op_get_link, 1368 .get_strings = ravb_get_strings, 1369 .get_ethtool_stats = ravb_get_ethtool_stats, 1370 .get_sset_count = ravb_get_sset_count, 1371 .get_ringparam = ravb_get_ringparam, 1372 .set_ringparam = ravb_set_ringparam, 1373 .get_ts_info = ravb_get_ts_info, 1374 .get_link_ksettings = ravb_get_link_ksettings, 1375 .set_link_ksettings = ravb_set_link_ksettings, 1376 .get_wol = ravb_get_wol, 1377 .set_wol = ravb_set_wol, 1378 }; 1379 1380 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1381 struct net_device *ndev, struct device *dev, 1382 const char *ch) 1383 { 1384 char *name; 1385 int error; 1386 1387 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1388 if (!name) 1389 return -ENOMEM; 1390 error = request_irq(irq, handler, 0, name, ndev); 1391 if (error) 1392 netdev_err(ndev, "cannot request IRQ %s\n", name); 1393 1394 return error; 1395 } 1396 1397 /* Network device open function for Ethernet AVB */ 1398 static int ravb_open(struct net_device *ndev) 1399 { 1400 struct ravb_private *priv = netdev_priv(ndev); 1401 struct platform_device *pdev = priv->pdev; 1402 struct device *dev = &pdev->dev; 1403 int error; 1404 1405 napi_enable(&priv->napi[RAVB_BE]); 1406 napi_enable(&priv->napi[RAVB_NC]); 1407 1408 if (priv->chip_id == RCAR_GEN2) { 1409 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1410 ndev->name, ndev); 1411 if (error) { 1412 netdev_err(ndev, "cannot request IRQ\n"); 1413 goto out_napi_off; 1414 } 1415 } else { 1416 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1417 dev, "ch22:multi"); 1418 if (error) 1419 goto out_napi_off; 1420 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1421 dev, "ch24:emac"); 1422 if (error) 1423 goto out_free_irq; 1424 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1425 ndev, dev, "ch0:rx_be"); 1426 if (error) 1427 goto out_free_irq_emac; 1428 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1429 ndev, dev, "ch18:tx_be"); 1430 if (error) 1431 goto out_free_irq_be_rx; 1432 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1433 ndev, dev, "ch1:rx_nc"); 1434 if (error) 1435 goto out_free_irq_be_tx; 1436 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1437 ndev, dev, "ch19:tx_nc"); 1438 if (error) 1439 goto out_free_irq_nc_rx; 1440 } 1441 1442 /* Device init */ 1443 error = ravb_dmac_init(ndev); 1444 if (error) 1445 goto out_free_irq_nc_tx; 1446 ravb_emac_init(ndev); 1447 1448 /* Initialise PTP Clock driver */ 1449 if (priv->chip_id == RCAR_GEN2) 1450 ravb_ptp_init(ndev, priv->pdev); 1451 1452 netif_tx_start_all_queues(ndev); 1453 1454 /* PHY control start */ 1455 error = ravb_phy_start(ndev); 1456 if (error) 1457 goto out_ptp_stop; 1458 1459 return 0; 1460 1461 out_ptp_stop: 1462 /* Stop PTP Clock driver */ 1463 if (priv->chip_id == RCAR_GEN2) 1464 ravb_ptp_stop(ndev); 1465 out_free_irq_nc_tx: 1466 if (priv->chip_id == RCAR_GEN2) 1467 goto out_free_irq; 1468 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1469 out_free_irq_nc_rx: 1470 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1471 out_free_irq_be_tx: 1472 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1473 out_free_irq_be_rx: 1474 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1475 out_free_irq_emac: 1476 free_irq(priv->emac_irq, ndev); 1477 out_free_irq: 1478 free_irq(ndev->irq, ndev); 1479 out_napi_off: 1480 napi_disable(&priv->napi[RAVB_NC]); 1481 napi_disable(&priv->napi[RAVB_BE]); 1482 return error; 1483 } 1484 1485 /* Timeout function for Ethernet AVB */ 1486 static void ravb_tx_timeout(struct net_device *ndev) 1487 { 1488 struct ravb_private *priv = netdev_priv(ndev); 1489 1490 netif_err(priv, tx_err, ndev, 1491 "transmit timed out, status %08x, resetting...\n", 1492 ravb_read(ndev, ISS)); 1493 1494 /* tx_errors count up */ 1495 ndev->stats.tx_errors++; 1496 1497 schedule_work(&priv->work); 1498 } 1499 1500 static void ravb_tx_timeout_work(struct work_struct *work) 1501 { 1502 struct ravb_private *priv = container_of(work, struct ravb_private, 1503 work); 1504 struct net_device *ndev = priv->ndev; 1505 1506 netif_tx_stop_all_queues(ndev); 1507 1508 /* Stop PTP Clock driver */ 1509 if (priv->chip_id == RCAR_GEN2) 1510 ravb_ptp_stop(ndev); 1511 1512 /* Wait for DMA stopping */ 1513 ravb_stop_dma(ndev); 1514 1515 ravb_ring_free(ndev, RAVB_BE); 1516 ravb_ring_free(ndev, RAVB_NC); 1517 1518 /* Device init */ 1519 ravb_dmac_init(ndev); 1520 ravb_emac_init(ndev); 1521 1522 /* Initialise PTP Clock driver */ 1523 if (priv->chip_id == RCAR_GEN2) 1524 ravb_ptp_init(ndev, priv->pdev); 1525 1526 netif_tx_start_all_queues(ndev); 1527 } 1528 1529 /* Packet transmit function for Ethernet AVB */ 1530 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1531 { 1532 struct ravb_private *priv = netdev_priv(ndev); 1533 u16 q = skb_get_queue_mapping(skb); 1534 struct ravb_tstamp_skb *ts_skb; 1535 struct ravb_tx_desc *desc; 1536 unsigned long flags; 1537 u32 dma_addr; 1538 void *buffer; 1539 u32 entry; 1540 u32 len; 1541 1542 spin_lock_irqsave(&priv->lock, flags); 1543 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1544 NUM_TX_DESC) { 1545 netif_err(priv, tx_queued, ndev, 1546 "still transmitting with the full ring!\n"); 1547 netif_stop_subqueue(ndev, q); 1548 spin_unlock_irqrestore(&priv->lock, flags); 1549 return NETDEV_TX_BUSY; 1550 } 1551 1552 if (skb_put_padto(skb, ETH_ZLEN)) 1553 goto exit; 1554 1555 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); 1556 priv->tx_skb[q][entry / NUM_TX_DESC] = skb; 1557 1558 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1559 entry / NUM_TX_DESC * DPTR_ALIGN; 1560 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1561 /* Zero length DMA descriptors are problematic as they seem to 1562 * terminate DMA transfers. Avoid them by simply using a length of 1563 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN. 1564 * 1565 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of 1566 * data by the call to skb_put_padto() above this is safe with 1567 * respect to both the length of the first DMA descriptor (len) 1568 * overflowing the available data and the length of the second DMA 1569 * descriptor (skb->len - len) being negative. 1570 */ 1571 if (len == 0) 1572 len = DPTR_ALIGN; 1573 1574 memcpy(buffer, skb->data, len); 1575 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1576 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1577 goto drop; 1578 1579 desc = &priv->tx_ring[q][entry]; 1580 desc->ds_tagl = cpu_to_le16(len); 1581 desc->dptr = cpu_to_le32(dma_addr); 1582 1583 buffer = skb->data + len; 1584 len = skb->len - len; 1585 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1586 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1587 goto unmap; 1588 1589 desc++; 1590 desc->ds_tagl = cpu_to_le16(len); 1591 desc->dptr = cpu_to_le32(dma_addr); 1592 1593 /* TX timestamp required */ 1594 if (q == RAVB_NC) { 1595 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1596 if (!ts_skb) { 1597 desc--; 1598 dma_unmap_single(ndev->dev.parent, dma_addr, len, 1599 DMA_TO_DEVICE); 1600 goto unmap; 1601 } 1602 ts_skb->skb = skb; 1603 ts_skb->tag = priv->ts_skb_tag++; 1604 priv->ts_skb_tag &= 0x3ff; 1605 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1606 1607 /* TAG and timestamp required flag */ 1608 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1609 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1610 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12); 1611 } 1612 1613 skb_tx_timestamp(skb); 1614 /* Descriptor type must be set after all the above writes */ 1615 dma_wmb(); 1616 desc->die_dt = DT_FEND; 1617 desc--; 1618 desc->die_dt = DT_FSTART; 1619 1620 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1621 1622 priv->cur_tx[q] += NUM_TX_DESC; 1623 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1624 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && 1625 !ravb_tx_free(ndev, q, true)) 1626 netif_stop_subqueue(ndev, q); 1627 1628 exit: 1629 mmiowb(); 1630 spin_unlock_irqrestore(&priv->lock, flags); 1631 return NETDEV_TX_OK; 1632 1633 unmap: 1634 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1635 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1636 drop: 1637 dev_kfree_skb_any(skb); 1638 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; 1639 goto exit; 1640 } 1641 1642 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1643 void *accel_priv, select_queue_fallback_t fallback) 1644 { 1645 /* If skb needs TX timestamp, it is handled in network control queue */ 1646 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1647 RAVB_BE; 1648 1649 } 1650 1651 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1652 { 1653 struct ravb_private *priv = netdev_priv(ndev); 1654 struct net_device_stats *nstats, *stats0, *stats1; 1655 1656 nstats = &ndev->stats; 1657 stats0 = &priv->stats[RAVB_BE]; 1658 stats1 = &priv->stats[RAVB_NC]; 1659 1660 nstats->tx_dropped += ravb_read(ndev, TROCR); 1661 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1662 nstats->collisions += ravb_read(ndev, CDCR); 1663 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1664 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1665 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1666 1667 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1668 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1669 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1670 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1671 1672 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1673 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1674 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1675 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1676 nstats->multicast = stats0->multicast + stats1->multicast; 1677 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1678 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1679 nstats->rx_frame_errors = 1680 stats0->rx_frame_errors + stats1->rx_frame_errors; 1681 nstats->rx_length_errors = 1682 stats0->rx_length_errors + stats1->rx_length_errors; 1683 nstats->rx_missed_errors = 1684 stats0->rx_missed_errors + stats1->rx_missed_errors; 1685 nstats->rx_over_errors = 1686 stats0->rx_over_errors + stats1->rx_over_errors; 1687 1688 return nstats; 1689 } 1690 1691 /* Update promiscuous bit */ 1692 static void ravb_set_rx_mode(struct net_device *ndev) 1693 { 1694 struct ravb_private *priv = netdev_priv(ndev); 1695 unsigned long flags; 1696 1697 spin_lock_irqsave(&priv->lock, flags); 1698 ravb_modify(ndev, ECMR, ECMR_PRM, 1699 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1700 mmiowb(); 1701 spin_unlock_irqrestore(&priv->lock, flags); 1702 } 1703 1704 /* Device close function for Ethernet AVB */ 1705 static int ravb_close(struct net_device *ndev) 1706 { 1707 struct device_node *np = ndev->dev.parent->of_node; 1708 struct ravb_private *priv = netdev_priv(ndev); 1709 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1710 1711 netif_tx_stop_all_queues(ndev); 1712 1713 /* Disable interrupts by clearing the interrupt masks. */ 1714 ravb_write(ndev, 0, RIC0); 1715 ravb_write(ndev, 0, RIC2); 1716 ravb_write(ndev, 0, TIC); 1717 1718 /* Stop PTP Clock driver */ 1719 if (priv->chip_id == RCAR_GEN2) 1720 ravb_ptp_stop(ndev); 1721 1722 /* Set the config mode to stop the AVB-DMAC's processes */ 1723 if (ravb_stop_dma(ndev) < 0) 1724 netdev_err(ndev, 1725 "device will be stopped after h/w processes are done.\n"); 1726 1727 /* Clear the timestamp list */ 1728 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1729 list_del(&ts_skb->list); 1730 kfree(ts_skb); 1731 } 1732 1733 /* PHY disconnect */ 1734 if (ndev->phydev) { 1735 phy_stop(ndev->phydev); 1736 phy_disconnect(ndev->phydev); 1737 if (of_phy_is_fixed_link(np)) 1738 of_phy_deregister_fixed_link(np); 1739 } 1740 1741 if (priv->chip_id != RCAR_GEN2) { 1742 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1743 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1744 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1745 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1746 free_irq(priv->emac_irq, ndev); 1747 } 1748 free_irq(ndev->irq, ndev); 1749 1750 napi_disable(&priv->napi[RAVB_NC]); 1751 napi_disable(&priv->napi[RAVB_BE]); 1752 1753 /* Free all the skb's in the RX queue and the DMA buffers. */ 1754 ravb_ring_free(ndev, RAVB_BE); 1755 ravb_ring_free(ndev, RAVB_NC); 1756 1757 return 0; 1758 } 1759 1760 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1761 { 1762 struct ravb_private *priv = netdev_priv(ndev); 1763 struct hwtstamp_config config; 1764 1765 config.flags = 0; 1766 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1767 HWTSTAMP_TX_OFF; 1768 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1769 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1770 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1771 config.rx_filter = HWTSTAMP_FILTER_ALL; 1772 else 1773 config.rx_filter = HWTSTAMP_FILTER_NONE; 1774 1775 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1776 -EFAULT : 0; 1777 } 1778 1779 /* Control hardware time stamping */ 1780 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1781 { 1782 struct ravb_private *priv = netdev_priv(ndev); 1783 struct hwtstamp_config config; 1784 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1785 u32 tstamp_tx_ctrl; 1786 1787 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1788 return -EFAULT; 1789 1790 /* Reserved for future extensions */ 1791 if (config.flags) 1792 return -EINVAL; 1793 1794 switch (config.tx_type) { 1795 case HWTSTAMP_TX_OFF: 1796 tstamp_tx_ctrl = 0; 1797 break; 1798 case HWTSTAMP_TX_ON: 1799 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1800 break; 1801 default: 1802 return -ERANGE; 1803 } 1804 1805 switch (config.rx_filter) { 1806 case HWTSTAMP_FILTER_NONE: 1807 tstamp_rx_ctrl = 0; 1808 break; 1809 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1810 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1811 break; 1812 default: 1813 config.rx_filter = HWTSTAMP_FILTER_ALL; 1814 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1815 } 1816 1817 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1818 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1819 1820 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1821 -EFAULT : 0; 1822 } 1823 1824 /* ioctl to device function */ 1825 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1826 { 1827 struct phy_device *phydev = ndev->phydev; 1828 1829 if (!netif_running(ndev)) 1830 return -EINVAL; 1831 1832 if (!phydev) 1833 return -ENODEV; 1834 1835 switch (cmd) { 1836 case SIOCGHWTSTAMP: 1837 return ravb_hwtstamp_get(ndev, req); 1838 case SIOCSHWTSTAMP: 1839 return ravb_hwtstamp_set(ndev, req); 1840 } 1841 1842 return phy_mii_ioctl(phydev, req, cmd); 1843 } 1844 1845 static const struct net_device_ops ravb_netdev_ops = { 1846 .ndo_open = ravb_open, 1847 .ndo_stop = ravb_close, 1848 .ndo_start_xmit = ravb_start_xmit, 1849 .ndo_select_queue = ravb_select_queue, 1850 .ndo_get_stats = ravb_get_stats, 1851 .ndo_set_rx_mode = ravb_set_rx_mode, 1852 .ndo_tx_timeout = ravb_tx_timeout, 1853 .ndo_do_ioctl = ravb_do_ioctl, 1854 .ndo_validate_addr = eth_validate_addr, 1855 .ndo_set_mac_address = eth_mac_addr, 1856 }; 1857 1858 /* MDIO bus init function */ 1859 static int ravb_mdio_init(struct ravb_private *priv) 1860 { 1861 struct platform_device *pdev = priv->pdev; 1862 struct device *dev = &pdev->dev; 1863 int error; 1864 1865 /* Bitbang init */ 1866 priv->mdiobb.ops = &bb_ops; 1867 1868 /* MII controller setting */ 1869 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1870 if (!priv->mii_bus) 1871 return -ENOMEM; 1872 1873 /* Hook up MII support for ethtool */ 1874 priv->mii_bus->name = "ravb_mii"; 1875 priv->mii_bus->parent = dev; 1876 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1877 pdev->name, pdev->id); 1878 1879 /* Register MDIO bus */ 1880 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1881 if (error) 1882 goto out_free_bus; 1883 1884 return 0; 1885 1886 out_free_bus: 1887 free_mdio_bitbang(priv->mii_bus); 1888 return error; 1889 } 1890 1891 /* MDIO bus release function */ 1892 static int ravb_mdio_release(struct ravb_private *priv) 1893 { 1894 /* Unregister mdio bus */ 1895 mdiobus_unregister(priv->mii_bus); 1896 1897 /* Free bitbang info */ 1898 free_mdio_bitbang(priv->mii_bus); 1899 1900 return 0; 1901 } 1902 1903 static const struct of_device_id ravb_match_table[] = { 1904 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1905 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1906 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1907 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1908 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1909 { } 1910 }; 1911 MODULE_DEVICE_TABLE(of, ravb_match_table); 1912 1913 static int ravb_set_gti(struct net_device *ndev) 1914 { 1915 1916 struct device *dev = ndev->dev.parent; 1917 struct device_node *np = dev->of_node; 1918 unsigned long rate; 1919 struct clk *clk; 1920 uint64_t inc; 1921 1922 clk = of_clk_get(np, 0); 1923 if (IS_ERR(clk)) { 1924 dev_err(dev, "could not get clock\n"); 1925 return PTR_ERR(clk); 1926 } 1927 1928 rate = clk_get_rate(clk); 1929 clk_put(clk); 1930 1931 if (!rate) 1932 return -EINVAL; 1933 1934 inc = 1000000000ULL << 20; 1935 do_div(inc, rate); 1936 1937 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1938 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1939 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1940 return -EINVAL; 1941 } 1942 1943 ravb_write(ndev, inc, GTI); 1944 1945 return 0; 1946 } 1947 1948 static void ravb_set_config_mode(struct net_device *ndev) 1949 { 1950 struct ravb_private *priv = netdev_priv(ndev); 1951 1952 if (priv->chip_id == RCAR_GEN2) { 1953 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1954 /* Set CSEL value */ 1955 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1956 } else { 1957 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1958 CCC_GAC | CCC_CSEL_HPB); 1959 } 1960 } 1961 1962 /* Set tx and rx clock internal delay modes */ 1963 static void ravb_set_delay_mode(struct net_device *ndev) 1964 { 1965 struct ravb_private *priv = netdev_priv(ndev); 1966 int set = 0; 1967 1968 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1969 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1970 set |= APSR_DM_RDM; 1971 1972 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1973 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1974 set |= APSR_DM_TDM; 1975 1976 ravb_modify(ndev, APSR, APSR_DM, set); 1977 } 1978 1979 static int ravb_probe(struct platform_device *pdev) 1980 { 1981 struct device_node *np = pdev->dev.of_node; 1982 struct ravb_private *priv; 1983 enum ravb_chip_id chip_id; 1984 struct net_device *ndev; 1985 int error, irq, q; 1986 struct resource *res; 1987 int i; 1988 1989 if (!np) { 1990 dev_err(&pdev->dev, 1991 "this driver is required to be instantiated from device tree\n"); 1992 return -EINVAL; 1993 } 1994 1995 /* Get base address */ 1996 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1997 if (!res) { 1998 dev_err(&pdev->dev, "invalid resource\n"); 1999 return -EINVAL; 2000 } 2001 2002 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2003 NUM_TX_QUEUE, NUM_RX_QUEUE); 2004 if (!ndev) 2005 return -ENOMEM; 2006 2007 pm_runtime_enable(&pdev->dev); 2008 pm_runtime_get_sync(&pdev->dev); 2009 2010 /* The Ether-specific entries in the device structure. */ 2011 ndev->base_addr = res->start; 2012 2013 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2014 2015 if (chip_id == RCAR_GEN3) 2016 irq = platform_get_irq_byname(pdev, "ch22"); 2017 else 2018 irq = platform_get_irq(pdev, 0); 2019 if (irq < 0) { 2020 error = irq; 2021 goto out_release; 2022 } 2023 ndev->irq = irq; 2024 2025 SET_NETDEV_DEV(ndev, &pdev->dev); 2026 2027 priv = netdev_priv(ndev); 2028 priv->ndev = ndev; 2029 priv->pdev = pdev; 2030 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2031 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2032 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2033 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2034 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2035 if (IS_ERR(priv->addr)) { 2036 error = PTR_ERR(priv->addr); 2037 goto out_release; 2038 } 2039 2040 spin_lock_init(&priv->lock); 2041 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2042 2043 priv->phy_interface = of_get_phy_mode(np); 2044 2045 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2046 priv->avb_link_active_low = 2047 of_property_read_bool(np, "renesas,ether-link-active-low"); 2048 2049 if (chip_id == RCAR_GEN3) { 2050 irq = platform_get_irq_byname(pdev, "ch24"); 2051 if (irq < 0) { 2052 error = irq; 2053 goto out_release; 2054 } 2055 priv->emac_irq = irq; 2056 for (i = 0; i < NUM_RX_QUEUE; i++) { 2057 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2058 if (irq < 0) { 2059 error = irq; 2060 goto out_release; 2061 } 2062 priv->rx_irqs[i] = irq; 2063 } 2064 for (i = 0; i < NUM_TX_QUEUE; i++) { 2065 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2066 if (irq < 0) { 2067 error = irq; 2068 goto out_release; 2069 } 2070 priv->tx_irqs[i] = irq; 2071 } 2072 } 2073 2074 priv->chip_id = chip_id; 2075 2076 /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */ 2077 priv->clk = devm_clk_get(&pdev->dev, NULL); 2078 if (IS_ERR(priv->clk)) 2079 priv->clk = NULL; 2080 2081 /* Set function */ 2082 ndev->netdev_ops = &ravb_netdev_ops; 2083 ndev->ethtool_ops = &ravb_ethtool_ops; 2084 2085 /* Set AVB config mode */ 2086 ravb_set_config_mode(ndev); 2087 2088 /* Set GTI value */ 2089 error = ravb_set_gti(ndev); 2090 if (error) 2091 goto out_release; 2092 2093 /* Request GTI loading */ 2094 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2095 2096 if (priv->chip_id != RCAR_GEN2) 2097 ravb_set_delay_mode(ndev); 2098 2099 /* Allocate descriptor base address table */ 2100 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2101 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2102 &priv->desc_bat_dma, GFP_KERNEL); 2103 if (!priv->desc_bat) { 2104 dev_err(&pdev->dev, 2105 "Cannot allocate desc base address table (size %d bytes)\n", 2106 priv->desc_bat_size); 2107 error = -ENOMEM; 2108 goto out_release; 2109 } 2110 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2111 priv->desc_bat[q].die_dt = DT_EOS; 2112 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2113 2114 /* Initialise HW timestamp list */ 2115 INIT_LIST_HEAD(&priv->ts_skb_list); 2116 2117 /* Initialise PTP Clock driver */ 2118 if (chip_id != RCAR_GEN2) 2119 ravb_ptp_init(ndev, pdev); 2120 2121 /* Debug message level */ 2122 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2123 2124 /* Read and set MAC address */ 2125 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2126 if (!is_valid_ether_addr(ndev->dev_addr)) { 2127 dev_warn(&pdev->dev, 2128 "no valid MAC address supplied, using a random one\n"); 2129 eth_hw_addr_random(ndev); 2130 } 2131 2132 /* MDIO bus init */ 2133 error = ravb_mdio_init(priv); 2134 if (error) { 2135 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2136 goto out_dma_free; 2137 } 2138 2139 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2140 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2141 2142 /* Network device register */ 2143 error = register_netdev(ndev); 2144 if (error) 2145 goto out_napi_del; 2146 2147 if (priv->clk) 2148 device_set_wakeup_capable(&pdev->dev, 1); 2149 2150 /* Print device information */ 2151 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2152 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2153 2154 platform_set_drvdata(pdev, ndev); 2155 2156 return 0; 2157 2158 out_napi_del: 2159 netif_napi_del(&priv->napi[RAVB_NC]); 2160 netif_napi_del(&priv->napi[RAVB_BE]); 2161 ravb_mdio_release(priv); 2162 out_dma_free: 2163 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2164 priv->desc_bat_dma); 2165 2166 /* Stop PTP Clock driver */ 2167 if (chip_id != RCAR_GEN2) 2168 ravb_ptp_stop(ndev); 2169 out_release: 2170 if (ndev) 2171 free_netdev(ndev); 2172 2173 pm_runtime_put(&pdev->dev); 2174 pm_runtime_disable(&pdev->dev); 2175 return error; 2176 } 2177 2178 static int ravb_remove(struct platform_device *pdev) 2179 { 2180 struct net_device *ndev = platform_get_drvdata(pdev); 2181 struct ravb_private *priv = netdev_priv(ndev); 2182 2183 /* Stop PTP Clock driver */ 2184 if (priv->chip_id != RCAR_GEN2) 2185 ravb_ptp_stop(ndev); 2186 2187 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2188 priv->desc_bat_dma); 2189 /* Set reset mode */ 2190 ravb_write(ndev, CCC_OPC_RESET, CCC); 2191 pm_runtime_put_sync(&pdev->dev); 2192 unregister_netdev(ndev); 2193 netif_napi_del(&priv->napi[RAVB_NC]); 2194 netif_napi_del(&priv->napi[RAVB_BE]); 2195 ravb_mdio_release(priv); 2196 pm_runtime_disable(&pdev->dev); 2197 free_netdev(ndev); 2198 platform_set_drvdata(pdev, NULL); 2199 2200 return 0; 2201 } 2202 2203 static int ravb_wol_setup(struct net_device *ndev) 2204 { 2205 struct ravb_private *priv = netdev_priv(ndev); 2206 2207 /* Disable interrupts by clearing the interrupt masks. */ 2208 ravb_write(ndev, 0, RIC0); 2209 ravb_write(ndev, 0, RIC2); 2210 ravb_write(ndev, 0, TIC); 2211 2212 /* Only allow ECI interrupts */ 2213 synchronize_irq(priv->emac_irq); 2214 napi_disable(&priv->napi[RAVB_NC]); 2215 napi_disable(&priv->napi[RAVB_BE]); 2216 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2217 2218 /* Enable MagicPacket */ 2219 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2220 2221 /* Increased clock usage so device won't be suspended */ 2222 clk_enable(priv->clk); 2223 2224 return enable_irq_wake(priv->emac_irq); 2225 } 2226 2227 static int ravb_wol_restore(struct net_device *ndev) 2228 { 2229 struct ravb_private *priv = netdev_priv(ndev); 2230 int ret; 2231 2232 napi_enable(&priv->napi[RAVB_NC]); 2233 napi_enable(&priv->napi[RAVB_BE]); 2234 2235 /* Disable MagicPacket */ 2236 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2237 2238 ret = ravb_close(ndev); 2239 if (ret < 0) 2240 return ret; 2241 2242 /* Restore clock usage count */ 2243 clk_disable(priv->clk); 2244 2245 return disable_irq_wake(priv->emac_irq); 2246 } 2247 2248 static int __maybe_unused ravb_suspend(struct device *dev) 2249 { 2250 struct net_device *ndev = dev_get_drvdata(dev); 2251 struct ravb_private *priv = netdev_priv(ndev); 2252 int ret; 2253 2254 if (!netif_running(ndev)) 2255 return 0; 2256 2257 netif_device_detach(ndev); 2258 2259 if (priv->wol_enabled) 2260 ret = ravb_wol_setup(ndev); 2261 else 2262 ret = ravb_close(ndev); 2263 2264 return ret; 2265 } 2266 2267 static int __maybe_unused ravb_resume(struct device *dev) 2268 { 2269 struct net_device *ndev = dev_get_drvdata(dev); 2270 struct ravb_private *priv = netdev_priv(ndev); 2271 int ret = 0; 2272 2273 if (priv->wol_enabled) { 2274 /* Reduce the usecount of the clock to zero and then 2275 * restore it to its original value. This is done to force 2276 * the clock to be re-enabled which is a workaround 2277 * for renesas-cpg-mssr driver which do not enable clocks 2278 * when resuming from PSCI suspend/resume. 2279 * 2280 * Without this workaround the driver fails to communicate 2281 * with the hardware if WoL was enabled when the system 2282 * entered PSCI suspend. This is due to that if WoL is enabled 2283 * we explicitly keep the clock from being turned off when 2284 * suspending, but in PSCI sleep power is cut so the clock 2285 * is disabled anyhow, the clock driver is not aware of this 2286 * so the clock is not turned back on when resuming. 2287 * 2288 * TODO: once the renesas-cpg-mssr suspend/resume is working 2289 * this clock dance should be removed. 2290 */ 2291 clk_disable(priv->clk); 2292 clk_disable(priv->clk); 2293 clk_enable(priv->clk); 2294 clk_enable(priv->clk); 2295 2296 /* Set reset mode to rearm the WoL logic */ 2297 ravb_write(ndev, CCC_OPC_RESET, CCC); 2298 } 2299 2300 /* All register have been reset to default values. 2301 * Restore all registers which where setup at probe time and 2302 * reopen device if it was running before system suspended. 2303 */ 2304 2305 /* Set AVB config mode */ 2306 ravb_set_config_mode(ndev); 2307 2308 /* Set GTI value */ 2309 ret = ravb_set_gti(ndev); 2310 if (ret) 2311 return ret; 2312 2313 /* Request GTI loading */ 2314 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2315 2316 if (priv->chip_id != RCAR_GEN2) 2317 ravb_set_delay_mode(ndev); 2318 2319 /* Restore descriptor base address table */ 2320 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2321 2322 if (netif_running(ndev)) { 2323 if (priv->wol_enabled) { 2324 ret = ravb_wol_restore(ndev); 2325 if (ret) 2326 return ret; 2327 } 2328 ret = ravb_open(ndev); 2329 if (ret < 0) 2330 return ret; 2331 netif_device_attach(ndev); 2332 } 2333 2334 return ret; 2335 } 2336 2337 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2338 { 2339 /* Runtime PM callback shared between ->runtime_suspend() 2340 * and ->runtime_resume(). Simply returns success. 2341 * 2342 * This driver re-initializes all registers after 2343 * pm_runtime_get_sync() anyway so there is no need 2344 * to save and restore registers here. 2345 */ 2346 return 0; 2347 } 2348 2349 static const struct dev_pm_ops ravb_dev_pm_ops = { 2350 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2351 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2352 }; 2353 2354 static struct platform_driver ravb_driver = { 2355 .probe = ravb_probe, 2356 .remove = ravb_remove, 2357 .driver = { 2358 .name = "ravb", 2359 .pm = &ravb_dev_pm_ops, 2360 .of_match_table = ravb_match_table, 2361 }, 2362 }; 2363 2364 module_platform_driver(ravb_driver); 2365 2366 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2367 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2368 MODULE_LICENSE("GPL v2"); 2369