1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2015 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 33 #include <asm/div64.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 44 "ch0", /* RAVB_BE */ 45 "ch1", /* RAVB_NC */ 46 }; 47 48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 49 "ch18", /* RAVB_BE */ 50 "ch19", /* RAVB_NC */ 51 }; 52 53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 54 u32 set) 55 { 56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 57 } 58 59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 60 { 61 int i; 62 63 for (i = 0; i < 10000; i++) { 64 if ((ravb_read(ndev, reg) & mask) == value) 65 return 0; 66 udelay(10); 67 } 68 return -ETIMEDOUT; 69 } 70 71 static int ravb_config(struct net_device *ndev) 72 { 73 int error; 74 75 /* Set config mode */ 76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 77 /* Check if the operating mode is changed to the config mode */ 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 79 if (error) 80 netdev_err(ndev, "failed to switch device to config mode\n"); 81 82 return error; 83 } 84 85 static void ravb_set_rate(struct net_device *ndev) 86 { 87 struct ravb_private *priv = netdev_priv(ndev); 88 89 switch (priv->speed) { 90 case 100: /* 100BASE */ 91 ravb_write(ndev, GECMR_SPEED_100, GECMR); 92 break; 93 case 1000: /* 1000BASE */ 94 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 95 break; 96 } 97 } 98 99 static void ravb_set_buffer_align(struct sk_buff *skb) 100 { 101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 102 103 if (reserve) 104 skb_reserve(skb, RAVB_ALIGN - reserve); 105 } 106 107 /* Get MAC address from the MAC address registers 108 * 109 * Ethernet AVB device doesn't have ROM for MAC address. 110 * This function gets the MAC address that was used by a bootloader. 111 */ 112 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 113 { 114 if (mac) { 115 ether_addr_copy(ndev->dev_addr, mac); 116 } else { 117 u32 mahr = ravb_read(ndev, MAHR); 118 u32 malr = ravb_read(ndev, MALR); 119 120 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 121 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 122 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 123 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 124 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 125 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 126 } 127 } 128 129 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 130 { 131 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 132 mdiobb); 133 134 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 135 } 136 137 /* MDC pin control */ 138 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 139 { 140 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 141 } 142 143 /* Data I/O pin control */ 144 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 145 { 146 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 147 } 148 149 /* Set data bit */ 150 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 151 { 152 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 153 } 154 155 /* Get data bit */ 156 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 157 { 158 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 159 mdiobb); 160 161 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 162 } 163 164 /* MDIO bus control struct */ 165 static struct mdiobb_ops bb_ops = { 166 .owner = THIS_MODULE, 167 .set_mdc = ravb_set_mdc, 168 .set_mdio_dir = ravb_set_mdio_dir, 169 .set_mdio_data = ravb_set_mdio_data, 170 .get_mdio_data = ravb_get_mdio_data, 171 }; 172 173 /* Free TX skb function for AVB-IP */ 174 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 175 { 176 struct ravb_private *priv = netdev_priv(ndev); 177 struct net_device_stats *stats = &priv->stats[q]; 178 int num_tx_desc = priv->num_tx_desc; 179 struct ravb_tx_desc *desc; 180 int free_num = 0; 181 int entry; 182 u32 size; 183 184 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 185 bool txed; 186 187 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 188 num_tx_desc); 189 desc = &priv->tx_ring[q][entry]; 190 txed = desc->die_dt == DT_FEMPTY; 191 if (free_txed_only && !txed) 192 break; 193 /* Descriptor type must be checked before all other reads */ 194 dma_rmb(); 195 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 196 /* Free the original skb. */ 197 if (priv->tx_skb[q][entry / num_tx_desc]) { 198 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 199 size, DMA_TO_DEVICE); 200 /* Last packet descriptor? */ 201 if (entry % num_tx_desc == num_tx_desc - 1) { 202 entry /= num_tx_desc; 203 dev_kfree_skb_any(priv->tx_skb[q][entry]); 204 priv->tx_skb[q][entry] = NULL; 205 if (txed) 206 stats->tx_packets++; 207 } 208 free_num++; 209 } 210 if (txed) 211 stats->tx_bytes += size; 212 desc->die_dt = DT_EEMPTY; 213 } 214 return free_num; 215 } 216 217 /* Free skb's and DMA buffers for Ethernet AVB */ 218 static void ravb_ring_free(struct net_device *ndev, int q) 219 { 220 struct ravb_private *priv = netdev_priv(ndev); 221 int num_tx_desc = priv->num_tx_desc; 222 int ring_size; 223 int i; 224 225 if (priv->rx_ring[q]) { 226 for (i = 0; i < priv->num_rx_ring[q]; i++) { 227 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 228 229 if (!dma_mapping_error(ndev->dev.parent, 230 le32_to_cpu(desc->dptr))) 231 dma_unmap_single(ndev->dev.parent, 232 le32_to_cpu(desc->dptr), 233 priv->rx_buf_sz, 234 DMA_FROM_DEVICE); 235 } 236 ring_size = sizeof(struct ravb_ex_rx_desc) * 237 (priv->num_rx_ring[q] + 1); 238 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 239 priv->rx_desc_dma[q]); 240 priv->rx_ring[q] = NULL; 241 } 242 243 if (priv->tx_ring[q]) { 244 ravb_tx_free(ndev, q, false); 245 246 ring_size = sizeof(struct ravb_tx_desc) * 247 (priv->num_tx_ring[q] * num_tx_desc + 1); 248 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 249 priv->tx_desc_dma[q]); 250 priv->tx_ring[q] = NULL; 251 } 252 253 /* Free RX skb ringbuffer */ 254 if (priv->rx_skb[q]) { 255 for (i = 0; i < priv->num_rx_ring[q]; i++) 256 dev_kfree_skb(priv->rx_skb[q][i]); 257 } 258 kfree(priv->rx_skb[q]); 259 priv->rx_skb[q] = NULL; 260 261 /* Free aligned TX buffers */ 262 kfree(priv->tx_align[q]); 263 priv->tx_align[q] = NULL; 264 265 /* Free TX skb ringbuffer. 266 * SKBs are freed by ravb_tx_free() call above. 267 */ 268 kfree(priv->tx_skb[q]); 269 priv->tx_skb[q] = NULL; 270 } 271 272 /* Format skb and descriptor buffer for Ethernet AVB */ 273 static void ravb_ring_format(struct net_device *ndev, int q) 274 { 275 struct ravb_private *priv = netdev_priv(ndev); 276 int num_tx_desc = priv->num_tx_desc; 277 struct ravb_ex_rx_desc *rx_desc; 278 struct ravb_tx_desc *tx_desc; 279 struct ravb_desc *desc; 280 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 281 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 282 num_tx_desc; 283 dma_addr_t dma_addr; 284 int i; 285 286 priv->cur_rx[q] = 0; 287 priv->cur_tx[q] = 0; 288 priv->dirty_rx[q] = 0; 289 priv->dirty_tx[q] = 0; 290 291 memset(priv->rx_ring[q], 0, rx_ring_size); 292 /* Build RX ring buffer */ 293 for (i = 0; i < priv->num_rx_ring[q]; i++) { 294 /* RX descriptor */ 295 rx_desc = &priv->rx_ring[q][i]; 296 rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 297 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 298 priv->rx_buf_sz, 299 DMA_FROM_DEVICE); 300 /* We just set the data size to 0 for a failed mapping which 301 * should prevent DMA from happening... 302 */ 303 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 304 rx_desc->ds_cc = cpu_to_le16(0); 305 rx_desc->dptr = cpu_to_le32(dma_addr); 306 rx_desc->die_dt = DT_FEMPTY; 307 } 308 rx_desc = &priv->rx_ring[q][i]; 309 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 310 rx_desc->die_dt = DT_LINKFIX; /* type */ 311 312 memset(priv->tx_ring[q], 0, tx_ring_size); 313 /* Build TX ring buffer */ 314 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 315 i++, tx_desc++) { 316 tx_desc->die_dt = DT_EEMPTY; 317 if (num_tx_desc > 1) { 318 tx_desc++; 319 tx_desc->die_dt = DT_EEMPTY; 320 } 321 } 322 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 323 tx_desc->die_dt = DT_LINKFIX; /* type */ 324 325 /* RX descriptor base address for best effort */ 326 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 327 desc->die_dt = DT_LINKFIX; /* type */ 328 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 329 330 /* TX descriptor base address for best effort */ 331 desc = &priv->desc_bat[q]; 332 desc->die_dt = DT_LINKFIX; /* type */ 333 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 334 } 335 336 /* Init skb and descriptor buffer for Ethernet AVB */ 337 static int ravb_ring_init(struct net_device *ndev, int q) 338 { 339 struct ravb_private *priv = netdev_priv(ndev); 340 int num_tx_desc = priv->num_tx_desc; 341 struct sk_buff *skb; 342 int ring_size; 343 int i; 344 345 priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) + 346 ETH_HLEN + VLAN_HLEN; 347 348 /* Allocate RX and TX skb rings */ 349 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 350 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 351 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 352 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 353 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 354 goto error; 355 356 for (i = 0; i < priv->num_rx_ring[q]; i++) { 357 skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1); 358 if (!skb) 359 goto error; 360 ravb_set_buffer_align(skb); 361 priv->rx_skb[q][i] = skb; 362 } 363 364 if (num_tx_desc > 1) { 365 /* Allocate rings for the aligned buffers */ 366 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 367 DPTR_ALIGN - 1, GFP_KERNEL); 368 if (!priv->tx_align[q]) 369 goto error; 370 } 371 372 /* Allocate all RX descriptors. */ 373 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 374 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 375 &priv->rx_desc_dma[q], 376 GFP_KERNEL); 377 if (!priv->rx_ring[q]) 378 goto error; 379 380 priv->dirty_rx[q] = 0; 381 382 /* Allocate all TX descriptors. */ 383 ring_size = sizeof(struct ravb_tx_desc) * 384 (priv->num_tx_ring[q] * num_tx_desc + 1); 385 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 386 &priv->tx_desc_dma[q], 387 GFP_KERNEL); 388 if (!priv->tx_ring[q]) 389 goto error; 390 391 return 0; 392 393 error: 394 ravb_ring_free(ndev, q); 395 396 return -ENOMEM; 397 } 398 399 /* E-MAC init function */ 400 static void ravb_emac_init(struct net_device *ndev) 401 { 402 /* Receive frame limit set register */ 403 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 404 405 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 406 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 407 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 408 ECMR_TE | ECMR_RE, ECMR); 409 410 ravb_set_rate(ndev); 411 412 /* Set MAC address */ 413 ravb_write(ndev, 414 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 415 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 416 ravb_write(ndev, 417 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 418 419 /* E-MAC status register clear */ 420 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 421 422 /* E-MAC interrupt enable register */ 423 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 424 } 425 426 /* Device init function for Ethernet AVB */ 427 static int ravb_dmac_init(struct net_device *ndev) 428 { 429 struct ravb_private *priv = netdev_priv(ndev); 430 int error; 431 432 /* Set CONFIG mode */ 433 error = ravb_config(ndev); 434 if (error) 435 return error; 436 437 error = ravb_ring_init(ndev, RAVB_BE); 438 if (error) 439 return error; 440 error = ravb_ring_init(ndev, RAVB_NC); 441 if (error) { 442 ravb_ring_free(ndev, RAVB_BE); 443 return error; 444 } 445 446 /* Descriptor format */ 447 ravb_ring_format(ndev, RAVB_BE); 448 ravb_ring_format(ndev, RAVB_NC); 449 450 #if defined(__LITTLE_ENDIAN) 451 ravb_modify(ndev, CCC, CCC_BOC, 0); 452 #else 453 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 454 #endif 455 456 /* Set AVB RX */ 457 ravb_write(ndev, 458 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 459 460 /* Set FIFO size */ 461 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 462 463 /* Timestamp enable */ 464 ravb_write(ndev, TCCR_TFEN, TCCR); 465 466 /* Interrupt init: */ 467 if (priv->chip_id == RCAR_GEN3) { 468 /* Clear DIL.DPLx */ 469 ravb_write(ndev, 0, DIL); 470 /* Set queue specific interrupt */ 471 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 472 } 473 /* Frame receive */ 474 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 475 /* Disable FIFO full warning */ 476 ravb_write(ndev, 0, RIC1); 477 /* Receive FIFO full error, descriptor empty */ 478 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 479 /* Frame transmitted, timestamp FIFO updated */ 480 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 481 482 /* Setting the control will start the AVB-DMAC process. */ 483 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 484 485 return 0; 486 } 487 488 static void ravb_get_tx_tstamp(struct net_device *ndev) 489 { 490 struct ravb_private *priv = netdev_priv(ndev); 491 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 492 struct skb_shared_hwtstamps shhwtstamps; 493 struct sk_buff *skb; 494 struct timespec64 ts; 495 u16 tag, tfa_tag; 496 int count; 497 u32 tfa2; 498 499 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 500 while (count--) { 501 tfa2 = ravb_read(ndev, TFA2); 502 tfa_tag = (tfa2 & TFA2_TST) >> 16; 503 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 504 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 505 ravb_read(ndev, TFA1); 506 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 507 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 508 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 509 list) { 510 skb = ts_skb->skb; 511 tag = ts_skb->tag; 512 list_del(&ts_skb->list); 513 kfree(ts_skb); 514 if (tag == tfa_tag) { 515 skb_tstamp_tx(skb, &shhwtstamps); 516 break; 517 } 518 } 519 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 520 } 521 } 522 523 static void ravb_rx_csum(struct sk_buff *skb) 524 { 525 u8 *hw_csum; 526 527 /* The hardware checksum is 2 bytes appended to packet data */ 528 if (unlikely(skb->len < 2)) 529 return; 530 hw_csum = skb_tail_pointer(skb) - 2; 531 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 532 skb->ip_summed = CHECKSUM_COMPLETE; 533 skb_trim(skb, skb->len - 2); 534 } 535 536 /* Packet receive function for Ethernet AVB */ 537 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 538 { 539 struct ravb_private *priv = netdev_priv(ndev); 540 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 541 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 542 priv->cur_rx[q]; 543 struct net_device_stats *stats = &priv->stats[q]; 544 struct ravb_ex_rx_desc *desc; 545 struct sk_buff *skb; 546 dma_addr_t dma_addr; 547 struct timespec64 ts; 548 u8 desc_status; 549 u16 pkt_len; 550 int limit; 551 552 boguscnt = min(boguscnt, *quota); 553 limit = boguscnt; 554 desc = &priv->rx_ring[q][entry]; 555 while (desc->die_dt != DT_FEMPTY) { 556 /* Descriptor type must be checked before all other reads */ 557 dma_rmb(); 558 desc_status = desc->msc; 559 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 560 561 if (--boguscnt < 0) 562 break; 563 564 /* We use 0-byte descriptors to mark the DMA mapping errors */ 565 if (!pkt_len) 566 continue; 567 568 if (desc_status & MSC_MC) 569 stats->multicast++; 570 571 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 572 MSC_CEEF)) { 573 stats->rx_errors++; 574 if (desc_status & MSC_CRC) 575 stats->rx_crc_errors++; 576 if (desc_status & MSC_RFE) 577 stats->rx_frame_errors++; 578 if (desc_status & (MSC_RTLF | MSC_RTSF)) 579 stats->rx_length_errors++; 580 if (desc_status & MSC_CEEF) 581 stats->rx_missed_errors++; 582 } else { 583 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 584 585 skb = priv->rx_skb[q][entry]; 586 priv->rx_skb[q][entry] = NULL; 587 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 588 priv->rx_buf_sz, 589 DMA_FROM_DEVICE); 590 get_ts &= (q == RAVB_NC) ? 591 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 592 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 593 if (get_ts) { 594 struct skb_shared_hwtstamps *shhwtstamps; 595 596 shhwtstamps = skb_hwtstamps(skb); 597 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 598 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 599 32) | le32_to_cpu(desc->ts_sl); 600 ts.tv_nsec = le32_to_cpu(desc->ts_n); 601 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 602 } 603 604 skb_put(skb, pkt_len); 605 skb->protocol = eth_type_trans(skb, ndev); 606 if (ndev->features & NETIF_F_RXCSUM) 607 ravb_rx_csum(skb); 608 napi_gro_receive(&priv->napi[q], skb); 609 stats->rx_packets++; 610 stats->rx_bytes += pkt_len; 611 } 612 613 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 614 desc = &priv->rx_ring[q][entry]; 615 } 616 617 /* Refill the RX ring buffers. */ 618 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 619 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 620 desc = &priv->rx_ring[q][entry]; 621 desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 622 623 if (!priv->rx_skb[q][entry]) { 624 skb = netdev_alloc_skb(ndev, 625 priv->rx_buf_sz + 626 RAVB_ALIGN - 1); 627 if (!skb) 628 break; /* Better luck next round. */ 629 ravb_set_buffer_align(skb); 630 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 631 le16_to_cpu(desc->ds_cc), 632 DMA_FROM_DEVICE); 633 skb_checksum_none_assert(skb); 634 /* We just set the data size to 0 for a failed mapping 635 * which should prevent DMA from happening... 636 */ 637 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 638 desc->ds_cc = cpu_to_le16(0); 639 desc->dptr = cpu_to_le32(dma_addr); 640 priv->rx_skb[q][entry] = skb; 641 } 642 /* Descriptor type must be set after all the above writes */ 643 dma_wmb(); 644 desc->die_dt = DT_FEMPTY; 645 } 646 647 *quota -= limit - (++boguscnt); 648 649 return boguscnt <= 0; 650 } 651 652 static void ravb_rcv_snd_disable(struct net_device *ndev) 653 { 654 /* Disable TX and RX */ 655 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 656 } 657 658 static void ravb_rcv_snd_enable(struct net_device *ndev) 659 { 660 /* Enable TX and RX */ 661 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 662 } 663 664 /* function for waiting dma process finished */ 665 static int ravb_stop_dma(struct net_device *ndev) 666 { 667 int error; 668 669 /* Wait for stopping the hardware TX process */ 670 error = ravb_wait(ndev, TCCR, 671 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 672 if (error) 673 return error; 674 675 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 676 0); 677 if (error) 678 return error; 679 680 /* Stop the E-MAC's RX/TX processes. */ 681 ravb_rcv_snd_disable(ndev); 682 683 /* Wait for stopping the RX DMA process */ 684 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 685 if (error) 686 return error; 687 688 /* Stop AVB-DMAC process */ 689 return ravb_config(ndev); 690 } 691 692 /* E-MAC interrupt handler */ 693 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 694 { 695 struct ravb_private *priv = netdev_priv(ndev); 696 u32 ecsr, psr; 697 698 ecsr = ravb_read(ndev, ECSR); 699 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 700 701 if (ecsr & ECSR_MPD) 702 pm_wakeup_event(&priv->pdev->dev, 0); 703 if (ecsr & ECSR_ICD) 704 ndev->stats.tx_carrier_errors++; 705 if (ecsr & ECSR_LCHNG) { 706 /* Link changed */ 707 if (priv->no_avb_link) 708 return; 709 psr = ravb_read(ndev, PSR); 710 if (priv->avb_link_active_low) 711 psr ^= PSR_LMON; 712 if (!(psr & PSR_LMON)) { 713 /* DIsable RX and TX */ 714 ravb_rcv_snd_disable(ndev); 715 } else { 716 /* Enable RX and TX */ 717 ravb_rcv_snd_enable(ndev); 718 } 719 } 720 } 721 722 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 723 { 724 struct net_device *ndev = dev_id; 725 struct ravb_private *priv = netdev_priv(ndev); 726 727 spin_lock(&priv->lock); 728 ravb_emac_interrupt_unlocked(ndev); 729 mmiowb(); 730 spin_unlock(&priv->lock); 731 return IRQ_HANDLED; 732 } 733 734 /* Error interrupt handler */ 735 static void ravb_error_interrupt(struct net_device *ndev) 736 { 737 struct ravb_private *priv = netdev_priv(ndev); 738 u32 eis, ris2; 739 740 eis = ravb_read(ndev, EIS); 741 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 742 if (eis & EIS_QFS) { 743 ris2 = ravb_read(ndev, RIS2); 744 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED), 745 RIS2); 746 747 /* Receive Descriptor Empty int */ 748 if (ris2 & RIS2_QFF0) 749 priv->stats[RAVB_BE].rx_over_errors++; 750 751 /* Receive Descriptor Empty int */ 752 if (ris2 & RIS2_QFF1) 753 priv->stats[RAVB_NC].rx_over_errors++; 754 755 /* Receive FIFO Overflow int */ 756 if (ris2 & RIS2_RFFF) 757 priv->rx_fifo_errors++; 758 } 759 } 760 761 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 762 { 763 struct ravb_private *priv = netdev_priv(ndev); 764 u32 ris0 = ravb_read(ndev, RIS0); 765 u32 ric0 = ravb_read(ndev, RIC0); 766 u32 tis = ravb_read(ndev, TIS); 767 u32 tic = ravb_read(ndev, TIC); 768 769 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 770 if (napi_schedule_prep(&priv->napi[q])) { 771 /* Mask RX and TX interrupts */ 772 if (priv->chip_id == RCAR_GEN2) { 773 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 774 ravb_write(ndev, tic & ~BIT(q), TIC); 775 } else { 776 ravb_write(ndev, BIT(q), RID0); 777 ravb_write(ndev, BIT(q), TID); 778 } 779 __napi_schedule(&priv->napi[q]); 780 } else { 781 netdev_warn(ndev, 782 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 783 ris0, ric0); 784 netdev_warn(ndev, 785 " tx status 0x%08x, tx mask 0x%08x.\n", 786 tis, tic); 787 } 788 return true; 789 } 790 return false; 791 } 792 793 static bool ravb_timestamp_interrupt(struct net_device *ndev) 794 { 795 u32 tis = ravb_read(ndev, TIS); 796 797 if (tis & TIS_TFUF) { 798 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 799 ravb_get_tx_tstamp(ndev); 800 return true; 801 } 802 return false; 803 } 804 805 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 806 { 807 struct net_device *ndev = dev_id; 808 struct ravb_private *priv = netdev_priv(ndev); 809 irqreturn_t result = IRQ_NONE; 810 u32 iss; 811 812 spin_lock(&priv->lock); 813 /* Get interrupt status */ 814 iss = ravb_read(ndev, ISS); 815 816 /* Received and transmitted interrupts */ 817 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 818 int q; 819 820 /* Timestamp updated */ 821 if (ravb_timestamp_interrupt(ndev)) 822 result = IRQ_HANDLED; 823 824 /* Network control and best effort queue RX/TX */ 825 for (q = RAVB_NC; q >= RAVB_BE; q--) { 826 if (ravb_queue_interrupt(ndev, q)) 827 result = IRQ_HANDLED; 828 } 829 } 830 831 /* E-MAC status summary */ 832 if (iss & ISS_MS) { 833 ravb_emac_interrupt_unlocked(ndev); 834 result = IRQ_HANDLED; 835 } 836 837 /* Error status summary */ 838 if (iss & ISS_ES) { 839 ravb_error_interrupt(ndev); 840 result = IRQ_HANDLED; 841 } 842 843 /* gPTP interrupt status summary */ 844 if (iss & ISS_CGIS) { 845 ravb_ptp_interrupt(ndev); 846 result = IRQ_HANDLED; 847 } 848 849 mmiowb(); 850 spin_unlock(&priv->lock); 851 return result; 852 } 853 854 /* Timestamp/Error/gPTP interrupt handler */ 855 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 856 { 857 struct net_device *ndev = dev_id; 858 struct ravb_private *priv = netdev_priv(ndev); 859 irqreturn_t result = IRQ_NONE; 860 u32 iss; 861 862 spin_lock(&priv->lock); 863 /* Get interrupt status */ 864 iss = ravb_read(ndev, ISS); 865 866 /* Timestamp updated */ 867 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 868 result = IRQ_HANDLED; 869 870 /* Error status summary */ 871 if (iss & ISS_ES) { 872 ravb_error_interrupt(ndev); 873 result = IRQ_HANDLED; 874 } 875 876 /* gPTP interrupt status summary */ 877 if (iss & ISS_CGIS) { 878 ravb_ptp_interrupt(ndev); 879 result = IRQ_HANDLED; 880 } 881 882 mmiowb(); 883 spin_unlock(&priv->lock); 884 return result; 885 } 886 887 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 888 { 889 struct net_device *ndev = dev_id; 890 struct ravb_private *priv = netdev_priv(ndev); 891 irqreturn_t result = IRQ_NONE; 892 893 spin_lock(&priv->lock); 894 895 /* Network control/Best effort queue RX/TX */ 896 if (ravb_queue_interrupt(ndev, q)) 897 result = IRQ_HANDLED; 898 899 mmiowb(); 900 spin_unlock(&priv->lock); 901 return result; 902 } 903 904 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 905 { 906 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 907 } 908 909 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 910 { 911 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 912 } 913 914 static int ravb_poll(struct napi_struct *napi, int budget) 915 { 916 struct net_device *ndev = napi->dev; 917 struct ravb_private *priv = netdev_priv(ndev); 918 unsigned long flags; 919 int q = napi - priv->napi; 920 int mask = BIT(q); 921 int quota = budget; 922 u32 ris0, tis; 923 924 for (;;) { 925 tis = ravb_read(ndev, TIS); 926 ris0 = ravb_read(ndev, RIS0); 927 if (!((ris0 & mask) || (tis & mask))) 928 break; 929 930 /* Processing RX Descriptor Ring */ 931 if (ris0 & mask) { 932 /* Clear RX interrupt */ 933 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 934 if (ravb_rx(ndev, "a, q)) 935 goto out; 936 } 937 /* Processing TX Descriptor Ring */ 938 if (tis & mask) { 939 spin_lock_irqsave(&priv->lock, flags); 940 /* Clear TX interrupt */ 941 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 942 ravb_tx_free(ndev, q, true); 943 netif_wake_subqueue(ndev, q); 944 mmiowb(); 945 spin_unlock_irqrestore(&priv->lock, flags); 946 } 947 } 948 949 napi_complete(napi); 950 951 /* Re-enable RX/TX interrupts */ 952 spin_lock_irqsave(&priv->lock, flags); 953 if (priv->chip_id == RCAR_GEN2) { 954 ravb_modify(ndev, RIC0, mask, mask); 955 ravb_modify(ndev, TIC, mask, mask); 956 } else { 957 ravb_write(ndev, mask, RIE0); 958 ravb_write(ndev, mask, TIE); 959 } 960 mmiowb(); 961 spin_unlock_irqrestore(&priv->lock, flags); 962 963 /* Receive error message handling */ 964 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 965 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 966 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 967 ndev->stats.rx_over_errors = priv->rx_over_errors; 968 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 969 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 970 out: 971 return budget - quota; 972 } 973 974 /* PHY state control function */ 975 static void ravb_adjust_link(struct net_device *ndev) 976 { 977 struct ravb_private *priv = netdev_priv(ndev); 978 struct phy_device *phydev = ndev->phydev; 979 bool new_state = false; 980 unsigned long flags; 981 982 spin_lock_irqsave(&priv->lock, flags); 983 984 /* Disable TX and RX right over here, if E-MAC change is ignored */ 985 if (priv->no_avb_link) 986 ravb_rcv_snd_disable(ndev); 987 988 if (phydev->link) { 989 if (phydev->speed != priv->speed) { 990 new_state = true; 991 priv->speed = phydev->speed; 992 ravb_set_rate(ndev); 993 } 994 if (!priv->link) { 995 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 996 new_state = true; 997 priv->link = phydev->link; 998 } 999 } else if (priv->link) { 1000 new_state = true; 1001 priv->link = 0; 1002 priv->speed = 0; 1003 } 1004 1005 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1006 if (priv->no_avb_link && phydev->link) 1007 ravb_rcv_snd_enable(ndev); 1008 1009 mmiowb(); 1010 spin_unlock_irqrestore(&priv->lock, flags); 1011 1012 if (new_state && netif_msg_link(priv)) 1013 phy_print_status(phydev); 1014 } 1015 1016 static const struct soc_device_attribute r8a7795es10[] = { 1017 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1018 { /* sentinel */ } 1019 }; 1020 1021 /* PHY init function */ 1022 static int ravb_phy_init(struct net_device *ndev) 1023 { 1024 struct device_node *np = ndev->dev.parent->of_node; 1025 struct ravb_private *priv = netdev_priv(ndev); 1026 struct phy_device *phydev; 1027 struct device_node *pn; 1028 int err; 1029 1030 priv->link = 0; 1031 priv->speed = 0; 1032 1033 /* Try connecting to PHY */ 1034 pn = of_parse_phandle(np, "phy-handle", 0); 1035 if (!pn) { 1036 /* In the case of a fixed PHY, the DT node associated 1037 * to the PHY is the Ethernet MAC DT node. 1038 */ 1039 if (of_phy_is_fixed_link(np)) { 1040 err = of_phy_register_fixed_link(np); 1041 if (err) 1042 return err; 1043 } 1044 pn = of_node_get(np); 1045 } 1046 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1047 priv->phy_interface); 1048 of_node_put(pn); 1049 if (!phydev) { 1050 netdev_err(ndev, "failed to connect PHY\n"); 1051 err = -ENOENT; 1052 goto err_deregister_fixed_link; 1053 } 1054 1055 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1056 * at this time. 1057 */ 1058 if (soc_device_match(r8a7795es10)) { 1059 err = phy_set_max_speed(phydev, SPEED_100); 1060 if (err) { 1061 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1062 goto err_phy_disconnect; 1063 } 1064 1065 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1066 } 1067 1068 /* 10BASE, Pause and Asym Pause is not supported */ 1069 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1070 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1071 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1072 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1073 1074 /* Half Duplex is not supported */ 1075 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1076 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1077 1078 phy_attached_info(phydev); 1079 1080 return 0; 1081 1082 err_phy_disconnect: 1083 phy_disconnect(phydev); 1084 err_deregister_fixed_link: 1085 if (of_phy_is_fixed_link(np)) 1086 of_phy_deregister_fixed_link(np); 1087 1088 return err; 1089 } 1090 1091 /* PHY control start function */ 1092 static int ravb_phy_start(struct net_device *ndev) 1093 { 1094 int error; 1095 1096 error = ravb_phy_init(ndev); 1097 if (error) 1098 return error; 1099 1100 phy_start(ndev->phydev); 1101 1102 return 0; 1103 } 1104 1105 static u32 ravb_get_msglevel(struct net_device *ndev) 1106 { 1107 struct ravb_private *priv = netdev_priv(ndev); 1108 1109 return priv->msg_enable; 1110 } 1111 1112 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1113 { 1114 struct ravb_private *priv = netdev_priv(ndev); 1115 1116 priv->msg_enable = value; 1117 } 1118 1119 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1120 "rx_queue_0_current", 1121 "tx_queue_0_current", 1122 "rx_queue_0_dirty", 1123 "tx_queue_0_dirty", 1124 "rx_queue_0_packets", 1125 "tx_queue_0_packets", 1126 "rx_queue_0_bytes", 1127 "tx_queue_0_bytes", 1128 "rx_queue_0_mcast_packets", 1129 "rx_queue_0_errors", 1130 "rx_queue_0_crc_errors", 1131 "rx_queue_0_frame_errors", 1132 "rx_queue_0_length_errors", 1133 "rx_queue_0_missed_errors", 1134 "rx_queue_0_over_errors", 1135 1136 "rx_queue_1_current", 1137 "tx_queue_1_current", 1138 "rx_queue_1_dirty", 1139 "tx_queue_1_dirty", 1140 "rx_queue_1_packets", 1141 "tx_queue_1_packets", 1142 "rx_queue_1_bytes", 1143 "tx_queue_1_bytes", 1144 "rx_queue_1_mcast_packets", 1145 "rx_queue_1_errors", 1146 "rx_queue_1_crc_errors", 1147 "rx_queue_1_frame_errors", 1148 "rx_queue_1_length_errors", 1149 "rx_queue_1_missed_errors", 1150 "rx_queue_1_over_errors", 1151 }; 1152 1153 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1154 1155 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1156 { 1157 switch (sset) { 1158 case ETH_SS_STATS: 1159 return RAVB_STATS_LEN; 1160 default: 1161 return -EOPNOTSUPP; 1162 } 1163 } 1164 1165 static void ravb_get_ethtool_stats(struct net_device *ndev, 1166 struct ethtool_stats *estats, u64 *data) 1167 { 1168 struct ravb_private *priv = netdev_priv(ndev); 1169 int i = 0; 1170 int q; 1171 1172 /* Device-specific stats */ 1173 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1174 struct net_device_stats *stats = &priv->stats[q]; 1175 1176 data[i++] = priv->cur_rx[q]; 1177 data[i++] = priv->cur_tx[q]; 1178 data[i++] = priv->dirty_rx[q]; 1179 data[i++] = priv->dirty_tx[q]; 1180 data[i++] = stats->rx_packets; 1181 data[i++] = stats->tx_packets; 1182 data[i++] = stats->rx_bytes; 1183 data[i++] = stats->tx_bytes; 1184 data[i++] = stats->multicast; 1185 data[i++] = stats->rx_errors; 1186 data[i++] = stats->rx_crc_errors; 1187 data[i++] = stats->rx_frame_errors; 1188 data[i++] = stats->rx_length_errors; 1189 data[i++] = stats->rx_missed_errors; 1190 data[i++] = stats->rx_over_errors; 1191 } 1192 } 1193 1194 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1195 { 1196 switch (stringset) { 1197 case ETH_SS_STATS: 1198 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1199 break; 1200 } 1201 } 1202 1203 static void ravb_get_ringparam(struct net_device *ndev, 1204 struct ethtool_ringparam *ring) 1205 { 1206 struct ravb_private *priv = netdev_priv(ndev); 1207 1208 ring->rx_max_pending = BE_RX_RING_MAX; 1209 ring->tx_max_pending = BE_TX_RING_MAX; 1210 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1211 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1212 } 1213 1214 static int ravb_set_ringparam(struct net_device *ndev, 1215 struct ethtool_ringparam *ring) 1216 { 1217 struct ravb_private *priv = netdev_priv(ndev); 1218 int error; 1219 1220 if (ring->tx_pending > BE_TX_RING_MAX || 1221 ring->rx_pending > BE_RX_RING_MAX || 1222 ring->tx_pending < BE_TX_RING_MIN || 1223 ring->rx_pending < BE_RX_RING_MIN) 1224 return -EINVAL; 1225 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1226 return -EINVAL; 1227 1228 if (netif_running(ndev)) { 1229 netif_device_detach(ndev); 1230 /* Stop PTP Clock driver */ 1231 if (priv->chip_id == RCAR_GEN2) 1232 ravb_ptp_stop(ndev); 1233 /* Wait for DMA stopping */ 1234 error = ravb_stop_dma(ndev); 1235 if (error) { 1236 netdev_err(ndev, 1237 "cannot set ringparam! Any AVB processes are still running?\n"); 1238 return error; 1239 } 1240 synchronize_irq(ndev->irq); 1241 1242 /* Free all the skb's in the RX queue and the DMA buffers. */ 1243 ravb_ring_free(ndev, RAVB_BE); 1244 ravb_ring_free(ndev, RAVB_NC); 1245 } 1246 1247 /* Set new parameters */ 1248 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1249 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1250 1251 if (netif_running(ndev)) { 1252 error = ravb_dmac_init(ndev); 1253 if (error) { 1254 netdev_err(ndev, 1255 "%s: ravb_dmac_init() failed, error %d\n", 1256 __func__, error); 1257 return error; 1258 } 1259 1260 ravb_emac_init(ndev); 1261 1262 /* Initialise PTP Clock driver */ 1263 if (priv->chip_id == RCAR_GEN2) 1264 ravb_ptp_init(ndev, priv->pdev); 1265 1266 netif_device_attach(ndev); 1267 } 1268 1269 return 0; 1270 } 1271 1272 static int ravb_get_ts_info(struct net_device *ndev, 1273 struct ethtool_ts_info *info) 1274 { 1275 struct ravb_private *priv = netdev_priv(ndev); 1276 1277 info->so_timestamping = 1278 SOF_TIMESTAMPING_TX_SOFTWARE | 1279 SOF_TIMESTAMPING_RX_SOFTWARE | 1280 SOF_TIMESTAMPING_SOFTWARE | 1281 SOF_TIMESTAMPING_TX_HARDWARE | 1282 SOF_TIMESTAMPING_RX_HARDWARE | 1283 SOF_TIMESTAMPING_RAW_HARDWARE; 1284 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1285 info->rx_filters = 1286 (1 << HWTSTAMP_FILTER_NONE) | 1287 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1288 (1 << HWTSTAMP_FILTER_ALL); 1289 info->phc_index = ptp_clock_index(priv->ptp.clock); 1290 1291 return 0; 1292 } 1293 1294 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1295 { 1296 struct ravb_private *priv = netdev_priv(ndev); 1297 1298 wol->supported = WAKE_MAGIC; 1299 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1300 } 1301 1302 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1303 { 1304 struct ravb_private *priv = netdev_priv(ndev); 1305 1306 if (wol->wolopts & ~WAKE_MAGIC) 1307 return -EOPNOTSUPP; 1308 1309 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1310 1311 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1312 1313 return 0; 1314 } 1315 1316 static const struct ethtool_ops ravb_ethtool_ops = { 1317 .nway_reset = phy_ethtool_nway_reset, 1318 .get_msglevel = ravb_get_msglevel, 1319 .set_msglevel = ravb_set_msglevel, 1320 .get_link = ethtool_op_get_link, 1321 .get_strings = ravb_get_strings, 1322 .get_ethtool_stats = ravb_get_ethtool_stats, 1323 .get_sset_count = ravb_get_sset_count, 1324 .get_ringparam = ravb_get_ringparam, 1325 .set_ringparam = ravb_set_ringparam, 1326 .get_ts_info = ravb_get_ts_info, 1327 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1328 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1329 .get_wol = ravb_get_wol, 1330 .set_wol = ravb_set_wol, 1331 }; 1332 1333 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1334 struct net_device *ndev, struct device *dev, 1335 const char *ch) 1336 { 1337 char *name; 1338 int error; 1339 1340 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1341 if (!name) 1342 return -ENOMEM; 1343 error = request_irq(irq, handler, 0, name, ndev); 1344 if (error) 1345 netdev_err(ndev, "cannot request IRQ %s\n", name); 1346 1347 return error; 1348 } 1349 1350 /* Network device open function for Ethernet AVB */ 1351 static int ravb_open(struct net_device *ndev) 1352 { 1353 struct ravb_private *priv = netdev_priv(ndev); 1354 struct platform_device *pdev = priv->pdev; 1355 struct device *dev = &pdev->dev; 1356 int error; 1357 1358 napi_enable(&priv->napi[RAVB_BE]); 1359 napi_enable(&priv->napi[RAVB_NC]); 1360 1361 if (priv->chip_id == RCAR_GEN2) { 1362 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1363 ndev->name, ndev); 1364 if (error) { 1365 netdev_err(ndev, "cannot request IRQ\n"); 1366 goto out_napi_off; 1367 } 1368 } else { 1369 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1370 dev, "ch22:multi"); 1371 if (error) 1372 goto out_napi_off; 1373 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1374 dev, "ch24:emac"); 1375 if (error) 1376 goto out_free_irq; 1377 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1378 ndev, dev, "ch0:rx_be"); 1379 if (error) 1380 goto out_free_irq_emac; 1381 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1382 ndev, dev, "ch18:tx_be"); 1383 if (error) 1384 goto out_free_irq_be_rx; 1385 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1386 ndev, dev, "ch1:rx_nc"); 1387 if (error) 1388 goto out_free_irq_be_tx; 1389 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1390 ndev, dev, "ch19:tx_nc"); 1391 if (error) 1392 goto out_free_irq_nc_rx; 1393 } 1394 1395 /* Device init */ 1396 error = ravb_dmac_init(ndev); 1397 if (error) 1398 goto out_free_irq_nc_tx; 1399 ravb_emac_init(ndev); 1400 1401 /* Initialise PTP Clock driver */ 1402 if (priv->chip_id == RCAR_GEN2) 1403 ravb_ptp_init(ndev, priv->pdev); 1404 1405 netif_tx_start_all_queues(ndev); 1406 1407 /* PHY control start */ 1408 error = ravb_phy_start(ndev); 1409 if (error) 1410 goto out_ptp_stop; 1411 1412 return 0; 1413 1414 out_ptp_stop: 1415 /* Stop PTP Clock driver */ 1416 if (priv->chip_id == RCAR_GEN2) 1417 ravb_ptp_stop(ndev); 1418 out_free_irq_nc_tx: 1419 if (priv->chip_id == RCAR_GEN2) 1420 goto out_free_irq; 1421 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1422 out_free_irq_nc_rx: 1423 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1424 out_free_irq_be_tx: 1425 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1426 out_free_irq_be_rx: 1427 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1428 out_free_irq_emac: 1429 free_irq(priv->emac_irq, ndev); 1430 out_free_irq: 1431 free_irq(ndev->irq, ndev); 1432 out_napi_off: 1433 napi_disable(&priv->napi[RAVB_NC]); 1434 napi_disable(&priv->napi[RAVB_BE]); 1435 return error; 1436 } 1437 1438 /* Timeout function for Ethernet AVB */ 1439 static void ravb_tx_timeout(struct net_device *ndev) 1440 { 1441 struct ravb_private *priv = netdev_priv(ndev); 1442 1443 netif_err(priv, tx_err, ndev, 1444 "transmit timed out, status %08x, resetting...\n", 1445 ravb_read(ndev, ISS)); 1446 1447 /* tx_errors count up */ 1448 ndev->stats.tx_errors++; 1449 1450 schedule_work(&priv->work); 1451 } 1452 1453 static void ravb_tx_timeout_work(struct work_struct *work) 1454 { 1455 struct ravb_private *priv = container_of(work, struct ravb_private, 1456 work); 1457 struct net_device *ndev = priv->ndev; 1458 1459 netif_tx_stop_all_queues(ndev); 1460 1461 /* Stop PTP Clock driver */ 1462 if (priv->chip_id == RCAR_GEN2) 1463 ravb_ptp_stop(ndev); 1464 1465 /* Wait for DMA stopping */ 1466 ravb_stop_dma(ndev); 1467 1468 ravb_ring_free(ndev, RAVB_BE); 1469 ravb_ring_free(ndev, RAVB_NC); 1470 1471 /* Device init */ 1472 ravb_dmac_init(ndev); 1473 ravb_emac_init(ndev); 1474 1475 /* Initialise PTP Clock driver */ 1476 if (priv->chip_id == RCAR_GEN2) 1477 ravb_ptp_init(ndev, priv->pdev); 1478 1479 netif_tx_start_all_queues(ndev); 1480 } 1481 1482 /* Packet transmit function for Ethernet AVB */ 1483 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1484 { 1485 struct ravb_private *priv = netdev_priv(ndev); 1486 int num_tx_desc = priv->num_tx_desc; 1487 u16 q = skb_get_queue_mapping(skb); 1488 struct ravb_tstamp_skb *ts_skb; 1489 struct ravb_tx_desc *desc; 1490 unsigned long flags; 1491 u32 dma_addr; 1492 void *buffer; 1493 u32 entry; 1494 u32 len; 1495 1496 spin_lock_irqsave(&priv->lock, flags); 1497 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1498 num_tx_desc) { 1499 netif_err(priv, tx_queued, ndev, 1500 "still transmitting with the full ring!\n"); 1501 netif_stop_subqueue(ndev, q); 1502 spin_unlock_irqrestore(&priv->lock, flags); 1503 return NETDEV_TX_BUSY; 1504 } 1505 1506 if (skb_put_padto(skb, ETH_ZLEN)) 1507 goto exit; 1508 1509 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1510 priv->tx_skb[q][entry / num_tx_desc] = skb; 1511 1512 if (num_tx_desc > 1) { 1513 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1514 entry / num_tx_desc * DPTR_ALIGN; 1515 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1516 1517 /* Zero length DMA descriptors are problematic as they seem 1518 * to terminate DMA transfers. Avoid them by simply using a 1519 * length of DPTR_ALIGN (4) when skb data is aligned to 1520 * DPTR_ALIGN. 1521 * 1522 * As skb is guaranteed to have at least ETH_ZLEN (60) 1523 * bytes of data by the call to skb_put_padto() above this 1524 * is safe with respect to both the length of the first DMA 1525 * descriptor (len) overflowing the available data and the 1526 * length of the second DMA descriptor (skb->len - len) 1527 * being negative. 1528 */ 1529 if (len == 0) 1530 len = DPTR_ALIGN; 1531 1532 memcpy(buffer, skb->data, len); 1533 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1534 DMA_TO_DEVICE); 1535 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1536 goto drop; 1537 1538 desc = &priv->tx_ring[q][entry]; 1539 desc->ds_tagl = cpu_to_le16(len); 1540 desc->dptr = cpu_to_le32(dma_addr); 1541 1542 buffer = skb->data + len; 1543 len = skb->len - len; 1544 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1545 DMA_TO_DEVICE); 1546 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1547 goto unmap; 1548 1549 desc++; 1550 } else { 1551 desc = &priv->tx_ring[q][entry]; 1552 len = skb->len; 1553 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1554 DMA_TO_DEVICE); 1555 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1556 goto drop; 1557 } 1558 desc->ds_tagl = cpu_to_le16(len); 1559 desc->dptr = cpu_to_le32(dma_addr); 1560 1561 /* TX timestamp required */ 1562 if (q == RAVB_NC) { 1563 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1564 if (!ts_skb) { 1565 if (num_tx_desc > 1) { 1566 desc--; 1567 dma_unmap_single(ndev->dev.parent, dma_addr, 1568 len, DMA_TO_DEVICE); 1569 } 1570 goto unmap; 1571 } 1572 ts_skb->skb = skb; 1573 ts_skb->tag = priv->ts_skb_tag++; 1574 priv->ts_skb_tag &= 0x3ff; 1575 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1576 1577 /* TAG and timestamp required flag */ 1578 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1579 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1580 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1581 } 1582 1583 skb_tx_timestamp(skb); 1584 /* Descriptor type must be set after all the above writes */ 1585 dma_wmb(); 1586 if (num_tx_desc > 1) { 1587 desc->die_dt = DT_FEND; 1588 desc--; 1589 desc->die_dt = DT_FSTART; 1590 } else { 1591 desc->die_dt = DT_FSINGLE; 1592 } 1593 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1594 1595 priv->cur_tx[q] += num_tx_desc; 1596 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1597 (priv->num_tx_ring[q] - 1) * num_tx_desc && 1598 !ravb_tx_free(ndev, q, true)) 1599 netif_stop_subqueue(ndev, q); 1600 1601 exit: 1602 mmiowb(); 1603 spin_unlock_irqrestore(&priv->lock, flags); 1604 return NETDEV_TX_OK; 1605 1606 unmap: 1607 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1608 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1609 drop: 1610 dev_kfree_skb_any(skb); 1611 priv->tx_skb[q][entry / num_tx_desc] = NULL; 1612 goto exit; 1613 } 1614 1615 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1616 struct net_device *sb_dev, 1617 select_queue_fallback_t fallback) 1618 { 1619 /* If skb needs TX timestamp, it is handled in network control queue */ 1620 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1621 RAVB_BE; 1622 1623 } 1624 1625 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1626 { 1627 struct ravb_private *priv = netdev_priv(ndev); 1628 struct net_device_stats *nstats, *stats0, *stats1; 1629 1630 nstats = &ndev->stats; 1631 stats0 = &priv->stats[RAVB_BE]; 1632 stats1 = &priv->stats[RAVB_NC]; 1633 1634 nstats->tx_dropped += ravb_read(ndev, TROCR); 1635 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1636 nstats->collisions += ravb_read(ndev, CDCR); 1637 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1638 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1639 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1640 1641 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1642 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1643 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1644 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1645 1646 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1647 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1648 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1649 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1650 nstats->multicast = stats0->multicast + stats1->multicast; 1651 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1652 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1653 nstats->rx_frame_errors = 1654 stats0->rx_frame_errors + stats1->rx_frame_errors; 1655 nstats->rx_length_errors = 1656 stats0->rx_length_errors + stats1->rx_length_errors; 1657 nstats->rx_missed_errors = 1658 stats0->rx_missed_errors + stats1->rx_missed_errors; 1659 nstats->rx_over_errors = 1660 stats0->rx_over_errors + stats1->rx_over_errors; 1661 1662 return nstats; 1663 } 1664 1665 /* Update promiscuous bit */ 1666 static void ravb_set_rx_mode(struct net_device *ndev) 1667 { 1668 struct ravb_private *priv = netdev_priv(ndev); 1669 unsigned long flags; 1670 1671 spin_lock_irqsave(&priv->lock, flags); 1672 ravb_modify(ndev, ECMR, ECMR_PRM, 1673 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1674 mmiowb(); 1675 spin_unlock_irqrestore(&priv->lock, flags); 1676 } 1677 1678 /* Device close function for Ethernet AVB */ 1679 static int ravb_close(struct net_device *ndev) 1680 { 1681 struct device_node *np = ndev->dev.parent->of_node; 1682 struct ravb_private *priv = netdev_priv(ndev); 1683 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1684 1685 netif_tx_stop_all_queues(ndev); 1686 1687 /* Disable interrupts by clearing the interrupt masks. */ 1688 ravb_write(ndev, 0, RIC0); 1689 ravb_write(ndev, 0, RIC2); 1690 ravb_write(ndev, 0, TIC); 1691 1692 /* Stop PTP Clock driver */ 1693 if (priv->chip_id == RCAR_GEN2) 1694 ravb_ptp_stop(ndev); 1695 1696 /* Set the config mode to stop the AVB-DMAC's processes */ 1697 if (ravb_stop_dma(ndev) < 0) 1698 netdev_err(ndev, 1699 "device will be stopped after h/w processes are done.\n"); 1700 1701 /* Clear the timestamp list */ 1702 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1703 list_del(&ts_skb->list); 1704 kfree(ts_skb); 1705 } 1706 1707 /* PHY disconnect */ 1708 if (ndev->phydev) { 1709 phy_stop(ndev->phydev); 1710 phy_disconnect(ndev->phydev); 1711 if (of_phy_is_fixed_link(np)) 1712 of_phy_deregister_fixed_link(np); 1713 } 1714 1715 if (priv->chip_id != RCAR_GEN2) { 1716 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1717 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1718 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1719 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1720 free_irq(priv->emac_irq, ndev); 1721 } 1722 free_irq(ndev->irq, ndev); 1723 1724 napi_disable(&priv->napi[RAVB_NC]); 1725 napi_disable(&priv->napi[RAVB_BE]); 1726 1727 /* Free all the skb's in the RX queue and the DMA buffers. */ 1728 ravb_ring_free(ndev, RAVB_BE); 1729 ravb_ring_free(ndev, RAVB_NC); 1730 1731 return 0; 1732 } 1733 1734 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1735 { 1736 struct ravb_private *priv = netdev_priv(ndev); 1737 struct hwtstamp_config config; 1738 1739 config.flags = 0; 1740 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1741 HWTSTAMP_TX_OFF; 1742 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1743 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1744 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1745 config.rx_filter = HWTSTAMP_FILTER_ALL; 1746 else 1747 config.rx_filter = HWTSTAMP_FILTER_NONE; 1748 1749 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1750 -EFAULT : 0; 1751 } 1752 1753 /* Control hardware time stamping */ 1754 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1755 { 1756 struct ravb_private *priv = netdev_priv(ndev); 1757 struct hwtstamp_config config; 1758 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1759 u32 tstamp_tx_ctrl; 1760 1761 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1762 return -EFAULT; 1763 1764 /* Reserved for future extensions */ 1765 if (config.flags) 1766 return -EINVAL; 1767 1768 switch (config.tx_type) { 1769 case HWTSTAMP_TX_OFF: 1770 tstamp_tx_ctrl = 0; 1771 break; 1772 case HWTSTAMP_TX_ON: 1773 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1774 break; 1775 default: 1776 return -ERANGE; 1777 } 1778 1779 switch (config.rx_filter) { 1780 case HWTSTAMP_FILTER_NONE: 1781 tstamp_rx_ctrl = 0; 1782 break; 1783 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1784 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1785 break; 1786 default: 1787 config.rx_filter = HWTSTAMP_FILTER_ALL; 1788 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1789 } 1790 1791 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1792 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1793 1794 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1795 -EFAULT : 0; 1796 } 1797 1798 /* ioctl to device function */ 1799 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1800 { 1801 struct phy_device *phydev = ndev->phydev; 1802 1803 if (!netif_running(ndev)) 1804 return -EINVAL; 1805 1806 if (!phydev) 1807 return -ENODEV; 1808 1809 switch (cmd) { 1810 case SIOCGHWTSTAMP: 1811 return ravb_hwtstamp_get(ndev, req); 1812 case SIOCSHWTSTAMP: 1813 return ravb_hwtstamp_set(ndev, req); 1814 } 1815 1816 return phy_mii_ioctl(phydev, req, cmd); 1817 } 1818 1819 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 1820 { 1821 if (netif_running(ndev)) 1822 return -EBUSY; 1823 1824 ndev->mtu = new_mtu; 1825 netdev_update_features(ndev); 1826 1827 return 0; 1828 } 1829 1830 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1831 { 1832 struct ravb_private *priv = netdev_priv(ndev); 1833 unsigned long flags; 1834 1835 spin_lock_irqsave(&priv->lock, flags); 1836 1837 /* Disable TX and RX */ 1838 ravb_rcv_snd_disable(ndev); 1839 1840 /* Modify RX Checksum setting */ 1841 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1842 1843 /* Enable TX and RX */ 1844 ravb_rcv_snd_enable(ndev); 1845 1846 spin_unlock_irqrestore(&priv->lock, flags); 1847 } 1848 1849 static int ravb_set_features(struct net_device *ndev, 1850 netdev_features_t features) 1851 { 1852 netdev_features_t changed = ndev->features ^ features; 1853 1854 if (changed & NETIF_F_RXCSUM) 1855 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1856 1857 ndev->features = features; 1858 1859 return 0; 1860 } 1861 1862 static const struct net_device_ops ravb_netdev_ops = { 1863 .ndo_open = ravb_open, 1864 .ndo_stop = ravb_close, 1865 .ndo_start_xmit = ravb_start_xmit, 1866 .ndo_select_queue = ravb_select_queue, 1867 .ndo_get_stats = ravb_get_stats, 1868 .ndo_set_rx_mode = ravb_set_rx_mode, 1869 .ndo_tx_timeout = ravb_tx_timeout, 1870 .ndo_do_ioctl = ravb_do_ioctl, 1871 .ndo_change_mtu = ravb_change_mtu, 1872 .ndo_validate_addr = eth_validate_addr, 1873 .ndo_set_mac_address = eth_mac_addr, 1874 .ndo_set_features = ravb_set_features, 1875 }; 1876 1877 /* MDIO bus init function */ 1878 static int ravb_mdio_init(struct ravb_private *priv) 1879 { 1880 struct platform_device *pdev = priv->pdev; 1881 struct device *dev = &pdev->dev; 1882 int error; 1883 1884 /* Bitbang init */ 1885 priv->mdiobb.ops = &bb_ops; 1886 1887 /* MII controller setting */ 1888 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1889 if (!priv->mii_bus) 1890 return -ENOMEM; 1891 1892 /* Hook up MII support for ethtool */ 1893 priv->mii_bus->name = "ravb_mii"; 1894 priv->mii_bus->parent = dev; 1895 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1896 pdev->name, pdev->id); 1897 1898 /* Register MDIO bus */ 1899 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1900 if (error) 1901 goto out_free_bus; 1902 1903 return 0; 1904 1905 out_free_bus: 1906 free_mdio_bitbang(priv->mii_bus); 1907 return error; 1908 } 1909 1910 /* MDIO bus release function */ 1911 static int ravb_mdio_release(struct ravb_private *priv) 1912 { 1913 /* Unregister mdio bus */ 1914 mdiobus_unregister(priv->mii_bus); 1915 1916 /* Free bitbang info */ 1917 free_mdio_bitbang(priv->mii_bus); 1918 1919 return 0; 1920 } 1921 1922 static const struct of_device_id ravb_match_table[] = { 1923 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1924 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1925 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1926 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1927 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1928 { } 1929 }; 1930 MODULE_DEVICE_TABLE(of, ravb_match_table); 1931 1932 static int ravb_set_gti(struct net_device *ndev) 1933 { 1934 struct ravb_private *priv = netdev_priv(ndev); 1935 struct device *dev = ndev->dev.parent; 1936 unsigned long rate; 1937 uint64_t inc; 1938 1939 rate = clk_get_rate(priv->clk); 1940 if (!rate) 1941 return -EINVAL; 1942 1943 inc = 1000000000ULL << 20; 1944 do_div(inc, rate); 1945 1946 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1947 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1948 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1949 return -EINVAL; 1950 } 1951 1952 ravb_write(ndev, inc, GTI); 1953 1954 return 0; 1955 } 1956 1957 static void ravb_set_config_mode(struct net_device *ndev) 1958 { 1959 struct ravb_private *priv = netdev_priv(ndev); 1960 1961 if (priv->chip_id == RCAR_GEN2) { 1962 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1963 /* Set CSEL value */ 1964 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1965 } else { 1966 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1967 CCC_GAC | CCC_CSEL_HPB); 1968 } 1969 } 1970 1971 /* Set tx and rx clock internal delay modes */ 1972 static void ravb_set_delay_mode(struct net_device *ndev) 1973 { 1974 struct ravb_private *priv = netdev_priv(ndev); 1975 int set = 0; 1976 1977 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1978 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1979 set |= APSR_DM_RDM; 1980 1981 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1982 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1983 set |= APSR_DM_TDM; 1984 1985 ravb_modify(ndev, APSR, APSR_DM, set); 1986 } 1987 1988 static int ravb_probe(struct platform_device *pdev) 1989 { 1990 struct device_node *np = pdev->dev.of_node; 1991 struct ravb_private *priv; 1992 enum ravb_chip_id chip_id; 1993 struct net_device *ndev; 1994 int error, irq, q; 1995 struct resource *res; 1996 int i; 1997 1998 if (!np) { 1999 dev_err(&pdev->dev, 2000 "this driver is required to be instantiated from device tree\n"); 2001 return -EINVAL; 2002 } 2003 2004 /* Get base address */ 2005 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2006 if (!res) { 2007 dev_err(&pdev->dev, "invalid resource\n"); 2008 return -EINVAL; 2009 } 2010 2011 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2012 NUM_TX_QUEUE, NUM_RX_QUEUE); 2013 if (!ndev) 2014 return -ENOMEM; 2015 2016 ndev->features = NETIF_F_RXCSUM; 2017 ndev->hw_features = NETIF_F_RXCSUM; 2018 2019 pm_runtime_enable(&pdev->dev); 2020 pm_runtime_get_sync(&pdev->dev); 2021 2022 /* The Ether-specific entries in the device structure. */ 2023 ndev->base_addr = res->start; 2024 2025 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2026 2027 if (chip_id == RCAR_GEN3) 2028 irq = platform_get_irq_byname(pdev, "ch22"); 2029 else 2030 irq = platform_get_irq(pdev, 0); 2031 if (irq < 0) { 2032 error = irq; 2033 goto out_release; 2034 } 2035 ndev->irq = irq; 2036 2037 SET_NETDEV_DEV(ndev, &pdev->dev); 2038 2039 priv = netdev_priv(ndev); 2040 priv->ndev = ndev; 2041 priv->pdev = pdev; 2042 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2043 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2044 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2045 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2046 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2047 if (IS_ERR(priv->addr)) { 2048 error = PTR_ERR(priv->addr); 2049 goto out_release; 2050 } 2051 2052 spin_lock_init(&priv->lock); 2053 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2054 2055 priv->phy_interface = of_get_phy_mode(np); 2056 2057 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2058 priv->avb_link_active_low = 2059 of_property_read_bool(np, "renesas,ether-link-active-low"); 2060 2061 if (chip_id == RCAR_GEN3) { 2062 irq = platform_get_irq_byname(pdev, "ch24"); 2063 if (irq < 0) { 2064 error = irq; 2065 goto out_release; 2066 } 2067 priv->emac_irq = irq; 2068 for (i = 0; i < NUM_RX_QUEUE; i++) { 2069 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2070 if (irq < 0) { 2071 error = irq; 2072 goto out_release; 2073 } 2074 priv->rx_irqs[i] = irq; 2075 } 2076 for (i = 0; i < NUM_TX_QUEUE; i++) { 2077 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2078 if (irq < 0) { 2079 error = irq; 2080 goto out_release; 2081 } 2082 priv->tx_irqs[i] = irq; 2083 } 2084 } 2085 2086 priv->chip_id = chip_id; 2087 2088 priv->clk = devm_clk_get(&pdev->dev, NULL); 2089 if (IS_ERR(priv->clk)) { 2090 error = PTR_ERR(priv->clk); 2091 goto out_release; 2092 } 2093 2094 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2095 ndev->min_mtu = ETH_MIN_MTU; 2096 2097 priv->num_tx_desc = chip_id == RCAR_GEN2 ? 2098 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3; 2099 2100 /* Set function */ 2101 ndev->netdev_ops = &ravb_netdev_ops; 2102 ndev->ethtool_ops = &ravb_ethtool_ops; 2103 2104 /* Set AVB config mode */ 2105 ravb_set_config_mode(ndev); 2106 2107 /* Set GTI value */ 2108 error = ravb_set_gti(ndev); 2109 if (error) 2110 goto out_release; 2111 2112 /* Request GTI loading */ 2113 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2114 2115 if (priv->chip_id != RCAR_GEN2) 2116 ravb_set_delay_mode(ndev); 2117 2118 /* Allocate descriptor base address table */ 2119 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2120 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2121 &priv->desc_bat_dma, GFP_KERNEL); 2122 if (!priv->desc_bat) { 2123 dev_err(&pdev->dev, 2124 "Cannot allocate desc base address table (size %d bytes)\n", 2125 priv->desc_bat_size); 2126 error = -ENOMEM; 2127 goto out_release; 2128 } 2129 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2130 priv->desc_bat[q].die_dt = DT_EOS; 2131 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2132 2133 /* Initialise HW timestamp list */ 2134 INIT_LIST_HEAD(&priv->ts_skb_list); 2135 2136 /* Initialise PTP Clock driver */ 2137 if (chip_id != RCAR_GEN2) 2138 ravb_ptp_init(ndev, pdev); 2139 2140 /* Debug message level */ 2141 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2142 2143 /* Read and set MAC address */ 2144 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2145 if (!is_valid_ether_addr(ndev->dev_addr)) { 2146 dev_warn(&pdev->dev, 2147 "no valid MAC address supplied, using a random one\n"); 2148 eth_hw_addr_random(ndev); 2149 } 2150 2151 /* MDIO bus init */ 2152 error = ravb_mdio_init(priv); 2153 if (error) { 2154 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2155 goto out_dma_free; 2156 } 2157 2158 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2159 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2160 2161 /* Network device register */ 2162 error = register_netdev(ndev); 2163 if (error) 2164 goto out_napi_del; 2165 2166 device_set_wakeup_capable(&pdev->dev, 1); 2167 2168 /* Print device information */ 2169 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2170 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2171 2172 platform_set_drvdata(pdev, ndev); 2173 2174 return 0; 2175 2176 out_napi_del: 2177 netif_napi_del(&priv->napi[RAVB_NC]); 2178 netif_napi_del(&priv->napi[RAVB_BE]); 2179 ravb_mdio_release(priv); 2180 out_dma_free: 2181 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2182 priv->desc_bat_dma); 2183 2184 /* Stop PTP Clock driver */ 2185 if (chip_id != RCAR_GEN2) 2186 ravb_ptp_stop(ndev); 2187 out_release: 2188 free_netdev(ndev); 2189 2190 pm_runtime_put(&pdev->dev); 2191 pm_runtime_disable(&pdev->dev); 2192 return error; 2193 } 2194 2195 static int ravb_remove(struct platform_device *pdev) 2196 { 2197 struct net_device *ndev = platform_get_drvdata(pdev); 2198 struct ravb_private *priv = netdev_priv(ndev); 2199 2200 /* Stop PTP Clock driver */ 2201 if (priv->chip_id != RCAR_GEN2) 2202 ravb_ptp_stop(ndev); 2203 2204 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2205 priv->desc_bat_dma); 2206 /* Set reset mode */ 2207 ravb_write(ndev, CCC_OPC_RESET, CCC); 2208 pm_runtime_put_sync(&pdev->dev); 2209 unregister_netdev(ndev); 2210 netif_napi_del(&priv->napi[RAVB_NC]); 2211 netif_napi_del(&priv->napi[RAVB_BE]); 2212 ravb_mdio_release(priv); 2213 pm_runtime_disable(&pdev->dev); 2214 free_netdev(ndev); 2215 platform_set_drvdata(pdev, NULL); 2216 2217 return 0; 2218 } 2219 2220 static int ravb_wol_setup(struct net_device *ndev) 2221 { 2222 struct ravb_private *priv = netdev_priv(ndev); 2223 2224 /* Disable interrupts by clearing the interrupt masks. */ 2225 ravb_write(ndev, 0, RIC0); 2226 ravb_write(ndev, 0, RIC2); 2227 ravb_write(ndev, 0, TIC); 2228 2229 /* Only allow ECI interrupts */ 2230 synchronize_irq(priv->emac_irq); 2231 napi_disable(&priv->napi[RAVB_NC]); 2232 napi_disable(&priv->napi[RAVB_BE]); 2233 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2234 2235 /* Enable MagicPacket */ 2236 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2237 2238 return enable_irq_wake(priv->emac_irq); 2239 } 2240 2241 static int ravb_wol_restore(struct net_device *ndev) 2242 { 2243 struct ravb_private *priv = netdev_priv(ndev); 2244 int ret; 2245 2246 napi_enable(&priv->napi[RAVB_NC]); 2247 napi_enable(&priv->napi[RAVB_BE]); 2248 2249 /* Disable MagicPacket */ 2250 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2251 2252 ret = ravb_close(ndev); 2253 if (ret < 0) 2254 return ret; 2255 2256 return disable_irq_wake(priv->emac_irq); 2257 } 2258 2259 static int __maybe_unused ravb_suspend(struct device *dev) 2260 { 2261 struct net_device *ndev = dev_get_drvdata(dev); 2262 struct ravb_private *priv = netdev_priv(ndev); 2263 int ret; 2264 2265 if (!netif_running(ndev)) 2266 return 0; 2267 2268 netif_device_detach(ndev); 2269 2270 if (priv->wol_enabled) 2271 ret = ravb_wol_setup(ndev); 2272 else 2273 ret = ravb_close(ndev); 2274 2275 return ret; 2276 } 2277 2278 static int __maybe_unused ravb_resume(struct device *dev) 2279 { 2280 struct net_device *ndev = dev_get_drvdata(dev); 2281 struct ravb_private *priv = netdev_priv(ndev); 2282 int ret = 0; 2283 2284 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2285 if (priv->wol_enabled) 2286 ravb_write(ndev, CCC_OPC_RESET, CCC); 2287 2288 /* All register have been reset to default values. 2289 * Restore all registers which where setup at probe time and 2290 * reopen device if it was running before system suspended. 2291 */ 2292 2293 /* Set AVB config mode */ 2294 ravb_set_config_mode(ndev); 2295 2296 /* Set GTI value */ 2297 ret = ravb_set_gti(ndev); 2298 if (ret) 2299 return ret; 2300 2301 /* Request GTI loading */ 2302 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2303 2304 if (priv->chip_id != RCAR_GEN2) 2305 ravb_set_delay_mode(ndev); 2306 2307 /* Restore descriptor base address table */ 2308 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2309 2310 if (netif_running(ndev)) { 2311 if (priv->wol_enabled) { 2312 ret = ravb_wol_restore(ndev); 2313 if (ret) 2314 return ret; 2315 } 2316 ret = ravb_open(ndev); 2317 if (ret < 0) 2318 return ret; 2319 netif_device_attach(ndev); 2320 } 2321 2322 return ret; 2323 } 2324 2325 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2326 { 2327 /* Runtime PM callback shared between ->runtime_suspend() 2328 * and ->runtime_resume(). Simply returns success. 2329 * 2330 * This driver re-initializes all registers after 2331 * pm_runtime_get_sync() anyway so there is no need 2332 * to save and restore registers here. 2333 */ 2334 return 0; 2335 } 2336 2337 static const struct dev_pm_ops ravb_dev_pm_ops = { 2338 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2339 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2340 }; 2341 2342 static struct platform_driver ravb_driver = { 2343 .probe = ravb_probe, 2344 .remove = ravb_remove, 2345 .driver = { 2346 .name = "ravb", 2347 .pm = &ravb_dev_pm_ops, 2348 .of_match_table = ravb_match_table, 2349 }, 2350 }; 2351 2352 module_platform_driver(ravb_driver); 2353 2354 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2355 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2356 MODULE_LICENSE("GPL v2"); 2357