1 /* Renesas Ethernet AVB device driver 2 * 3 * Copyright (C) 2014-2015 Renesas Electronics Corporation 4 * Copyright (C) 2015 Renesas Solutions Corp. 5 * Copyright (C) 2015 Cogent Embedded, Inc. <source@cogentembedded.com> 6 * 7 * Based on the SuperH Ethernet driver 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License version 2, 11 * as published by the Free Software Foundation. 12 */ 13 14 #include <linux/cache.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/err.h> 19 #include <linux/etherdevice.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/kernel.h> 23 #include <linux/list.h> 24 #include <linux/module.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_mdio.h> 30 #include <linux/of_net.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/slab.h> 33 #include <linux/spinlock.h> 34 35 #include <asm/div64.h> 36 37 #include "ravb.h" 38 39 #define RAVB_DEF_MSG_ENABLE \ 40 (NETIF_MSG_LINK | \ 41 NETIF_MSG_TIMER | \ 42 NETIF_MSG_RX_ERR | \ 43 NETIF_MSG_TX_ERR) 44 45 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 46 { 47 int i; 48 49 for (i = 0; i < 10000; i++) { 50 if ((ravb_read(ndev, reg) & mask) == value) 51 return 0; 52 udelay(10); 53 } 54 return -ETIMEDOUT; 55 } 56 57 static int ravb_config(struct net_device *ndev) 58 { 59 int error; 60 61 /* Set config mode */ 62 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_CONFIG, 63 CCC); 64 /* Check if the operating mode is changed to the config mode */ 65 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 66 if (error) 67 netdev_err(ndev, "failed to switch device to config mode\n"); 68 69 return error; 70 } 71 72 static void ravb_set_duplex(struct net_device *ndev) 73 { 74 struct ravb_private *priv = netdev_priv(ndev); 75 u32 ecmr = ravb_read(ndev, ECMR); 76 77 if (priv->duplex) /* Full */ 78 ecmr |= ECMR_DM; 79 else /* Half */ 80 ecmr &= ~ECMR_DM; 81 ravb_write(ndev, ecmr, ECMR); 82 } 83 84 static void ravb_set_rate(struct net_device *ndev) 85 { 86 struct ravb_private *priv = netdev_priv(ndev); 87 88 switch (priv->speed) { 89 case 100: /* 100BASE */ 90 ravb_write(ndev, GECMR_SPEED_100, GECMR); 91 break; 92 case 1000: /* 1000BASE */ 93 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 94 break; 95 default: 96 break; 97 } 98 } 99 100 static void ravb_set_buffer_align(struct sk_buff *skb) 101 { 102 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 103 104 if (reserve) 105 skb_reserve(skb, RAVB_ALIGN - reserve); 106 } 107 108 /* Get MAC address from the MAC address registers 109 * 110 * Ethernet AVB device doesn't have ROM for MAC address. 111 * This function gets the MAC address that was used by a bootloader. 112 */ 113 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 114 { 115 if (mac) { 116 ether_addr_copy(ndev->dev_addr, mac); 117 } else { 118 u32 mahr = ravb_read(ndev, MAHR); 119 u32 malr = ravb_read(ndev, MALR); 120 121 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 122 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 123 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 124 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 125 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 126 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 127 } 128 } 129 130 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 131 { 132 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 133 mdiobb); 134 u32 pir = ravb_read(priv->ndev, PIR); 135 136 if (set) 137 pir |= mask; 138 else 139 pir &= ~mask; 140 ravb_write(priv->ndev, pir, PIR); 141 } 142 143 /* MDC pin control */ 144 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 145 { 146 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 147 } 148 149 /* Data I/O pin control */ 150 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 151 { 152 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 153 } 154 155 /* Set data bit */ 156 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 157 { 158 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 159 } 160 161 /* Get data bit */ 162 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 163 { 164 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 165 mdiobb); 166 167 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 168 } 169 170 /* MDIO bus control struct */ 171 static struct mdiobb_ops bb_ops = { 172 .owner = THIS_MODULE, 173 .set_mdc = ravb_set_mdc, 174 .set_mdio_dir = ravb_set_mdio_dir, 175 .set_mdio_data = ravb_set_mdio_data, 176 .get_mdio_data = ravb_get_mdio_data, 177 }; 178 179 /* Free skb's and DMA buffers for Ethernet AVB */ 180 static void ravb_ring_free(struct net_device *ndev, int q) 181 { 182 struct ravb_private *priv = netdev_priv(ndev); 183 int ring_size; 184 int i; 185 186 /* Free RX skb ringbuffer */ 187 if (priv->rx_skb[q]) { 188 for (i = 0; i < priv->num_rx_ring[q]; i++) 189 dev_kfree_skb(priv->rx_skb[q][i]); 190 } 191 kfree(priv->rx_skb[q]); 192 priv->rx_skb[q] = NULL; 193 194 /* Free TX skb ringbuffer */ 195 if (priv->tx_skb[q]) { 196 for (i = 0; i < priv->num_tx_ring[q]; i++) 197 dev_kfree_skb(priv->tx_skb[q][i]); 198 } 199 kfree(priv->tx_skb[q]); 200 priv->tx_skb[q] = NULL; 201 202 /* Free aligned TX buffers */ 203 kfree(priv->tx_align[q]); 204 priv->tx_align[q] = NULL; 205 206 if (priv->rx_ring[q]) { 207 ring_size = sizeof(struct ravb_ex_rx_desc) * 208 (priv->num_rx_ring[q] + 1); 209 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 210 priv->rx_desc_dma[q]); 211 priv->rx_ring[q] = NULL; 212 } 213 214 if (priv->tx_ring[q]) { 215 ring_size = sizeof(struct ravb_tx_desc) * 216 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 217 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 218 priv->tx_desc_dma[q]); 219 priv->tx_ring[q] = NULL; 220 } 221 } 222 223 /* Format skb and descriptor buffer for Ethernet AVB */ 224 static void ravb_ring_format(struct net_device *ndev, int q) 225 { 226 struct ravb_private *priv = netdev_priv(ndev); 227 struct ravb_ex_rx_desc *rx_desc; 228 struct ravb_tx_desc *tx_desc; 229 struct ravb_desc *desc; 230 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 231 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 232 NUM_TX_DESC; 233 dma_addr_t dma_addr; 234 int i; 235 236 priv->cur_rx[q] = 0; 237 priv->cur_tx[q] = 0; 238 priv->dirty_rx[q] = 0; 239 priv->dirty_tx[q] = 0; 240 241 memset(priv->rx_ring[q], 0, rx_ring_size); 242 /* Build RX ring buffer */ 243 for (i = 0; i < priv->num_rx_ring[q]; i++) { 244 /* RX descriptor */ 245 rx_desc = &priv->rx_ring[q][i]; 246 /* The size of the buffer should be on 16-byte boundary. */ 247 rx_desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16)); 248 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 249 ALIGN(PKT_BUF_SZ, 16), 250 DMA_FROM_DEVICE); 251 /* We just set the data size to 0 for a failed mapping which 252 * should prevent DMA from happening... 253 */ 254 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 255 rx_desc->ds_cc = cpu_to_le16(0); 256 rx_desc->dptr = cpu_to_le32(dma_addr); 257 rx_desc->die_dt = DT_FEMPTY; 258 } 259 rx_desc = &priv->rx_ring[q][i]; 260 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 261 rx_desc->die_dt = DT_LINKFIX; /* type */ 262 263 memset(priv->tx_ring[q], 0, tx_ring_size); 264 /* Build TX ring buffer */ 265 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 266 i++, tx_desc++) { 267 tx_desc->die_dt = DT_EEMPTY; 268 tx_desc++; 269 tx_desc->die_dt = DT_EEMPTY; 270 } 271 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 272 tx_desc->die_dt = DT_LINKFIX; /* type */ 273 274 /* RX descriptor base address for best effort */ 275 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 276 desc->die_dt = DT_LINKFIX; /* type */ 277 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 278 279 /* TX descriptor base address for best effort */ 280 desc = &priv->desc_bat[q]; 281 desc->die_dt = DT_LINKFIX; /* type */ 282 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 283 } 284 285 /* Init skb and descriptor buffer for Ethernet AVB */ 286 static int ravb_ring_init(struct net_device *ndev, int q) 287 { 288 struct ravb_private *priv = netdev_priv(ndev); 289 struct sk_buff *skb; 290 int ring_size; 291 int i; 292 293 /* Allocate RX and TX skb rings */ 294 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 295 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 296 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 297 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 298 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 299 goto error; 300 301 for (i = 0; i < priv->num_rx_ring[q]; i++) { 302 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1); 303 if (!skb) 304 goto error; 305 ravb_set_buffer_align(skb); 306 priv->rx_skb[q][i] = skb; 307 } 308 309 /* Allocate rings for the aligned buffers */ 310 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 311 DPTR_ALIGN - 1, GFP_KERNEL); 312 if (!priv->tx_align[q]) 313 goto error; 314 315 /* Allocate all RX descriptors. */ 316 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 317 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 318 &priv->rx_desc_dma[q], 319 GFP_KERNEL); 320 if (!priv->rx_ring[q]) 321 goto error; 322 323 priv->dirty_rx[q] = 0; 324 325 /* Allocate all TX descriptors. */ 326 ring_size = sizeof(struct ravb_tx_desc) * 327 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 328 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 329 &priv->tx_desc_dma[q], 330 GFP_KERNEL); 331 if (!priv->tx_ring[q]) 332 goto error; 333 334 return 0; 335 336 error: 337 ravb_ring_free(ndev, q); 338 339 return -ENOMEM; 340 } 341 342 /* E-MAC init function */ 343 static void ravb_emac_init(struct net_device *ndev) 344 { 345 struct ravb_private *priv = netdev_priv(ndev); 346 347 /* Receive frame limit set register */ 348 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 349 350 /* PAUSE prohibition */ 351 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | 352 ECMR_TE | ECMR_RE, ECMR); 353 354 ravb_set_rate(ndev); 355 356 /* Set MAC address */ 357 ravb_write(ndev, 358 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 359 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 360 ravb_write(ndev, 361 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 362 363 ravb_write(ndev, 1, MPR); 364 365 /* E-MAC status register clear */ 366 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 367 368 /* E-MAC interrupt enable register */ 369 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 370 } 371 372 /* Device init function for Ethernet AVB */ 373 static int ravb_dmac_init(struct net_device *ndev) 374 { 375 int error; 376 377 /* Set CONFIG mode */ 378 error = ravb_config(ndev); 379 if (error) 380 return error; 381 382 error = ravb_ring_init(ndev, RAVB_BE); 383 if (error) 384 return error; 385 error = ravb_ring_init(ndev, RAVB_NC); 386 if (error) { 387 ravb_ring_free(ndev, RAVB_BE); 388 return error; 389 } 390 391 /* Descriptor format */ 392 ravb_ring_format(ndev, RAVB_BE); 393 ravb_ring_format(ndev, RAVB_NC); 394 395 #if defined(__LITTLE_ENDIAN) 396 ravb_write(ndev, ravb_read(ndev, CCC) & ~CCC_BOC, CCC); 397 #else 398 ravb_write(ndev, ravb_read(ndev, CCC) | CCC_BOC, CCC); 399 #endif 400 401 /* Set AVB RX */ 402 ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR); 403 404 /* Set FIFO size */ 405 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 406 407 /* Timestamp enable */ 408 ravb_write(ndev, TCCR_TFEN, TCCR); 409 410 /* Interrupt init: */ 411 /* Frame receive */ 412 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 413 /* Disable FIFO full warning */ 414 ravb_write(ndev, 0, RIC1); 415 /* Receive FIFO full error, descriptor empty */ 416 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 417 /* Frame transmitted, timestamp FIFO updated */ 418 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 419 420 /* Setting the control will start the AVB-DMAC process. */ 421 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | CCC_OPC_OPERATION, 422 CCC); 423 424 return 0; 425 } 426 427 /* Free TX skb function for AVB-IP */ 428 static int ravb_tx_free(struct net_device *ndev, int q) 429 { 430 struct ravb_private *priv = netdev_priv(ndev); 431 struct net_device_stats *stats = &priv->stats[q]; 432 struct ravb_tx_desc *desc; 433 int free_num = 0; 434 int entry; 435 u32 size; 436 437 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 438 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 439 NUM_TX_DESC); 440 desc = &priv->tx_ring[q][entry]; 441 if (desc->die_dt != DT_FEMPTY) 442 break; 443 /* Descriptor type must be checked before all other reads */ 444 dma_rmb(); 445 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 446 /* Free the original skb. */ 447 if (priv->tx_skb[q][entry / NUM_TX_DESC]) { 448 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 449 size, DMA_TO_DEVICE); 450 /* Last packet descriptor? */ 451 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { 452 entry /= NUM_TX_DESC; 453 dev_kfree_skb_any(priv->tx_skb[q][entry]); 454 priv->tx_skb[q][entry] = NULL; 455 stats->tx_packets++; 456 } 457 free_num++; 458 } 459 stats->tx_bytes += size; 460 desc->die_dt = DT_EEMPTY; 461 } 462 return free_num; 463 } 464 465 static void ravb_get_tx_tstamp(struct net_device *ndev) 466 { 467 struct ravb_private *priv = netdev_priv(ndev); 468 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 469 struct skb_shared_hwtstamps shhwtstamps; 470 struct sk_buff *skb; 471 struct timespec64 ts; 472 u16 tag, tfa_tag; 473 int count; 474 u32 tfa2; 475 476 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 477 while (count--) { 478 tfa2 = ravb_read(ndev, TFA2); 479 tfa_tag = (tfa2 & TFA2_TST) >> 16; 480 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 481 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 482 ravb_read(ndev, TFA1); 483 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 484 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 485 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 486 list) { 487 skb = ts_skb->skb; 488 tag = ts_skb->tag; 489 list_del(&ts_skb->list); 490 kfree(ts_skb); 491 if (tag == tfa_tag) { 492 skb_tstamp_tx(skb, &shhwtstamps); 493 break; 494 } 495 } 496 ravb_write(ndev, ravb_read(ndev, TCCR) | TCCR_TFR, TCCR); 497 } 498 } 499 500 /* Packet receive function for Ethernet AVB */ 501 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 502 { 503 struct ravb_private *priv = netdev_priv(ndev); 504 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 505 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 506 priv->cur_rx[q]; 507 struct net_device_stats *stats = &priv->stats[q]; 508 struct ravb_ex_rx_desc *desc; 509 struct sk_buff *skb; 510 dma_addr_t dma_addr; 511 struct timespec64 ts; 512 u8 desc_status; 513 u16 pkt_len; 514 int limit; 515 516 boguscnt = min(boguscnt, *quota); 517 limit = boguscnt; 518 desc = &priv->rx_ring[q][entry]; 519 while (desc->die_dt != DT_FEMPTY) { 520 /* Descriptor type must be checked before all other reads */ 521 dma_rmb(); 522 desc_status = desc->msc; 523 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 524 525 if (--boguscnt < 0) 526 break; 527 528 /* We use 0-byte descriptors to mark the DMA mapping errors */ 529 if (!pkt_len) 530 continue; 531 532 if (desc_status & MSC_MC) 533 stats->multicast++; 534 535 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 536 MSC_CEEF)) { 537 stats->rx_errors++; 538 if (desc_status & MSC_CRC) 539 stats->rx_crc_errors++; 540 if (desc_status & MSC_RFE) 541 stats->rx_frame_errors++; 542 if (desc_status & (MSC_RTLF | MSC_RTSF)) 543 stats->rx_length_errors++; 544 if (desc_status & MSC_CEEF) 545 stats->rx_missed_errors++; 546 } else { 547 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 548 549 skb = priv->rx_skb[q][entry]; 550 priv->rx_skb[q][entry] = NULL; 551 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 552 ALIGN(PKT_BUF_SZ, 16), 553 DMA_FROM_DEVICE); 554 get_ts &= (q == RAVB_NC) ? 555 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 556 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 557 if (get_ts) { 558 struct skb_shared_hwtstamps *shhwtstamps; 559 560 shhwtstamps = skb_hwtstamps(skb); 561 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 562 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 563 32) | le32_to_cpu(desc->ts_sl); 564 ts.tv_nsec = le32_to_cpu(desc->ts_n); 565 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 566 } 567 skb_put(skb, pkt_len); 568 skb->protocol = eth_type_trans(skb, ndev); 569 napi_gro_receive(&priv->napi[q], skb); 570 stats->rx_packets++; 571 stats->rx_bytes += pkt_len; 572 } 573 574 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 575 desc = &priv->rx_ring[q][entry]; 576 } 577 578 /* Refill the RX ring buffers. */ 579 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 580 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 581 desc = &priv->rx_ring[q][entry]; 582 /* The size of the buffer should be on 16-byte boundary. */ 583 desc->ds_cc = cpu_to_le16(ALIGN(PKT_BUF_SZ, 16)); 584 585 if (!priv->rx_skb[q][entry]) { 586 skb = netdev_alloc_skb(ndev, 587 PKT_BUF_SZ + RAVB_ALIGN - 1); 588 if (!skb) 589 break; /* Better luck next round. */ 590 ravb_set_buffer_align(skb); 591 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 592 le16_to_cpu(desc->ds_cc), 593 DMA_FROM_DEVICE); 594 skb_checksum_none_assert(skb); 595 /* We just set the data size to 0 for a failed mapping 596 * which should prevent DMA from happening... 597 */ 598 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 599 desc->ds_cc = cpu_to_le16(0); 600 desc->dptr = cpu_to_le32(dma_addr); 601 priv->rx_skb[q][entry] = skb; 602 } 603 /* Descriptor type must be set after all the above writes */ 604 dma_wmb(); 605 desc->die_dt = DT_FEMPTY; 606 } 607 608 *quota -= limit - (++boguscnt); 609 610 return boguscnt <= 0; 611 } 612 613 static void ravb_rcv_snd_disable(struct net_device *ndev) 614 { 615 /* Disable TX and RX */ 616 ravb_write(ndev, ravb_read(ndev, ECMR) & ~(ECMR_RE | ECMR_TE), ECMR); 617 } 618 619 static void ravb_rcv_snd_enable(struct net_device *ndev) 620 { 621 /* Enable TX and RX */ 622 ravb_write(ndev, ravb_read(ndev, ECMR) | ECMR_RE | ECMR_TE, ECMR); 623 } 624 625 /* function for waiting dma process finished */ 626 static int ravb_stop_dma(struct net_device *ndev) 627 { 628 int error; 629 630 /* Wait for stopping the hardware TX process */ 631 error = ravb_wait(ndev, TCCR, 632 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 633 if (error) 634 return error; 635 636 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 637 0); 638 if (error) 639 return error; 640 641 /* Stop the E-MAC's RX/TX processes. */ 642 ravb_rcv_snd_disable(ndev); 643 644 /* Wait for stopping the RX DMA process */ 645 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 646 if (error) 647 return error; 648 649 /* Stop AVB-DMAC process */ 650 return ravb_config(ndev); 651 } 652 653 /* E-MAC interrupt handler */ 654 static void ravb_emac_interrupt(struct net_device *ndev) 655 { 656 struct ravb_private *priv = netdev_priv(ndev); 657 u32 ecsr, psr; 658 659 ecsr = ravb_read(ndev, ECSR); 660 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 661 if (ecsr & ECSR_ICD) 662 ndev->stats.tx_carrier_errors++; 663 if (ecsr & ECSR_LCHNG) { 664 /* Link changed */ 665 if (priv->no_avb_link) 666 return; 667 psr = ravb_read(ndev, PSR); 668 if (priv->avb_link_active_low) 669 psr ^= PSR_LMON; 670 if (!(psr & PSR_LMON)) { 671 /* DIsable RX and TX */ 672 ravb_rcv_snd_disable(ndev); 673 } else { 674 /* Enable RX and TX */ 675 ravb_rcv_snd_enable(ndev); 676 } 677 } 678 } 679 680 /* Error interrupt handler */ 681 static void ravb_error_interrupt(struct net_device *ndev) 682 { 683 struct ravb_private *priv = netdev_priv(ndev); 684 u32 eis, ris2; 685 686 eis = ravb_read(ndev, EIS); 687 ravb_write(ndev, ~EIS_QFS, EIS); 688 if (eis & EIS_QFS) { 689 ris2 = ravb_read(ndev, RIS2); 690 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); 691 692 /* Receive Descriptor Empty int */ 693 if (ris2 & RIS2_QFF0) 694 priv->stats[RAVB_BE].rx_over_errors++; 695 696 /* Receive Descriptor Empty int */ 697 if (ris2 & RIS2_QFF1) 698 priv->stats[RAVB_NC].rx_over_errors++; 699 700 /* Receive FIFO Overflow int */ 701 if (ris2 & RIS2_RFFF) 702 priv->rx_fifo_errors++; 703 } 704 } 705 706 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 707 { 708 struct net_device *ndev = dev_id; 709 struct ravb_private *priv = netdev_priv(ndev); 710 irqreturn_t result = IRQ_NONE; 711 u32 iss; 712 713 spin_lock(&priv->lock); 714 /* Get interrupt status */ 715 iss = ravb_read(ndev, ISS); 716 717 /* Received and transmitted interrupts */ 718 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 719 u32 ris0 = ravb_read(ndev, RIS0); 720 u32 ric0 = ravb_read(ndev, RIC0); 721 u32 tis = ravb_read(ndev, TIS); 722 u32 tic = ravb_read(ndev, TIC); 723 int q; 724 725 /* Timestamp updated */ 726 if (tis & TIS_TFUF) { 727 ravb_write(ndev, ~TIS_TFUF, TIS); 728 ravb_get_tx_tstamp(ndev); 729 result = IRQ_HANDLED; 730 } 731 732 /* Network control and best effort queue RX/TX */ 733 for (q = RAVB_NC; q >= RAVB_BE; q--) { 734 if (((ris0 & ric0) & BIT(q)) || 735 ((tis & tic) & BIT(q))) { 736 if (napi_schedule_prep(&priv->napi[q])) { 737 /* Mask RX and TX interrupts */ 738 ric0 &= ~BIT(q); 739 tic &= ~BIT(q); 740 ravb_write(ndev, ric0, RIC0); 741 ravb_write(ndev, tic, TIC); 742 __napi_schedule(&priv->napi[q]); 743 } else { 744 netdev_warn(ndev, 745 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 746 ris0, ric0); 747 netdev_warn(ndev, 748 " tx status 0x%08x, tx mask 0x%08x.\n", 749 tis, tic); 750 } 751 result = IRQ_HANDLED; 752 } 753 } 754 } 755 756 /* E-MAC status summary */ 757 if (iss & ISS_MS) { 758 ravb_emac_interrupt(ndev); 759 result = IRQ_HANDLED; 760 } 761 762 /* Error status summary */ 763 if (iss & ISS_ES) { 764 ravb_error_interrupt(ndev); 765 result = IRQ_HANDLED; 766 } 767 768 if (iss & ISS_CGIS) 769 result = ravb_ptp_interrupt(ndev); 770 771 mmiowb(); 772 spin_unlock(&priv->lock); 773 return result; 774 } 775 776 static int ravb_poll(struct napi_struct *napi, int budget) 777 { 778 struct net_device *ndev = napi->dev; 779 struct ravb_private *priv = netdev_priv(ndev); 780 unsigned long flags; 781 int q = napi - priv->napi; 782 int mask = BIT(q); 783 int quota = budget; 784 u32 ris0, tis; 785 786 for (;;) { 787 tis = ravb_read(ndev, TIS); 788 ris0 = ravb_read(ndev, RIS0); 789 if (!((ris0 & mask) || (tis & mask))) 790 break; 791 792 /* Processing RX Descriptor Ring */ 793 if (ris0 & mask) { 794 /* Clear RX interrupt */ 795 ravb_write(ndev, ~mask, RIS0); 796 if (ravb_rx(ndev, "a, q)) 797 goto out; 798 } 799 /* Processing TX Descriptor Ring */ 800 if (tis & mask) { 801 spin_lock_irqsave(&priv->lock, flags); 802 /* Clear TX interrupt */ 803 ravb_write(ndev, ~mask, TIS); 804 ravb_tx_free(ndev, q); 805 netif_wake_subqueue(ndev, q); 806 mmiowb(); 807 spin_unlock_irqrestore(&priv->lock, flags); 808 } 809 } 810 811 napi_complete(napi); 812 813 /* Re-enable RX/TX interrupts */ 814 spin_lock_irqsave(&priv->lock, flags); 815 ravb_write(ndev, ravb_read(ndev, RIC0) | mask, RIC0); 816 ravb_write(ndev, ravb_read(ndev, TIC) | mask, TIC); 817 mmiowb(); 818 spin_unlock_irqrestore(&priv->lock, flags); 819 820 /* Receive error message handling */ 821 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 822 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 823 if (priv->rx_over_errors != ndev->stats.rx_over_errors) { 824 ndev->stats.rx_over_errors = priv->rx_over_errors; 825 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n"); 826 } 827 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) { 828 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 829 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n"); 830 } 831 out: 832 return budget - quota; 833 } 834 835 /* PHY state control function */ 836 static void ravb_adjust_link(struct net_device *ndev) 837 { 838 struct ravb_private *priv = netdev_priv(ndev); 839 struct phy_device *phydev = priv->phydev; 840 bool new_state = false; 841 842 if (phydev->link) { 843 if (phydev->duplex != priv->duplex) { 844 new_state = true; 845 priv->duplex = phydev->duplex; 846 ravb_set_duplex(ndev); 847 } 848 849 if (phydev->speed != priv->speed) { 850 new_state = true; 851 priv->speed = phydev->speed; 852 ravb_set_rate(ndev); 853 } 854 if (!priv->link) { 855 ravb_write(ndev, ravb_read(ndev, ECMR) & ~ECMR_TXF, 856 ECMR); 857 new_state = true; 858 priv->link = phydev->link; 859 if (priv->no_avb_link) 860 ravb_rcv_snd_enable(ndev); 861 } 862 } else if (priv->link) { 863 new_state = true; 864 priv->link = 0; 865 priv->speed = 0; 866 priv->duplex = -1; 867 if (priv->no_avb_link) 868 ravb_rcv_snd_disable(ndev); 869 } 870 871 if (new_state && netif_msg_link(priv)) 872 phy_print_status(phydev); 873 } 874 875 /* PHY init function */ 876 static int ravb_phy_init(struct net_device *ndev) 877 { 878 struct device_node *np = ndev->dev.parent->of_node; 879 struct ravb_private *priv = netdev_priv(ndev); 880 struct phy_device *phydev; 881 struct device_node *pn; 882 int err; 883 884 priv->link = 0; 885 priv->speed = 0; 886 priv->duplex = -1; 887 888 /* Try connecting to PHY */ 889 pn = of_parse_phandle(np, "phy-handle", 0); 890 if (!pn) { 891 /* In the case of a fixed PHY, the DT node associated 892 * to the PHY is the Ethernet MAC DT node. 893 */ 894 if (of_phy_is_fixed_link(np)) { 895 err = of_phy_register_fixed_link(np); 896 if (err) 897 return err; 898 } 899 pn = of_node_get(np); 900 } 901 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 902 priv->phy_interface); 903 if (!phydev) { 904 netdev_err(ndev, "failed to connect PHY\n"); 905 return -ENOENT; 906 } 907 908 /* This driver only support 10/100Mbit speeds on Gen3 909 * at this time. 910 */ 911 if (priv->chip_id == RCAR_GEN3) { 912 int err; 913 914 err = phy_set_max_speed(phydev, SPEED_100); 915 if (err) { 916 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 917 phy_disconnect(phydev); 918 return err; 919 } 920 921 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 922 } 923 924 /* 10BASE is not supported */ 925 phydev->supported &= ~PHY_10BT_FEATURES; 926 927 phy_attached_info(phydev); 928 929 priv->phydev = phydev; 930 931 return 0; 932 } 933 934 /* PHY control start function */ 935 static int ravb_phy_start(struct net_device *ndev) 936 { 937 struct ravb_private *priv = netdev_priv(ndev); 938 int error; 939 940 error = ravb_phy_init(ndev); 941 if (error) 942 return error; 943 944 phy_start(priv->phydev); 945 946 return 0; 947 } 948 949 static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 950 { 951 struct ravb_private *priv = netdev_priv(ndev); 952 int error = -ENODEV; 953 unsigned long flags; 954 955 if (priv->phydev) { 956 spin_lock_irqsave(&priv->lock, flags); 957 error = phy_ethtool_gset(priv->phydev, ecmd); 958 spin_unlock_irqrestore(&priv->lock, flags); 959 } 960 961 return error; 962 } 963 964 static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 965 { 966 struct ravb_private *priv = netdev_priv(ndev); 967 unsigned long flags; 968 int error; 969 970 if (!priv->phydev) 971 return -ENODEV; 972 973 spin_lock_irqsave(&priv->lock, flags); 974 975 /* Disable TX and RX */ 976 ravb_rcv_snd_disable(ndev); 977 978 error = phy_ethtool_sset(priv->phydev, ecmd); 979 if (error) 980 goto error_exit; 981 982 if (ecmd->duplex == DUPLEX_FULL) 983 priv->duplex = 1; 984 else 985 priv->duplex = 0; 986 987 ravb_set_duplex(ndev); 988 989 error_exit: 990 mdelay(1); 991 992 /* Enable TX and RX */ 993 ravb_rcv_snd_enable(ndev); 994 995 mmiowb(); 996 spin_unlock_irqrestore(&priv->lock, flags); 997 998 return error; 999 } 1000 1001 static int ravb_nway_reset(struct net_device *ndev) 1002 { 1003 struct ravb_private *priv = netdev_priv(ndev); 1004 int error = -ENODEV; 1005 unsigned long flags; 1006 1007 if (priv->phydev) { 1008 spin_lock_irqsave(&priv->lock, flags); 1009 error = phy_start_aneg(priv->phydev); 1010 spin_unlock_irqrestore(&priv->lock, flags); 1011 } 1012 1013 return error; 1014 } 1015 1016 static u32 ravb_get_msglevel(struct net_device *ndev) 1017 { 1018 struct ravb_private *priv = netdev_priv(ndev); 1019 1020 return priv->msg_enable; 1021 } 1022 1023 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1024 { 1025 struct ravb_private *priv = netdev_priv(ndev); 1026 1027 priv->msg_enable = value; 1028 } 1029 1030 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1031 "rx_queue_0_current", 1032 "tx_queue_0_current", 1033 "rx_queue_0_dirty", 1034 "tx_queue_0_dirty", 1035 "rx_queue_0_packets", 1036 "tx_queue_0_packets", 1037 "rx_queue_0_bytes", 1038 "tx_queue_0_bytes", 1039 "rx_queue_0_mcast_packets", 1040 "rx_queue_0_errors", 1041 "rx_queue_0_crc_errors", 1042 "rx_queue_0_frame_errors", 1043 "rx_queue_0_length_errors", 1044 "rx_queue_0_missed_errors", 1045 "rx_queue_0_over_errors", 1046 1047 "rx_queue_1_current", 1048 "tx_queue_1_current", 1049 "rx_queue_1_dirty", 1050 "tx_queue_1_dirty", 1051 "rx_queue_1_packets", 1052 "tx_queue_1_packets", 1053 "rx_queue_1_bytes", 1054 "tx_queue_1_bytes", 1055 "rx_queue_1_mcast_packets", 1056 "rx_queue_1_errors", 1057 "rx_queue_1_crc_errors", 1058 "rx_queue_1_frame_errors", 1059 "rx_queue_1_length_errors", 1060 "rx_queue_1_missed_errors", 1061 "rx_queue_1_over_errors", 1062 }; 1063 1064 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1065 1066 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1067 { 1068 switch (sset) { 1069 case ETH_SS_STATS: 1070 return RAVB_STATS_LEN; 1071 default: 1072 return -EOPNOTSUPP; 1073 } 1074 } 1075 1076 static void ravb_get_ethtool_stats(struct net_device *ndev, 1077 struct ethtool_stats *stats, u64 *data) 1078 { 1079 struct ravb_private *priv = netdev_priv(ndev); 1080 int i = 0; 1081 int q; 1082 1083 /* Device-specific stats */ 1084 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1085 struct net_device_stats *stats = &priv->stats[q]; 1086 1087 data[i++] = priv->cur_rx[q]; 1088 data[i++] = priv->cur_tx[q]; 1089 data[i++] = priv->dirty_rx[q]; 1090 data[i++] = priv->dirty_tx[q]; 1091 data[i++] = stats->rx_packets; 1092 data[i++] = stats->tx_packets; 1093 data[i++] = stats->rx_bytes; 1094 data[i++] = stats->tx_bytes; 1095 data[i++] = stats->multicast; 1096 data[i++] = stats->rx_errors; 1097 data[i++] = stats->rx_crc_errors; 1098 data[i++] = stats->rx_frame_errors; 1099 data[i++] = stats->rx_length_errors; 1100 data[i++] = stats->rx_missed_errors; 1101 data[i++] = stats->rx_over_errors; 1102 } 1103 } 1104 1105 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1106 { 1107 switch (stringset) { 1108 case ETH_SS_STATS: 1109 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1110 break; 1111 } 1112 } 1113 1114 static void ravb_get_ringparam(struct net_device *ndev, 1115 struct ethtool_ringparam *ring) 1116 { 1117 struct ravb_private *priv = netdev_priv(ndev); 1118 1119 ring->rx_max_pending = BE_RX_RING_MAX; 1120 ring->tx_max_pending = BE_TX_RING_MAX; 1121 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1122 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1123 } 1124 1125 static int ravb_set_ringparam(struct net_device *ndev, 1126 struct ethtool_ringparam *ring) 1127 { 1128 struct ravb_private *priv = netdev_priv(ndev); 1129 int error; 1130 1131 if (ring->tx_pending > BE_TX_RING_MAX || 1132 ring->rx_pending > BE_RX_RING_MAX || 1133 ring->tx_pending < BE_TX_RING_MIN || 1134 ring->rx_pending < BE_RX_RING_MIN) 1135 return -EINVAL; 1136 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1137 return -EINVAL; 1138 1139 if (netif_running(ndev)) { 1140 netif_device_detach(ndev); 1141 /* Stop PTP Clock driver */ 1142 ravb_ptp_stop(ndev); 1143 /* Wait for DMA stopping */ 1144 error = ravb_stop_dma(ndev); 1145 if (error) { 1146 netdev_err(ndev, 1147 "cannot set ringparam! Any AVB processes are still running?\n"); 1148 return error; 1149 } 1150 synchronize_irq(ndev->irq); 1151 1152 /* Free all the skb's in the RX queue and the DMA buffers. */ 1153 ravb_ring_free(ndev, RAVB_BE); 1154 ravb_ring_free(ndev, RAVB_NC); 1155 } 1156 1157 /* Set new parameters */ 1158 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1159 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1160 1161 if (netif_running(ndev)) { 1162 error = ravb_dmac_init(ndev); 1163 if (error) { 1164 netdev_err(ndev, 1165 "%s: ravb_dmac_init() failed, error %d\n", 1166 __func__, error); 1167 return error; 1168 } 1169 1170 ravb_emac_init(ndev); 1171 1172 /* Initialise PTP Clock driver */ 1173 ravb_ptp_init(ndev, priv->pdev); 1174 1175 netif_device_attach(ndev); 1176 } 1177 1178 return 0; 1179 } 1180 1181 static int ravb_get_ts_info(struct net_device *ndev, 1182 struct ethtool_ts_info *info) 1183 { 1184 struct ravb_private *priv = netdev_priv(ndev); 1185 1186 info->so_timestamping = 1187 SOF_TIMESTAMPING_TX_SOFTWARE | 1188 SOF_TIMESTAMPING_RX_SOFTWARE | 1189 SOF_TIMESTAMPING_SOFTWARE | 1190 SOF_TIMESTAMPING_TX_HARDWARE | 1191 SOF_TIMESTAMPING_RX_HARDWARE | 1192 SOF_TIMESTAMPING_RAW_HARDWARE; 1193 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1194 info->rx_filters = 1195 (1 << HWTSTAMP_FILTER_NONE) | 1196 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1197 (1 << HWTSTAMP_FILTER_ALL); 1198 info->phc_index = ptp_clock_index(priv->ptp.clock); 1199 1200 return 0; 1201 } 1202 1203 static const struct ethtool_ops ravb_ethtool_ops = { 1204 .get_settings = ravb_get_settings, 1205 .set_settings = ravb_set_settings, 1206 .nway_reset = ravb_nway_reset, 1207 .get_msglevel = ravb_get_msglevel, 1208 .set_msglevel = ravb_set_msglevel, 1209 .get_link = ethtool_op_get_link, 1210 .get_strings = ravb_get_strings, 1211 .get_ethtool_stats = ravb_get_ethtool_stats, 1212 .get_sset_count = ravb_get_sset_count, 1213 .get_ringparam = ravb_get_ringparam, 1214 .set_ringparam = ravb_set_ringparam, 1215 .get_ts_info = ravb_get_ts_info, 1216 }; 1217 1218 /* Network device open function for Ethernet AVB */ 1219 static int ravb_open(struct net_device *ndev) 1220 { 1221 struct ravb_private *priv = netdev_priv(ndev); 1222 int error; 1223 1224 napi_enable(&priv->napi[RAVB_BE]); 1225 napi_enable(&priv->napi[RAVB_NC]); 1226 1227 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, ndev->name, 1228 ndev); 1229 if (error) { 1230 netdev_err(ndev, "cannot request IRQ\n"); 1231 goto out_napi_off; 1232 } 1233 1234 if (priv->chip_id == RCAR_GEN3) { 1235 error = request_irq(priv->emac_irq, ravb_interrupt, 1236 IRQF_SHARED, ndev->name, ndev); 1237 if (error) { 1238 netdev_err(ndev, "cannot request IRQ\n"); 1239 goto out_free_irq; 1240 } 1241 } 1242 1243 /* Device init */ 1244 error = ravb_dmac_init(ndev); 1245 if (error) 1246 goto out_free_irq2; 1247 ravb_emac_init(ndev); 1248 1249 /* Initialise PTP Clock driver */ 1250 if (priv->chip_id == RCAR_GEN2) 1251 ravb_ptp_init(ndev, priv->pdev); 1252 1253 netif_tx_start_all_queues(ndev); 1254 1255 /* PHY control start */ 1256 error = ravb_phy_start(ndev); 1257 if (error) 1258 goto out_ptp_stop; 1259 1260 return 0; 1261 1262 out_ptp_stop: 1263 /* Stop PTP Clock driver */ 1264 if (priv->chip_id == RCAR_GEN2) 1265 ravb_ptp_stop(ndev); 1266 out_free_irq2: 1267 if (priv->chip_id == RCAR_GEN3) 1268 free_irq(priv->emac_irq, ndev); 1269 out_free_irq: 1270 free_irq(ndev->irq, ndev); 1271 out_napi_off: 1272 napi_disable(&priv->napi[RAVB_NC]); 1273 napi_disable(&priv->napi[RAVB_BE]); 1274 return error; 1275 } 1276 1277 /* Timeout function for Ethernet AVB */ 1278 static void ravb_tx_timeout(struct net_device *ndev) 1279 { 1280 struct ravb_private *priv = netdev_priv(ndev); 1281 1282 netif_err(priv, tx_err, ndev, 1283 "transmit timed out, status %08x, resetting...\n", 1284 ravb_read(ndev, ISS)); 1285 1286 /* tx_errors count up */ 1287 ndev->stats.tx_errors++; 1288 1289 schedule_work(&priv->work); 1290 } 1291 1292 static void ravb_tx_timeout_work(struct work_struct *work) 1293 { 1294 struct ravb_private *priv = container_of(work, struct ravb_private, 1295 work); 1296 struct net_device *ndev = priv->ndev; 1297 1298 netif_tx_stop_all_queues(ndev); 1299 1300 /* Stop PTP Clock driver */ 1301 ravb_ptp_stop(ndev); 1302 1303 /* Wait for DMA stopping */ 1304 ravb_stop_dma(ndev); 1305 1306 ravb_ring_free(ndev, RAVB_BE); 1307 ravb_ring_free(ndev, RAVB_NC); 1308 1309 /* Device init */ 1310 ravb_dmac_init(ndev); 1311 ravb_emac_init(ndev); 1312 1313 /* Initialise PTP Clock driver */ 1314 ravb_ptp_init(ndev, priv->pdev); 1315 1316 netif_tx_start_all_queues(ndev); 1317 } 1318 1319 /* Packet transmit function for Ethernet AVB */ 1320 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1321 { 1322 struct ravb_private *priv = netdev_priv(ndev); 1323 u16 q = skb_get_queue_mapping(skb); 1324 struct ravb_tstamp_skb *ts_skb; 1325 struct ravb_tx_desc *desc; 1326 unsigned long flags; 1327 u32 dma_addr; 1328 void *buffer; 1329 u32 entry; 1330 u32 len; 1331 1332 spin_lock_irqsave(&priv->lock, flags); 1333 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1334 NUM_TX_DESC) { 1335 netif_err(priv, tx_queued, ndev, 1336 "still transmitting with the full ring!\n"); 1337 netif_stop_subqueue(ndev, q); 1338 spin_unlock_irqrestore(&priv->lock, flags); 1339 return NETDEV_TX_BUSY; 1340 } 1341 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); 1342 priv->tx_skb[q][entry / NUM_TX_DESC] = skb; 1343 1344 if (skb_put_padto(skb, ETH_ZLEN)) 1345 goto drop; 1346 1347 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1348 entry / NUM_TX_DESC * DPTR_ALIGN; 1349 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1350 memcpy(buffer, skb->data, len); 1351 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1352 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1353 goto drop; 1354 1355 desc = &priv->tx_ring[q][entry]; 1356 desc->ds_tagl = cpu_to_le16(len); 1357 desc->dptr = cpu_to_le32(dma_addr); 1358 1359 buffer = skb->data + len; 1360 len = skb->len - len; 1361 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1362 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1363 goto unmap; 1364 1365 desc++; 1366 desc->ds_tagl = cpu_to_le16(len); 1367 desc->dptr = cpu_to_le32(dma_addr); 1368 1369 /* TX timestamp required */ 1370 if (q == RAVB_NC) { 1371 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1372 if (!ts_skb) { 1373 desc--; 1374 dma_unmap_single(ndev->dev.parent, dma_addr, len, 1375 DMA_TO_DEVICE); 1376 goto unmap; 1377 } 1378 ts_skb->skb = skb; 1379 ts_skb->tag = priv->ts_skb_tag++; 1380 priv->ts_skb_tag &= 0x3ff; 1381 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1382 1383 /* TAG and timestamp required flag */ 1384 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1385 skb_tx_timestamp(skb); 1386 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1387 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12); 1388 } 1389 1390 /* Descriptor type must be set after all the above writes */ 1391 dma_wmb(); 1392 desc->die_dt = DT_FEND; 1393 desc--; 1394 desc->die_dt = DT_FSTART; 1395 1396 ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR); 1397 1398 priv->cur_tx[q] += NUM_TX_DESC; 1399 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1400 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q)) 1401 netif_stop_subqueue(ndev, q); 1402 1403 exit: 1404 mmiowb(); 1405 spin_unlock_irqrestore(&priv->lock, flags); 1406 return NETDEV_TX_OK; 1407 1408 unmap: 1409 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1410 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1411 drop: 1412 dev_kfree_skb_any(skb); 1413 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; 1414 goto exit; 1415 } 1416 1417 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1418 void *accel_priv, select_queue_fallback_t fallback) 1419 { 1420 /* If skb needs TX timestamp, it is handled in network control queue */ 1421 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1422 RAVB_BE; 1423 1424 } 1425 1426 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1427 { 1428 struct ravb_private *priv = netdev_priv(ndev); 1429 struct net_device_stats *nstats, *stats0, *stats1; 1430 1431 nstats = &ndev->stats; 1432 stats0 = &priv->stats[RAVB_BE]; 1433 stats1 = &priv->stats[RAVB_NC]; 1434 1435 nstats->tx_dropped += ravb_read(ndev, TROCR); 1436 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1437 nstats->collisions += ravb_read(ndev, CDCR); 1438 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1439 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1440 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1441 1442 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1443 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1444 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1445 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1446 1447 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1448 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1449 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1450 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1451 nstats->multicast = stats0->multicast + stats1->multicast; 1452 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1453 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1454 nstats->rx_frame_errors = 1455 stats0->rx_frame_errors + stats1->rx_frame_errors; 1456 nstats->rx_length_errors = 1457 stats0->rx_length_errors + stats1->rx_length_errors; 1458 nstats->rx_missed_errors = 1459 stats0->rx_missed_errors + stats1->rx_missed_errors; 1460 nstats->rx_over_errors = 1461 stats0->rx_over_errors + stats1->rx_over_errors; 1462 1463 return nstats; 1464 } 1465 1466 /* Update promiscuous bit */ 1467 static void ravb_set_rx_mode(struct net_device *ndev) 1468 { 1469 struct ravb_private *priv = netdev_priv(ndev); 1470 unsigned long flags; 1471 u32 ecmr; 1472 1473 spin_lock_irqsave(&priv->lock, flags); 1474 ecmr = ravb_read(ndev, ECMR); 1475 if (ndev->flags & IFF_PROMISC) 1476 ecmr |= ECMR_PRM; 1477 else 1478 ecmr &= ~ECMR_PRM; 1479 ravb_write(ndev, ecmr, ECMR); 1480 mmiowb(); 1481 spin_unlock_irqrestore(&priv->lock, flags); 1482 } 1483 1484 /* Device close function for Ethernet AVB */ 1485 static int ravb_close(struct net_device *ndev) 1486 { 1487 struct ravb_private *priv = netdev_priv(ndev); 1488 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1489 1490 netif_tx_stop_all_queues(ndev); 1491 1492 /* Disable interrupts by clearing the interrupt masks. */ 1493 ravb_write(ndev, 0, RIC0); 1494 ravb_write(ndev, 0, RIC2); 1495 ravb_write(ndev, 0, TIC); 1496 1497 /* Stop PTP Clock driver */ 1498 if (priv->chip_id == RCAR_GEN2) 1499 ravb_ptp_stop(ndev); 1500 1501 /* Set the config mode to stop the AVB-DMAC's processes */ 1502 if (ravb_stop_dma(ndev) < 0) 1503 netdev_err(ndev, 1504 "device will be stopped after h/w processes are done.\n"); 1505 1506 /* Clear the timestamp list */ 1507 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1508 list_del(&ts_skb->list); 1509 kfree(ts_skb); 1510 } 1511 1512 /* PHY disconnect */ 1513 if (priv->phydev) { 1514 phy_stop(priv->phydev); 1515 phy_disconnect(priv->phydev); 1516 priv->phydev = NULL; 1517 } 1518 1519 free_irq(ndev->irq, ndev); 1520 1521 napi_disable(&priv->napi[RAVB_NC]); 1522 napi_disable(&priv->napi[RAVB_BE]); 1523 1524 /* Free all the skb's in the RX queue and the DMA buffers. */ 1525 ravb_ring_free(ndev, RAVB_BE); 1526 ravb_ring_free(ndev, RAVB_NC); 1527 1528 return 0; 1529 } 1530 1531 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1532 { 1533 struct ravb_private *priv = netdev_priv(ndev); 1534 struct hwtstamp_config config; 1535 1536 config.flags = 0; 1537 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1538 HWTSTAMP_TX_OFF; 1539 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1540 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1541 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1542 config.rx_filter = HWTSTAMP_FILTER_ALL; 1543 else 1544 config.rx_filter = HWTSTAMP_FILTER_NONE; 1545 1546 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1547 -EFAULT : 0; 1548 } 1549 1550 /* Control hardware time stamping */ 1551 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1552 { 1553 struct ravb_private *priv = netdev_priv(ndev); 1554 struct hwtstamp_config config; 1555 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1556 u32 tstamp_tx_ctrl; 1557 1558 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1559 return -EFAULT; 1560 1561 /* Reserved for future extensions */ 1562 if (config.flags) 1563 return -EINVAL; 1564 1565 switch (config.tx_type) { 1566 case HWTSTAMP_TX_OFF: 1567 tstamp_tx_ctrl = 0; 1568 break; 1569 case HWTSTAMP_TX_ON: 1570 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1571 break; 1572 default: 1573 return -ERANGE; 1574 } 1575 1576 switch (config.rx_filter) { 1577 case HWTSTAMP_FILTER_NONE: 1578 tstamp_rx_ctrl = 0; 1579 break; 1580 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1581 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1582 break; 1583 default: 1584 config.rx_filter = HWTSTAMP_FILTER_ALL; 1585 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1586 } 1587 1588 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1589 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1590 1591 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1592 -EFAULT : 0; 1593 } 1594 1595 /* ioctl to device function */ 1596 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1597 { 1598 struct ravb_private *priv = netdev_priv(ndev); 1599 struct phy_device *phydev = priv->phydev; 1600 1601 if (!netif_running(ndev)) 1602 return -EINVAL; 1603 1604 if (!phydev) 1605 return -ENODEV; 1606 1607 switch (cmd) { 1608 case SIOCGHWTSTAMP: 1609 return ravb_hwtstamp_get(ndev, req); 1610 case SIOCSHWTSTAMP: 1611 return ravb_hwtstamp_set(ndev, req); 1612 } 1613 1614 return phy_mii_ioctl(phydev, req, cmd); 1615 } 1616 1617 static const struct net_device_ops ravb_netdev_ops = { 1618 .ndo_open = ravb_open, 1619 .ndo_stop = ravb_close, 1620 .ndo_start_xmit = ravb_start_xmit, 1621 .ndo_select_queue = ravb_select_queue, 1622 .ndo_get_stats = ravb_get_stats, 1623 .ndo_set_rx_mode = ravb_set_rx_mode, 1624 .ndo_tx_timeout = ravb_tx_timeout, 1625 .ndo_do_ioctl = ravb_do_ioctl, 1626 .ndo_validate_addr = eth_validate_addr, 1627 .ndo_set_mac_address = eth_mac_addr, 1628 .ndo_change_mtu = eth_change_mtu, 1629 }; 1630 1631 /* MDIO bus init function */ 1632 static int ravb_mdio_init(struct ravb_private *priv) 1633 { 1634 struct platform_device *pdev = priv->pdev; 1635 struct device *dev = &pdev->dev; 1636 int error; 1637 1638 /* Bitbang init */ 1639 priv->mdiobb.ops = &bb_ops; 1640 1641 /* MII controller setting */ 1642 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1643 if (!priv->mii_bus) 1644 return -ENOMEM; 1645 1646 /* Hook up MII support for ethtool */ 1647 priv->mii_bus->name = "ravb_mii"; 1648 priv->mii_bus->parent = dev; 1649 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1650 pdev->name, pdev->id); 1651 1652 /* Register MDIO bus */ 1653 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1654 if (error) 1655 goto out_free_bus; 1656 1657 return 0; 1658 1659 out_free_bus: 1660 free_mdio_bitbang(priv->mii_bus); 1661 return error; 1662 } 1663 1664 /* MDIO bus release function */ 1665 static int ravb_mdio_release(struct ravb_private *priv) 1666 { 1667 /* Unregister mdio bus */ 1668 mdiobus_unregister(priv->mii_bus); 1669 1670 /* Free bitbang info */ 1671 free_mdio_bitbang(priv->mii_bus); 1672 1673 return 0; 1674 } 1675 1676 static const struct of_device_id ravb_match_table[] = { 1677 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1678 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1679 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1680 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1681 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1682 { } 1683 }; 1684 MODULE_DEVICE_TABLE(of, ravb_match_table); 1685 1686 static int ravb_set_gti(struct net_device *ndev) 1687 { 1688 1689 struct device *dev = ndev->dev.parent; 1690 struct device_node *np = dev->of_node; 1691 unsigned long rate; 1692 struct clk *clk; 1693 uint64_t inc; 1694 1695 clk = of_clk_get(np, 0); 1696 if (IS_ERR(clk)) { 1697 dev_err(dev, "could not get clock\n"); 1698 return PTR_ERR(clk); 1699 } 1700 1701 rate = clk_get_rate(clk); 1702 clk_put(clk); 1703 1704 inc = 1000000000ULL << 20; 1705 do_div(inc, rate); 1706 1707 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1708 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1709 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1710 return -EINVAL; 1711 } 1712 1713 ravb_write(ndev, inc, GTI); 1714 1715 return 0; 1716 } 1717 1718 static int ravb_probe(struct platform_device *pdev) 1719 { 1720 struct device_node *np = pdev->dev.of_node; 1721 const struct of_device_id *match; 1722 struct ravb_private *priv; 1723 enum ravb_chip_id chip_id; 1724 struct net_device *ndev; 1725 int error, irq, q; 1726 struct resource *res; 1727 1728 if (!np) { 1729 dev_err(&pdev->dev, 1730 "this driver is required to be instantiated from device tree\n"); 1731 return -EINVAL; 1732 } 1733 1734 /* Get base address */ 1735 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1736 if (!res) { 1737 dev_err(&pdev->dev, "invalid resource\n"); 1738 return -EINVAL; 1739 } 1740 1741 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 1742 NUM_TX_QUEUE, NUM_RX_QUEUE); 1743 if (!ndev) 1744 return -ENOMEM; 1745 1746 pm_runtime_enable(&pdev->dev); 1747 pm_runtime_get_sync(&pdev->dev); 1748 1749 /* The Ether-specific entries in the device structure. */ 1750 ndev->base_addr = res->start; 1751 ndev->dma = -1; 1752 1753 match = of_match_device(of_match_ptr(ravb_match_table), &pdev->dev); 1754 chip_id = (enum ravb_chip_id)match->data; 1755 1756 if (chip_id == RCAR_GEN3) 1757 irq = platform_get_irq_byname(pdev, "ch22"); 1758 else 1759 irq = platform_get_irq(pdev, 0); 1760 if (irq < 0) { 1761 error = irq; 1762 goto out_release; 1763 } 1764 ndev->irq = irq; 1765 1766 SET_NETDEV_DEV(ndev, &pdev->dev); 1767 1768 priv = netdev_priv(ndev); 1769 priv->ndev = ndev; 1770 priv->pdev = pdev; 1771 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 1772 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 1773 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 1774 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 1775 priv->addr = devm_ioremap_resource(&pdev->dev, res); 1776 if (IS_ERR(priv->addr)) { 1777 error = PTR_ERR(priv->addr); 1778 goto out_release; 1779 } 1780 1781 spin_lock_init(&priv->lock); 1782 INIT_WORK(&priv->work, ravb_tx_timeout_work); 1783 1784 priv->phy_interface = of_get_phy_mode(np); 1785 1786 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 1787 priv->avb_link_active_low = 1788 of_property_read_bool(np, "renesas,ether-link-active-low"); 1789 1790 if (chip_id == RCAR_GEN3) { 1791 irq = platform_get_irq_byname(pdev, "ch24"); 1792 if (irq < 0) { 1793 error = irq; 1794 goto out_release; 1795 } 1796 priv->emac_irq = irq; 1797 } 1798 1799 priv->chip_id = chip_id; 1800 1801 /* Set function */ 1802 ndev->netdev_ops = &ravb_netdev_ops; 1803 ndev->ethtool_ops = &ravb_ethtool_ops; 1804 1805 /* Set AVB config mode */ 1806 if (chip_id == RCAR_GEN2) { 1807 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | 1808 CCC_OPC_CONFIG, CCC); 1809 /* Set CSEL value */ 1810 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | 1811 CCC_CSEL_HPB, CCC); 1812 } else { 1813 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_OPC) | 1814 CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB, CCC); 1815 } 1816 1817 /* Set CSEL value */ 1818 ravb_write(ndev, (ravb_read(ndev, CCC) & ~CCC_CSEL) | CCC_CSEL_HPB, 1819 CCC); 1820 1821 /* Set GTI value */ 1822 error = ravb_set_gti(ndev); 1823 if (error) 1824 goto out_release; 1825 1826 /* Request GTI loading */ 1827 ravb_write(ndev, ravb_read(ndev, GCCR) | GCCR_LTI, GCCR); 1828 1829 /* Allocate descriptor base address table */ 1830 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 1831 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 1832 &priv->desc_bat_dma, GFP_KERNEL); 1833 if (!priv->desc_bat) { 1834 dev_err(&pdev->dev, 1835 "Cannot allocate desc base address table (size %d bytes)\n", 1836 priv->desc_bat_size); 1837 error = -ENOMEM; 1838 goto out_release; 1839 } 1840 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 1841 priv->desc_bat[q].die_dt = DT_EOS; 1842 ravb_write(ndev, priv->desc_bat_dma, DBAT); 1843 1844 /* Initialise HW timestamp list */ 1845 INIT_LIST_HEAD(&priv->ts_skb_list); 1846 1847 /* Initialise PTP Clock driver */ 1848 if (chip_id != RCAR_GEN2) 1849 ravb_ptp_init(ndev, pdev); 1850 1851 /* Debug message level */ 1852 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 1853 1854 /* Read and set MAC address */ 1855 ravb_read_mac_address(ndev, of_get_mac_address(np)); 1856 if (!is_valid_ether_addr(ndev->dev_addr)) { 1857 dev_warn(&pdev->dev, 1858 "no valid MAC address supplied, using a random one\n"); 1859 eth_hw_addr_random(ndev); 1860 } 1861 1862 /* MDIO bus init */ 1863 error = ravb_mdio_init(priv); 1864 if (error) { 1865 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 1866 goto out_dma_free; 1867 } 1868 1869 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 1870 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 1871 1872 /* Network device register */ 1873 error = register_netdev(ndev); 1874 if (error) 1875 goto out_napi_del; 1876 1877 /* Print device information */ 1878 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 1879 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 1880 1881 platform_set_drvdata(pdev, ndev); 1882 1883 return 0; 1884 1885 out_napi_del: 1886 netif_napi_del(&priv->napi[RAVB_NC]); 1887 netif_napi_del(&priv->napi[RAVB_BE]); 1888 ravb_mdio_release(priv); 1889 out_dma_free: 1890 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 1891 priv->desc_bat_dma); 1892 1893 /* Stop PTP Clock driver */ 1894 if (chip_id != RCAR_GEN2) 1895 ravb_ptp_stop(ndev); 1896 out_release: 1897 if (ndev) 1898 free_netdev(ndev); 1899 1900 pm_runtime_put(&pdev->dev); 1901 pm_runtime_disable(&pdev->dev); 1902 return error; 1903 } 1904 1905 static int ravb_remove(struct platform_device *pdev) 1906 { 1907 struct net_device *ndev = platform_get_drvdata(pdev); 1908 struct ravb_private *priv = netdev_priv(ndev); 1909 1910 /* Stop PTP Clock driver */ 1911 if (priv->chip_id != RCAR_GEN2) 1912 ravb_ptp_stop(ndev); 1913 1914 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 1915 priv->desc_bat_dma); 1916 /* Set reset mode */ 1917 ravb_write(ndev, CCC_OPC_RESET, CCC); 1918 pm_runtime_put_sync(&pdev->dev); 1919 unregister_netdev(ndev); 1920 netif_napi_del(&priv->napi[RAVB_NC]); 1921 netif_napi_del(&priv->napi[RAVB_BE]); 1922 ravb_mdio_release(priv); 1923 pm_runtime_disable(&pdev->dev); 1924 free_netdev(ndev); 1925 platform_set_drvdata(pdev, NULL); 1926 1927 return 0; 1928 } 1929 1930 #ifdef CONFIG_PM 1931 static int ravb_runtime_nop(struct device *dev) 1932 { 1933 /* Runtime PM callback shared between ->runtime_suspend() 1934 * and ->runtime_resume(). Simply returns success. 1935 * 1936 * This driver re-initializes all registers after 1937 * pm_runtime_get_sync() anyway so there is no need 1938 * to save and restore registers here. 1939 */ 1940 return 0; 1941 } 1942 1943 static const struct dev_pm_ops ravb_dev_pm_ops = { 1944 .runtime_suspend = ravb_runtime_nop, 1945 .runtime_resume = ravb_runtime_nop, 1946 }; 1947 1948 #define RAVB_PM_OPS (&ravb_dev_pm_ops) 1949 #else 1950 #define RAVB_PM_OPS NULL 1951 #endif 1952 1953 static struct platform_driver ravb_driver = { 1954 .probe = ravb_probe, 1955 .remove = ravb_remove, 1956 .driver = { 1957 .name = "ravb", 1958 .pm = RAVB_PM_OPS, 1959 .of_match_table = ravb_match_table, 1960 }, 1961 }; 1962 1963 module_platform_driver(ravb_driver); 1964 1965 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 1966 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 1967 MODULE_LICENSE("GPL v2"); 1968